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finish test of dl814_k7_cal_coarse

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archive dl814_k7_cal_coarse_20230419 and dl814_k7_null_verify_20230420, the function of lcmv nulling algorithm and the data exchange between boards are verified by pre-generated data
This commit is contained in:
josh
2023-04-20 11:39:02 +08:00
parent 3c2cd0ba29
commit 14a5d6e48a
1365 changed files with 494026 additions and 186114 deletions
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projects/dl814_k7/dl814_k7_cal_coarse/project/project.runs/impl_1/debug_nets.ltx
+705 -62
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projects/dl814_k7/dl814_k7_cal_coarse/project/project.runs/impl_1/system_top.bit
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projects/dl814_k7/dl814_k7_cal_coarse/project/project.runs/impl_1/system_top.ltx
+705 -62
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projects/dl814_k7/dl814_k7_cal_coarse/project/project.sdk/dl814_k7_48m/src/dev_profile/ad9361_reg_profile.c
+526 -39
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@@ -97,10 +97,497 @@ uint32_t ad9361_reg_config(struct ad9361_reg_dev *dev){
status = ad9361_reg_write(dev, 0x0002, 0xA4); // Setup Tx Digital Filters/ Channels
status = ad9361_reg_write(dev, 0x0003, 0xE4); // Setup Rx Digital Filters/ Channels
status = ad9361_reg_write(dev, 0x0003, 0xE5); // Setup Rx Digital Filters/ Channels
status = ad9361_reg_write(dev, 0x0004, 0x03); // Select Rx input pin(A,B,C)/ Tx out pin (A,B)
status = ad9361_reg_write(dev, 0x000A, 0x12); // Set BBPLL post divide rate
//************************************************************
// Program Rx FIR: C:\Users\josh\Desktop\Config\rx64.txt
//************************************************************
status = ad9361_reg_write(dev, 0x00F5, 0x9A); // Enable clock to Rx FIR Filter
status = ad9361_reg_write(dev, 0x00F6, 0x02); // Write Filter Gain setting
status = ad9361_reg_write(dev, 0x00F0, 0x00); // Write FIR coefficient address
status = ad9361_reg_write(dev, 0x00F1, 0x00); // Write FIR coefficient data[7:0]
status = ad9361_reg_write(dev, 0x00F2, 0x00); // Write FIR coefficient data[15:8]
status = ad9361_reg_write(dev, 0x00F5, 0x9E); // Set Write EN to push data into FIR filter register map
status = ad9361_reg_write(dev, 0x00F4, 0x00); // Dummy Write to Read only register to delay ~1us
status = ad9361_reg_write(dev, 0x00F4, 0x00); // Dummy Write to Read only register to delay ~1us
status = ad9361_reg_write(dev, 0x00F0, 0x01);
status = ad9361_reg_write(dev, 0x00F1, 0xB6);
status = ad9361_reg_write(dev, 0x00F2, 0xFF);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x02);
status = ad9361_reg_write(dev, 0x00F1, 0xA5);
status = ad9361_reg_write(dev, 0x00F2, 0xFF);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x03);
status = ad9361_reg_write(dev, 0x00F1, 0xEA);
status = ad9361_reg_write(dev, 0x00F2, 0xFF);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x04);
status = ad9361_reg_write(dev, 0x00F1, 0x61);
status = ad9361_reg_write(dev, 0x00F2, 0x00);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x05);
status = ad9361_reg_write(dev, 0x00F1, 0xA3);
status = ad9361_reg_write(dev, 0x00F2, 0x00);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x06);
status = ad9361_reg_write(dev, 0x00F1, 0x4D);
status = ad9361_reg_write(dev, 0x00F2, 0x00);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x07);
status = ad9361_reg_write(dev, 0x00F1, 0x77);
status = ad9361_reg_write(dev, 0x00F2, 0xFF);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x08);
status = ad9361_reg_write(dev, 0x00F1, 0xD5);
status = ad9361_reg_write(dev, 0x00F2, 0xFE);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x09);
status = ad9361_reg_write(dev, 0x00F1, 0x38);
status = ad9361_reg_write(dev, 0x00F2, 0xFF);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x0A);
status = ad9361_reg_write(dev, 0x00F1, 0xA5);
status = ad9361_reg_write(dev, 0x00F2, 0x00);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x0B);
status = ad9361_reg_write(dev, 0x00F1, 0xF8);
status = ad9361_reg_write(dev, 0x00F2, 0x01);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x0C);
status = ad9361_reg_write(dev, 0x00F1, 0xAD);
status = ad9361_reg_write(dev, 0x00F2, 0x01);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x0D);
status = ad9361_reg_write(dev, 0x00F1, 0x75);
status = ad9361_reg_write(dev, 0x00F2, 0xFF);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x0E);
status = ad9361_reg_write(dev, 0x00F1, 0xFD);
status = ad9361_reg_write(dev, 0x00F2, 0xFC);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x0F);
status = ad9361_reg_write(dev, 0x00F1, 0xD8);
status = ad9361_reg_write(dev, 0x00F2, 0xFC);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x10);
status = ad9361_reg_write(dev, 0x00F1, 0x00);
status = ad9361_reg_write(dev, 0x00F2, 0x00);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x11);
status = ad9361_reg_write(dev, 0x00F1, 0x3A);
status = ad9361_reg_write(dev, 0x00F2, 0x04);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x12);
status = ad9361_reg_write(dev, 0x00F1, 0x6B);
status = ad9361_reg_write(dev, 0x00F2, 0x05);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x13);
status = ad9361_reg_write(dev, 0x00F1, 0x51);
status = ad9361_reg_write(dev, 0x00F2, 0x01);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x14);
status = ad9361_reg_write(dev, 0x00F1, 0x80);
status = ad9361_reg_write(dev, 0x00F2, 0xFA);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x15);
status = ad9361_reg_write(dev, 0x00F1, 0x34);
status = ad9361_reg_write(dev, 0x00F2, 0xF7);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x16);
status = ad9361_reg_write(dev, 0x00F1, 0x08);
status = ad9361_reg_write(dev, 0x00F2, 0xFC);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x17);
status = ad9361_reg_write(dev, 0x00F1, 0xB2);
status = ad9361_reg_write(dev, 0x00F2, 0x06);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x18);
status = ad9361_reg_write(dev, 0x00F1, 0x1A);
status = ad9361_reg_write(dev, 0x00F2, 0x0E);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x19);
status = ad9361_reg_write(dev, 0x00F1, 0x44);
status = ad9361_reg_write(dev, 0x00F2, 0x09);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x1A);
status = ad9361_reg_write(dev, 0x00F1, 0x54);
status = ad9361_reg_write(dev, 0x00F2, 0xF8);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x1B);
status = ad9361_reg_write(dev, 0x00F1, 0xD1);
status = ad9361_reg_write(dev, 0x00F2, 0xE7);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x1C);
status = ad9361_reg_write(dev, 0x00F1, 0xC2);
status = ad9361_reg_write(dev, 0x00F2, 0xE9);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x1D);
status = ad9361_reg_write(dev, 0x00F1, 0x4F);
status = ad9361_reg_write(dev, 0x00F2, 0x08);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x1E);
status = ad9361_reg_write(dev, 0x00F1, 0xB2);
status = ad9361_reg_write(dev, 0x00F2, 0x3B);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x1F);
status = ad9361_reg_write(dev, 0x00F1, 0x2A);
status = ad9361_reg_write(dev, 0x00F2, 0x6C);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x20);
status = ad9361_reg_write(dev, 0x00F1, 0xFF);
status = ad9361_reg_write(dev, 0x00F2, 0x7F);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x21);
status = ad9361_reg_write(dev, 0x00F1, 0x2A);
status = ad9361_reg_write(dev, 0x00F2, 0x6C);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x22);
status = ad9361_reg_write(dev, 0x00F1, 0xB2);
status = ad9361_reg_write(dev, 0x00F2, 0x3B);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x23);
status = ad9361_reg_write(dev, 0x00F1, 0x4F);
status = ad9361_reg_write(dev, 0x00F2, 0x08);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x24);
status = ad9361_reg_write(dev, 0x00F1, 0xC2);
status = ad9361_reg_write(dev, 0x00F2, 0xE9);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x25);
status = ad9361_reg_write(dev, 0x00F1, 0xD1);
status = ad9361_reg_write(dev, 0x00F2, 0xE7);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x26);
status = ad9361_reg_write(dev, 0x00F1, 0x54);
status = ad9361_reg_write(dev, 0x00F2, 0xF8);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x27);
status = ad9361_reg_write(dev, 0x00F1, 0x44);
status = ad9361_reg_write(dev, 0x00F2, 0x09);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x28);
status = ad9361_reg_write(dev, 0x00F1, 0x1A);
status = ad9361_reg_write(dev, 0x00F2, 0x0E);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x29);
status = ad9361_reg_write(dev, 0x00F1, 0xB2);
status = ad9361_reg_write(dev, 0x00F2, 0x06);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x2A);
status = ad9361_reg_write(dev, 0x00F1, 0x08);
status = ad9361_reg_write(dev, 0x00F2, 0xFC);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x2B);
status = ad9361_reg_write(dev, 0x00F1, 0x34);
status = ad9361_reg_write(dev, 0x00F2, 0xF7);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x2C);
status = ad9361_reg_write(dev, 0x00F1, 0x80);
status = ad9361_reg_write(dev, 0x00F2, 0xFA);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x2D);
status = ad9361_reg_write(dev, 0x00F1, 0x51);
status = ad9361_reg_write(dev, 0x00F2, 0x01);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x2E);
status = ad9361_reg_write(dev, 0x00F1, 0x6B);
status = ad9361_reg_write(dev, 0x00F2, 0x05);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x2F);
status = ad9361_reg_write(dev, 0x00F1, 0x3A);
status = ad9361_reg_write(dev, 0x00F2, 0x04);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x30);
status = ad9361_reg_write(dev, 0x00F1, 0x00);
status = ad9361_reg_write(dev, 0x00F2, 0x00);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x31);
status = ad9361_reg_write(dev, 0x00F1, 0xD8);
status = ad9361_reg_write(dev, 0x00F2, 0xFC);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x32);
status = ad9361_reg_write(dev, 0x00F1, 0xFD);
status = ad9361_reg_write(dev, 0x00F2, 0xFC);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x33);
status = ad9361_reg_write(dev, 0x00F1, 0x75);
status = ad9361_reg_write(dev, 0x00F2, 0xFF);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x34);
status = ad9361_reg_write(dev, 0x00F1, 0xAD);
status = ad9361_reg_write(dev, 0x00F2, 0x01);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x35);
status = ad9361_reg_write(dev, 0x00F1, 0xF8);
status = ad9361_reg_write(dev, 0x00F2, 0x01);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x36);
status = ad9361_reg_write(dev, 0x00F1, 0xA5);
status = ad9361_reg_write(dev, 0x00F2, 0x00);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x37);
status = ad9361_reg_write(dev, 0x00F1, 0x38);
status = ad9361_reg_write(dev, 0x00F2, 0xFF);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x38);
status = ad9361_reg_write(dev, 0x00F1, 0xD5);
status = ad9361_reg_write(dev, 0x00F2, 0xFE);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x39);
status = ad9361_reg_write(dev, 0x00F1, 0x77);
status = ad9361_reg_write(dev, 0x00F2, 0xFF);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x3A);
status = ad9361_reg_write(dev, 0x00F1, 0x4D);
status = ad9361_reg_write(dev, 0x00F2, 0x00);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x3B);
status = ad9361_reg_write(dev, 0x00F1, 0xA3);
status = ad9361_reg_write(dev, 0x00F2, 0x00);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x3C);
status = ad9361_reg_write(dev, 0x00F1, 0x61);
status = ad9361_reg_write(dev, 0x00F2, 0x00);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x3D);
status = ad9361_reg_write(dev, 0x00F1, 0xEA);
status = ad9361_reg_write(dev, 0x00F2, 0xFF);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x3E);
status = ad9361_reg_write(dev, 0x00F1, 0xA5);
status = ad9361_reg_write(dev, 0x00F2, 0xFF);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x3F);
status = ad9361_reg_write(dev, 0x00F1, 0xB6);
status = ad9361_reg_write(dev, 0x00F2, 0xFF);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x40);
status = ad9361_reg_write(dev, 0x00F1, 0x00);
status = ad9361_reg_write(dev, 0x00F2, 0x00);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x41);
status = ad9361_reg_write(dev, 0x00F1, 0x00);
status = ad9361_reg_write(dev, 0x00F2, 0x00);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x42);
status = ad9361_reg_write(dev, 0x00F1, 0x00);
status = ad9361_reg_write(dev, 0x00F2, 0x00);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x43);
status = ad9361_reg_write(dev, 0x00F1, 0x00);
status = ad9361_reg_write(dev, 0x00F2, 0x00);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x44);
status = ad9361_reg_write(dev, 0x00F1, 0x00);
status = ad9361_reg_write(dev, 0x00F2, 0x00);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x45);
status = ad9361_reg_write(dev, 0x00F1, 0x00);
status = ad9361_reg_write(dev, 0x00F2, 0x00);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x46);
status = ad9361_reg_write(dev, 0x00F1, 0x00);
status = ad9361_reg_write(dev, 0x00F2, 0x00);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x47);
status = ad9361_reg_write(dev, 0x00F1, 0x00);
status = ad9361_reg_write(dev, 0x00F2, 0x00);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x48);
status = ad9361_reg_write(dev, 0x00F1, 0x00);
status = ad9361_reg_write(dev, 0x00F2, 0x00);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x49);
status = ad9361_reg_write(dev, 0x00F1, 0x00);
status = ad9361_reg_write(dev, 0x00F2, 0x00);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x4A);
status = ad9361_reg_write(dev, 0x00F1, 0x00);
status = ad9361_reg_write(dev, 0x00F2, 0x00);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x4B);
status = ad9361_reg_write(dev, 0x00F1, 0x00);
status = ad9361_reg_write(dev, 0x00F2, 0x00);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x4C);
status = ad9361_reg_write(dev, 0x00F1, 0x00);
status = ad9361_reg_write(dev, 0x00F2, 0x00);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x4D);
status = ad9361_reg_write(dev, 0x00F1, 0x00);
status = ad9361_reg_write(dev, 0x00F2, 0x00);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x4E);
status = ad9361_reg_write(dev, 0x00F1, 0x00);
status = ad9361_reg_write(dev, 0x00F2, 0x00);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F0, 0x4F);
status = ad9361_reg_write(dev, 0x00F1, 0x00);
status = ad9361_reg_write(dev, 0x00F2, 0x00);
status = ad9361_reg_write(dev, 0x00F5, 0x9E);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F4, 0x00);
status = ad9361_reg_write(dev, 0x00F5, 0x98); // Disable clock to Rx Filter
//************************************************************
// Setup the Parallel Port (Digital Data Interface)
//************************************************************
@@ -108,7 +595,7 @@ uint32_t ad9361_reg_config(struct ad9361_reg_dev *dev){
status = ad9361_reg_write(dev, 0x0011, 0x00); // I/O Config. Alt Word Order; -Rx1; -Rx2; -Tx1; -Tx2; Invert Rx Frame; Delay Rx Data
status = ad9361_reg_write(dev, 0x0012, 0x02); // I/O Config. Rx=2*Tx; Swap Ports; SDR; LVDS; Half Duplex; Single Port; Full Port; Swap Bits
status = ad9361_reg_write(dev, 0x0006, 0x00); // PPORT Rx Delay (adjusts Tco Dataclk->Data)
status = ad9361_reg_write(dev, 0x0007, 0x08); // PPORT TX Delay (adjusts setup/hold FBCLK->Data)
status = ad9361_reg_write(dev, 0x0007, 0x0F); // PPORT TX Delay (adjusts setup/hold FBCLK->Data)
//************************************************************
// Setup AuxDAC
@@ -1039,12 +1526,12 @@ uint32_t ad9361_reg_config(struct ad9361_reg_dev *dev){
status = ad9361_reg_write(dev, 0x011A, 0x27); // Initial LMT Gain Limit
status = ad9361_reg_write(dev, 0x0081, 0x00); // Tx Symbol Gain Control
//************************************************************
// RX Baseband Filter Tuning (Real BW: 20.000000 MHz) 3dB Filter
// Corner @ 28.000000 MHz)
// RX Baseband Filter Tuning (Real BW: 7.500000 MHz) 3dB Filter
// Corner @ 10.500000 MHz)
//************************************************************
status = ad9361_reg_write(dev, 0x01FB, 0x14); // RX Freq Corner (MHz)
status = ad9361_reg_write(dev, 0x01FC, 0x00); // RX Freq Corner (Khz)
status = ad9361_reg_write(dev, 0x01F8, 0x05); // Rx BBF Tune Divider[7:0]
status = ad9361_reg_write(dev, 0x01FB, 0x07); // RX Freq Corner (MHz)
status = ad9361_reg_write(dev, 0x01FC, 0x40); // RX Freq Corner (Khz)
status = ad9361_reg_write(dev, 0x01F8, 0x0D); // Rx BBF Tune Divider[7:0]
status = ad9361_reg_write(dev, 0x01F9, 0x1E); // RX BBF Tune Divider[8]
status = ad9361_reg_write(dev, 0x01D5, 0x3F); // Set Rx Mix LO CM
@@ -1053,7 +1540,7 @@ uint32_t ad9361_reg_config(struct ad9361_reg_dev *dev){
status = ad9361_reg_write(dev, 0x01E3, 0x02); // Enable Rx2 Filter Tuner
status = ad9361_reg_write(dev, 0x0016, 0x80); // Start RX Filter Tune
// Wait for RX filter to tune, Max Cal Time: 2.648 us (Done when 0x016[7]==0)
// Wait for RX filter to tune, Max Cal Time: 6.884 us (Done when 0x016[7]==0)
time_out_cnt = 0;
do{
status |= ad9361_reg_read(dev, 0x0016, &value);
@@ -1064,16 +1551,16 @@ uint32_t ad9361_reg_config(struct ad9361_reg_dev *dev){
status = ad9361_reg_write(dev, 0x01E2, 0x03); // Disable Rx Filter Tuner (Rx1)
status = ad9361_reg_write(dev, 0x01E3, 0x03); // Disable Rx Filter Tuner (Rx2)
//************************************************************
// TX Baseband Filter Tuning (Real BW: 20.000000 MHz) 3dB Filter
// Corner @ 32.000000 MHz)
// TX Baseband Filter Tuning (Real BW: 7.500000 MHz) 3dB Filter
// Corner @ 12.000000 MHz)
//************************************************************
status = ad9361_reg_write(dev, 0x00D6, 0x04); // TX BBF Tune Divider[7:0]
status = ad9361_reg_write(dev, 0x00D6, 0x0B); // TX BBF Tune Divider[7:0]
status = ad9361_reg_write(dev, 0x00D7, 0x1E); // TX BBF Tune Divider[8]
status = ad9361_reg_write(dev, 0x00CA, 0x22); // Enable Tx Filter Tuner
status = ad9361_reg_write(dev, 0x0016, 0x40); // Start Tx Filter Tune
// Wait for TX filter to tune, Max Cal Time: 1.233 us (Done when 0x016[6]==0)
// Wait for TX filter to tune, Max Cal Time: 3.390 us (Done when 0x016[6]==0)
time_out_cnt = 0;
do{
status |= ad9361_reg_read(dev, 0x0016, &value);
@@ -1086,23 +1573,23 @@ uint32_t ad9361_reg_config(struct ad9361_reg_dev *dev){
// RX TIA Setup: Setup values scale based on RxBBF calibration
// results. See information in Calibration Guide.
//************************************************************
status = ad9361_reg_write(dev, 0x01DB, 0x20); // Set TIA selcc[2:0]
status = ad9361_reg_write(dev, 0x01DB, 0x60); // Set TIA selcc[2:0]
status = ad9361_reg_write(dev, 0x01DD, 0x00); // Set RX TIA1 C MSB[6:0]
status = ad9361_reg_write(dev, 0x01DF, 0x00); // Set RX TIA2 C MSB[6:0]
status = ad9361_reg_write(dev, 0x01DC, 0x47); // Set RX TIA1 C LSB[5:0]
status = ad9361_reg_write(dev, 0x01DE, 0x47); // Set RX TIA2 C LSB[5:0]
status = ad9361_reg_write(dev, 0x01DC, 0x72); // Set RX TIA1 C LSB[5:0]
status = ad9361_reg_write(dev, 0x01DE, 0x72); // Set RX TIA2 C LSB[5:0]
//************************************************************
// TX Secondary Filter Calibration Setup: Real Bandwidth
// 20.000000MHz, 3dB Corner @ 100.000000MHz
// 7.500000MHz, 3dB Corner @ 37.500000MHz
//************************************************************
status = ad9361_reg_write(dev, 0x00D2, 0x04); // TX Secondary Filter PDF Cap cal[5:0]
status = ad9361_reg_write(dev, 0x00D2, 0x1E); // TX Secondary Filter PDF Cap cal[5:0]
status = ad9361_reg_write(dev, 0x00D1, 0x0C); // TX Secondary Filter PDF Res cal[3:0]
status = ad9361_reg_write(dev, 0x00D0, 0x57); // Pdampbias
status = ad9361_reg_write(dev, 0x00D0, 0x56); // Pdampbias
//************************************************************
// ADC Setup: Tune ADC Performance based on RX analog filter tune
// corner. Real Bandwidth: 18.155158 MHz, ADC Clock Frequency:
// corner. Real Bandwidth: 6.982753 MHz, ADC Clock Frequency:
// 288.000000 MHz. The values in registers 0x200 - 0x227 need to be
// calculated using the equations in the Calibration Guide.
//************************************************************
@@ -1114,23 +1601,23 @@ uint32_t ad9361_reg_config(struct ad9361_reg_dev *dev){
status = ad9361_reg_write(dev, 0x0204, 0x24);
status = ad9361_reg_write(dev, 0x0205, 0x00);
status = ad9361_reg_write(dev, 0x0206, 0x00);
status = ad9361_reg_write(dev, 0x0207, 0x67);
status = ad9361_reg_write(dev, 0x0208, 0x55);
status = ad9361_reg_write(dev, 0x0209, 0x31);
status = ad9361_reg_write(dev, 0x020A, 0x3E);
status = ad9361_reg_write(dev, 0x020B, 0x35);
status = ad9361_reg_write(dev, 0x020C, 0x41);
status = ad9361_reg_write(dev, 0x020D, 0x34);
status = ad9361_reg_write(dev, 0x0207, 0x7C);
status = ad9361_reg_write(dev, 0x0208, 0x46);
status = ad9361_reg_write(dev, 0x0209, 0x3C);
status = ad9361_reg_write(dev, 0x020A, 0x4C);
status = ad9361_reg_write(dev, 0x020B, 0x2C);
status = ad9361_reg_write(dev, 0x020C, 0x4F);
status = ad9361_reg_write(dev, 0x020D, 0x2A);
status = ad9361_reg_write(dev, 0x020E, 0x00);
status = ad9361_reg_write(dev, 0x020F, 0x6A);
status = ad9361_reg_write(dev, 0x0210, 0x6A);
status = ad9361_reg_write(dev, 0x0211, 0x6A);
status = ad9361_reg_write(dev, 0x0212, 0x3C);
status = ad9361_reg_write(dev, 0x0213, 0x3C);
status = ad9361_reg_write(dev, 0x0214, 0x3C);
status = ad9361_reg_write(dev, 0x0215, 0x3F);
status = ad9361_reg_write(dev, 0x0216, 0x3F);
status = ad9361_reg_write(dev, 0x0217, 0x3F);
status = ad9361_reg_write(dev, 0x020F, 0x7F);
status = ad9361_reg_write(dev, 0x0210, 0x7F);
status = ad9361_reg_write(dev, 0x0211, 0x7F);
status = ad9361_reg_write(dev, 0x0212, 0x4A);
status = ad9361_reg_write(dev, 0x0213, 0x4A);
status = ad9361_reg_write(dev, 0x0214, 0x4A);
status = ad9361_reg_write(dev, 0x0215, 0x4D);
status = ad9361_reg_write(dev, 0x0216, 0x4D);
status = ad9361_reg_write(dev, 0x0217, 0x4D);
status = ad9361_reg_write(dev, 0x0218, 0x2E);
status = ad9361_reg_write(dev, 0x0219, 0x9C);
status = ad9361_reg_write(dev, 0x021A, 0x1F);
@@ -1182,8 +1669,8 @@ uint32_t ad9361_reg_config(struct ad9361_reg_dev *dev){
//************************************************************
// Tx Quadrature Calibration Settings
//************************************************************
status = ad9361_reg_write(dev, 0x00A0, 0x5F); // Set TxQuadcal NCO frequency
status = ad9361_reg_write(dev, 0x00A3, 0x80); // Set TxQuadcal NCO frequency (Only update bits [7:6])
status = ad9361_reg_write(dev, 0x00A0, 0x15); // Set TxQuadcal NCO frequency
status = ad9361_reg_write(dev, 0x00A3, 0x00); // Set TxQuadcal NCO frequency (Only update bits [7:6])
status = ad9361_reg_write(dev, 0x00A1, 0x7B); // Tx Quad Cal Configuration, Phase and Gain Cal Enable
status = ad9361_reg_write(dev, 0x00A9, 0xFF); // Set Tx Quad Cal Count
status = ad9361_reg_write(dev, 0x00A2, 0x7F); // Set Tx Quad Cal Kexp
@@ -1236,8 +1723,8 @@ uint32_t ad9361_reg_config(struct ad9361_reg_dev *dev){
//************************************************************
// Enable External LO & External VCO Buffer
//************************************************************
status |= ad9361_reg_write(dev, 0x0005, 0x07);
status |= ad9361_reg_write(dev, 0x0057, 0x1C);
status |= ad9361_reg_write(dev, 0x0005, 0x07);
status |= ad9361_reg_write(dev, 0x0057, 0x1C);
return status;
}
projects/dl814_k7/dl814_k7_cal_coarse/project/project.sdk/dl814_k7_48m/src/main.c
+3 -1
View File
@@ -183,7 +183,8 @@ int main(void)
/********* AD9361 Multichip Rx Phase Calibration **********/
/**********************************************************/
// switch to lower frequency
Status = Hardware_SwitchFreq(ad9361_1_reg_inst, TX_FREQ_125);
Status = Hardware_SwitchFreq(ad9361_1_reg_inst, TX_FREQ_126);
XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9361_TX_SW, 1);
mdelay(20);
// switch rx channel
@@ -247,6 +248,7 @@ int main(void)
// switch to higher frequency
Status = Hardware_SwitchFreq(ad9361_1_reg_inst, TX_FREQ_4125);
XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9361_TX_SW, 0);
print("Done.\n");
projects/dl814_k7/dl814_k7_cal_coarse/project/project.sdk/dl814_k7_48m/src/parameters.h
+1
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@@ -84,6 +84,7 @@
#define AD9361_1_CAL_START 21
#define AD9361_2_CAL_START 22
#define AD9361_RECAL 23
#define AD9361_TX_SW 24
#define AD9361_1_CTRL_OUT_0 0
#define AD9361_1_CTRL_OUT_1 1
projects/dl814_k7/dl814_k7_cal_coarse/project/project.sdk/system_top.hdf
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