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finish test of dl814_k7_cal_coarse

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archive dl814_k7_cal_coarse_20230419 and dl814_k7_null_verify_20230420, the function of lcmv nulling algorithm and the data exchange between boards are verified by pre-generated data
This commit is contained in:
josh
2023-04-20 11:39:02 +08:00
parent 3c2cd0ba29
commit 14a5d6e48a
1365 changed files with 494026 additions and 186114 deletions
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projects/dl814_k7/dl814_k7_cal_coarse/rtl/rx_pre_process/accor_mat_formatting.v
+163 -174
View File
@@ -43,26 +43,27 @@
module accor_mat_formatting
#(
parameter ROW_NUM = 4,
parameter COL_NUM = 4,
parameter DATA_I_WIDTH = 32,
parameter FRAME_HEAD = 32'h7E7E7E7E
parameter ROW_NUM = 4,
parameter COL_NUM = 4,
parameter DATA_I_WIDTH = 32,
parameter FRAME_HEAD = 32'h7E7E7E7E
)
(
// clock & reset
input sys_clk,
input sys_rst,
input clk_96m,
input ant_rst,
// clock & reset
input sys_clk,
input sys_rst,
input clk_96m,
input ant_rst,
// input data
input din_valid,
input [ROW_NUM*COL_NUM*DATA_I_WIDTH-1 : 0] din_real,
input [ROW_NUM*COL_NUM*DATA_I_WIDTH-1 : 0] din_imag,
// input data
input din_valid,
input [ROW_NUM*COL_NUM*DATA_I_WIDTH-1 : 0] din_real,
input [ROW_NUM*COL_NUM*DATA_I_WIDTH-1 : 0] din_imag,
input fifo_cdc_rst,
// output data
output dout_valid,
output dout_data
// output data
output dout_valid,
output dout_data
);
localparam CMPLX_DIM = 2;
@@ -85,159 +86,147 @@ reg [DATA_I_WIDTH-1 : 0] din_array_cdc [0 : ROW_NUM*COL_NUM*CMPLX_DIM-1];
generate
for (i = 0; i < ROW_NUM*COL_NUM; i = i + 1) begin: input_mat_reshape
assign din_array[i*2] = din_real[i*DATA_I_WIDTH +: DATA_I_WIDTH];
assign din_array[i*2+1] = din_imag[i*DATA_I_WIDTH +: DATA_I_WIDTH];
assign din_array[i*2] = din_real[i*DATA_I_WIDTH +: DATA_I_WIDTH];
assign din_array[i*2+1] = din_imag[i*DATA_I_WIDTH +: DATA_I_WIDTH];
end
endgenerate
// input clock domain crossing buffer
// clock domain crossing fifo, write channel
reg fifo_wr_start = 'b0;
reg fifo_wr_en = 'b0;
reg fifo_wr_en_d1 = 'b0; // buffer input data for 1 clock cycle
reg [$clog2(ROW_NUM*COL_NUM*CMPLX_DIM)-1 : 0] fifo_wr_cnt = 'b0;
reg [DATA_I_WIDTH-1 : 0] fifo_din = 'b0;
always @(posedge sys_clk) begin
if (sys_rst) begin
fifo_wr_en <= 'b0;
end
else if (din_valid) begin
fifo_wr_en <= 1'b1;
end
else if (fifo_wr_cnt == ROW_NUM*COL_NUM*CMPLX_DIM-1) begin
fifo_wr_en <= 1'b0;
end
else begin
fifo_wr_en <= fifo_wr_en;
end
if (sys_rst) begin
fifo_wr_start <= 'b0;
end
else if (din_valid) begin
fifo_wr_start <= 1'b1;
end
else if (fifo_wr_cnt == ROW_NUM*COL_NUM*CMPLX_DIM-1) begin
fifo_wr_start <= 1'b0;
end
else begin
fifo_wr_start <= fifo_wr_start;
end
end
always @(posedge sys_clk) begin
if (sys_rst) begin
fifo_wr_en_d1 <= 'b0;
end
else begin
fifo_wr_en_d1 <= fifo_wr_en;
end
end
always @(posedge sys_clk) begin
if (sys_rst) begin
fifo_wr_cnt <= 'b0;
end
else if (fifo_wr_en) begin
fifo_wr_cnt <= fifo_wr_cnt + 1'b1;
end
else begin
fifo_wr_cnt <= 'b0;
end
end
always @(posedge sys_clk) begin
if (sys_rst) begin
fifo_din <= 'b0;
end
else if (fifo_wr_en) begin
fifo_din <= din_array[fifo_wr_cnt];
end
else begin
fifo_din <= 'b0;
end
if (sys_rst) begin
fifo_wr_en <= 'b0;
fifo_wr_cnt <= 'b0;
fifo_din <= 'b0;
end
else if (fifo_wr_start) begin
fifo_wr_en <= 1'b1;
fifo_wr_cnt <= fifo_wr_cnt + 1'b1;
fifo_din <= din_array[fifo_wr_cnt];
end
else begin
fifo_wr_en <= 'b0;
fifo_wr_cnt <= 'b0;
fifo_din <= 'b0;
end
end
// clock domain crossing fifo, read channel
reg fifo_rd_en = 'b0;
reg fifo_rd_en_d1 = 'b0; // read data latency
reg fifo_rd_en_d1 = 'b0;
reg [$clog2(ROW_NUM*COL_NUM*CMPLX_DIM)-1 : 0] fifo_rd_cnt = 'b0;
reg [$clog2(ROW_NUM*COL_NUM*CMPLX_DIM)-1 : 0] fifo_rd_cnt_d1 = 'b0; // read data latency
reg fifo_rd_valid = 'b0;
wire [DATA_I_WIDTH-1 : 0] fifo_dout;
wire [$clog2(ROW_NUM*COL_NUM*CMPLX_DIM)-1 : 0] fifo_rd_num;
wire [$clog2(ROW_NUM*COL_NUM*CMPLX_DIM*2)-1 : 0] fifo_rd_num;
wire fifo_full;
wire fifo_empty;
always @(posedge clk_96m) begin
if (ant_rst) begin
fifo_rd_en <= 'b0;
end
else if (fifo_rd_num == ROW_NUM*COL_NUM) begin
fifo_rd_en <= 1'b1;
end
else if (fifo_rd_cnt == ROW_NUM*COL_NUM*CMPLX_DIM-1) begin
fifo_rd_en <= 'b0;
end
else begin
fifo_rd_en <= fifo_rd_en;
end
if (ant_rst) begin
fifo_rd_en <= 'b0;
end
else if (fifo_rd_num == ROW_NUM*COL_NUM*CMPLX_DIM-1) begin
fifo_rd_en <= 1'b1;
end
else if (fifo_rd_cnt == ROW_NUM*COL_NUM*CMPLX_DIM-1) begin
fifo_rd_en <= 'b0;
end
else begin
fifo_rd_en <= fifo_rd_en;
end
end
always @(posedge clk_96m) begin
if (ant_rst) begin
fifo_rd_en_d1 <= 'b0;
end
else begin
fifo_rd_en_d1 <= fifo_rd_en;
end
if (ant_rst) begin
fifo_rd_en_d1 <= 'b0;
end
else begin
fifo_rd_en_d1 <= fifo_rd_en;
end
end
always @(posedge clk_96m) begin
if (ant_rst) begin
fifo_rd_cnt <= 'b0;
end
else if (fifo_rd_en) begin
fifo_rd_cnt <= fifo_rd_cnt + 1'b1;
end
else begin
fifo_rd_cnt <= 'b0;
end
if (ant_rst) begin
fifo_rd_cnt <= 'b0;
end
else if (fifo_rd_en) begin
fifo_rd_cnt <= fifo_rd_cnt + 1'b1;
end
else begin
fifo_rd_cnt <= 'b0;
end
end
always @(posedge clk_96m) begin
if (ant_rst) begin
fifo_rd_cnt_d1 <= 'b0;
end
else begin
fifo_rd_cnt_d1 <= fifo_rd_cnt;
end
if (ant_rst) begin
fifo_rd_cnt_d1 <= 'b0;
end
else begin
fifo_rd_cnt_d1 <= fifo_rd_cnt;
end
end
always @(posedge clk_96m) begin
if (ant_rst) begin
fifo_rd_valid <= 'b0;
end
else if (fifo_rd_cnt_d1 == ROW_NUM*COL_NUM*CMPLX_DIM-1) begin
fifo_rd_valid <= 1'b1;
end
else begin
fifo_rd_valid <= 'b0;
end
if (ant_rst) begin
fifo_rd_valid <= 'b0;
end
else if (fifo_rd_cnt_d1 == ROW_NUM*COL_NUM*CMPLX_DIM-1) begin
fifo_rd_valid <= 1'b1;
end
else begin
fifo_rd_valid <= 'b0;
end
end
always @(posedge clk_96m) begin
if (ant_rst) begin
for (m = 0; m < ROW_NUM*COL_NUM*CMPLX_DIM; m = m + 1) begin
din_array_cdc[m] <= 'b0;
end
end
else if (fifo_rd_en_d1) begin
din_array_cdc[fifo_rd_cnt_d1] <= fifo_dout;
end
else begin
for (m = 0; m < ROW_NUM*COL_NUM*CMPLX_DIM; m = m + 1) begin
din_array_cdc[m] <= din_array_cdc[m];
end
end
if (ant_rst) begin
for (m = 0; m < ROW_NUM*COL_NUM*CMPLX_DIM; m = m + 1) begin
din_array_cdc[m] <= 'b0;
end
end
else if (fifo_rd_en_d1) begin
din_array_cdc[fifo_rd_cnt_d1] <= fifo_dout;
end
else begin
for (m = 0; m < ROW_NUM*COL_NUM*CMPLX_DIM; m = m + 1) begin
din_array_cdc[m] <= din_array_cdc[m];
end
end
end
// clock domain crossing fifo, interface
fifo_accor_cdc u_fifo_accor_cdc
(
.wr_clk (sys_clk ), // input wire wr_clk
.wr_rst (sys_rst ), // input wire wr_rst
.rd_clk (clk_96m ), // input wire rd_clk
.rd_rst (ant_rst ), // input wire rd_rst
.din (fifo_din ), // input wire [31 : 0] din
.wr_en (fifo_wr_en_d1 ), // input wire wr_en
.rd_en (fifo_rd_en ), // input wire rd_en
.dout (fifo_dout ), // output wire [31 : 0] dout
.full ( ), // output wire full
.empty ( ), // output wire empty
.rd_data_count (fifo_rd_num ) // output wire [4 : 0] rd_data_count
.rst (fifo_cdc_rst ), // input wire wr_rst
.wr_clk (sys_clk ), // input wire wr_clk
.rd_clk (clk_96m ), // input wire rd_clk
.din (fifo_din ), // input wire [31 : 0] din
.wr_en (fifo_wr_en ), // input wire wr_en
.rd_en (fifo_rd_en ), // input wire rd_en
.dout (fifo_dout ), // output wire [31 : 0] dout
.full (fifo_full ), // output wire full
.empty (fifo_empty ), // output wire empty
.rd_data_count (fifo_rd_num ) // output wire [5 : 0] rd_data_count
);
// center state machine & counter
@@ -246,45 +235,45 @@ reg [$clog2(DATA_I_WIDTH)-1 : 0] bit_cnt = 'b0; // bit counter within one frame
reg [$clog2(FRAME_LEN)-1 : 0] frame_cnt = 'b0; // frame counter
always @(posedge clk_96m) begin
if (ant_rst) begin
state <= STATE_IDLE;
end
else begin
case (state)
STATE_IDLE: state <= fifo_rd_valid ? STATE_HEAD : STATE_IDLE;
STATE_HEAD: state <= (bit_cnt == DATA_I_WIDTH-1) ? STATE_LEN : STATE_HEAD;
STATE_LEN : state <= (bit_cnt == DATA_I_WIDTH-1) ? STATE_DATA : STATE_LEN;
STATE_DATA: state <= (frame_cnt == FRAME_LEN-1 && bit_cnt == DATA_I_WIDTH-1) ? STATE_IDLE : STATE_DATA;
default: state <= STATE_IDLE;
endcase
end
if (ant_rst) begin
state <= STATE_IDLE;
end
else begin
case (state)
STATE_IDLE: state <= fifo_rd_valid ? STATE_HEAD : STATE_IDLE;
STATE_HEAD: state <= (bit_cnt == DATA_I_WIDTH-1) ? STATE_LEN : STATE_HEAD;
STATE_LEN : state <= (bit_cnt == DATA_I_WIDTH-1) ? STATE_DATA : STATE_LEN;
STATE_DATA: state <= (frame_cnt == FRAME_LEN-1 && bit_cnt == DATA_I_WIDTH-1) ? STATE_IDLE : STATE_DATA;
default: state <= STATE_IDLE;
endcase
end
end
always @(posedge clk_96m) begin
if (ant_rst) begin
bit_cnt <= 'b0;
end
else if (state == STATE_IDLE) begin
bit_cnt <= 'b0;
end
else begin
bit_cnt <= (bit_cnt == DATA_I_WIDTH-1) ? 'b0 : bit_cnt + 1'b1;
end
if (ant_rst) begin
bit_cnt <= 'b0;
end
else if (state == STATE_IDLE) begin
bit_cnt <= 'b0;
end
else begin
bit_cnt <= (bit_cnt == DATA_I_WIDTH-1) ? 'b0 : bit_cnt + 1'b1;
end
end
always @(posedge clk_96m) begin
if (ant_rst) begin
frame_cnt <= 'b0;
end
else if (state == STATE_IDLE) begin
frame_cnt <= 'b0;
end
else if (state == STATE_DATA && bit_cnt == DATA_I_WIDTH-1) begin
frame_cnt <= frame_cnt + 1'b1;
end
else begin
frame_cnt <= frame_cnt;
end
if (ant_rst) begin
frame_cnt <= 'b0;
end
else if (state == STATE_IDLE) begin
frame_cnt <= 'b0;
end
else if (state == STATE_DATA && bit_cnt == DATA_I_WIDTH-1) begin
frame_cnt <= frame_cnt + 1'b1;
end
else begin
frame_cnt <= frame_cnt;
end
end
@@ -296,17 +285,17 @@ assign dout_valid = dout_valid_buf;
assign dout_data = dout_data_buf;
always @(posedge clk_96m) begin
if (ant_rst) begin
dout_valid_buf <= 'b0;
dout_data_buf <= 'b0;
end
else case (state)
STATE_IDLE: begin dout_valid_buf <= 'b0 ; dout_data_buf <= 'b0; end
STATE_HEAD: begin dout_valid_buf <= 1'b1; dout_data_buf <= FRAME_HEAD[DATA_I_WIDTH-1 - bit_cnt]; end
STATE_LEN : begin dout_valid_buf <= 1'b1; dout_data_buf <= BYTE_LEN[DATA_I_WIDTH-1 - bit_cnt]; end
STATE_DATA: begin dout_valid_buf <= 1'b1; dout_data_buf <= din_array_cdc[frame_cnt][DATA_I_WIDTH-1 - bit_cnt]; end
default: begin dout_valid_buf <= 'b0 ; dout_data_buf <= 'b0; end
endcase
if (ant_rst) begin
dout_valid_buf <= 'b0;
dout_data_buf <= 'b0;
end
else case (state)
STATE_IDLE: begin dout_valid_buf <= 'b0 ; dout_data_buf <= 'b0; end
STATE_HEAD: begin dout_valid_buf <= 1'b1; dout_data_buf <= FRAME_HEAD[DATA_I_WIDTH-1 - bit_cnt]; end
STATE_LEN : begin dout_valid_buf <= 1'b1; dout_data_buf <= BYTE_LEN[DATA_I_WIDTH-1 - bit_cnt]; end
STATE_DATA: begin dout_valid_buf <= 1'b1; dout_data_buf <= din_array_cdc[frame_cnt][DATA_I_WIDTH-1 - bit_cnt]; end
default: begin dout_valid_buf <= 'b0 ; dout_data_buf <= 'b0; end
endcase
end
endmodule
projects/dl814_k7/dl814_k7_cal_coarse/rtl/rx_pre_process/ad9361_phase_cal_coarse.v
+6 -6
View File
@@ -268,23 +268,23 @@ always @(posedge clk) begin
if (rx_ch2_i_rec[ADC_DATA_WIDTH-1] == rx_ch4_i_rec[ADC_DATA_WIDTH-1]) begin
ad9361_cal_result_buf <= 'b0;
rx_cal_ch1_i_buf <= rx_ch1_i;
rx_cal_ch2_i_buf <= -rx_ch2_i;
rx_cal_ch3_i_buf <= rx_ch3_i;
rx_cal_ch4_i_buf <= -rx_ch4_i;
rx_cal_ch1_q_buf <= rx_ch1_q;
rx_cal_ch2_i_buf <= -rx_ch2_i;
rx_cal_ch2_q_buf <= -rx_ch2_q;
rx_cal_ch3_i_buf <= rx_ch3_i;
rx_cal_ch3_q_buf <= rx_ch3_q;
rx_cal_ch4_i_buf <= -rx_ch4_i;
rx_cal_ch4_q_buf <= -rx_ch4_q;
end
else begin
ad9361_cal_result_buf <= 'b1;
rx_cal_ch1_i_buf <= rx_ch1_i;
rx_cal_ch2_i_buf <= -rx_ch2_i;
rx_cal_ch3_i_buf <= -rx_ch3_i;
rx_cal_ch4_i_buf <= rx_ch4_i;
rx_cal_ch1_q_buf <= rx_ch1_q;
rx_cal_ch2_i_buf <= -rx_ch2_i;
rx_cal_ch2_q_buf <= -rx_ch2_q;
rx_cal_ch3_i_buf <= -rx_ch3_i;
rx_cal_ch3_q_buf <= -rx_ch3_q;
rx_cal_ch4_i_buf <= rx_ch4_i;
rx_cal_ch4_q_buf <= rx_ch4_q;
end
end
projects/dl814_k7/dl814_k7_cal_coarse/rtl/rx_pre_process/rx_pre_process.v
+44 -22
View File
@@ -52,7 +52,9 @@ module rx_pre_process
parameter PS_PL_WIDTH = 32 ,
parameter WEIGHT_TRUNC_WIDTH = 16 ,
parameter CMPLX_DIM = 2 ,
parameter OUTPUT_DATA_WIDTH = ADC_DATA_WIDTH
parameter OUTPUT_DATA_WIDTH = ADC_DATA_WIDTH,
parameter ACCOR_FRAME_HEAD = 32'h7E7E7E7E,
parameter WEIGHT_FRAME_HEAD = ACCOR_FRAME_HEAD // Same head is required by [c2c_bridge] module
)
(
// clock & reset
@@ -148,6 +150,8 @@ reg [$clog2(STABLE_CNT_MOD)-1 : 0] stable_cnt = 'b0;
reg [$clog2(SNAPSHOT_NUM)-1 : 0] snapshot_cnt = 'b0;
reg snapshot_valid = 'b0;
reg fifo_cdc_rst = 1'b0; // reset [fifo_accor_cdc] & [fifo_weight_cdc] at each hop
wire hop_start_flag_cdc;
xpm_cdc_pulse #(
@@ -231,6 +235,18 @@ always @(posedge sys_clk) begin
end
end
always @(posedge sys_clk) begin
if (sys_rst) begin
fifo_cdc_rst <= 'b0;
end
else if (acorr_state == ACORR_STATE_STABLE) begin
fifo_cdc_rst <= 1'b1;
end
else begin
fifo_cdc_rst <= 'b0;
end
end
////////////////////////////////////////////////////////////////////////////////
////////////////////// Autocorrelation of Snapshot Vector //////////////////////
////////////////////////////////////////////////////////////////////////////////
@@ -337,25 +353,27 @@ assign accor_stream_valid = stream_dout_valid; // to module port
assign accor_stream_data = stream_dout_data; // to module port
accor_mat_formatting #(
.ROW_NUM (CHANNEL_NUM ),
.COL_NUM (CHANNEL_NUM ),
.DATA_I_WIDTH (PS_PL_WIDTH )
.ROW_NUM (CHANNEL_NUM ),
.COL_NUM (CHANNEL_NUM ),
.DATA_I_WIDTH (PS_PL_WIDTH ),
.FRAME_HEAD (ACCOR_FRAME_HEAD )
) u_accor_mat_stream
(
// clock & reset
.sys_clk (sys_clk ),
.sys_rst (sys_rst ),
.clk_96m (clk_96m ),
.ant_rst (ant_rst ),
.sys_clk (sys_clk ),
.sys_rst (sys_rst ),
.clk_96m (clk_96m ),
.ant_rst (ant_rst ),
// input data, sync to [sys_clk]
.din_valid (stream_din_valid ),
.din_real (stream_din_real ),
.din_imag (stream_din_imag ),
.din_valid (stream_din_valid ),
.din_real (stream_din_real ),
.din_imag (stream_din_imag ),
.fifo_cdc_rst (fifo_cdc_rst ),
// output data, sync to [clk_96m]
.dout_valid (stream_dout_valid ),
.dout_data (stream_dout_data )
.dout_valid (stream_dout_valid ),
.dout_data (stream_dout_data )
);
@@ -377,22 +395,26 @@ wire [CHANNEL_NUM*WEIGHT_TRUNC_WIDTH-1 : 0] weight_dout_imag;
weight_vec_formatting #(
.COL_NUM (CHANNEL_NUM ),
.WEIGHT_WIDTH (PS_PL_WIDTH ),
.DATA_O_WIDTH (WEIGHT_TRUNC_WIDTH )
.DATA_O_WIDTH (WEIGHT_TRUNC_WIDTH ),
.FRAME_HEAD (WEIGHT_FRAME_HEAD )
) u_weight_vec_formatting
(
// clock & reset
.sys_clk (sys_clk ),
.sys_rst (sys_rst ),
.clk_96m (clk_96m ),
.ant_rst (ant_rst ),
.sys_clk (sys_clk ),
.sys_rst (sys_rst ),
.clk_96m (clk_96m ),
.ant_rst (ant_rst ),
// input data, sync to [clk_96m]
.din_data (weight_din_data ),
.din_data (weight_din_data ),
// sync to [sys_clk]
.fifo_cdc_rst (fifo_cdc_rst ),
// output data, sync to [sys_clk]
.dout_valid (weight_dout_valid ),
.dout_real (weight_dout_real ),
.dout_imag (weight_dout_imag )
.dout_valid (weight_dout_valid ),
.dout_real (weight_dout_real ),
.dout_imag (weight_dout_imag )
);
projects/dl814_k7/dl814_k7_cal_coarse/rtl/rx_pre_process/rx_pre_test.v
+81 -303
View File
@@ -36,24 +36,27 @@ module rx_pre_test
input sys_clk_4x ,
input sys_rst ,
// calc result
input ad9361_cal_result , // sync to [sys_clk]
input ad9361_cal_result ,
input ad9361_cal_valid ,
//
input hop_trigger ,
input hop_trigger_en ,
// output test data
output [ADC_DATA_WIDTH-1:0] rx_ch1_i , // sync to [sys_clk]
output [ADC_DATA_WIDTH-1:0] rx_ch1_q , // sync to [sys_clk]
output [ADC_DATA_WIDTH-1:0] rx_ch2_i , // sync to [sys_clk]
output [ADC_DATA_WIDTH-1:0] rx_ch2_q , // sync to [sys_clk]
output [ADC_DATA_WIDTH-1:0] rx_ch3_i , // sync to [sys_clk]
output [ADC_DATA_WIDTH-1:0] rx_ch3_q , // sync to [sys_clk]
output [ADC_DATA_WIDTH-1:0] rx_ch4_i , // sync to [sys_clk]
output [ADC_DATA_WIDTH-1:0] rx_ch4_q , // sync to [sys_clk]
output hop_start_flag // sync to [sys_clk_4x]
output [ADC_DATA_WIDTH-1:0] rx_ch1_i ,
output [ADC_DATA_WIDTH-1:0] rx_ch1_q ,
output [ADC_DATA_WIDTH-1:0] rx_ch2_i ,
output [ADC_DATA_WIDTH-1:0] rx_ch2_q ,
output [ADC_DATA_WIDTH-1:0] rx_ch3_i ,
output [ADC_DATA_WIDTH-1:0] rx_ch3_q ,
output [ADC_DATA_WIDTH-1:0] rx_ch4_i ,
output [ADC_DATA_WIDTH-1:0] rx_ch4_q ,
output hop_start_flag
);
localparam HOP_CNT_MOD_192M = 192*200;
localparam HOP_CNT_MOD_48M = 48*200;
// [hop_start_flag] generation
// data valid cdc
wire ad9361_cal_valid_cdc;
xpm_cdc_single #(
@@ -70,27 +73,70 @@ xpm_cdc_single #(
.src_in (ad9361_cal_valid ) // 1-bit input: Input signal to be synchronized to dest_clk domain.
);
// auto hop flag generation
reg [$clog2(HOP_CNT_MOD_192M)-1 : 0] hop_cnt_192m = 'b0;
reg hop_flag = 'b0;
assign hop_start_flag = hop_flag;
reg hop_flag_auto = 'b0;
always @(posedge sys_clk_4x) begin
if (sys_rst) begin
hop_cnt_192m = 'b0;
hop_flag = 'b0;
hop_flag_auto = 'b0;
end
else if (ad9361_cal_valid_cdc) begin
hop_cnt_192m <= (hop_cnt_192m == HOP_CNT_MOD_192M-1) ? 'b0 : hop_cnt_192m + 1'b1;
hop_flag <= (hop_cnt_192m == 20) ? 1'b1 : 1'b0;
hop_flag_auto <= (hop_cnt_192m == 20) ? 1'b1 : 1'b0;
end
else begin
hop_cnt_192m <= 'b0;
hop_flag = 'b0;
hop_flag_auto = 'b0;
end
end
// read rx data
// manual hop flag generation
reg hop_flag_manual = 'b0;
reg hop_trigger_d1 = 'b0;
always @(posedge sys_clk_4x) begin
hop_trigger_d1 <= hop_trigger;
end
always @(posedge sys_clk_4x) begin
if (sys_rst) begin
hop_flag_manual <= 'b0;
end
else if (ad9361_cal_valid_cdc) begin
if (~hop_trigger_d1 && hop_trigger) begin
hop_flag_manual <= 1'b1;
end
else begin
hop_flag_manual <= 1'b0;
end
end
else begin
hop_flag_manual <= 'b0;
end
end
// output hop flag
reg hop_start_flag_buf = 'b0;
assign hop_start_flag = hop_start_flag_buf;
always @(posedge sys_clk_4x) begin
if (sys_rst) begin
hop_start_flag_buf <= 'b0;
end
else begin
if (hop_trigger_en) begin
hop_start_flag_buf <= hop_flag_manual;
end
else begin
hop_start_flag_buf <= hop_flag_auto;
end
end
end
// hop flag cdc
wire hop_flag_cdc;
xpm_cdc_pulse #(
@@ -101,23 +147,24 @@ xpm_cdc_pulse #(
.SIM_ASSERT_CHK (0) // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
) u_hop_flag_cdc
(
.dest_pulse (hop_flag_cdc ), // 1-bit output: Outputs a pulse the size of one dest_clk period when a pulse
// transfer is correctly initiated on src_pulse input. This output is
// combinatorial unless REG_OUTPUT is set to 1.
.dest_clk (sys_clk ), // 1-bit input: Destination clock.
.dest_rst (sys_rst ), // 1-bit input: optional; required when RST_USED = 1
.src_clk (sys_clk_4x ), // 1-bit input: Source clock.
.src_pulse (hop_flag ), // 1-bit input: Rising edge of this signal initiates a pulse transfer to the
// destination clock domain. The minimum gap between each pulse transfer must be
// at the minimum 2*(larger(src_clk period, dest_clk period)). This is measured
// between the falling edge of a src_pulse to the rising edge of the next
// src_pulse. This minimum gap will guarantee that each rising edge of src_pulse
// will generate a pulse the size of one dest_clk period in the destination
// clock domain. When RST_USED = 1, pulse transfers will not be guaranteed while
// src_rst and/or dest_rst are asserted.
.src_rst (sys_rst ) // 1-bit input: optional; required when RST_USED = 1
.dest_pulse (hop_flag_cdc ), // 1-bit output: Outputs a pulse the size of one dest_clk period when a pulse
// transfer is correctly initiated on src_pulse input. This output is
// combinatorial unless REG_OUTPUT is set to 1.
.dest_clk (sys_clk ), // 1-bit input: Destination clock.
.dest_rst (sys_rst ), // 1-bit input: optional; required when RST_USED = 1
.src_clk (sys_clk_4x ), // 1-bit input: Source clock.
.src_pulse (hop_start_flag_buf ), // 1-bit input: Rising edge of this signal initiates a pulse transfer to the
// destination clock domain. The minimum gap between each pulse transfer must be
// at the minimum 2*(larger(src_clk period, dest_clk period)). This is measured
// between the falling edge of a src_pulse to the rising edge of the next
// src_pulse. This minimum gap will guarantee that each rising edge of src_pulse
// will generate a pulse the size of one dest_clk period in the destination
// clock domain. When RST_USED = 1, pulse transfers will not be guaranteed while
// src_rst and/or dest_rst are asserted.
.src_rst (sys_rst ) // 1-bit input: optional; required when RST_USED = 1
);
// data rom address counter
reg [$clog2(HOP_CNT_MOD_48M)-1 : 0] hop_cnt_48m = 'b0;
always @(posedge sys_clk) begin
@@ -137,6 +184,7 @@ always @(posedge sys_clk) begin
end
end
// rom interface
wire [95:0] hop_data;
wire [11:0] rom_ch1_i,rom_ch2_i,rom_ch3_i,rom_ch4_i;
@@ -152,7 +200,6 @@ rom_hop_data u_rom_hop_data
.douta (hop_data ) // output wire [95 : 0] douta
);
reg [11:0] rom_ch1_i_buf,rom_ch2_i_buf,rom_ch3_i_buf,rom_ch4_i_buf;
reg [11:0] rom_ch1_q_buf,rom_ch2_q_buf,rom_ch3_q_buf,rom_ch4_q_buf;
@@ -201,272 +248,3 @@ end
end
endmodule
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
// _ _ ____
// | | ___ ___| |__ / ___| __ _ ___
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
// \___/ \___/|___/_| |_| \____|\__,_|\___/
//
// Create Date: 2022/11/16 15:08:02
// Design Name:
// Module Name: tb_re_pre_test
// Project Name:
// Target Devices:
// Tool Versions:
// Description: testbench for [rx_pre_test]
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
// module tb_re_pre_test;
// reg sys_clk = 1'b1;
// reg sys_clk_4x = 1'b1;
// reg sys_rst = 1'b1;
// reg ad9361_cal_result = 1'b0;
// reg ad9361_cal_valid = 1'b0;
// wire [11:0] rx_ch1_i;
// wire [11:0] rx_ch1_q;
// wire [11:0] rx_ch2_i;
// wire [11:0] rx_ch2_q;
// wire [11:0] rx_ch3_i;
// wire [11:0] rx_ch3_q;
// wire [11:0] rx_ch4_i;
// wire [11:0] rx_ch4_q;
// wire hop_start_flag;
// rx_pre_test u_rx_pre_test
// (
// // clock & reset
// .sys_clk (sys_clk ),
// .sys_clk_4x (sys_clk_4x ),
// .sys_rst (sys_rst ),
// // calc result
// .ad9361_cal_result (ad9361_cal_result ),
// .ad9361_cal_valid (ad9361_cal_valid ),
// // output test data
// .rx_ch1_i (rx_ch1_i ),
// .rx_ch1_q (rx_ch1_q ),
// .rx_ch2_i (rx_ch2_i ),
// .rx_ch2_q (rx_ch2_q ),
// .rx_ch3_i (rx_ch3_i ),
// .rx_ch3_q (rx_ch3_q ),
// .rx_ch4_i (rx_ch4_i ),
// .rx_ch4_q (rx_ch4_q ),
// .hop_start_flag (hop_start_flag )
// );
// // system clock generation
// always begin
// #20 sys_clk = ~sys_clk;
// end
// always begin
// #5 sys_clk_4x = ~sys_clk_4x;
// end
// initial begin
// #102
// sys_rst = 1'b0;
// #100
// ad9361_cal_valid = 1'b1;
// end
// endmodule
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
// _ _ ____
// | | ___ ___| |__ / ___| __ _ ___
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
// \___/ \___/|___/_| |_| \____|\__,_|\___/
//
// Create Date: 2022/11/16 15:58:28
// Design Name:
// Module Name: tb_rx_pre_test
// Project Name:
// Target Devices:
// Tool Versions:
// Description: Co-simulation testbench for [rx_pre_process] and [rx_pre_test]
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
// module tb_rx_pre_test;
// localparam COL_NUM = 4;
// localparam PS_PL_WIDTH = 32;
// localparam FRAME_HEAD = 32'b01001100011100001111000111001101;
// localparam FRAME_BITS = (2+COL_NUM*2)*PS_PL_WIDTH;
// reg [FRAME_BITS-1 : 0] weight_stream_buf =
// {
// FRAME_HEAD, 32'd40,
// 32'd1681399168, -32'd984290880,
// 32'd1494147072, -32'd1542469120,
// 32'd1531326976, 32'd1443639808,
// 32'd1665626240, 32'd1083120000
// };
// reg sys_clk = 1'b1;
// reg sys_clk_4x = 1'b1;
// reg sys_rst = 1'b1;
// reg clk_96m = 1'b1;
// reg ant_rst = 1'b1;
// reg ad9361_1_cal_start = 'b0;
// wire ad9361_1_cal_done ;
// reg ad9361_2_cal_start = 'b0;
// wire ad9361_2_cal_done ;
// wire ad9361_cal_result ;
// wire ad9361_cal_valid ;
// reg ad9361_recal = 'b0;
// // phase difference of 0 degree
// wire [11:0] rx_ch1_i;
// wire [11:0] rx_ch1_q;
// wire [11:0] rx_ch2_i;
// wire [11:0] rx_ch2_q;
// wire [11:0] rx_ch3_q;
// wire [11:0] rx_ch3_i;
// wire [11:0] rx_ch4_i;
// wire [11:0] rx_ch4_q;
// wire hop_start_flag;
// wire accor_stream_valid;
// wire accor_stream_data;
// wire weight_stream_data;
// wire rx_data_valid;
// wire [11:0] rx_data_i, rx_data_q;
// rx_pre_process #(
// .BYPASS_CAL (1)
// ) u_rx_pre_process
// (
// // clock & reset
// .sys_clk (sys_clk ), // sync to adc data
// .sys_clk_4x (sys_clk_4x ), // sync to physical layer
// .sys_rst (sys_rst ), // sync to [sys_clk]
// .clk_96m (clk_96m ), // sync to c2c data
// .ant_rst (ant_rst ), // sync to [clk_96m]
// // input data interface
// .rx_ch1_i (rx_ch1_i ),
// .rx_ch1_q (rx_ch1_q ),
// .rx_ch2_i (rx_ch2_i ),
// .rx_ch2_q (rx_ch2_q ),
// .rx_ch3_i (rx_ch3_i ),
// .rx_ch3_q (rx_ch3_q ),
// .rx_ch4_i (rx_ch4_i ),
// .rx_ch4_q (rx_ch4_q ),
// // ad9361 calibration interface
// .ad9361_1_cal_start (ad9361_1_cal_start ),
// .ad9361_1_cal_done (ad9361_1_cal_done ),
// .ad9361_2_cal_start (ad9361_2_cal_start ),
// .ad9361_2_cal_done (ad9361_2_cal_done ),
// .ad9361_cal_result (ad9361_cal_result ),
// .ad9361_cal_valid (ad9361_cal_valid ),
// .ad9361_recal (ad9361_recal ),
// // nulling algotithm interface
// .hop_start_flag (hop_start_flag ), // sync to [sys_clk_4x]
// .accor_stream_valid (accor_stream_valid ), // sync to [clk_96m]
// .accor_stream_data (accor_stream_data ), // sync to [clk_96m]
// .weight_stream_data (weight_stream_data ), // sync to [clk_96m]
// .rx_data_valid (rx_data_valid ), // sync to [sys_clk]
// .rx_data_i (rx_data_i ), // sync to [sys_clk]
// .rx_data_q (rx_data_q ) // sync to [sys_clk]
// );
// // temporary test cases
// rx_pre_test #(
// .BYPASS_CAL (1)
// ) u_rx_pre_test
// (
// // clock & reset
// .sys_clk (sys_clk ),
// .sys_clk_4x (sys_clk_4x ),
// .sys_rst (sys_rst ),
// // calc result
// .ad9361_cal_result (ad9361_cal_result ),
// .ad9361_cal_valid (ad9361_cal_valid ),
// // output test data
// .rx_ch1_i (rx_ch1_i ),
// .rx_ch1_q (rx_ch1_q ),
// .rx_ch2_i (rx_ch2_i ),
// .rx_ch2_q (rx_ch2_q ),
// .rx_ch3_i (rx_ch3_i ),
// .rx_ch3_q (rx_ch3_q ),
// .rx_ch4_i (rx_ch4_i ),
// .rx_ch4_q (rx_ch4_q ),
// .hop_start_flag (hop_start_flag )
// );
// // system clock generation
// always begin
// #20 sys_clk = ~sys_clk;
// end
// always begin
// #5 sys_clk_4x = ~sys_clk_4x;
// end
// always begin
// #7;
// clk_96m = ~clk_96m;
// #3;
// end
// initial begin
// #102
// sys_rst = 1'b0;
// ant_rst = 1'b0;
// end
// reg weight_stream_valid = 'b0;
// always @(negedge accor_stream_valid) begin
// #((48*50)*40+18); // 50us of 48M clock
// weight_stream_valid = 'b1;
// #(FRAME_BITS*20);
// weight_stream_valid = 'b0;
// end
// reg [$clog2(FRAME_BITS)-1 : 0] weight_stream_cnt;
// always @(posedge clk_96m) begin
// if (sys_rst) begin
// weight_stream_cnt <= 'b0;
// end
// else begin
// weight_stream_cnt <= (weight_stream_valid & ~(weight_stream_cnt == FRAME_BITS - 1)) ? weight_stream_cnt + 1'b1 : 'b0;
// end
// end
// assign weight_stream_data = weight_stream_buf[FRAME_BITS-1-weight_stream_cnt];
// endmodule
projects/dl814_k7/dl814_k7_cal_coarse/rtl/rx_pre_process/spatial_filter.v
+1 -1
View File
@@ -56,7 +56,7 @@ module spatial_filter
output [FILTER_O_WIDTH-1 : 0] dout_imag
);
localparam RAM_HOP_DEPTH = 9328;
localparam RAM_HOP_DEPTH = 9728;
localparam CMPLX_DIM = 2;
localparam FILTER_MULT_FULL_WIDTH = WEIGHT_WIDTH+ADC_WIDTH+1;
projects/dl814_k7/dl814_k7_cal_coarse/rtl/rx_pre_process/weight_vec_formatting.v
+179 -147
View File
@@ -43,26 +43,28 @@
module weight_vec_formatting
#(
parameter COL_NUM = 4,
parameter WEIGHT_WIDTH = 32,
parameter DATA_O_WIDTH = 16,
parameter FRAME_HEAD = 32'h7E7E7E7E,
parameter FIFO_CDC_DEPTH = 32
parameter COL_NUM = 4,
parameter WEIGHT_WIDTH = 32,
parameter DATA_O_WIDTH = 16,
parameter FRAME_HEAD = 32'h7E7E7E7E,
parameter FIFO_CDC_DEPTH = 32
)
(
// clock & reset
input sys_clk,
input sys_rst,
input clk_96m,
input ant_rst,
// clock & reset
input sys_clk,
input sys_rst,
input clk_96m,
input ant_rst,
// input data
input din_data,
// input data
input din_data,
// output data
output dout_valid,
output [COL_NUM*DATA_O_WIDTH-1 : 0] dout_real,
output [COL_NUM*DATA_O_WIDTH-1 : 0] dout_imag
input fifo_cdc_rst,
// output data
output dout_valid,
output [COL_NUM*DATA_O_WIDTH-1 : 0] dout_real,
output [COL_NUM*DATA_O_WIDTH-1 : 0] dout_imag
);
localparam CMPLX_DIM = 2;
@@ -86,12 +88,12 @@ integer m;
reg [WEIGHT_WIDTH-1 : 0] din_shift = 'b0;
always @(posedge clk_96m) begin
if (ant_rst) begin
din_shift <= 'b0;
end
else begin
din_shift <= {din_shift[WEIGHT_WIDTH-2 : 0],din_data};
end
if (ant_rst) begin
din_shift <= 'b0;
end
else begin
din_shift <= {din_shift[WEIGHT_WIDTH-2 : 0],din_data};
end
end
// input data center state machine & counter
@@ -100,160 +102,190 @@ reg [$clog2(WEIGHT_WIDTH)-1 : 0] bit_cnt = 'b0; // bit counter within one frame
reg [$clog2(FRAME_LEN)-1 : 0] frame_cnt = 'b0; // frame counter
always @(posedge clk_96m) begin
if (ant_rst) begin
state_din <= STATE_IDLE_DIN;
end
else begin
case (state_din)
STATE_IDLE_DIN: state_din <= (din_shift == FRAME_HEAD) ? STATE_LEN_DIN : STATE_IDLE_DIN;
STATE_LEN_DIN : begin
if (bit_cnt == WEIGHT_WIDTH-1) begin
state_din <= (din_shift == BYTE_LEN) ? STATE_DATA_DIN : STATE_IDLE_DIN;
end
else begin
state_din <= STATE_LEN_DIN;
end
end
STATE_DATA_DIN: state_din <= (frame_cnt == FRAME_LEN-1 && bit_cnt == WEIGHT_WIDTH-1) ? STATE_IDLE_DIN : STATE_DATA_DIN;
default: state_din <= STATE_IDLE_DIN;
endcase
end
if (ant_rst) begin
state_din <= STATE_IDLE_DIN;
end
else begin
case (state_din)
STATE_IDLE_DIN: state_din <= (din_shift == FRAME_HEAD) ? STATE_LEN_DIN : STATE_IDLE_DIN;
STATE_LEN_DIN : begin
if (bit_cnt == WEIGHT_WIDTH-1) begin
state_din <= (din_shift == BYTE_LEN) ? STATE_DATA_DIN : STATE_IDLE_DIN;
end
else begin
state_din <= STATE_LEN_DIN;
end
end
STATE_DATA_DIN: state_din <= (frame_cnt == FRAME_LEN-1 && bit_cnt == WEIGHT_WIDTH-1) ? STATE_IDLE_DIN : STATE_DATA_DIN;
default: state_din <= STATE_IDLE_DIN;
endcase
end
end
always @(posedge clk_96m) begin
if (ant_rst) begin
bit_cnt <= 'b0;
end
else if (state_din == STATE_IDLE_DIN) begin
bit_cnt <= 'b0;
end
else begin
bit_cnt <= (bit_cnt == WEIGHT_WIDTH-1) ? 'b0 : bit_cnt + 1'b1;
end
if (ant_rst) begin
bit_cnt <= 'b0;
end
else if (state_din == STATE_IDLE_DIN) begin
bit_cnt <= 'b0;
end
else begin
bit_cnt <= (bit_cnt == WEIGHT_WIDTH-1) ? 'b0 : bit_cnt + 1'b1;
end
end
always @(posedge clk_96m) begin
if (ant_rst) begin
frame_cnt <= 'b0;
end
else if (state_din == STATE_IDLE_DIN) begin
frame_cnt <= 'b0;
end
else if (state_din == STATE_DATA_DIN && bit_cnt == WEIGHT_WIDTH-1) begin
frame_cnt <= frame_cnt + 1'b1;
end
else begin
frame_cnt <= frame_cnt;
end
if (ant_rst) begin
frame_cnt <= 'b0;
end
else if (state_din == STATE_IDLE_DIN) begin
frame_cnt <= 'b0;
end
else if (state_din == STATE_DATA_DIN && bit_cnt == WEIGHT_WIDTH-1) begin
frame_cnt <= frame_cnt + 1'b1;
end
else begin
frame_cnt <= frame_cnt;
end
end
// output data center state machine & counter
reg [$clog2(STATE_NUM_DOUT)-1 : 0] state_dout = STATE_IDLE_DOUT;
wire [$clog2(FIFO_CDC_DEPTH)-1 : 0] fifo_rd_cnt;
always @(posedge sys_clk) begin
if (sys_rst) begin
state_dout <= STATE_IDLE_DOUT;
end
else begin
case (state_dout)
STATE_IDLE_DOUT: state_dout <= (fifo_rd_cnt == FRAME_LEN) ? STATE_READ_DOUT : STATE_IDLE_DOUT;
STATE_READ_DOUT: state_dout <= (fifo_rd_cnt == 0) ? STATE_IDLE_DOUT : STATE_READ_DOUT;
default: state_dout <= STATE_IDLE_DOUT;
endcase
end
end
// clock domain crossing fifo
// clock domain crossing fifo, write channel
reg [DATA_O_WIDTH-1 : 0] fifo_din = 'b0;
reg fifo_wr_en = 'b0;
wire [DATA_O_WIDTH-1 : 0] fifo_dout;
reg fifo_rd_en = 'b0;
always @(posedge clk_96m) begin
if (ant_rst) begin
fifo_din <= 'b0;
fifo_wr_en <= 'b0;
end
else if (state_din == STATE_DATA_DIN && bit_cnt == DATA_O_WIDTH-1) begin
fifo_din <= din_shift[DATA_O_WIDTH-1 -: DATA_O_WIDTH];
fifo_wr_en <= 1'b1;
end
else begin
fifo_din <= fifo_din;
fifo_wr_en <= 'b0;
end
if (ant_rst) begin
fifo_din <= 'b0;
fifo_wr_en <= 'b0;
end
else if (state_din == STATE_DATA_DIN && bit_cnt == DATA_O_WIDTH-1) begin
fifo_din <= din_shift[DATA_O_WIDTH-1 -: DATA_O_WIDTH];
fifo_wr_en <= 1'b1;
end
else begin
fifo_din <= fifo_din;
fifo_wr_en <= 'b0;
end
end
// clock domain crossing fifo, read channel
reg fifo_rd_en = 'b0;
reg fifo_rd_en_d1 = 'b0;
reg [$clog2(COL_NUM*CMPLX_DIM)-1 : 0] fifo_rd_cnt = 'b0;
reg [$clog2(COL_NUM*CMPLX_DIM)-1 : 0] fifo_rd_cnt_d1 = 'b0; // read data latency
reg fifo_rd_valid = 'b0;
wire [DATA_O_WIDTH-1 : 0] fifo_dout;
wire [$clog2(COL_NUM*CMPLX_DIM*2)-1 : 0] fifo_rd_num;
wire fifo_full;
wire fifo_empty;
reg [DATA_O_WIDTH-1 : 0] dout_array_cdc [0 : COL_NUM*CMPLX_DIM-1];
always @(posedge sys_clk) begin
if (sys_rst) begin
fifo_rd_en <= 'b0;
end
else if (fifo_rd_num == COL_NUM*CMPLX_DIM) begin
fifo_rd_en <= 1'b1;
end
else if (fifo_rd_cnt == COL_NUM*CMPLX_DIM-1) begin
fifo_rd_en <= 'b0;
end
else begin
fifo_rd_en <= fifo_rd_en;
end
end
always @(posedge sys_clk) begin
if (sys_rst) begin
fifo_rd_en <= 'b0;
end
else if (state_dout == STATE_READ_DOUT) begin
fifo_rd_en <= 1'b1;
end
else begin
fifo_rd_en <= 'b0;
end
if (sys_rst) begin
fifo_rd_en_d1 <= 'b0;
end
else begin
fifo_rd_en_d1 <= fifo_rd_en;
end
end
always @(posedge sys_clk) begin
if (sys_rst) begin
fifo_rd_cnt <= 'b0;
end
else if (fifo_rd_en) begin
fifo_rd_cnt <= fifo_rd_cnt + 1'b1;
end
else begin
fifo_rd_cnt <= 'b0;
end
end
always @(posedge sys_clk) begin
if (sys_rst) begin
fifo_rd_cnt_d1 <= 'b0;
end
else begin
fifo_rd_cnt_d1 <= fifo_rd_cnt;
end
end
always @(posedge sys_clk) begin
if (sys_rst) begin
fifo_rd_valid <= 'b0;
end
else if (fifo_rd_cnt_d1 == COL_NUM*CMPLX_DIM-1) begin
fifo_rd_valid <= 1'b1;
end
else begin
fifo_rd_valid <= 'b0;
end
end
always @(posedge sys_clk) begin
if (sys_rst) begin
for (m = 0; m < COL_NUM*CMPLX_DIM; m = m + 1) begin
dout_array_cdc[m] <= 'b0;
end
end
else if (fifo_rd_en_d1) begin
dout_array_cdc[fifo_rd_cnt_d1] <= fifo_dout;
end
else begin
for (m = 0; m < COL_NUM*CMPLX_DIM; m = m + 1) begin
dout_array_cdc[m] <= dout_array_cdc[m];
end
end
end
fifo_weight_cdc u_fifo_weight_cdc
(
.wr_clk (clk_96m ), // input wire wr_clk
.wr_rst (ant_rst ), // input wire wr_rst
.rd_clk (sys_clk ), // input wire rd_clk
.rd_rst (sys_rst ), // input wire rd_rst
.din (fifo_din ), // input wire [15 : 0] din
.wr_en (fifo_wr_en ), // input wire wr_en
.rd_en (fifo_rd_en ), // input wire rd_en
.dout (fifo_dout ), // output wire [15 : 0] dout
.full ( ), // output wire full
.empty ( ), // output wire empty
.rd_data_count (fifo_rd_cnt) // output wire [3 : 0] rd_data_count
.rst (fifo_cdc_rst ), // input wire rd_rst
.wr_clk (clk_96m ), // input wire wr_clk
.rd_clk (sys_clk ), // input wire rd_clk
.din (fifo_din ), // input wire [15 : 0] din
.wr_en (fifo_wr_en ), // input wire wr_en
.rd_en (fifo_rd_en ), // input wire rd_en
.dout (fifo_dout ), // output wire [15 : 0] dout
.full (fifo_full ), // output wire full
.empty (fifo_empty ), // output wire empty
.rd_data_count (fifo_rd_num ) // output wire [3 : 0] rd_data_count
);
// format output data array
reg [DATA_O_WIDTH-1 : 0] dout_real_array [0 : COL_NUM-1];
reg [DATA_O_WIDTH-1 : 0] dout_imag_array [0 : COL_NUM-1];
reg dout_valid_buf = 'b0;
wire [DATA_O_WIDTH-1 : 0] dout_real_array [0 : COL_NUM-1];
wire [DATA_O_WIDTH-1 : 0] dout_imag_array [0 : COL_NUM-1];
generate
for(i = 0; i < COL_NUM; i = i + 1) begin: array_convert
assign dout_real[i*DATA_O_WIDTH +: DATA_O_WIDTH] = dout_real_array[i];
assign dout_imag[i*DATA_O_WIDTH +: DATA_O_WIDTH] = dout_imag_array[i];
for(i = 0; i < COL_NUM; i = i + 1) begin: array_convert_stg1
assign dout_real_array[i] = dout_array_cdc[2*i];
assign dout_imag_array[i] = dout_array_cdc[2*i+1];
end
endgenerate
assign dout_valid = dout_valid_buf;
always @(posedge sys_clk) begin
if (sys_rst) begin
for (m = 0; m < COL_NUM; m = m + 1) begin: dout_data_array_reset
dout_real_array[m] <= 'b0;
dout_imag_array[m] <= 'b0;
end
end
else if (fifo_rd_en) begin
if (fifo_rd_cnt[0]) begin
dout_imag_array[COL_NUM-1-fifo_rd_cnt[$clog2(FIFO_CDC_DEPTH)-1 : 1]] <= fifo_dout;
end
else begin
dout_real_array[COL_NUM-fifo_rd_cnt[$clog2(FIFO_CDC_DEPTH)-1 : 1]] <= fifo_dout;
end
end
generate
for(i = 0; i < COL_NUM; i = i + 1) begin: array_convert_stg2
assign dout_real[i*DATA_O_WIDTH +: DATA_O_WIDTH] = dout_real_array[i];
assign dout_imag[i*DATA_O_WIDTH +: DATA_O_WIDTH] = dout_imag_array[i];
end
endgenerate
always @(posedge sys_clk) begin
if (sys_rst) begin
dout_valid_buf <= 'b0;
end
else if (state_dout == STATE_READ_DOUT && fifo_rd_cnt == 0) begin
dout_valid_buf <= 1'b1;
end
else begin
dout_valid_buf <= 'b0;
end
end
assign dout_valid = fifo_rd_valid;
endmodule
projects/dl814_k7/dl814_k7_cal_coarse/rtl/system_top.v
+60 -34
View File
@@ -400,8 +400,9 @@ wire rf_dary;
wire rf_dout;
// nulling algorithm
wire accor_stream_valid;
wire accor_stream_data;
wire weight_stream_data;
reg weight_stream_data = 'b0 ;
// buffer output data
reg ant_din1_buf = 'b0;
@@ -420,33 +421,28 @@ always @(posedge clk_96m) begin
ant_dary_buf <= 'b0;
end
else begin
ant_din1_buf <= rf_data | accor_stream_data;
ant_din1_buf <= (accor_stream_valid) ? accor_stream_data : rf_data;
ant_tr_buf <= rf_tr;
ant_dary_buf <= rf_dary;
end
end
// input data
wire ant_dout0_cdc, ant_dout1_cdc;
reg ant_dout1_d1 = 'b0;
reg ant_dout1_d2 = 'b0;
assign rf_dout = ant_dout1_cdc;
assign weight_stream_data = ant_dout1_cdc;
xpm_cdc_single u_cdc_ant_dout0
(
.dest_out (ant_dout0_cdc ), // 1-bit output: src_in synchronized to the destination clock domain. This output is registered.
.dest_clk (clk_96m ), // 1-bit input: Clock signal for the destination clock domain.
.src_clk (ant_cout ), // 1-bit input: optional; required when SRC_INPUT_REG = 1
.src_in (ant_dout0 ) // 1-bit input: Input signal to be synchronized to dest_clk domain.
);
xpm_cdc_single u_cdc_ant_dout1
(
.dest_out (ant_dout1_cdc ), // 1-bit output: src_in synchronized to the destination clock domain. This output is registered.
.dest_clk (clk_96m ), // 1-bit input: Clock signal for the destination clock domain.
.src_clk (ant_cout ), // 1-bit input: optional; required when SRC_INPUT_REG = 1
.src_in (ant_dout1 ) // 1-bit input: Input signal to be synchronized to dest_clk domain.
);
always @(posedge clk_96m) begin
if (ant_rst) begin
ant_dout1_d1 <= 'b0;
ant_dout1_d2 <= 'b0;
weight_stream_data <= 'b0;
end
else begin
ant_dout1_d1 <= ant_dout1;
ant_dout1_d2 <= ant_dout1_d1;
weight_stream_data <= ant_dout1_d2;
end
end
ant_rf_ctrl u_ant_rf_ctrl
(
@@ -605,13 +601,13 @@ wire [11:0] rx_ch4_i_test, rx_ch4_q_test;
wire rx_data_valid;
wire [29:0] rx_data_i, rx_data_q;
wire hop_trigger;
wire hop_start_flag ;
wire accor_stream_valid ;
// wire accor_stream_valid ;
// wire accor_stream_data ;
// wire weight_stream_data ;
wire rx_data_sel;
always @(posedge sys_clk) begin
if (sys_rst) begin
rx_ch1_i <= 'b0;
@@ -623,7 +619,7 @@ always @(posedge sys_clk) begin
rx_ch3_q <= 'b0;
rx_ch4_q <= 'b0;
end
else if (rx_data_sel) begin
else if (ad9361_cal_valid) begin
rx_ch1_i <= rx_ch1_i_test;
rx_ch2_i <= rx_ch2_i_test;
rx_ch3_i <= rx_ch3_i_test;
@@ -725,6 +721,8 @@ rx_pre_test u_rx_pre_test
.sys_clk (sys_clk ),
.sys_clk_4x (sys_clk_4x ),
.sys_rst (sys_rst ),
.hop_trigger (hop_trigger ),
.hop_trigger_en (hop_trigger_en ),
// calc result
.ad9361_cal_result (ad9361_cal_result ),
.ad9361_cal_valid (ad9361_cal_valid ),
@@ -886,7 +884,7 @@ ila_2x12x1024 u_ila_tx
.probe1 (tx_ch1_q ) // input wire [11:0] probe1
);
ila_8x12_2x30_131072 u_ila_rx
ila_8x12_2x30_8192 u_ila_rx
(
.clk (sys_clk ), // input wire clk
.probe0 (u_rx_pre_process.rx_cal_ch1_i ), // input wire [11:0] probe0
@@ -921,13 +919,35 @@ ila_cal u_ila_cal
.probe14(u_rx_pre_process.rx_cal_ch4_q ) // input wire [11:0] probe14
);
ila_rx_pre u_ila_rx_pre
ila_rx_pre_sys u_ila_rx_pre_sys
(
.clk (clk_96m ), // input wire clk
.probe0 (u_rx_pre_process.hop_start_flag_cdc ), // input wire [0:0] probe0
.probe1 (accor_stream_valid ), // input wire [0:0] probe1
.probe2 (accor_stream_data ), // input wire [0:0] probe2
.probe3 (weight_stream_data ) // input wire [0:0] probe3
.clk (sys_clk ), // input wire clk
.probe0 (u_rx_pre_process.hop_start_flag_cdc ), // input wire [0:0] probe0
.probe1 (u_rx_pre_process.fifo_cdc_rst ), // input wire [0:0] probe1
.probe2 (u_rx_pre_process.u_accor_mat_stream.fifo_wr_en ), // input wire [0:0] probe2
.probe3 (u_rx_pre_process.u_accor_mat_stream.fifo_din ), // input wire [31:0] probe3
.probe4 (u_rx_pre_process.u_accor_mat_stream.fifo_full ), // input wire [0:0] probe4
.probe5 (u_rx_pre_process.u_weight_vec_formatting.fifo_rd_en ), // input wire [0:0] probe5
.probe6 (u_rx_pre_process.u_weight_vec_formatting.fifo_dout ), // input wire [15:0] probe6
.probe7 (u_rx_pre_process.u_weight_vec_formatting.fifo_empty ), // input wire [0:0] probe7
.probe8 (u_rx_pre_process.u_weight_vec_formatting.fifo_rd_num ) // input wire [3:0] probe8
);
ila_rx_pre_ant u_ila_rx_pre_ant
(
.clk (clk_96m ), // input wire clk
.probe0 (u_rx_pre_process.hop_start_flag_cdc ), // input wire [0:0] probe0
.probe1 (accor_stream_valid ), // input wire [0:0] probe1
.probe2 (accor_stream_data ), // input wire [0:0] probe2
.probe3 (weight_stream_data ), // input wire [0:0] probe3
.probe4 (u_rx_pre_process.fifo_cdc_rst ), // input wire [0:0] probe4
.probe5 (u_rx_pre_process.u_accor_mat_stream.fifo_rd_en ), // input wire [0:0] probe5
.probe6 (u_rx_pre_process.u_accor_mat_stream.fifo_dout ), // input wire [31:0] probe6
.probe7 (u_rx_pre_process.u_accor_mat_stream.fifo_empty ), // input wire [0:0] probe7
.probe8 (u_rx_pre_process.u_accor_mat_stream.fifo_rd_num ), // input wire [4:0] probe8
.probe9 (u_rx_pre_process.u_weight_vec_formatting.fifo_wr_en), // input wire [0:0] probe9
.probe10(u_rx_pre_process.u_weight_vec_formatting.fifo_din ), // input wire [15:0] probe10
.probe11(u_rx_pre_process.u_weight_vec_formatting.fifo_full ) // input wire [0:0] probe11
);
vio_manual_ctrl u_vio_manual_ctrl
@@ -937,8 +957,14 @@ vio_manual_ctrl u_vio_manual_ctrl
.probe_out1 (sweep_on ), // output wire [0 : 0] probe_out1
.probe_out2 (freq_set[31:0] ), // output wire [31 : 0] probe_out2
.probe_out3 (iq_sel[1:0] ), // output wire [1 : 0] probe_out3
.probe_out4 (bb_rshift[3:0] ), // output wire [3 : 0] probe_out4
.probe_out5 (rx_data_sel ) // output wire [0 : 0] probe_out5
.probe_out4 (bb_rshift[3:0] ) // output wire [3 : 0] probe_out4
);
vio_hop u_vio_hop
(
.clk (sys_clk_4x ), // input wire clk
.probe_out0 (hop_trigger ), // output wire [0 : 0] probe_out1
.probe_out1 (hop_trigger_en ) // output wire [0 : 0] probe_out2
);
endmodule