Archived
finish test of dl814_k7_cal_coarse
archive dl814_k7_cal_coarse_20230419 and dl814_k7_null_verify_20230420, the function of lcmv nulling algorithm and the data exchange between boards are verified by pre-generated data
This commit is contained in:
+7
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@@ -1,6 +1,6 @@
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version:1
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@@ -26,4 +26,5 @@ version:1
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version:1
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version:1
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eof:
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+11
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<!--The data in this file is primarily intended for consumption by Xilinx tools.
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||||
The structure and the elements are likely to change over the next few releases.
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||||
This means code written to parse this file will need to be revisited each subsequent release.-->
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||||
<application name="pa" timeStamp="Thu Apr 13 10:53:01 2023">
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||||
<application name="pa" timeStamp="Wed Apr 19 16:12:19 2023">
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||||
<section name="Project Information" visible="false">
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||||
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||||
<property name="ProjectIteration" value="1" type="ProjectIteration"/>
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||||
@@ -18,17 +18,18 @@ This means code written to parse this file will need to be revisited each subseq
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||||
</item>
|
||||
<item name="Java Command Handlers">
|
||||
<property name="AddExistingIPHandler" value="3" type="JavaHandler"/>
|
||||
<property name="CloseProject" value="1" type="JavaHandler"/>
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||||
<property name="CloseProject" value="2" type="JavaHandler"/>
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||||
<property name="CopyIPHandler" value="2" type="JavaHandler"/>
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||||
<property name="EditDelete" value="2" type="JavaHandler"/>
|
||||
<property name="ManageCompositeTargets" value="3" type="JavaHandler"/>
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||||
<property name="NewIPLocationHandler" value="2" type="JavaHandler"/>
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||||
<property name="OpenPreviousIPHandler" value="1" type="JavaHandler"/>
|
||||
<property name="RecustomizeCore" value="3" type="JavaHandler"/>
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||||
<property name="UpgradeIP" value="1" type="JavaHandler"/>
|
||||
</item>
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||||
<item name="Gui Handlers">
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||||
<property name="BaseDialog_CANCEL" value="2" type="GuiHandlerData"/>
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||||
<property name="BaseDialog_OK" value="12" type="GuiHandlerData"/>
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||||
<property name="BaseDialog_CANCEL" value="3" type="GuiHandlerData"/>
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||||
<property name="BaseDialog_OK" value="13" type="GuiHandlerData"/>
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||||
<property name="CopyIPHandler_DESTINATION_IP_NAME" value="2" type="GuiHandlerData"/>
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||||
<property name="ExpRunTreePanel_EXP_RUN_TREE_TABLE" value="3" type="GuiHandlerData"/>
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||||
<property name="FPGAChooser_FPGA_TABLE" value="2" type="GuiHandlerData"/>
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@@ -36,14 +37,14 @@ This means code written to parse this file will need to be revisited each subseq
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<property name="GettingStartedView_MANAGE_IP" value="2" type="GuiHandlerData"/>
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<property name="GettingStartedView_START_USING_VIVADO_WITH_IP_CATALOG" value="2" type="GuiHandlerData"/>
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<property name="MainMenuMgr_FILE" value="4" type="GuiHandlerData"/>
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<property name="MainMenuMgr_IP" value="2" type="GuiHandlerData"/>
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||||
<property name="MainMenuMgr_PROJECT" value="2" type="GuiHandlerData"/>
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||||
<property name="MainMenuMgr_PROJECT" value="3" type="GuiHandlerData"/>
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||||
<property name="MainMenuMgr_TEXT_EDITOR" value="1" type="GuiHandlerData"/>
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||||
<property name="NewIPProjectWizard_IP_LOCATION" value="2" type="GuiHandlerData"/>
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||||
<property name="NewIPProjectWizard_PART" value="1" type="GuiHandlerData"/>
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||||
<property name="PACommandNames_ADD_EXISTING_IP" value="3" type="GuiHandlerData"/>
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||||
<property name="PACommandNames_CLOSE_PROJECT" value="1" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_CLOSE_PROJECT" value="2" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_COPY_IP" value="2" type="GuiHandlerData"/>
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||||
<property name="PACommandNames_GENERATE_COMPOSITE_FILE" value="2" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_RESET_COMPOSITE_FILE" value="1" type="GuiHandlerData"/>
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||||
@@ -54,11 +55,12 @@ This means code written to parse this file will need to be revisited each subseq
|
||||
<property name="SimpleOutputProductDialog_RESET_OUTPUT_PRODUCTS" value="1" type="GuiHandlerData"/>
|
||||
<property name="SrcChooserPanel_ADD_CONFIGURABLE_IP_FILES" value="4" type="GuiHandlerData"/>
|
||||
<property name="SrcMenu_IP_DOCUMENTATION" value="1" type="GuiHandlerData"/>
|
||||
<property name="SyntheticaGettingStartedView_RECENT_IP_LOCATIONS" value="1" type="GuiHandlerData"/>
|
||||
</item>
|
||||
<item name="Other">
|
||||
<property name="GuiMode" value="89" type="GuiMode"/>
|
||||
<property name="GuiMode" value="98" type="GuiMode"/>
|
||||
<property name="BatchMode" value="0" type="BatchMode"/>
|
||||
<property name="TclMode" value="63" type="TclMode"/>
|
||||
<property name="TclMode" value="66" type="TclMode"/>
|
||||
</item>
|
||||
</section>
|
||||
</application>
|
||||
|
||||
Binary file not shown.
@@ -55,17 +55,16 @@
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||||
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||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
fifo_accor_cdc your_instance_name (
|
||||
.rst(rst), // input wire rst
|
||||
.wr_clk(wr_clk), // input wire wr_clk
|
||||
.wr_rst(wr_rst), // input wire wr_rst
|
||||
.rd_clk(rd_clk), // input wire rd_clk
|
||||
.rd_rst(rd_rst), // input wire rd_rst
|
||||
.din(din), // input wire [31 : 0] din
|
||||
.wr_en(wr_en), // input wire wr_en
|
||||
.rd_en(rd_en), // input wire rd_en
|
||||
.dout(dout), // output wire [31 : 0] dout
|
||||
.full(full), // output wire full
|
||||
.empty(empty), // output wire empty
|
||||
.rd_data_count(rd_data_count) // output wire [4 : 0] rd_data_count
|
||||
.rd_data_count(rd_data_count) // output wire [5 : 0] rd_data_count
|
||||
);
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
|
||||
@@ -54,17 +54,16 @@
|
||||
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
|
||||
COMPONENT fifo_accor_cdc
|
||||
PORT (
|
||||
rst : IN STD_LOGIC;
|
||||
wr_clk : IN STD_LOGIC;
|
||||
wr_rst : IN STD_LOGIC;
|
||||
rd_clk : IN STD_LOGIC;
|
||||
rd_rst : IN STD_LOGIC;
|
||||
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
wr_en : IN STD_LOGIC;
|
||||
rd_en : IN STD_LOGIC;
|
||||
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
full : OUT STD_LOGIC;
|
||||
empty : OUT STD_LOGIC;
|
||||
rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
|
||||
rd_data_count : OUT STD_LOGIC_VECTOR(5 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
||||
@@ -75,10 +74,9 @@ END COMPONENT;
|
||||
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
|
||||
your_instance_name : fifo_accor_cdc
|
||||
PORT MAP (
|
||||
rst => rst,
|
||||
wr_clk => wr_clk,
|
||||
wr_rst => wr_rst,
|
||||
rd_clk => rd_clk,
|
||||
rd_rst => rd_rst,
|
||||
din => din,
|
||||
wr_en => wr_en,
|
||||
rd_en => rd_en,
|
||||
|
||||
BIN
Binary file not shown.
BIN
Binary file not shown.
@@ -1,10 +1,10 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Wed Apr 12 20:00:11 2023
|
||||
// Date : Wed Apr 19 16:56:12 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_accor_cdc_synth_1/fifo_accor_cdc_stub.v
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top fifo_accor_cdc -prefix
|
||||
// fifo_accor_cdc_ fifo_accor_cdc_stub.v
|
||||
// Design : fifo_accor_cdc
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
|
||||
@@ -14,18 +14,17 @@
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "fifo_generator_v13_2_4,Vivado 2019.1.3" *)
|
||||
module fifo_accor_cdc(wr_clk, wr_rst, rd_clk, rd_rst, din, wr_en, rd_en,
|
||||
dout, full, empty, rd_data_count)
|
||||
/* synthesis syn_black_box black_box_pad_pin="wr_clk,wr_rst,rd_clk,rd_rst,din[31:0],wr_en,rd_en,dout[31:0],full,empty,rd_data_count[4:0]" */;
|
||||
module fifo_accor_cdc(rst, wr_clk, rd_clk, din, wr_en, rd_en, dout, full,
|
||||
empty, rd_data_count)
|
||||
/* synthesis syn_black_box black_box_pad_pin="rst,wr_clk,rd_clk,din[31:0],wr_en,rd_en,dout[31:0],full,empty,rd_data_count[5:0]" */;
|
||||
input rst;
|
||||
input wr_clk;
|
||||
input wr_rst;
|
||||
input rd_clk;
|
||||
input rd_rst;
|
||||
input [31:0]din;
|
||||
input wr_en;
|
||||
input rd_en;
|
||||
output [31:0]dout;
|
||||
output full;
|
||||
output empty;
|
||||
output [4:0]rd_data_count;
|
||||
output [5:0]rd_data_count;
|
||||
endmodule
|
||||
|
||||
+6
-7
@@ -1,10 +1,10 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Wed Apr 12 20:00:11 2023
|
||||
-- Date : Wed Apr 19 16:56:12 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_accor_cdc_synth_1/fifo_accor_cdc_stub.vhdl
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top fifo_accor_cdc -prefix
|
||||
-- fifo_accor_cdc_ fifo_accor_cdc_stub.vhdl
|
||||
-- Design : fifo_accor_cdc
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7k410tffg900-2
|
||||
@@ -14,17 +14,16 @@ use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity fifo_accor_cdc is
|
||||
Port (
|
||||
rst : in STD_LOGIC;
|
||||
wr_clk : in STD_LOGIC;
|
||||
wr_rst : in STD_LOGIC;
|
||||
rd_clk : in STD_LOGIC;
|
||||
rd_rst : in STD_LOGIC;
|
||||
din : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
wr_en : in STD_LOGIC;
|
||||
rd_en : in STD_LOGIC;
|
||||
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
full : out STD_LOGIC;
|
||||
empty : out STD_LOGIC;
|
||||
rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 )
|
||||
rd_data_count : out STD_LOGIC_VECTOR ( 5 downto 0 )
|
||||
);
|
||||
|
||||
end fifo_accor_cdc;
|
||||
@@ -33,7 +32,7 @@ architecture stub of fifo_accor_cdc is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "wr_clk,wr_rst,rd_clk,rd_rst,din[31:0],wr_en,rd_en,dout[31:0],full,empty,rd_data_count[4:0]";
|
||||
attribute black_box_pad_pin of stub : architecture is "rst,wr_clk,rd_clk,din[31:0],wr_en,rd_en,dout[31:0],full,empty,rd_data_count[5:0]";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "fifo_generator_v13_2_4,Vivado 2019.1.3";
|
||||
begin
|
||||
|
||||
@@ -0,0 +1,526 @@
|
||||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:fifo_generator:13.2
|
||||
// IP Revision: 4
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module fifo_accor_cdc (
|
||||
rst,
|
||||
wr_clk,
|
||||
rd_clk,
|
||||
din,
|
||||
wr_en,
|
||||
rd_en,
|
||||
dout,
|
||||
full,
|
||||
empty,
|
||||
rd_data_count
|
||||
);
|
||||
|
||||
input wire rst;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME write_clk, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 write_clk CLK" *)
|
||||
input wire wr_clk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME read_clk, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 read_clk CLK" *)
|
||||
input wire rd_clk;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA" *)
|
||||
input wire [31 : 0] din;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN" *)
|
||||
input wire wr_en;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN" *)
|
||||
input wire rd_en;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA" *)
|
||||
output wire [31 : 0] dout;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL" *)
|
||||
output wire full;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY" *)
|
||||
output wire empty;
|
||||
output wire [5 : 0] rd_data_count;
|
||||
|
||||
fifo_generator_v13_2_4 #(
|
||||
.C_COMMON_CLOCK(0),
|
||||
.C_SELECT_XPM(0),
|
||||
.C_COUNT_TYPE(0),
|
||||
.C_DATA_COUNT_WIDTH(6),
|
||||
.C_DEFAULT_VALUE("BlankString"),
|
||||
.C_DIN_WIDTH(32),
|
||||
.C_DOUT_RST_VAL("0"),
|
||||
.C_DOUT_WIDTH(32),
|
||||
.C_ENABLE_RLOCS(0),
|
||||
.C_FAMILY("kintex7"),
|
||||
.C_FULL_FLAGS_RST_VAL(1),
|
||||
.C_HAS_ALMOST_EMPTY(0),
|
||||
.C_HAS_ALMOST_FULL(0),
|
||||
.C_HAS_BACKUP(0),
|
||||
.C_HAS_DATA_COUNT(0),
|
||||
.C_HAS_INT_CLK(0),
|
||||
.C_HAS_MEMINIT_FILE(0),
|
||||
.C_HAS_OVERFLOW(0),
|
||||
.C_HAS_RD_DATA_COUNT(1),
|
||||
.C_HAS_RD_RST(0),
|
||||
.C_HAS_RST(1),
|
||||
.C_HAS_SRST(0),
|
||||
.C_HAS_UNDERFLOW(0),
|
||||
.C_HAS_VALID(0),
|
||||
.C_HAS_WR_ACK(0),
|
||||
.C_HAS_WR_DATA_COUNT(0),
|
||||
.C_HAS_WR_RST(0),
|
||||
.C_IMPLEMENTATION_TYPE(2),
|
||||
.C_INIT_WR_PNTR_VAL(0),
|
||||
.C_MEMORY_TYPE(2),
|
||||
.C_MIF_FILE_NAME("BlankString"),
|
||||
.C_OPTIMIZATION_MODE(0),
|
||||
.C_OVERFLOW_LOW(0),
|
||||
.C_PRELOAD_LATENCY(1),
|
||||
.C_PRELOAD_REGS(0),
|
||||
.C_PRIM_FIFO_TYPE("512x36"),
|
||||
.C_PROG_EMPTY_THRESH_ASSERT_VAL(2),
|
||||
.C_PROG_EMPTY_THRESH_NEGATE_VAL(3),
|
||||
.C_PROG_EMPTY_TYPE(0),
|
||||
.C_PROG_FULL_THRESH_ASSERT_VAL(61),
|
||||
.C_PROG_FULL_THRESH_NEGATE_VAL(60),
|
||||
.C_PROG_FULL_TYPE(0),
|
||||
.C_RD_DATA_COUNT_WIDTH(6),
|
||||
.C_RD_DEPTH(64),
|
||||
.C_RD_FREQ(1),
|
||||
.C_RD_PNTR_WIDTH(6),
|
||||
.C_UNDERFLOW_LOW(0),
|
||||
.C_USE_DOUT_RST(1),
|
||||
.C_USE_ECC(0),
|
||||
.C_USE_EMBEDDED_REG(0),
|
||||
.C_USE_PIPELINE_REG(0),
|
||||
.C_POWER_SAVING_MODE(0),
|
||||
.C_USE_FIFO16_FLAGS(0),
|
||||
.C_USE_FWFT_DATA_COUNT(0),
|
||||
.C_VALID_LOW(0),
|
||||
.C_WR_ACK_LOW(0),
|
||||
.C_WR_DATA_COUNT_WIDTH(6),
|
||||
.C_WR_DEPTH(64),
|
||||
.C_WR_FREQ(1),
|
||||
.C_WR_PNTR_WIDTH(6),
|
||||
.C_WR_RESPONSE_LATENCY(1),
|
||||
.C_MSGON_VAL(1),
|
||||
.C_ENABLE_RST_SYNC(1),
|
||||
.C_EN_SAFETY_CKT(0),
|
||||
.C_ERROR_INJECTION_TYPE(0),
|
||||
.C_SYNCHRONIZER_STAGE(2),
|
||||
.C_INTERFACE_TYPE(0),
|
||||
.C_AXI_TYPE(1),
|
||||
.C_HAS_AXI_WR_CHANNEL(1),
|
||||
.C_HAS_AXI_RD_CHANNEL(1),
|
||||
.C_HAS_SLAVE_CE(0),
|
||||
.C_HAS_MASTER_CE(0),
|
||||
.C_ADD_NGC_CONSTRAINT(0),
|
||||
.C_USE_COMMON_OVERFLOW(0),
|
||||
.C_USE_COMMON_UNDERFLOW(0),
|
||||
.C_USE_DEFAULT_SETTINGS(0),
|
||||
.C_AXI_ID_WIDTH(1),
|
||||
.C_AXI_ADDR_WIDTH(32),
|
||||
.C_AXI_DATA_WIDTH(64),
|
||||
.C_AXI_LEN_WIDTH(8),
|
||||
.C_AXI_LOCK_WIDTH(1),
|
||||
.C_HAS_AXI_ID(0),
|
||||
.C_HAS_AXI_AWUSER(0),
|
||||
.C_HAS_AXI_WUSER(0),
|
||||
.C_HAS_AXI_BUSER(0),
|
||||
.C_HAS_AXI_ARUSER(0),
|
||||
.C_HAS_AXI_RUSER(0),
|
||||
.C_AXI_ARUSER_WIDTH(1),
|
||||
.C_AXI_AWUSER_WIDTH(1),
|
||||
.C_AXI_WUSER_WIDTH(1),
|
||||
.C_AXI_BUSER_WIDTH(1),
|
||||
.C_AXI_RUSER_WIDTH(1),
|
||||
.C_HAS_AXIS_TDATA(1),
|
||||
.C_HAS_AXIS_TID(0),
|
||||
.C_HAS_AXIS_TDEST(0),
|
||||
.C_HAS_AXIS_TUSER(1),
|
||||
.C_HAS_AXIS_TREADY(1),
|
||||
.C_HAS_AXIS_TLAST(0),
|
||||
.C_HAS_AXIS_TSTRB(0),
|
||||
.C_HAS_AXIS_TKEEP(0),
|
||||
.C_AXIS_TDATA_WIDTH(8),
|
||||
.C_AXIS_TID_WIDTH(1),
|
||||
.C_AXIS_TDEST_WIDTH(1),
|
||||
.C_AXIS_TUSER_WIDTH(4),
|
||||
.C_AXIS_TSTRB_WIDTH(1),
|
||||
.C_AXIS_TKEEP_WIDTH(1),
|
||||
.C_WACH_TYPE(0),
|
||||
.C_WDCH_TYPE(0),
|
||||
.C_WRCH_TYPE(0),
|
||||
.C_RACH_TYPE(0),
|
||||
.C_RDCH_TYPE(0),
|
||||
.C_AXIS_TYPE(0),
|
||||
.C_IMPLEMENTATION_TYPE_WACH(1),
|
||||
.C_IMPLEMENTATION_TYPE_WDCH(1),
|
||||
.C_IMPLEMENTATION_TYPE_WRCH(1),
|
||||
.C_IMPLEMENTATION_TYPE_RACH(1),
|
||||
.C_IMPLEMENTATION_TYPE_RDCH(1),
|
||||
.C_IMPLEMENTATION_TYPE_AXIS(1),
|
||||
.C_APPLICATION_TYPE_WACH(0),
|
||||
.C_APPLICATION_TYPE_WDCH(0),
|
||||
.C_APPLICATION_TYPE_WRCH(0),
|
||||
.C_APPLICATION_TYPE_RACH(0),
|
||||
.C_APPLICATION_TYPE_RDCH(0),
|
||||
.C_APPLICATION_TYPE_AXIS(0),
|
||||
.C_PRIM_FIFO_TYPE_WACH("512x36"),
|
||||
.C_PRIM_FIFO_TYPE_WDCH("1kx36"),
|
||||
.C_PRIM_FIFO_TYPE_WRCH("512x36"),
|
||||
.C_PRIM_FIFO_TYPE_RACH("512x36"),
|
||||
.C_PRIM_FIFO_TYPE_RDCH("1kx36"),
|
||||
.C_PRIM_FIFO_TYPE_AXIS("1kx18"),
|
||||
.C_USE_ECC_WACH(0),
|
||||
.C_USE_ECC_WDCH(0),
|
||||
.C_USE_ECC_WRCH(0),
|
||||
.C_USE_ECC_RACH(0),
|
||||
.C_USE_ECC_RDCH(0),
|
||||
.C_USE_ECC_AXIS(0),
|
||||
.C_ERROR_INJECTION_TYPE_WACH(0),
|
||||
.C_ERROR_INJECTION_TYPE_WDCH(0),
|
||||
.C_ERROR_INJECTION_TYPE_WRCH(0),
|
||||
.C_ERROR_INJECTION_TYPE_RACH(0),
|
||||
.C_ERROR_INJECTION_TYPE_RDCH(0),
|
||||
.C_ERROR_INJECTION_TYPE_AXIS(0),
|
||||
.C_DIN_WIDTH_WACH(1),
|
||||
.C_DIN_WIDTH_WDCH(64),
|
||||
.C_DIN_WIDTH_WRCH(2),
|
||||
.C_DIN_WIDTH_RACH(32),
|
||||
.C_DIN_WIDTH_RDCH(64),
|
||||
.C_DIN_WIDTH_AXIS(1),
|
||||
.C_WR_DEPTH_WACH(16),
|
||||
.C_WR_DEPTH_WDCH(1024),
|
||||
.C_WR_DEPTH_WRCH(16),
|
||||
.C_WR_DEPTH_RACH(16),
|
||||
.C_WR_DEPTH_RDCH(1024),
|
||||
.C_WR_DEPTH_AXIS(1024),
|
||||
.C_WR_PNTR_WIDTH_WACH(4),
|
||||
.C_WR_PNTR_WIDTH_WDCH(10),
|
||||
.C_WR_PNTR_WIDTH_WRCH(4),
|
||||
.C_WR_PNTR_WIDTH_RACH(4),
|
||||
.C_WR_PNTR_WIDTH_RDCH(10),
|
||||
.C_WR_PNTR_WIDTH_AXIS(10),
|
||||
.C_HAS_DATA_COUNTS_WACH(0),
|
||||
.C_HAS_DATA_COUNTS_WDCH(0),
|
||||
.C_HAS_DATA_COUNTS_WRCH(0),
|
||||
.C_HAS_DATA_COUNTS_RACH(0),
|
||||
.C_HAS_DATA_COUNTS_RDCH(0),
|
||||
.C_HAS_DATA_COUNTS_AXIS(0),
|
||||
.C_HAS_PROG_FLAGS_WACH(0),
|
||||
.C_HAS_PROG_FLAGS_WDCH(0),
|
||||
.C_HAS_PROG_FLAGS_WRCH(0),
|
||||
.C_HAS_PROG_FLAGS_RACH(0),
|
||||
.C_HAS_PROG_FLAGS_RDCH(0),
|
||||
.C_HAS_PROG_FLAGS_AXIS(0),
|
||||
.C_PROG_FULL_TYPE_WACH(0),
|
||||
.C_PROG_FULL_TYPE_WDCH(0),
|
||||
.C_PROG_FULL_TYPE_WRCH(0),
|
||||
.C_PROG_FULL_TYPE_RACH(0),
|
||||
.C_PROG_FULL_TYPE_RDCH(0),
|
||||
.C_PROG_FULL_TYPE_AXIS(0),
|
||||
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
|
||||
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
|
||||
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
|
||||
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
|
||||
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
|
||||
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
|
||||
.C_PROG_EMPTY_TYPE_WACH(0),
|
||||
.C_PROG_EMPTY_TYPE_WDCH(0),
|
||||
.C_PROG_EMPTY_TYPE_WRCH(0),
|
||||
.C_PROG_EMPTY_TYPE_RACH(0),
|
||||
.C_PROG_EMPTY_TYPE_RDCH(0),
|
||||
.C_PROG_EMPTY_TYPE_AXIS(0),
|
||||
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
|
||||
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
|
||||
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
|
||||
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
|
||||
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
|
||||
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
|
||||
.C_REG_SLICE_MODE_WACH(0),
|
||||
.C_REG_SLICE_MODE_WDCH(0),
|
||||
.C_REG_SLICE_MODE_WRCH(0),
|
||||
.C_REG_SLICE_MODE_RACH(0),
|
||||
.C_REG_SLICE_MODE_RDCH(0),
|
||||
.C_REG_SLICE_MODE_AXIS(0)
|
||||
) inst (
|
||||
.backup(1'D0),
|
||||
.backup_marker(1'D0),
|
||||
.clk(1'D0),
|
||||
.rst(rst),
|
||||
.srst(1'D0),
|
||||
.wr_clk(wr_clk),
|
||||
.wr_rst(1'D0),
|
||||
.rd_clk(rd_clk),
|
||||
.rd_rst(1'D0),
|
||||
.din(din),
|
||||
.wr_en(wr_en),
|
||||
.rd_en(rd_en),
|
||||
.prog_empty_thresh(6'B0),
|
||||
.prog_empty_thresh_assert(6'B0),
|
||||
.prog_empty_thresh_negate(6'B0),
|
||||
.prog_full_thresh(6'B0),
|
||||
.prog_full_thresh_assert(6'B0),
|
||||
.prog_full_thresh_negate(6'B0),
|
||||
.int_clk(1'D0),
|
||||
.injectdbiterr(1'D0),
|
||||
.injectsbiterr(1'D0),
|
||||
.sleep(1'D0),
|
||||
.dout(dout),
|
||||
.full(full),
|
||||
.almost_full(),
|
||||
.wr_ack(),
|
||||
.overflow(),
|
||||
.empty(empty),
|
||||
.almost_empty(),
|
||||
.valid(),
|
||||
.underflow(),
|
||||
.data_count(),
|
||||
.rd_data_count(rd_data_count),
|
||||
.wr_data_count(),
|
||||
.prog_full(),
|
||||
.prog_empty(),
|
||||
.sbiterr(),
|
||||
.dbiterr(),
|
||||
.wr_rst_busy(),
|
||||
.rd_rst_busy(),
|
||||
.m_aclk(1'D0),
|
||||
.s_aclk(1'D0),
|
||||
.s_aresetn(1'D0),
|
||||
.m_aclk_en(1'D0),
|
||||
.s_aclk_en(1'D0),
|
||||
.s_axi_awid(1'B0),
|
||||
.s_axi_awaddr(32'B0),
|
||||
.s_axi_awlen(8'B0),
|
||||
.s_axi_awsize(3'B0),
|
||||
.s_axi_awburst(2'B0),
|
||||
.s_axi_awlock(1'B0),
|
||||
.s_axi_awcache(4'B0),
|
||||
.s_axi_awprot(3'B0),
|
||||
.s_axi_awqos(4'B0),
|
||||
.s_axi_awregion(4'B0),
|
||||
.s_axi_awuser(1'B0),
|
||||
.s_axi_awvalid(1'D0),
|
||||
.s_axi_awready(),
|
||||
.s_axi_wid(1'B0),
|
||||
.s_axi_wdata(64'B0),
|
||||
.s_axi_wstrb(8'B0),
|
||||
.s_axi_wlast(1'D0),
|
||||
.s_axi_wuser(1'B0),
|
||||
.s_axi_wvalid(1'D0),
|
||||
.s_axi_wready(),
|
||||
.s_axi_bid(),
|
||||
.s_axi_bresp(),
|
||||
.s_axi_buser(),
|
||||
.s_axi_bvalid(),
|
||||
.s_axi_bready(1'D0),
|
||||
.m_axi_awid(),
|
||||
.m_axi_awaddr(),
|
||||
.m_axi_awlen(),
|
||||
.m_axi_awsize(),
|
||||
.m_axi_awburst(),
|
||||
.m_axi_awlock(),
|
||||
.m_axi_awcache(),
|
||||
.m_axi_awprot(),
|
||||
.m_axi_awqos(),
|
||||
.m_axi_awregion(),
|
||||
.m_axi_awuser(),
|
||||
.m_axi_awvalid(),
|
||||
.m_axi_awready(1'D0),
|
||||
.m_axi_wid(),
|
||||
.m_axi_wdata(),
|
||||
.m_axi_wstrb(),
|
||||
.m_axi_wlast(),
|
||||
.m_axi_wuser(),
|
||||
.m_axi_wvalid(),
|
||||
.m_axi_wready(1'D0),
|
||||
.m_axi_bid(1'B0),
|
||||
.m_axi_bresp(2'B0),
|
||||
.m_axi_buser(1'B0),
|
||||
.m_axi_bvalid(1'D0),
|
||||
.m_axi_bready(),
|
||||
.s_axi_arid(1'B0),
|
||||
.s_axi_araddr(32'B0),
|
||||
.s_axi_arlen(8'B0),
|
||||
.s_axi_arsize(3'B0),
|
||||
.s_axi_arburst(2'B0),
|
||||
.s_axi_arlock(1'B0),
|
||||
.s_axi_arcache(4'B0),
|
||||
.s_axi_arprot(3'B0),
|
||||
.s_axi_arqos(4'B0),
|
||||
.s_axi_arregion(4'B0),
|
||||
.s_axi_aruser(1'B0),
|
||||
.s_axi_arvalid(1'D0),
|
||||
.s_axi_arready(),
|
||||
.s_axi_rid(),
|
||||
.s_axi_rdata(),
|
||||
.s_axi_rresp(),
|
||||
.s_axi_rlast(),
|
||||
.s_axi_ruser(),
|
||||
.s_axi_rvalid(),
|
||||
.s_axi_rready(1'D0),
|
||||
.m_axi_arid(),
|
||||
.m_axi_araddr(),
|
||||
.m_axi_arlen(),
|
||||
.m_axi_arsize(),
|
||||
.m_axi_arburst(),
|
||||
.m_axi_arlock(),
|
||||
.m_axi_arcache(),
|
||||
.m_axi_arprot(),
|
||||
.m_axi_arqos(),
|
||||
.m_axi_arregion(),
|
||||
.m_axi_aruser(),
|
||||
.m_axi_arvalid(),
|
||||
.m_axi_arready(1'D0),
|
||||
.m_axi_rid(1'B0),
|
||||
.m_axi_rdata(64'B0),
|
||||
.m_axi_rresp(2'B0),
|
||||
.m_axi_rlast(1'D0),
|
||||
.m_axi_ruser(1'B0),
|
||||
.m_axi_rvalid(1'D0),
|
||||
.m_axi_rready(),
|
||||
.s_axis_tvalid(1'D0),
|
||||
.s_axis_tready(),
|
||||
.s_axis_tdata(8'B0),
|
||||
.s_axis_tstrb(1'B0),
|
||||
.s_axis_tkeep(1'B0),
|
||||
.s_axis_tlast(1'D0),
|
||||
.s_axis_tid(1'B0),
|
||||
.s_axis_tdest(1'B0),
|
||||
.s_axis_tuser(4'B0),
|
||||
.m_axis_tvalid(),
|
||||
.m_axis_tready(1'D0),
|
||||
.m_axis_tdata(),
|
||||
.m_axis_tstrb(),
|
||||
.m_axis_tkeep(),
|
||||
.m_axis_tlast(),
|
||||
.m_axis_tid(),
|
||||
.m_axis_tdest(),
|
||||
.m_axis_tuser(),
|
||||
.axi_aw_injectsbiterr(1'D0),
|
||||
.axi_aw_injectdbiterr(1'D0),
|
||||
.axi_aw_prog_full_thresh(4'B0),
|
||||
.axi_aw_prog_empty_thresh(4'B0),
|
||||
.axi_aw_data_count(),
|
||||
.axi_aw_wr_data_count(),
|
||||
.axi_aw_rd_data_count(),
|
||||
.axi_aw_sbiterr(),
|
||||
.axi_aw_dbiterr(),
|
||||
.axi_aw_overflow(),
|
||||
.axi_aw_underflow(),
|
||||
.axi_aw_prog_full(),
|
||||
.axi_aw_prog_empty(),
|
||||
.axi_w_injectsbiterr(1'D0),
|
||||
.axi_w_injectdbiterr(1'D0),
|
||||
.axi_w_prog_full_thresh(10'B0),
|
||||
.axi_w_prog_empty_thresh(10'B0),
|
||||
.axi_w_data_count(),
|
||||
.axi_w_wr_data_count(),
|
||||
.axi_w_rd_data_count(),
|
||||
.axi_w_sbiterr(),
|
||||
.axi_w_dbiterr(),
|
||||
.axi_w_overflow(),
|
||||
.axi_w_underflow(),
|
||||
.axi_w_prog_full(),
|
||||
.axi_w_prog_empty(),
|
||||
.axi_b_injectsbiterr(1'D0),
|
||||
.axi_b_injectdbiterr(1'D0),
|
||||
.axi_b_prog_full_thresh(4'B0),
|
||||
.axi_b_prog_empty_thresh(4'B0),
|
||||
.axi_b_data_count(),
|
||||
.axi_b_wr_data_count(),
|
||||
.axi_b_rd_data_count(),
|
||||
.axi_b_sbiterr(),
|
||||
.axi_b_dbiterr(),
|
||||
.axi_b_overflow(),
|
||||
.axi_b_underflow(),
|
||||
.axi_b_prog_full(),
|
||||
.axi_b_prog_empty(),
|
||||
.axi_ar_injectsbiterr(1'D0),
|
||||
.axi_ar_injectdbiterr(1'D0),
|
||||
.axi_ar_prog_full_thresh(4'B0),
|
||||
.axi_ar_prog_empty_thresh(4'B0),
|
||||
.axi_ar_data_count(),
|
||||
.axi_ar_wr_data_count(),
|
||||
.axi_ar_rd_data_count(),
|
||||
.axi_ar_sbiterr(),
|
||||
.axi_ar_dbiterr(),
|
||||
.axi_ar_overflow(),
|
||||
.axi_ar_underflow(),
|
||||
.axi_ar_prog_full(),
|
||||
.axi_ar_prog_empty(),
|
||||
.axi_r_injectsbiterr(1'D0),
|
||||
.axi_r_injectdbiterr(1'D0),
|
||||
.axi_r_prog_full_thresh(10'B0),
|
||||
.axi_r_prog_empty_thresh(10'B0),
|
||||
.axi_r_data_count(),
|
||||
.axi_r_wr_data_count(),
|
||||
.axi_r_rd_data_count(),
|
||||
.axi_r_sbiterr(),
|
||||
.axi_r_dbiterr(),
|
||||
.axi_r_overflow(),
|
||||
.axi_r_underflow(),
|
||||
.axi_r_prog_full(),
|
||||
.axi_r_prog_empty(),
|
||||
.axis_injectsbiterr(1'D0),
|
||||
.axis_injectdbiterr(1'D0),
|
||||
.axis_prog_full_thresh(10'B0),
|
||||
.axis_prog_empty_thresh(10'B0),
|
||||
.axis_data_count(),
|
||||
.axis_wr_data_count(),
|
||||
.axis_rd_data_count(),
|
||||
.axis_sbiterr(),
|
||||
.axis_dbiterr(),
|
||||
.axis_overflow(),
|
||||
.axis_underflow(),
|
||||
.axis_prog_full(),
|
||||
.axis_prog_empty()
|
||||
);
|
||||
endmodule
|
||||
@@ -55,10 +55,9 @@
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
fifo_weight_cdc your_instance_name (
|
||||
.rst(rst), // input wire rst
|
||||
.wr_clk(wr_clk), // input wire wr_clk
|
||||
.wr_rst(wr_rst), // input wire wr_rst
|
||||
.rd_clk(rd_clk), // input wire rd_clk
|
||||
.rd_rst(rd_rst), // input wire rd_rst
|
||||
.din(din), // input wire [15 : 0] din
|
||||
.wr_en(wr_en), // input wire wr_en
|
||||
.rd_en(rd_en), // input wire rd_en
|
||||
|
||||
@@ -54,10 +54,9 @@
|
||||
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
|
||||
COMPONENT fifo_weight_cdc
|
||||
PORT (
|
||||
rst : IN STD_LOGIC;
|
||||
wr_clk : IN STD_LOGIC;
|
||||
wr_rst : IN STD_LOGIC;
|
||||
rd_clk : IN STD_LOGIC;
|
||||
rd_rst : IN STD_LOGIC;
|
||||
din : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
wr_en : IN STD_LOGIC;
|
||||
rd_en : IN STD_LOGIC;
|
||||
@@ -75,10 +74,9 @@ END COMPONENT;
|
||||
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
|
||||
your_instance_name : fifo_weight_cdc
|
||||
PORT MAP (
|
||||
rst => rst,
|
||||
wr_clk => wr_clk,
|
||||
wr_rst => wr_rst,
|
||||
rd_clk => rd_clk,
|
||||
rd_rst => rd_rst,
|
||||
din => din,
|
||||
wr_en => wr_en,
|
||||
rd_en => rd_en,
|
||||
|
||||
BIN
Binary file not shown.
BIN
Binary file not shown.
@@ -1,10 +1,10 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Wed Apr 12 20:00:07 2023
|
||||
// Date : Wed Apr 19 16:13:44 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/fifo_weight_cdc_stub.v
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top fifo_weight_cdc -prefix
|
||||
// fifo_weight_cdc_ fifo_weight_cdc_stub.v
|
||||
// Design : fifo_weight_cdc
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
|
||||
@@ -14,13 +14,12 @@
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "fifo_generator_v13_2_4,Vivado 2019.1.3" *)
|
||||
module fifo_weight_cdc(wr_clk, wr_rst, rd_clk, rd_rst, din, wr_en, rd_en,
|
||||
dout, full, empty, rd_data_count)
|
||||
/* synthesis syn_black_box black_box_pad_pin="wr_clk,wr_rst,rd_clk,rd_rst,din[15:0],wr_en,rd_en,dout[15:0],full,empty,rd_data_count[4:0]" */;
|
||||
module fifo_weight_cdc(rst, wr_clk, rd_clk, din, wr_en, rd_en, dout, full,
|
||||
empty, rd_data_count)
|
||||
/* synthesis syn_black_box black_box_pad_pin="rst,wr_clk,rd_clk,din[15:0],wr_en,rd_en,dout[15:0],full,empty,rd_data_count[4:0]" */;
|
||||
input rst;
|
||||
input wr_clk;
|
||||
input wr_rst;
|
||||
input rd_clk;
|
||||
input rd_rst;
|
||||
input [15:0]din;
|
||||
input wr_en;
|
||||
input rd_en;
|
||||
|
||||
+5
-6
@@ -1,10 +1,10 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Wed Apr 12 20:00:07 2023
|
||||
-- Date : Wed Apr 19 16:13:44 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/fifo_weight_cdc_stub.vhdl
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top fifo_weight_cdc -prefix
|
||||
-- fifo_weight_cdc_ fifo_weight_cdc_stub.vhdl
|
||||
-- Design : fifo_weight_cdc
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7k410tffg900-2
|
||||
@@ -14,10 +14,9 @@ use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity fifo_weight_cdc is
|
||||
Port (
|
||||
rst : in STD_LOGIC;
|
||||
wr_clk : in STD_LOGIC;
|
||||
wr_rst : in STD_LOGIC;
|
||||
rd_clk : in STD_LOGIC;
|
||||
rd_rst : in STD_LOGIC;
|
||||
din : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
wr_en : in STD_LOGIC;
|
||||
rd_en : in STD_LOGIC;
|
||||
@@ -33,7 +32,7 @@ architecture stub of fifo_weight_cdc is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "wr_clk,wr_rst,rd_clk,rd_rst,din[15:0],wr_en,rd_en,dout[15:0],full,empty,rd_data_count[4:0]";
|
||||
attribute black_box_pad_pin of stub : architecture is "rst,wr_clk,rd_clk,din[15:0],wr_en,rd_en,dout[15:0],full,empty,rd_data_count[4:0]";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "fifo_generator_v13_2_4,Vivado 2019.1.3";
|
||||
begin
|
||||
|
||||
@@ -0,0 +1,526 @@
|
||||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:fifo_generator:13.2
|
||||
// IP Revision: 4
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module fifo_weight_cdc (
|
||||
rst,
|
||||
wr_clk,
|
||||
rd_clk,
|
||||
din,
|
||||
wr_en,
|
||||
rd_en,
|
||||
dout,
|
||||
full,
|
||||
empty,
|
||||
rd_data_count
|
||||
);
|
||||
|
||||
input wire rst;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME write_clk, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 write_clk CLK" *)
|
||||
input wire wr_clk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME read_clk, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 read_clk CLK" *)
|
||||
input wire rd_clk;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA" *)
|
||||
input wire [15 : 0] din;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN" *)
|
||||
input wire wr_en;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN" *)
|
||||
input wire rd_en;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA" *)
|
||||
output wire [15 : 0] dout;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL" *)
|
||||
output wire full;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY" *)
|
||||
output wire empty;
|
||||
output wire [4 : 0] rd_data_count;
|
||||
|
||||
fifo_generator_v13_2_4 #(
|
||||
.C_COMMON_CLOCK(0),
|
||||
.C_SELECT_XPM(0),
|
||||
.C_COUNT_TYPE(0),
|
||||
.C_DATA_COUNT_WIDTH(5),
|
||||
.C_DEFAULT_VALUE("BlankString"),
|
||||
.C_DIN_WIDTH(16),
|
||||
.C_DOUT_RST_VAL("0"),
|
||||
.C_DOUT_WIDTH(16),
|
||||
.C_ENABLE_RLOCS(0),
|
||||
.C_FAMILY("kintex7"),
|
||||
.C_FULL_FLAGS_RST_VAL(1),
|
||||
.C_HAS_ALMOST_EMPTY(0),
|
||||
.C_HAS_ALMOST_FULL(0),
|
||||
.C_HAS_BACKUP(0),
|
||||
.C_HAS_DATA_COUNT(0),
|
||||
.C_HAS_INT_CLK(0),
|
||||
.C_HAS_MEMINIT_FILE(0),
|
||||
.C_HAS_OVERFLOW(0),
|
||||
.C_HAS_RD_DATA_COUNT(1),
|
||||
.C_HAS_RD_RST(0),
|
||||
.C_HAS_RST(1),
|
||||
.C_HAS_SRST(0),
|
||||
.C_HAS_UNDERFLOW(0),
|
||||
.C_HAS_VALID(0),
|
||||
.C_HAS_WR_ACK(0),
|
||||
.C_HAS_WR_DATA_COUNT(0),
|
||||
.C_HAS_WR_RST(0),
|
||||
.C_IMPLEMENTATION_TYPE(2),
|
||||
.C_INIT_WR_PNTR_VAL(0),
|
||||
.C_MEMORY_TYPE(2),
|
||||
.C_MIF_FILE_NAME("BlankString"),
|
||||
.C_OPTIMIZATION_MODE(0),
|
||||
.C_OVERFLOW_LOW(0),
|
||||
.C_PRELOAD_LATENCY(1),
|
||||
.C_PRELOAD_REGS(0),
|
||||
.C_PRIM_FIFO_TYPE("512x36"),
|
||||
.C_PROG_EMPTY_THRESH_ASSERT_VAL(2),
|
||||
.C_PROG_EMPTY_THRESH_NEGATE_VAL(3),
|
||||
.C_PROG_EMPTY_TYPE(0),
|
||||
.C_PROG_FULL_THRESH_ASSERT_VAL(29),
|
||||
.C_PROG_FULL_THRESH_NEGATE_VAL(28),
|
||||
.C_PROG_FULL_TYPE(0),
|
||||
.C_RD_DATA_COUNT_WIDTH(5),
|
||||
.C_RD_DEPTH(32),
|
||||
.C_RD_FREQ(1),
|
||||
.C_RD_PNTR_WIDTH(5),
|
||||
.C_UNDERFLOW_LOW(0),
|
||||
.C_USE_DOUT_RST(1),
|
||||
.C_USE_ECC(0),
|
||||
.C_USE_EMBEDDED_REG(0),
|
||||
.C_USE_PIPELINE_REG(0),
|
||||
.C_POWER_SAVING_MODE(0),
|
||||
.C_USE_FIFO16_FLAGS(0),
|
||||
.C_USE_FWFT_DATA_COUNT(0),
|
||||
.C_VALID_LOW(0),
|
||||
.C_WR_ACK_LOW(0),
|
||||
.C_WR_DATA_COUNT_WIDTH(5),
|
||||
.C_WR_DEPTH(32),
|
||||
.C_WR_FREQ(1),
|
||||
.C_WR_PNTR_WIDTH(5),
|
||||
.C_WR_RESPONSE_LATENCY(1),
|
||||
.C_MSGON_VAL(1),
|
||||
.C_ENABLE_RST_SYNC(1),
|
||||
.C_EN_SAFETY_CKT(0),
|
||||
.C_ERROR_INJECTION_TYPE(0),
|
||||
.C_SYNCHRONIZER_STAGE(2),
|
||||
.C_INTERFACE_TYPE(0),
|
||||
.C_AXI_TYPE(1),
|
||||
.C_HAS_AXI_WR_CHANNEL(1),
|
||||
.C_HAS_AXI_RD_CHANNEL(1),
|
||||
.C_HAS_SLAVE_CE(0),
|
||||
.C_HAS_MASTER_CE(0),
|
||||
.C_ADD_NGC_CONSTRAINT(0),
|
||||
.C_USE_COMMON_OVERFLOW(0),
|
||||
.C_USE_COMMON_UNDERFLOW(0),
|
||||
.C_USE_DEFAULT_SETTINGS(0),
|
||||
.C_AXI_ID_WIDTH(1),
|
||||
.C_AXI_ADDR_WIDTH(32),
|
||||
.C_AXI_DATA_WIDTH(64),
|
||||
.C_AXI_LEN_WIDTH(8),
|
||||
.C_AXI_LOCK_WIDTH(1),
|
||||
.C_HAS_AXI_ID(0),
|
||||
.C_HAS_AXI_AWUSER(0),
|
||||
.C_HAS_AXI_WUSER(0),
|
||||
.C_HAS_AXI_BUSER(0),
|
||||
.C_HAS_AXI_ARUSER(0),
|
||||
.C_HAS_AXI_RUSER(0),
|
||||
.C_AXI_ARUSER_WIDTH(1),
|
||||
.C_AXI_AWUSER_WIDTH(1),
|
||||
.C_AXI_WUSER_WIDTH(1),
|
||||
.C_AXI_BUSER_WIDTH(1),
|
||||
.C_AXI_RUSER_WIDTH(1),
|
||||
.C_HAS_AXIS_TDATA(1),
|
||||
.C_HAS_AXIS_TID(0),
|
||||
.C_HAS_AXIS_TDEST(0),
|
||||
.C_HAS_AXIS_TUSER(1),
|
||||
.C_HAS_AXIS_TREADY(1),
|
||||
.C_HAS_AXIS_TLAST(0),
|
||||
.C_HAS_AXIS_TSTRB(0),
|
||||
.C_HAS_AXIS_TKEEP(0),
|
||||
.C_AXIS_TDATA_WIDTH(8),
|
||||
.C_AXIS_TID_WIDTH(1),
|
||||
.C_AXIS_TDEST_WIDTH(1),
|
||||
.C_AXIS_TUSER_WIDTH(4),
|
||||
.C_AXIS_TSTRB_WIDTH(1),
|
||||
.C_AXIS_TKEEP_WIDTH(1),
|
||||
.C_WACH_TYPE(0),
|
||||
.C_WDCH_TYPE(0),
|
||||
.C_WRCH_TYPE(0),
|
||||
.C_RACH_TYPE(0),
|
||||
.C_RDCH_TYPE(0),
|
||||
.C_AXIS_TYPE(0),
|
||||
.C_IMPLEMENTATION_TYPE_WACH(1),
|
||||
.C_IMPLEMENTATION_TYPE_WDCH(1),
|
||||
.C_IMPLEMENTATION_TYPE_WRCH(1),
|
||||
.C_IMPLEMENTATION_TYPE_RACH(1),
|
||||
.C_IMPLEMENTATION_TYPE_RDCH(1),
|
||||
.C_IMPLEMENTATION_TYPE_AXIS(1),
|
||||
.C_APPLICATION_TYPE_WACH(0),
|
||||
.C_APPLICATION_TYPE_WDCH(0),
|
||||
.C_APPLICATION_TYPE_WRCH(0),
|
||||
.C_APPLICATION_TYPE_RACH(0),
|
||||
.C_APPLICATION_TYPE_RDCH(0),
|
||||
.C_APPLICATION_TYPE_AXIS(0),
|
||||
.C_PRIM_FIFO_TYPE_WACH("512x36"),
|
||||
.C_PRIM_FIFO_TYPE_WDCH("1kx36"),
|
||||
.C_PRIM_FIFO_TYPE_WRCH("512x36"),
|
||||
.C_PRIM_FIFO_TYPE_RACH("512x36"),
|
||||
.C_PRIM_FIFO_TYPE_RDCH("1kx36"),
|
||||
.C_PRIM_FIFO_TYPE_AXIS("1kx18"),
|
||||
.C_USE_ECC_WACH(0),
|
||||
.C_USE_ECC_WDCH(0),
|
||||
.C_USE_ECC_WRCH(0),
|
||||
.C_USE_ECC_RACH(0),
|
||||
.C_USE_ECC_RDCH(0),
|
||||
.C_USE_ECC_AXIS(0),
|
||||
.C_ERROR_INJECTION_TYPE_WACH(0),
|
||||
.C_ERROR_INJECTION_TYPE_WDCH(0),
|
||||
.C_ERROR_INJECTION_TYPE_WRCH(0),
|
||||
.C_ERROR_INJECTION_TYPE_RACH(0),
|
||||
.C_ERROR_INJECTION_TYPE_RDCH(0),
|
||||
.C_ERROR_INJECTION_TYPE_AXIS(0),
|
||||
.C_DIN_WIDTH_WACH(1),
|
||||
.C_DIN_WIDTH_WDCH(64),
|
||||
.C_DIN_WIDTH_WRCH(2),
|
||||
.C_DIN_WIDTH_RACH(32),
|
||||
.C_DIN_WIDTH_RDCH(64),
|
||||
.C_DIN_WIDTH_AXIS(1),
|
||||
.C_WR_DEPTH_WACH(16),
|
||||
.C_WR_DEPTH_WDCH(1024),
|
||||
.C_WR_DEPTH_WRCH(16),
|
||||
.C_WR_DEPTH_RACH(16),
|
||||
.C_WR_DEPTH_RDCH(1024),
|
||||
.C_WR_DEPTH_AXIS(1024),
|
||||
.C_WR_PNTR_WIDTH_WACH(4),
|
||||
.C_WR_PNTR_WIDTH_WDCH(10),
|
||||
.C_WR_PNTR_WIDTH_WRCH(4),
|
||||
.C_WR_PNTR_WIDTH_RACH(4),
|
||||
.C_WR_PNTR_WIDTH_RDCH(10),
|
||||
.C_WR_PNTR_WIDTH_AXIS(10),
|
||||
.C_HAS_DATA_COUNTS_WACH(0),
|
||||
.C_HAS_DATA_COUNTS_WDCH(0),
|
||||
.C_HAS_DATA_COUNTS_WRCH(0),
|
||||
.C_HAS_DATA_COUNTS_RACH(0),
|
||||
.C_HAS_DATA_COUNTS_RDCH(0),
|
||||
.C_HAS_DATA_COUNTS_AXIS(0),
|
||||
.C_HAS_PROG_FLAGS_WACH(0),
|
||||
.C_HAS_PROG_FLAGS_WDCH(0),
|
||||
.C_HAS_PROG_FLAGS_WRCH(0),
|
||||
.C_HAS_PROG_FLAGS_RACH(0),
|
||||
.C_HAS_PROG_FLAGS_RDCH(0),
|
||||
.C_HAS_PROG_FLAGS_AXIS(0),
|
||||
.C_PROG_FULL_TYPE_WACH(0),
|
||||
.C_PROG_FULL_TYPE_WDCH(0),
|
||||
.C_PROG_FULL_TYPE_WRCH(0),
|
||||
.C_PROG_FULL_TYPE_RACH(0),
|
||||
.C_PROG_FULL_TYPE_RDCH(0),
|
||||
.C_PROG_FULL_TYPE_AXIS(0),
|
||||
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
|
||||
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
|
||||
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
|
||||
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
|
||||
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
|
||||
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
|
||||
.C_PROG_EMPTY_TYPE_WACH(0),
|
||||
.C_PROG_EMPTY_TYPE_WDCH(0),
|
||||
.C_PROG_EMPTY_TYPE_WRCH(0),
|
||||
.C_PROG_EMPTY_TYPE_RACH(0),
|
||||
.C_PROG_EMPTY_TYPE_RDCH(0),
|
||||
.C_PROG_EMPTY_TYPE_AXIS(0),
|
||||
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
|
||||
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
|
||||
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
|
||||
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
|
||||
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
|
||||
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
|
||||
.C_REG_SLICE_MODE_WACH(0),
|
||||
.C_REG_SLICE_MODE_WDCH(0),
|
||||
.C_REG_SLICE_MODE_WRCH(0),
|
||||
.C_REG_SLICE_MODE_RACH(0),
|
||||
.C_REG_SLICE_MODE_RDCH(0),
|
||||
.C_REG_SLICE_MODE_AXIS(0)
|
||||
) inst (
|
||||
.backup(1'D0),
|
||||
.backup_marker(1'D0),
|
||||
.clk(1'D0),
|
||||
.rst(rst),
|
||||
.srst(1'D0),
|
||||
.wr_clk(wr_clk),
|
||||
.wr_rst(1'D0),
|
||||
.rd_clk(rd_clk),
|
||||
.rd_rst(1'D0),
|
||||
.din(din),
|
||||
.wr_en(wr_en),
|
||||
.rd_en(rd_en),
|
||||
.prog_empty_thresh(5'B0),
|
||||
.prog_empty_thresh_assert(5'B0),
|
||||
.prog_empty_thresh_negate(5'B0),
|
||||
.prog_full_thresh(5'B0),
|
||||
.prog_full_thresh_assert(5'B0),
|
||||
.prog_full_thresh_negate(5'B0),
|
||||
.int_clk(1'D0),
|
||||
.injectdbiterr(1'D0),
|
||||
.injectsbiterr(1'D0),
|
||||
.sleep(1'D0),
|
||||
.dout(dout),
|
||||
.full(full),
|
||||
.almost_full(),
|
||||
.wr_ack(),
|
||||
.overflow(),
|
||||
.empty(empty),
|
||||
.almost_empty(),
|
||||
.valid(),
|
||||
.underflow(),
|
||||
.data_count(),
|
||||
.rd_data_count(rd_data_count),
|
||||
.wr_data_count(),
|
||||
.prog_full(),
|
||||
.prog_empty(),
|
||||
.sbiterr(),
|
||||
.dbiterr(),
|
||||
.wr_rst_busy(),
|
||||
.rd_rst_busy(),
|
||||
.m_aclk(1'D0),
|
||||
.s_aclk(1'D0),
|
||||
.s_aresetn(1'D0),
|
||||
.m_aclk_en(1'D0),
|
||||
.s_aclk_en(1'D0),
|
||||
.s_axi_awid(1'B0),
|
||||
.s_axi_awaddr(32'B0),
|
||||
.s_axi_awlen(8'B0),
|
||||
.s_axi_awsize(3'B0),
|
||||
.s_axi_awburst(2'B0),
|
||||
.s_axi_awlock(1'B0),
|
||||
.s_axi_awcache(4'B0),
|
||||
.s_axi_awprot(3'B0),
|
||||
.s_axi_awqos(4'B0),
|
||||
.s_axi_awregion(4'B0),
|
||||
.s_axi_awuser(1'B0),
|
||||
.s_axi_awvalid(1'D0),
|
||||
.s_axi_awready(),
|
||||
.s_axi_wid(1'B0),
|
||||
.s_axi_wdata(64'B0),
|
||||
.s_axi_wstrb(8'B0),
|
||||
.s_axi_wlast(1'D0),
|
||||
.s_axi_wuser(1'B0),
|
||||
.s_axi_wvalid(1'D0),
|
||||
.s_axi_wready(),
|
||||
.s_axi_bid(),
|
||||
.s_axi_bresp(),
|
||||
.s_axi_buser(),
|
||||
.s_axi_bvalid(),
|
||||
.s_axi_bready(1'D0),
|
||||
.m_axi_awid(),
|
||||
.m_axi_awaddr(),
|
||||
.m_axi_awlen(),
|
||||
.m_axi_awsize(),
|
||||
.m_axi_awburst(),
|
||||
.m_axi_awlock(),
|
||||
.m_axi_awcache(),
|
||||
.m_axi_awprot(),
|
||||
.m_axi_awqos(),
|
||||
.m_axi_awregion(),
|
||||
.m_axi_awuser(),
|
||||
.m_axi_awvalid(),
|
||||
.m_axi_awready(1'D0),
|
||||
.m_axi_wid(),
|
||||
.m_axi_wdata(),
|
||||
.m_axi_wstrb(),
|
||||
.m_axi_wlast(),
|
||||
.m_axi_wuser(),
|
||||
.m_axi_wvalid(),
|
||||
.m_axi_wready(1'D0),
|
||||
.m_axi_bid(1'B0),
|
||||
.m_axi_bresp(2'B0),
|
||||
.m_axi_buser(1'B0),
|
||||
.m_axi_bvalid(1'D0),
|
||||
.m_axi_bready(),
|
||||
.s_axi_arid(1'B0),
|
||||
.s_axi_araddr(32'B0),
|
||||
.s_axi_arlen(8'B0),
|
||||
.s_axi_arsize(3'B0),
|
||||
.s_axi_arburst(2'B0),
|
||||
.s_axi_arlock(1'B0),
|
||||
.s_axi_arcache(4'B0),
|
||||
.s_axi_arprot(3'B0),
|
||||
.s_axi_arqos(4'B0),
|
||||
.s_axi_arregion(4'B0),
|
||||
.s_axi_aruser(1'B0),
|
||||
.s_axi_arvalid(1'D0),
|
||||
.s_axi_arready(),
|
||||
.s_axi_rid(),
|
||||
.s_axi_rdata(),
|
||||
.s_axi_rresp(),
|
||||
.s_axi_rlast(),
|
||||
.s_axi_ruser(),
|
||||
.s_axi_rvalid(),
|
||||
.s_axi_rready(1'D0),
|
||||
.m_axi_arid(),
|
||||
.m_axi_araddr(),
|
||||
.m_axi_arlen(),
|
||||
.m_axi_arsize(),
|
||||
.m_axi_arburst(),
|
||||
.m_axi_arlock(),
|
||||
.m_axi_arcache(),
|
||||
.m_axi_arprot(),
|
||||
.m_axi_arqos(),
|
||||
.m_axi_arregion(),
|
||||
.m_axi_aruser(),
|
||||
.m_axi_arvalid(),
|
||||
.m_axi_arready(1'D0),
|
||||
.m_axi_rid(1'B0),
|
||||
.m_axi_rdata(64'B0),
|
||||
.m_axi_rresp(2'B0),
|
||||
.m_axi_rlast(1'D0),
|
||||
.m_axi_ruser(1'B0),
|
||||
.m_axi_rvalid(1'D0),
|
||||
.m_axi_rready(),
|
||||
.s_axis_tvalid(1'D0),
|
||||
.s_axis_tready(),
|
||||
.s_axis_tdata(8'B0),
|
||||
.s_axis_tstrb(1'B0),
|
||||
.s_axis_tkeep(1'B0),
|
||||
.s_axis_tlast(1'D0),
|
||||
.s_axis_tid(1'B0),
|
||||
.s_axis_tdest(1'B0),
|
||||
.s_axis_tuser(4'B0),
|
||||
.m_axis_tvalid(),
|
||||
.m_axis_tready(1'D0),
|
||||
.m_axis_tdata(),
|
||||
.m_axis_tstrb(),
|
||||
.m_axis_tkeep(),
|
||||
.m_axis_tlast(),
|
||||
.m_axis_tid(),
|
||||
.m_axis_tdest(),
|
||||
.m_axis_tuser(),
|
||||
.axi_aw_injectsbiterr(1'D0),
|
||||
.axi_aw_injectdbiterr(1'D0),
|
||||
.axi_aw_prog_full_thresh(4'B0),
|
||||
.axi_aw_prog_empty_thresh(4'B0),
|
||||
.axi_aw_data_count(),
|
||||
.axi_aw_wr_data_count(),
|
||||
.axi_aw_rd_data_count(),
|
||||
.axi_aw_sbiterr(),
|
||||
.axi_aw_dbiterr(),
|
||||
.axi_aw_overflow(),
|
||||
.axi_aw_underflow(),
|
||||
.axi_aw_prog_full(),
|
||||
.axi_aw_prog_empty(),
|
||||
.axi_w_injectsbiterr(1'D0),
|
||||
.axi_w_injectdbiterr(1'D0),
|
||||
.axi_w_prog_full_thresh(10'B0),
|
||||
.axi_w_prog_empty_thresh(10'B0),
|
||||
.axi_w_data_count(),
|
||||
.axi_w_wr_data_count(),
|
||||
.axi_w_rd_data_count(),
|
||||
.axi_w_sbiterr(),
|
||||
.axi_w_dbiterr(),
|
||||
.axi_w_overflow(),
|
||||
.axi_w_underflow(),
|
||||
.axi_w_prog_full(),
|
||||
.axi_w_prog_empty(),
|
||||
.axi_b_injectsbiterr(1'D0),
|
||||
.axi_b_injectdbiterr(1'D0),
|
||||
.axi_b_prog_full_thresh(4'B0),
|
||||
.axi_b_prog_empty_thresh(4'B0),
|
||||
.axi_b_data_count(),
|
||||
.axi_b_wr_data_count(),
|
||||
.axi_b_rd_data_count(),
|
||||
.axi_b_sbiterr(),
|
||||
.axi_b_dbiterr(),
|
||||
.axi_b_overflow(),
|
||||
.axi_b_underflow(),
|
||||
.axi_b_prog_full(),
|
||||
.axi_b_prog_empty(),
|
||||
.axi_ar_injectsbiterr(1'D0),
|
||||
.axi_ar_injectdbiterr(1'D0),
|
||||
.axi_ar_prog_full_thresh(4'B0),
|
||||
.axi_ar_prog_empty_thresh(4'B0),
|
||||
.axi_ar_data_count(),
|
||||
.axi_ar_wr_data_count(),
|
||||
.axi_ar_rd_data_count(),
|
||||
.axi_ar_sbiterr(),
|
||||
.axi_ar_dbiterr(),
|
||||
.axi_ar_overflow(),
|
||||
.axi_ar_underflow(),
|
||||
.axi_ar_prog_full(),
|
||||
.axi_ar_prog_empty(),
|
||||
.axi_r_injectsbiterr(1'D0),
|
||||
.axi_r_injectdbiterr(1'D0),
|
||||
.axi_r_prog_full_thresh(10'B0),
|
||||
.axi_r_prog_empty_thresh(10'B0),
|
||||
.axi_r_data_count(),
|
||||
.axi_r_wr_data_count(),
|
||||
.axi_r_rd_data_count(),
|
||||
.axi_r_sbiterr(),
|
||||
.axi_r_dbiterr(),
|
||||
.axi_r_overflow(),
|
||||
.axi_r_underflow(),
|
||||
.axi_r_prog_full(),
|
||||
.axi_r_prog_empty(),
|
||||
.axis_injectsbiterr(1'D0),
|
||||
.axis_injectdbiterr(1'D0),
|
||||
.axis_prog_full_thresh(10'B0),
|
||||
.axis_prog_empty_thresh(10'B0),
|
||||
.axis_data_count(),
|
||||
.axis_wr_data_count(),
|
||||
.axis_rd_data_count(),
|
||||
.axis_sbiterr(),
|
||||
.axis_dbiterr(),
|
||||
.axis_overflow(),
|
||||
.axis_underflow(),
|
||||
.axis_prog_full(),
|
||||
.axis_prog_empty()
|
||||
);
|
||||
endmodule
|
||||
+78
@@ -0,0 +1,78 @@
|
||||
// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
|
||||
ila_8x12_2x30_8192 your_instance_name (
|
||||
.clk(clk), // input wire clk
|
||||
|
||||
|
||||
.probe0(probe0), // input wire [11:0] probe0
|
||||
.probe1(probe1), // input wire [11:0] probe1
|
||||
.probe2(probe2), // input wire [11:0] probe2
|
||||
.probe3(probe3), // input wire [11:0] probe3
|
||||
.probe4(probe4), // input wire [11:0] probe4
|
||||
.probe5(probe5), // input wire [11:0] probe5
|
||||
.probe6(probe6), // input wire [11:0] probe6
|
||||
.probe7(probe7), // input wire [11:0] probe7
|
||||
.probe8(probe8), // input wire [29:0] probe8
|
||||
.probe9(probe9) // input wire [29:0] probe9
|
||||
);
|
||||
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
// You must compile the wrapper file ila_8x12_2x30_8192 when simulating
|
||||
// the core, ila_8x12_2x30_8192. When compiling the wrapper file, be sure to
|
||||
// reference the Verilog simulation library.
|
||||
|
||||
|
||||
LFS
BIN
Binary file not shown.
LFS
BIN
Binary file not shown.
+31
@@ -0,0 +1,31 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Wed Apr 19 13:37:44 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/ila_8x12_2x30_8192_synth_1/ila_8x12_2x30_8192_stub.v
|
||||
// Design : ila_8x12_2x30_8192
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "ila,Vivado 2019.1.3" *)
|
||||
module ila_8x12_2x30_8192(clk, probe0, probe1, probe2, probe3, probe4, probe5,
|
||||
probe6, probe7, probe8, probe9)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[11:0],probe1[11:0],probe2[11:0],probe3[11:0],probe4[11:0],probe5[11:0],probe6[11:0],probe7[11:0],probe8[29:0],probe9[29:0]" */;
|
||||
input clk;
|
||||
input [11:0]probe0;
|
||||
input [11:0]probe1;
|
||||
input [11:0]probe2;
|
||||
input [11:0]probe3;
|
||||
input [11:0]probe4;
|
||||
input [11:0]probe5;
|
||||
input [11:0]probe6;
|
||||
input [11:0]probe7;
|
||||
input [29:0]probe8;
|
||||
input [29:0]probe9;
|
||||
endmodule
|
||||
+40
@@ -0,0 +1,40 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Wed Apr 19 13:37:44 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/ila_8x12_2x30_8192_synth_1/ila_8x12_2x30_8192_stub.vhdl
|
||||
-- Design : ila_8x12_2x30_8192
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity ila_8x12_2x30_8192 is
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
probe0 : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe1 : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe2 : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe3 : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe4 : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe5 : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe6 : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe7 : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe8 : in STD_LOGIC_VECTOR ( 29 downto 0 );
|
||||
probe9 : in STD_LOGIC_VECTOR ( 29 downto 0 )
|
||||
);
|
||||
|
||||
end ila_8x12_2x30_8192;
|
||||
|
||||
architecture stub of ila_8x12_2x30_8192 is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe0[11:0],probe1[11:0],probe2[11:0],probe3[11:0],probe4[11:0],probe5[11:0],probe6[11:0],probe7[11:0],probe8[29:0],probe9[29:0]";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
+80
@@ -0,0 +1,80 @@
|
||||
// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
`timescale 1ns / 1ps
|
||||
module ila_8x12_2x30_8192 (
|
||||
clk,
|
||||
|
||||
|
||||
probe0,
|
||||
probe1,
|
||||
probe2,
|
||||
probe3,
|
||||
probe4,
|
||||
probe5,
|
||||
probe6,
|
||||
probe7,
|
||||
probe8,
|
||||
probe9
|
||||
);
|
||||
|
||||
input clk;
|
||||
|
||||
|
||||
input [11 : 0] probe0;
|
||||
input [11 : 0] probe1;
|
||||
input [11 : 0] probe2;
|
||||
input [11 : 0] probe3;
|
||||
input [11 : 0] probe4;
|
||||
input [11 : 0] probe5;
|
||||
input [11 : 0] probe6;
|
||||
input [11 : 0] probe7;
|
||||
input [29 : 0] probe8;
|
||||
input [29 : 0] probe9;
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,80 @@
|
||||
// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
|
||||
ila_rx_pre_ant your_instance_name (
|
||||
.clk(clk), // input wire clk
|
||||
|
||||
|
||||
.probe0(probe0), // input wire [0:0] probe0
|
||||
.probe1(probe1), // input wire [0:0] probe1
|
||||
.probe2(probe2), // input wire [0:0] probe2
|
||||
.probe3(probe3), // input wire [0:0] probe3
|
||||
.probe4(probe4), // input wire [0:0] probe4
|
||||
.probe5(probe5), // input wire [0:0] probe5
|
||||
.probe6(probe6), // input wire [31:0] probe6
|
||||
.probe7(probe7), // input wire [0:0] probe7
|
||||
.probe8(probe8), // input wire [4:0] probe8
|
||||
.probe9(probe9), // input wire [0:0] probe9
|
||||
.probe10(probe10), // input wire [15:0] probe10
|
||||
.probe11(probe11) // input wire [0:0] probe11
|
||||
);
|
||||
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
// You must compile the wrapper file ila_rx_pre_ant when simulating
|
||||
// the core, ila_rx_pre_ant. When compiling the wrapper file, be sure to
|
||||
// reference the Verilog simulation library.
|
||||
|
||||
|
||||
BIN
Binary file not shown.
BIN
Binary file not shown.
@@ -0,0 +1,33 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Wed Apr 19 19:15:51 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/ila_rx_pre_ant_synth_1/ila_rx_pre_ant_stub.v
|
||||
// Design : ila_rx_pre_ant
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "ila,Vivado 2019.1.3" *)
|
||||
module ila_rx_pre_ant(clk, probe0, probe1, probe2, probe3, probe4, probe5,
|
||||
probe6, probe7, probe8, probe9, probe10, probe11)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[0:0],probe1[0:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[31:0],probe7[0:0],probe8[4:0],probe9[0:0],probe10[15:0],probe11[0:0]" */;
|
||||
input clk;
|
||||
input [0:0]probe0;
|
||||
input [0:0]probe1;
|
||||
input [0:0]probe2;
|
||||
input [0:0]probe3;
|
||||
input [0:0]probe4;
|
||||
input [0:0]probe5;
|
||||
input [31:0]probe6;
|
||||
input [0:0]probe7;
|
||||
input [4:0]probe8;
|
||||
input [0:0]probe9;
|
||||
input [15:0]probe10;
|
||||
input [0:0]probe11;
|
||||
endmodule
|
||||
@@ -0,0 +1,42 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Wed Apr 19 19:15:51 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/ila_rx_pre_ant_synth_1/ila_rx_pre_ant_stub.vhdl
|
||||
-- Design : ila_rx_pre_ant
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity ila_rx_pre_ant is
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
probe0 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe1 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe2 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe3 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe4 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe5 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe6 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe7 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe8 : in STD_LOGIC_VECTOR ( 4 downto 0 );
|
||||
probe9 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe10 : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe11 : in STD_LOGIC_VECTOR ( 0 to 0 )
|
||||
);
|
||||
|
||||
end ila_rx_pre_ant;
|
||||
|
||||
architecture stub of ila_rx_pre_ant is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe0[0:0],probe1[0:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[31:0],probe7[0:0],probe8[4:0],probe9[0:0],probe10[15:0],probe11[0:0]";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
@@ -0,0 +1,84 @@
|
||||
// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
`timescale 1ns / 1ps
|
||||
module ila_rx_pre_ant (
|
||||
clk,
|
||||
|
||||
|
||||
probe0,
|
||||
probe1,
|
||||
probe2,
|
||||
probe3,
|
||||
probe4,
|
||||
probe5,
|
||||
probe6,
|
||||
probe7,
|
||||
probe8,
|
||||
probe9,
|
||||
probe10,
|
||||
probe11
|
||||
);
|
||||
|
||||
input clk;
|
||||
|
||||
|
||||
input [0 : 0] probe0;
|
||||
input [0 : 0] probe1;
|
||||
input [0 : 0] probe2;
|
||||
input [0 : 0] probe3;
|
||||
input [0 : 0] probe4;
|
||||
input [0 : 0] probe5;
|
||||
input [31 : 0] probe6;
|
||||
input [0 : 0] probe7;
|
||||
input [4 : 0] probe8;
|
||||
input [0 : 0] probe9;
|
||||
input [15 : 0] probe10;
|
||||
input [0 : 0] probe11;
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,77 @@
|
||||
// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
|
||||
ila_rx_pre_sys your_instance_name (
|
||||
.clk(clk), // input wire clk
|
||||
|
||||
|
||||
.probe0(probe0), // input wire [0:0] probe0
|
||||
.probe1(probe1), // input wire [0:0] probe1
|
||||
.probe2(probe2), // input wire [0:0] probe2
|
||||
.probe3(probe3), // input wire [31:0] probe3
|
||||
.probe4(probe4), // input wire [0:0] probe4
|
||||
.probe5(probe5), // input wire [0:0] probe5
|
||||
.probe6(probe6), // input wire [15:0] probe6
|
||||
.probe7(probe7), // input wire [0:0] probe7
|
||||
.probe8(probe8) // input wire [3:0] probe8
|
||||
);
|
||||
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
// You must compile the wrapper file ila_rx_pre_sys when simulating
|
||||
// the core, ila_rx_pre_sys. When compiling the wrapper file, be sure to
|
||||
// reference the Verilog simulation library.
|
||||
|
||||
|
||||
BIN
Binary file not shown.
BIN
Binary file not shown.
@@ -0,0 +1,30 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Wed Apr 19 19:16:16 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/ila_rx_pre_sys_synth_1/ila_rx_pre_sys_stub.v
|
||||
// Design : ila_rx_pre_sys
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "ila,Vivado 2019.1.3" *)
|
||||
module ila_rx_pre_sys(clk, probe0, probe1, probe2, probe3, probe4, probe5,
|
||||
probe6, probe7, probe8)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[0:0],probe1[0:0],probe2[0:0],probe3[31:0],probe4[0:0],probe5[0:0],probe6[15:0],probe7[0:0],probe8[3:0]" */;
|
||||
input clk;
|
||||
input [0:0]probe0;
|
||||
input [0:0]probe1;
|
||||
input [0:0]probe2;
|
||||
input [31:0]probe3;
|
||||
input [0:0]probe4;
|
||||
input [0:0]probe5;
|
||||
input [15:0]probe6;
|
||||
input [0:0]probe7;
|
||||
input [3:0]probe8;
|
||||
endmodule
|
||||
@@ -0,0 +1,39 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Wed Apr 19 19:16:16 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/ila_rx_pre_sys_synth_1/ila_rx_pre_sys_stub.vhdl
|
||||
-- Design : ila_rx_pre_sys
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity ila_rx_pre_sys is
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
probe0 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe1 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe2 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe3 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe4 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe5 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe6 : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe7 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe8 : in STD_LOGIC_VECTOR ( 3 downto 0 )
|
||||
);
|
||||
|
||||
end ila_rx_pre_sys;
|
||||
|
||||
architecture stub of ila_rx_pre_sys is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe0[0:0],probe1[0:0],probe2[0:0],probe3[31:0],probe4[0:0],probe5[0:0],probe6[15:0],probe7[0:0],probe8[3:0]";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
@@ -0,0 +1,78 @@
|
||||
// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
`timescale 1ns / 1ps
|
||||
module ila_rx_pre_sys (
|
||||
clk,
|
||||
|
||||
|
||||
probe0,
|
||||
probe1,
|
||||
probe2,
|
||||
probe3,
|
||||
probe4,
|
||||
probe5,
|
||||
probe6,
|
||||
probe7,
|
||||
probe8
|
||||
);
|
||||
|
||||
input clk;
|
||||
|
||||
|
||||
input [0 : 0] probe0;
|
||||
input [0 : 0] probe1;
|
||||
input [0 : 0] probe2;
|
||||
input [31 : 0] probe3;
|
||||
input [0 : 0] probe4;
|
||||
input [0 : 0] probe5;
|
||||
input [15 : 0] probe6;
|
||||
input [0 : 0] probe7;
|
||||
input [3 : 0] probe8;
|
||||
|
||||
|
||||
endmodule
|
||||
+283
@@ -0,0 +1,283 @@
|
||||
`pragma protect begin_protected
|
||||
`pragma protect version = 1
|
||||
`pragma protect encrypt_agent = "XILINX"
|
||||
`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2019.1"
|
||||
`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
|
||||
`pragma protect key_block
|
||||
GbQWy7xyRnDVKNEgu/syxcQSo3KIIWjSBPIwi/pSAYCe9sIQf1xA0ykhHf7s3r7GRWRS+sel+0Xx
|
||||
XWe4lBDDrw==
|
||||
|
||||
`pragma protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-2", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
|
||||
`pragma protect key_block
|
||||
rLh670IEMVEjBamdsB+LhhoxrK6I5H9wfmPCOFqaLelJt08QWbH7WNvjIhNNz7hnkT7w+wDWT6AH
|
||||
9ZJgOGPSJmj9pWoXHAojkkRBTIXpFT11+IDyFQ4FgN2TPXWILoYGY+uZG1GlGN7dsEIm5HUCUy2c
|
||||
eVhT3XSIJDvufMyiJUc=
|
||||
|
||||
`pragma protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
KgKxjU+tI9TXRZLkaaosEf4JcTfzGtF82aOinFlVe78eUyHdMvwHHcKsxUKAjkhYW491bZ0jTKit
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||||
pNc3Ov7QvW8kjTq3JHFuCf7SmCYRrmElQv0XobTk6mnMb4khaXw9wTP8YMS0XAqk3Bksal+aKfvX
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||||
LL/afyM4UwBfiIb04ZgvhdOlp/dkCqWqZyDL2qVScyGrZcDCW3CCZTVQO29hqMLZP5S82keXpBv3
|
||||
5J7nHHbQ3n4dxsRykYtJtwg7JDyqGHiwhj1HDtjhG+LX9ry1wy5YgvxrzSfKoouAeHCKXcG7TY0a
|
||||
sz4nRUsC3Yg3/CybYyPjvVJDirIzWRzSD6l1DQ==
|
||||
|
||||
`pragma protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
ItrqCM44kZl0WwWeSAjetSYD0fPwYZdVjFp5cRl5XZyoYOMWKCVEXncinM06x/MDVlkYiXgz2Xqn
|
||||
6ui7jR7RwOKALvqoqdehIoXZUA/5yPMntFpxPcFIY1DonBI4CuMjhqCuB2RkxKNIco5Z7/QxCk49
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||||
MCUlvIFRd2MXM+zvhCRdja7e9blnwJEUETukq+EKuAwuR3+VN3uzCXsNtgBqMZa2CyM6Z60fStuc
|
||||
v1eiDP/hxOimuSfsS7evakl5WMjgZuj4Jld1+y5hTOuPvw4+s3KIb2ejIH2r/I7ui7sWUZTah36a
|
||||
4QexKWP16Ghv319FCz4KExZ6lY+7HuoO55lf4A==
|
||||
|
||||
`pragma protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2019_02", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
FGUAaXx6dK7W5dgDUXY6j9xLpCHdbPvbaH+O+ozu9kcNjL5BJcGWnTdooAxaZdBsOZBvrVuXUU4v
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
|
||||
`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
|
||||
`pragma protect key_block
|
||||
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||||
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|
||||
R19uHYIhWP+7IpmjTiQ=
|
||||
|
||||
`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-2", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
|
||||
`pragma protect data_method = "AES128-CBC"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12464)
|
||||
`pragma protect data_block
|
||||
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||||
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||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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90/8XCJA0a9VcsSrh1LoO0V3YX80VWdNPY79OUOlqftl3rNXVXE=
|
||||
`pragma protect end_protected
|
||||
+1
-1
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Wed Apr 12 20:00:28 CST 2023
|
||||
# Generated by export_simulation on Wed Apr 19 17:06:59 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
+1
-1
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Wed Apr 12 20:00:28 CST 2023
|
||||
# Generated by Vivado on Wed Apr 19 17:06:59 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Wed Apr 12 20:00:28 CST 2023
|
||||
# Generated by export_simulation on Wed Apr 19 17:06:59 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
+1
-1
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Wed Apr 12 20:00:28 CST 2023
|
||||
# Generated by Vivado on Wed Apr 19 17:06:59 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
+1
-1
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Wed Apr 12 20:00:28 CST 2023
|
||||
# Generated by export_simulation on Wed Apr 19 17:06:59 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
+1
-1
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Wed Apr 12 20:00:28 CST 2023
|
||||
# Generated by Vivado on Wed Apr 19 17:06:59 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
+1
-1
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Wed Apr 12 20:00:28 CST 2023
|
||||
# Generated by export_simulation on Wed Apr 19 17:06:59 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
+1
-1
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Wed Apr 12 20:00:28 CST 2023
|
||||
# Generated by Vivado on Wed Apr 19 17:06:59 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
+1
-1
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Wed Apr 12 20:00:28 CST 2023
|
||||
# Generated by export_simulation on Wed Apr 19 17:06:59 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
+1
-1
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Wed Apr 12 20:00:28 CST 2023
|
||||
# Generated by Vivado on Wed Apr 19 17:06:59 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Wed Apr 12 20:00:28 CST 2023
|
||||
# Generated by export_simulation on Wed Apr 19 17:06:59 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
+1
-1
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Wed Apr 12 20:00:28 CST 2023
|
||||
# Generated by Vivado on Wed Apr 19 17:06:59 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
+1
-1
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Wed Apr 12 20:00:28 CST 2023
|
||||
# Generated by export_simulation on Wed Apr 19 17:06:59 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
+1
-1
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Wed Apr 12 20:00:28 CST 2023
|
||||
# Generated by Vivado on Wed Apr 19 17:06:59 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
+1
-1
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Wed Apr 12 20:00:28 CST 2023
|
||||
# Generated by export_simulation on Wed Apr 19 17:06:59 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
+1
-1
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Wed Apr 12 20:00:28 CST 2023
|
||||
# Generated by Vivado on Wed Apr 19 17:06:59 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
+1
-1
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Wed Apr 12 20:00:35 CST 2023
|
||||
# Generated by export_simulation on Wed Apr 19 16:55:15 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
+1
-1
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Wed Apr 12 20:00:35 CST 2023
|
||||
# Generated by Vivado on Wed Apr 19 16:55:15 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
+1
-1
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Wed Apr 12 20:00:35 CST 2023
|
||||
# Generated by export_simulation on Wed Apr 19 16:55:15 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
+1
-1
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Wed Apr 12 20:00:35 CST 2023
|
||||
# Generated by Vivado on Wed Apr 19 16:55:15 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
+1
-1
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Wed Apr 12 20:00:35 CST 2023
|
||||
# Generated by export_simulation on Wed Apr 19 16:55:15 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
+1
-1
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Wed Apr 12 20:00:35 CST 2023
|
||||
# Generated by Vivado on Wed Apr 19 16:55:15 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
+1
-1
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Wed Apr 12 20:00:35 CST 2023
|
||||
# Generated by export_simulation on Wed Apr 19 16:55:15 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
+1
-1
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Wed Apr 12 20:00:35 CST 2023
|
||||
# Generated by Vivado on Wed Apr 19 16:55:15 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
+1
-1
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Wed Apr 12 20:00:35 CST 2023
|
||||
# Generated by export_simulation on Wed Apr 19 16:55:15 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
+1
-1
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Wed Apr 12 20:00:35 CST 2023
|
||||
# Generated by Vivado on Wed Apr 19 16:55:15 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
+1
-1
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Wed Apr 12 20:00:35 CST 2023
|
||||
# Generated by export_simulation on Wed Apr 19 16:55:15 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
+1
-1
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Wed Apr 12 20:00:35 CST 2023
|
||||
# Generated by Vivado on Wed Apr 19 16:55:15 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
+1
-1
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Wed Apr 12 20:00:35 CST 2023
|
||||
# Generated by export_simulation on Wed Apr 19 16:55:15 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
+1
-1
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Wed Apr 12 20:00:35 CST 2023
|
||||
# Generated by Vivado on Wed Apr 19 16:55:15 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
+1
-1
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Wed Apr 12 20:00:35 CST 2023
|
||||
# Generated by export_simulation on Wed Apr 19 16:55:15 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
+1
-1
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Wed Apr 12 20:00:35 CST 2023
|
||||
# Generated by Vivado on Wed Apr 19 16:55:15 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
+49
@@ -0,0 +1,49 @@
|
||||
################################################################################
|
||||
# Vivado (TM) v2019.1.3 (64-bit)
|
||||
#
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Wed Apr 19 13:36:19 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
1. How to run the generated simulation script:-
|
||||
|
||||
From the shell prompt in the current directory, issue the following command:-
|
||||
|
||||
./ila_8x12_2x30_8192.sh
|
||||
|
||||
This command will launch the 'compile', 'elaborate' and 'simulate' functions
|
||||
implemented in the script file for the 3-step flow. These functions are called
|
||||
from the main 'run' function in the script file.
|
||||
|
||||
The 'run' function first executes the 'setup' function, the purpose of which is to
|
||||
create simulator specific setup files, create design library mappings and library
|
||||
directories and copy 'glbl.v' from the Vivado software install location into the
|
||||
current directory.
|
||||
|
||||
The 'setup' function is also used for removing the simulator generated data in
|
||||
order to reset the current directory to the original state when export_simulation
|
||||
was launched from Vivado. This generated data can be removed by specifying the
|
||||
'-reset_run' switch to the './ila_8x12_2x30_8192.sh' script.
|
||||
|
||||
./ila_8x12_2x30_8192.sh -reset_run
|
||||
|
||||
To keep the generated data from the previous run but regenerate the setup files and
|
||||
library directories, use the '-noclean_files' switch.
|
||||
|
||||
./ila_8x12_2x30_8192.sh -noclean_files
|
||||
|
||||
For more information on the script, please type './ila_8x12_2x30_8192.sh -help'.
|
||||
|
||||
2. Additional design information files:-
|
||||
|
||||
export_simulation generates following additional file that can be used for fetching
|
||||
the design files information or for integrating with external custom scripts.
|
||||
|
||||
Name : file_info.txt
|
||||
Purpose: This file contains detail design file information based on the compile order
|
||||
when export_simulation was executed from Vivado. The file contains information
|
||||
about the file type, name, whether it is part of the IP, associated library
|
||||
and the file path information.
|
||||
+22
@@ -0,0 +1,22 @@
|
||||
vlib work
|
||||
vlib activehdl
|
||||
|
||||
vlib activehdl/xil_defaultlib
|
||||
vlib activehdl/xpm
|
||||
|
||||
vmap xil_defaultlib activehdl/xil_defaultlib
|
||||
vmap xpm activehdl/xpm
|
||||
|
||||
vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ip/ila_8x12_2x30_8192/hdl/verilog" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
|
||||
vcom -work xpm -93 \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
|
||||
vlog -work xil_defaultlib -v2k5 "+incdir+../../../ip/ila_8x12_2x30_8192/hdl/verilog" \
|
||||
"../../../ip/ila_8x12_2x30_8192/sim/ila_8x12_2x30_8192.v" \
|
||||
|
||||
vlog -work xil_defaultlib \
|
||||
"glbl.v"
|
||||
|
||||
+5
@@ -0,0 +1,5 @@
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_8x12_2x30_8192/hdl/verilog"
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_8x12_2x30_8192/hdl/verilog"
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_8x12_2x30_8192/hdl/verilog"
|
||||
ila_8x12_2x30_8192.v,verilog,xil_defaultlib,../../../ip/ila_8x12_2x30_8192/sim/ila_8x12_2x30_8192.v,incdir="../../../ip/ila_8x12_2x30_8192/hdl/verilog"
|
||||
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||
+152
@@ -0,0 +1,152 @@
|
||||
#!/bin/bash -f
|
||||
#*********************************************************************************************************
|
||||
# Vivado (TM) v2019.1.3 (64-bit)
|
||||
#
|
||||
# Filename : ila_8x12_2x30_8192.sh
|
||||
# Simulator : Aldec Active-HDL Simulator
|
||||
# Description : Simulation script for compiling, elaborating and verifying the project source files.
|
||||
# The script will automatically create the design libraries sub-directories in the run
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Wed Apr 19 13:36:19 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
# usage: ila_8x12_2x30_8192.sh [-help]
|
||||
# usage: ila_8x12_2x30_8192.sh [-lib_map_path]
|
||||
# usage: ila_8x12_2x30_8192.sh [-noclean_files]
|
||||
# usage: ila_8x12_2x30_8192.sh [-reset_run]
|
||||
#
|
||||
# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
|
||||
# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
|
||||
# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
|
||||
# that points to these libraries and rerun export_simulation. For more information about this switch please
|
||||
# type 'export_simulation -help' in the Tcl shell.
|
||||
#
|
||||
# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
|
||||
# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
|
||||
# executing this script. Please type 'ila_8x12_2x30_8192.sh -help' for more information.
|
||||
#
|
||||
# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
|
||||
#
|
||||
#*********************************************************************************************************
|
||||
|
||||
|
||||
# Script info
|
||||
echo -e "ila_8x12_2x30_8192.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
|
||||
|
||||
# Main steps
|
||||
run()
|
||||
{
|
||||
check_args $# $1
|
||||
setup $1 $2
|
||||
compile
|
||||
simulate
|
||||
}
|
||||
|
||||
# RUN_STEP: <compile>
|
||||
compile()
|
||||
{
|
||||
# Compile design files
|
||||
source compile.do 2>&1 | tee -a compile.log
|
||||
|
||||
}
|
||||
|
||||
# RUN_STEP: <simulate>
|
||||
simulate()
|
||||
{
|
||||
runvsimsa -l simulate.log -do "do {simulate.do}"
|
||||
}
|
||||
|
||||
# STEP: setup
|
||||
setup()
|
||||
{
|
||||
case $1 in
|
||||
"-lib_map_path" )
|
||||
if [[ ($2 == "") ]]; then
|
||||
echo -e "ERROR: Simulation library directory path not specified (type \"./ila_8x12_2x30_8192.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
map_setup_file $2
|
||||
;;
|
||||
"-reset_run" )
|
||||
reset_run
|
||||
echo -e "INFO: Simulation run files deleted.\n"
|
||||
exit 0
|
||||
;;
|
||||
"-noclean_files" )
|
||||
# do not remove previous data
|
||||
;;
|
||||
* )
|
||||
map_setup_file $2
|
||||
esac
|
||||
|
||||
# Add any setup/initialization commands here:-
|
||||
|
||||
# <user specific commands>
|
||||
|
||||
}
|
||||
|
||||
# Map library.cfg file
|
||||
map_setup_file()
|
||||
{
|
||||
file="library.cfg"
|
||||
lib_map_path=""
|
||||
if [[ ($1 != "") ]]; then
|
||||
lib_map_path="$1"
|
||||
fi
|
||||
if [[ ($lib_map_path != "") ]]; then
|
||||
src_file="$lib_map_path/$file"
|
||||
if [[ -e $src_file ]]; then
|
||||
vmap -link $lib_map_path
|
||||
fi
|
||||
fi
|
||||
}
|
||||
|
||||
# Delete generated data from the previous run
|
||||
reset_run()
|
||||
{
|
||||
files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl)
|
||||
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
|
||||
file="${files_to_remove[i]}"
|
||||
if [[ -e $file ]]; then
|
||||
rm -rf $file
|
||||
fi
|
||||
done
|
||||
}
|
||||
|
||||
# Check command line arguments
|
||||
check_args()
|
||||
{
|
||||
if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
|
||||
echo -e "ERROR: Unknown option specified '$2' (type \"./ila_8x12_2x30_8192.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
|
||||
if [[ ($2 == "-help" || $2 == "-h") ]]; then
|
||||
usage
|
||||
fi
|
||||
}
|
||||
|
||||
# Script usage
|
||||
usage()
|
||||
{
|
||||
msg="Usage: ila_8x12_2x30_8192.sh [-help]\n\
|
||||
Usage: ila_8x12_2x30_8192.sh [-lib_map_path]\n\
|
||||
Usage: ila_8x12_2x30_8192.sh [-reset_run]\n\
|
||||
Usage: ila_8x12_2x30_8192.sh [-noclean_files]\n\n\
|
||||
[-help] -- Print help information for this script\n\n\
|
||||
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
|
||||
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
|
||||
[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
|
||||
from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
|
||||
-noclean_files switch.\n\n\
|
||||
[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
|
||||
echo -e $msg
|
||||
exit 1
|
||||
}
|
||||
|
||||
# Launch script
|
||||
run $1 $2
|
||||
+17
@@ -0,0 +1,17 @@
|
||||
onbreak {quit -force}
|
||||
onerror {quit -force}
|
||||
|
||||
asim -t 1ps +access +r +m+ila_8x12_2x30_8192 -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.ila_8x12_2x30_8192 xil_defaultlib.glbl
|
||||
|
||||
do {wave.do}
|
||||
|
||||
view wave
|
||||
view structure
|
||||
|
||||
do {ila_8x12_2x30_8192.udo}
|
||||
|
||||
run -all
|
||||
|
||||
endsim
|
||||
|
||||
quit -force
|
||||
+48
@@ -0,0 +1,48 @@
|
||||
################################################################################
|
||||
# Vivado (TM) v2019.1.3 (64-bit)
|
||||
#
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Wed Apr 19 13:36:19 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
1. How to run the generated simulation script:-
|
||||
|
||||
From the shell prompt in the current directory, issue the following command:-
|
||||
|
||||
./ila_8x12_2x30_8192.sh
|
||||
|
||||
This command will launch the 'execute' function for the single-step flow. This
|
||||
function is called from the main 'run' function in the script file.
|
||||
|
||||
The 'run' function first executes the 'setup' function, the purpose of which is to
|
||||
create simulator specific setup files, create design library mappings and library
|
||||
directories and copy 'glbl.v' from the Vivado software install location into the
|
||||
current directory.
|
||||
|
||||
The 'setup' function is also used for removing the simulator generated data in
|
||||
order to reset the current directory to the original state when export_simulation
|
||||
was launched from Vivado. This generated data can be removed by specifying the
|
||||
'-reset_run' switch to the './ila_8x12_2x30_8192.sh' script.
|
||||
|
||||
./ila_8x12_2x30_8192.sh -reset_run
|
||||
|
||||
To keep the generated data from the previous run but regenerate the setup files and
|
||||
library directories, use the '-noclean_files' switch.
|
||||
|
||||
./ila_8x12_2x30_8192.sh -noclean_files
|
||||
|
||||
For more information on the script, please type './ila_8x12_2x30_8192.sh -help'.
|
||||
|
||||
2. Additional design information files:-
|
||||
|
||||
export_simulation generates following additional file that can be used for fetching
|
||||
the design files information or for integrating with external custom scripts.
|
||||
|
||||
Name : file_info.txt
|
||||
Purpose: This file contains detail design file information based on the compile order
|
||||
when export_simulation was executed from Vivado. The file contains information
|
||||
about the file type, name, whether it is part of the IP, associated library
|
||||
and the file path information.
|
||||
+5
@@ -0,0 +1,5 @@
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_8x12_2x30_8192/hdl/verilog"
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_8x12_2x30_8192/hdl/verilog"
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_8x12_2x30_8192/hdl/verilog"
|
||||
ila_8x12_2x30_8192.v,verilog,xil_defaultlib,../../../ip/ila_8x12_2x30_8192/sim/ila_8x12_2x30_8192.v,incdir="../../../ip/ila_8x12_2x30_8192/hdl/verilog"
|
||||
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||
Executable
+176
@@ -0,0 +1,176 @@
|
||||
#!/bin/bash -f
|
||||
#*********************************************************************************************************
|
||||
# Vivado (TM) v2019.1.3 (64-bit)
|
||||
#
|
||||
# Filename : ila_8x12_2x30_8192.sh
|
||||
# Simulator : Cadence Incisive Enterprise Simulator
|
||||
# Description : Simulation script for compiling, elaborating and verifying the project source files.
|
||||
# The script will automatically create the design libraries sub-directories in the run
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Wed Apr 19 13:36:19 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
# usage: ila_8x12_2x30_8192.sh [-help]
|
||||
# usage: ila_8x12_2x30_8192.sh [-lib_map_path]
|
||||
# usage: ila_8x12_2x30_8192.sh [-noclean_files]
|
||||
# usage: ila_8x12_2x30_8192.sh [-reset_run]
|
||||
#
|
||||
# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
|
||||
# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
|
||||
# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
|
||||
# that points to these libraries and rerun export_simulation. For more information about this switch please
|
||||
# type 'export_simulation -help' in the Tcl shell.
|
||||
#
|
||||
# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
|
||||
# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
|
||||
# executing this script. Please type 'ila_8x12_2x30_8192.sh -help' for more information.
|
||||
#
|
||||
# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
|
||||
#
|
||||
#*********************************************************************************************************
|
||||
|
||||
# Directory path for design sources and include directories (if any) wrt this path
|
||||
ref_dir="."
|
||||
|
||||
# Override directory with 'export_sim_ref_dir' env path value if set in the shell
|
||||
if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
|
||||
ref_dir="$export_sim_ref_dir"
|
||||
fi
|
||||
|
||||
# Set the compiled library directory
|
||||
ref_lib_dir="."
|
||||
|
||||
# Command line options
|
||||
irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen"
|
||||
|
||||
# Design libraries
|
||||
design_libs=(xil_defaultlib xpm)
|
||||
|
||||
# Simulation root library directory
|
||||
sim_lib_dir="ies_lib"
|
||||
|
||||
# Script info
|
||||
echo -e "ila_8x12_2x30_8192.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
|
||||
|
||||
# Main steps
|
||||
run()
|
||||
{
|
||||
check_args $# $1
|
||||
setup $1 $2
|
||||
execute
|
||||
}
|
||||
|
||||
# RUN_STEP: <execute>
|
||||
execute()
|
||||
{
|
||||
irun $irun_opts \
|
||||
-reflib "$ref_lib_dir/unisim:unisim" \
|
||||
-reflib "$ref_lib_dir/unisims_ver:unisims_ver" \
|
||||
-reflib "$ref_lib_dir/secureip:secureip" \
|
||||
-reflib "$ref_lib_dir/unimacro:unimacro" \
|
||||
-reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \
|
||||
-top xil_defaultlib.ila_8x12_2x30_8192 \
|
||||
-f run.f \
|
||||
-top glbl \
|
||||
glbl.v \
|
||||
+incdir+"../../../ip/ila_8x12_2x30_8192/hdl/verilog"
|
||||
}
|
||||
|
||||
# STEP: setup
|
||||
setup()
|
||||
{
|
||||
case $1 in
|
||||
"-lib_map_path" )
|
||||
if [[ ($2 == "") ]]; then
|
||||
echo -e "ERROR: Simulation library directory path not specified (type \"./ila_8x12_2x30_8192.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
else
|
||||
ref_lib_dir=$2
|
||||
fi
|
||||
;;
|
||||
"-reset_run" )
|
||||
reset_run
|
||||
echo -e "INFO: Simulation run files deleted.\n"
|
||||
exit 0
|
||||
;;
|
||||
"-noclean_files" )
|
||||
# do not remove previous data
|
||||
;;
|
||||
* )
|
||||
esac
|
||||
|
||||
create_lib_dir
|
||||
|
||||
# Add any setup/initialization commands here:-
|
||||
|
||||
# <user specific commands>
|
||||
|
||||
}
|
||||
|
||||
# Create design library directory paths
|
||||
create_lib_dir()
|
||||
{
|
||||
if [[ -e $sim_lib_dir ]]; then
|
||||
rm -rf $sim_lib_dir
|
||||
fi
|
||||
|
||||
for (( i=0; i<${#design_libs[*]}; i++ )); do
|
||||
lib="${design_libs[i]}"
|
||||
lib_dir="$sim_lib_dir/$lib"
|
||||
if [[ ! -e $lib_dir ]]; then
|
||||
mkdir -p $lib_dir
|
||||
fi
|
||||
done
|
||||
}
|
||||
|
||||
# Delete generated data from the previous run
|
||||
reset_run()
|
||||
{
|
||||
files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs)
|
||||
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
|
||||
file="${files_to_remove[i]}"
|
||||
if [[ -e $file ]]; then
|
||||
rm -rf $file
|
||||
fi
|
||||
done
|
||||
|
||||
create_lib_dir
|
||||
}
|
||||
|
||||
# Check command line arguments
|
||||
check_args()
|
||||
{
|
||||
if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
|
||||
echo -e "ERROR: Unknown option specified '$2' (type \"./ila_8x12_2x30_8192.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
|
||||
if [[ ($2 == "-help" || $2 == "-h") ]]; then
|
||||
usage
|
||||
fi
|
||||
}
|
||||
|
||||
# Script usage
|
||||
usage()
|
||||
{
|
||||
msg="Usage: ila_8x12_2x30_8192.sh [-help]\n\
|
||||
Usage: ila_8x12_2x30_8192.sh [-lib_map_path]\n\
|
||||
Usage: ila_8x12_2x30_8192.sh [-reset_run]\n\
|
||||
Usage: ila_8x12_2x30_8192.sh [-noclean_files]\n\n\
|
||||
[-help] -- Print help information for this script\n\n\
|
||||
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
|
||||
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
|
||||
[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
|
||||
from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
|
||||
-noclean_files switch.\n\n\
|
||||
[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
|
||||
echo -e $msg
|
||||
exit 1
|
||||
}
|
||||
|
||||
# Launch script
|
||||
run $1 $2
|
||||
@@ -0,0 +1,14 @@
|
||||
-makelib ies_lib/xil_defaultlib -sv \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
-endlib
|
||||
-makelib ies_lib/xpm \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
-endlib
|
||||
-makelib ies_lib/xil_defaultlib \
|
||||
"../../../ip/ila_8x12_2x30_8192/sim/ila_8x12_2x30_8192.v" \
|
||||
-endlib
|
||||
-makelib ies_lib/xil_defaultlib \
|
||||
glbl.v
|
||||
-endlib
|
||||
|
||||
+49
@@ -0,0 +1,49 @@
|
||||
################################################################################
|
||||
# Vivado (TM) v2019.1.3 (64-bit)
|
||||
#
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Wed Apr 19 13:36:19 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
1. How to run the generated simulation script:-
|
||||
|
||||
From the shell prompt in the current directory, issue the following command:-
|
||||
|
||||
./ila_8x12_2x30_8192.sh
|
||||
|
||||
This command will launch the 'compile', 'elaborate' and 'simulate' functions
|
||||
implemented in the script file for the 3-step flow. These functions are called
|
||||
from the main 'run' function in the script file.
|
||||
|
||||
The 'run' function first executes the 'setup' function, the purpose of which is to
|
||||
create simulator specific setup files, create design library mappings and library
|
||||
directories and copy 'glbl.v' from the Vivado software install location into the
|
||||
current directory.
|
||||
|
||||
The 'setup' function is also used for removing the simulator generated data in
|
||||
order to reset the current directory to the original state when export_simulation
|
||||
was launched from Vivado. This generated data can be removed by specifying the
|
||||
'-reset_run' switch to the './ila_8x12_2x30_8192.sh' script.
|
||||
|
||||
./ila_8x12_2x30_8192.sh -reset_run
|
||||
|
||||
To keep the generated data from the previous run but regenerate the setup files and
|
||||
library directories, use the '-noclean_files' switch.
|
||||
|
||||
./ila_8x12_2x30_8192.sh -noclean_files
|
||||
|
||||
For more information on the script, please type './ila_8x12_2x30_8192.sh -help'.
|
||||
|
||||
2. Additional design information files:-
|
||||
|
||||
export_simulation generates following additional file that can be used for fetching
|
||||
the design files information or for integrating with external custom scripts.
|
||||
|
||||
Name : file_info.txt
|
||||
Purpose: This file contains detail design file information based on the compile order
|
||||
when export_simulation was executed from Vivado. The file contains information
|
||||
about the file type, name, whether it is part of the IP, associated library
|
||||
and the file path information.
|
||||
+22
@@ -0,0 +1,22 @@
|
||||
vlib modelsim_lib/work
|
||||
vlib modelsim_lib/msim
|
||||
|
||||
vlib modelsim_lib/msim/xil_defaultlib
|
||||
vlib modelsim_lib/msim/xpm
|
||||
|
||||
vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib
|
||||
vmap xpm modelsim_lib/msim/xpm
|
||||
|
||||
vlog -work xil_defaultlib -64 -incr -sv "+incdir+../../../ip/ila_8x12_2x30_8192/hdl/verilog" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
|
||||
vcom -work xpm -64 -93 \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
|
||||
vlog -work xil_defaultlib -64 -incr "+incdir+../../../ip/ila_8x12_2x30_8192/hdl/verilog" \
|
||||
"../../../ip/ila_8x12_2x30_8192/sim/ila_8x12_2x30_8192.v" \
|
||||
|
||||
vlog -work xil_defaultlib \
|
||||
"glbl.v"
|
||||
|
||||
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Reference in New Issue
Block a user