diff --git a/projects/dl814_dj/dl814_dj_48m/ip/coe/freq_word.coe b/projects/dl814_dj/dl814_dj_48m/ip/coe/freq_word.coe new file mode 100644 index 00000000..590747a4 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/coe/freq_word.coe @@ -0,0 +1,83 @@ +MEMORY_INITIALIZATION_RADIX = 10; +MEMORY_INITIALIZATION_VECTOR = +1624, +1611, +1598, +1585, +1572, +1559, +1546, +1533, +1520, +1507, +1494, +1481, +1468, +1455, +1442, +1429, +1416, +1403, +1390, +1377, +1364, +1351, +1338, +1325, +1312, +1299, +1286, +1273, +1260, +1247, +1234, +1221, +1208, +1195, +1182, +1169, +1156, +1143, +1130, +1117, +1104, +1091, +1078, +1065, +1052, +1039, +1026, +1013, +1000, +987, +974, +961, +948, +935, +922, +909, +896, +883, +870, +857, +844, +831, +818, +805, +792, +779, +766, +753, +740, +727, +714, +701, +688, +675, +662, +649, +636, +623, +610, +597, +584, diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/fifo_48m_to_122p88m/fifo_48m_to_122p88m_sim_netlist.v b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/fifo_48m_to_122p88m/fifo_48m_to_122p88m_sim_netlist.v deleted file mode 100644 index 1c3d8a4a..00000000 --- a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/fifo_48m_to_122p88m/fifo_48m_to_122p88m_sim_netlist.v +++ /dev/null @@ -1,3 +0,0 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:61f26df1ca43806108e513a9c986f3edf71deb5e2fd1465819442f731a2b8fd2 -size 126640 diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/fifo_48m_to_122p88m/fifo_48m_to_122p88m_sim_netlist.vhdl b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/fifo_48m_to_122p88m/fifo_48m_to_122p88m_sim_netlist.vhdl deleted file mode 100644 index f84d08a8..00000000 --- a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/fifo_48m_to_122p88m/fifo_48m_to_122p88m_sim_netlist.vhdl +++ /dev/null @@ -1,3 +0,0 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:6e5544b6ae2c0b5cc930ef5d33dea2559555f41791ba2caecbf5ee13ac404ee0 -size 192057 diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/fifo_48m_to_122p88m/sim/fifo_48m_to_122p88m.v b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/fifo_48m_to_122p88m/sim/fifo_48m_to_122p88m.v deleted file mode 100644 index 06c8b355..00000000 --- a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/fifo_48m_to_122p88m/sim/fifo_48m_to_122p88m.v +++ /dev/null @@ -1,532 +0,0 @@ -// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -// DO NOT MODIFY THIS FILE. - - -// IP VLNV: xilinx.com:ip:fifo_generator:13.2 -// IP Revision: 4 - -`timescale 1ns/1ps - -(* DowngradeIPIdentifiedWarnings = "yes" *) -module fifo_48m_to_122p88m ( - wr_rst_busy, - rd_rst_busy, - m_aclk, - s_aclk, - s_aresetn, - s_axis_tvalid, - s_axis_tready, - s_axis_tdata, - m_axis_tvalid, - m_axis_tready, - m_axis_tdata -); - -output wire wr_rst_busy; -output wire rd_rst_busy; -(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME master_aclk, ASSOCIATED_BUSIF M_AXIS:M_AXI, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0" *) -(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 master_aclk CLK" *) -input wire m_aclk; -(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME slave_aclk, ASSOCIATED_BUSIF S_AXIS:S_AXI, ASSOCIATED_RESET s_aresetn, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0" *) -(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 slave_aclk CLK" *) -input wire s_aclk; -(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME slave_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) -(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 slave_aresetn RST" *) -input wire s_aresetn; -(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *) -input wire s_axis_tvalid; -(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *) -output wire s_axis_tready; -(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0" *) -(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TDATA" *) -input wire [15 : 0] s_axis_tdata; -(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TVALID" *) -output wire m_axis_tvalid; -(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TREADY" *) -input wire m_axis_tready; -(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0" *) -(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TDATA" *) -output wire [15 : 0] m_axis_tdata; - - fifo_generator_v13_2_4 #( - .C_COMMON_CLOCK(0), - .C_SELECT_XPM(0), - .C_COUNT_TYPE(0), - .C_DATA_COUNT_WIDTH(10), - .C_DEFAULT_VALUE("BlankString"), - .C_DIN_WIDTH(18), - .C_DOUT_RST_VAL("0"), - .C_DOUT_WIDTH(18), - .C_ENABLE_RLOCS(0), - .C_FAMILY("zynq"), - .C_FULL_FLAGS_RST_VAL(1), - .C_HAS_ALMOST_EMPTY(0), - .C_HAS_ALMOST_FULL(0), - .C_HAS_BACKUP(0), - .C_HAS_DATA_COUNT(0), - .C_HAS_INT_CLK(0), - .C_HAS_MEMINIT_FILE(0), - .C_HAS_OVERFLOW(0), - .C_HAS_RD_DATA_COUNT(0), - .C_HAS_RD_RST(0), - .C_HAS_RST(1), - .C_HAS_SRST(0), - .C_HAS_UNDERFLOW(0), - .C_HAS_VALID(0), - .C_HAS_WR_ACK(0), - .C_HAS_WR_DATA_COUNT(0), - .C_HAS_WR_RST(0), - .C_IMPLEMENTATION_TYPE(0), - .C_INIT_WR_PNTR_VAL(0), - .C_MEMORY_TYPE(1), - .C_MIF_FILE_NAME("BlankString"), - .C_OPTIMIZATION_MODE(0), - .C_OVERFLOW_LOW(0), - .C_PRELOAD_LATENCY(1), - .C_PRELOAD_REGS(0), - .C_PRIM_FIFO_TYPE("4kx4"), - .C_PROG_EMPTY_THRESH_ASSERT_VAL(2), - .C_PROG_EMPTY_THRESH_NEGATE_VAL(3), - .C_PROG_EMPTY_TYPE(0), - .C_PROG_FULL_THRESH_ASSERT_VAL(1022), - .C_PROG_FULL_THRESH_NEGATE_VAL(1021), - .C_PROG_FULL_TYPE(0), - .C_RD_DATA_COUNT_WIDTH(10), - .C_RD_DEPTH(1024), - .C_RD_FREQ(1), - .C_RD_PNTR_WIDTH(10), - .C_UNDERFLOW_LOW(0), - .C_USE_DOUT_RST(1), - .C_USE_ECC(0), - .C_USE_EMBEDDED_REG(0), - .C_USE_PIPELINE_REG(0), - .C_POWER_SAVING_MODE(0), - .C_USE_FIFO16_FLAGS(0), - .C_USE_FWFT_DATA_COUNT(0), - .C_VALID_LOW(0), - .C_WR_ACK_LOW(0), - .C_WR_DATA_COUNT_WIDTH(10), - .C_WR_DEPTH(1024), - .C_WR_FREQ(1), - .C_WR_PNTR_WIDTH(10), - .C_WR_RESPONSE_LATENCY(1), - .C_MSGON_VAL(1), - .C_ENABLE_RST_SYNC(1), - .C_EN_SAFETY_CKT(1), - .C_ERROR_INJECTION_TYPE(0), - .C_SYNCHRONIZER_STAGE(2), - .C_INTERFACE_TYPE(1), - .C_AXI_TYPE(1), - .C_HAS_AXI_WR_CHANNEL(1), - .C_HAS_AXI_RD_CHANNEL(1), - .C_HAS_SLAVE_CE(0), - .C_HAS_MASTER_CE(0), - .C_ADD_NGC_CONSTRAINT(0), - .C_USE_COMMON_OVERFLOW(0), - .C_USE_COMMON_UNDERFLOW(0), - .C_USE_DEFAULT_SETTINGS(0), - .C_AXI_ID_WIDTH(1), - .C_AXI_ADDR_WIDTH(32), - .C_AXI_DATA_WIDTH(64), - .C_AXI_LEN_WIDTH(8), - .C_AXI_LOCK_WIDTH(1), - .C_HAS_AXI_ID(0), - .C_HAS_AXI_AWUSER(0), - .C_HAS_AXI_WUSER(0), - .C_HAS_AXI_BUSER(0), - .C_HAS_AXI_ARUSER(0), - .C_HAS_AXI_RUSER(0), - .C_AXI_ARUSER_WIDTH(1), - .C_AXI_AWUSER_WIDTH(1), - .C_AXI_WUSER_WIDTH(1), - .C_AXI_BUSER_WIDTH(1), - .C_AXI_RUSER_WIDTH(1), - .C_HAS_AXIS_TDATA(1), - .C_HAS_AXIS_TID(0), - .C_HAS_AXIS_TDEST(0), - .C_HAS_AXIS_TUSER(0), - .C_HAS_AXIS_TREADY(1), - .C_HAS_AXIS_TLAST(0), - .C_HAS_AXIS_TSTRB(0), - .C_HAS_AXIS_TKEEP(0), - .C_AXIS_TDATA_WIDTH(16), - .C_AXIS_TID_WIDTH(1), - .C_AXIS_TDEST_WIDTH(1), - .C_AXIS_TUSER_WIDTH(1), - .C_AXIS_TSTRB_WIDTH(2), - .C_AXIS_TKEEP_WIDTH(2), - .C_WACH_TYPE(0), - .C_WDCH_TYPE(0), - .C_WRCH_TYPE(0), - .C_RACH_TYPE(0), - .C_RDCH_TYPE(0), - .C_AXIS_TYPE(0), - .C_IMPLEMENTATION_TYPE_WACH(12), - .C_IMPLEMENTATION_TYPE_WDCH(11), - .C_IMPLEMENTATION_TYPE_WRCH(12), - .C_IMPLEMENTATION_TYPE_RACH(12), - .C_IMPLEMENTATION_TYPE_RDCH(11), - .C_IMPLEMENTATION_TYPE_AXIS(12), - .C_APPLICATION_TYPE_WACH(0), - .C_APPLICATION_TYPE_WDCH(0), - .C_APPLICATION_TYPE_WRCH(0), - .C_APPLICATION_TYPE_RACH(0), - .C_APPLICATION_TYPE_RDCH(0), - .C_APPLICATION_TYPE_AXIS(0), - .C_PRIM_FIFO_TYPE_WACH("512x36"), - .C_PRIM_FIFO_TYPE_WDCH("1kx36"), - .C_PRIM_FIFO_TYPE_WRCH("512x36"), - .C_PRIM_FIFO_TYPE_RACH("512x36"), - .C_PRIM_FIFO_TYPE_RDCH("1kx36"), - .C_PRIM_FIFO_TYPE_AXIS("512x36"), - .C_USE_ECC_WACH(0), - .C_USE_ECC_WDCH(0), - .C_USE_ECC_WRCH(0), - .C_USE_ECC_RACH(0), - .C_USE_ECC_RDCH(0), - .C_USE_ECC_AXIS(0), - .C_ERROR_INJECTION_TYPE_WACH(0), - .C_ERROR_INJECTION_TYPE_WDCH(0), - .C_ERROR_INJECTION_TYPE_WRCH(0), - .C_ERROR_INJECTION_TYPE_RACH(0), - .C_ERROR_INJECTION_TYPE_RDCH(0), - .C_ERROR_INJECTION_TYPE_AXIS(0), - .C_DIN_WIDTH_WACH(32), - .C_DIN_WIDTH_WDCH(64), - .C_DIN_WIDTH_WRCH(2), - .C_DIN_WIDTH_RACH(32), - .C_DIN_WIDTH_RDCH(64), - .C_DIN_WIDTH_AXIS(16), - .C_WR_DEPTH_WACH(16), - .C_WR_DEPTH_WDCH(1024), - .C_WR_DEPTH_WRCH(16), - .C_WR_DEPTH_RACH(16), - .C_WR_DEPTH_RDCH(1024), - .C_WR_DEPTH_AXIS(16), - .C_WR_PNTR_WIDTH_WACH(4), - .C_WR_PNTR_WIDTH_WDCH(10), - .C_WR_PNTR_WIDTH_WRCH(4), - .C_WR_PNTR_WIDTH_RACH(4), - .C_WR_PNTR_WIDTH_RDCH(10), - .C_WR_PNTR_WIDTH_AXIS(4), - .C_HAS_DATA_COUNTS_WACH(0), - .C_HAS_DATA_COUNTS_WDCH(0), - .C_HAS_DATA_COUNTS_WRCH(0), - .C_HAS_DATA_COUNTS_RACH(0), - .C_HAS_DATA_COUNTS_RDCH(0), - .C_HAS_DATA_COUNTS_AXIS(0), - .C_HAS_PROG_FLAGS_WACH(0), - .C_HAS_PROG_FLAGS_WDCH(0), - .C_HAS_PROG_FLAGS_WRCH(0), - .C_HAS_PROG_FLAGS_RACH(0), - .C_HAS_PROG_FLAGS_RDCH(0), - .C_HAS_PROG_FLAGS_AXIS(0), - .C_PROG_FULL_TYPE_WACH(0), - .C_PROG_FULL_TYPE_WDCH(0), - .C_PROG_FULL_TYPE_WRCH(0), - .C_PROG_FULL_TYPE_RACH(0), - .C_PROG_FULL_TYPE_RDCH(0), - .C_PROG_FULL_TYPE_AXIS(0), - .C_PROG_FULL_THRESH_ASSERT_VAL_WACH(15), - .C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023), - .C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(15), - .C_PROG_FULL_THRESH_ASSERT_VAL_RACH(15), - .C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023), - .C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(15), - .C_PROG_EMPTY_TYPE_WACH(0), - .C_PROG_EMPTY_TYPE_WDCH(0), - .C_PROG_EMPTY_TYPE_WRCH(0), - .C_PROG_EMPTY_TYPE_RACH(0), - .C_PROG_EMPTY_TYPE_RDCH(0), - .C_PROG_EMPTY_TYPE_AXIS(0), - .C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(13), - .C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1021), - .C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(13), - .C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(13), - .C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1021), - .C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(13), - .C_REG_SLICE_MODE_WACH(0), - .C_REG_SLICE_MODE_WDCH(0), - .C_REG_SLICE_MODE_WRCH(0), - .C_REG_SLICE_MODE_RACH(0), - .C_REG_SLICE_MODE_RDCH(0), - .C_REG_SLICE_MODE_AXIS(0) - ) inst ( - .backup(1'D0), - .backup_marker(1'D0), - .clk(1'D0), - .rst(1'D0), - .srst(1'D0), - .wr_clk(1'D0), - .wr_rst(1'D0), - .rd_clk(1'D0), - .rd_rst(1'D0), - .din(18'B0), - .wr_en(1'D0), - .rd_en(1'D0), - .prog_empty_thresh(10'B0), - .prog_empty_thresh_assert(10'B0), - .prog_empty_thresh_negate(10'B0), - .prog_full_thresh(10'B0), - .prog_full_thresh_assert(10'B0), - .prog_full_thresh_negate(10'B0), - .int_clk(1'D0), - .injectdbiterr(1'D0), - .injectsbiterr(1'D0), - .sleep(1'D0), - .dout(), - .full(), - .almost_full(), - .wr_ack(), - .overflow(), - .empty(), - .almost_empty(), - .valid(), - .underflow(), - .data_count(), - .rd_data_count(), - .wr_data_count(), - .prog_full(), - .prog_empty(), - .sbiterr(), - .dbiterr(), - .wr_rst_busy(wr_rst_busy), - .rd_rst_busy(rd_rst_busy), - .m_aclk(m_aclk), - .s_aclk(s_aclk), - .s_aresetn(s_aresetn), - .m_aclk_en(1'D0), - .s_aclk_en(1'D0), - .s_axi_awid(1'B0), - .s_axi_awaddr(32'B0), - .s_axi_awlen(8'B0), - .s_axi_awsize(3'B0), - .s_axi_awburst(2'B0), - .s_axi_awlock(1'B0), - .s_axi_awcache(4'B0), - .s_axi_awprot(3'B0), - .s_axi_awqos(4'B0), - .s_axi_awregion(4'B0), - .s_axi_awuser(1'B0), - .s_axi_awvalid(1'D0), - .s_axi_awready(), - .s_axi_wid(1'B0), - .s_axi_wdata(64'B0), - .s_axi_wstrb(8'B0), - .s_axi_wlast(1'D0), - .s_axi_wuser(1'B0), - .s_axi_wvalid(1'D0), - .s_axi_wready(), - .s_axi_bid(), - .s_axi_bresp(), - .s_axi_buser(), - .s_axi_bvalid(), - .s_axi_bready(1'D0), - .m_axi_awid(), - .m_axi_awaddr(), - .m_axi_awlen(), - .m_axi_awsize(), - .m_axi_awburst(), - .m_axi_awlock(), - .m_axi_awcache(), - .m_axi_awprot(), - .m_axi_awqos(), - .m_axi_awregion(), - .m_axi_awuser(), - .m_axi_awvalid(), - .m_axi_awready(1'D0), - .m_axi_wid(), - .m_axi_wdata(), - .m_axi_wstrb(), - .m_axi_wlast(), - .m_axi_wuser(), - .m_axi_wvalid(), - .m_axi_wready(1'D0), - .m_axi_bid(1'B0), - .m_axi_bresp(2'B0), - .m_axi_buser(1'B0), - .m_axi_bvalid(1'D0), - .m_axi_bready(), - .s_axi_arid(1'B0), - .s_axi_araddr(32'B0), - .s_axi_arlen(8'B0), - .s_axi_arsize(3'B0), - .s_axi_arburst(2'B0), - .s_axi_arlock(1'B0), - .s_axi_arcache(4'B0), - .s_axi_arprot(3'B0), - .s_axi_arqos(4'B0), - .s_axi_arregion(4'B0), - .s_axi_aruser(1'B0), - .s_axi_arvalid(1'D0), - .s_axi_arready(), - .s_axi_rid(), - .s_axi_rdata(), - .s_axi_rresp(), - .s_axi_rlast(), - .s_axi_ruser(), - .s_axi_rvalid(), - .s_axi_rready(1'D0), - .m_axi_arid(), - .m_axi_araddr(), - .m_axi_arlen(), - .m_axi_arsize(), - .m_axi_arburst(), - .m_axi_arlock(), - .m_axi_arcache(), - .m_axi_arprot(), - .m_axi_arqos(), - .m_axi_arregion(), - .m_axi_aruser(), - .m_axi_arvalid(), - .m_axi_arready(1'D0), - .m_axi_rid(1'B0), - .m_axi_rdata(64'B0), - .m_axi_rresp(2'B0), - .m_axi_rlast(1'D0), - .m_axi_ruser(1'B0), - .m_axi_rvalid(1'D0), - .m_axi_rready(), - .s_axis_tvalid(s_axis_tvalid), - .s_axis_tready(s_axis_tready), - .s_axis_tdata(s_axis_tdata), - .s_axis_tstrb(2'B0), - .s_axis_tkeep(2'B0), - .s_axis_tlast(1'D0), - .s_axis_tid(1'B0), - .s_axis_tdest(1'B0), - .s_axis_tuser(1'B0), - .m_axis_tvalid(m_axis_tvalid), - .m_axis_tready(m_axis_tready), - .m_axis_tdata(m_axis_tdata), - .m_axis_tstrb(), - .m_axis_tkeep(), - .m_axis_tlast(), - .m_axis_tid(), - .m_axis_tdest(), - .m_axis_tuser(), - .axi_aw_injectsbiterr(1'D0), - .axi_aw_injectdbiterr(1'D0), - .axi_aw_prog_full_thresh(4'B0), - .axi_aw_prog_empty_thresh(4'B0), - .axi_aw_data_count(), - .axi_aw_wr_data_count(), - .axi_aw_rd_data_count(), - .axi_aw_sbiterr(), - .axi_aw_dbiterr(), - .axi_aw_overflow(), - .axi_aw_underflow(), - .axi_aw_prog_full(), - .axi_aw_prog_empty(), - .axi_w_injectsbiterr(1'D0), - .axi_w_injectdbiterr(1'D0), - .axi_w_prog_full_thresh(10'B0), - .axi_w_prog_empty_thresh(10'B0), - .axi_w_data_count(), - .axi_w_wr_data_count(), - .axi_w_rd_data_count(), - .axi_w_sbiterr(), - .axi_w_dbiterr(), - .axi_w_overflow(), - .axi_w_underflow(), - .axi_w_prog_full(), - .axi_w_prog_empty(), - .axi_b_injectsbiterr(1'D0), - .axi_b_injectdbiterr(1'D0), - .axi_b_prog_full_thresh(4'B0), - .axi_b_prog_empty_thresh(4'B0), - .axi_b_data_count(), - .axi_b_wr_data_count(), - .axi_b_rd_data_count(), - .axi_b_sbiterr(), - .axi_b_dbiterr(), - .axi_b_overflow(), - .axi_b_underflow(), - .axi_b_prog_full(), - .axi_b_prog_empty(), - .axi_ar_injectsbiterr(1'D0), - .axi_ar_injectdbiterr(1'D0), - .axi_ar_prog_full_thresh(4'B0), - .axi_ar_prog_empty_thresh(4'B0), - .axi_ar_data_count(), - .axi_ar_wr_data_count(), - .axi_ar_rd_data_count(), - .axi_ar_sbiterr(), - .axi_ar_dbiterr(), - .axi_ar_overflow(), - .axi_ar_underflow(), - .axi_ar_prog_full(), - .axi_ar_prog_empty(), - .axi_r_injectsbiterr(1'D0), - .axi_r_injectdbiterr(1'D0), - .axi_r_prog_full_thresh(10'B0), - .axi_r_prog_empty_thresh(10'B0), - .axi_r_data_count(), - .axi_r_wr_data_count(), - .axi_r_rd_data_count(), - .axi_r_sbiterr(), - .axi_r_dbiterr(), - .axi_r_overflow(), - .axi_r_underflow(), - .axi_r_prog_full(), - .axi_r_prog_empty(), - .axis_injectsbiterr(1'D0), - .axis_injectdbiterr(1'D0), - .axis_prog_full_thresh(4'B0), - .axis_prog_empty_thresh(4'B0), - .axis_data_count(), - .axis_wr_data_count(), - .axis_rd_data_count(), - .axis_sbiterr(), - .axis_dbiterr(), - .axis_overflow(), - .axis_underflow(), - .axis_prog_full(), - .axis_prog_empty() - ); -endmodule diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/lpf_125k/lpf_125k_sim_netlist.v b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/lpf_125k/lpf_125k_sim_netlist.v deleted file mode 100644 index d0637842..00000000 --- a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/lpf_125k/lpf_125k_sim_netlist.v +++ /dev/null @@ -1,3 +0,0 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:8275143f122bdc3555c76c611fc8ec1323c298206a1081ac95e050b1d7f27294 -size 1012404 diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/lpf_125k/lpf_125k_sim_netlist.vhdl b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/lpf_125k/lpf_125k_sim_netlist.vhdl deleted file mode 100644 index 01ec5ab9..00000000 --- a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/lpf_125k/lpf_125k_sim_netlist.vhdl +++ /dev/null @@ -1,3 +0,0 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:78d602cb9e77d8cd877d2d9da7ca5d378aad8af07d6530ff4651c50721c80543 -size 1328333 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/rom_hop_data/rom_hop_data.veo b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/rom_freq_word/rom_freq_word.veo similarity index 90% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/rom_hop_data/rom_hop_data.veo rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/rom_freq_word/rom_freq_word.veo index 08f4206a..b92dae58 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/rom_hop_data/rom_hop_data.veo +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/rom_freq_word/rom_freq_word.veo @@ -54,14 +54,14 @@ // (in parentheses) to your own signal names. //----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG -rom_hop_data your_instance_name ( +rom_freq_word your_instance_name ( .clka(clka), // input wire clka - .addra(addra), // input wire [13 : 0] addra - .douta(douta) // output wire [95 : 0] douta + .addra(addra), // input wire [6 : 0] addra + .douta(douta) // output wire [10 : 0] douta ); // INST_TAG_END ------ End INSTANTIATION Template --------- -// You must compile the wrapper file rom_hop_data.v when simulating -// the core, rom_hop_data. When compiling the wrapper file, be sure to +// You must compile the wrapper file rom_freq_word.v when simulating +// the core, rom_freq_word. When compiling the wrapper file, be sure to // reference the Verilog simulation library. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/rom_hop_data/rom_hop_data.vho b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/rom_freq_word/rom_freq_word.vho similarity index 90% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/rom_hop_data/rom_hop_data.vho rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/rom_freq_word/rom_freq_word.vho index 10f7d947..ab09483f 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/rom_hop_data/rom_hop_data.vho +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/rom_freq_word/rom_freq_word.vho @@ -52,11 +52,11 @@ -- The following code must appear in the VHDL architecture header. ------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG -COMPONENT rom_hop_data +COMPONENT rom_freq_word PORT ( clka : IN STD_LOGIC; - addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0); - douta : OUT STD_LOGIC_VECTOR(95 DOWNTO 0) + addra : IN STD_LOGIC_VECTOR(6 DOWNTO 0); + douta : OUT STD_LOGIC_VECTOR(10 DOWNTO 0) ); END COMPONENT; -- COMP_TAG_END ------ End COMPONENT Declaration ------------ @@ -65,7 +65,7 @@ END COMPONENT; -- body. Substitute your own instance name and net names. ------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG -your_instance_name : rom_hop_data +your_instance_name : rom_freq_word PORT MAP ( clka => clka, addra => addra, @@ -73,7 +73,7 @@ your_instance_name : rom_hop_data ); -- INST_TAG_END ------ End INSTANTIATION Template --------- --- You must compile the wrapper file rom_hop_data.vhd when simulating --- the core, rom_hop_data. When compiling the wrapper file, be sure to +-- You must compile the wrapper file rom_freq_word.vhd when simulating +-- the core, rom_freq_word. When compiling the wrapper file, be sure to -- reference the VHDL simulation library. diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_sim_netlist.v b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_sim_netlist.v new file mode 100644 index 00000000..54bf9fd2 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:ee77aa9f5f241d950e00888da443f80b8cee570bf6d9cdbc74f9dc67dbacb994 +size 28824 diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_sim_netlist.vhdl b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_sim_netlist.vhdl new file mode 100644 index 00000000..4360a2e5 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:1e0611322da5d005a87134e1c1c1dc2480c3dce787dd976b1d92348a3ba5286c +size 42610 diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_stub.v b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_stub.v new file mode 100644 index 00000000..3acbc634 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_stub.v @@ -0,0 +1,22 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Mon May 8 18:56:10 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub +// /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.v +// Design : rom_freq_word +// Purpose : Stub declaration of top-level module interface +// Device : xc7z100ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "blk_mem_gen_v8_4_3,Vivado 2019.1.3" *) +module rom_freq_word(clka, addra, douta) +/* synthesis syn_black_box black_box_pad_pin="clka,addra[6:0],douta[10:0]" */; + input clka; + input [6:0]addra; + output [10:0]douta; +endmodule diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_stub.vhdl b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_stub.vhdl new file mode 100644 index 00000000..fc4a414f --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_stub.vhdl @@ -0,0 +1,32 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Mon May 8 18:56:10 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.vhdl +-- Design : rom_freq_word +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity rom_freq_word is + Port ( + clka : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR ( 6 downto 0 ); + douta : out STD_LOGIC_VECTOR ( 10 downto 0 ) + ); + +end rom_freq_word; + +architecture stub of rom_freq_word is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clka,addra[6:0],douta[10:0]"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_3,Vivado 2019.1.3"; +begin +end; diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/rom_freq_word/sim/rom_freq_word.v b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/rom_freq_word/sim/rom_freq_word.v new file mode 100644 index 00000000..bca88b77 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/rom_freq_word/sim/rom_freq_word.v @@ -0,0 +1,211 @@ +// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4 +// IP Revision: 3 + +`timescale 1ns/1ps + +(* DowngradeIPIdentifiedWarnings = "yes" *) +module rom_freq_word ( + clka, + addra, + douta +); + +(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) +input wire clka; +(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) +input wire [6 : 0] addra; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1" *) +(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *) +output wire [10 : 0] douta; + + blk_mem_gen_v8_4_3 #( + .C_FAMILY("zynq"), + .C_XDEVICEFAMILY("zynq"), + .C_ELABORATION_DIR("./"), + .C_INTERFACE_TYPE(0), + .C_AXI_TYPE(1), + .C_AXI_SLAVE_TYPE(0), + .C_USE_BRAM_BLOCK(0), + .C_ENABLE_32BIT_ADDRESS(0), + .C_CTRL_ECC_ALGO("NONE"), + .C_HAS_AXI_ID(0), + .C_AXI_ID_WIDTH(4), + .C_MEM_TYPE(3), + .C_BYTE_SIZE(9), + .C_ALGORITHM(1), + .C_PRIM_TYPE(1), + .C_LOAD_INIT_FILE(1), + .C_INIT_FILE_NAME("rom_freq_word.mif"), + .C_INIT_FILE("rom_freq_word.mem"), + .C_USE_DEFAULT_DATA(0), + .C_DEFAULT_DATA("0"), + .C_HAS_RSTA(0), + .C_RST_PRIORITY_A("CE"), + .C_RSTRAM_A(0), + .C_INITA_VAL("0"), + .C_HAS_ENA(0), + .C_HAS_REGCEA(0), + .C_USE_BYTE_WEA(0), + .C_WEA_WIDTH(1), + .C_WRITE_MODE_A("WRITE_FIRST"), + .C_WRITE_WIDTH_A(11), + .C_READ_WIDTH_A(11), + .C_WRITE_DEPTH_A(81), + .C_READ_DEPTH_A(81), + .C_ADDRA_WIDTH(7), + .C_HAS_RSTB(0), + .C_RST_PRIORITY_B("CE"), + .C_RSTRAM_B(0), + .C_INITB_VAL("0"), + .C_HAS_ENB(0), + .C_HAS_REGCEB(0), + .C_USE_BYTE_WEB(0), + .C_WEB_WIDTH(1), + .C_WRITE_MODE_B("WRITE_FIRST"), + .C_WRITE_WIDTH_B(11), + .C_READ_WIDTH_B(11), + .C_WRITE_DEPTH_B(81), + .C_READ_DEPTH_B(81), + .C_ADDRB_WIDTH(7), + .C_HAS_MEM_OUTPUT_REGS_A(1), + .C_HAS_MEM_OUTPUT_REGS_B(0), + .C_HAS_MUX_OUTPUT_REGS_A(0), + .C_HAS_MUX_OUTPUT_REGS_B(0), + .C_MUX_PIPELINE_STAGES(0), + .C_HAS_SOFTECC_INPUT_REGS_A(0), + .C_HAS_SOFTECC_OUTPUT_REGS_B(0), + .C_USE_SOFTECC(0), + .C_USE_ECC(0), + .C_EN_ECC_PIPE(0), + .C_READ_LATENCY_A(1), + .C_READ_LATENCY_B(1), + .C_HAS_INJECTERR(0), + .C_SIM_COLLISION_CHECK("ALL"), + .C_COMMON_CLK(0), + .C_DISABLE_WARN_BHV_COLL(0), + .C_EN_SLEEP_PIN(0), + .C_USE_URAM(0), + .C_EN_RDADDRA_CHG(0), + .C_EN_RDADDRB_CHG(0), + .C_EN_DEEPSLEEP_PIN(0), + .C_EN_SHUTDOWN_PIN(0), + .C_EN_SAFETY_CKT(0), + .C_DISABLE_WARN_BHV_RANGE(0), + .C_COUNT_36K_BRAM("0"), + .C_COUNT_18K_BRAM("1"), + .C_EST_POWER_SUMMARY("Estimated Power for IP : 2.5016 mW") + ) inst ( + .clka(clka), + .rsta(1'D0), + .ena(1'D0), + .regcea(1'D0), + .wea(1'B0), + .addra(addra), + .dina(11'B0), + .douta(douta), + .clkb(1'D0), + .rstb(1'D0), + .enb(1'D0), + .regceb(1'D0), + .web(1'B0), + .addrb(7'B0), + .dinb(11'B0), + .doutb(), + .injectsbiterr(1'D0), + .injectdbiterr(1'D0), + .eccpipece(1'D0), + .sbiterr(), + .dbiterr(), + .rdaddrecc(), + .sleep(1'D0), + .deepsleep(1'D0), + .shutdown(1'D0), + .rsta_busy(), + .rstb_busy(), + .s_aclk(1'H0), + .s_aresetn(1'D0), + .s_axi_awid(4'B0), + .s_axi_awaddr(32'B0), + .s_axi_awlen(8'B0), + .s_axi_awsize(3'B0), + .s_axi_awburst(2'B0), + .s_axi_awvalid(1'D0), + .s_axi_awready(), + .s_axi_wdata(11'B0), + .s_axi_wstrb(1'B0), + .s_axi_wlast(1'D0), + .s_axi_wvalid(1'D0), + .s_axi_wready(), + .s_axi_bid(), + .s_axi_bresp(), + .s_axi_bvalid(), + .s_axi_bready(1'D0), + .s_axi_arid(4'B0), + .s_axi_araddr(32'B0), + .s_axi_arlen(8'B0), + .s_axi_arsize(3'B0), + .s_axi_arburst(2'B0), + .s_axi_arvalid(1'D0), + .s_axi_arready(), + .s_axi_rid(), + .s_axi_rdata(), + .s_axi_rresp(), + .s_axi_rlast(), + .s_axi_rvalid(), + .s_axi_rready(1'D0), + .s_axi_injectsbiterr(1'D0), + .s_axi_injectdbiterr(1'D0), + .s_axi_sbiterr(), + .s_axi_dbiterr(), + .s_axi_rdaddrecc() + ); +endmodule diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/sig_clk_gen/sig_clk_gen.v b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/sig_clk_gen/sig_clk_gen.v deleted file mode 100644 index 010c06d4..00000000 --- a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/sig_clk_gen/sig_clk_gen.v +++ /dev/null @@ -1,92 +0,0 @@ - -// file: sig_clk_gen.v -// -// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -//---------------------------------------------------------------------------- -// User entered comments -//---------------------------------------------------------------------------- -// None -// -//---------------------------------------------------------------------------- -// Output Output Phase Duty Cycle Pk-to-Pk Phase -// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) -//---------------------------------------------------------------------------- -// clk_out1____48.000______0.000______50.0______172.739____111.288 -// -//---------------------------------------------------------------------------- -// Input Clock Freq (MHz) Input Jitter (UI) -//---------------------------------------------------------------------------- -// __primary__________122.88____________0.010 - -`timescale 1ps/1ps - -(* CORE_GENERATION_INFO = "sig_clk_gen,clk_wiz_v6_0_3_0_0,{component_name=sig_clk_gen,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=8.138,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *) - -module sig_clk_gen - ( - // Clock out ports - output clk_out1, - // Status and control signals - input reset, - output locked, - // Clock in ports - input clk_in1 - ); - - sig_clk_gen_clk_wiz inst - ( - // Clock out ports - .clk_out1(clk_out1), - // Status and control signals - .reset(reset), - .locked(locked), - // Clock in ports - .clk_in1(clk_in1) - ); - -endmodule diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/sig_clk_gen/sig_clk_gen_clk_wiz.v b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/sig_clk_gen/sig_clk_gen_clk_wiz.v deleted file mode 100644 index 1bb22e84..00000000 --- a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/sig_clk_gen/sig_clk_gen_clk_wiz.v +++ /dev/null @@ -1,204 +0,0 @@ - -// file: sig_clk_gen.v -// -// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. -// -// This file contains confidential and proprietary information -// of Xilinx, Inc. and is protected under U.S. and -// international copyright and other intellectual property -// laws. -// -// DISCLAIMER -// This disclaimer is not a license and does not grant any -// rights to the materials distributed herewith. Except as -// otherwise provided in a valid license issued to you by -// Xilinx, and to the maximum extent permitted by applicable -// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -// (2) Xilinx shall not be liable (whether in contract or tort, -// including negligence, or under any other theory of -// liability) for any loss or damage of any kind or nature -// related to, arising under or in connection with these -// materials, including for any direct, or any indirect, -// special, incidental, or consequential loss or damage -// (including loss of data, profits, goodwill, or any type of -// loss or damage suffered as a result of any action brought -// by a third party) even if such damage or loss was -// reasonably foreseeable or Xilinx had been advised of the -// possibility of the same. -// -// CRITICAL APPLICATIONS -// Xilinx products are not designed or intended to be fail- -// safe, or for use in any application requiring fail-safe -// performance, such as life-support or safety devices or -// systems, Class III medical devices, nuclear facilities, -// applications related to the deployment of airbags, or any -// other applications that could lead to death, personal -// injury, or severe property or environmental damage -// (individually and collectively, "Critical -// Applications"). Customer assumes the sole risk and -// liability of any use of Xilinx products in Critical -// Applications, subject only to applicable laws and -// regulations governing limitations on product liability. -// -// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -// PART OF THIS FILE AT ALL TIMES. -// -//---------------------------------------------------------------------------- -// User entered comments -//---------------------------------------------------------------------------- -// None -// -//---------------------------------------------------------------------------- -// Output Output Phase Duty Cycle Pk-to-Pk Phase -// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) -//---------------------------------------------------------------------------- -// clk_out1____48.000______0.000______50.0______172.739____111.288 -// -//---------------------------------------------------------------------------- -// Input Clock Freq (MHz) Input Jitter (UI) -//---------------------------------------------------------------------------- -// __primary__________122.88____________0.010 - -`timescale 1ps/1ps - -module sig_clk_gen_clk_wiz - - (// Clock in ports - // Clock out ports - output clk_out1, - // Status and control signals - input reset, - output locked, - input clk_in1 - ); - // Input buffering - //------------------------------------ -wire clk_in1_sig_clk_gen; -wire clk_in2_sig_clk_gen; - BUFG clkin1_bufg - (.O (clk_in1_sig_clk_gen), - .I (clk_in1)); - - - - - // Clocking PRIMITIVE - //------------------------------------ - - // Instantiation of the MMCM PRIMITIVE - // * Unused inputs are tied off - // * Unused outputs are labeled unused - - wire clk_out1_sig_clk_gen; - wire clk_out2_sig_clk_gen; - wire clk_out3_sig_clk_gen; - wire clk_out4_sig_clk_gen; - wire clk_out5_sig_clk_gen; - wire clk_out6_sig_clk_gen; - wire clk_out7_sig_clk_gen; - - wire [15:0] do_unused; - wire drdy_unused; - wire psdone_unused; - wire locked_int; - wire clkfbout_sig_clk_gen; - wire clkfbout_buf_sig_clk_gen; - wire clkfboutb_unused; - wire clkout0b_unused; - wire clkout1_unused; - wire clkout1b_unused; - wire clkout2_unused; - wire clkout2b_unused; - wire clkout3_unused; - wire clkout3b_unused; - wire clkout4_unused; - wire clkout5_unused; - wire clkout6_unused; - wire clkfbstopped_unused; - wire clkinstopped_unused; - wire reset_high; - - MMCME2_ADV - #(.BANDWIDTH ("OPTIMIZED"), - .CLKOUT4_CASCADE ("FALSE"), - .COMPENSATION ("ZHOLD"), - .STARTUP_WAIT ("FALSE"), - .DIVCLK_DIVIDE (2), - .CLKFBOUT_MULT_F (15.625), - .CLKFBOUT_PHASE (0.000), - .CLKFBOUT_USE_FINE_PS ("FALSE"), - .CLKOUT0_DIVIDE_F (20.000), - .CLKOUT0_PHASE (0.000), - .CLKOUT0_DUTY_CYCLE (0.500), - .CLKOUT0_USE_FINE_PS ("FALSE"), - .CLKIN1_PERIOD (8.138)) - mmcm_adv_inst - // Output clocks - ( - .CLKFBOUT (clkfbout_sig_clk_gen), - .CLKFBOUTB (clkfboutb_unused), - .CLKOUT0 (clk_out1_sig_clk_gen), - .CLKOUT0B (clkout0b_unused), - .CLKOUT1 (clkout1_unused), - .CLKOUT1B (clkout1b_unused), - .CLKOUT2 (clkout2_unused), - .CLKOUT2B (clkout2b_unused), - .CLKOUT3 (clkout3_unused), - .CLKOUT3B (clkout3b_unused), - .CLKOUT4 (clkout4_unused), - .CLKOUT5 (clkout5_unused), - .CLKOUT6 (clkout6_unused), - // Input clock control - .CLKFBIN (clkfbout_buf_sig_clk_gen), - .CLKIN1 (clk_in1_sig_clk_gen), - .CLKIN2 (1'b0), - // Tied to always select the primary input clock - .CLKINSEL (1'b1), - // Ports for dynamic reconfiguration - .DADDR (7'h0), - .DCLK (1'b0), - .DEN (1'b0), - .DI (16'h0), - .DO (do_unused), - .DRDY (drdy_unused), - .DWE (1'b0), - // Ports for dynamic phase shift - .PSCLK (1'b0), - .PSEN (1'b0), - .PSINCDEC (1'b0), - .PSDONE (psdone_unused), - // Other control and status signals - .LOCKED (locked_int), - .CLKINSTOPPED (clkinstopped_unused), - .CLKFBSTOPPED (clkfbstopped_unused), - .PWRDWN (1'b0), - .RST (reset_high)); - assign reset_high = reset; - - assign locked = locked_int; -// Clock Monitor clock assigning -//-------------------------------------- - // Output buffering - //----------------------------------- - - BUFG clkf_buf - (.O (clkfbout_buf_sig_clk_gen), - .I (clkfbout_sig_clk_gen)); - - - - - - - BUFG clkout1_buf - (.O (clk_out1), - .I (clk_out1_sig_clk_gen)); - - - - -endmodule diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/sig_clk_gen/sig_clk_gen_sim_netlist.v b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/sig_clk_gen/sig_clk_gen_sim_netlist.v deleted file mode 100644 index a8b47913..00000000 --- a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/sig_clk_gen/sig_clk_gen_sim_netlist.v +++ /dev/null @@ -1,3 +0,0 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:2339b0a13d0b690c03b1c728fd710c497931802447f287dcc06e0515f26d3778 -size 7063 diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/vio_manual_ctrl/sim/vio_manual_ctrl.v b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/vio_manual_ctrl/sim/vio_manual_ctrl.v new file mode 100644 index 00000000..56471ab0 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/vio_manual_ctrl/sim/vio_manual_ctrl.v @@ -0,0 +1,68 @@ +// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. +`timescale 1ns / 1ps +module vio_manual_ctrl ( +clk, + +probe_out0, +probe_out1, +probe_out2, +probe_out3, +probe_out4 +); + +input clk; + +output reg [2 : 0] probe_out0 = 'h4 ; +output reg [0 : 0] probe_out1 = 'h0 ; +output reg [31 : 0] probe_out2 = 'h00000000 ; +output reg [1 : 0] probe_out3 = 'h3 ; +output reg [3 : 0] probe_out4 = 'h0 ; + + +endmodule diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl.veo b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl.veo new file mode 100644 index 00000000..4832fe5b --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl.veo @@ -0,0 +1,70 @@ +// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:vio:3.0 +// IP Revision: 20 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +vio_manual_ctrl your_instance_name ( + .clk(clk), // input wire clk + .probe_out0(probe_out0), // output wire [2 : 0] probe_out0 + .probe_out1(probe_out1), // output wire [0 : 0] probe_out1 + .probe_out2(probe_out2), // output wire [31 : 0] probe_out2 + .probe_out3(probe_out3), // output wire [1 : 0] probe_out3 + .probe_out4(probe_out4) // output wire [3 : 0] probe_out4 +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file vio_manual_ctrl.v when simulating +// the core, vio_manual_ctrl. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl.vho b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl.vho new file mode 100644 index 00000000..0775b07e --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl.vho @@ -0,0 +1,85 @@ +-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:vio:3.0 +-- IP Revision: 20 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT vio_manual_ctrl + PORT ( + clk : IN STD_LOGIC; + probe_out0 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + probe_out1 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + probe_out2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + probe_out3 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + probe_out4 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : vio_manual_ctrl + PORT MAP ( + clk => clk, + probe_out0 => probe_out0, + probe_out1 => probe_out1, + probe_out2 => probe_out2, + probe_out3 => probe_out3, + probe_out4 => probe_out4 + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file vio_manual_ctrl.vhd when simulating +-- the core, vio_manual_ctrl. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_sim_netlist.v b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_sim_netlist.v new file mode 100644 index 00000000..c7abe00f --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:cb065d0eddb5b655bab77fb0852a87bb5011a810896d8e714356346485691606 +size 353149 diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_sim_netlist.vhdl b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_sim_netlist.vhdl new file mode 100644 index 00000000..69476f18 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:ce8bf1803b3191b816081504adefaa817efc0507189277d23ceb58cfe1deba32 +size 635009 diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_stub.v b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_stub.v new file mode 100644 index 00000000..4ca646b3 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_stub.v @@ -0,0 +1,26 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Mon May 8 17:56:01 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub +// /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.v +// Design : vio_manual_ctrl +// Purpose : Stub declaration of top-level module interface +// Device : xc7z100ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "vio,Vivado 2019.1.3" *) +module vio_manual_ctrl(clk, probe_out0, probe_out1, probe_out2, + probe_out3, probe_out4) +/* synthesis syn_black_box black_box_pad_pin="clk,probe_out0[2:0],probe_out1[0:0],probe_out2[31:0],probe_out3[1:0],probe_out4[3:0]" */; + input clk; + output [2:0]probe_out0; + output [0:0]probe_out1; + output [31:0]probe_out2; + output [1:0]probe_out3; + output [3:0]probe_out4; +endmodule diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/vio_hop_stub.vhdl b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_stub.vhdl similarity index 59% rename from projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/vio_hop_stub.vhdl rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_stub.vhdl index 754c0f7c..7883d1ed 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/vio_hop_stub.vhdl +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_stub.vhdl @@ -1,31 +1,34 @@ -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 --- Date : Wed Apr 19 12:04:19 2023 +-- Date : Mon May 8 17:56:01 2023 -- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS -- Command : write_vhdl -force -mode synth_stub --- /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/vio_hop_stub.vhdl --- Design : vio_hop +-- /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.vhdl +-- Design : vio_manual_ctrl -- Purpose : Stub declaration of top-level module interface --- Device : xc7k410tffg900-2 +-- Device : xc7z100ffg900-2 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -entity vio_hop is +entity vio_manual_ctrl is Port ( clk : in STD_LOGIC; - probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 ) + probe_out0 : out STD_LOGIC_VECTOR ( 2 downto 0 ); + probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out2 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + probe_out3 : out STD_LOGIC_VECTOR ( 1 downto 0 ); + probe_out4 : out STD_LOGIC_VECTOR ( 3 downto 0 ) ); -end vio_hop; +end vio_manual_ctrl; -architecture stub of vio_hop is +architecture stub of vio_manual_ctrl is attribute syn_black_box : boolean; attribute black_box_pad_pin : string; attribute syn_black_box of stub : architecture is true; -attribute black_box_pad_pin of stub : architecture is "clk,probe_out0[0:0],probe_out1[0:0]"; +attribute black_box_pad_pin of stub : architecture is "clk,probe_out0[2:0],probe_out1[0:0],probe_out2[31:0],probe_out3[1:0],probe_out4[3:0]"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3"; begin diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/vio_cal/hdl/vio_v3_0_20_vio_include.v b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/vio_rf_control/hdl/vio_v3_0_20_vio_include.v similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/vio_cal/hdl/vio_v3_0_20_vio_include.v rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/vio_rf_control/hdl/vio_v3_0_20_vio_include.v diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/vio_rf_control/sim/vio_rf_control.v b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/vio_rf_control/sim/vio_rf_control.v new file mode 100644 index 00000000..e228a872 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/vio_rf_control/sim/vio_rf_control.v @@ -0,0 +1,87 @@ +// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. +`timescale 1ns / 1ps +module vio_rf_control ( +clk, +probe_in0, +probe_out0, +probe_out1, +probe_out2, +probe_out3, +probe_out4, +probe_out5, +probe_out6, +probe_out7, +probe_out8, +probe_out9, +probe_out10, +probe_out11, +probe_out12, +probe_out13 +); + +input clk; +input [10 : 0] probe_in0; + +output reg [0 : 0] probe_out0 = 'h0 ; +output reg [1 : 0] probe_out1 = 'h0 ; +output reg [0 : 0] probe_out2 = 'h0 ; +output reg [5 : 0] probe_out3 = 'h08 ; +output reg [5 : 0] probe_out4 = 'h38 ; +output reg [10 : 0] probe_out5 = 'h3E8 ; +output reg [0 : 0] probe_out6 = 'h0 ; +output reg [0 : 0] probe_out7 = 'h0 ; +output reg [0 : 0] probe_out8 = 'h0 ; +output reg [0 : 0] probe_out9 = 'h0 ; +output reg [0 : 0] probe_out10 = 'h0 ; +output reg [0 : 0] probe_out11 = 'h0 ; +output reg [0 : 0] probe_out12 = 'h0 ; +output reg [15 : 0] probe_out13 = 'h0000 ; + + +endmodule diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/vio_rf_control/vio_rf_control.veo b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/vio_rf_control/vio_rf_control.veo new file mode 100644 index 00000000..bf4aaddc --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/vio_rf_control/vio_rf_control.veo @@ -0,0 +1,80 @@ +// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:vio:3.0 +// IP Revision: 20 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +vio_rf_control your_instance_name ( + .clk(clk), // input wire clk + .probe_in0(probe_in0), // input wire [10 : 0] probe_in0 + .probe_out0(probe_out0), // output wire [0 : 0] probe_out0 + .probe_out1(probe_out1), // output wire [1 : 0] probe_out1 + .probe_out2(probe_out2), // output wire [0 : 0] probe_out2 + .probe_out3(probe_out3), // output wire [5 : 0] probe_out3 + .probe_out4(probe_out4), // output wire [5 : 0] probe_out4 + .probe_out5(probe_out5), // output wire [10 : 0] probe_out5 + .probe_out6(probe_out6), // output wire [0 : 0] probe_out6 + .probe_out7(probe_out7), // output wire [0 : 0] probe_out7 + .probe_out8(probe_out8), // output wire [0 : 0] probe_out8 + .probe_out9(probe_out9), // output wire [0 : 0] probe_out9 + .probe_out10(probe_out10), // output wire [0 : 0] probe_out10 + .probe_out11(probe_out11), // output wire [0 : 0] probe_out11 + .probe_out12(probe_out12), // output wire [0 : 0] probe_out12 + .probe_out13(probe_out13) // output wire [15 : 0] probe_out13 +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file vio_rf_control.v when simulating +// the core, vio_rf_control. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/vio_rf_control/vio_rf_control.vho b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/vio_rf_control/vio_rf_control.vho new file mode 100644 index 00000000..9b2be4b5 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/vio_rf_control/vio_rf_control.vho @@ -0,0 +1,105 @@ +-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:vio:3.0 +-- IP Revision: 20 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT vio_rf_control + PORT ( + clk : IN STD_LOGIC; + probe_in0 : IN STD_LOGIC_VECTOR(10 DOWNTO 0); + probe_out0 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + probe_out1 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + probe_out2 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + probe_out3 : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); + probe_out4 : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); + probe_out5 : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); + probe_out6 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + probe_out7 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + probe_out8 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + probe_out9 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + probe_out10 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + probe_out11 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + probe_out12 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + probe_out13 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : vio_rf_control + PORT MAP ( + clk => clk, + probe_in0 => probe_in0, + probe_out0 => probe_out0, + probe_out1 => probe_out1, + probe_out2 => probe_out2, + probe_out3 => probe_out3, + probe_out4 => probe_out4, + probe_out5 => probe_out5, + probe_out6 => probe_out6, + probe_out7 => probe_out7, + probe_out8 => probe_out8, + probe_out9 => probe_out9, + probe_out10 => probe_out10, + probe_out11 => probe_out11, + probe_out12 => probe_out12, + probe_out13 => probe_out13 + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file vio_rf_control.vhd when simulating +-- the core, vio_rf_control. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/vio_rf_control/vio_rf_control_sim_netlist.v b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/vio_rf_control/vio_rf_control_sim_netlist.v new file mode 100644 index 00000000..5a41880c --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/vio_rf_control/vio_rf_control_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:4013731fff3a120d51c39228ec54c25ea8220b145f5ea9ffe59ef68ba014c545 +size 375426 diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/vio_rf_control/vio_rf_control_sim_netlist.vhdl b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/vio_rf_control/vio_rf_control_sim_netlist.vhdl new file mode 100644 index 00000000..772a0cfd --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/vio_rf_control/vio_rf_control_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:b9f1a6b33d88da7b9015910d2fc0eb24fdc1e58fe2f8b9e226884fb09cc64abb +size 668202 diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/vio_rf_control/vio_rf_control_stub.v b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/vio_rf_control/vio_rf_control_stub.v new file mode 100644 index 00000000..a5f1d5af --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/vio_rf_control/vio_rf_control_stub.v @@ -0,0 +1,37 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Sun May 7 19:30:43 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub +// /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_stub.v +// Design : vio_rf_control +// Purpose : Stub declaration of top-level module interface +// Device : xc7z100ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "vio,Vivado 2019.1.3" *) +module vio_rf_control(clk, probe_in0, probe_out0, probe_out1, + probe_out2, probe_out3, probe_out4, probe_out5, probe_out6, probe_out7, probe_out8, probe_out9, + probe_out10, probe_out11, probe_out12, probe_out13) +/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[10:0],probe_out0[0:0],probe_out1[1:0],probe_out2[0:0],probe_out3[5:0],probe_out4[5:0],probe_out5[10:0],probe_out6[0:0],probe_out7[0:0],probe_out8[0:0],probe_out9[0:0],probe_out10[0:0],probe_out11[0:0],probe_out12[0:0],probe_out13[15:0]" */; + input clk; + input [10:0]probe_in0; + output [0:0]probe_out0; + output [1:0]probe_out1; + output [0:0]probe_out2; + output [5:0]probe_out3; + output [5:0]probe_out4; + output [10:0]probe_out5; + output [0:0]probe_out6; + output [0:0]probe_out7; + output [0:0]probe_out8; + output [0:0]probe_out9; + output [0:0]probe_out10; + output [0:0]probe_out11; + output [0:0]probe_out12; + output [15:0]probe_out13; +endmodule diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/vio_rf_control/vio_rf_control_stub.vhdl b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/vio_rf_control/vio_rf_control_stub.vhdl new file mode 100644 index 00000000..f7668fae --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/vio_rf_control/vio_rf_control_stub.vhdl @@ -0,0 +1,45 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Sun May 7 19:30:43 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_stub.vhdl +-- Design : vio_rf_control +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity vio_rf_control is + Port ( + clk : in STD_LOGIC; + probe_in0 : in STD_LOGIC_VECTOR ( 10 downto 0 ); + probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out1 : out STD_LOGIC_VECTOR ( 1 downto 0 ); + probe_out2 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out3 : out STD_LOGIC_VECTOR ( 5 downto 0 ); + probe_out4 : out STD_LOGIC_VECTOR ( 5 downto 0 ); + probe_out5 : out STD_LOGIC_VECTOR ( 10 downto 0 ); + probe_out6 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out7 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out8 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out9 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out10 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out11 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out12 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out13 : out STD_LOGIC_VECTOR ( 15 downto 0 ) + ); + +end vio_rf_control; + +architecture stub of vio_rf_control is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[10:0],probe_out0[0:0],probe_out1[1:0],probe_out2[0:0],probe_out3[5:0],probe_out4[5:0],probe_out5[10:0],probe_out6[0:0],probe_out7[0:0],probe_out8[0:0],probe_out9[0:0],probe_out10[0:0],probe_out11[0:0],probe_out12[0:0],probe_out13[15:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3"; +begin +end; diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ipstatic/simulation/blk_mem_gen_v8_4.v b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ipstatic/simulation/blk_mem_gen_v8_4.v new file mode 100644 index 00000000..2dbe576b --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ipstatic/simulation/blk_mem_gen_v8_4.v @@ -0,0 +1,4522 @@ +/****************************************************************************** +-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- + ***************************************************************************** + * + * Filename: blk_mem_gen_v8_4_3.v + * + * Description: + * This file is the Verilog behvarial model for the + * Block Memory Generator Core. + * + ***************************************************************************** + * Author: Xilinx + * + * History: Jan 11, 2006 Initial revision + * Jun 11, 2007 Added independent register stages for + * Port A and Port B (IP1_Jm/v2.5) + * Aug 28, 2007 Added mux pipeline stages feature (IP2_Jm/v2.6) + * Mar 13, 2008 Behavioral model optimizations + * April 07, 2009 : Added support for Spartan-6 and Virtex-6 + * features, including the following: + * (i) error injection, detection and/or correction + * (ii) reset priority + * (iii) special reset behavior + * + *****************************************************************************/ +`timescale 1ps/1ps + +module STATE_LOGIC_v8_4 (O, I0, I1, I2, I3, I4, I5); + + parameter INIT = 64'h0000000000000000; + + input I0, I1, I2, I3, I4, I5; + + output O; + + reg O; + reg tmp; + + always @( I5 or I4 or I3 or I2 or I1 or I0 ) begin + + tmp = I0 ^ I1 ^ I2 ^ I3 ^ I4 ^ I5; + + if ( tmp == 0 || tmp == 1) + + O = INIT[{I5, I4, I3, I2, I1, I0}]; + + end +endmodule + +module beh_vlog_muxf7_v8_4 (O, I0, I1, S); + + output O; + reg O; + + input I0, I1, S; + + always @(I0 or I1 or S) + if (S) + O = I1; + else + O = I0; +endmodule + +module beh_vlog_ff_clr_v8_4 (Q, C, CLR, D); + parameter INIT = 0; +localparam FLOP_DELAY = 100; + output Q; + + input C, CLR, D; + + reg Q; + + initial Q= 1'b0; + + always @(posedge C ) + if (CLR) + Q<= 1'b0; + else + Q<= #FLOP_DELAY D; + + +endmodule + +module beh_vlog_ff_pre_v8_4 (Q, C, D, PRE); + + parameter INIT = 0; +localparam FLOP_DELAY = 100; + output Q; + input C, D, PRE; + + reg Q; + + initial Q= 1'b0; + + always @(posedge C ) + if (PRE) + Q <= 1'b1; + else + Q <= #FLOP_DELAY D; + +endmodule + +module beh_vlog_ff_ce_clr_v8_4 (Q, C, CE, CLR, D); + + parameter INIT = 0; +localparam FLOP_DELAY = 100; + output Q; + input C, CE, CLR, D; + + reg Q; + + initial Q= 1'b0; + always @(posedge C ) + if (CLR) + Q <= 1'b0; + else if (CE) + Q <= #FLOP_DELAY D; + +endmodule + +module write_netlist_v8_4 +#( + parameter C_AXI_TYPE = 0 + ) + ( + S_ACLK, S_ARESETN, S_AXI_AWVALID, S_AXI_WVALID, S_AXI_BREADY, + w_last_c, bready_timeout_c, aw_ready_r, S_AXI_WREADY, S_AXI_BVALID, + S_AXI_WR_EN, addr_en_c, incr_addr_c, bvalid_c + ); + + input S_ACLK; + input S_ARESETN; + input S_AXI_AWVALID; + input S_AXI_WVALID; + input S_AXI_BREADY; + input w_last_c; + input bready_timeout_c; + output aw_ready_r; + output S_AXI_WREADY; + output S_AXI_BVALID; + output S_AXI_WR_EN; + output addr_en_c; + output incr_addr_c; + output bvalid_c; + //------------------------------------------------------------------------- + //AXI LITE + //------------------------------------------------------------------------- +generate if (C_AXI_TYPE == 0 ) begin : gbeh_axi_lite_sm + wire w_ready_r_7; + wire w_ready_c; + wire aw_ready_c; + wire NlwRenamedSignal_bvalid_c; + wire NlwRenamedSignal_incr_addr_c; + wire present_state_FSM_FFd3_13; + wire present_state_FSM_FFd2_14; + wire present_state_FSM_FFd1_15; + wire present_state_FSM_FFd4_16; + wire present_state_FSM_FFd4_In; + wire present_state_FSM_FFd3_In; + wire present_state_FSM_FFd2_In; + wire present_state_FSM_FFd1_In; + wire present_state_FSM_FFd4_In1_21; + wire [0:0] Mmux_aw_ready_c ; +begin + assign + S_AXI_WREADY = w_ready_r_7, + S_AXI_BVALID = NlwRenamedSignal_incr_addr_c, + S_AXI_WR_EN = NlwRenamedSignal_bvalid_c, + incr_addr_c = NlwRenamedSignal_incr_addr_c, + bvalid_c = NlwRenamedSignal_bvalid_c; + + assign NlwRenamedSignal_incr_addr_c = 1'b0; + + beh_vlog_ff_clr_v8_4 #( + .INIT (1'b0)) + aw_ready_r_2 ( + .C ( S_ACLK), + .CLR ( S_ARESETN), + .D ( aw_ready_c), + .Q ( aw_ready_r) + ); + beh_vlog_ff_clr_v8_4 #( + .INIT (1'b0)) + w_ready_r ( + .C ( S_ACLK), + .CLR ( S_ARESETN), + .D ( w_ready_c), + .Q ( w_ready_r_7) + ); + beh_vlog_ff_pre_v8_4 #( + .INIT (1'b1)) + present_state_FSM_FFd4 ( + .C ( S_ACLK), + .D ( present_state_FSM_FFd4_In), + .PRE ( S_ARESETN), + .Q ( present_state_FSM_FFd4_16) + ); + beh_vlog_ff_clr_v8_4 #( + .INIT (1'b0)) + present_state_FSM_FFd3 ( + .C ( S_ACLK), + .CLR ( S_ARESETN), + .D ( present_state_FSM_FFd3_In), + .Q ( present_state_FSM_FFd3_13) + ); + beh_vlog_ff_clr_v8_4 #( + .INIT (1'b0)) + present_state_FSM_FFd2 ( + .C ( S_ACLK), + .CLR ( S_ARESETN), + .D ( present_state_FSM_FFd2_In), + .Q ( present_state_FSM_FFd2_14) + ); +beh_vlog_ff_clr_v8_4 #( + .INIT (1'b0)) + present_state_FSM_FFd1 ( + .C ( S_ACLK), + .CLR ( S_ARESETN), + .D ( present_state_FSM_FFd1_In), + .Q ( present_state_FSM_FFd1_15) + ); +STATE_LOGIC_v8_4 #( + .INIT (64'h0000000055554440)) + present_state_FSM_FFd3_In1 ( + .I0 ( S_AXI_WVALID), + .I1 ( S_AXI_AWVALID), + .I2 ( present_state_FSM_FFd2_14), + .I3 ( present_state_FSM_FFd4_16), + .I4 ( present_state_FSM_FFd3_13), + .I5 (1'b0), + .O ( present_state_FSM_FFd3_In) + ); +STATE_LOGIC_v8_4 #( + .INIT (64'h0000000088880800)) + present_state_FSM_FFd2_In1 ( + .I0 ( S_AXI_AWVALID), + .I1 ( S_AXI_WVALID), + .I2 ( bready_timeout_c), + .I3 ( present_state_FSM_FFd2_14), + .I4 ( present_state_FSM_FFd4_16), + .I5 (1'b0), + .O ( present_state_FSM_FFd2_In) + ); +STATE_LOGIC_v8_4 #( + .INIT (64'h00000000AAAA2000)) + Mmux_addr_en_c_0_1 ( + .I0 ( S_AXI_AWVALID), + .I1 ( bready_timeout_c), + .I2 ( present_state_FSM_FFd2_14), + .I3 ( S_AXI_WVALID), + .I4 ( present_state_FSM_FFd4_16), + .I5 (1'b0), + .O ( addr_en_c) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'hF5F07570F5F05500)) + Mmux_w_ready_c_0_1 ( + .I0 ( S_AXI_WVALID), + .I1 ( bready_timeout_c), + .I2 ( S_AXI_AWVALID), + .I3 ( present_state_FSM_FFd3_13), + .I4 ( present_state_FSM_FFd4_16), + .I5 ( present_state_FSM_FFd2_14), + .O ( w_ready_c) + ); +STATE_LOGIC_v8_4 #( + .INIT (64'h88808880FFFF8880)) + present_state_FSM_FFd1_In1 ( + .I0 ( S_AXI_WVALID), + .I1 ( bready_timeout_c), + .I2 ( present_state_FSM_FFd3_13), + .I3 ( present_state_FSM_FFd2_14), + .I4 ( present_state_FSM_FFd1_15), + .I5 ( S_AXI_BREADY), + .O ( present_state_FSM_FFd1_In) + ); +STATE_LOGIC_v8_4 #( + .INIT (64'h00000000000000A8)) + Mmux_S_AXI_WR_EN_0_1 ( + .I0 ( S_AXI_WVALID), + .I1 ( present_state_FSM_FFd2_14), + .I2 ( present_state_FSM_FFd3_13), + .I3 (1'b0), + .I4 (1'b0), + .I5 (1'b0), + .O ( NlwRenamedSignal_bvalid_c) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h2F0F27072F0F2200)) + present_state_FSM_FFd4_In1 ( + .I0 ( S_AXI_WVALID), + .I1 ( bready_timeout_c), + .I2 ( S_AXI_AWVALID), + .I3 ( present_state_FSM_FFd3_13), + .I4 ( present_state_FSM_FFd4_16), + .I5 ( present_state_FSM_FFd2_14), + .O ( present_state_FSM_FFd4_In1_21) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h00000000000000F8)) + present_state_FSM_FFd4_In2 ( + .I0 ( present_state_FSM_FFd1_15), + .I1 ( S_AXI_BREADY), + .I2 ( present_state_FSM_FFd4_In1_21), + .I3 (1'b0), + .I4 (1'b0), + .I5 (1'b0), + .O ( present_state_FSM_FFd4_In) + ); +STATE_LOGIC_v8_4 #( + .INIT (64'h7535753575305500)) + Mmux_aw_ready_c_0_1 ( + .I0 ( S_AXI_AWVALID), + .I1 ( bready_timeout_c), + .I2 ( S_AXI_WVALID), + .I3 ( present_state_FSM_FFd4_16), + .I4 ( present_state_FSM_FFd3_13), + .I5 ( present_state_FSM_FFd2_14), + .O ( Mmux_aw_ready_c[0]) + ); +STATE_LOGIC_v8_4 #( + .INIT (64'h00000000000000F8)) + Mmux_aw_ready_c_0_2 ( + .I0 ( present_state_FSM_FFd1_15), + .I1 ( S_AXI_BREADY), + .I2 ( Mmux_aw_ready_c[0]), + .I3 (1'b0), + .I4 (1'b0), + .I5 (1'b0), + .O ( aw_ready_c) + ); +end +end +endgenerate + + //--------------------------------------------------------------------- + // AXI FULL + //--------------------------------------------------------------------- +generate if (C_AXI_TYPE == 1 ) begin : gbeh_axi_full_sm + wire w_ready_r_8; + wire w_ready_c; + wire aw_ready_c; + wire NlwRenamedSig_OI_bvalid_c; + wire present_state_FSM_FFd1_16; + wire present_state_FSM_FFd4_17; + wire present_state_FSM_FFd3_18; + wire present_state_FSM_FFd2_19; + wire present_state_FSM_FFd4_In; + wire present_state_FSM_FFd3_In; + wire present_state_FSM_FFd2_In; + wire present_state_FSM_FFd1_In; + wire present_state_FSM_FFd2_In1_24; + wire present_state_FSM_FFd4_In1_25; + wire N2; + wire N4; +begin +assign + S_AXI_WREADY = w_ready_r_8, + bvalid_c = NlwRenamedSig_OI_bvalid_c, + S_AXI_BVALID = 1'b0; + +beh_vlog_ff_clr_v8_4 #( + .INIT (1'b0)) + aw_ready_r_2 + ( + .C ( S_ACLK), + .CLR ( S_ARESETN), + .D ( aw_ready_c), + .Q ( aw_ready_r) + ); +beh_vlog_ff_clr_v8_4 #( + .INIT (1'b0)) + w_ready_r + ( + .C ( S_ACLK), + .CLR ( S_ARESETN), + .D ( w_ready_c), + .Q ( w_ready_r_8) + ); + beh_vlog_ff_pre_v8_4 #( + .INIT (1'b1)) + present_state_FSM_FFd4 + ( + .C ( S_ACLK), + .D ( present_state_FSM_FFd4_In), + .PRE ( S_ARESETN), + .Q ( present_state_FSM_FFd4_17) + ); +beh_vlog_ff_clr_v8_4 #( + .INIT (1'b0)) + present_state_FSM_FFd3 + ( + .C ( S_ACLK), + .CLR ( S_ARESETN), + .D ( present_state_FSM_FFd3_In), + .Q ( present_state_FSM_FFd3_18) + ); +beh_vlog_ff_clr_v8_4 #( + .INIT (1'b0)) + present_state_FSM_FFd2 + ( + .C ( S_ACLK), + .CLR ( S_ARESETN), + .D ( present_state_FSM_FFd2_In), + .Q ( present_state_FSM_FFd2_19) + ); + beh_vlog_ff_clr_v8_4 #( + .INIT (1'b0)) + present_state_FSM_FFd1 + ( + .C ( S_ACLK), + .CLR ( S_ARESETN), + .D ( present_state_FSM_FFd1_In), + .Q ( present_state_FSM_FFd1_16) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h0000000000005540)) + present_state_FSM_FFd3_In1 + ( + .I0 ( S_AXI_WVALID), + .I1 ( present_state_FSM_FFd4_17), + .I2 ( S_AXI_AWVALID), + .I3 ( present_state_FSM_FFd3_18), + .I4 (1'b0), + .I5 (1'b0), + .O ( present_state_FSM_FFd3_In) + ); +STATE_LOGIC_v8_4 #( + .INIT (64'hBF3FBB33AF0FAA00)) + Mmux_aw_ready_c_0_2 + ( + .I0 ( S_AXI_BREADY), + .I1 ( bready_timeout_c), + .I2 ( S_AXI_AWVALID), + .I3 ( present_state_FSM_FFd1_16), + .I4 ( present_state_FSM_FFd4_17), + .I5 ( NlwRenamedSig_OI_bvalid_c), + .O ( aw_ready_c) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'hAAAAAAAA20000000)) + Mmux_addr_en_c_0_1 + ( + .I0 ( S_AXI_AWVALID), + .I1 ( bready_timeout_c), + .I2 ( present_state_FSM_FFd2_19), + .I3 ( S_AXI_WVALID), + .I4 ( w_last_c), + .I5 ( present_state_FSM_FFd4_17), + .O ( addr_en_c) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h00000000000000A8)) + Mmux_S_AXI_WR_EN_0_1 + ( + .I0 ( S_AXI_WVALID), + .I1 ( present_state_FSM_FFd2_19), + .I2 ( present_state_FSM_FFd3_18), + .I3 (1'b0), + .I4 (1'b0), + .I5 (1'b0), + .O ( S_AXI_WR_EN) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h0000000000002220)) + Mmux_incr_addr_c_0_1 + ( + .I0 ( S_AXI_WVALID), + .I1 ( w_last_c), + .I2 ( present_state_FSM_FFd2_19), + .I3 ( present_state_FSM_FFd3_18), + .I4 (1'b0), + .I5 (1'b0), + .O ( incr_addr_c) + ); +STATE_LOGIC_v8_4 #( + .INIT (64'h0000000000008880)) + Mmux_aw_ready_c_0_11 + ( + .I0 ( S_AXI_WVALID), + .I1 ( w_last_c), + .I2 ( present_state_FSM_FFd2_19), + .I3 ( present_state_FSM_FFd3_18), + .I4 (1'b0), + .I5 (1'b0), + .O ( NlwRenamedSig_OI_bvalid_c) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h000000000000D5C0)) + present_state_FSM_FFd2_In1 + ( + .I0 ( w_last_c), + .I1 ( S_AXI_AWVALID), + .I2 ( present_state_FSM_FFd4_17), + .I3 ( present_state_FSM_FFd3_18), + .I4 (1'b0), + .I5 (1'b0), + .O ( present_state_FSM_FFd2_In1_24) + ); +STATE_LOGIC_v8_4 #( + .INIT (64'hFFFFAAAA08AAAAAA)) + present_state_FSM_FFd2_In2 + ( + .I0 ( present_state_FSM_FFd2_19), + .I1 ( S_AXI_AWVALID), + .I2 ( bready_timeout_c), + .I3 ( w_last_c), + .I4 ( S_AXI_WVALID), + .I5 ( present_state_FSM_FFd2_In1_24), + .O ( present_state_FSM_FFd2_In) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h00C0004000C00000)) + present_state_FSM_FFd4_In1 + ( + .I0 ( S_AXI_AWVALID), + .I1 ( w_last_c), + .I2 ( S_AXI_WVALID), + .I3 ( bready_timeout_c), + .I4 ( present_state_FSM_FFd3_18), + .I5 ( present_state_FSM_FFd2_19), + .O ( present_state_FSM_FFd4_In1_25) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h00000000FFFF88F8)) + present_state_FSM_FFd4_In2 + ( + .I0 ( present_state_FSM_FFd1_16), + .I1 ( S_AXI_BREADY), + .I2 ( present_state_FSM_FFd4_17), + .I3 ( S_AXI_AWVALID), + .I4 ( present_state_FSM_FFd4_In1_25), + .I5 (1'b0), + .O ( present_state_FSM_FFd4_In) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h0000000000000007)) + Mmux_w_ready_c_0_SW0 + ( + .I0 ( w_last_c), + .I1 ( S_AXI_WVALID), + .I2 (1'b0), + .I3 (1'b0), + .I4 (1'b0), + .I5 (1'b0), + .O ( N2) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'hFABAFABAFAAAF000)) + Mmux_w_ready_c_0_Q + ( + .I0 ( N2), + .I1 ( bready_timeout_c), + .I2 ( S_AXI_AWVALID), + .I3 ( present_state_FSM_FFd4_17), + .I4 ( present_state_FSM_FFd3_18), + .I5 ( present_state_FSM_FFd2_19), + .O ( w_ready_c) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h0000000000000008)) + Mmux_aw_ready_c_0_11_SW0 + ( + .I0 ( bready_timeout_c), + .I1 ( S_AXI_WVALID), + .I2 (1'b0), + .I3 (1'b0), + .I4 (1'b0), + .I5 (1'b0), + .O ( N4) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h88808880FFFF8880)) + present_state_FSM_FFd1_In1 + ( + .I0 ( w_last_c), + .I1 ( N4), + .I2 ( present_state_FSM_FFd2_19), + .I3 ( present_state_FSM_FFd3_18), + .I4 ( present_state_FSM_FFd1_16), + .I5 ( S_AXI_BREADY), + .O ( present_state_FSM_FFd1_In) + ); +end +end +endgenerate +endmodule + + +module read_netlist_v8_4 #( + parameter C_AXI_TYPE = 1, + parameter C_ADDRB_WIDTH = 12 + ) ( S_AXI_R_LAST_INT, S_ACLK, S_ARESETN, S_AXI_ARVALID, + S_AXI_RREADY,S_AXI_INCR_ADDR,S_AXI_ADDR_EN, + S_AXI_SINGLE_TRANS,S_AXI_MUX_SEL, S_AXI_R_LAST, S_AXI_ARREADY, + S_AXI_RLAST, S_AXI_RVALID, S_AXI_RD_EN, S_AXI_ARLEN); + + input S_AXI_R_LAST_INT; + input S_ACLK; + input S_ARESETN; + input S_AXI_ARVALID; + input S_AXI_RREADY; + output S_AXI_INCR_ADDR; + output S_AXI_ADDR_EN; + output S_AXI_SINGLE_TRANS; + output S_AXI_MUX_SEL; + output S_AXI_R_LAST; + output S_AXI_ARREADY; + output S_AXI_RLAST; + output S_AXI_RVALID; + output S_AXI_RD_EN; + input [7:0] S_AXI_ARLEN; + + wire present_state_FSM_FFd1_13 ; + wire present_state_FSM_FFd2_14 ; + wire gaxi_full_sm_outstanding_read_r_15 ; + wire gaxi_full_sm_ar_ready_r_16 ; + wire gaxi_full_sm_r_last_r_17 ; + wire NlwRenamedSig_OI_gaxi_full_sm_r_valid_r ; + wire gaxi_full_sm_r_valid_c ; + wire S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o ; + wire gaxi_full_sm_ar_ready_c ; + wire gaxi_full_sm_outstanding_read_c ; + wire NlwRenamedSig_OI_S_AXI_R_LAST ; + wire S_AXI_ARLEN_7_GND_8_o_equal_1_o ; + wire present_state_FSM_FFd2_In ; + wire present_state_FSM_FFd1_In ; + wire Mmux_S_AXI_R_LAST13 ; + wire N01 ; + wire N2 ; + wire Mmux_gaxi_full_sm_ar_ready_c11 ; + wire N4 ; + wire N8 ; + wire N9 ; + wire N10 ; + wire N11 ; + wire N12 ; + wire N13 ; + assign + S_AXI_R_LAST = NlwRenamedSig_OI_S_AXI_R_LAST, + S_AXI_ARREADY = gaxi_full_sm_ar_ready_r_16, + S_AXI_RLAST = gaxi_full_sm_r_last_r_17, + S_AXI_RVALID = NlwRenamedSig_OI_gaxi_full_sm_r_valid_r; + + beh_vlog_ff_clr_v8_4 #( + .INIT (1'b0)) + gaxi_full_sm_outstanding_read_r ( + .C (S_ACLK), + .CLR(S_ARESETN), + .D(gaxi_full_sm_outstanding_read_c), + .Q(gaxi_full_sm_outstanding_read_r_15) + ); + beh_vlog_ff_ce_clr_v8_4 #( + .INIT (1'b0)) + gaxi_full_sm_r_valid_r ( + .C (S_ACLK), + .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o), + .CLR (S_ARESETN), + .D (gaxi_full_sm_r_valid_c), + .Q (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r) + ); + beh_vlog_ff_clr_v8_4 #( + .INIT (1'b0)) + gaxi_full_sm_ar_ready_r ( + .C (S_ACLK), + .CLR (S_ARESETN), + .D (gaxi_full_sm_ar_ready_c), + .Q (gaxi_full_sm_ar_ready_r_16) + ); + beh_vlog_ff_ce_clr_v8_4 #( + .INIT(1'b0)) + gaxi_full_sm_r_last_r ( + .C (S_ACLK), + .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o), + .CLR (S_ARESETN), + .D (NlwRenamedSig_OI_S_AXI_R_LAST), + .Q (gaxi_full_sm_r_last_r_17) + ); + beh_vlog_ff_clr_v8_4 #( + .INIT (1'b0)) + present_state_FSM_FFd2 ( + .C ( S_ACLK), + .CLR ( S_ARESETN), + .D ( present_state_FSM_FFd2_In), + .Q ( present_state_FSM_FFd2_14) + ); + beh_vlog_ff_clr_v8_4 #( + .INIT (1'b0)) + present_state_FSM_FFd1 ( + .C (S_ACLK), + .CLR (S_ARESETN), + .D (present_state_FSM_FFd1_In), + .Q (present_state_FSM_FFd1_13) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h000000000000000B)) + S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 ( + .I0 ( S_AXI_RREADY), + .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), + .I2 (1'b0), + .I3 (1'b0), + .I4 (1'b0), + .I5 (1'b0), + .O (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h0000000000000008)) + Mmux_S_AXI_SINGLE_TRANS11 ( + .I0 (S_AXI_ARVALID), + .I1 (S_AXI_ARLEN_7_GND_8_o_equal_1_o), + .I2 (1'b0), + .I3 (1'b0), + .I4 (1'b0), + .I5 (1'b0), + .O (S_AXI_SINGLE_TRANS) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h0000000000000004)) + Mmux_S_AXI_ADDR_EN11 ( + .I0 (present_state_FSM_FFd1_13), + .I1 (S_AXI_ARVALID), + .I2 (1'b0), + .I3 (1'b0), + .I4 (1'b0), + .I5 (1'b0), + .O (S_AXI_ADDR_EN) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'hECEE2022EEEE2022)) + present_state_FSM_FFd2_In1 ( + .I0 ( S_AXI_ARVALID), + .I1 ( present_state_FSM_FFd1_13), + .I2 ( S_AXI_RREADY), + .I3 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o), + .I4 ( present_state_FSM_FFd2_14), + .I5 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), + .O ( present_state_FSM_FFd2_In) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h0000000044440444)) + Mmux_S_AXI_R_LAST131 ( + .I0 ( present_state_FSM_FFd1_13), + .I1 ( S_AXI_ARVALID), + .I2 ( present_state_FSM_FFd2_14), + .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), + .I4 ( S_AXI_RREADY), + .I5 (1'b0), + .O ( Mmux_S_AXI_R_LAST13) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h4000FFFF40004000)) + Mmux_S_AXI_INCR_ADDR11 ( + .I0 ( S_AXI_R_LAST_INT), + .I1 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o), + .I2 ( present_state_FSM_FFd2_14), + .I3 ( present_state_FSM_FFd1_13), + .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o), + .I5 ( Mmux_S_AXI_R_LAST13), + .O ( S_AXI_INCR_ADDR) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h00000000000000FE)) + S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 ( + .I0 ( S_AXI_ARLEN[2]), + .I1 ( S_AXI_ARLEN[1]), + .I2 ( S_AXI_ARLEN[0]), + .I3 ( 1'b0), + .I4 ( 1'b0), + .I5 ( 1'b0), + .O ( N01) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h0000000000000001)) + S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q ( + .I0 ( S_AXI_ARLEN[7]), + .I1 ( S_AXI_ARLEN[6]), + .I2 ( S_AXI_ARLEN[5]), + .I3 ( S_AXI_ARLEN[4]), + .I4 ( S_AXI_ARLEN[3]), + .I5 ( N01), + .O ( S_AXI_ARLEN_7_GND_8_o_equal_1_o) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h0000000000000007)) + Mmux_gaxi_full_sm_outstanding_read_c1_SW0 ( + .I0 ( S_AXI_ARVALID), + .I1 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o), + .I2 ( 1'b0), + .I3 ( 1'b0), + .I4 ( 1'b0), + .I5 ( 1'b0), + .O ( N2) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h0020000002200200)) + Mmux_gaxi_full_sm_outstanding_read_c1 ( + .I0 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), + .I1 ( S_AXI_RREADY), + .I2 ( present_state_FSM_FFd1_13), + .I3 ( present_state_FSM_FFd2_14), + .I4 ( gaxi_full_sm_outstanding_read_r_15), + .I5 ( N2), + .O ( gaxi_full_sm_outstanding_read_c) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h0000000000004555)) + Mmux_gaxi_full_sm_ar_ready_c12 ( + .I0 ( S_AXI_ARVALID), + .I1 ( S_AXI_RREADY), + .I2 ( present_state_FSM_FFd2_14), + .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), + .I4 ( 1'b0), + .I5 ( 1'b0), + .O ( Mmux_gaxi_full_sm_ar_ready_c11) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h00000000000000EF)) + Mmux_S_AXI_R_LAST11_SW0 ( + .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o), + .I1 ( S_AXI_RREADY), + .I2 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), + .I3 ( 1'b0), + .I4 ( 1'b0), + .I5 ( 1'b0), + .O ( N4) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'hFCAAFC0A00AA000A)) + Mmux_S_AXI_R_LAST11 ( + .I0 ( S_AXI_ARVALID), + .I1 ( gaxi_full_sm_outstanding_read_r_15), + .I2 ( present_state_FSM_FFd2_14), + .I3 ( present_state_FSM_FFd1_13), + .I4 ( N4), + .I5 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o), + .O ( gaxi_full_sm_r_valid_c) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h00000000AAAAAA08)) + S_AXI_MUX_SEL1 ( + .I0 (present_state_FSM_FFd1_13), + .I1 (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), + .I2 (S_AXI_RREADY), + .I3 (present_state_FSM_FFd2_14), + .I4 (gaxi_full_sm_outstanding_read_r_15), + .I5 (1'b0), + .O (S_AXI_MUX_SEL) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'hF3F3F755A2A2A200)) + Mmux_S_AXI_RD_EN11 ( + .I0 ( present_state_FSM_FFd1_13), + .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), + .I2 ( S_AXI_RREADY), + .I3 ( gaxi_full_sm_outstanding_read_r_15), + .I4 ( present_state_FSM_FFd2_14), + .I5 ( S_AXI_ARVALID), + .O ( S_AXI_RD_EN) + ); + beh_vlog_muxf7_v8_4 present_state_FSM_FFd1_In3 ( + .I0 ( N8), + .I1 ( N9), + .S ( present_state_FSM_FFd1_13), + .O ( present_state_FSM_FFd1_In) + ); + + STATE_LOGIC_v8_4 #( + .INIT (64'h000000005410F4F0)) + present_state_FSM_FFd1_In3_F ( + .I0 ( S_AXI_RREADY), + .I1 ( present_state_FSM_FFd2_14), + .I2 ( S_AXI_ARVALID), + .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), + .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o), + .I5 ( 1'b0), + .O ( N8) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h0000000072FF7272)) + present_state_FSM_FFd1_In3_G ( + .I0 ( present_state_FSM_FFd2_14), + .I1 ( S_AXI_R_LAST_INT), + .I2 ( gaxi_full_sm_outstanding_read_r_15), + .I3 ( S_AXI_RREADY), + .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), + .I5 ( 1'b0), + .O ( N9) + ); + beh_vlog_muxf7_v8_4 Mmux_gaxi_full_sm_ar_ready_c14 ( + .I0 ( N10), + .I1 ( N11), + .S ( present_state_FSM_FFd1_13), + .O ( gaxi_full_sm_ar_ready_c) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h00000000FFFF88A8)) + Mmux_gaxi_full_sm_ar_ready_c14_F ( + .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o), + .I1 ( S_AXI_RREADY), + .I2 ( present_state_FSM_FFd2_14), + .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), + .I4 ( Mmux_gaxi_full_sm_ar_ready_c11), + .I5 ( 1'b0), + .O ( N10) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h000000008D008D8D)) + Mmux_gaxi_full_sm_ar_ready_c14_G ( + .I0 ( present_state_FSM_FFd2_14), + .I1 ( S_AXI_R_LAST_INT), + .I2 ( gaxi_full_sm_outstanding_read_r_15), + .I3 ( S_AXI_RREADY), + .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), + .I5 ( 1'b0), + .O ( N11) + ); + beh_vlog_muxf7_v8_4 Mmux_S_AXI_R_LAST1 ( + .I0 ( N12), + .I1 ( N13), + .S ( present_state_FSM_FFd1_13), + .O ( NlwRenamedSig_OI_S_AXI_R_LAST) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h0000000088088888)) + Mmux_S_AXI_R_LAST1_F ( + .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o), + .I1 ( S_AXI_ARVALID), + .I2 ( present_state_FSM_FFd2_14), + .I3 ( S_AXI_RREADY), + .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), + .I5 ( 1'b0), + .O ( N12) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h00000000E400E4E4)) + Mmux_S_AXI_R_LAST1_G ( + .I0 ( present_state_FSM_FFd2_14), + .I1 ( gaxi_full_sm_outstanding_read_r_15), + .I2 ( S_AXI_R_LAST_INT), + .I3 ( S_AXI_RREADY), + .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), + .I5 ( 1'b0), + .O ( N13) + ); + +endmodule + + +module blk_mem_axi_write_wrapper_beh_v8_4 + # ( + // AXI Interface related parameters start here + parameter C_INTERFACE_TYPE = 0, // 0: Native Interface; 1: AXI Interface + parameter C_AXI_TYPE = 0, // 0: AXI Lite; 1: AXI Full; + parameter C_AXI_SLAVE_TYPE = 0, // 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE; + parameter C_MEMORY_TYPE = 0, // 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM; + parameter C_WRITE_DEPTH_A = 0, + parameter C_AXI_AWADDR_WIDTH = 32, + parameter C_ADDRA_WIDTH = 12, + parameter C_AXI_WDATA_WIDTH = 32, + parameter C_HAS_AXI_ID = 0, + parameter C_AXI_ID_WIDTH = 4, + // AXI OUTSTANDING WRITES + parameter C_AXI_OS_WR = 2 + ) + ( + // AXI Global Signals + input S_ACLK, + input S_ARESETN, + // AXI Full/Lite Slave Write Channel (write side) + input [C_AXI_ID_WIDTH-1:0] S_AXI_AWID, + input [C_AXI_AWADDR_WIDTH-1:0] S_AXI_AWADDR, + input [8-1:0] S_AXI_AWLEN, + input [2:0] S_AXI_AWSIZE, + input [1:0] S_AXI_AWBURST, + input S_AXI_AWVALID, + output S_AXI_AWREADY, + input S_AXI_WVALID, + output S_AXI_WREADY, + output reg [C_AXI_ID_WIDTH-1:0] S_AXI_BID = 0, + output S_AXI_BVALID, + input S_AXI_BREADY, + // Signals for BMG interface + output [C_ADDRA_WIDTH-1:0] S_AXI_AWADDR_OUT, + output S_AXI_WR_EN + ); + + localparam FLOP_DELAY = 100; // 100 ps + + localparam C_RANGE = ((C_AXI_WDATA_WIDTH == 8)?0: + ((C_AXI_WDATA_WIDTH==16)?1: + ((C_AXI_WDATA_WIDTH==32)?2: + ((C_AXI_WDATA_WIDTH==64)?3: + ((C_AXI_WDATA_WIDTH==128)?4: + ((C_AXI_WDATA_WIDTH==256)?5:0)))))); + + + + + wire bvalid_c ; + reg bready_timeout_c = 0; + wire [1:0] bvalid_rd_cnt_c; + reg bvalid_r = 0; + reg [2:0] bvalid_count_r = 0; + reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)? + C_AXI_AWADDR_WIDTH:C_ADDRA_WIDTH)-1:0] awaddr_reg = 0; + reg [1:0] bvalid_wr_cnt_r = 0; + reg [1:0] bvalid_rd_cnt_r = 0; + wire w_last_c ; + wire addr_en_c ; + wire incr_addr_c ; + wire aw_ready_r ; + wire dec_alen_c ; + reg bvalid_d1_c = 0; + reg [7:0] awlen_cntr_r = 0; + reg [7:0] awlen_int = 0; + reg [1:0] awburst_int = 0; + + integer total_bytes = 0; + integer wrap_boundary = 0; + integer wrap_base_addr = 0; + integer num_of_bytes_c = 0; + integer num_of_bytes_r = 0; + // Array to store BIDs + reg [C_AXI_ID_WIDTH-1:0] axi_bid_array[3:0] ; + wire S_AXI_BVALID_axi_wr_fsm; + + //------------------------------------- + //AXI WRITE FSM COMPONENT INSTANTIATION + //------------------------------------- + write_netlist_v8_4 #(.C_AXI_TYPE(C_AXI_TYPE)) axi_wr_fsm + ( + .S_ACLK(S_ACLK), + .S_ARESETN(S_ARESETN), + .S_AXI_AWVALID(S_AXI_AWVALID), + .aw_ready_r(aw_ready_r), + .S_AXI_WVALID(S_AXI_WVALID), + .S_AXI_WREADY(S_AXI_WREADY), + .S_AXI_BREADY(S_AXI_BREADY), + .S_AXI_WR_EN(S_AXI_WR_EN), + .w_last_c(w_last_c), + .bready_timeout_c(bready_timeout_c), + .addr_en_c(addr_en_c), + .incr_addr_c(incr_addr_c), + .bvalid_c(bvalid_c), + .S_AXI_BVALID (S_AXI_BVALID_axi_wr_fsm) + ); + + + //Wrap Address boundary calculation + always@(*) begin + num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWSIZE:0); + total_bytes = (num_of_bytes_r)*(awlen_int+1); + wrap_base_addr = ((awaddr_reg)/((total_bytes==0)?1:total_bytes))*(total_bytes); + wrap_boundary = wrap_base_addr+total_bytes; + end + + //------------------------------------------------------------------------- + // BMG address generation + //------------------------------------------------------------------------- + always @(posedge S_ACLK or S_ARESETN) begin + if (S_ARESETN == 1'b1) begin + awaddr_reg <= 0; + num_of_bytes_r <= 0; + awburst_int <= 0; + end else begin + if (addr_en_c == 1'b1) begin + awaddr_reg <= #FLOP_DELAY S_AXI_AWADDR ; + num_of_bytes_r <= num_of_bytes_c; + awburst_int <= ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWBURST:2'b01); + end else if (incr_addr_c == 1'b1) begin + if (awburst_int == 2'b10) begin + if(awaddr_reg == (wrap_boundary-num_of_bytes_r)) begin + awaddr_reg <= wrap_base_addr; + end else begin + awaddr_reg <= awaddr_reg + num_of_bytes_r; + end + end else if (awburst_int == 2'b01 || awburst_int == 2'b11) begin + awaddr_reg <= awaddr_reg + num_of_bytes_r; + end + end + end + end + + + assign S_AXI_AWADDR_OUT = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)? + awaddr_reg[C_AXI_AWADDR_WIDTH-1:C_RANGE]:awaddr_reg); + + //------------------------------------------------------------------------- + // AXI wlast generation + //------------------------------------------------------------------------- + always @(posedge S_ACLK or S_ARESETN) begin + if (S_ARESETN == 1'b1) begin + awlen_cntr_r <= 0; + awlen_int <= 0; + end else begin + if (addr_en_c == 1'b1) begin + awlen_int <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ; + awlen_cntr_r <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ; + end else if (dec_alen_c == 1'b1) begin + awlen_cntr_r <= #FLOP_DELAY awlen_cntr_r - 1 ; + end + end + end + + assign w_last_c = (awlen_cntr_r == 0 && S_AXI_WVALID == 1'b1)?1'b1:1'b0; + + assign dec_alen_c = (incr_addr_c | w_last_c); + + //------------------------------------------------------------------------- + // Generation of bvalid counter for outstanding transactions + //------------------------------------------------------------------------- + always @(posedge S_ACLK or S_ARESETN) begin + if (S_ARESETN == 1'b1) begin + bvalid_count_r <= 0; + end else begin + // bvalid_count_r generation + if (bvalid_c == 1'b1 && bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1) begin + bvalid_count_r <= #FLOP_DELAY bvalid_count_r ; + end else if (bvalid_c == 1'b1) begin + bvalid_count_r <= #FLOP_DELAY bvalid_count_r + 1 ; + end else if (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1 && bvalid_count_r != 0) begin + bvalid_count_r <= #FLOP_DELAY bvalid_count_r - 1 ; + end + end + end + + //------------------------------------------------------------------------- + // Generation of bvalid when BID is used + //------------------------------------------------------------------------- + generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r + always @(posedge S_ACLK or S_ARESETN) begin + if (S_ARESETN == 1'b1) begin + bvalid_r <= 0; + bvalid_d1_c <= 0; + end else begin + // Delay the generation o bvalid_r for generation for BID + bvalid_d1_c <= bvalid_c; + + //external bvalid signal generation + if (bvalid_d1_c == 1'b1) begin + bvalid_r <= #FLOP_DELAY 1'b1 ; + end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin + bvalid_r <= #FLOP_DELAY 0 ; + end + end + end + end + endgenerate + + //------------------------------------------------------------------------- + // Generation of bvalid when BID is not used + //------------------------------------------------------------------------- + generate if(C_HAS_AXI_ID == 0) begin:gaxi_bvalid_noid_r + always @(posedge S_ACLK or S_ARESETN) begin + if (S_ARESETN == 1'b1) begin + bvalid_r <= 0; + end else begin + //external bvalid signal generation + if (bvalid_c == 1'b1) begin + bvalid_r <= #FLOP_DELAY 1'b1 ; + end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin + bvalid_r <= #FLOP_DELAY 0 ; + end + end + end + end + endgenerate + + //------------------------------------------------------------------------- + // Generation of Bready timeout + //------------------------------------------------------------------------- + always @(bvalid_count_r) begin + // bready_timeout_c generation + if(bvalid_count_r == C_AXI_OS_WR-1) begin + bready_timeout_c <= 1'b1; + end else begin + bready_timeout_c <= 1'b0; + end + end + + //------------------------------------------------------------------------- + // Generation of BID + //------------------------------------------------------------------------- + generate if(C_HAS_AXI_ID == 1) begin:gaxi_bid_gen + + always @(posedge S_ACLK or S_ARESETN) begin + if (S_ARESETN == 1'b1) begin + bvalid_wr_cnt_r <= 0; + bvalid_rd_cnt_r <= 0; + end else begin + // STORE AWID IN AN ARRAY + if(bvalid_c == 1'b1) begin + bvalid_wr_cnt_r <= bvalid_wr_cnt_r + 1; + end + // generate BID FROM AWID ARRAY + bvalid_rd_cnt_r <= #FLOP_DELAY bvalid_rd_cnt_c ; + S_AXI_BID <= axi_bid_array[bvalid_rd_cnt_c]; + end + end + + assign bvalid_rd_cnt_c = (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1)?bvalid_rd_cnt_r+1:bvalid_rd_cnt_r; + + //------------------------------------------------------------------------- + // Storing AWID for generation of BID + //------------------------------------------------------------------------- + always @(posedge S_ACLK or S_ARESETN) begin + if(S_ARESETN == 1'b1) begin + axi_bid_array[0] = 0; + axi_bid_array[1] = 0; + axi_bid_array[2] = 0; + axi_bid_array[3] = 0; + end else if(aw_ready_r == 1'b1 && S_AXI_AWVALID == 1'b1) begin + axi_bid_array[bvalid_wr_cnt_r] <= S_AXI_AWID; + end + end + + end + endgenerate + + assign S_AXI_BVALID = bvalid_r; + assign S_AXI_AWREADY = aw_ready_r; + + endmodule + +module blk_mem_axi_read_wrapper_beh_v8_4 +# ( + //// AXI Interface related parameters start here + parameter C_INTERFACE_TYPE = 0, + parameter C_AXI_TYPE = 0, + parameter C_AXI_SLAVE_TYPE = 0, + parameter C_MEMORY_TYPE = 0, + parameter C_WRITE_WIDTH_A = 4, + parameter C_WRITE_DEPTH_A = 32, + parameter C_ADDRA_WIDTH = 12, + parameter C_AXI_PIPELINE_STAGES = 0, + parameter C_AXI_ARADDR_WIDTH = 12, + parameter C_HAS_AXI_ID = 0, + parameter C_AXI_ID_WIDTH = 4, + parameter C_ADDRB_WIDTH = 12 + ) + ( + + //// AXI Global Signals + input S_ACLK, + input S_ARESETN, + //// AXI Full/Lite Slave Read (Read side) + input [C_AXI_ARADDR_WIDTH-1:0] S_AXI_ARADDR, + input [7:0] S_AXI_ARLEN, + input [2:0] S_AXI_ARSIZE, + input [1:0] S_AXI_ARBURST, + input S_AXI_ARVALID, + output S_AXI_ARREADY, + output S_AXI_RLAST, + output S_AXI_RVALID, + input S_AXI_RREADY, + input [C_AXI_ID_WIDTH-1:0] S_AXI_ARID, + output reg [C_AXI_ID_WIDTH-1:0] S_AXI_RID = 0, + //// AXI Full/Lite Read Address Signals to BRAM + output [C_ADDRB_WIDTH-1:0] S_AXI_ARADDR_OUT, + output S_AXI_RD_EN + ); + + localparam FLOP_DELAY = 100; // 100 ps + localparam C_RANGE = ((C_WRITE_WIDTH_A == 8)?0: + ((C_WRITE_WIDTH_A==16)?1: + ((C_WRITE_WIDTH_A==32)?2: + ((C_WRITE_WIDTH_A==64)?3: + ((C_WRITE_WIDTH_A==128)?4: + ((C_WRITE_WIDTH_A==256)?5:0)))))); + + + + reg [C_AXI_ID_WIDTH-1:0] ar_id_r=0; + wire addr_en_c; + wire rd_en_c; + wire incr_addr_c; + wire single_trans_c; + wire dec_alen_c; + wire mux_sel_c; + wire r_last_c; + wire r_last_int_c; + wire [C_ADDRB_WIDTH-1 : 0] araddr_out; + + reg [7:0] arlen_int_r=0; + reg [7:0] arlen_cntr=8'h01; + reg [1:0] arburst_int_c=0; + reg [1:0] arburst_int_r=0; + reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)? + C_AXI_ARADDR_WIDTH:C_ADDRA_WIDTH)-1:0] araddr_reg =0; + integer num_of_bytes_c = 0; + integer total_bytes = 0; + integer num_of_bytes_r = 0; + integer wrap_base_addr_r = 0; + integer wrap_boundary_r = 0; + + reg [7:0] arlen_int_c=0; + integer total_bytes_c = 0; + integer wrap_base_addr_c = 0; + integer wrap_boundary_c = 0; + + assign dec_alen_c = incr_addr_c | r_last_int_c; + + + read_netlist_v8_4 + #(.C_AXI_TYPE (1), + .C_ADDRB_WIDTH (C_ADDRB_WIDTH)) + axi_read_fsm ( + .S_AXI_INCR_ADDR(incr_addr_c), + .S_AXI_ADDR_EN(addr_en_c), + .S_AXI_SINGLE_TRANS(single_trans_c), + .S_AXI_MUX_SEL(mux_sel_c), + .S_AXI_R_LAST(r_last_c), + .S_AXI_R_LAST_INT(r_last_int_c), + + //// AXI Global Signals + .S_ACLK(S_ACLK), + .S_ARESETN(S_ARESETN), + //// AXI Full/Lite Slave Read (Read side) + .S_AXI_ARLEN(S_AXI_ARLEN), + .S_AXI_ARVALID(S_AXI_ARVALID), + .S_AXI_ARREADY(S_AXI_ARREADY), + .S_AXI_RLAST(S_AXI_RLAST), + .S_AXI_RVALID(S_AXI_RVALID), + .S_AXI_RREADY(S_AXI_RREADY), + //// AXI Full/Lite Read Address Signals to BRAM + .S_AXI_RD_EN(rd_en_c) + ); + + always@(*) begin + num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARSIZE:0); + total_bytes = (num_of_bytes_r)*(arlen_int_r+1); + wrap_base_addr_r = ((araddr_reg)/(total_bytes==0?1:total_bytes))*(total_bytes); + wrap_boundary_r = wrap_base_addr_r+total_bytes; + + //////// combinatorial from interface + arlen_int_c = (C_AXI_TYPE == 0?0:S_AXI_ARLEN); + total_bytes_c = (num_of_bytes_c)*(arlen_int_c+1); + wrap_base_addr_c = ((S_AXI_ARADDR)/(total_bytes_c==0?1:total_bytes_c))*(total_bytes_c); + wrap_boundary_c = wrap_base_addr_c+total_bytes_c; + + arburst_int_c = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARBURST:1); + end + + ////------------------------------------------------------------------------- + //// BMG address generation + ////------------------------------------------------------------------------- + always @(posedge S_ACLK or S_ARESETN) begin + if (S_ARESETN == 1'b1) begin + araddr_reg <= 0; + arburst_int_r <= 0; + num_of_bytes_r <= 0; + end else begin + if (incr_addr_c == 1'b1 && addr_en_c == 1'b1 && single_trans_c == 1'b0) begin + arburst_int_r <= arburst_int_c; + num_of_bytes_r <= num_of_bytes_c; + if (arburst_int_c == 2'b10) begin + if(S_AXI_ARADDR == (wrap_boundary_c-num_of_bytes_c)) begin + araddr_reg <= wrap_base_addr_c; + end else begin + araddr_reg <= S_AXI_ARADDR + num_of_bytes_c; + end + end else if (arburst_int_c == 2'b01 || arburst_int_c == 2'b11) begin + araddr_reg <= S_AXI_ARADDR + num_of_bytes_c; + end + + end else if (addr_en_c == 1'b1) begin + araddr_reg <= S_AXI_ARADDR; + num_of_bytes_r <= num_of_bytes_c; + arburst_int_r <= arburst_int_c; + end else if (incr_addr_c == 1'b1) begin + if (arburst_int_r == 2'b10) begin + if(araddr_reg == (wrap_boundary_r-num_of_bytes_r)) begin + araddr_reg <= wrap_base_addr_r; + end else begin + araddr_reg <= araddr_reg + num_of_bytes_r; + end + end else if (arburst_int_r == 2'b01 || arburst_int_r == 2'b11) begin + araddr_reg <= araddr_reg + num_of_bytes_r; + end + end + end + end + +assign araddr_out = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?araddr_reg[C_AXI_ARADDR_WIDTH-1:C_RANGE]:araddr_reg); + + + ////----------------------------------------------------------------------- + //// Counter to generate r_last_int_c from registered ARLEN - AXI FULL FSM + ////----------------------------------------------------------------------- + always @(posedge S_ACLK or S_ARESETN) begin + if (S_ARESETN == 1'b1) begin + arlen_cntr <= 8'h01; + arlen_int_r <= 0; + end else begin + if (addr_en_c == 1'b1 && dec_alen_c == 1'b1 && single_trans_c == 1'b0) begin + arlen_int_r <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ; + arlen_cntr <= S_AXI_ARLEN - 1'b1; + end else if (addr_en_c == 1'b1) begin + arlen_int_r <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ; + arlen_cntr <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ; + end else if (dec_alen_c == 1'b1) begin + arlen_cntr <= arlen_cntr - 1'b1 ; + end + else begin + arlen_cntr <= arlen_cntr; + end + end + end + + assign r_last_int_c = (arlen_cntr == 0 && S_AXI_RREADY == 1'b1)?1'b1:1'b0; + + + ////------------------------------------------------------------------------ + //// AXI FULL FSM + //// Mux Selection of ARADDR + //// ARADDR is driven out from the read fsm based on the mux_sel_c + //// Based on mux_sel either ARADDR is given out or the latched ARADDR is + //// given out to BRAM + ////------------------------------------------------------------------------ + assign S_AXI_ARADDR_OUT = (mux_sel_c == 1'b0)?((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARADDR[C_AXI_ARADDR_WIDTH-1:C_RANGE]:S_AXI_ARADDR):araddr_out; + + ////------------------------------------------------------------------------ + //// Assign output signals - AXI FULL FSM + ////------------------------------------------------------------------------ + assign S_AXI_RD_EN = rd_en_c; + + generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r + always @(posedge S_ACLK or S_ARESETN) begin + if (S_ARESETN == 1'b1) begin + S_AXI_RID <= 0; + ar_id_r <= 0; + end else begin + if (addr_en_c == 1'b1 && rd_en_c == 1'b1) begin + S_AXI_RID <= S_AXI_ARID; + ar_id_r <= S_AXI_ARID; + end else if (addr_en_c == 1'b1 && rd_en_c == 1'b0) begin + ar_id_r <= S_AXI_ARID; + end else if (rd_en_c == 1'b1) begin + S_AXI_RID <= ar_id_r; + end + end + end + end + endgenerate + +endmodule + +module blk_mem_axi_regs_fwd_v8_4 + #(parameter C_DATA_WIDTH = 8 + )( + input ACLK, + input ARESET, + input S_VALID, + output S_READY, + input [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA, + output M_VALID, + input M_READY, + output reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA + ); + + reg [C_DATA_WIDTH-1:0] STORAGE_DATA; + wire S_READY_I; + reg M_VALID_I; + reg [1:0] ARESET_D; + + //assign local signal to its output signal + assign S_READY = S_READY_I; + assign M_VALID = M_VALID_I; + + always @(posedge ACLK) begin + ARESET_D <= {ARESET_D[0], ARESET}; + end + + //Save payload data whenever we have a transaction on the slave side + always @(posedge ACLK or ARESET) begin + if (ARESET == 1'b1) begin + STORAGE_DATA <= 0; + end else begin + if(S_VALID == 1'b1 && S_READY_I == 1'b1 ) begin + STORAGE_DATA <= S_PAYLOAD_DATA; + end + end + end + + always @(posedge ACLK) begin + M_PAYLOAD_DATA = STORAGE_DATA; + end + + //M_Valid set to high when we have a completed transfer on slave side + //Is removed on a M_READY except if we have a new transfer on the slave side + + always @(posedge ACLK or ARESET_D) begin + if (ARESET_D != 2'b00) begin + M_VALID_I <= 1'b0; + end else begin + if (S_VALID == 1'b1) begin + //Always set M_VALID_I when slave side is valid + M_VALID_I <= 1'b1; + end else if (M_READY == 1'b1 ) begin + //Clear (or keep) when no slave side is valid but master side is ready + M_VALID_I <= 1'b0; + end + end + end + + //Slave Ready is either when Master side drives M_READY or we have space in our storage data + assign S_READY_I = (M_READY || (!M_VALID_I)) && !(|(ARESET_D)); + + endmodule + +//***************************************************************************** +// Output Register Stage module +// +// This module builds the output register stages of the memory. This module is +// instantiated in the main memory module (blk_mem_gen_v8_4_3) which is +// declared/implemented further down in this file. +//***************************************************************************** +module blk_mem_gen_v8_4_3_output_stage + #(parameter C_FAMILY = "virtex7", + parameter C_XDEVICEFAMILY = "virtex7", + parameter C_RST_TYPE = "SYNC", + parameter C_HAS_RST = 0, + parameter C_RSTRAM = 0, + parameter C_RST_PRIORITY = "CE", + parameter C_INIT_VAL = "0", + parameter C_HAS_EN = 0, + parameter C_HAS_REGCE = 0, + parameter C_DATA_WIDTH = 32, + parameter C_ADDRB_WIDTH = 10, + parameter C_HAS_MEM_OUTPUT_REGS = 0, + parameter C_USE_SOFTECC = 0, + parameter C_USE_ECC = 0, + parameter NUM_STAGES = 1, + parameter C_EN_ECC_PIPE = 0, + parameter FLOP_DELAY = 100 + ) + ( + input CLK, + input RST, + input EN, + input REGCE, + input [C_DATA_WIDTH-1:0] DIN_I, + output reg [C_DATA_WIDTH-1:0] DOUT, + input SBITERR_IN_I, + input DBITERR_IN_I, + output reg SBITERR, + output reg DBITERR, + input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN_I, + input ECCPIPECE, + output reg [C_ADDRB_WIDTH-1:0] RDADDRECC +); + +//****************************** +// Port and Generic Definitions +//****************************** + ////////////////////////////////////////////////////////////////////////// + // Generic Definitions + ////////////////////////////////////////////////////////////////////////// + // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following + // options are available - "spartan3", "spartan6", + // "virtex4", "virtex5", "virtex6" and "virtex6l". + // C_RST_TYPE : Type of reset - Synchronous or Asynchronous + // C_HAS_RST : Determines the presence of the RST port + // C_RSTRAM : Determines if special reset behavior is used + // C_RST_PRIORITY : Determines the priority between CE and SR + // C_INIT_VAL : Initialization value + // C_HAS_EN : Determines the presence of the EN port + // C_HAS_REGCE : Determines the presence of the REGCE port + // C_DATA_WIDTH : Memory write/read width + // C_ADDRB_WIDTH : Width of the ADDRB input port + // C_HAS_MEM_OUTPUT_REGS : Designates the use of a register at the output + // of the RAM primitive + // C_USE_SOFTECC : Determines if the Soft ECC feature is used or + // not. Only applicable Spartan-6 + // C_USE_ECC : Determines if the ECC feature is used or + // not. Only applicable for V5 and V6 + // NUM_STAGES : Determines the number of output stages + // FLOP_DELAY : Constant delay for register assignments + ////////////////////////////////////////////////////////////////////////// + // Port Definitions + ////////////////////////////////////////////////////////////////////////// + // CLK : Clock to synchronize all read and write operations + // RST : Reset input to reset memory outputs to a user-defined + // reset state + // EN : Enable all read and write operations + // REGCE : Register Clock Enable to control each pipeline output + // register stages + // DIN : Data input to the Output stage. + // DOUT : Final Data output + // SBITERR_IN : SBITERR input signal to the Output stage. + // SBITERR : Final SBITERR Output signal. + // DBITERR_IN : DBITERR input signal to the Output stage. + // DBITERR : Final DBITERR Output signal. + // RDADDRECC_IN : RDADDRECC input signal to the Output stage. + // RDADDRECC : Final RDADDRECC Output signal. + ////////////////////////////////////////////////////////////////////////// + +// Fix for CR-509792 + + localparam REG_STAGES = (NUM_STAGES < 2) ? 1 : NUM_STAGES-1; + + // Declare the pipeline registers + // (includes mem output reg, mux pipeline stages, and mux output reg) + reg [C_DATA_WIDTH*REG_STAGES-1:0] out_regs; + reg [C_ADDRB_WIDTH*REG_STAGES-1:0] rdaddrecc_regs; + reg [REG_STAGES-1:0] sbiterr_regs; + reg [REG_STAGES-1:0] dbiterr_regs; + + reg [C_DATA_WIDTH*8-1:0] init_str = C_INIT_VAL; + reg [C_DATA_WIDTH-1:0] init_val ; + + //********************************************* + // Wire off optional inputs based on parameters + //********************************************* + wire en_i; + wire regce_i; + wire rst_i; + + // Internal signals + reg [C_DATA_WIDTH-1:0] DIN; + reg [C_ADDRB_WIDTH-1:0] RDADDRECC_IN; + reg SBITERR_IN; + reg DBITERR_IN; + + + // Internal enable for output registers is tied to user EN or '1' depending + // on parameters + assign en_i = (C_HAS_EN==0 || EN); + + // Internal register enable for output registers is tied to user REGCE, EN or + // '1' depending on parameters + // For V4 ECC, REGCE is always 1 + // Virtex-4 ECC Not Yet Supported + assign regce_i = ((C_HAS_REGCE==1) && REGCE) || + ((C_HAS_REGCE==0) && (C_HAS_EN==0 || EN)); + + //Internal SRR is tied to user RST or '0' depending on parameters + assign rst_i = (C_HAS_RST==1) && RST; + + //**************************************************** + // Power on: load up the output registers and latches + //**************************************************** + initial begin + if (!($sscanf(init_str, "%h", init_val))) begin + init_val = 0; + end + DOUT = init_val; + RDADDRECC = 0; + SBITERR = 1'b0; + DBITERR = 1'b0; + DIN = {(C_DATA_WIDTH){1'b0}}; + RDADDRECC_IN = 0; + SBITERR_IN = 0; + DBITERR_IN = 0; + // This will be one wider than need, but 0 is an error + out_regs = {(REG_STAGES+1){init_val}}; + rdaddrecc_regs = 0; + sbiterr_regs = {(REG_STAGES+1){1'b0}}; + dbiterr_regs = {(REG_STAGES+1){1'b0}}; + end + + //*********************************************** + // NUM_STAGES = 0 (No output registers. RAM only) + //*********************************************** + generate if (NUM_STAGES == 0) begin : zero_stages + always @* begin + DOUT = DIN; + RDADDRECC = RDADDRECC_IN; + SBITERR = SBITERR_IN; + DBITERR = DBITERR_IN; + end + end + endgenerate + + generate if (C_EN_ECC_PIPE == 0) begin : no_ecc_pipe_reg + always @* begin + DIN = DIN_I; + SBITERR_IN = SBITERR_IN_I; + DBITERR_IN = DBITERR_IN_I; + RDADDRECC_IN = RDADDRECC_IN_I; + end + end + endgenerate + + generate if (C_EN_ECC_PIPE == 1) begin : with_ecc_pipe_reg + always @(posedge CLK) begin + if(ECCPIPECE == 1) begin + DIN <= #FLOP_DELAY DIN_I; + SBITERR_IN <= #FLOP_DELAY SBITERR_IN_I; + DBITERR_IN <= #FLOP_DELAY DBITERR_IN_I; + RDADDRECC_IN <= #FLOP_DELAY RDADDRECC_IN_I; + end + end + end + endgenerate + + + //*********************************************** + // NUM_STAGES = 1 + // (Mem Output Reg only or Mux Output Reg only) + //*********************************************** + + // Possible valid combinations: + // Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1) + // +-----------------------------------------+ + // | C_RSTRAM_* | Reset Behavior | + // +----------------+------------------------+ + // | 0 | Normal Behavior | + // +----------------+------------------------+ + // | 1 | Special Behavior | + // +----------------+------------------------+ + // + // Normal = REGCE gates reset, as in the case of all families except S3ADSP. + // Special = EN gates reset, as in the case of S3ADSP. + + generate if (NUM_STAGES == 1 && + (C_RSTRAM == 0 || (C_RSTRAM == 1 && (C_XDEVICEFAMILY != "spartan3adsp" && C_XDEVICEFAMILY != "aspartan3adsp" )) || + C_HAS_MEM_OUTPUT_REGS == 0 || C_HAS_RST == 0)) + begin : one_stages_norm + + always @(posedge CLK) begin + if (C_RST_PRIORITY == "CE") begin //REGCE has priority + if (regce_i && rst_i) begin + DOUT <= #FLOP_DELAY init_val; + RDADDRECC <= #FLOP_DELAY 0; + SBITERR <= #FLOP_DELAY 1'b0; + DBITERR <= #FLOP_DELAY 1'b0; + end else if (regce_i) begin + DOUT <= #FLOP_DELAY DIN; + RDADDRECC <= #FLOP_DELAY RDADDRECC_IN; + SBITERR <= #FLOP_DELAY SBITERR_IN; + DBITERR <= #FLOP_DELAY DBITERR_IN; + end //Output signal assignments + end else begin //RST has priority + if (rst_i) begin + DOUT <= #FLOP_DELAY init_val; + RDADDRECC <= #FLOP_DELAY RDADDRECC_IN; + SBITERR <= #FLOP_DELAY 1'b0; + DBITERR <= #FLOP_DELAY 1'b0; + end else if (regce_i) begin + DOUT <= #FLOP_DELAY DIN; + RDADDRECC <= #FLOP_DELAY RDADDRECC_IN; + SBITERR <= #FLOP_DELAY SBITERR_IN; + DBITERR <= #FLOP_DELAY DBITERR_IN; + end //Output signal assignments + end //end Priority conditions + end //end RST Type conditions + end //end one_stages_norm generate statement + endgenerate + + // Special Reset Behavior for S3ADSP + generate if (NUM_STAGES == 1 && C_RSTRAM == 1 && (C_XDEVICEFAMILY =="spartan3adsp" || C_XDEVICEFAMILY =="aspartan3adsp")) + begin : one_stage_splbhv + always @(posedge CLK) begin + if (en_i && rst_i) begin + DOUT <= #FLOP_DELAY init_val; + end else if (regce_i && !rst_i) begin + DOUT <= #FLOP_DELAY DIN; + end //Output signal assignments + end //end CLK + end //end one_stage_splbhv generate statement + endgenerate + + //************************************************************ + // NUM_STAGES > 1 + // Mem Output Reg + Mux Output Reg + // or + // Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg + // or + // Mux Pipeline Stages (>0) + Mux Output Reg + //************************************************************* + generate if (NUM_STAGES > 1) begin : multi_stage + //Asynchronous Reset + always @(posedge CLK) begin + if (C_RST_PRIORITY == "CE") begin //REGCE has priority + if (regce_i && rst_i) begin + DOUT <= #FLOP_DELAY init_val; + RDADDRECC <= #FLOP_DELAY 0; + SBITERR <= #FLOP_DELAY 1'b0; + DBITERR <= #FLOP_DELAY 1'b0; + end else if (regce_i) begin + DOUT <= #FLOP_DELAY + out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH]; + RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH]; + SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2]; + DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2]; + end //Output signal assignments + end else begin //RST has priority + if (rst_i) begin + DOUT <= #FLOP_DELAY init_val; + RDADDRECC <= #FLOP_DELAY 0; + SBITERR <= #FLOP_DELAY 1'b0; + DBITERR <= #FLOP_DELAY 1'b0; + end else if (regce_i) begin + DOUT <= #FLOP_DELAY + out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH]; + RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH]; + SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2]; + DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2]; + end //Output signal assignments + end //end Priority conditions + // Shift the data through the output stages + if (en_i) begin + out_regs <= #FLOP_DELAY (out_regs << C_DATA_WIDTH) | DIN; + rdaddrecc_regs <= #FLOP_DELAY (rdaddrecc_regs << C_ADDRB_WIDTH) | RDADDRECC_IN; + sbiterr_regs <= #FLOP_DELAY (sbiterr_regs << 1) | SBITERR_IN; + dbiterr_regs <= #FLOP_DELAY (dbiterr_regs << 1) | DBITERR_IN; + end + end //end CLK + end //end multi_stage generate statement + endgenerate +endmodule + +module blk_mem_gen_v8_4_3_softecc_output_reg_stage + #(parameter C_DATA_WIDTH = 32, + parameter C_ADDRB_WIDTH = 10, + parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0, + parameter C_USE_SOFTECC = 0, + parameter FLOP_DELAY = 100 + ) + ( + input CLK, + input [C_DATA_WIDTH-1:0] DIN, + output reg [C_DATA_WIDTH-1:0] DOUT, + input SBITERR_IN, + input DBITERR_IN, + output reg SBITERR, + output reg DBITERR, + input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN, + output reg [C_ADDRB_WIDTH-1:0] RDADDRECC +); + +//****************************** +// Port and Generic Definitions +//****************************** + ////////////////////////////////////////////////////////////////////////// + // Generic Definitions + ////////////////////////////////////////////////////////////////////////// + // C_DATA_WIDTH : Memory write/read width + // C_ADDRB_WIDTH : Width of the ADDRB input port + // C_HAS_SOFTECC_OUTPUT_REGS_B : Designates the use of a register at the output + // of the RAM primitive + // C_USE_SOFTECC : Determines if the Soft ECC feature is used or + // not. Only applicable Spartan-6 + // FLOP_DELAY : Constant delay for register assignments + ////////////////////////////////////////////////////////////////////////// + // Port Definitions + ////////////////////////////////////////////////////////////////////////// + // CLK : Clock to synchronize all read and write operations + // DIN : Data input to the Output stage. + // DOUT : Final Data output + // SBITERR_IN : SBITERR input signal to the Output stage. + // SBITERR : Final SBITERR Output signal. + // DBITERR_IN : DBITERR input signal to the Output stage. + // DBITERR : Final DBITERR Output signal. + // RDADDRECC_IN : RDADDRECC input signal to the Output stage. + // RDADDRECC : Final RDADDRECC Output signal. + ////////////////////////////////////////////////////////////////////////// + + reg [C_DATA_WIDTH-1:0] dout_i = 0; + reg sbiterr_i = 0; + reg dbiterr_i = 0; + reg [C_ADDRB_WIDTH-1:0] rdaddrecc_i = 0; + + //*********************************************** + // NO OUTPUT REGISTERS. + //*********************************************** + generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==0) begin : no_output_stage + always @* begin + DOUT = DIN; + RDADDRECC = RDADDRECC_IN; + SBITERR = SBITERR_IN; + DBITERR = DBITERR_IN; + end + end + endgenerate + + //*********************************************** + // WITH OUTPUT REGISTERS. + //*********************************************** + generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==1) begin : has_output_stage + always @(posedge CLK) begin + dout_i <= #FLOP_DELAY DIN; + rdaddrecc_i <= #FLOP_DELAY RDADDRECC_IN; + sbiterr_i <= #FLOP_DELAY SBITERR_IN; + dbiterr_i <= #FLOP_DELAY DBITERR_IN; + end + + always @* begin + DOUT = dout_i; + RDADDRECC = rdaddrecc_i; + SBITERR = sbiterr_i; + DBITERR = dbiterr_i; + end //end always + end //end in_or_out_stage generate statement + endgenerate + +endmodule + + +//***************************************************************************** +// Main Memory module +// +// This module is the top-level behavioral model and this implements the RAM +//***************************************************************************** +module blk_mem_gen_v8_4_3_mem_module + #(parameter C_CORENAME = "blk_mem_gen_v8_4_3", + parameter C_FAMILY = "virtex7", + parameter C_XDEVICEFAMILY = "virtex7", + parameter C_MEM_TYPE = 2, + parameter C_BYTE_SIZE = 9, + parameter C_USE_BRAM_BLOCK = 0, + parameter C_ALGORITHM = 1, + parameter C_PRIM_TYPE = 3, + parameter C_LOAD_INIT_FILE = 0, + parameter C_INIT_FILE_NAME = "", + parameter C_INIT_FILE = "", + parameter C_USE_DEFAULT_DATA = 0, + parameter C_DEFAULT_DATA = "0", + parameter C_RST_TYPE = "SYNC", + parameter C_HAS_RSTA = 0, + parameter C_RST_PRIORITY_A = "CE", + parameter C_RSTRAM_A = 0, + parameter C_INITA_VAL = "0", + parameter C_HAS_ENA = 1, + parameter C_HAS_REGCEA = 0, + parameter C_USE_BYTE_WEA = 0, + parameter C_WEA_WIDTH = 1, + parameter C_WRITE_MODE_A = "WRITE_FIRST", + parameter C_WRITE_WIDTH_A = 32, + parameter C_READ_WIDTH_A = 32, + parameter C_WRITE_DEPTH_A = 64, + parameter C_READ_DEPTH_A = 64, + parameter C_ADDRA_WIDTH = 5, + parameter C_HAS_RSTB = 0, + parameter C_RST_PRIORITY_B = "CE", + parameter C_RSTRAM_B = 0, + parameter C_INITB_VAL = "", + parameter C_HAS_ENB = 1, + parameter C_HAS_REGCEB = 0, + parameter C_USE_BYTE_WEB = 0, + parameter C_WEB_WIDTH = 1, + parameter C_WRITE_MODE_B = "WRITE_FIRST", + parameter C_WRITE_WIDTH_B = 32, + parameter C_READ_WIDTH_B = 32, + parameter C_WRITE_DEPTH_B = 64, + parameter C_READ_DEPTH_B = 64, + parameter C_ADDRB_WIDTH = 5, + parameter C_HAS_MEM_OUTPUT_REGS_A = 0, + parameter C_HAS_MEM_OUTPUT_REGS_B = 0, + parameter C_HAS_MUX_OUTPUT_REGS_A = 0, + parameter C_HAS_MUX_OUTPUT_REGS_B = 0, + parameter C_HAS_SOFTECC_INPUT_REGS_A = 0, + parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0, + parameter C_MUX_PIPELINE_STAGES = 0, + parameter C_USE_SOFTECC = 0, + parameter C_USE_ECC = 0, + parameter C_HAS_INJECTERR = 0, + parameter C_SIM_COLLISION_CHECK = "NONE", + parameter C_COMMON_CLK = 1, + parameter FLOP_DELAY = 100, + parameter C_DISABLE_WARN_BHV_COLL = 0, + parameter C_EN_ECC_PIPE = 0, + parameter C_DISABLE_WARN_BHV_RANGE = 0 + ) + (input CLKA, + input RSTA, + input ENA, + input REGCEA, + input [C_WEA_WIDTH-1:0] WEA, + input [C_ADDRA_WIDTH-1:0] ADDRA, + input [C_WRITE_WIDTH_A-1:0] DINA, + output [C_READ_WIDTH_A-1:0] DOUTA, + input CLKB, + input RSTB, + input ENB, + input REGCEB, + input [C_WEB_WIDTH-1:0] WEB, + input [C_ADDRB_WIDTH-1:0] ADDRB, + input [C_WRITE_WIDTH_B-1:0] DINB, + output [C_READ_WIDTH_B-1:0] DOUTB, + input INJECTSBITERR, + input INJECTDBITERR, + input ECCPIPECE, + input SLEEP, + output SBITERR, + output DBITERR, + output [C_ADDRB_WIDTH-1:0] RDADDRECC + ); +//****************************** +// Port and Generic Definitions +//****************************** + ////////////////////////////////////////////////////////////////////////// + // Generic Definitions + ////////////////////////////////////////////////////////////////////////// + // C_CORENAME : Instance name of the Block Memory Generator core + // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following + // options are available - "spartan3", "spartan6", + // "virtex4", "virtex5", "virtex6" and "virtex6l". + // C_MEM_TYPE : Designates memory type. + // It can be + // 0 - Single Port Memory + // 1 - Simple Dual Port Memory + // 2 - True Dual Port Memory + // 3 - Single Port Read Only Memory + // 4 - Dual Port Read Only Memory + // C_BYTE_SIZE : Size of a byte (8 or 9 bits) + // C_ALGORITHM : Designates the algorithm method used + // for constructing the memory. + // It can be Fixed_Primitives, Minimum_Area or + // Low_Power + // C_PRIM_TYPE : Designates the user selected primitive used to + // construct the memory. + // + // C_LOAD_INIT_FILE : Designates the use of an initialization file to + // initialize memory contents. + // C_INIT_FILE_NAME : Memory initialization file name. + // C_USE_DEFAULT_DATA : Designates whether to fill remaining + // initialization space with default data + // C_DEFAULT_DATA : Default value of all memory locations + // not initialized by the memory + // initialization file. + // C_RST_TYPE : Type of reset - Synchronous or Asynchronous + // C_HAS_RSTA : Determines the presence of the RSTA port + // C_RST_PRIORITY_A : Determines the priority between CE and SR for + // Port A. + // C_RSTRAM_A : Determines if special reset behavior is used for + // Port A + // C_INITA_VAL : The initialization value for Port A + // C_HAS_ENA : Determines the presence of the ENA port + // C_HAS_REGCEA : Determines the presence of the REGCEA port + // C_USE_BYTE_WEA : Determines if the Byte Write is used or not. + // C_WEA_WIDTH : The width of the WEA port + // C_WRITE_MODE_A : Configurable write mode for Port A. It can be + // WRITE_FIRST, READ_FIRST or NO_CHANGE. + // C_WRITE_WIDTH_A : Memory write width for Port A. + // C_READ_WIDTH_A : Memory read width for Port A. + // C_WRITE_DEPTH_A : Memory write depth for Port A. + // C_READ_DEPTH_A : Memory read depth for Port A. + // C_ADDRA_WIDTH : Width of the ADDRA input port + // C_HAS_RSTB : Determines the presence of the RSTB port + // C_RST_PRIORITY_B : Determines the priority between CE and SR for + // Port B. + // C_RSTRAM_B : Determines if special reset behavior is used for + // Port B + // C_INITB_VAL : The initialization value for Port B + // C_HAS_ENB : Determines the presence of the ENB port + // C_HAS_REGCEB : Determines the presence of the REGCEB port + // C_USE_BYTE_WEB : Determines if the Byte Write is used or not. + // C_WEB_WIDTH : The width of the WEB port + // C_WRITE_MODE_B : Configurable write mode for Port B. It can be + // WRITE_FIRST, READ_FIRST or NO_CHANGE. + // C_WRITE_WIDTH_B : Memory write width for Port B. + // C_READ_WIDTH_B : Memory read width for Port B. + // C_WRITE_DEPTH_B : Memory write depth for Port B. + // C_READ_DEPTH_B : Memory read depth for Port B. + // C_ADDRB_WIDTH : Width of the ADDRB input port + // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output + // of the RAM primitive for Port A. + // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output + // of the RAM primitive for Port B. + // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output + // of the MUX for Port A. + // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output + // of the MUX for Port B. + // C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in + // between the muxes. + // C_USE_SOFTECC : Determines if the Soft ECC feature is used or + // not. Only applicable Spartan-6 + // C_USE_ECC : Determines if the ECC feature is used or + // not. Only applicable for V5 and V6 + // C_HAS_INJECTERR : Determines if the error injection pins + // are present or not. If the ECC feature + // is not used, this value is defaulted to + // 0, else the following are the allowed + // values: + // 0 : No INJECTSBITERR or INJECTDBITERR pins + // 1 : Only INJECTSBITERR pin exists + // 2 : Only INJECTDBITERR pin exists + // 3 : Both INJECTSBITERR and INJECTDBITERR pins exist + // C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision + // warnings. It can be "ALL", "NONE", + // "Warnings_Only" or "Generate_X_Only". + // C_COMMON_CLK : Determins if the core has a single CLK input. + // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings + // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range + // warnings + ////////////////////////////////////////////////////////////////////////// + // Port Definitions + ////////////////////////////////////////////////////////////////////////// + // CLKA : Clock to synchronize all read and write operations of Port A. + // RSTA : Reset input to reset memory outputs to a user-defined + // reset state for Port A. + // ENA : Enable all read and write operations of Port A. + // REGCEA : Register Clock Enable to control each pipeline output + // register stages for Port A. + // WEA : Write Enable to enable all write operations of Port A. + // ADDRA : Address of Port A. + // DINA : Data input of Port A. + // DOUTA : Data output of Port A. + // CLKB : Clock to synchronize all read and write operations of Port B. + // RSTB : Reset input to reset memory outputs to a user-defined + // reset state for Port B. + // ENB : Enable all read and write operations of Port B. + // REGCEB : Register Clock Enable to control each pipeline output + // register stages for Port B. + // WEB : Write Enable to enable all write operations of Port B. + // ADDRB : Address of Port B. + // DINB : Data input of Port B. + // DOUTB : Data output of Port B. + // INJECTSBITERR : Single Bit ECC Error Injection Pin. + // INJECTDBITERR : Double Bit ECC Error Injection Pin. + // SBITERR : Output signal indicating that a Single Bit ECC Error has been + // detected and corrected. + // DBITERR : Output signal indicating that a Double Bit ECC Error has been + // detected. + // RDADDRECC : Read Address Output signal indicating address at which an + // ECC error has occurred. + ////////////////////////////////////////////////////////////////////////// + + +// Note: C_CORENAME parameter is hard-coded to "blk_mem_gen_v8_4_3" and it is +// only used by this module to print warning messages. It is neither passed +// down from blk_mem_gen_v8_4_3_xst.v nor present in the instantiation template +// coregen generates + + //*************************************************************************** + // constants for the core behavior + //*************************************************************************** + // file handles for logging + //-------------------------------------------------- + localparam ADDRFILE = 32'h8000_0001; //stdout for addr out of range + localparam COLLFILE = 32'h8000_0001; //stdout for coll detection + localparam ERRFILE = 32'h8000_0001; //stdout for file I/O errors + + // other constants + //-------------------------------------------------- + localparam COLL_DELAY = 100; // 100 ps + + // locally derived parameters to determine memory shape + //----------------------------------------------------- + + localparam CHKBIT_WIDTH = (C_WRITE_WIDTH_A>57 ? 8 : (C_WRITE_WIDTH_A>26 ? 7 : (C_WRITE_WIDTH_A>11 ? 6 : (C_WRITE_WIDTH_A>4 ? 5 : (C_WRITE_WIDTH_A<5 ? 4 :0))))); + + localparam MIN_WIDTH_A = (C_WRITE_WIDTH_A < C_READ_WIDTH_A) ? + C_WRITE_WIDTH_A : C_READ_WIDTH_A; + localparam MIN_WIDTH_B = (C_WRITE_WIDTH_B < C_READ_WIDTH_B) ? + C_WRITE_WIDTH_B : C_READ_WIDTH_B; + localparam MIN_WIDTH = (MIN_WIDTH_A < MIN_WIDTH_B) ? + MIN_WIDTH_A : MIN_WIDTH_B; + + localparam MAX_DEPTH_A = (C_WRITE_DEPTH_A > C_READ_DEPTH_A) ? + C_WRITE_DEPTH_A : C_READ_DEPTH_A; + localparam MAX_DEPTH_B = (C_WRITE_DEPTH_B > C_READ_DEPTH_B) ? + C_WRITE_DEPTH_B : C_READ_DEPTH_B; + localparam MAX_DEPTH = (MAX_DEPTH_A > MAX_DEPTH_B) ? + MAX_DEPTH_A : MAX_DEPTH_B; + + + // locally derived parameters to assist memory access + //---------------------------------------------------- + // Calculate the width ratios of each port with respect to the narrowest + // port + localparam WRITE_WIDTH_RATIO_A = C_WRITE_WIDTH_A/MIN_WIDTH; + localparam READ_WIDTH_RATIO_A = C_READ_WIDTH_A/MIN_WIDTH; + localparam WRITE_WIDTH_RATIO_B = C_WRITE_WIDTH_B/MIN_WIDTH; + localparam READ_WIDTH_RATIO_B = C_READ_WIDTH_B/MIN_WIDTH; + + // To modify the LSBs of the 'wider' data to the actual + // address value + //---------------------------------------------------- + localparam WRITE_ADDR_A_DIV = C_WRITE_WIDTH_A/MIN_WIDTH_A; + localparam READ_ADDR_A_DIV = C_READ_WIDTH_A/MIN_WIDTH_A; + localparam WRITE_ADDR_B_DIV = C_WRITE_WIDTH_B/MIN_WIDTH_B; + localparam READ_ADDR_B_DIV = C_READ_WIDTH_B/MIN_WIDTH_B; + + // If byte writes aren't being used, make sure BYTE_SIZE is not + // wider than the memory elements to avoid compilation warnings + localparam BYTE_SIZE = (C_BYTE_SIZE < MIN_WIDTH) ? C_BYTE_SIZE : MIN_WIDTH; + + // The memory + reg [MIN_WIDTH-1:0] memory [0:MAX_DEPTH-1]; + reg [MIN_WIDTH-1:0] temp_mem_array [0:MAX_DEPTH-1]; + reg [C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:0] doublebit_error = 3; + // ECC error arrays + reg sbiterr_arr [0:MAX_DEPTH-1]; + reg dbiterr_arr [0:MAX_DEPTH-1]; + + reg softecc_sbiterr_arr [0:MAX_DEPTH-1]; + reg softecc_dbiterr_arr [0:MAX_DEPTH-1]; + // Memory output 'latches' + reg [C_READ_WIDTH_A-1:0] memory_out_a; + reg [C_READ_WIDTH_B-1:0] memory_out_b; + + // ECC error inputs and outputs from output_stage module: + reg sbiterr_in; + wire sbiterr_sdp; + reg dbiterr_in; + wire dbiterr_sdp; + + wire [C_READ_WIDTH_B-1:0] dout_i; + wire dbiterr_i; + wire sbiterr_i; + wire [C_ADDRB_WIDTH-1:0] rdaddrecc_i; + + reg [C_ADDRB_WIDTH-1:0] rdaddrecc_in; + wire [C_ADDRB_WIDTH-1:0] rdaddrecc_sdp; + + // Reset values + reg [C_READ_WIDTH_A-1:0] inita_val; + reg [C_READ_WIDTH_B-1:0] initb_val; + + // Collision detect + reg is_collision; + reg is_collision_a, is_collision_delay_a; + reg is_collision_b, is_collision_delay_b; + + // Temporary variables for initialization + //--------------------------------------- + integer status; + integer initfile; + integer meminitfile; + // data input buffer + reg [C_WRITE_WIDTH_A-1:0] mif_data; + reg [C_WRITE_WIDTH_A-1:0] mem_data; + // string values in hex + reg [C_READ_WIDTH_A*8-1:0] inita_str = C_INITA_VAL; + reg [C_READ_WIDTH_B*8-1:0] initb_str = C_INITB_VAL; + reg [C_WRITE_WIDTH_A*8-1:0] default_data_str = C_DEFAULT_DATA; + // initialization filename + reg [1023*8-1:0] init_file_str = C_INIT_FILE_NAME; + reg [1023*8-1:0] mem_init_file_str = C_INIT_FILE; + + + //Constants used to calculate the effective address widths for each of the + //four ports. + integer cnt = 1; + integer write_addr_a_width, read_addr_a_width; + integer write_addr_b_width, read_addr_b_width; + + localparam C_FAMILY_LOCALPARAM = (C_FAMILY=="virtexuplushbm"?"virtex7":(C_FAMILY=="zynquplusrfsoc"?"virtex7":(C_FAMILY=="zynquplus"?"virtex7":(C_FAMILY=="kintexuplus"?"virtex7":(C_FAMILY=="virtexuplus"?"virtex7":(C_FAMILY=="virtexu"?"virtex7":(C_FAMILY=="kintexu" ? "virtex7":(C_FAMILY=="virtex7" ? "virtex7" : (C_FAMILY=="virtex7l" ? "virtex7" : (C_FAMILY=="qvirtex7" ? "virtex7" : (C_FAMILY=="qvirtex7l" ? "virtex7" : (C_FAMILY=="kintex7" ? "virtex7" : (C_FAMILY=="kintex7l" ? "virtex7" : (C_FAMILY=="qkintex7" ? "virtex7" : (C_FAMILY=="qkintex7l" ? "virtex7" : (C_FAMILY=="artix7" ? "virtex7" : (C_FAMILY=="artix7l" ? "virtex7" : (C_FAMILY=="qartix7" ? "virtex7" : (C_FAMILY=="qartix7l" ? "virtex7" : (C_FAMILY=="aartix7" ? "virtex7" : (C_FAMILY=="zynq" ? "virtex7" : (C_FAMILY=="azynq" ? "virtex7" : (C_FAMILY=="qzynq" ? "virtex7" : C_FAMILY))))))))))))))))))))))); + + // Internal configuration parameters + //--------------------------------------------- + localparam SINGLE_PORT = (C_MEM_TYPE==0 || C_MEM_TYPE==3); + localparam IS_ROM = (C_MEM_TYPE==3 || C_MEM_TYPE==4); + localparam HAS_A_WRITE = (!IS_ROM); + localparam HAS_B_WRITE = (C_MEM_TYPE==2); + localparam HAS_A_READ = (C_MEM_TYPE!=1); + localparam HAS_B_READ = (!SINGLE_PORT); + localparam HAS_B_PORT = (HAS_B_READ || HAS_B_WRITE); + + // Calculate the mux pipeline register stages for Port A and Port B + //------------------------------------------------------------------ + localparam MUX_PIPELINE_STAGES_A = (C_HAS_MUX_OUTPUT_REGS_A) ? + C_MUX_PIPELINE_STAGES : 0; + localparam MUX_PIPELINE_STAGES_B = (C_HAS_MUX_OUTPUT_REGS_B) ? + C_MUX_PIPELINE_STAGES : 0; + + // Calculate total number of register stages in the core + // ----------------------------------------------------- + localparam NUM_OUTPUT_STAGES_A = (C_HAS_MEM_OUTPUT_REGS_A+MUX_PIPELINE_STAGES_A+C_HAS_MUX_OUTPUT_REGS_A); + + localparam NUM_OUTPUT_STAGES_B = (C_HAS_MEM_OUTPUT_REGS_B+MUX_PIPELINE_STAGES_B+C_HAS_MUX_OUTPUT_REGS_B); + + wire ena_i; + wire enb_i; + wire reseta_i; + wire resetb_i; + wire [C_WEA_WIDTH-1:0] wea_i; + wire [C_WEB_WIDTH-1:0] web_i; + wire rea_i; + wire reb_i; + wire rsta_outp_stage; + wire rstb_outp_stage; + // ECC SBITERR/DBITERR Outputs + // The ECC Behavior is modeled by the behavioral models only for Virtex-6. + // For Virtex-5, these outputs will be tied to 0. + assign SBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?sbiterr_sdp:0; + assign DBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?dbiterr_sdp:0; + assign RDADDRECC = (((C_FAMILY_LOCALPARAM == "virtex7") && C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?rdaddrecc_sdp:0; + + + // This effectively wires off optional inputs + assign ena_i = (C_HAS_ENA==0) || ENA; + assign enb_i = ((C_HAS_ENB==0) || ENB) && HAS_B_PORT; + // To match RTL : In RTL, write enable of the primitive is tied to all 1's and + // the enable of the primitive is ANDing of wea(0) and ena. so eventually, the + // write operation depends on both enable and write enable. So, the below code + // which is actually doing the write operation only on enable ignoring the wea + // is removed to be in consistent with RTL. + // To Fix CR855535 (The fix to this CR is reverted to match RTL) + //assign wea_i = (HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 1 && ENA == 1) ? 'b1 :(HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 0) ? WEA : (HAS_A_WRITE && ena_i && C_USE_ECC == 0) ? WEA : 'b0; + assign wea_i = (HAS_A_WRITE && ena_i) ? WEA : 'b0; + assign web_i = (HAS_B_WRITE && enb_i) ? WEB : 'b0; + assign rea_i = (HAS_A_READ) ? ena_i : 'b0; + assign reb_i = (HAS_B_READ) ? enb_i : 'b0; + + // These signals reset the memory latches + + assign reseta_i = + ((C_HAS_RSTA==1 && RSTA && NUM_OUTPUT_STAGES_A==0) || + (C_HAS_RSTA==1 && RSTA && C_RSTRAM_A==1)); + + assign resetb_i = + ((C_HAS_RSTB==1 && RSTB && NUM_OUTPUT_STAGES_B==0) || + (C_HAS_RSTB==1 && RSTB && C_RSTRAM_B==1)); + + // Tasks to access the memory + //--------------------------- + //************** + // write_a + //************** + task write_a + (input reg [C_ADDRA_WIDTH-1:0] addr, + input reg [C_WEA_WIDTH-1:0] byte_en, + input reg [C_WRITE_WIDTH_A-1:0] data, + input inj_sbiterr, + input inj_dbiterr); + reg [C_WRITE_WIDTH_A-1:0] current_contents; + reg [C_ADDRA_WIDTH-1:0] address; + integer i; + begin + // Shift the address by the ratio + address = (addr/WRITE_ADDR_A_DIV); + if (address >= C_WRITE_DEPTH_A) begin + if (!C_DISABLE_WARN_BHV_RANGE) begin + $fdisplay(ADDRFILE, + "%0s WARNING: Address %0h is outside range for A Write", + C_CORENAME, addr); + end + + // valid address + end else begin + + // Combine w/ byte writes + if (C_USE_BYTE_WEA) begin + + // Get the current memory contents + if (WRITE_WIDTH_RATIO_A == 1) begin + // Workaround for IUS 5.5 part-select issue + current_contents = memory[address]; + end else begin + for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin + current_contents[MIN_WIDTH*i+:MIN_WIDTH] + = memory[address*WRITE_WIDTH_RATIO_A + i]; + end + end + + // Apply incoming bytes + if (C_WEA_WIDTH == 1) begin + // Workaround for IUS 5.5 part-select issue + if (byte_en[0]) begin + current_contents = data; + end + end else begin + for (i = 0; i < C_WEA_WIDTH; i = i + 1) begin + if (byte_en[i]) begin + current_contents[BYTE_SIZE*i+:BYTE_SIZE] + = data[BYTE_SIZE*i+:BYTE_SIZE]; + end + end + end + + // No byte-writes, overwrite the whole word + end else begin + current_contents = data; + end + + // Insert double bit errors: + if (C_USE_ECC == 1) begin + if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin +// Modified for Implementing CR_859399 + current_contents[0] = !(current_contents[30]); + current_contents[1] = !(current_contents[62]); + + /*current_contents[0] = !(current_contents[0]); + current_contents[1] = !(current_contents[1]);*/ + end + end + + // Insert softecc double bit errors: + if (C_USE_SOFTECC == 1) begin + if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin + doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:2] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-3:0]; + doublebit_error[0] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1]; + doublebit_error[1] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-2]; + current_contents = current_contents ^ doublebit_error[C_WRITE_WIDTH_A-1:0]; + end + end + + // Write data to memory + if (WRITE_WIDTH_RATIO_A == 1) begin + // Workaround for IUS 5.5 part-select issue + memory[address*WRITE_WIDTH_RATIO_A] = current_contents; + end else begin + for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin + memory[address*WRITE_WIDTH_RATIO_A + i] + = current_contents[MIN_WIDTH*i+:MIN_WIDTH]; + end + end + + // Store the address at which error is injected: + if ((C_FAMILY_LOCALPARAM == "virtex7") && C_USE_ECC == 1) begin + if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || + (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1)) + begin + sbiterr_arr[addr] = 1; + end else begin + sbiterr_arr[addr] = 0; + end + + if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin + dbiterr_arr[addr] = 1; + end else begin + dbiterr_arr[addr] = 0; + end + end + + // Store the address at which softecc error is injected: + if (C_USE_SOFTECC == 1) begin + if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || + (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1)) + begin + softecc_sbiterr_arr[addr] = 1; + end else begin + softecc_sbiterr_arr[addr] = 0; + end + + if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin + softecc_dbiterr_arr[addr] = 1; + end else begin + softecc_dbiterr_arr[addr] = 0; + end + end + + end + end + endtask + + //************** + // write_b + //************** + task write_b + (input reg [C_ADDRB_WIDTH-1:0] addr, + input reg [C_WEB_WIDTH-1:0] byte_en, + input reg [C_WRITE_WIDTH_B-1:0] data); + reg [C_WRITE_WIDTH_B-1:0] current_contents; + reg [C_ADDRB_WIDTH-1:0] address; + integer i; + begin + // Shift the address by the ratio + address = (addr/WRITE_ADDR_B_DIV); + if (address >= C_WRITE_DEPTH_B) begin + if (!C_DISABLE_WARN_BHV_RANGE) begin + $fdisplay(ADDRFILE, + "%0s WARNING: Address %0h is outside range for B Write", + C_CORENAME, addr); + end + + // valid address + end else begin + + // Combine w/ byte writes + if (C_USE_BYTE_WEB) begin + + // Get the current memory contents + if (WRITE_WIDTH_RATIO_B == 1) begin + // Workaround for IUS 5.5 part-select issue + current_contents = memory[address]; + end else begin + for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin + current_contents[MIN_WIDTH*i+:MIN_WIDTH] + = memory[address*WRITE_WIDTH_RATIO_B + i]; + end + end + + // Apply incoming bytes + if (C_WEB_WIDTH == 1) begin + // Workaround for IUS 5.5 part-select issue + if (byte_en[0]) begin + current_contents = data; + end + end else begin + for (i = 0; i < C_WEB_WIDTH; i = i + 1) begin + if (byte_en[i]) begin + current_contents[BYTE_SIZE*i+:BYTE_SIZE] + = data[BYTE_SIZE*i+:BYTE_SIZE]; + end + end + end + + // No byte-writes, overwrite the whole word + end else begin + current_contents = data; + end + + // Write data to memory + if (WRITE_WIDTH_RATIO_B == 1) begin + // Workaround for IUS 5.5 part-select issue + memory[address*WRITE_WIDTH_RATIO_B] = current_contents; + end else begin + for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin + memory[address*WRITE_WIDTH_RATIO_B + i] + = current_contents[MIN_WIDTH*i+:MIN_WIDTH]; + end + end + end + end + endtask + + //************** + // read_a + //************** + task read_a + (input reg [C_ADDRA_WIDTH-1:0] addr, + input reg reset); + reg [C_ADDRA_WIDTH-1:0] address; + integer i; + begin + + if (reset) begin + memory_out_a <= #FLOP_DELAY inita_val; + end else begin + // Shift the address by the ratio + address = (addr/READ_ADDR_A_DIV); + if (address >= C_READ_DEPTH_A) begin + if (!C_DISABLE_WARN_BHV_RANGE) begin + $fdisplay(ADDRFILE, + "%0s WARNING: Address %0h is outside range for A Read", + C_CORENAME, addr); + end + memory_out_a <= #FLOP_DELAY 'bX; + // valid address + end else begin + if (READ_WIDTH_RATIO_A==1) begin + memory_out_a <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A]; + end else begin + // Increment through the 'partial' words in the memory + for (i = 0; i < READ_WIDTH_RATIO_A; i = i + 1) begin + memory_out_a[MIN_WIDTH*i+:MIN_WIDTH] + <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A + i]; + end + end //end READ_WIDTH_RATIO_A==1 loop + + end //end valid address loop + end //end reset-data assignment loops + end + endtask + + //************** + // read_b + //************** + task read_b + (input reg [C_ADDRB_WIDTH-1:0] addr, + input reg reset); + reg [C_ADDRB_WIDTH-1:0] address; + integer i; + begin + + if (reset) begin + memory_out_b <= #FLOP_DELAY initb_val; + sbiterr_in <= #FLOP_DELAY 1'b0; + dbiterr_in <= #FLOP_DELAY 1'b0; + rdaddrecc_in <= #FLOP_DELAY 0; + end else begin + // Shift the address + address = (addr/READ_ADDR_B_DIV); + if (address >= C_READ_DEPTH_B) begin + if (!C_DISABLE_WARN_BHV_RANGE) begin + $fdisplay(ADDRFILE, + "%0s WARNING: Address %0h is outside range for B Read", + C_CORENAME, addr); + end + memory_out_b <= #FLOP_DELAY 'bX; + sbiterr_in <= #FLOP_DELAY 1'bX; + dbiterr_in <= #FLOP_DELAY 1'bX; + rdaddrecc_in <= #FLOP_DELAY 'bX; + // valid address + end else begin + if (READ_WIDTH_RATIO_B==1) begin + memory_out_b <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B]; + end else begin + // Increment through the 'partial' words in the memory + for (i = 0; i < READ_WIDTH_RATIO_B; i = i + 1) begin + memory_out_b[MIN_WIDTH*i+:MIN_WIDTH] + <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B + i]; + end + end + + if ((C_FAMILY_LOCALPARAM == "virtex7") && C_USE_ECC == 1) begin + rdaddrecc_in <= #FLOP_DELAY addr; + if (sbiterr_arr[addr] == 1) begin + sbiterr_in <= #FLOP_DELAY 1'b1; + end else begin + sbiterr_in <= #FLOP_DELAY 1'b0; + end + + if (dbiterr_arr[addr] == 1) begin + dbiterr_in <= #FLOP_DELAY 1'b1; + end else begin + dbiterr_in <= #FLOP_DELAY 1'b0; + end + + end else if (C_USE_SOFTECC == 1) begin + rdaddrecc_in <= #FLOP_DELAY addr; + if (softecc_sbiterr_arr[addr] == 1) begin + sbiterr_in <= #FLOP_DELAY 1'b1; + end else begin + sbiterr_in <= #FLOP_DELAY 1'b0; + end + + if (softecc_dbiterr_arr[addr] == 1) begin + dbiterr_in <= #FLOP_DELAY 1'b1; + end else begin + dbiterr_in <= #FLOP_DELAY 1'b0; + end + end else begin + rdaddrecc_in <= #FLOP_DELAY 0; + dbiterr_in <= #FLOP_DELAY 1'b0; + sbiterr_in <= #FLOP_DELAY 1'b0; + end //end SOFTECC Loop + end //end Valid address loop + end //end reset-data assignment loops + end + endtask + + //************** + // reset_a + //************** + task reset_a (input reg reset); + begin + if (reset) memory_out_a <= #FLOP_DELAY inita_val; + end + endtask + + //************** + // reset_b + //************** + task reset_b (input reg reset); + begin + if (reset) memory_out_b <= #FLOP_DELAY initb_val; + end + endtask + + //************** + // init_memory + //************** + task init_memory; + integer i, j, addr_step; + integer status; + reg [C_WRITE_WIDTH_A-1:0] default_data; + begin + default_data = 0; + + //Display output message indicating that the behavioral model is being + //initialized + if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) $display(" Block Memory Generator module loading initial data..."); + + // Convert the default to hex + if (C_USE_DEFAULT_DATA) begin + if (default_data_str == "") begin + $fdisplay(ERRFILE, "%0s ERROR: C_DEFAULT_DATA is empty!", C_CORENAME); + $finish; + end else begin + status = $sscanf(default_data_str, "%h", default_data); + if (status == 0) begin + $fdisplay(ERRFILE, {"%0s ERROR: Unsuccessful hexadecimal read", + "from C_DEFAULT_DATA: %0s"}, + C_CORENAME, C_DEFAULT_DATA); + $finish; + end + end + end + + // Step by WRITE_ADDR_A_DIV through the memory via the + // Port A write interface to hit every location once + addr_step = WRITE_ADDR_A_DIV; + + // 'write' to every location with default (or 0) + for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin + write_a(i, {C_WEA_WIDTH{1'b1}}, default_data, 1'b0, 1'b0); + end + + // Get specialized data from the MIF file + if (C_LOAD_INIT_FILE) begin + if (init_file_str == "") begin + $fdisplay(ERRFILE, "%0s ERROR: C_INIT_FILE_NAME is empty!", + C_CORENAME); + $finish; + end else begin + initfile = $fopen(init_file_str, "r"); + if (initfile == 0) begin + $fdisplay(ERRFILE, {"%0s, ERROR: Problem opening", + "C_INIT_FILE_NAME: %0s!"}, + C_CORENAME, init_file_str); + $finish; + end else begin + // loop through the mif file, loading in the data + for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin + status = $fscanf(initfile, "%b", mif_data); + if (status > 0) begin + write_a(i, {C_WEA_WIDTH{1'b1}}, mif_data, 1'b0, 1'b0); + end + end + $fclose(initfile); + end //initfile + end //init_file_str + end //C_LOAD_INIT_FILE + + + if (C_USE_BRAM_BLOCK) begin + // Get specialized data from the MIF file + if (C_INIT_FILE != "NONE") begin + if (mem_init_file_str == "") begin + $fdisplay(ERRFILE, "%0s ERROR: C_INIT_FILE is empty!", + C_CORENAME); + $finish; + end else begin + meminitfile = $fopen(mem_init_file_str, "r"); + if (meminitfile == 0) begin + $fdisplay(ERRFILE, {"%0s, ERROR: Problem opening", + "C_INIT_FILE: %0s!"}, + C_CORENAME, mem_init_file_str); + $finish; + end else begin + // loop through the mif file, loading in the data + $readmemh(mem_init_file_str, memory ); + for (j = 0; j < MAX_DEPTH-1 ; j = j + 1) begin + end + $fclose(meminitfile); + end //meminitfile + end //mem_init_file_str + end //C_INIT_FILE + end //C_USE_BRAM_BLOCK + + //Display output message indicating that the behavioral model is done + //initializing + if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) + $display(" Block Memory Generator data initialization complete."); + end + endtask + + //************** + // log2roundup + //************** + function integer log2roundup (input integer data_value); + integer width; + integer cnt; + begin + width = 0; + + if (data_value > 1) begin + for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin + width = width + 1; + end //loop + end //if + + log2roundup = width; + + end //log2roundup + endfunction + + + //******************* + // collision_check + //******************* + function integer collision_check (input reg [C_ADDRA_WIDTH-1:0] addr_a, + input integer iswrite_a, + input reg [C_ADDRB_WIDTH-1:0] addr_b, + input integer iswrite_b); + reg c_aw_bw, c_aw_br, c_ar_bw; + integer scaled_addra_to_waddrb_width; + integer scaled_addrb_to_waddrb_width; + integer scaled_addra_to_waddra_width; + integer scaled_addrb_to_waddra_width; + integer scaled_addra_to_raddrb_width; + integer scaled_addrb_to_raddrb_width; + integer scaled_addra_to_raddra_width; + integer scaled_addrb_to_raddra_width; + + + + begin + + c_aw_bw = 0; + c_aw_br = 0; + c_ar_bw = 0; + + //If write_addr_b_width is smaller, scale both addresses to that width for + //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH, + //scale it down to write_addr_b_width. addr_b starts as C_ADDRB_WIDTH, + //scale it down to write_addr_b_width. Once both are scaled to + //write_addr_b_width, compare. + scaled_addra_to_waddrb_width = ((addr_a)/ + 2**(C_ADDRA_WIDTH-write_addr_b_width)); + scaled_addrb_to_waddrb_width = ((addr_b)/ + 2**(C_ADDRB_WIDTH-write_addr_b_width)); + + //If write_addr_a_width is smaller, scale both addresses to that width for + //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH, + //scale it down to write_addr_a_width. addr_b starts as C_ADDRB_WIDTH, + //scale it down to write_addr_a_width. Once both are scaled to + //write_addr_a_width, compare. + scaled_addra_to_waddra_width = ((addr_a)/ + 2**(C_ADDRA_WIDTH-write_addr_a_width)); + scaled_addrb_to_waddra_width = ((addr_b)/ + 2**(C_ADDRB_WIDTH-write_addr_a_width)); + + //If read_addr_b_width is smaller, scale both addresses to that width for + //comparing write_addr_a and read_addr_b; addr_a starts as C_ADDRA_WIDTH, + //scale it down to read_addr_b_width. addr_b starts as C_ADDRB_WIDTH, + //scale it down to read_addr_b_width. Once both are scaled to + //read_addr_b_width, compare. + scaled_addra_to_raddrb_width = ((addr_a)/ + 2**(C_ADDRA_WIDTH-read_addr_b_width)); + scaled_addrb_to_raddrb_width = ((addr_b)/ + 2**(C_ADDRB_WIDTH-read_addr_b_width)); + + //If read_addr_a_width is smaller, scale both addresses to that width for + //comparing read_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH, + //scale it down to read_addr_a_width. addr_b starts as C_ADDRB_WIDTH, + //scale it down to read_addr_a_width. Once both are scaled to + //read_addr_a_width, compare. + scaled_addra_to_raddra_width = ((addr_a)/ + 2**(C_ADDRA_WIDTH-read_addr_a_width)); + scaled_addrb_to_raddra_width = ((addr_b)/ + 2**(C_ADDRB_WIDTH-read_addr_a_width)); + + //Look for a write-write collision. In order for a write-write + //collision to exist, both ports must have a write transaction. + if (iswrite_a && iswrite_b) begin + if (write_addr_a_width > write_addr_b_width) begin + if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin + c_aw_bw = 1; + end else begin + c_aw_bw = 0; + end + end else begin + if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin + c_aw_bw = 1; + end else begin + c_aw_bw = 0; + end + end //width + end //iswrite_a and iswrite_b + + //If the B port is reading (which means it is enabled - so could be + //a TX_WRITE or TX_READ), then check for a write-read collision). + //This could happen whether or not a write-write collision exists due + //to asymmetric write/read ports. + if (iswrite_a) begin + if (write_addr_a_width > read_addr_b_width) begin + if (scaled_addra_to_raddrb_width == scaled_addrb_to_raddrb_width) begin + c_aw_br = 1; + end else begin + c_aw_br = 0; + end + end else begin + if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin + c_aw_br = 1; + end else begin + c_aw_br = 0; + end + end //width + end //iswrite_a + + //If the A port is reading (which means it is enabled - so could be + // a TX_WRITE or TX_READ), then check for a write-read collision). + //This could happen whether or not a write-write collision exists due + // to asymmetric write/read ports. + if (iswrite_b) begin + if (read_addr_a_width > write_addr_b_width) begin + if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin + c_ar_bw = 1; + end else begin + c_ar_bw = 0; + end + end else begin + if (scaled_addrb_to_raddra_width == scaled_addra_to_raddra_width) begin + c_ar_bw = 1; + end else begin + c_ar_bw = 0; + end + end //width + end //iswrite_b + + + + collision_check = c_aw_bw | c_aw_br | c_ar_bw; + + end + endfunction + + //******************************* + // power on values + //******************************* + initial begin + // Load up the memory + init_memory; + // Load up the output registers and latches + if ($sscanf(inita_str, "%h", inita_val)) begin + memory_out_a = inita_val; + end else begin + memory_out_a = 0; + end + if ($sscanf(initb_str, "%h", initb_val)) begin + memory_out_b = initb_val; + end else begin + memory_out_b = 0; + end + + sbiterr_in = 1'b0; + dbiterr_in = 1'b0; + rdaddrecc_in = 0; + + // Determine the effective address widths for each of the 4 ports + write_addr_a_width = C_ADDRA_WIDTH - log2roundup(WRITE_ADDR_A_DIV); + read_addr_a_width = C_ADDRA_WIDTH - log2roundup(READ_ADDR_A_DIV); + write_addr_b_width = C_ADDRB_WIDTH - log2roundup(WRITE_ADDR_B_DIV); + read_addr_b_width = C_ADDRB_WIDTH - log2roundup(READ_ADDR_B_DIV); + + $display("Block Memory Generator module %m is using a behavioral model for simulation which will not precisely model memory collision behavior."); + + end + + //*************************************************************************** + // These are the main blocks which schedule read and write operations + // Note that the reset priority feature at the latch stage is only supported + // for Spartan-6. For other families, the default priority at the latch stage + // is "CE" + //*************************************************************************** + // Synchronous clocks: schedule port operations with respect to + // both write operating modes + generate + if(C_COMMON_CLK && (C_WRITE_MODE_A == "WRITE_FIRST") && (C_WRITE_MODE_B == + "WRITE_FIRST")) begin : com_clk_sched_wf_wf + always @(posedge CLKA) begin + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + + if (rea_i) read_a(ADDRA, reseta_i); + + //Read B + if (reb_i) read_b(ADDRB, resetb_i); + end + end + else + if(C_COMMON_CLK && (C_WRITE_MODE_A == "READ_FIRST") && (C_WRITE_MODE_B == + "WRITE_FIRST")) begin : com_clk_sched_rf_wf + always @(posedge CLKA) begin + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + //Read B + if (reb_i) read_b(ADDRB, resetb_i); + //Read A + if (rea_i) read_a(ADDRA, reseta_i); + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + end + end + else + if(C_COMMON_CLK && (C_WRITE_MODE_A == "WRITE_FIRST") && (C_WRITE_MODE_B == + "READ_FIRST")) begin : com_clk_sched_wf_rf + always @(posedge CLKA) begin + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Read A + if (rea_i) read_a(ADDRA, reseta_i); + //Read B + if (reb_i) read_b(ADDRB, resetb_i); + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + end + end + else + if(C_COMMON_CLK && (C_WRITE_MODE_A == "READ_FIRST") && (C_WRITE_MODE_B == + "READ_FIRST")) begin : com_clk_sched_rf_rf + always @(posedge CLKA) begin + //Read A + if (rea_i) read_a(ADDRA, reseta_i); + //Read B + if (reb_i) read_b(ADDRB, resetb_i); + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + end + end + else if(C_COMMON_CLK && (C_WRITE_MODE_A =="WRITE_FIRST") && (C_WRITE_MODE_B == + "NO_CHANGE")) begin : com_clk_sched_wf_nc + always @(posedge CLKA) begin + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Read A + if (rea_i) read_a(ADDRA, reseta_i); + //Read B + if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i); + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + end + end + else if(C_COMMON_CLK && (C_WRITE_MODE_A =="READ_FIRST") && (C_WRITE_MODE_B == + "NO_CHANGE")) begin : com_clk_sched_rf_nc + always @(posedge CLKA) begin + //Read A + if (rea_i) read_a(ADDRA, reseta_i); + //Read B + if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i); + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + end + end + else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B == + "WRITE_FIRST")) begin : com_clk_sched_nc_wf + always @(posedge CLKA) begin + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + //Read A + if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i); + //Read B + if (reb_i) read_b(ADDRB, resetb_i); + end + end + else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B == + "READ_FIRST")) begin : com_clk_sched_nc_rf + always @(posedge CLKA) begin + //Read B + if (reb_i) read_b(ADDRB, resetb_i); + //Read A + if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i); + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + end + end + else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B == + "NO_CHANGE")) begin : com_clk_sched_nc_nc + always @(posedge CLKA) begin + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + //Read A + if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i); + //Read B + if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i); + end + end + else if(C_COMMON_CLK) begin: com_clk_sched_default + always @(posedge CLKA) begin + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + //Read A + if (rea_i) read_a(ADDRA, reseta_i); + //Read B + if (reb_i) read_b(ADDRB, resetb_i); + end + end + endgenerate + + // Asynchronous clocks: port operation is independent + generate + if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "WRITE_FIRST")) begin : async_clk_sched_clka_wf + always @(posedge CLKA) begin + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Read A + if (rea_i) read_a(ADDRA, reseta_i); + end + end + else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "READ_FIRST")) begin : async_clk_sched_clka_rf + always @(posedge CLKA) begin + //Read A + if (rea_i) read_a(ADDRA, reseta_i); + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + end + end + else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "NO_CHANGE")) begin : async_clk_sched_clka_nc + always @(posedge CLKA) begin + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Read A + if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i); + end + end + endgenerate + + generate + if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "WRITE_FIRST")) begin: async_clk_sched_clkb_wf + always @(posedge CLKB) begin + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + //Read B + if (reb_i) read_b(ADDRB, resetb_i); + end + end + else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "READ_FIRST")) begin: async_clk_sched_clkb_rf + always @(posedge CLKB) begin + //Read B + if (reb_i) read_b(ADDRB, resetb_i); + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + end + end + else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "NO_CHANGE")) begin: async_clk_sched_clkb_nc + always @(posedge CLKB) begin + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + //Read B + if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i); + end + end + endgenerate + + + //*************************************************************** + // Instantiate the variable depth output register stage module + //*************************************************************** + // Port A + + assign rsta_outp_stage = RSTA & (~SLEEP); + + blk_mem_gen_v8_4_3_output_stage + #(.C_FAMILY (C_FAMILY), + .C_XDEVICEFAMILY (C_XDEVICEFAMILY), + .C_RST_TYPE ("SYNC"), + .C_HAS_RST (C_HAS_RSTA), + .C_RSTRAM (C_RSTRAM_A), + .C_RST_PRIORITY (C_RST_PRIORITY_A), + .C_INIT_VAL (C_INITA_VAL), + .C_HAS_EN (C_HAS_ENA), + .C_HAS_REGCE (C_HAS_REGCEA), + .C_DATA_WIDTH (C_READ_WIDTH_A), + .C_ADDRB_WIDTH (C_ADDRB_WIDTH), + .C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_A), + .C_USE_SOFTECC (C_USE_SOFTECC), + .C_USE_ECC (C_USE_ECC), + .NUM_STAGES (NUM_OUTPUT_STAGES_A), + .C_EN_ECC_PIPE (0), + .FLOP_DELAY (FLOP_DELAY)) + reg_a + (.CLK (CLKA), + .RST (rsta_outp_stage),//(RSTA), + .EN (ENA), + .REGCE (REGCEA), + .DIN_I (memory_out_a), + .DOUT (DOUTA), + .SBITERR_IN_I (1'b0), + .DBITERR_IN_I (1'b0), + .SBITERR (), + .DBITERR (), + .RDADDRECC_IN_I ({C_ADDRB_WIDTH{1'b0}}), + .ECCPIPECE (1'b0), + .RDADDRECC () + ); + + assign rstb_outp_stage = RSTB & (~SLEEP); + + // Port B + blk_mem_gen_v8_4_3_output_stage + #(.C_FAMILY (C_FAMILY), + .C_XDEVICEFAMILY (C_XDEVICEFAMILY), + .C_RST_TYPE ("SYNC"), + .C_HAS_RST (C_HAS_RSTB), + .C_RSTRAM (C_RSTRAM_B), + .C_RST_PRIORITY (C_RST_PRIORITY_B), + .C_INIT_VAL (C_INITB_VAL), + .C_HAS_EN (C_HAS_ENB), + .C_HAS_REGCE (C_HAS_REGCEB), + .C_DATA_WIDTH (C_READ_WIDTH_B), + .C_ADDRB_WIDTH (C_ADDRB_WIDTH), + .C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_B), + .C_USE_SOFTECC (C_USE_SOFTECC), + .C_USE_ECC (C_USE_ECC), + .NUM_STAGES (NUM_OUTPUT_STAGES_B), + .C_EN_ECC_PIPE (C_EN_ECC_PIPE), + .FLOP_DELAY (FLOP_DELAY)) + reg_b + (.CLK (CLKB), + .RST (rstb_outp_stage),//(RSTB), + .EN (ENB), + .REGCE (REGCEB), + .DIN_I (memory_out_b), + .DOUT (dout_i), + .SBITERR_IN_I (sbiterr_in), + .DBITERR_IN_I (dbiterr_in), + .SBITERR (sbiterr_i), + .DBITERR (dbiterr_i), + .RDADDRECC_IN_I (rdaddrecc_in), + .ECCPIPECE (ECCPIPECE), + .RDADDRECC (rdaddrecc_i) + ); + + //*************************************************************** + // Instantiate the Input and Output register stages + //*************************************************************** +blk_mem_gen_v8_4_3_softecc_output_reg_stage + #(.C_DATA_WIDTH (C_READ_WIDTH_B), + .C_ADDRB_WIDTH (C_ADDRB_WIDTH), + .C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B), + .C_USE_SOFTECC (C_USE_SOFTECC), + .FLOP_DELAY (FLOP_DELAY)) + has_softecc_output_reg_stage + (.CLK (CLKB), + .DIN (dout_i), + .DOUT (DOUTB), + .SBITERR_IN (sbiterr_i), + .DBITERR_IN (dbiterr_i), + .SBITERR (sbiterr_sdp), + .DBITERR (dbiterr_sdp), + .RDADDRECC_IN (rdaddrecc_i), + .RDADDRECC (rdaddrecc_sdp) +); + + //**************************************************** + // Synchronous collision checks + //**************************************************** +// CR 780544 : To make verilog model's collison warnings in consistant with +// vhdl model, the non-blocking assignments are replaced with blocking +// assignments. + generate if (!C_DISABLE_WARN_BHV_COLL && C_COMMON_CLK) begin : sync_coll + always @(posedge CLKA) begin + // Possible collision if both are enabled and the addresses match + if (ena_i && enb_i) begin + if (wea_i || web_i) begin + is_collision = collision_check(ADDRA, wea_i, ADDRB, web_i); + end else begin + is_collision = 0; + end + end else begin + is_collision = 0; + end + + // If the write port is in READ_FIRST mode, there is no collision + if (C_WRITE_MODE_A=="READ_FIRST" && wea_i && !web_i) begin + is_collision = 0; + end + if (C_WRITE_MODE_B=="READ_FIRST" && web_i && !wea_i) begin + is_collision = 0; + end + + // Only flag if one of the accesses is a write + if (is_collision && (wea_i || web_i)) begin + $fwrite(COLLFILE, "%0s collision detected at time: %0d, ", + C_CORENAME, $time); + $fwrite(COLLFILE, "Instance: %m, A %0s address: %0h, B %0s address: %0h\n", + wea_i ? "write" : "read", ADDRA, + web_i ? "write" : "read", ADDRB); + end + end + + //**************************************************** + // Asynchronous collision checks + //**************************************************** + end else if (!C_DISABLE_WARN_BHV_COLL && !C_COMMON_CLK) begin : async_coll + + // Delay A and B addresses in order to mimic setup/hold times + wire [C_ADDRA_WIDTH-1:0] #COLL_DELAY addra_delay = ADDRA; + wire [0:0] #COLL_DELAY wea_delay = wea_i; + wire #COLL_DELAY ena_delay = ena_i; + wire [C_ADDRB_WIDTH-1:0] #COLL_DELAY addrb_delay = ADDRB; + wire [0:0] #COLL_DELAY web_delay = web_i; + wire #COLL_DELAY enb_delay = enb_i; + + // Do the checks w/rt A + always @(posedge CLKA) begin + // Possible collision if both are enabled and the addresses match + if (ena_i && enb_i) begin + if (wea_i || web_i) begin + is_collision_a = collision_check(ADDRA, wea_i, ADDRB, web_i); + end else begin + is_collision_a = 0; + end + end else begin + is_collision_a = 0; + end + + if (ena_i && enb_delay) begin + if(wea_i || web_delay) begin + is_collision_delay_a = collision_check(ADDRA, wea_i, addrb_delay, + web_delay); + end else begin + is_collision_delay_a = 0; + end + end else begin + is_collision_delay_a = 0; + end + + // Only flag if B access is a write + if (is_collision_a && web_i) begin + $fwrite(COLLFILE, "%0s collision detected at time: %0d, ", + C_CORENAME, $time); + $fwrite(COLLFILE, "Instance: %m, A %0s address: %0h, B write address: %0h\n", + wea_i ? "write" : "read", ADDRA, ADDRB); + + end else if (is_collision_delay_a && web_delay) begin + $fwrite(COLLFILE, "%0s collision detected at time: %0d, ", + C_CORENAME, $time); + $fwrite(COLLFILE, "Instance: %m, A %0s address: %0h, B write address: %0h\n", + wea_i ? "write" : "read", ADDRA, addrb_delay); + end + + end + + // Do the checks w/rt B + always @(posedge CLKB) begin + + // Possible collision if both are enabled and the addresses match + if (ena_i && enb_i) begin + if (wea_i || web_i) begin + is_collision_b = collision_check(ADDRA, wea_i, ADDRB, web_i); + end else begin + is_collision_b = 0; + end + end else begin + is_collision_b = 0; + end + + if (ena_delay && enb_i) begin + if (wea_delay || web_i) begin + is_collision_delay_b = collision_check(addra_delay, wea_delay, ADDRB, + web_i); + end else begin + is_collision_delay_b = 0; + end + end else begin + is_collision_delay_b = 0; + end + + + // Only flag if A access is a write + if (is_collision_b && wea_i) begin + $fwrite(COLLFILE, "%0s collision detected at time: %0d, ", + C_CORENAME, $time); + $fwrite(COLLFILE, "Instance: %m, A write address: %0h, B %s address: %0h\n", + ADDRA, web_i ? "write" : "read", ADDRB); + + end else if (is_collision_delay_b && wea_delay) begin + $fwrite(COLLFILE, "%0s collision detected at time: %0d, ", + C_CORENAME, $time); + $fwrite(COLLFILE, "Instance: %m, A write address: %0h, B %s address: %0h\n", + addra_delay, web_i ? "write" : "read", ADDRB); + end + + end + end + endgenerate + +endmodule +//***************************************************************************** +// Top module wraps Input register and Memory module +// +// This module is the top-level behavioral model and this implements the memory +// module and the input registers +//***************************************************************************** +module blk_mem_gen_v8_4_3 + #(parameter C_CORENAME = "blk_mem_gen_v8_4_3", + parameter C_FAMILY = "virtex7", + parameter C_XDEVICEFAMILY = "virtex7", + parameter C_ELABORATION_DIR = "", + parameter C_INTERFACE_TYPE = 0, + parameter C_USE_BRAM_BLOCK = 0, + parameter C_CTRL_ECC_ALGO = "NONE", + parameter C_ENABLE_32BIT_ADDRESS = 0, + parameter C_AXI_TYPE = 0, + parameter C_AXI_SLAVE_TYPE = 0, + parameter C_HAS_AXI_ID = 0, + parameter C_AXI_ID_WIDTH = 4, + parameter C_MEM_TYPE = 2, + parameter C_BYTE_SIZE = 9, + parameter C_ALGORITHM = 1, + parameter C_PRIM_TYPE = 3, + parameter C_LOAD_INIT_FILE = 0, + parameter C_INIT_FILE_NAME = "", + parameter C_INIT_FILE = "", + parameter C_USE_DEFAULT_DATA = 0, + parameter C_DEFAULT_DATA = "0", + //parameter C_RST_TYPE = "SYNC", + parameter C_HAS_RSTA = 0, + parameter C_RST_PRIORITY_A = "CE", + parameter C_RSTRAM_A = 0, + parameter C_INITA_VAL = "0", + parameter C_HAS_ENA = 1, + parameter C_HAS_REGCEA = 0, + parameter C_USE_BYTE_WEA = 0, + parameter C_WEA_WIDTH = 1, + parameter C_WRITE_MODE_A = "WRITE_FIRST", + parameter C_WRITE_WIDTH_A = 32, + parameter C_READ_WIDTH_A = 32, + parameter C_WRITE_DEPTH_A = 64, + parameter C_READ_DEPTH_A = 64, + parameter C_ADDRA_WIDTH = 5, + parameter C_HAS_RSTB = 0, + parameter C_RST_PRIORITY_B = "CE", + parameter C_RSTRAM_B = 0, + parameter C_INITB_VAL = "", + parameter C_HAS_ENB = 1, + parameter C_HAS_REGCEB = 0, + parameter C_USE_BYTE_WEB = 0, + parameter C_WEB_WIDTH = 1, + parameter C_WRITE_MODE_B = "WRITE_FIRST", + parameter C_WRITE_WIDTH_B = 32, + parameter C_READ_WIDTH_B = 32, + parameter C_WRITE_DEPTH_B = 64, + parameter C_READ_DEPTH_B = 64, + parameter C_ADDRB_WIDTH = 5, + parameter C_HAS_MEM_OUTPUT_REGS_A = 0, + parameter C_HAS_MEM_OUTPUT_REGS_B = 0, + parameter C_HAS_MUX_OUTPUT_REGS_A = 0, + parameter C_HAS_MUX_OUTPUT_REGS_B = 0, + parameter C_HAS_SOFTECC_INPUT_REGS_A = 0, + parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0, + parameter C_MUX_PIPELINE_STAGES = 0, + parameter C_USE_SOFTECC = 0, + parameter C_READ_LATENCY_A = 1, + parameter C_READ_LATENCY_B = 1, + parameter C_USE_ECC = 0, + parameter C_EN_ECC_PIPE = 0, + parameter C_HAS_INJECTERR = 0, + parameter C_SIM_COLLISION_CHECK = "NONE", + parameter C_COMMON_CLK = 1, + parameter C_DISABLE_WARN_BHV_COLL = 0, + parameter C_EN_SLEEP_PIN = 0, + parameter C_USE_URAM = 0, + parameter C_EN_RDADDRA_CHG = 0, + parameter C_EN_RDADDRB_CHG = 0, + parameter C_EN_DEEPSLEEP_PIN = 0, + parameter C_EN_SHUTDOWN_PIN = 0, + parameter C_EN_SAFETY_CKT = 0, + parameter C_COUNT_36K_BRAM = "", + parameter C_COUNT_18K_BRAM = "", + parameter C_EST_POWER_SUMMARY = "", + parameter C_DISABLE_WARN_BHV_RANGE = 0 + + ) + (input clka, + input rsta, + input ena, + input regcea, + input [C_WEA_WIDTH-1:0] wea, + input [C_ADDRA_WIDTH-1:0] addra, + input [C_WRITE_WIDTH_A-1:0] dina, + output [C_READ_WIDTH_A-1:0] douta, + input clkb, + input rstb, + input enb, + input regceb, + input [C_WEB_WIDTH-1:0] web, + input [C_ADDRB_WIDTH-1:0] addrb, + input [C_WRITE_WIDTH_B-1:0] dinb, + output [C_READ_WIDTH_B-1:0] doutb, + input injectsbiterr, + input injectdbiterr, + output sbiterr, + output dbiterr, + output [C_ADDRB_WIDTH-1:0] rdaddrecc, + input eccpipece, + input sleep, + input deepsleep, + input shutdown, + output rsta_busy, + output rstb_busy, + //AXI BMG Input and Output Port Declarations + + //AXI Global Signals + input s_aclk, + input s_aresetn, + + //AXI Full/lite slave write (write side) + input [C_AXI_ID_WIDTH-1:0] s_axi_awid, + input [31:0] s_axi_awaddr, + input [7:0] s_axi_awlen, + input [2:0] s_axi_awsize, + input [1:0] s_axi_awburst, + input s_axi_awvalid, + output s_axi_awready, + input [C_WRITE_WIDTH_A-1:0] s_axi_wdata, + input [C_WEA_WIDTH-1:0] s_axi_wstrb, + input s_axi_wlast, + input s_axi_wvalid, + output s_axi_wready, + output [C_AXI_ID_WIDTH-1:0] s_axi_bid, + output [1:0] s_axi_bresp, + output s_axi_bvalid, + input s_axi_bready, + + //AXI Full/lite slave read (write side) + input [C_AXI_ID_WIDTH-1:0] s_axi_arid, + input [31:0] s_axi_araddr, + input [7:0] s_axi_arlen, + input [2:0] s_axi_arsize, + input [1:0] s_axi_arburst, + input s_axi_arvalid, + output s_axi_arready, + output [C_AXI_ID_WIDTH-1:0] s_axi_rid, + output [C_WRITE_WIDTH_B-1:0] s_axi_rdata, + output [1:0] s_axi_rresp, + output s_axi_rlast, + output s_axi_rvalid, + input s_axi_rready, + + //AXI Full/lite sideband signals + input s_axi_injectsbiterr, + input s_axi_injectdbiterr, + output s_axi_sbiterr, + output s_axi_dbiterr, + output [C_ADDRB_WIDTH-1:0] s_axi_rdaddrecc + + ); +//****************************** +// Port and Generic Definitions +//****************************** + ////////////////////////////////////////////////////////////////////////// + // Generic Definitions + ////////////////////////////////////////////////////////////////////////// + // C_CORENAME : Instance name of the Block Memory Generator core + // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following + // options are available - "spartan3", "spartan6", + // "virtex4", "virtex5", "virtex6" and "virtex6l". + // C_MEM_TYPE : Designates memory type. + // It can be + // 0 - Single Port Memory + // 1 - Simple Dual Port Memory + // 2 - True Dual Port Memory + // 3 - Single Port Read Only Memory + // 4 - Dual Port Read Only Memory + // C_BYTE_SIZE : Size of a byte (8 or 9 bits) + // C_ALGORITHM : Designates the algorithm method used + // for constructing the memory. + // It can be Fixed_Primitives, Minimum_Area or + // Low_Power + // C_PRIM_TYPE : Designates the user selected primitive used to + // construct the memory. + // + // C_LOAD_INIT_FILE : Designates the use of an initialization file to + // initialize memory contents. + // C_INIT_FILE_NAME : Memory initialization file name. + // C_USE_DEFAULT_DATA : Designates whether to fill remaining + // initialization space with default data + // C_DEFAULT_DATA : Default value of all memory locations + // not initialized by the memory + // initialization file. + // C_RST_TYPE : Type of reset - Synchronous or Asynchronous + // C_HAS_RSTA : Determines the presence of the RSTA port + // C_RST_PRIORITY_A : Determines the priority between CE and SR for + // Port A. + // C_RSTRAM_A : Determines if special reset behavior is used for + // Port A + // C_INITA_VAL : The initialization value for Port A + // C_HAS_ENA : Determines the presence of the ENA port + // C_HAS_REGCEA : Determines the presence of the REGCEA port + // C_USE_BYTE_WEA : Determines if the Byte Write is used or not. + // C_WEA_WIDTH : The width of the WEA port + // C_WRITE_MODE_A : Configurable write mode for Port A. It can be + // WRITE_FIRST, READ_FIRST or NO_CHANGE. + // C_WRITE_WIDTH_A : Memory write width for Port A. + // C_READ_WIDTH_A : Memory read width for Port A. + // C_WRITE_DEPTH_A : Memory write depth for Port A. + // C_READ_DEPTH_A : Memory read depth for Port A. + // C_ADDRA_WIDTH : Width of the ADDRA input port + // C_HAS_RSTB : Determines the presence of the RSTB port + // C_RST_PRIORITY_B : Determines the priority between CE and SR for + // Port B. + // C_RSTRAM_B : Determines if special reset behavior is used for + // Port B + // C_INITB_VAL : The initialization value for Port B + // C_HAS_ENB : Determines the presence of the ENB port + // C_HAS_REGCEB : Determines the presence of the REGCEB port + // C_USE_BYTE_WEB : Determines if the Byte Write is used or not. + // C_WEB_WIDTH : The width of the WEB port + // C_WRITE_MODE_B : Configurable write mode for Port B. It can be + // WRITE_FIRST, READ_FIRST or NO_CHANGE. + // C_WRITE_WIDTH_B : Memory write width for Port B. + // C_READ_WIDTH_B : Memory read width for Port B. + // C_WRITE_DEPTH_B : Memory write depth for Port B. + // C_READ_DEPTH_B : Memory read depth for Port B. + // C_ADDRB_WIDTH : Width of the ADDRB input port + // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output + // of the RAM primitive for Port A. + // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output + // of the RAM primitive for Port B. + // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output + // of the MUX for Port A. + // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output + // of the MUX for Port B. + // C_HAS_SOFTECC_INPUT_REGS_A : + // C_HAS_SOFTECC_OUTPUT_REGS_B : + // C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in + // between the muxes. + // C_USE_SOFTECC : Determines if the Soft ECC feature is used or + // not. Only applicable Spartan-6 + // C_USE_ECC : Determines if the ECC feature is used or + // not. Only applicable for V5 and V6 + // C_HAS_INJECTERR : Determines if the error injection pins + // are present or not. If the ECC feature + // is not used, this value is defaulted to + // 0, else the following are the allowed + // values: + // 0 : No INJECTSBITERR or INJECTDBITERR pins + // 1 : Only INJECTSBITERR pin exists + // 2 : Only INJECTDBITERR pin exists + // 3 : Both INJECTSBITERR and INJECTDBITERR pins exist + // C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision + // warnings. It can be "ALL", "NONE", + // "Warnings_Only" or "Generate_X_Only". + // C_COMMON_CLK : Determins if the core has a single CLK input. + // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings + // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range + // warnings + ////////////////////////////////////////////////////////////////////////// + // Port Definitions + ////////////////////////////////////////////////////////////////////////// + // CLKA : Clock to synchronize all read and write operations of Port A. + // RSTA : Reset input to reset memory outputs to a user-defined + // reset state for Port A. + // ENA : Enable all read and write operations of Port A. + // REGCEA : Register Clock Enable to control each pipeline output + // register stages for Port A. + // WEA : Write Enable to enable all write operations of Port A. + // ADDRA : Address of Port A. + // DINA : Data input of Port A. + // DOUTA : Data output of Port A. + // CLKB : Clock to synchronize all read and write operations of Port B. + // RSTB : Reset input to reset memory outputs to a user-defined + // reset state for Port B. + // ENB : Enable all read and write operations of Port B. + // REGCEB : Register Clock Enable to control each pipeline output + // register stages for Port B. + // WEB : Write Enable to enable all write operations of Port B. + // ADDRB : Address of Port B. + // DINB : Data input of Port B. + // DOUTB : Data output of Port B. + // INJECTSBITERR : Single Bit ECC Error Injection Pin. + // INJECTDBITERR : Double Bit ECC Error Injection Pin. + // SBITERR : Output signal indicating that a Single Bit ECC Error has been + // detected and corrected. + // DBITERR : Output signal indicating that a Double Bit ECC Error has been + // detected. + // RDADDRECC : Read Address Output signal indicating address at which an + // ECC error has occurred. + ////////////////////////////////////////////////////////////////////////// + + wire SBITERR; + wire DBITERR; + wire S_AXI_AWREADY; + wire S_AXI_WREADY; + wire S_AXI_BVALID; + wire S_AXI_ARREADY; + wire S_AXI_RLAST; + wire S_AXI_RVALID; + wire S_AXI_SBITERR; + wire S_AXI_DBITERR; + + wire [C_WEA_WIDTH-1:0] WEA = wea; + wire [C_ADDRA_WIDTH-1:0] ADDRA = addra; + wire [C_WRITE_WIDTH_A-1:0] DINA = dina; + wire [C_READ_WIDTH_A-1:0] DOUTA; + wire [C_WEB_WIDTH-1:0] WEB = web; + wire [C_ADDRB_WIDTH-1:0] ADDRB = addrb; + wire [C_WRITE_WIDTH_B-1:0] DINB = dinb; + wire [C_READ_WIDTH_B-1:0] DOUTB; + wire [C_ADDRB_WIDTH-1:0] RDADDRECC; + wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID = s_axi_awid; + wire [31:0] S_AXI_AWADDR = s_axi_awaddr; + wire [7:0] S_AXI_AWLEN = s_axi_awlen; + wire [2:0] S_AXI_AWSIZE = s_axi_awsize; + wire [1:0] S_AXI_AWBURST = s_axi_awburst; + wire [C_WRITE_WIDTH_A-1:0] S_AXI_WDATA = s_axi_wdata; + wire [C_WEA_WIDTH-1:0] S_AXI_WSTRB = s_axi_wstrb; + wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID; + wire [1:0] S_AXI_BRESP; + wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID = s_axi_arid; + wire [31:0] S_AXI_ARADDR = s_axi_araddr; + wire [7:0] S_AXI_ARLEN = s_axi_arlen; + wire [2:0] S_AXI_ARSIZE = s_axi_arsize; + wire [1:0] S_AXI_ARBURST = s_axi_arburst; + wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID; + wire [C_WRITE_WIDTH_B-1:0] S_AXI_RDATA; + wire [1:0] S_AXI_RRESP; + wire [C_ADDRB_WIDTH-1:0] S_AXI_RDADDRECC; + // Added to fix the simulation warning #CR731605 + wire [C_WEB_WIDTH-1:0] WEB_parameterized = 0; + wire ECCPIPECE; + wire SLEEP; + reg RSTA_BUSY = 0; + reg RSTB_BUSY = 0; + // Declaration of internal signals to avoid warnings #927399 + wire CLKA; + wire RSTA; + wire ENA; + wire REGCEA; + wire CLKB; + wire RSTB; + wire ENB; + wire REGCEB; + wire INJECTSBITERR; + wire INJECTDBITERR; + wire S_ACLK; + wire S_ARESETN; + wire S_AXI_AWVALID; + wire S_AXI_WLAST; + wire S_AXI_WVALID; + wire S_AXI_BREADY; + wire S_AXI_ARVALID; + wire S_AXI_RREADY; + wire S_AXI_INJECTSBITERR; + wire S_AXI_INJECTDBITERR; + + assign CLKA = clka; + assign RSTA = rsta; + assign ENA = ena; + assign REGCEA = regcea; + assign CLKB = clkb; + assign RSTB = rstb; + assign ENB = enb; + assign REGCEB = regceb; + assign INJECTSBITERR = injectsbiterr; + assign INJECTDBITERR = injectdbiterr; + assign ECCPIPECE = eccpipece; + assign SLEEP = sleep; + assign sbiterr = SBITERR; + assign dbiterr = DBITERR; + assign S_ACLK = s_aclk; + assign S_ARESETN = s_aresetn; + assign S_AXI_AWVALID = s_axi_awvalid; + assign s_axi_awready = S_AXI_AWREADY; + assign S_AXI_WLAST = s_axi_wlast; + assign S_AXI_WVALID = s_axi_wvalid; + assign s_axi_wready = S_AXI_WREADY; + assign s_axi_bvalid = S_AXI_BVALID; + assign S_AXI_BREADY = s_axi_bready; + assign S_AXI_ARVALID = s_axi_arvalid; + assign s_axi_arready = S_AXI_ARREADY; + assign s_axi_rlast = S_AXI_RLAST; + assign s_axi_rvalid = S_AXI_RVALID; + assign S_AXI_RREADY = s_axi_rready; + assign S_AXI_INJECTSBITERR = s_axi_injectsbiterr; + assign S_AXI_INJECTDBITERR = s_axi_injectdbiterr; + assign s_axi_sbiterr = S_AXI_SBITERR; + assign s_axi_dbiterr = S_AXI_DBITERR; + + assign rsta_busy = RSTA_BUSY; + assign rstb_busy = RSTB_BUSY; + + assign doutb = DOUTB; + assign douta = DOUTA; + assign rdaddrecc = RDADDRECC; + assign s_axi_bid = S_AXI_BID; + assign s_axi_bresp = S_AXI_BRESP; + assign s_axi_rid = S_AXI_RID; + assign s_axi_rdata = S_AXI_RDATA; + assign s_axi_rresp = S_AXI_RRESP; + assign s_axi_rdaddrecc = S_AXI_RDADDRECC; + + localparam FLOP_DELAY = 100; // 100 ps + + reg injectsbiterr_in; + reg injectdbiterr_in; + reg rsta_in; + reg ena_in; + reg regcea_in; + reg [C_WEA_WIDTH-1:0] wea_in; + reg [C_ADDRA_WIDTH-1:0] addra_in; + reg [C_WRITE_WIDTH_A-1:0] dina_in; + + wire [C_ADDRA_WIDTH-1:0] s_axi_awaddr_out_c; + wire [C_ADDRB_WIDTH-1:0] s_axi_araddr_out_c; + wire s_axi_wr_en_c; + wire s_axi_rd_en_c; + wire s_aresetn_a_c; + wire [7:0] s_axi_arlen_c ; + + + wire [C_AXI_ID_WIDTH-1 : 0] s_axi_rid_c; + wire [C_WRITE_WIDTH_B-1 : 0] s_axi_rdata_c; + wire [1:0] s_axi_rresp_c; + wire s_axi_rlast_c; + wire s_axi_rvalid_c; + wire s_axi_rready_c; + wire regceb_c; + + localparam C_AXI_PAYLOAD = (C_HAS_MUX_OUTPUT_REGS_B == 1)?C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3:C_AXI_ID_WIDTH+3; + wire [C_AXI_PAYLOAD-1 : 0] s_axi_payload_c; + wire [C_AXI_PAYLOAD-1 : 0] m_axi_payload_c; + +// Safety logic related signals + + reg [4:0] RSTA_SHFT_REG = 0; + reg POR_A = 0; + reg [4:0] RSTB_SHFT_REG = 0; + reg POR_B = 0; + + reg ENA_dly = 0; + reg ENA_dly_D = 0; + + reg ENB_dly = 0; + reg ENB_dly_D = 0; + + wire RSTA_I_SAFE; + wire RSTB_I_SAFE; + + wire ENA_I_SAFE; + wire ENB_I_SAFE; + + reg ram_rstram_a_busy = 0; + reg ram_rstreg_a_busy = 0; + reg ram_rstram_b_busy = 0; + reg ram_rstreg_b_busy = 0; + + reg ENA_dly_reg = 0; + reg ENB_dly_reg = 0; + + reg ENA_dly_reg_D = 0; + reg ENB_dly_reg_D = 0; + + //************** + // log2roundup + //************** + function integer log2roundup (input integer data_value); + integer width; + integer cnt; + begin + width = 0; + + if (data_value > 1) begin + for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin + width = width + 1; + end //loop + end //if + + log2roundup = width; + + end //log2roundup + endfunction + + //************** + // log2int + //************** + function integer log2int (input integer data_value); + integer width; + integer cnt; + begin + width = 0; + cnt= data_value; + + for(cnt=data_value ; cnt >1 ; cnt = cnt / 2) begin + width = width + 1; + end //loop + + log2int = width; + + end //log2int + endfunction + + //************************************************************************** + // FUNCTION : divroundup + // Returns the ceiling value of the division + // Data_value - the quantity to be divided, dividend + // Divisor - the value to divide the data_value by + //************************************************************************** + function integer divroundup (input integer data_value,input integer divisor); + integer div; + begin + div = data_value/divisor; + if ((data_value % divisor) != 0) begin + div = div+1; + end //if + divroundup = div; + end //if + endfunction + + localparam AXI_FULL_MEMORY_SLAVE = ((C_AXI_SLAVE_TYPE == 0 && C_AXI_TYPE == 1)?1:0); + localparam C_AXI_ADDR_WIDTH_MSB = C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8); + localparam C_AXI_ADDR_WIDTH = C_AXI_ADDR_WIDTH_MSB; + + //Data Width Number of LSB address bits to be discarded + //1 to 16 1 + //17 to 32 2 + //33 to 64 3 + //65 to 128 4 + //129 to 256 5 + //257 to 512 6 + //513 to 1024 7 + // The following two constants determine this. + + localparam LOWER_BOUND_VAL = (log2roundup(divroundup(C_WRITE_WIDTH_A,8) == 0))?0:(log2roundup(divroundup(C_WRITE_WIDTH_A,8))); + localparam C_AXI_ADDR_WIDTH_LSB = ((AXI_FULL_MEMORY_SLAVE == 1)?0:LOWER_BOUND_VAL); + localparam C_AXI_OS_WR = 2; + + //*********************************************** + // INPUT REGISTERS. + //*********************************************** + generate if (C_HAS_SOFTECC_INPUT_REGS_A==0) begin : no_softecc_input_reg_stage + always @* begin + injectsbiterr_in = INJECTSBITERR; + injectdbiterr_in = INJECTDBITERR; + rsta_in = RSTA; + ena_in = ENA; + regcea_in = REGCEA; + wea_in = WEA; + addra_in = ADDRA; + dina_in = DINA; + end //end always + end //end no_softecc_input_reg_stage + endgenerate + + generate if (C_HAS_SOFTECC_INPUT_REGS_A==1) begin : has_softecc_input_reg_stage + always @(posedge CLKA) begin + injectsbiterr_in <= #FLOP_DELAY INJECTSBITERR; + injectdbiterr_in <= #FLOP_DELAY INJECTDBITERR; + rsta_in <= #FLOP_DELAY RSTA; + ena_in <= #FLOP_DELAY ENA; + regcea_in <= #FLOP_DELAY REGCEA; + wea_in <= #FLOP_DELAY WEA; + addra_in <= #FLOP_DELAY ADDRA; + dina_in <= #FLOP_DELAY DINA; + end //end always + end //end input_reg_stages generate statement + endgenerate + + //************************************************************************** + // NO SAFETY LOGIC + //************************************************************************** + + generate + if (C_EN_SAFETY_CKT == 0) begin : NO_SAFETY_CKT_GEN + assign ENA_I_SAFE = ena_in; + assign ENB_I_SAFE = ENB; + assign RSTA_I_SAFE = rsta_in; + assign RSTB_I_SAFE = RSTB; + end + endgenerate + + //*************************************************************************** + // SAFETY LOGIC + // Power-ON Reset Generation + //*************************************************************************** + generate + if (C_EN_SAFETY_CKT == 1) begin + always @(posedge clka) RSTA_SHFT_REG <= #FLOP_DELAY {RSTA_SHFT_REG[3:0],1'b1} ; + always @(posedge clka) POR_A <= #FLOP_DELAY RSTA_SHFT_REG[4] ^ RSTA_SHFT_REG[0]; + always @(posedge clkb) RSTB_SHFT_REG <= #FLOP_DELAY {RSTB_SHFT_REG[3:0],1'b1} ; + always @(posedge clkb) POR_B <= #FLOP_DELAY RSTB_SHFT_REG[4] ^ RSTB_SHFT_REG[0]; + + assign RSTA_I_SAFE = rsta_in | POR_A; + assign RSTB_I_SAFE = (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) ? 1'b0 : (RSTB | POR_B); + end + endgenerate + + //----------------------------------------------------------------------------- + // -- RSTA/B_BUSY Generation + //----------------------------------------------------------------------------- + + generate + if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && (C_EN_SAFETY_CKT == 1)) begin : RSTA_BUSY_NO_REG + always @(*) ram_rstram_a_busy = RSTA_I_SAFE | ENA_dly | ENA_dly_D; + always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstram_a_busy; + end + endgenerate + + generate + if (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0 && C_EN_SAFETY_CKT == 1) begin : RSTA_BUSY_WITH_REG + always @(*) ram_rstreg_a_busy = RSTA_I_SAFE | ENA_dly_reg | ENA_dly_reg_D; + always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstreg_a_busy; + end + endgenerate + + generate + if ( (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) && C_EN_SAFETY_CKT == 1) begin : SPRAM_RST_BUSY + always @(*) RSTB_BUSY = 1'b0; + end + endgenerate + + generate + if ( (C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && (C_MEM_TYPE != 0 && C_MEM_TYPE != 3) && C_EN_SAFETY_CKT == 1) begin : RSTB_BUSY_NO_REG + always @(*) ram_rstram_b_busy = RSTB_I_SAFE | ENB_dly | ENB_dly_D; + always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstram_b_busy; + end + endgenerate + + generate + if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : RSTB_BUSY_WITH_REG + always @(*) ram_rstreg_b_busy = RSTB_I_SAFE | ENB_dly_reg | ENB_dly_reg_D; + always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstreg_b_busy; + end + endgenerate + + //----------------------------------------------------------------------------- + // -- ENA/ENB Generation + //----------------------------------------------------------------------------- + + generate + if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && C_EN_SAFETY_CKT == 1) begin : ENA_NO_REG + always @(posedge clka) begin + ENA_dly <= #FLOP_DELAY RSTA_I_SAFE; + ENA_dly_D <= #FLOP_DELAY ENA_dly; + end + assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_D | ena_in); + end + endgenerate + + generate + if ( (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0) && C_EN_SAFETY_CKT == 1) begin : ENA_WITH_REG + always @(posedge clka) begin + ENA_dly_reg <= #FLOP_DELAY RSTA_I_SAFE; + ENA_dly_reg_D <= #FLOP_DELAY ENA_dly_reg; + end + assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_reg_D | ena_in); + end + endgenerate + + generate + if (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) begin : SPRAM_ENB + assign ENB_I_SAFE = 1'b0; + end + endgenerate + + generate + if ((C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : ENB_NO_REG + always @(posedge clkb) begin : PROC_ENB_GEN + ENB_dly <= #FLOP_DELAY RSTB_I_SAFE; + ENB_dly_D <= #FLOP_DELAY ENB_dly; + end + assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_D | ENB); + end + endgenerate + + generate + if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1)begin : ENB_WITH_REG + always @(posedge clkb) begin : PROC_ENB_GEN + ENB_dly_reg <= #FLOP_DELAY RSTB_I_SAFE; + ENB_dly_reg_D <= #FLOP_DELAY ENB_dly_reg; + end + assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_reg_D | ENB); + end + endgenerate + + generate if ((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 0)) begin : native_mem_module +blk_mem_gen_v8_4_3_mem_module + #(.C_CORENAME (C_CORENAME), + .C_FAMILY (C_FAMILY), + .C_XDEVICEFAMILY (C_XDEVICEFAMILY), + .C_MEM_TYPE (C_MEM_TYPE), + .C_BYTE_SIZE (C_BYTE_SIZE), + .C_ALGORITHM (C_ALGORITHM), + .C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK), + .C_PRIM_TYPE (C_PRIM_TYPE), + .C_LOAD_INIT_FILE (C_LOAD_INIT_FILE), + .C_INIT_FILE_NAME (C_INIT_FILE_NAME), + .C_INIT_FILE (C_INIT_FILE), + .C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA), + .C_DEFAULT_DATA (C_DEFAULT_DATA), + .C_RST_TYPE ("SYNC"), + .C_HAS_RSTA (C_HAS_RSTA), + .C_RST_PRIORITY_A (C_RST_PRIORITY_A), + .C_RSTRAM_A (C_RSTRAM_A), + .C_INITA_VAL (C_INITA_VAL), + .C_HAS_ENA (C_HAS_ENA), + .C_HAS_REGCEA (C_HAS_REGCEA), + .C_USE_BYTE_WEA (C_USE_BYTE_WEA), + .C_WEA_WIDTH (C_WEA_WIDTH), + .C_WRITE_MODE_A (C_WRITE_MODE_A), + .C_WRITE_WIDTH_A (C_WRITE_WIDTH_A), + .C_READ_WIDTH_A (C_READ_WIDTH_A), + .C_WRITE_DEPTH_A (C_WRITE_DEPTH_A), + .C_READ_DEPTH_A (C_READ_DEPTH_A), + .C_ADDRA_WIDTH (C_ADDRA_WIDTH), + .C_HAS_RSTB (C_HAS_RSTB), + .C_RST_PRIORITY_B (C_RST_PRIORITY_B), + .C_RSTRAM_B (C_RSTRAM_B), + .C_INITB_VAL (C_INITB_VAL), + .C_HAS_ENB (C_HAS_ENB), + .C_HAS_REGCEB (C_HAS_REGCEB), + .C_USE_BYTE_WEB (C_USE_BYTE_WEB), + .C_WEB_WIDTH (C_WEB_WIDTH), + .C_WRITE_MODE_B (C_WRITE_MODE_B), + .C_WRITE_WIDTH_B (C_WRITE_WIDTH_B), + .C_READ_WIDTH_B (C_READ_WIDTH_B), + .C_WRITE_DEPTH_B (C_WRITE_DEPTH_B), + .C_READ_DEPTH_B (C_READ_DEPTH_B), + .C_ADDRB_WIDTH (C_ADDRB_WIDTH), + .C_HAS_MEM_OUTPUT_REGS_A (C_HAS_MEM_OUTPUT_REGS_A), + .C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B), + .C_HAS_MUX_OUTPUT_REGS_A (C_HAS_MUX_OUTPUT_REGS_A), + .C_HAS_MUX_OUTPUT_REGS_B (C_HAS_MUX_OUTPUT_REGS_B), + .C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A), + .C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B), + .C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES), + .C_USE_SOFTECC (C_USE_SOFTECC), + .C_USE_ECC (C_USE_ECC), + .C_HAS_INJECTERR (C_HAS_INJECTERR), + .C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK), + .C_COMMON_CLK (C_COMMON_CLK), + .FLOP_DELAY (FLOP_DELAY), + .C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL), + .C_EN_ECC_PIPE (C_EN_ECC_PIPE), + .C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE)) + blk_mem_gen_v8_4_3_inst + (.CLKA (CLKA), + .RSTA (RSTA_I_SAFE),//(rsta_in), + .ENA (ENA_I_SAFE),//(ena_in), + .REGCEA (regcea_in), + .WEA (wea_in), + .ADDRA (addra_in), + .DINA (dina_in), + .DOUTA (DOUTA), + .CLKB (CLKB), + .RSTB (RSTB_I_SAFE),//(RSTB), + .ENB (ENB_I_SAFE),//(ENB), + .REGCEB (REGCEB), + .WEB (WEB), + .ADDRB (ADDRB), + .DINB (DINB), + .DOUTB (DOUTB), + .INJECTSBITERR (injectsbiterr_in), + .INJECTDBITERR (injectdbiterr_in), + .ECCPIPECE (ECCPIPECE), + .SLEEP (SLEEP), + .SBITERR (SBITERR), + .DBITERR (DBITERR), + .RDADDRECC (RDADDRECC) + ); + end + endgenerate + + generate if((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 1)) begin : native_mem_mapped_module + + localparam C_ADDRA_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_A); + localparam C_ADDRB_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_B); + + localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8); + localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8); + // localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_A/8); + // localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_B/8); + localparam C_MEM_MAP_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_MSB; + localparam C_MEM_MAP_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_MSB; + + // Data Width Number of LSB address bits to be discarded + // 1 to 16 1 + // 17 to 32 2 + // 33 to 64 3 + // 65 to 128 4 + // 129 to 256 5 + // 257 to 512 6 + // 513 to 1024 7 + // The following two constants determine this. + + localparam MEM_MAP_LOWER_BOUND_VAL_A = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8))); + localparam MEM_MAP_LOWER_BOUND_VAL_B = (log2int(divroundup(C_WRITE_WIDTH_B,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_B,8))); + localparam C_MEM_MAP_ADDRA_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_A; + localparam C_MEM_MAP_ADDRB_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_B; + + wire [C_ADDRB_WIDTH_ACTUAL-1 :0] rdaddrecc_i; + wire [C_ADDRB_WIDTH-1:C_MEM_MAP_ADDRB_WIDTH_MSB] msb_zero_i; + wire [C_MEM_MAP_ADDRB_WIDTH_LSB-1:0] lsb_zero_i; + + assign msb_zero_i = 0; + assign lsb_zero_i = 0; + assign RDADDRECC = {msb_zero_i,rdaddrecc_i,lsb_zero_i}; + +blk_mem_gen_v8_4_3_mem_module + #(.C_CORENAME (C_CORENAME), + .C_FAMILY (C_FAMILY), + .C_XDEVICEFAMILY (C_XDEVICEFAMILY), + .C_MEM_TYPE (C_MEM_TYPE), + .C_BYTE_SIZE (C_BYTE_SIZE), + .C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK), + .C_ALGORITHM (C_ALGORITHM), + .C_PRIM_TYPE (C_PRIM_TYPE), + .C_LOAD_INIT_FILE (C_LOAD_INIT_FILE), + .C_INIT_FILE_NAME (C_INIT_FILE_NAME), + .C_INIT_FILE (C_INIT_FILE), + .C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA), + .C_DEFAULT_DATA (C_DEFAULT_DATA), + .C_RST_TYPE ("SYNC"), + .C_HAS_RSTA (C_HAS_RSTA), + .C_RST_PRIORITY_A (C_RST_PRIORITY_A), + .C_RSTRAM_A (C_RSTRAM_A), + .C_INITA_VAL (C_INITA_VAL), + .C_HAS_ENA (C_HAS_ENA), + .C_HAS_REGCEA (C_HAS_REGCEA), + .C_USE_BYTE_WEA (C_USE_BYTE_WEA), + .C_WEA_WIDTH (C_WEA_WIDTH), + .C_WRITE_MODE_A (C_WRITE_MODE_A), + .C_WRITE_WIDTH_A (C_WRITE_WIDTH_A), + .C_READ_WIDTH_A (C_READ_WIDTH_A), + .C_WRITE_DEPTH_A (C_WRITE_DEPTH_A), + .C_READ_DEPTH_A (C_READ_DEPTH_A), + .C_ADDRA_WIDTH (C_ADDRA_WIDTH_ACTUAL), + .C_HAS_RSTB (C_HAS_RSTB), + .C_RST_PRIORITY_B (C_RST_PRIORITY_B), + .C_RSTRAM_B (C_RSTRAM_B), + .C_INITB_VAL (C_INITB_VAL), + .C_HAS_ENB (C_HAS_ENB), + .C_HAS_REGCEB (C_HAS_REGCEB), + .C_USE_BYTE_WEB (C_USE_BYTE_WEB), + .C_WEB_WIDTH (C_WEB_WIDTH), + .C_WRITE_MODE_B (C_WRITE_MODE_B), + .C_WRITE_WIDTH_B (C_WRITE_WIDTH_B), + .C_READ_WIDTH_B (C_READ_WIDTH_B), + .C_WRITE_DEPTH_B (C_WRITE_DEPTH_B), + .C_READ_DEPTH_B (C_READ_DEPTH_B), + .C_ADDRB_WIDTH (C_ADDRB_WIDTH_ACTUAL), + .C_HAS_MEM_OUTPUT_REGS_A (C_HAS_MEM_OUTPUT_REGS_A), + .C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B), + .C_HAS_MUX_OUTPUT_REGS_A (C_HAS_MUX_OUTPUT_REGS_A), + .C_HAS_MUX_OUTPUT_REGS_B (C_HAS_MUX_OUTPUT_REGS_B), + .C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A), + .C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B), + .C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES), + .C_USE_SOFTECC (C_USE_SOFTECC), + .C_USE_ECC (C_USE_ECC), + .C_HAS_INJECTERR (C_HAS_INJECTERR), + .C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK), + .C_COMMON_CLK (C_COMMON_CLK), + .FLOP_DELAY (FLOP_DELAY), + .C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL), + .C_EN_ECC_PIPE (C_EN_ECC_PIPE), + .C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE)) + blk_mem_gen_v8_4_3_inst + (.CLKA (CLKA), + .RSTA (RSTA_I_SAFE),//(rsta_in), + .ENA (ENA_I_SAFE),//(ena_in), + .REGCEA (regcea_in), + .WEA (wea_in), + .ADDRA (addra_in[C_MEM_MAP_ADDRA_WIDTH_MSB-1:C_MEM_MAP_ADDRA_WIDTH_LSB]), + .DINA (dina_in), + .DOUTA (DOUTA), + .CLKB (CLKB), + .RSTB (RSTB_I_SAFE),//(RSTB), + .ENB (ENB_I_SAFE),//(ENB), + .REGCEB (REGCEB), + .WEB (WEB), + .ADDRB (ADDRB[C_MEM_MAP_ADDRB_WIDTH_MSB-1:C_MEM_MAP_ADDRB_WIDTH_LSB]), + .DINB (DINB), + .DOUTB (DOUTB), + .INJECTSBITERR (injectsbiterr_in), + .INJECTDBITERR (injectdbiterr_in), + .ECCPIPECE (ECCPIPECE), + .SLEEP (SLEEP), + .SBITERR (SBITERR), + .DBITERR (DBITERR), + .RDADDRECC (rdaddrecc_i) + ); + end + endgenerate + + generate if (C_HAS_MEM_OUTPUT_REGS_B == 0 && C_HAS_MUX_OUTPUT_REGS_B == 0 ) begin : no_regs + assign S_AXI_RDATA = s_axi_rdata_c; + assign S_AXI_RLAST = s_axi_rlast_c; + assign S_AXI_RVALID = s_axi_rvalid_c; + assign S_AXI_RID = s_axi_rid_c; + assign S_AXI_RRESP = s_axi_rresp_c; + assign s_axi_rready_c = S_AXI_RREADY; + end + endgenerate + + generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regceb + assign regceb_c = s_axi_rvalid_c && s_axi_rready_c; + end + endgenerate + + generate if (C_HAS_MEM_OUTPUT_REGS_B == 0) begin : no_regceb + assign regceb_c = REGCEB; + end + endgenerate + + generate if (C_HAS_MUX_OUTPUT_REGS_B == 1) begin : only_core_op_regs + assign s_axi_payload_c = {s_axi_rid_c,s_axi_rdata_c,s_axi_rresp_c,s_axi_rlast_c}; + assign S_AXI_RID = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH]; + assign S_AXI_RDATA = m_axi_payload_c[C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B]; + assign S_AXI_RRESP = m_axi_payload_c[2:1]; + assign S_AXI_RLAST = m_axi_payload_c[0]; + end + endgenerate + + generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : only_emb_op_regs + assign s_axi_payload_c = {s_axi_rid_c,s_axi_rresp_c,s_axi_rlast_c}; + assign S_AXI_RDATA = s_axi_rdata_c; + assign S_AXI_RID = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH]; + assign S_AXI_RRESP = m_axi_payload_c[2:1]; + assign S_AXI_RLAST = m_axi_payload_c[0]; + end + endgenerate + + generate if (C_HAS_MUX_OUTPUT_REGS_B == 1 || C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regs_fwd + + blk_mem_axi_regs_fwd_v8_4 + #(.C_DATA_WIDTH (C_AXI_PAYLOAD)) + axi_regs_inst ( + .ACLK (S_ACLK), + .ARESET (s_aresetn_a_c), + .S_VALID (s_axi_rvalid_c), + .S_READY (s_axi_rready_c), + .S_PAYLOAD_DATA (s_axi_payload_c), + .M_VALID (S_AXI_RVALID), + .M_READY (S_AXI_RREADY), + .M_PAYLOAD_DATA (m_axi_payload_c) + ); + end + endgenerate + + generate if (C_INTERFACE_TYPE == 1) begin : axi_mem_module + +assign s_aresetn_a_c = !S_ARESETN; +assign S_AXI_BRESP = 2'b00; +assign s_axi_rresp_c = 2'b00; +assign s_axi_arlen_c = (C_AXI_TYPE == 1)?S_AXI_ARLEN:8'h0; + + blk_mem_axi_write_wrapper_beh_v8_4 + #(.C_INTERFACE_TYPE (C_INTERFACE_TYPE), + .C_AXI_TYPE (C_AXI_TYPE), + .C_AXI_SLAVE_TYPE (C_AXI_SLAVE_TYPE), + .C_MEMORY_TYPE (C_MEM_TYPE), + .C_WRITE_DEPTH_A (C_WRITE_DEPTH_A), + .C_AXI_AWADDR_WIDTH ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB), + .C_HAS_AXI_ID (C_HAS_AXI_ID), + .C_AXI_ID_WIDTH (C_AXI_ID_WIDTH), + .C_ADDRA_WIDTH (C_ADDRA_WIDTH), + .C_AXI_WDATA_WIDTH (C_WRITE_WIDTH_A), + .C_AXI_OS_WR (C_AXI_OS_WR)) + axi_wr_fsm ( + // AXI Global Signals + .S_ACLK (S_ACLK), + .S_ARESETN (s_aresetn_a_c), + // AXI Full/Lite Slave Write interface + .S_AXI_AWADDR (S_AXI_AWADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]), + .S_AXI_AWLEN (S_AXI_AWLEN), + .S_AXI_AWID (S_AXI_AWID), + .S_AXI_AWSIZE (S_AXI_AWSIZE), + .S_AXI_AWBURST (S_AXI_AWBURST), + .S_AXI_AWVALID (S_AXI_AWVALID), + .S_AXI_AWREADY (S_AXI_AWREADY), + .S_AXI_WVALID (S_AXI_WVALID), + .S_AXI_WREADY (S_AXI_WREADY), + .S_AXI_BVALID (S_AXI_BVALID), + .S_AXI_BREADY (S_AXI_BREADY), + .S_AXI_BID (S_AXI_BID), + // Signals for BRAM interfac( + .S_AXI_AWADDR_OUT (s_axi_awaddr_out_c), + .S_AXI_WR_EN (s_axi_wr_en_c) + ); + + blk_mem_axi_read_wrapper_beh_v8_4 + #(.C_INTERFACE_TYPE (C_INTERFACE_TYPE), + .C_AXI_TYPE (C_AXI_TYPE), + .C_AXI_SLAVE_TYPE (C_AXI_SLAVE_TYPE), + .C_MEMORY_TYPE (C_MEM_TYPE), + .C_WRITE_WIDTH_A (C_WRITE_WIDTH_A), + .C_ADDRA_WIDTH (C_ADDRA_WIDTH), + .C_AXI_PIPELINE_STAGES (1), + .C_AXI_ARADDR_WIDTH ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB), + .C_HAS_AXI_ID (C_HAS_AXI_ID), + .C_AXI_ID_WIDTH (C_AXI_ID_WIDTH), + .C_ADDRB_WIDTH (C_ADDRB_WIDTH)) + axi_rd_sm( + //AXI Global Signals + .S_ACLK (S_ACLK), + .S_ARESETN (s_aresetn_a_c), + //AXI Full/Lite Read Side + .S_AXI_ARADDR (S_AXI_ARADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]), + .S_AXI_ARLEN (s_axi_arlen_c), + .S_AXI_ARSIZE (S_AXI_ARSIZE), + .S_AXI_ARBURST (S_AXI_ARBURST), + .S_AXI_ARVALID (S_AXI_ARVALID), + .S_AXI_ARREADY (S_AXI_ARREADY), + .S_AXI_RLAST (s_axi_rlast_c), + .S_AXI_RVALID (s_axi_rvalid_c), + .S_AXI_RREADY (s_axi_rready_c), + .S_AXI_ARID (S_AXI_ARID), + .S_AXI_RID (s_axi_rid_c), + //AXI Full/Lite Read FSM Outputs + .S_AXI_ARADDR_OUT (s_axi_araddr_out_c), + .S_AXI_RD_EN (s_axi_rd_en_c) + ); + +blk_mem_gen_v8_4_3_mem_module + #(.C_CORENAME (C_CORENAME), + .C_FAMILY (C_FAMILY), + .C_XDEVICEFAMILY (C_XDEVICEFAMILY), + .C_MEM_TYPE (C_MEM_TYPE), + .C_BYTE_SIZE (C_BYTE_SIZE), + .C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK), + .C_ALGORITHM (C_ALGORITHM), + .C_PRIM_TYPE (C_PRIM_TYPE), + .C_LOAD_INIT_FILE (C_LOAD_INIT_FILE), + .C_INIT_FILE_NAME (C_INIT_FILE_NAME), + .C_INIT_FILE (C_INIT_FILE), + .C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA), + .C_DEFAULT_DATA (C_DEFAULT_DATA), + .C_RST_TYPE ("SYNC"), + .C_HAS_RSTA (C_HAS_RSTA), + .C_RST_PRIORITY_A (C_RST_PRIORITY_A), + .C_RSTRAM_A (C_RSTRAM_A), + .C_INITA_VAL (C_INITA_VAL), + .C_HAS_ENA (1), + .C_HAS_REGCEA (C_HAS_REGCEA), + .C_USE_BYTE_WEA (1), + .C_WEA_WIDTH (C_WEA_WIDTH), + .C_WRITE_MODE_A (C_WRITE_MODE_A), + .C_WRITE_WIDTH_A (C_WRITE_WIDTH_A), + .C_READ_WIDTH_A (C_READ_WIDTH_A), + .C_WRITE_DEPTH_A (C_WRITE_DEPTH_A), + .C_READ_DEPTH_A (C_READ_DEPTH_A), + .C_ADDRA_WIDTH (C_ADDRA_WIDTH), + .C_HAS_RSTB (C_HAS_RSTB), + .C_RST_PRIORITY_B (C_RST_PRIORITY_B), + .C_RSTRAM_B (C_RSTRAM_B), + .C_INITB_VAL (C_INITB_VAL), + .C_HAS_ENB (1), + .C_HAS_REGCEB (C_HAS_MEM_OUTPUT_REGS_B), + .C_USE_BYTE_WEB (1), + .C_WEB_WIDTH (C_WEB_WIDTH), + .C_WRITE_MODE_B (C_WRITE_MODE_B), + .C_WRITE_WIDTH_B (C_WRITE_WIDTH_B), + .C_READ_WIDTH_B (C_READ_WIDTH_B), + .C_WRITE_DEPTH_B (C_WRITE_DEPTH_B), + .C_READ_DEPTH_B (C_READ_DEPTH_B), + .C_ADDRB_WIDTH (C_ADDRB_WIDTH), + .C_HAS_MEM_OUTPUT_REGS_A (0), + .C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B), + .C_HAS_MUX_OUTPUT_REGS_A (0), + .C_HAS_MUX_OUTPUT_REGS_B (0), + .C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A), + .C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B), + .C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES), + .C_USE_SOFTECC (C_USE_SOFTECC), + .C_USE_ECC (C_USE_ECC), + .C_HAS_INJECTERR (C_HAS_INJECTERR), + .C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK), + .C_COMMON_CLK (C_COMMON_CLK), + .FLOP_DELAY (FLOP_DELAY), + .C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL), + .C_EN_ECC_PIPE (0), + .C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE)) + blk_mem_gen_v8_4_3_inst + (.CLKA (S_ACLK), + .RSTA (s_aresetn_a_c), + .ENA (s_axi_wr_en_c), + .REGCEA (regcea_in), + .WEA (S_AXI_WSTRB), + .ADDRA (s_axi_awaddr_out_c), + .DINA (S_AXI_WDATA), + .DOUTA (DOUTA), + .CLKB (S_ACLK), + .RSTB (s_aresetn_a_c), + .ENB (s_axi_rd_en_c), + .REGCEB (regceb_c), + .WEB (WEB_parameterized), + .ADDRB (s_axi_araddr_out_c), + .DINB (DINB), + .DOUTB (s_axi_rdata_c), + .INJECTSBITERR (injectsbiterr_in), + .INJECTDBITERR (injectdbiterr_in), + .SBITERR (SBITERR), + .DBITERR (DBITERR), + .ECCPIPECE (1'b0), + .SLEEP (1'b0), + .RDADDRECC (RDADDRECC) + ); + end + endgenerate +endmodule + + + diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/mem_init_files/freq_word.coe b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/mem_init_files/freq_word.coe new file mode 100755 index 00000000..590747a4 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/mem_init_files/freq_word.coe @@ -0,0 +1,83 @@ +MEMORY_INITIALIZATION_RADIX = 10; +MEMORY_INITIALIZATION_VECTOR = +1624, +1611, +1598, +1585, +1572, +1559, +1546, +1533, +1520, +1507, +1494, +1481, +1468, +1455, +1442, +1429, +1416, +1403, +1390, +1377, +1364, +1351, +1338, +1325, +1312, +1299, +1286, +1273, +1260, +1247, +1234, +1221, +1208, +1195, +1182, +1169, +1156, +1143, +1130, +1117, +1104, +1091, +1078, +1065, +1052, +1039, +1026, +1013, +1000, +987, +974, +961, +948, +935, +922, +909, +896, +883, +870, +857, +844, +831, +818, +805, +792, +779, +766, +753, +740, +727, +714, +701, +688, +675, +662, +649, +636, +623, +610, +597, +584, diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/mem_init_files/rom_freq_word.mif b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/mem_init_files/rom_freq_word.mif new file mode 100644 index 00000000..355400b4 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/mem_init_files/rom_freq_word.mif @@ -0,0 +1,81 @@ +11001011000 +11001001011 +11000111110 +11000110001 +11000100100 +11000010111 +11000001010 +10111111101 +10111110000 +10111100011 +10111010110 +10111001001 +10110111100 +10110101111 +10110100010 +10110010101 +10110001000 +10101111011 +10101101110 +10101100001 +10101010100 +10101000111 +10100111010 +10100101101 +10100100000 +10100010011 +10100000110 +10011111001 +10011101100 +10011011111 +10011010010 +10011000101 +10010111000 +10010101011 +10010011110 +10010010001 +10010000100 +10001110111 +10001101010 +10001011101 +10001010000 +10001000011 +10000110110 +10000101001 +10000011100 +10000001111 +10000000010 +01111110101 +01111101000 +01111011011 +01111001110 +01111000001 +01110110100 +01110100111 +01110011010 +01110001101 +01110000000 +01101110011 +01101100110 +01101011001 +01101001100 +01100111111 +01100110010 +01100100101 +01100011000 +01100001011 +01011111110 +01011110001 +01011100100 +01011010111 +01011001010 +01010111101 +01010110000 +01010100011 +01010010110 +01010001001 +01001111100 +01001101111 +01001100010 +01001010101 +01001001000 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_dmf_invert_prbs7_deci8/README.txt b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/README.txt similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_dmf_invert_prbs7_deci8/README.txt rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/README.txt diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/README.txt b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/README.txt new file mode 100644 index 00000000..34c03a45 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 18:55:24 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./rom_freq_word.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './rom_freq_word.sh' script. + +./rom_freq_word.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./rom_freq_word.sh -noclean_files + +For more information on the script, please type './rom_freq_word.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/activehdl/compile.do b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/compile.do similarity index 92% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/activehdl/compile.do rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/compile.do index 073a5dbb..1e5ae39c 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/activehdl/compile.do +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/compile.do @@ -20,7 +20,7 @@ vlog -work blk_mem_gen_v8_4_3 -v2k5 \ "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ vlog -work xil_defaultlib -v2k5 \ -"../../../ip/rom_hop_data/sim/rom_hop_data.v" \ +"../../../ip/rom_freq_word/sim/rom_freq_word.v" \ vlog -work xil_defaultlib \ "glbl.v" diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/activehdl/file_info.txt b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/file_info.txt similarity index 86% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/activehdl/file_info.txt rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/file_info.txt index eee4f6da..78704c4b 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/activehdl/file_info.txt +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/file_info.txt @@ -2,5 +2,5 @@ xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tool xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, -rom_hop_data.v,verilog,xil_defaultlib,../../../ip/rom_hop_data/sim/rom_hop_data.v, +rom_freq_word.v,verilog,xil_defaultlib,../../../ip/rom_freq_word/sim/rom_freq_word.v, glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/freq_word.coe b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/freq_word.coe new file mode 100755 index 00000000..590747a4 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/freq_word.coe @@ -0,0 +1,83 @@ +MEMORY_INITIALIZATION_RADIX = 10; +MEMORY_INITIALIZATION_VECTOR = +1624, +1611, +1598, +1585, +1572, +1559, +1546, +1533, +1520, +1507, +1494, +1481, +1468, +1455, +1442, +1429, +1416, +1403, +1390, +1377, +1364, +1351, +1338, +1325, +1312, +1299, +1286, +1273, +1260, +1247, +1234, +1221, +1208, +1195, +1182, +1169, +1156, +1143, +1130, +1117, +1104, +1091, +1078, +1065, +1052, +1039, +1026, +1013, +1000, +987, +974, +961, +948, +935, +922, +909, +896, +883, +870, +857, +844, +831, +818, +805, +792, +779, +766, +753, +740, +727, +714, +701, +688, +675, +662, +649, +636, +623, +610, +597, +584, diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_dmf_invert_prbs7_deci8/activehdl/glbl.v b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/glbl.v similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_dmf_invert_prbs7_deci8/activehdl/glbl.v rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/glbl.v diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/rom_freq_word.mif b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/rom_freq_word.mif new file mode 100644 index 00000000..355400b4 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/rom_freq_word.mif @@ -0,0 +1,81 @@ +11001011000 +11001001011 +11000111110 +11000110001 +11000100100 +11000010111 +11000001010 +10111111101 +10111110000 +10111100011 +10111010110 +10111001001 +10110111100 +10110101111 +10110100010 +10110010101 +10110001000 +10101111011 +10101101110 +10101100001 +10101010100 +10101000111 +10100111010 +10100101101 +10100100000 +10100010011 +10100000110 +10011111001 +10011101100 +10011011111 +10011010010 +10011000101 +10010111000 +10010101011 +10010011110 +10010010001 +10010000100 +10001110111 +10001101010 +10001011101 +10001010000 +10001000011 +10000110110 +10000101001 +10000011100 +10000001111 +10000000010 +01111110101 +01111101000 +01111011011 +01111001110 +01111000001 +01110110100 +01110100111 +01110011010 +01110001101 +01110000000 +01101110011 +01101100110 +01101011001 +01101001100 +01100111111 +01100110010 +01100100101 +01100011000 +01100001011 +01011111110 +01011110001 +01011100100 +01011010111 +01011001010 +01010111101 +01010110000 +01010100011 +01010010110 +01010001001 +01001111100 +01001101111 +01001100010 +01001010101 +01001001000 diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/rom_freq_word.sh b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/rom_freq_word.sh new file mode 100755 index 00000000..885cd093 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/rom_freq_word.sh @@ -0,0 +1,152 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : rom_freq_word.sh +# Simulator : Aldec Active-HDL Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 18:55:24 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: rom_freq_word.sh [-help] +# usage: rom_freq_word.sh [-lib_map_path] +# usage: rom_freq_word.sh [-noclean_files] +# usage: rom_freq_word.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'rom_freq_word.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "rom_freq_word.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./rom_freq_word.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./rom_freq_word.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: rom_freq_word.sh [-help]\n\ +Usage: rom_freq_word.sh [-lib_map_path]\n\ +Usage: rom_freq_word.sh [-reset_run]\n\ +Usage: rom_freq_word.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_dmf_invert_prbs7_deci8/activehdl/fir_dmf_invert_prbs7_deci8.udo b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/rom_freq_word.udo similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_dmf_invert_prbs7_deci8/activehdl/fir_dmf_invert_prbs7_deci8.udo rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/rom_freq_word.udo diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/simulate.do b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/simulate.do new file mode 100644 index 00000000..b880455d --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+rom_freq_word -L xil_defaultlib -L xpm -L blk_mem_gen_v8_4_3 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.rom_freq_word xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {rom_freq_word.udo} + +run -all + +endsim + +quit -force diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_dmf_invert_prbs7_deci8/activehdl/wave.do b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/wave.do similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_dmf_invert_prbs7_deci8/activehdl/wave.do rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/wave.do diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/ies/README.txt b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/ies/README.txt new file mode 100644 index 00000000..55c357de --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/ies/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 18:55:24 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./rom_freq_word.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './rom_freq_word.sh' script. + +./rom_freq_word.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./rom_freq_word.sh -noclean_files + +For more information on the script, please type './rom_freq_word.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/ies/file_info.txt b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/ies/file_info.txt similarity index 86% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/ies/file_info.txt rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/ies/file_info.txt index eee4f6da..78704c4b 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/ies/file_info.txt +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/ies/file_info.txt @@ -2,5 +2,5 @@ xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tool xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, -rom_hop_data.v,verilog,xil_defaultlib,../../../ip/rom_hop_data/sim/rom_hop_data.v, +rom_freq_word.v,verilog,xil_defaultlib,../../../ip/rom_freq_word/sim/rom_freq_word.v, glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/ies/freq_word.coe b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/ies/freq_word.coe new file mode 100755 index 00000000..590747a4 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/ies/freq_word.coe @@ -0,0 +1,83 @@ +MEMORY_INITIALIZATION_RADIX = 10; +MEMORY_INITIALIZATION_VECTOR = +1624, +1611, +1598, +1585, +1572, +1559, +1546, +1533, +1520, +1507, +1494, +1481, +1468, +1455, +1442, +1429, +1416, +1403, +1390, +1377, +1364, +1351, +1338, +1325, +1312, +1299, +1286, +1273, +1260, +1247, +1234, +1221, +1208, +1195, +1182, +1169, +1156, +1143, +1130, +1117, +1104, +1091, +1078, +1065, +1052, +1039, +1026, +1013, +1000, +987, +974, +961, +948, +935, +922, +909, +896, +883, +870, +857, +844, +831, +818, +805, +792, +779, +766, +753, +740, +727, +714, +701, +688, +675, +662, +649, +636, +623, +610, +597, +584, diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_dmf_invert_prbs7_deci8/ies/glbl.v b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/ies/glbl.v similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_dmf_invert_prbs7_deci8/ies/glbl.v rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/ies/glbl.v diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/ies/rom_freq_word.mif b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/ies/rom_freq_word.mif new file mode 100644 index 00000000..355400b4 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/ies/rom_freq_word.mif @@ -0,0 +1,81 @@ +11001011000 +11001001011 +11000111110 +11000110001 +11000100100 +11000010111 +11000001010 +10111111101 +10111110000 +10111100011 +10111010110 +10111001001 +10110111100 +10110101111 +10110100010 +10110010101 +10110001000 +10101111011 +10101101110 +10101100001 +10101010100 +10101000111 +10100111010 +10100101101 +10100100000 +10100010011 +10100000110 +10011111001 +10011101100 +10011011111 +10011010010 +10011000101 +10010111000 +10010101011 +10010011110 +10010010001 +10010000100 +10001110111 +10001101010 +10001011101 +10001010000 +10001000011 +10000110110 +10000101001 +10000011100 +10000001111 +10000000010 +01111110101 +01111101000 +01111011011 +01111001110 +01111000001 +01110110100 +01110100111 +01110011010 +01110001101 +01110000000 +01101110011 +01101100110 +01101011001 +01101001100 +01100111111 +01100110010 +01100100101 +01100011000 +01100001011 +01011111110 +01011110001 +01011100100 +01011010111 +01011001010 +01010111101 +01010110000 +01010100011 +01010010110 +01010001001 +01001111100 +01001101111 +01001100010 +01001010101 +01001001000 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/ies/rom_hop_data.sh b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/ies/rom_freq_word.sh similarity index 86% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/ies/rom_hop_data.sh rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/ies/rom_freq_word.sh index aeb78fa5..e4560370 100755 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/ies/rom_hop_data.sh +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/ies/rom_freq_word.sh @@ -2,22 +2,22 @@ #********************************************************************************************************* # Vivado (TM) v2019.1.3 (64-bit) # -# Filename : rom_hop_data.sh +# Filename : rom_freq_word.sh # Simulator : Cadence Incisive Enterprise Simulator # Description : Simulation script for compiling, elaborating and verifying the project source files. # The script will automatically create the design libraries sub-directories in the run # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon Apr 17 13:38:36 CST 2023 +# Generated by Vivado on Mon May 08 18:55:24 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. # -# usage: rom_hop_data.sh [-help] -# usage: rom_hop_data.sh [-lib_map_path] -# usage: rom_hop_data.sh [-noclean_files] -# usage: rom_hop_data.sh [-reset_run] +# usage: rom_freq_word.sh [-help] +# usage: rom_freq_word.sh [-lib_map_path] +# usage: rom_freq_word.sh [-noclean_files] +# usage: rom_freq_word.sh [-reset_run] # # Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the # 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the @@ -27,7 +27,7 @@ # # You can also point to the simulation libraries by either replacing the in this # script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'rom_hop_data.sh -help' for more information. +# executing this script. Please type 'rom_freq_word.sh -help' for more information. # # Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' # @@ -54,7 +54,7 @@ design_libs=(xil_defaultlib xpm blk_mem_gen_v8_4_3) sim_lib_dir="ies_lib" # Script info -echo -e "rom_hop_data.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" +echo -e "rom_freq_word.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" # Main steps run() @@ -73,7 +73,7 @@ execute() -reflib "$ref_lib_dir/secureip:secureip" \ -reflib "$ref_lib_dir/unimacro:unimacro" \ -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ - -top xil_defaultlib.rom_hop_data \ + -top xil_defaultlib.rom_freq_word \ -f run.f \ -top glbl \ glbl.v @@ -85,7 +85,7 @@ setup() case $1 in "-lib_map_path" ) if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./rom_hop_data.sh -help\" for more information)\n" + echo -e "ERROR: Simulation library directory path not specified (type \"./rom_freq_word.sh -help\" for more information)\n" exit 1 else ref_lib_dir=$2 @@ -144,7 +144,7 @@ reset_run() check_args() { if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./rom_hop_data.sh -help\" for more information)\n" + echo -e "ERROR: Unknown option specified '$2' (type \"./rom_freq_word.sh -help\" for more information)\n" exit 1 fi @@ -156,10 +156,10 @@ check_args() # Script usage usage() { - msg="Usage: rom_hop_data.sh [-help]\n\ -Usage: rom_hop_data.sh [-lib_map_path]\n\ -Usage: rom_hop_data.sh [-reset_run]\n\ -Usage: rom_hop_data.sh [-noclean_files]\n\n\ + msg="Usage: rom_freq_word.sh [-help]\n\ +Usage: rom_freq_word.sh [-lib_map_path]\n\ +Usage: rom_freq_word.sh [-reset_run]\n\ +Usage: rom_freq_word.sh [-noclean_files]\n\n\ [-help] -- Print help information for this script\n\n\ [-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/ies/run.f b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/ies/run.f similarity index 90% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/ies/run.f rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/ies/run.f index f648a0a1..09c85501 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/ies/run.f +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/ies/run.f @@ -9,7 +9,7 @@ "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ -endlib -makelib ies_lib/xil_defaultlib \ - "../../../ip/rom_hop_data/sim/rom_hop_data.v" \ + "../../../ip/rom_freq_word/sim/rom_freq_word.v" \ -endlib -makelib ies_lib/xil_defaultlib \ glbl.v diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/README.txt b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/README.txt new file mode 100644 index 00000000..34c03a45 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 18:55:24 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./rom_freq_word.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './rom_freq_word.sh' script. + +./rom_freq_word.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./rom_freq_word.sh -noclean_files + +For more information on the script, please type './rom_freq_word.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/modelsim/compile.do b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/compile.do similarity index 81% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/modelsim/compile.do rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/compile.do index 9fc08028..8b8458a0 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/modelsim/compile.do +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/compile.do @@ -6,7 +6,7 @@ vlib modelsim_lib/msim/xil_defaultlib vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib vlog -work xil_defaultlib -64 -incr \ -"../../../ip/rom_hop_data/sim/rom_hop_data.v" \ +"../../../ip/rom_freq_word/sim/rom_freq_word.v" \ vlog -work xil_defaultlib \ diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/file_info.txt b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/file_info.txt new file mode 100644 index 00000000..fe59d479 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/file_info.txt @@ -0,0 +1,2 @@ +rom_freq_word.v,verilog,xil_defaultlib,../../../ip/rom_freq_word/sim/rom_freq_word.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/freq_word.coe b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/freq_word.coe new file mode 100755 index 00000000..590747a4 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/freq_word.coe @@ -0,0 +1,83 @@ +MEMORY_INITIALIZATION_RADIX = 10; +MEMORY_INITIALIZATION_VECTOR = +1624, +1611, +1598, +1585, +1572, +1559, +1546, +1533, +1520, +1507, +1494, +1481, +1468, +1455, +1442, +1429, +1416, +1403, +1390, +1377, +1364, +1351, +1338, +1325, +1312, +1299, +1286, +1273, +1260, +1247, +1234, +1221, +1208, +1195, +1182, +1169, +1156, +1143, +1130, +1117, +1104, +1091, +1078, +1065, +1052, +1039, +1026, +1013, +1000, +987, +974, +961, +948, +935, +922, +909, +896, +883, +870, +857, +844, +831, +818, +805, +792, +779, +766, +753, +740, +727, +714, +701, +688, +675, +662, +649, +636, +623, +610, +597, +584, diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_dmf_invert_prbs7_deci8/questa/glbl.v b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/glbl.v similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_dmf_invert_prbs7_deci8/questa/glbl.v rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/glbl.v diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/rom_freq_word.mif b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/rom_freq_word.mif new file mode 100644 index 00000000..355400b4 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/rom_freq_word.mif @@ -0,0 +1,81 @@ +11001011000 +11001001011 +11000111110 +11000110001 +11000100100 +11000010111 +11000001010 +10111111101 +10111110000 +10111100011 +10111010110 +10111001001 +10110111100 +10110101111 +10110100010 +10110010101 +10110001000 +10101111011 +10101101110 +10101100001 +10101010100 +10101000111 +10100111010 +10100101101 +10100100000 +10100010011 +10100000110 +10011111001 +10011101100 +10011011111 +10011010010 +10011000101 +10010111000 +10010101011 +10010011110 +10010010001 +10010000100 +10001110111 +10001101010 +10001011101 +10001010000 +10001000011 +10000110110 +10000101001 +10000011100 +10000001111 +10000000010 +01111110101 +01111101000 +01111011011 +01111001110 +01111000001 +01110110100 +01110100111 +01110011010 +01110001101 +01110000000 +01101110011 +01101100110 +01101011001 +01101001100 +01100111111 +01100110010 +01100100101 +01100011000 +01100001011 +01011111110 +01011110001 +01011100100 +01011010111 +01011001010 +01010111101 +01010110000 +01010100011 +01010010110 +01010001001 +01001111100 +01001101111 +01001100010 +01001010101 +01001001000 diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/rom_freq_word.sh b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/rom_freq_word.sh new file mode 100755 index 00000000..565c605c --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/rom_freq_word.sh @@ -0,0 +1,167 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : rom_freq_word.sh +# Simulator : Mentor Graphics ModelSim Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 18:55:24 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: rom_freq_word.sh [-help] +# usage: rom_freq_word.sh [-lib_map_path] +# usage: rom_freq_word.sh [-noclean_files] +# usage: rom_freq_word.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'rom_freq_word.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "rom_freq_word.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./rom_freq_word.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Software/Xilinx/CompLib/Model/2019.1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="modelsim_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./rom_freq_word.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: rom_freq_word.sh [-help]\n\ +Usage: rom_freq_word.sh [-lib_map_path]\n\ +Usage: rom_freq_word.sh [-reset_run]\n\ +Usage: rom_freq_word.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_dmf_invert_prbs7_deci8/modelsim/fir_dmf_invert_prbs7_deci8.udo b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/rom_freq_word.udo similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_dmf_invert_prbs7_deci8/modelsim/fir_dmf_invert_prbs7_deci8.udo rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/rom_freq_word.udo diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/modelsim/simulate.do b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/simulate.do similarity index 74% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/modelsim/simulate.do rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/simulate.do index e578449e..3bc7aaf4 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/modelsim/simulate.do +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/simulate.do @@ -1,7 +1,7 @@ onbreak {quit -f} onerror {quit -f} -vsim -voptargs="+acc" -t 1ps -L blk_mem_gen_v8_4_3 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm -lib xil_defaultlib xil_defaultlib.rom_hop_data xil_defaultlib.glbl +vsim -voptargs="+acc" -t 1ps -L blk_mem_gen_v8_4_3 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm -lib xil_defaultlib xil_defaultlib.rom_freq_word xil_defaultlib.glbl do {wave.do} @@ -9,7 +9,7 @@ view wave view structure view signals -do {rom_hop_data.udo} +do {rom_freq_word.udo} run -all diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_dmf_invert_prbs7_deci8/questa/wave.do b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/wave.do similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_dmf_invert_prbs7_deci8/questa/wave.do rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/wave.do diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/README.txt b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/README.txt new file mode 100644 index 00000000..34c03a45 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 18:55:24 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./rom_freq_word.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './rom_freq_word.sh' script. + +./rom_freq_word.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./rom_freq_word.sh -noclean_files + +For more information on the script, please type './rom_freq_word.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/questa/compile.do b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/compile.do similarity index 93% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/questa/compile.do rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/compile.do index d27fcf7a..bd408354 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/questa/compile.do +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/compile.do @@ -20,7 +20,7 @@ vlog -work blk_mem_gen_v8_4_3 -64 \ "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ vlog -work xil_defaultlib -64 \ -"../../../ip/rom_hop_data/sim/rom_hop_data.v" \ +"../../../ip/rom_freq_word/sim/rom_freq_word.v" \ vlog -work xil_defaultlib \ "glbl.v" diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/questa/elaborate.do b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/elaborate.do similarity index 60% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/questa/elaborate.do rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/elaborate.do index 7a6b513d..f81f2bb9 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/questa/elaborate.do +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/elaborate.do @@ -1 +1 @@ -vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L blk_mem_gen_v8_4_3 -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.rom_hop_data xil_defaultlib.glbl -o rom_hop_data_opt +vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L blk_mem_gen_v8_4_3 -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.rom_freq_word xil_defaultlib.glbl -o rom_freq_word_opt diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/questa/file_info.txt b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/file_info.txt similarity index 86% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/questa/file_info.txt rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/file_info.txt index eee4f6da..78704c4b 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/questa/file_info.txt +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/file_info.txt @@ -2,5 +2,5 @@ xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tool xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, -rom_hop_data.v,verilog,xil_defaultlib,../../../ip/rom_hop_data/sim/rom_hop_data.v, +rom_freq_word.v,verilog,xil_defaultlib,../../../ip/rom_freq_word/sim/rom_freq_word.v, glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/freq_word.coe b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/freq_word.coe new file mode 100755 index 00000000..590747a4 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/freq_word.coe @@ -0,0 +1,83 @@ +MEMORY_INITIALIZATION_RADIX = 10; +MEMORY_INITIALIZATION_VECTOR = +1624, +1611, +1598, +1585, +1572, +1559, +1546, +1533, +1520, +1507, +1494, +1481, +1468, +1455, +1442, +1429, +1416, +1403, +1390, +1377, +1364, +1351, +1338, +1325, +1312, +1299, +1286, +1273, +1260, +1247, +1234, +1221, +1208, +1195, +1182, +1169, +1156, +1143, +1130, +1117, +1104, +1091, +1078, +1065, +1052, +1039, +1026, +1013, +1000, +987, +974, +961, +948, +935, +922, +909, +896, +883, +870, +857, +844, +831, +818, +805, +792, +779, +766, +753, +740, +727, +714, +701, +688, +675, +662, +649, +636, +623, +610, +597, +584, diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_dmf_invert_prbs7_deci8/riviera/glbl.v b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/glbl.v similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_dmf_invert_prbs7_deci8/riviera/glbl.v rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/glbl.v diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/rom_freq_word.mif b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/rom_freq_word.mif new file mode 100644 index 00000000..355400b4 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/rom_freq_word.mif @@ -0,0 +1,81 @@ +11001011000 +11001001011 +11000111110 +11000110001 +11000100100 +11000010111 +11000001010 +10111111101 +10111110000 +10111100011 +10111010110 +10111001001 +10110111100 +10110101111 +10110100010 +10110010101 +10110001000 +10101111011 +10101101110 +10101100001 +10101010100 +10101000111 +10100111010 +10100101101 +10100100000 +10100010011 +10100000110 +10011111001 +10011101100 +10011011111 +10011010010 +10011000101 +10010111000 +10010101011 +10010011110 +10010010001 +10010000100 +10001110111 +10001101010 +10001011101 +10001010000 +10001000011 +10000110110 +10000101001 +10000011100 +10000001111 +10000000010 +01111110101 +01111101000 +01111011011 +01111001110 +01111000001 +01110110100 +01110100111 +01110011010 +01110001101 +01110000000 +01101110011 +01101100110 +01101011001 +01101001100 +01100111111 +01100110010 +01100100101 +01100011000 +01100001011 +01011111110 +01011110001 +01011100100 +01011010111 +01011001010 +01010111101 +01010110000 +01010100011 +01010010110 +01010001001 +01001111100 +01001101111 +01001100010 +01001010101 +01001001000 diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/rom_freq_word.sh b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/rom_freq_word.sh new file mode 100755 index 00000000..5c854a90 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/rom_freq_word.sh @@ -0,0 +1,174 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : rom_freq_word.sh +# Simulator : Mentor Graphics Questa Advanced Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 18:55:24 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: rom_freq_word.sh [-help] +# usage: rom_freq_word.sh [-lib_map_path] +# usage: rom_freq_word.sh [-noclean_files] +# usage: rom_freq_word.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'rom_freq_word.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "rom_freq_word.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +elaborate() +{ + source elaborate.do 2>&1 | tee -a elaborate.log +} + +# RUN_STEP: +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./rom_freq_word.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/questa" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="questa_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./rom_freq_word.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: rom_freq_word.sh [-help]\n\ +Usage: rom_freq_word.sh [-lib_map_path]\n\ +Usage: rom_freq_word.sh [-reset_run]\n\ +Usage: rom_freq_word.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_dmf_invert_prbs7_deci8/questa/fir_dmf_invert_prbs7_deci8.udo b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/rom_freq_word.udo similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_dmf_invert_prbs7_deci8/questa/fir_dmf_invert_prbs7_deci8.udo rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/rom_freq_word.udo diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_null_phase/questa/simulate.do b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/simulate.do similarity index 60% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_null_phase/questa/simulate.do rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/simulate.do index cb239119..d8b2f89d 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_null_phase/questa/simulate.do +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/simulate.do @@ -1,7 +1,7 @@ onbreak {quit -f} onerror {quit -f} -vsim -t 1ps -lib xil_defaultlib vio_null_phase_opt +vsim -t 1ps -lib xil_defaultlib rom_freq_word_opt do {wave.do} @@ -9,7 +9,7 @@ view wave view structure view signals -do {vio_null_phase.udo} +do {rom_freq_word.udo} run -all diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_dmf_invert_prbs7_deci8/riviera/wave.do b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/wave.do similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_dmf_invert_prbs7_deci8/riviera/wave.do rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/wave.do diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/README.txt b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/README.txt new file mode 100644 index 00000000..34c03a45 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 18:55:24 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./rom_freq_word.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './rom_freq_word.sh' script. + +./rom_freq_word.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./rom_freq_word.sh -noclean_files + +For more information on the script, please type './rom_freq_word.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/riviera/compile.do b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/compile.do similarity index 92% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/riviera/compile.do rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/compile.do index 6a4a7a3f..1baef140 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/riviera/compile.do +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/compile.do @@ -20,7 +20,7 @@ vlog -work blk_mem_gen_v8_4_3 -v2k5 \ "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ vlog -work xil_defaultlib -v2k5 \ -"../../../ip/rom_hop_data/sim/rom_hop_data.v" \ +"../../../ip/rom_freq_word/sim/rom_freq_word.v" \ vlog -work xil_defaultlib \ "glbl.v" diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/riviera/file_info.txt b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/file_info.txt similarity index 86% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/riviera/file_info.txt rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/file_info.txt index eee4f6da..78704c4b 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/riviera/file_info.txt +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/file_info.txt @@ -2,5 +2,5 @@ xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tool xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, -rom_hop_data.v,verilog,xil_defaultlib,../../../ip/rom_hop_data/sim/rom_hop_data.v, +rom_freq_word.v,verilog,xil_defaultlib,../../../ip/rom_freq_word/sim/rom_freq_word.v, glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/freq_word.coe b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/freq_word.coe new file mode 100755 index 00000000..590747a4 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/freq_word.coe @@ -0,0 +1,83 @@ +MEMORY_INITIALIZATION_RADIX = 10; +MEMORY_INITIALIZATION_VECTOR = +1624, +1611, +1598, +1585, +1572, +1559, +1546, +1533, +1520, +1507, +1494, +1481, +1468, +1455, +1442, +1429, +1416, +1403, +1390, +1377, +1364, +1351, +1338, +1325, +1312, +1299, +1286, +1273, +1260, +1247, +1234, +1221, +1208, +1195, +1182, +1169, +1156, +1143, +1130, +1117, +1104, +1091, +1078, +1065, +1052, +1039, +1026, +1013, +1000, +987, +974, +961, +948, +935, +922, +909, +896, +883, +870, +857, +844, +831, +818, +805, +792, +779, +766, +753, +740, +727, +714, +701, +688, +675, +662, +649, +636, +623, +610, +597, +584, diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_dmf_invert_prbs7_deci8/xcelium/glbl.v b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/glbl.v similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_dmf_invert_prbs7_deci8/xcelium/glbl.v rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/glbl.v diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/rom_freq_word.mif b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/rom_freq_word.mif new file mode 100644 index 00000000..355400b4 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/rom_freq_word.mif @@ -0,0 +1,81 @@ +11001011000 +11001001011 +11000111110 +11000110001 +11000100100 +11000010111 +11000001010 +10111111101 +10111110000 +10111100011 +10111010110 +10111001001 +10110111100 +10110101111 +10110100010 +10110010101 +10110001000 +10101111011 +10101101110 +10101100001 +10101010100 +10101000111 +10100111010 +10100101101 +10100100000 +10100010011 +10100000110 +10011111001 +10011101100 +10011011111 +10011010010 +10011000101 +10010111000 +10010101011 +10010011110 +10010010001 +10010000100 +10001110111 +10001101010 +10001011101 +10001010000 +10001000011 +10000110110 +10000101001 +10000011100 +10000001111 +10000000010 +01111110101 +01111101000 +01111011011 +01111001110 +01111000001 +01110110100 +01110100111 +01110011010 +01110001101 +01110000000 +01101110011 +01101100110 +01101011001 +01101001100 +01100111111 +01100110010 +01100100101 +01100011000 +01100001011 +01011111110 +01011110001 +01011100100 +01011010111 +01011001010 +01010111101 +01010110000 +01010100011 +01010010110 +01010001001 +01001111100 +01001101111 +01001100010 +01001010101 +01001001000 diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/rom_freq_word.sh b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/rom_freq_word.sh new file mode 100755 index 00000000..61eec7db --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/rom_freq_word.sh @@ -0,0 +1,153 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : rom_freq_word.sh +# Simulator : Aldec Riviera-PRO Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 18:55:24 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: rom_freq_word.sh [-help] +# usage: rom_freq_word.sh [-lib_map_path] +# usage: rom_freq_word.sh [-noclean_files] +# usage: rom_freq_word.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'rom_freq_word.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "rom_freq_word.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./rom_freq_word.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/riviera" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./rom_freq_word.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: rom_freq_word.sh [-help]\n\ +Usage: rom_freq_word.sh [-lib_map_path]\n\ +Usage: rom_freq_word.sh [-reset_run]\n\ +Usage: rom_freq_word.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_dmf_invert_prbs7_deci8/riviera/fir_dmf_invert_prbs7_deci8.udo b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/rom_freq_word.udo similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_dmf_invert_prbs7_deci8/riviera/fir_dmf_invert_prbs7_deci8.udo rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/rom_freq_word.udo diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/simulate.do b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/simulate.do new file mode 100644 index 00000000..b880455d --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+rom_freq_word -L xil_defaultlib -L xpm -L blk_mem_gen_v8_4_3 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.rom_freq_word xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {rom_freq_word.udo} + +run -all + +endsim + +quit -force diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/activehdl/wave.do b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/wave.do similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/activehdl/wave.do rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/wave.do diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/README.txt b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/README.txt new file mode 100644 index 00000000..34c03a45 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 18:55:24 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./rom_freq_word.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './rom_freq_word.sh' script. + +./rom_freq_word.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./rom_freq_word.sh -noclean_files + +For more information on the script, please type './rom_freq_word.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/file_info.txt b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/file_info.txt new file mode 100644 index 00000000..fe59d479 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/file_info.txt @@ -0,0 +1,2 @@ +rom_freq_word.v,verilog,xil_defaultlib,../../../ip/rom_freq_word/sim/rom_freq_word.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/freq_word.coe b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/freq_word.coe new file mode 100755 index 00000000..590747a4 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/freq_word.coe @@ -0,0 +1,83 @@ +MEMORY_INITIALIZATION_RADIX = 10; +MEMORY_INITIALIZATION_VECTOR = +1624, +1611, +1598, +1585, +1572, +1559, +1546, +1533, +1520, +1507, +1494, +1481, +1468, +1455, +1442, +1429, +1416, +1403, +1390, +1377, +1364, +1351, +1338, +1325, +1312, +1299, +1286, +1273, +1260, +1247, +1234, +1221, +1208, +1195, +1182, +1169, +1156, +1143, +1130, +1117, +1104, +1091, +1078, +1065, +1052, +1039, +1026, +1013, +1000, +987, +974, +961, +948, +935, +922, +909, +896, +883, +870, +857, +844, +831, +818, +805, +792, +779, +766, +753, +740, +727, +714, +701, +688, +675, +662, +649, +636, +623, +610, +597, +584, diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/activehdl/glbl.v b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/glbl.v similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/activehdl/glbl.v rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/glbl.v diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/rom_freq_word.mif b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/rom_freq_word.mif new file mode 100644 index 00000000..355400b4 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/rom_freq_word.mif @@ -0,0 +1,81 @@ +11001011000 +11001001011 +11000111110 +11000110001 +11000100100 +11000010111 +11000001010 +10111111101 +10111110000 +10111100011 +10111010110 +10111001001 +10110111100 +10110101111 +10110100010 +10110010101 +10110001000 +10101111011 +10101101110 +10101100001 +10101010100 +10101000111 +10100111010 +10100101101 +10100100000 +10100010011 +10100000110 +10011111001 +10011101100 +10011011111 +10011010010 +10011000101 +10010111000 +10010101011 +10010011110 +10010010001 +10010000100 +10001110111 +10001101010 +10001011101 +10001010000 +10001000011 +10000110110 +10000101001 +10000011100 +10000001111 +10000000010 +01111110101 +01111101000 +01111011011 +01111001110 +01111000001 +01110110100 +01110100111 +01110011010 +01110001101 +01110000000 +01101110011 +01101100110 +01101011001 +01101001100 +01100111111 +01100110010 +01100100101 +01100011000 +01100001011 +01011111110 +01011110001 +01011100100 +01011010111 +01011001010 +01010111101 +01010110000 +01010100011 +01010010110 +01010001001 +01001111100 +01001101111 +01001100010 +01001010101 +01001001000 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/vcs/rom_hop_data.sh b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/rom_freq_word.sh similarity index 82% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/vcs/rom_hop_data.sh rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/rom_freq_word.sh index a406009b..abf1b7d1 100755 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/vcs/rom_hop_data.sh +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/rom_freq_word.sh @@ -2,22 +2,22 @@ #********************************************************************************************************* # Vivado (TM) v2019.1.3 (64-bit) # -# Filename : rom_hop_data.sh +# Filename : rom_freq_word.sh # Simulator : Synopsys Verilog Compiler Simulator # Description : Simulation script for compiling, elaborating and verifying the project source files. # The script will automatically create the design libraries sub-directories in the run # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon Apr 17 13:38:36 CST 2023 +# Generated by Vivado on Mon May 08 18:55:24 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. # -# usage: rom_hop_data.sh [-help] -# usage: rom_hop_data.sh [-lib_map_path] -# usage: rom_hop_data.sh [-noclean_files] -# usage: rom_hop_data.sh [-reset_run] +# usage: rom_freq_word.sh [-help] +# usage: rom_freq_word.sh [-lib_map_path] +# usage: rom_freq_word.sh [-noclean_files] +# usage: rom_freq_word.sh [-reset_run] # # Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the # 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the @@ -27,7 +27,7 @@ # # You can also point to the simulation libraries by either replacing the in this # script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'rom_hop_data.sh -help' for more information. +# executing this script. Please type 'rom_freq_word.sh -help' for more information. # # Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' # @@ -54,7 +54,7 @@ design_libs=(xil_defaultlib) sim_lib_dir="vcs_lib" # Script info -echo -e "rom_hop_data.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" +echo -e "rom_freq_word.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" # Main steps run() @@ -71,7 +71,7 @@ compile() { # Compile design files vlogan -work xil_defaultlib $vlogan_opts +v2k \ - "$ref_dir/../../../ip/rom_hop_data/sim/rom_hop_data.v" \ + "$ref_dir/../../../ip/rom_freq_word/sim/rom_freq_word.v" \ 2>&1 | tee -a vlogan.log @@ -84,13 +84,13 @@ compile() # RUN_STEP: elaborate() { - vcs $vcs_elab_opts xil_defaultlib.rom_hop_data xil_defaultlib.glbl -o rom_hop_data_simv + vcs $vcs_elab_opts xil_defaultlib.rom_freq_word xil_defaultlib.glbl -o rom_freq_word_simv } # RUN_STEP: simulate() { - ./rom_hop_data_simv $vcs_sim_opts -do simulate.do + ./rom_freq_word_simv $vcs_sim_opts -do simulate.do } # STEP: setup @@ -99,7 +99,7 @@ setup() case $1 in "-lib_map_path" ) if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./rom_hop_data.sh -help\" for more information)\n" + echo -e "ERROR: Simulation library directory path not specified (type \"./rom_freq_word.sh -help\" for more information)\n" exit 1 fi create_lib_mappings $2 @@ -175,7 +175,7 @@ create_lib_dir() # Delete generated data from the previous run reset_run() { - files_to_remove=(ucli.key rom_hop_data_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc rom_hop_data_simv.daidir) + files_to_remove=(ucli.key rom_freq_word_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc rom_freq_word_simv.daidir) for (( i=0; i<${#files_to_remove[*]}; i++ )); do file="${files_to_remove[i]}" if [[ -e $file ]]; then @@ -190,7 +190,7 @@ reset_run() check_args() { if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./rom_hop_data.sh -help\" for more information)\n" + echo -e "ERROR: Unknown option specified '$2' (type \"./rom_freq_word.sh -help\" for more information)\n" exit 1 fi @@ -202,10 +202,10 @@ check_args() # Script usage usage() { - msg="Usage: rom_hop_data.sh [-help]\n\ -Usage: rom_hop_data.sh [-lib_map_path]\n\ -Usage: rom_hop_data.sh [-reset_run]\n\ -Usage: rom_hop_data.sh [-noclean_files]\n\n\ + msg="Usage: rom_freq_word.sh [-help]\n\ +Usage: rom_freq_word.sh [-lib_map_path]\n\ +Usage: rom_freq_word.sh [-reset_run]\n\ +Usage: rom_freq_word.sh [-noclean_files]\n\n\ [-help] -- Print help information for this script\n\n\ [-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_dmf_invert_prbs7_deci8/vcs/simulate.do b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/simulate.do similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_dmf_invert_prbs7_deci8/vcs/simulate.do rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/simulate.do diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/README.txt b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/README.txt new file mode 100644 index 00000000..55c357de --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 18:55:24 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./rom_freq_word.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './rom_freq_word.sh' script. + +./rom_freq_word.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./rom_freq_word.sh -noclean_files + +For more information on the script, please type './rom_freq_word.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/file_info.txt b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/file_info.txt new file mode 100644 index 00000000..78704c4b --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/file_info.txt @@ -0,0 +1,6 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +rom_freq_word.v,verilog,xil_defaultlib,../../../ip/rom_freq_word/sim/rom_freq_word.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/freq_word.coe b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/freq_word.coe new file mode 100755 index 00000000..590747a4 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/freq_word.coe @@ -0,0 +1,83 @@ +MEMORY_INITIALIZATION_RADIX = 10; +MEMORY_INITIALIZATION_VECTOR = +1624, +1611, +1598, +1585, +1572, +1559, +1546, +1533, +1520, +1507, +1494, +1481, +1468, +1455, +1442, +1429, +1416, +1403, +1390, +1377, +1364, +1351, +1338, +1325, +1312, +1299, +1286, +1273, +1260, +1247, +1234, +1221, +1208, +1195, +1182, +1169, +1156, +1143, +1130, +1117, +1104, +1091, +1078, +1065, +1052, +1039, +1026, +1013, +1000, +987, +974, +961, +948, +935, +922, +909, +896, +883, +870, +857, +844, +831, +818, +805, +792, +779, +766, +753, +740, +727, +714, +701, +688, +675, +662, +649, +636, +623, +610, +597, +584, diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/ies/glbl.v b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/glbl.v similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/ies/glbl.v rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/glbl.v diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/rom_freq_word.mif b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/rom_freq_word.mif new file mode 100644 index 00000000..355400b4 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/rom_freq_word.mif @@ -0,0 +1,81 @@ +11001011000 +11001001011 +11000111110 +11000110001 +11000100100 +11000010111 +11000001010 +10111111101 +10111110000 +10111100011 +10111010110 +10111001001 +10110111100 +10110101111 +10110100010 +10110010101 +10110001000 +10101111011 +10101101110 +10101100001 +10101010100 +10101000111 +10100111010 +10100101101 +10100100000 +10100010011 +10100000110 +10011111001 +10011101100 +10011011111 +10011010010 +10011000101 +10010111000 +10010101011 +10010011110 +10010010001 +10010000100 +10001110111 +10001101010 +10001011101 +10001010000 +10001000011 +10000110110 +10000101001 +10000011100 +10000001111 +10000000010 +01111110101 +01111101000 +01111011011 +01111001110 +01111000001 +01110110100 +01110100111 +01110011010 +01110001101 +01110000000 +01101110011 +01101100110 +01101011001 +01101001100 +01100111111 +01100110010 +01100100101 +01100011000 +01100001011 +01011111110 +01011110001 +01011100100 +01011010111 +01011001010 +01010111101 +01010110000 +01010100011 +01010010110 +01010001001 +01001111100 +01001101111 +01001100010 +01001010101 +01001001000 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/xcelium/rom_hop_data.sh b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/rom_freq_word.sh similarity index 86% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/xcelium/rom_hop_data.sh rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/rom_freq_word.sh index 96788f24..120a4efd 100755 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/xcelium/rom_hop_data.sh +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/rom_freq_word.sh @@ -2,22 +2,22 @@ #********************************************************************************************************* # Vivado (TM) v2019.1.3 (64-bit) # -# Filename : rom_hop_data.sh +# Filename : rom_freq_word.sh # Simulator : Cadence Xcelium Parallel Simulator # Description : Simulation script for compiling, elaborating and verifying the project source files. # The script will automatically create the design libraries sub-directories in the run # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon Apr 17 13:38:36 CST 2023 +# Generated by Vivado on Mon May 08 18:55:24 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. # -# usage: rom_hop_data.sh [-help] -# usage: rom_hop_data.sh [-lib_map_path] -# usage: rom_hop_data.sh [-noclean_files] -# usage: rom_hop_data.sh [-reset_run] +# usage: rom_freq_word.sh [-help] +# usage: rom_freq_word.sh [-lib_map_path] +# usage: rom_freq_word.sh [-noclean_files] +# usage: rom_freq_word.sh [-reset_run] # # Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the # 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the @@ -27,7 +27,7 @@ # # You can also point to the simulation libraries by either replacing the in this # script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'rom_hop_data.sh -help' for more information. +# executing this script. Please type 'rom_freq_word.sh -help' for more information. # # Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' # @@ -54,7 +54,7 @@ design_libs=(xil_defaultlib xpm blk_mem_gen_v8_4_3) sim_lib_dir="xcelium_lib" # Script info -echo -e "rom_hop_data.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" +echo -e "rom_freq_word.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" # Main steps run() @@ -73,7 +73,7 @@ execute() -reflib "$ref_lib_dir/secureip:secureip" \ -reflib "$ref_lib_dir/unimacro:unimacro" \ -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ - -top xil_defaultlib.rom_hop_data \ + -top xil_defaultlib.rom_freq_word \ -f run.f \ -top glbl \ glbl.v @@ -85,7 +85,7 @@ setup() case $1 in "-lib_map_path" ) if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./rom_hop_data.sh -help\" for more information)\n" + echo -e "ERROR: Simulation library directory path not specified (type \"./rom_freq_word.sh -help\" for more information)\n" exit 1 else ref_lib_dir=$2 @@ -144,7 +144,7 @@ reset_run() check_args() { if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./rom_hop_data.sh -help\" for more information)\n" + echo -e "ERROR: Unknown option specified '$2' (type \"./rom_freq_word.sh -help\" for more information)\n" exit 1 fi @@ -156,10 +156,10 @@ check_args() # Script usage usage() { - msg="Usage: rom_hop_data.sh [-help]\n\ -Usage: rom_hop_data.sh [-lib_map_path]\n\ -Usage: rom_hop_data.sh [-reset_run]\n\ -Usage: rom_hop_data.sh [-noclean_files]\n\n\ + msg="Usage: rom_freq_word.sh [-help]\n\ +Usage: rom_freq_word.sh [-lib_map_path]\n\ +Usage: rom_freq_word.sh [-reset_run]\n\ +Usage: rom_freq_word.sh [-noclean_files]\n\n\ [-help] -- Print help information for this script\n\n\ [-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/xcelium/run.f b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/run.f similarity index 90% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/xcelium/run.f rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/run.f index 885e7f30..7720194b 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/xcelium/run.f +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/run.f @@ -9,7 +9,7 @@ "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ -endlib -makelib xcelium_lib/xil_defaultlib \ - "../../../ip/rom_hop_data/sim/rom_hop_data.v" \ + "../../../ip/rom_freq_word/sim/rom_freq_word.v" \ -endlib -makelib xcelium_lib/xil_defaultlib \ glbl.v diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/README.txt b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/README.txt new file mode 100644 index 00000000..34c03a45 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 18:55:24 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./rom_freq_word.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './rom_freq_word.sh' script. + +./rom_freq_word.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./rom_freq_word.sh -noclean_files + +For more information on the script, please type './rom_freq_word.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_dmf_invert_prbs7_deci8/xsim/cmd.tcl b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/cmd.tcl similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/fir_dmf_invert_prbs7_deci8/xsim/cmd.tcl rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/cmd.tcl diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/file_info.txt b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/file_info.txt new file mode 100644 index 00000000..fe59d479 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/file_info.txt @@ -0,0 +1,2 @@ +rom_freq_word.v,verilog,xil_defaultlib,../../../ip/rom_freq_word/sim/rom_freq_word.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/freq_word.coe b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/freq_word.coe new file mode 100755 index 00000000..590747a4 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/freq_word.coe @@ -0,0 +1,83 @@ +MEMORY_INITIALIZATION_RADIX = 10; +MEMORY_INITIALIZATION_VECTOR = +1624, +1611, +1598, +1585, +1572, +1559, +1546, +1533, +1520, +1507, +1494, +1481, +1468, +1455, +1442, +1429, +1416, +1403, +1390, +1377, +1364, +1351, +1338, +1325, +1312, +1299, +1286, +1273, +1260, +1247, +1234, +1221, +1208, +1195, +1182, +1169, +1156, +1143, +1130, +1117, +1104, +1091, +1078, +1065, +1052, +1039, +1026, +1013, +1000, +987, +974, +961, +948, +935, +922, +909, +896, +883, +870, +857, +844, +831, +818, +805, +792, +779, +766, +753, +740, +727, +714, +701, +688, +675, +662, +649, +636, +623, +610, +597, +584, diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/modelsim/glbl.v b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/glbl.v similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/modelsim/glbl.v rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/glbl.v diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/rom_freq_word.mif b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/rom_freq_word.mif new file mode 100644 index 00000000..355400b4 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/rom_freq_word.mif @@ -0,0 +1,81 @@ +11001011000 +11001001011 +11000111110 +11000110001 +11000100100 +11000010111 +11000001010 +10111111101 +10111110000 +10111100011 +10111010110 +10111001001 +10110111100 +10110101111 +10110100010 +10110010101 +10110001000 +10101111011 +10101101110 +10101100001 +10101010100 +10101000111 +10100111010 +10100101101 +10100100000 +10100010011 +10100000110 +10011111001 +10011101100 +10011011111 +10011010010 +10011000101 +10010111000 +10010101011 +10010011110 +10010010001 +10010000100 +10001110111 +10001101010 +10001011101 +10001010000 +10001000011 +10000110110 +10000101001 +10000011100 +10000001111 +10000000010 +01111110101 +01111101000 +01111011011 +01111001110 +01111000001 +01110110100 +01110100111 +01110011010 +01110001101 +01110000000 +01101110011 +01101100110 +01101011001 +01101001100 +01100111111 +01100110010 +01100100101 +01100011000 +01100001011 +01011111110 +01011110001 +01011100100 +01011010111 +01011001010 +01010111101 +01010110000 +01010100011 +01010010110 +01010001001 +01001111100 +01001101111 +01001100010 +01001010101 +01001001000 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/xsim/rom_hop_data.sh b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/rom_freq_word.sh similarity index 85% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/xsim/rom_hop_data.sh rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/rom_freq_word.sh index 9c23bf1d..2f32272e 100755 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/xsim/rom_hop_data.sh +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/rom_freq_word.sh @@ -2,22 +2,22 @@ #********************************************************************************************************* # Vivado (TM) v2019.1.3 (64-bit) # -# Filename : rom_hop_data.sh +# Filename : rom_freq_word.sh # Simulator : Xilinx Vivado Simulator # Description : Simulation script for compiling, elaborating and verifying the project source files. # The script will automatically create the design libraries sub-directories in the run # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon Apr 17 13:38:36 CST 2023 +# Generated by Vivado on Mon May 08 18:55:24 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. # -# usage: rom_hop_data.sh [-help] -# usage: rom_hop_data.sh [-lib_map_path] -# usage: rom_hop_data.sh [-noclean_files] -# usage: rom_hop_data.sh [-reset_run] +# usage: rom_freq_word.sh [-help] +# usage: rom_freq_word.sh [-lib_map_path] +# usage: rom_freq_word.sh [-noclean_files] +# usage: rom_freq_word.sh [-reset_run] # #********************************************************************************************************* @@ -27,7 +27,7 @@ xvlog_opts="--relax" # Script info -echo -e "rom_hop_data.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" +echo -e "rom_freq_word.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" # Main steps run() @@ -50,13 +50,13 @@ compile() # RUN_STEP: elaborate() { - xelab --relax --debug typical --mt auto -L blk_mem_gen_v8_4_3 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot rom_hop_data xil_defaultlib.rom_hop_data xil_defaultlib.glbl -log elaborate.log + xelab --relax --debug typical --mt auto -L blk_mem_gen_v8_4_3 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot rom_freq_word xil_defaultlib.rom_freq_word xil_defaultlib.glbl -log elaborate.log } # RUN_STEP: simulate() { - xsim rom_hop_data -key {Behavioral:sim_1:Functional:rom_hop_data} -tclbatch cmd.tcl -log simulate.log + xsim rom_freq_word -key {Behavioral:sim_1:Functional:rom_freq_word} -tclbatch cmd.tcl -log simulate.log } # STEP: setup @@ -65,7 +65,7 @@ setup() case $1 in "-lib_map_path" ) if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./rom_hop_data.sh -help\" for more information)\n" + echo -e "ERROR: Simulation library directory path not specified (type \"./rom_freq_word.sh -help\" for more information)\n" exit 1 fi copy_setup_file $2 @@ -168,7 +168,7 @@ map_local_libs() # Delete generated data from the previous run reset_run() { - files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb rom_hop_data.wdb xsim.dir) + files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb rom_freq_word.wdb xsim.dir) for (( i=0; i<${#files_to_remove[*]}; i++ )); do file="${files_to_remove[i]}" if [[ -e $file ]]; then @@ -181,7 +181,7 @@ reset_run() check_args() { if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./rom_hop_data.sh -help\" for more information)\n" + echo -e "ERROR: Unknown option specified '$2' (type \"./rom_freq_word.sh -help\" for more information)\n" exit 1 fi @@ -193,10 +193,10 @@ check_args() # Script usage usage() { - msg="Usage: rom_hop_data.sh [-help]\n\ -Usage: rom_hop_data.sh [-lib_map_path]\n\ -Usage: rom_hop_data.sh [-reset_run]\n\ -Usage: rom_hop_data.sh [-noclean_files]\n\n\ + msg="Usage: rom_freq_word.sh [-help]\n\ +Usage: rom_freq_word.sh [-lib_map_path]\n\ +Usage: rom_freq_word.sh [-reset_run]\n\ +Usage: rom_freq_word.sh [-noclean_files]\n\n\ [-help] -- Print help information for this script\n\n\ [-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/xsim/vlog.prj b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/vlog.prj similarity index 57% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/xsim/vlog.prj rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/vlog.prj index ef49934a..5f7fb546 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/xsim/vlog.prj +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/vlog.prj @@ -1,5 +1,5 @@ verilog xil_defaultlib \ -"../../../ip/rom_hop_data/sim/rom_hop_data.v" \ +"../../../ip/rom_freq_word/sim/rom_freq_word.v" \ verilog xil_defaultlib "glbl.v" diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/README.txt b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/README.txt similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/README.txt rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/README.txt diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/README.txt b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/README.txt new file mode 100644 index 00000000..2fa77f2b --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 17:55:43 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_manual_ctrl.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_manual_ctrl.sh' script. + +./vio_manual_ctrl.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_manual_ctrl.sh -noclean_files + +For more information on the script, please type './vio_manual_ctrl.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/compile.do b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/compile.do new file mode 100644 index 00000000..1f6495c2 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/compile.do @@ -0,0 +1,22 @@ +vlib work +vlib activehdl + +vlib activehdl/xil_defaultlib +vlib activehdl/xpm + +vmap xil_defaultlib activehdl/xil_defaultlib +vmap xpm activehdl/xpm + +vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ip/vio_manual_ctrl/hdl/verilog" "+incdir+../../../ip/vio_manual_ctrl/hdl" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../ip/vio_manual_ctrl/hdl/verilog" "+incdir+../../../ip/vio_manual_ctrl/hdl" \ +"../../../ip/vio_manual_ctrl/sim/vio_manual_ctrl.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/file_info.txt b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/file_info.txt new file mode 100644 index 00000000..f5242d57 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl" +vio_manual_ctrl.v,verilog,xil_defaultlib,../../../ip/vio_manual_ctrl/sim/vio_manual_ctrl.v,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/questa/glbl.v b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/glbl.v similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/questa/glbl.v rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/glbl.v diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/simulate.do b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/simulate.do new file mode 100644 index 00000000..dc4a0b81 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+vio_manual_ctrl -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.vio_manual_ctrl xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {vio_manual_ctrl.udo} + +run -all + +endsim + +quit -force diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/vio_manual_ctrl.sh b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/vio_manual_ctrl.sh new file mode 100755 index 00000000..edb0b36b --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/vio_manual_ctrl.sh @@ -0,0 +1,152 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_manual_ctrl.sh +# Simulator : Aldec Active-HDL Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 17:55:43 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_manual_ctrl.sh [-help] +# usage: vio_manual_ctrl.sh [-lib_map_path] +# usage: vio_manual_ctrl.sh [-noclean_files] +# usage: vio_manual_ctrl.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'vio_manual_ctrl.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "vio_manual_ctrl.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_manual_ctrl.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_manual_ctrl.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_manual_ctrl.sh [-help]\n\ +Usage: vio_manual_ctrl.sh [-lib_map_path]\n\ +Usage: vio_manual_ctrl.sh [-reset_run]\n\ +Usage: vio_manual_ctrl.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/activehdl/rom_hop_data.udo b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/vio_manual_ctrl.udo similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/activehdl/rom_hop_data.udo rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/vio_manual_ctrl.udo diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/modelsim/wave.do b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/wave.do similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/modelsim/wave.do rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/wave.do diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/ies/README.txt b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/ies/README.txt new file mode 100644 index 00000000..348c0719 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/ies/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 17:55:43 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_manual_ctrl.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_manual_ctrl.sh' script. + +./vio_manual_ctrl.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_manual_ctrl.sh -noclean_files + +For more information on the script, please type './vio_manual_ctrl.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/ies/file_info.txt b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/ies/file_info.txt new file mode 100644 index 00000000..f5242d57 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/ies/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl" +vio_manual_ctrl.v,verilog,xil_defaultlib,../../../ip/vio_manual_ctrl/sim/vio_manual_ctrl.v,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/riviera/glbl.v b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/ies/glbl.v similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/riviera/glbl.v rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/ies/glbl.v diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/ies/run.f b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/ies/run.f new file mode 100644 index 00000000..36f5e07d --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/ies/run.f @@ -0,0 +1,14 @@ +-makelib ies_lib/xil_defaultlib -sv \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib ies_lib/xpm \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../ip/vio_manual_ctrl/sim/vio_manual_ctrl.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/ies/vio_manual_ctrl.sh b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/ies/vio_manual_ctrl.sh new file mode 100755 index 00000000..c5f1490f --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/ies/vio_manual_ctrl.sh @@ -0,0 +1,177 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_manual_ctrl.sh +# Simulator : Cadence Incisive Enterprise Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 17:55:43 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_manual_ctrl.sh [-help] +# usage: vio_manual_ctrl.sh [-lib_map_path] +# usage: vio_manual_ctrl.sh [-noclean_files] +# usage: vio_manual_ctrl.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'vio_manual_ctrl.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xil_defaultlib xpm) + +# Simulation root library directory +sim_lib_dir="ies_lib" + +# Script info +echo -e "vio_manual_ctrl.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: +execute() +{ + irun $irun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.vio_manual_ctrl \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"../../../ip/vio_manual_ctrl/hdl/verilog" \ + +incdir+"../../../ip/vio_manual_ctrl/hdl" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_manual_ctrl.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_manual_ctrl.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_manual_ctrl.sh [-help]\n\ +Usage: vio_manual_ctrl.sh [-lib_map_path]\n\ +Usage: vio_manual_ctrl.sh [-reset_run]\n\ +Usage: vio_manual_ctrl.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/README.txt b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/README.txt new file mode 100644 index 00000000..2fa77f2b --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 17:55:43 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_manual_ctrl.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_manual_ctrl.sh' script. + +./vio_manual_ctrl.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_manual_ctrl.sh -noclean_files + +For more information on the script, please type './vio_manual_ctrl.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/compile.do b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/compile.do new file mode 100644 index 00000000..59c2be37 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/compile.do @@ -0,0 +1,14 @@ +vlib modelsim_lib/work +vlib modelsim_lib/msim + +vlib modelsim_lib/msim/xil_defaultlib + +vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib + +vlog -work xil_defaultlib -64 -incr "+incdir+../../../ip/vio_manual_ctrl/hdl/verilog" "+incdir+../../../ip/vio_manual_ctrl/hdl" \ +"../../../ip/vio_manual_ctrl/sim/vio_manual_ctrl.v" \ + + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/file_info.txt b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/file_info.txt new file mode 100644 index 00000000..23d1ee0b --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/file_info.txt @@ -0,0 +1,2 @@ +vio_manual_ctrl.v,verilog,xil_defaultlib,../../../ip/vio_manual_ctrl/sim/vio_manual_ctrl.v,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/vcs/glbl.v b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/glbl.v similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/vcs/glbl.v rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/glbl.v diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/simulate.do b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/simulate.do new file mode 100644 index 00000000..2dedf95d --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -voptargs="+acc" -t 1ps -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm -lib xil_defaultlib xil_defaultlib.vio_manual_ctrl xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure +view signals + +do {vio_manual_ctrl.udo} + +run -all + +quit -force diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/vio_manual_ctrl.sh b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/vio_manual_ctrl.sh new file mode 100755 index 00000000..c5be1668 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/vio_manual_ctrl.sh @@ -0,0 +1,167 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_manual_ctrl.sh +# Simulator : Mentor Graphics ModelSim Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 17:55:43 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_manual_ctrl.sh [-help] +# usage: vio_manual_ctrl.sh [-lib_map_path] +# usage: vio_manual_ctrl.sh [-noclean_files] +# usage: vio_manual_ctrl.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'vio_manual_ctrl.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "vio_manual_ctrl.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_manual_ctrl.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Software/Xilinx/CompLib/Model/2019.1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="modelsim_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_manual_ctrl.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_manual_ctrl.sh [-help]\n\ +Usage: vio_manual_ctrl.sh [-lib_map_path]\n\ +Usage: vio_manual_ctrl.sh [-reset_run]\n\ +Usage: vio_manual_ctrl.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/modelsim/rom_hop_data.udo b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/vio_manual_ctrl.udo similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/modelsim/rom_hop_data.udo rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/vio_manual_ctrl.udo diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/questa/wave.do b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/wave.do similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/questa/wave.do rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/wave.do diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/README.txt b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/README.txt new file mode 100644 index 00000000..2fa77f2b --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 17:55:43 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_manual_ctrl.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_manual_ctrl.sh' script. + +./vio_manual_ctrl.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_manual_ctrl.sh -noclean_files + +For more information on the script, please type './vio_manual_ctrl.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/compile.do b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/compile.do new file mode 100644 index 00000000..a2f2d23e --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/compile.do @@ -0,0 +1,22 @@ +vlib questa_lib/work +vlib questa_lib/msim + +vlib questa_lib/msim/xil_defaultlib +vlib questa_lib/msim/xpm + +vmap xil_defaultlib questa_lib/msim/xil_defaultlib +vmap xpm questa_lib/msim/xpm + +vlog -work xil_defaultlib -64 -sv "+incdir+../../../ip/vio_manual_ctrl/hdl/verilog" "+incdir+../../../ip/vio_manual_ctrl/hdl" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -64 "+incdir+../../../ip/vio_manual_ctrl/hdl/verilog" "+incdir+../../../ip/vio_manual_ctrl/hdl" \ +"../../../ip/vio_manual_ctrl/sim/vio_manual_ctrl.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/elaborate.do b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/elaborate.do new file mode 100644 index 00000000..e5aaa3c5 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/elaborate.do @@ -0,0 +1 @@ +vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.vio_manual_ctrl xil_defaultlib.glbl -o vio_manual_ctrl_opt diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/file_info.txt b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/file_info.txt new file mode 100644 index 00000000..f5242d57 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl" +vio_manual_ctrl.v,verilog,xil_defaultlib,../../../ip/vio_manual_ctrl/sim/vio_manual_ctrl.v,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/xcelium/glbl.v b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/glbl.v similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/xcelium/glbl.v rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/glbl.v diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/simulate.do b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/simulate.do new file mode 100644 index 00000000..f829579e --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -t 1ps -lib xil_defaultlib vio_manual_ctrl_opt + +do {wave.do} + +view wave +view structure +view signals + +do {vio_manual_ctrl.udo} + +run -all + +quit -force diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/vio_manual_ctrl.sh b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/vio_manual_ctrl.sh new file mode 100755 index 00000000..61c3a61f --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/vio_manual_ctrl.sh @@ -0,0 +1,174 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_manual_ctrl.sh +# Simulator : Mentor Graphics Questa Advanced Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 17:55:43 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_manual_ctrl.sh [-help] +# usage: vio_manual_ctrl.sh [-lib_map_path] +# usage: vio_manual_ctrl.sh [-noclean_files] +# usage: vio_manual_ctrl.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'vio_manual_ctrl.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "vio_manual_ctrl.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +elaborate() +{ + source elaborate.do 2>&1 | tee -a elaborate.log +} + +# RUN_STEP: +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_manual_ctrl.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/questa" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="questa_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_manual_ctrl.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_manual_ctrl.sh [-help]\n\ +Usage: vio_manual_ctrl.sh [-lib_map_path]\n\ +Usage: vio_manual_ctrl.sh [-reset_run]\n\ +Usage: vio_manual_ctrl.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/questa/rom_hop_data.udo b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/vio_manual_ctrl.udo similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/questa/rom_hop_data.udo rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/vio_manual_ctrl.udo diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/riviera/wave.do b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/wave.do similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/riviera/wave.do rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/wave.do diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/README.txt b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/README.txt new file mode 100644 index 00000000..2fa77f2b --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 17:55:43 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_manual_ctrl.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_manual_ctrl.sh' script. + +./vio_manual_ctrl.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_manual_ctrl.sh -noclean_files + +For more information on the script, please type './vio_manual_ctrl.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/compile.do b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/compile.do new file mode 100644 index 00000000..8710eef1 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/compile.do @@ -0,0 +1,22 @@ +vlib work +vlib riviera + +vlib riviera/xil_defaultlib +vlib riviera/xpm + +vmap xil_defaultlib riviera/xil_defaultlib +vmap xpm riviera/xpm + +vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ip/vio_manual_ctrl/hdl/verilog" "+incdir+../../../ip/vio_manual_ctrl/hdl" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../ip/vio_manual_ctrl/hdl/verilog" "+incdir+../../../ip/vio_manual_ctrl/hdl" \ +"../../../ip/vio_manual_ctrl/sim/vio_manual_ctrl.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/file_info.txt b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/file_info.txt new file mode 100644 index 00000000..f5242d57 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl" +vio_manual_ctrl.v,verilog,xil_defaultlib,../../../ip/vio_manual_ctrl/sim/vio_manual_ctrl.v,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/xsim/glbl.v b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/glbl.v similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/xsim/glbl.v rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/glbl.v diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/simulate.do b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/simulate.do new file mode 100644 index 00000000..dc4a0b81 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+vio_manual_ctrl -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.vio_manual_ctrl xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {vio_manual_ctrl.udo} + +run -all + +endsim + +quit -force diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/vio_manual_ctrl.sh b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/vio_manual_ctrl.sh new file mode 100755 index 00000000..9f2c82be --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/vio_manual_ctrl.sh @@ -0,0 +1,153 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_manual_ctrl.sh +# Simulator : Aldec Riviera-PRO Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 17:55:43 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_manual_ctrl.sh [-help] +# usage: vio_manual_ctrl.sh [-lib_map_path] +# usage: vio_manual_ctrl.sh [-noclean_files] +# usage: vio_manual_ctrl.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'vio_manual_ctrl.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "vio_manual_ctrl.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_manual_ctrl.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/riviera" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_manual_ctrl.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_manual_ctrl.sh [-help]\n\ +Usage: vio_manual_ctrl.sh [-lib_map_path]\n\ +Usage: vio_manual_ctrl.sh [-reset_run]\n\ +Usage: vio_manual_ctrl.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/riviera/rom_hop_data.udo b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/vio_manual_ctrl.udo similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/riviera/rom_hop_data.udo rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/vio_manual_ctrl.udo diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_cal/activehdl/wave.do b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/wave.do similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_cal/activehdl/wave.do rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/wave.do diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/vcs/README.txt b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/vcs/README.txt new file mode 100644 index 00000000..2fa77f2b --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/vcs/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 17:55:43 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_manual_ctrl.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_manual_ctrl.sh' script. + +./vio_manual_ctrl.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_manual_ctrl.sh -noclean_files + +For more information on the script, please type './vio_manual_ctrl.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/vcs/file_info.txt b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/vcs/file_info.txt new file mode 100644 index 00000000..23d1ee0b --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/vcs/file_info.txt @@ -0,0 +1,2 @@ +vio_manual_ctrl.v,verilog,xil_defaultlib,../../../ip/vio_manual_ctrl/sim/vio_manual_ctrl.v,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_cal/activehdl/glbl.v b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/vcs/glbl.v similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_cal/activehdl/glbl.v rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/vcs/glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/vcs/simulate.do b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/vcs/simulate.do similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/vcs/simulate.do rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/vcs/simulate.do diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/vcs/vio_manual_ctrl.sh b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/vcs/vio_manual_ctrl.sh new file mode 100755 index 00000000..bf5e5f8f --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/vcs/vio_manual_ctrl.sh @@ -0,0 +1,221 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_manual_ctrl.sh +# Simulator : Synopsys Verilog Compiler Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 17:55:43 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_manual_ctrl.sh [-help] +# usage: vio_manual_ctrl.sh [-lib_map_path] +# usage: vio_manual_ctrl.sh [-noclean_files] +# usage: vio_manual_ctrl.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'vio_manual_ctrl.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Command line options +vlogan_opts="-full64" +vhdlan_opts="-full64" +vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log" +vcs_sim_opts="-ucli -licqueue -l simulate.log" + +# Design libraries +design_libs=(xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="vcs_lib" + +# Script info +echo -e "vio_manual_ctrl.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../ip/vio_manual_ctrl/hdl/verilog" +incdir+"$ref_dir/../../../ip/vio_manual_ctrl/hdl" \ + "$ref_dir/../../../ip/vio_manual_ctrl/sim/vio_manual_ctrl.v" \ + 2>&1 | tee -a vlogan.log + + + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + glbl.v \ + 2>&1 | tee -a vlogan.log + +} + +# RUN_STEP: +elaborate() +{ + vcs $vcs_elab_opts xil_defaultlib.vio_manual_ctrl xil_defaultlib.glbl -o vio_manual_ctrl_simv +} + +# RUN_STEP: +simulate() +{ + ./vio_manual_ctrl_simv $vcs_sim_opts -do simulate.do +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_manual_ctrl.sh -help\" for more information)\n" + exit 1 + fi + create_lib_mappings $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + create_lib_mappings $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Define design library mappings +create_lib_mappings() +{ + file="synopsys_sim.setup" + if [[ -e $file ]]; then + if [[ ($1 == "") ]]; then + return + else + rm -rf $file + fi + fi + + touch $file + + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Software/Xilinx/CompLib/VCS/2019.1" + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + mapping="$lib:$sim_lib_dir/$lib" + echo $mapping >> $file + done + + if [[ ($lib_map_path != "") ]]; then + incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup" + echo $incl_ref >> $file + fi +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ucli.key vio_manual_ctrl_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc vio_manual_ctrl_simv.daidir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_manual_ctrl.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_manual_ctrl.sh [-help]\n\ +Usage: vio_manual_ctrl.sh [-lib_map_path]\n\ +Usage: vio_manual_ctrl.sh [-reset_run]\n\ +Usage: vio_manual_ctrl.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xcelium/README.txt b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xcelium/README.txt new file mode 100644 index 00000000..348c0719 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xcelium/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 17:55:43 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_manual_ctrl.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_manual_ctrl.sh' script. + +./vio_manual_ctrl.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_manual_ctrl.sh -noclean_files + +For more information on the script, please type './vio_manual_ctrl.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xcelium/file_info.txt b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xcelium/file_info.txt new file mode 100644 index 00000000..f5242d57 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xcelium/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl" +vio_manual_ctrl.v,verilog,xil_defaultlib,../../../ip/vio_manual_ctrl/sim/vio_manual_ctrl.v,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_cal/ies/glbl.v b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xcelium/glbl.v similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_cal/ies/glbl.v rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xcelium/glbl.v diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xcelium/run.f b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xcelium/run.f new file mode 100644 index 00000000..f65ce74a --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xcelium/run.f @@ -0,0 +1,14 @@ +-makelib xcelium_lib/xil_defaultlib -sv \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib xcelium_lib/xpm \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../ip/vio_manual_ctrl/sim/vio_manual_ctrl.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xcelium/vio_manual_ctrl.sh b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xcelium/vio_manual_ctrl.sh new file mode 100755 index 00000000..9d1b0838 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xcelium/vio_manual_ctrl.sh @@ -0,0 +1,177 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_manual_ctrl.sh +# Simulator : Cadence Xcelium Parallel Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 17:55:43 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_manual_ctrl.sh [-help] +# usage: vio_manual_ctrl.sh [-lib_map_path] +# usage: vio_manual_ctrl.sh [-noclean_files] +# usage: vio_manual_ctrl.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'vio_manual_ctrl.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xil_defaultlib xpm) + +# Simulation root library directory +sim_lib_dir="xcelium_lib" + +# Script info +echo -e "vio_manual_ctrl.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: +execute() +{ + xrun $xrun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.vio_manual_ctrl \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"../../../ip/vio_manual_ctrl/hdl/verilog" \ + +incdir+"../../../ip/vio_manual_ctrl/hdl" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_manual_ctrl.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_manual_ctrl.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_manual_ctrl.sh [-help]\n\ +Usage: vio_manual_ctrl.sh [-lib_map_path]\n\ +Usage: vio_manual_ctrl.sh [-reset_run]\n\ +Usage: vio_manual_ctrl.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xsim/README.txt b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xsim/README.txt new file mode 100644 index 00000000..2fa77f2b --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 17:55:43 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_manual_ctrl.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_manual_ctrl.sh' script. + +./vio_manual_ctrl.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_manual_ctrl.sh -noclean_files + +For more information on the script, please type './vio_manual_ctrl.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/xsim/cmd.tcl b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xsim/cmd.tcl similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/rom_hop_data/xsim/cmd.tcl rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xsim/cmd.tcl diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xsim/file_info.txt b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xsim/file_info.txt new file mode 100644 index 00000000..23d1ee0b --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xsim/file_info.txt @@ -0,0 +1,2 @@ +vio_manual_ctrl.v,verilog,xil_defaultlib,../../../ip/vio_manual_ctrl/sim/vio_manual_ctrl.v,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_cal/modelsim/glbl.v b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xsim/glbl.v similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_cal/modelsim/glbl.v rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xsim/glbl.v diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xsim/vio_manual_ctrl.sh b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xsim/vio_manual_ctrl.sh new file mode 100755 index 00000000..e9df6963 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xsim/vio_manual_ctrl.sh @@ -0,0 +1,212 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_manual_ctrl.sh +# Simulator : Xilinx Vivado Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 17:55:43 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_manual_ctrl.sh [-help] +# usage: vio_manual_ctrl.sh [-lib_map_path] +# usage: vio_manual_ctrl.sh [-noclean_files] +# usage: vio_manual_ctrl.sh [-reset_run] +# +#********************************************************************************************************* + +# Command line options +xv_boost_lib_path=/tools/Xilinx/Vivado/2019.1/tps/boost_1_64_0 +xvlog_opts="--relax" + + +# Script info +echo -e "vio_manual_ctrl.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log + +} + +# RUN_STEP: +elaborate() +{ + xelab --relax --debug typical --mt auto -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot vio_manual_ctrl xil_defaultlib.vio_manual_ctrl xil_defaultlib.glbl -log elaborate.log +} + +# RUN_STEP: +simulate() +{ + xsim vio_manual_ctrl -key {Behavioral:sim_1:Functional:vio_manual_ctrl} -tclbatch cmd.tcl -log simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_manual_ctrl.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Copy xsim.ini file +copy_setup_file() +{ + file="xsim.ini" + lib_map_path="/tools/Xilinx/Vivado/2019.1/data/xsim" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + cp $src_file . + fi + + # Map local design libraries to xsim.ini + map_local_libs + + fi +} + +# Map local design libraries +map_local_libs() +{ + updated_mappings=() + local_mappings=() + + # Local design libraries + local_libs=() + + if [[ 0 == ${#local_libs[@]} ]]; then + return + fi + + file="xsim.ini" + file_backup="xsim.ini.bak" + + if [[ -e $file ]]; then + rm -f $file_backup + # Create a backup copy of the xsim.ini file + cp $file $file_backup + # Read libraries from backup file and search in local library collection + while read -r line + do + IN=$line + # Split mapping entry with '=' delimiter to fetch library name and mapping + read lib_name mapping <<<$(IFS="="; echo $IN) + # If local library found, then construct the local mapping and add to local mapping collection + if `echo ${local_libs[@]} | grep -wq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + local_mappings+=("$lib_name") + fi + # Add to updated library mapping collection + updated_mappings+=("$line") + done < "$file_backup" + # Append local libraries not found originally from xsim.ini + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + updated_mappings+=("$line") + fi + done + # Write updated mappings in xsim.ini + rm -f $file + for (( i=0; i<${#updated_mappings[*]}; i++ )); do + lib_name="${updated_mappings[i]}" + echo $lib_name >> $file + done + else + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + mapping="$lib_name=xsim.dir/$lib_name" + echo $mapping >> $file + done + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb vio_manual_ctrl.wdb xsim.dir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_manual_ctrl.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_manual_ctrl.sh [-help]\n\ +Usage: vio_manual_ctrl.sh [-lib_map_path]\n\ +Usage: vio_manual_ctrl.sh [-reset_run]\n\ +Usage: vio_manual_ctrl.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xsim/vlog.prj b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xsim/vlog.prj new file mode 100644 index 00000000..5036d554 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xsim/vlog.prj @@ -0,0 +1,6 @@ +verilog xil_defaultlib --include "../../../ip/vio_manual_ctrl/hdl/verilog" --include "../../../ip/vio_manual_ctrl/hdl" \ +"../../../ip/vio_manual_ctrl/sim/vio_manual_ctrl.v" \ + +verilog xil_defaultlib "glbl.v" + +nosort diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_cal/README.txt b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/README.txt similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_cal/README.txt rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/README.txt diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/activehdl/README.txt b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/activehdl/README.txt new file mode 100644 index 00000000..fdb6b834 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/activehdl/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 17:52:16 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_rf_control.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_rf_control.sh' script. + +./vio_rf_control.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_rf_control.sh -noclean_files + +For more information on the script, please type './vio_rf_control.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/activehdl/compile.do b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/activehdl/compile.do new file mode 100644 index 00000000..192201b2 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/activehdl/compile.do @@ -0,0 +1,22 @@ +vlib work +vlib activehdl + +vlib activehdl/xil_defaultlib +vlib activehdl/xpm + +vmap xil_defaultlib activehdl/xil_defaultlib +vmap xpm activehdl/xpm + +vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ip/vio_rf_control/hdl/verilog" "+incdir+../../../ip/vio_rf_control/hdl" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../ip/vio_rf_control/hdl/verilog" "+incdir+../../../ip/vio_rf_control/hdl" \ +"../../../ip/vio_rf_control/sim/vio_rf_control.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/activehdl/file_info.txt b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/activehdl/file_info.txt new file mode 100644 index 00000000..5d1c0b80 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/activehdl/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" +vio_rf_control.v,verilog,xil_defaultlib,../../../ip/vio_rf_control/sim/vio_rf_control.v,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_cal/questa/glbl.v b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/activehdl/glbl.v similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_cal/questa/glbl.v rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/activehdl/glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_null_phase/activehdl/simulate.do b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/activehdl/simulate.do similarity index 59% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_null_phase/activehdl/simulate.do rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/activehdl/simulate.do index 950577fd..ffcd11d6 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_null_phase/activehdl/simulate.do +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/activehdl/simulate.do @@ -1,14 +1,14 @@ onbreak {quit -force} onerror {quit -force} -asim -t 1ps +access +r +m+vio_null_phase -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.vio_null_phase xil_defaultlib.glbl +asim -t 1ps +access +r +m+vio_rf_control -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.vio_rf_control xil_defaultlib.glbl do {wave.do} view wave view structure -do {vio_null_phase.udo} +do {vio_rf_control.udo} run -all diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_null_phase/activehdl/vio_null_phase.sh b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/activehdl/vio_rf_control.sh similarity index 85% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_null_phase/activehdl/vio_null_phase.sh rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/activehdl/vio_rf_control.sh index 64d13667..f43bac98 100755 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_null_phase/activehdl/vio_null_phase.sh +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/activehdl/vio_rf_control.sh @@ -2,22 +2,22 @@ #********************************************************************************************************* # Vivado (TM) v2019.1.3 (64-bit) # -# Filename : vio_null_phase.sh +# Filename : vio_rf_control.sh # Simulator : Aldec Active-HDL Simulator # Description : Simulation script for compiling, elaborating and verifying the project source files. # The script will automatically create the design libraries sub-directories in the run # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Tue Apr 25 17:40:58 CST 2023 +# Generated by Vivado on Mon May 08 17:52:16 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. # -# usage: vio_null_phase.sh [-help] -# usage: vio_null_phase.sh [-lib_map_path] -# usage: vio_null_phase.sh [-noclean_files] -# usage: vio_null_phase.sh [-reset_run] +# usage: vio_rf_control.sh [-help] +# usage: vio_rf_control.sh [-lib_map_path] +# usage: vio_rf_control.sh [-noclean_files] +# usage: vio_rf_control.sh [-reset_run] # # Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the # 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the @@ -27,7 +27,7 @@ # # You can also point to the simulation libraries by either replacing the in this # script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'vio_null_phase.sh -help' for more information. +# executing this script. Please type 'vio_rf_control.sh -help' for more information. # # Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' # @@ -35,7 +35,7 @@ # Script info -echo -e "vio_null_phase.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" +echo -e "vio_rf_control.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" # Main steps run() @@ -66,7 +66,7 @@ setup() case $1 in "-lib_map_path" ) if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./vio_null_phase.sh -help\" for more information)\n" + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_rf_control.sh -help\" for more information)\n" exit 1 fi map_setup_file $2 @@ -121,7 +121,7 @@ reset_run() check_args() { if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./vio_null_phase.sh -help\" for more information)\n" + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_rf_control.sh -help\" for more information)\n" exit 1 fi @@ -133,10 +133,10 @@ check_args() # Script usage usage() { - msg="Usage: vio_null_phase.sh [-help]\n\ -Usage: vio_null_phase.sh [-lib_map_path]\n\ -Usage: vio_null_phase.sh [-reset_run]\n\ -Usage: vio_null_phase.sh [-noclean_files]\n\n\ + msg="Usage: vio_rf_control.sh [-help]\n\ +Usage: vio_rf_control.sh [-lib_map_path]\n\ +Usage: vio_rf_control.sh [-reset_run]\n\ +Usage: vio_rf_control.sh [-noclean_files]\n\n\ [-help] -- Print help information for this script\n\n\ [-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_cal/activehdl/vio_cal.udo b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/activehdl/vio_rf_control.udo similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_cal/activehdl/vio_cal.udo rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/activehdl/vio_rf_control.udo diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_cal/modelsim/wave.do b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/activehdl/wave.do similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_cal/modelsim/wave.do rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/activehdl/wave.do diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/ies/README.txt b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/ies/README.txt new file mode 100644 index 00000000..935aafbf --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/ies/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 17:52:16 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_rf_control.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_rf_control.sh' script. + +./vio_rf_control.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_rf_control.sh -noclean_files + +For more information on the script, please type './vio_rf_control.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/ies/file_info.txt b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/ies/file_info.txt new file mode 100644 index 00000000..5d1c0b80 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/ies/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" +vio_rf_control.v,verilog,xil_defaultlib,../../../ip/vio_rf_control/sim/vio_rf_control.v,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_cal/riviera/glbl.v b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/ies/glbl.v similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_cal/riviera/glbl.v rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/ies/glbl.v diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/ies/run.f b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/ies/run.f new file mode 100644 index 00000000..e4edaabe --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/ies/run.f @@ -0,0 +1,14 @@ +-makelib ies_lib/xil_defaultlib -sv \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib ies_lib/xpm \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../ip/vio_rf_control/sim/vio_rf_control.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_null_phase/ies/vio_null_phase.sh b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/ies/vio_rf_control.sh similarity index 85% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_null_phase/ies/vio_null_phase.sh rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/ies/vio_rf_control.sh index fe7547df..5d2aca67 100755 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_null_phase/ies/vio_null_phase.sh +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/ies/vio_rf_control.sh @@ -2,22 +2,22 @@ #********************************************************************************************************* # Vivado (TM) v2019.1.3 (64-bit) # -# Filename : vio_null_phase.sh +# Filename : vio_rf_control.sh # Simulator : Cadence Incisive Enterprise Simulator # Description : Simulation script for compiling, elaborating and verifying the project source files. # The script will automatically create the design libraries sub-directories in the run # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Tue Apr 25 17:40:58 CST 2023 +# Generated by Vivado on Mon May 08 17:52:16 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. # -# usage: vio_null_phase.sh [-help] -# usage: vio_null_phase.sh [-lib_map_path] -# usage: vio_null_phase.sh [-noclean_files] -# usage: vio_null_phase.sh [-reset_run] +# usage: vio_rf_control.sh [-help] +# usage: vio_rf_control.sh [-lib_map_path] +# usage: vio_rf_control.sh [-noclean_files] +# usage: vio_rf_control.sh [-reset_run] # # Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the # 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the @@ -27,7 +27,7 @@ # # You can also point to the simulation libraries by either replacing the in this # script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'vio_null_phase.sh -help' for more information. +# executing this script. Please type 'vio_rf_control.sh -help' for more information. # # Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' # @@ -54,7 +54,7 @@ design_libs=(xil_defaultlib xpm) sim_lib_dir="ies_lib" # Script info -echo -e "vio_null_phase.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" +echo -e "vio_rf_control.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" # Main steps run() @@ -73,12 +73,12 @@ execute() -reflib "$ref_lib_dir/secureip:secureip" \ -reflib "$ref_lib_dir/unimacro:unimacro" \ -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ - -top xil_defaultlib.vio_null_phase \ + -top xil_defaultlib.vio_rf_control \ -f run.f \ -top glbl \ glbl.v \ - +incdir+"../../../ip/vio_null_phase/hdl/verilog" \ - +incdir+"../../../ip/vio_null_phase/hdl" + +incdir+"../../../ip/vio_rf_control/hdl/verilog" \ + +incdir+"../../../ip/vio_rf_control/hdl" } # STEP: setup @@ -87,7 +87,7 @@ setup() case $1 in "-lib_map_path" ) if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./vio_null_phase.sh -help\" for more information)\n" + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_rf_control.sh -help\" for more information)\n" exit 1 else ref_lib_dir=$2 @@ -146,7 +146,7 @@ reset_run() check_args() { if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./vio_null_phase.sh -help\" for more information)\n" + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_rf_control.sh -help\" for more information)\n" exit 1 fi @@ -158,10 +158,10 @@ check_args() # Script usage usage() { - msg="Usage: vio_null_phase.sh [-help]\n\ -Usage: vio_null_phase.sh [-lib_map_path]\n\ -Usage: vio_null_phase.sh [-reset_run]\n\ -Usage: vio_null_phase.sh [-noclean_files]\n\n\ + msg="Usage: vio_rf_control.sh [-help]\n\ +Usage: vio_rf_control.sh [-lib_map_path]\n\ +Usage: vio_rf_control.sh [-reset_run]\n\ +Usage: vio_rf_control.sh [-noclean_files]\n\n\ [-help] -- Print help information for this script\n\n\ [-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/modelsim/README.txt b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/modelsim/README.txt new file mode 100644 index 00000000..fdb6b834 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/modelsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 17:52:16 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_rf_control.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_rf_control.sh' script. + +./vio_rf_control.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_rf_control.sh -noclean_files + +For more information on the script, please type './vio_rf_control.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/modelsim/compile.do b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/modelsim/compile.do new file mode 100644 index 00000000..c4d49900 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/modelsim/compile.do @@ -0,0 +1,22 @@ +vlib modelsim_lib/work +vlib modelsim_lib/msim + +vlib modelsim_lib/msim/xil_defaultlib +vlib modelsim_lib/msim/xpm + +vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib +vmap xpm modelsim_lib/msim/xpm + +vlog -work xil_defaultlib -64 -incr -sv "+incdir+../../../ip/vio_rf_control/hdl/verilog" "+incdir+../../../ip/vio_rf_control/hdl" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -64 -incr "+incdir+../../../ip/vio_rf_control/hdl/verilog" "+incdir+../../../ip/vio_rf_control/hdl" \ +"../../../ip/vio_rf_control/sim/vio_rf_control.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/modelsim/file_info.txt b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/modelsim/file_info.txt new file mode 100644 index 00000000..5d1c0b80 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/modelsim/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" +vio_rf_control.v,verilog,xil_defaultlib,../../../ip/vio_rf_control/sim/vio_rf_control.v,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_cal/vcs/glbl.v b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/modelsim/glbl.v similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_cal/vcs/glbl.v rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/modelsim/glbl.v diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/modelsim/simulate.do b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/modelsim/simulate.do new file mode 100644 index 00000000..29fc4b9a --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/modelsim/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -voptargs="+acc" -t 1ps -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.vio_rf_control xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure +view signals + +do {vio_rf_control.udo} + +run -all + +quit -force diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/modelsim/vio_rf_control.sh b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/modelsim/vio_rf_control.sh new file mode 100755 index 00000000..eaafd465 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/modelsim/vio_rf_control.sh @@ -0,0 +1,168 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_rf_control.sh +# Simulator : Mentor Graphics ModelSim Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 17:52:16 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_rf_control.sh [-help] +# usage: vio_rf_control.sh [-lib_map_path] +# usage: vio_rf_control.sh [-noclean_files] +# usage: vio_rf_control.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'vio_rf_control.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "vio_rf_control.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_rf_control.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + lib_map_path="" + if [[ ($1 != "" && -e $1) ]]; then + lib_map_path="$1" + else + echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="modelsim_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_rf_control.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_rf_control.sh [-help]\n\ +Usage: vio_rf_control.sh [-lib_map_path]\n\ +Usage: vio_rf_control.sh [-reset_run]\n\ +Usage: vio_rf_control.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_cal/modelsim/vio_cal.udo b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/modelsim/vio_rf_control.udo similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_cal/modelsim/vio_cal.udo rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/modelsim/vio_rf_control.udo diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_cal/questa/wave.do b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/modelsim/wave.do similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_cal/questa/wave.do rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/modelsim/wave.do diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/README.txt b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/README.txt new file mode 100644 index 00000000..fdb6b834 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 17:52:16 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_rf_control.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_rf_control.sh' script. + +./vio_rf_control.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_rf_control.sh -noclean_files + +For more information on the script, please type './vio_rf_control.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/compile.do b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/compile.do new file mode 100644 index 00000000..d50d8c8e --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/compile.do @@ -0,0 +1,22 @@ +vlib questa_lib/work +vlib questa_lib/msim + +vlib questa_lib/msim/xil_defaultlib +vlib questa_lib/msim/xpm + +vmap xil_defaultlib questa_lib/msim/xil_defaultlib +vmap xpm questa_lib/msim/xpm + +vlog -work xil_defaultlib -64 -sv "+incdir+../../../ip/vio_rf_control/hdl/verilog" "+incdir+../../../ip/vio_rf_control/hdl" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -64 "+incdir+../../../ip/vio_rf_control/hdl/verilog" "+incdir+../../../ip/vio_rf_control/hdl" \ +"../../../ip/vio_rf_control/sim/vio_rf_control.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_null_phase/questa/elaborate.do b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/elaborate.do similarity index 66% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_null_phase/questa/elaborate.do rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/elaborate.do index 574ba355..904131c9 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_null_phase/questa/elaborate.do +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/elaborate.do @@ -1 +1 @@ -vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.vio_null_phase xil_defaultlib.glbl -o vio_null_phase_opt +vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.vio_rf_control xil_defaultlib.glbl -o vio_rf_control_opt diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/file_info.txt b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/file_info.txt new file mode 100644 index 00000000..5d1c0b80 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" +vio_rf_control.v,verilog,xil_defaultlib,../../../ip/vio_rf_control/sim/vio_rf_control.v,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_cal/xcelium/glbl.v b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/glbl.v similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_cal/xcelium/glbl.v rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/glbl.v diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/simulate.do b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/simulate.do new file mode 100644 index 00000000..5aa3f82e --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -t 1ps -lib xil_defaultlib vio_rf_control_opt + +do {wave.do} + +view wave +view structure +view signals + +do {vio_rf_control.udo} + +run -all + +quit -force diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/vio_rf_control.sh b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/vio_rf_control.sh new file mode 100755 index 00000000..82d661ed --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/vio_rf_control.sh @@ -0,0 +1,173 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_rf_control.sh +# Simulator : Mentor Graphics Questa Advanced Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 17:52:16 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_rf_control.sh [-help] +# usage: vio_rf_control.sh [-lib_map_path] +# usage: vio_rf_control.sh [-noclean_files] +# usage: vio_rf_control.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'vio_rf_control.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "vio_rf_control.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +elaborate() +{ + source elaborate.do 2>&1 | tee -a elaborate.log +} + +# RUN_STEP: +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_rf_control.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="questa_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_rf_control.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_rf_control.sh [-help]\n\ +Usage: vio_rf_control.sh [-lib_map_path]\n\ +Usage: vio_rf_control.sh [-reset_run]\n\ +Usage: vio_rf_control.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_cal/questa/vio_cal.udo b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/vio_rf_control.udo similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_cal/questa/vio_cal.udo rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/vio_rf_control.udo diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_cal/riviera/wave.do b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/wave.do similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_cal/riviera/wave.do rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/wave.do diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/riviera/README.txt b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/riviera/README.txt new file mode 100644 index 00000000..fdb6b834 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/riviera/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 17:52:16 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_rf_control.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_rf_control.sh' script. + +./vio_rf_control.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_rf_control.sh -noclean_files + +For more information on the script, please type './vio_rf_control.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/riviera/compile.do b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/riviera/compile.do new file mode 100644 index 00000000..72ffdcee --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/riviera/compile.do @@ -0,0 +1,22 @@ +vlib work +vlib riviera + +vlib riviera/xil_defaultlib +vlib riviera/xpm + +vmap xil_defaultlib riviera/xil_defaultlib +vmap xpm riviera/xpm + +vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ip/vio_rf_control/hdl/verilog" "+incdir+../../../ip/vio_rf_control/hdl" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../ip/vio_rf_control/hdl/verilog" "+incdir+../../../ip/vio_rf_control/hdl" \ +"../../../ip/vio_rf_control/sim/vio_rf_control.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/riviera/file_info.txt b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/riviera/file_info.txt new file mode 100644 index 00000000..5d1c0b80 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/riviera/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" +vio_rf_control.v,verilog,xil_defaultlib,../../../ip/vio_rf_control/sim/vio_rf_control.v,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_cal/xsim/glbl.v b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/riviera/glbl.v similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_cal/xsim/glbl.v rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/riviera/glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_null_phase/riviera/simulate.do b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/riviera/simulate.do similarity index 59% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_null_phase/riviera/simulate.do rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/riviera/simulate.do index 950577fd..ffcd11d6 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_null_phase/riviera/simulate.do +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/riviera/simulate.do @@ -1,14 +1,14 @@ onbreak {quit -force} onerror {quit -force} -asim -t 1ps +access +r +m+vio_null_phase -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.vio_null_phase xil_defaultlib.glbl +asim -t 1ps +access +r +m+vio_rf_control -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.vio_rf_control xil_defaultlib.glbl do {wave.do} view wave view structure -do {vio_null_phase.udo} +do {vio_rf_control.udo} run -all diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/riviera/vio_rf_control.sh b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/riviera/vio_rf_control.sh new file mode 100755 index 00000000..12263f9e --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/riviera/vio_rf_control.sh @@ -0,0 +1,152 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_rf_control.sh +# Simulator : Aldec Riviera-PRO Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 17:52:16 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_rf_control.sh [-help] +# usage: vio_rf_control.sh [-lib_map_path] +# usage: vio_rf_control.sh [-noclean_files] +# usage: vio_rf_control.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'vio_rf_control.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "vio_rf_control.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_rf_control.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_rf_control.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_rf_control.sh [-help]\n\ +Usage: vio_rf_control.sh [-lib_map_path]\n\ +Usage: vio_rf_control.sh [-reset_run]\n\ +Usage: vio_rf_control.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_cal/riviera/vio_cal.udo b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/riviera/vio_rf_control.udo similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_cal/riviera/vio_cal.udo rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/riviera/vio_rf_control.udo diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_hop/activehdl/wave.do b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/riviera/wave.do similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_hop/activehdl/wave.do rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/riviera/wave.do diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/vcs/README.txt b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/vcs/README.txt new file mode 100644 index 00000000..fdb6b834 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/vcs/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 17:52:16 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_rf_control.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_rf_control.sh' script. + +./vio_rf_control.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_rf_control.sh -noclean_files + +For more information on the script, please type './vio_rf_control.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/vcs/file_info.txt b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/vcs/file_info.txt new file mode 100644 index 00000000..5d1c0b80 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/vcs/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" +vio_rf_control.v,verilog,xil_defaultlib,../../../ip/vio_rf_control/sim/vio_rf_control.v,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_hop/activehdl/glbl.v b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/vcs/glbl.v similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_hop/activehdl/glbl.v rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/vcs/glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_cal/vcs/simulate.do b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/vcs/simulate.do similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_cal/vcs/simulate.do rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/vcs/simulate.do diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/vcs/vio_rf_control.sh b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/vcs/vio_rf_control.sh new file mode 100755 index 00000000..ef64e67c --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/vcs/vio_rf_control.sh @@ -0,0 +1,229 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_rf_control.sh +# Simulator : Synopsys Verilog Compiler Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 17:52:16 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_rf_control.sh [-help] +# usage: vio_rf_control.sh [-lib_map_path] +# usage: vio_rf_control.sh [-noclean_files] +# usage: vio_rf_control.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'vio_rf_control.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Command line options +vlogan_opts="-full64" +vhdlan_opts="-full64" +vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log" +vcs_sim_opts="-ucli -licqueue -l simulate.log" + +# Design libraries +design_libs=(xil_defaultlib xpm) + +# Simulation root library directory +sim_lib_dir="vcs_lib" + +# Script info +echo -e "vio_rf_control.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + vlogan -work xil_defaultlib $vlogan_opts -sverilog +incdir+"$ref_dir/../../../ip/vio_rf_control/hdl/verilog" +incdir+"$ref_dir/../../../ip/vio_rf_control/hdl" \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + 2>&1 | tee -a vlogan.log + + vhdlan -work xpm $vhdlan_opts \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + 2>&1 | tee -a vhdlan.log + + vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../ip/vio_rf_control/hdl/verilog" +incdir+"$ref_dir/../../../ip/vio_rf_control/hdl" \ + "$ref_dir/../../../ip/vio_rf_control/sim/vio_rf_control.v" \ + 2>&1 | tee -a vlogan.log + + + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + glbl.v \ + 2>&1 | tee -a vlogan.log + +} + +# RUN_STEP: +elaborate() +{ + vcs $vcs_elab_opts xil_defaultlib.vio_rf_control xil_defaultlib.glbl -o vio_rf_control_simv +} + +# RUN_STEP: +simulate() +{ + ./vio_rf_control_simv $vcs_sim_opts -do simulate.do +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_rf_control.sh -help\" for more information)\n" + exit 1 + fi + create_lib_mappings $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + create_lib_mappings $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Define design library mappings +create_lib_mappings() +{ + file="synopsys_sim.setup" + if [[ -e $file ]]; then + if [[ ($1 == "") ]]; then + return + else + rm -rf $file + fi + fi + + touch $file + + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + mapping="$lib:$sim_lib_dir/$lib" + echo $mapping >> $file + done + + if [[ ($lib_map_path != "") ]]; then + incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup" + echo $incl_ref >> $file + fi +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ucli.key vio_rf_control_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc vio_rf_control_simv.daidir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_rf_control.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_rf_control.sh [-help]\n\ +Usage: vio_rf_control.sh [-lib_map_path]\n\ +Usage: vio_rf_control.sh [-reset_run]\n\ +Usage: vio_rf_control.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xcelium/README.txt b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xcelium/README.txt new file mode 100644 index 00000000..935aafbf --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xcelium/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 17:52:16 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_rf_control.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_rf_control.sh' script. + +./vio_rf_control.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_rf_control.sh -noclean_files + +For more information on the script, please type './vio_rf_control.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xcelium/file_info.txt b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xcelium/file_info.txt new file mode 100644 index 00000000..5d1c0b80 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xcelium/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" +vio_rf_control.v,verilog,xil_defaultlib,../../../ip/vio_rf_control/sim/vio_rf_control.v,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_hop/ies/glbl.v b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xcelium/glbl.v similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_hop/ies/glbl.v rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xcelium/glbl.v diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xcelium/run.f b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xcelium/run.f new file mode 100644 index 00000000..60d4bd69 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xcelium/run.f @@ -0,0 +1,14 @@ +-makelib xcelium_lib/xil_defaultlib -sv \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib xcelium_lib/xpm \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../ip/vio_rf_control/sim/vio_rf_control.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_null_phase/xcelium/vio_null_phase.sh b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xcelium/vio_rf_control.sh similarity index 85% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_null_phase/xcelium/vio_null_phase.sh rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xcelium/vio_rf_control.sh index 074ab1f3..54050391 100755 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_null_phase/xcelium/vio_null_phase.sh +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xcelium/vio_rf_control.sh @@ -2,22 +2,22 @@ #********************************************************************************************************* # Vivado (TM) v2019.1.3 (64-bit) # -# Filename : vio_null_phase.sh +# Filename : vio_rf_control.sh # Simulator : Cadence Xcelium Parallel Simulator # Description : Simulation script for compiling, elaborating and verifying the project source files. # The script will automatically create the design libraries sub-directories in the run # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Tue Apr 25 17:40:58 CST 2023 +# Generated by Vivado on Mon May 08 17:52:16 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. # -# usage: vio_null_phase.sh [-help] -# usage: vio_null_phase.sh [-lib_map_path] -# usage: vio_null_phase.sh [-noclean_files] -# usage: vio_null_phase.sh [-reset_run] +# usage: vio_rf_control.sh [-help] +# usage: vio_rf_control.sh [-lib_map_path] +# usage: vio_rf_control.sh [-noclean_files] +# usage: vio_rf_control.sh [-reset_run] # # Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the # 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the @@ -27,7 +27,7 @@ # # You can also point to the simulation libraries by either replacing the in this # script with the compiled library directory path or specify this path with the '-lib_map_path' switch when -# executing this script. Please type 'vio_null_phase.sh -help' for more information. +# executing this script. Please type 'vio_rf_control.sh -help' for more information. # # Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' # @@ -54,7 +54,7 @@ design_libs=(xil_defaultlib xpm) sim_lib_dir="xcelium_lib" # Script info -echo -e "vio_null_phase.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" +echo -e "vio_rf_control.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" # Main steps run() @@ -73,12 +73,12 @@ execute() -reflib "$ref_lib_dir/secureip:secureip" \ -reflib "$ref_lib_dir/unimacro:unimacro" \ -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ - -top xil_defaultlib.vio_null_phase \ + -top xil_defaultlib.vio_rf_control \ -f run.f \ -top glbl \ glbl.v \ - +incdir+"../../../ip/vio_null_phase/hdl/verilog" \ - +incdir+"../../../ip/vio_null_phase/hdl" + +incdir+"../../../ip/vio_rf_control/hdl/verilog" \ + +incdir+"../../../ip/vio_rf_control/hdl" } # STEP: setup @@ -87,7 +87,7 @@ setup() case $1 in "-lib_map_path" ) if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./vio_null_phase.sh -help\" for more information)\n" + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_rf_control.sh -help\" for more information)\n" exit 1 else ref_lib_dir=$2 @@ -146,7 +146,7 @@ reset_run() check_args() { if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./vio_null_phase.sh -help\" for more information)\n" + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_rf_control.sh -help\" for more information)\n" exit 1 fi @@ -158,10 +158,10 @@ check_args() # Script usage usage() { - msg="Usage: vio_null_phase.sh [-help]\n\ -Usage: vio_null_phase.sh [-lib_map_path]\n\ -Usage: vio_null_phase.sh [-reset_run]\n\ -Usage: vio_null_phase.sh [-noclean_files]\n\n\ + msg="Usage: vio_rf_control.sh [-help]\n\ +Usage: vio_rf_control.sh [-lib_map_path]\n\ +Usage: vio_rf_control.sh [-reset_run]\n\ +Usage: vio_rf_control.sh [-noclean_files]\n\n\ [-help] -- Print help information for this script\n\n\ [-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xsim/README.txt b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xsim/README.txt new file mode 100644 index 00000000..fdb6b834 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 17:52:16 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_rf_control.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_rf_control.sh' script. + +./vio_rf_control.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_rf_control.sh -noclean_files + +For more information on the script, please type './vio_rf_control.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_cal/xsim/cmd.tcl b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xsim/cmd.tcl similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_cal/xsim/cmd.tcl rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xsim/cmd.tcl diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xsim/file_info.txt b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xsim/file_info.txt new file mode 100644 index 00000000..6afb6a11 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xsim/file_info.txt @@ -0,0 +1,2 @@ +vio_rf_control.v,verilog,xil_defaultlib,../../../ip/vio_rf_control/sim/vio_rf_control.v,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_hop/modelsim/glbl.v b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xsim/glbl.v similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_hop/modelsim/glbl.v rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xsim/glbl.v diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_null_phase/xsim/vio_null_phase.sh b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xsim/vio_rf_control.sh similarity index 85% rename from projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_null_phase/xsim/vio_null_phase.sh rename to projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xsim/vio_rf_control.sh index b399ae3a..b0595436 100755 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/sim_scripts/vio_null_phase/xsim/vio_null_phase.sh +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xsim/vio_rf_control.sh @@ -2,22 +2,22 @@ #********************************************************************************************************* # Vivado (TM) v2019.1.3 (64-bit) # -# Filename : vio_null_phase.sh +# Filename : vio_rf_control.sh # Simulator : Xilinx Vivado Simulator # Description : Simulation script for compiling, elaborating and verifying the project source files. # The script will automatically create the design libraries sub-directories in the run # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Tue Apr 25 17:40:58 CST 2023 +# Generated by Vivado on Mon May 08 17:52:16 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. # -# usage: vio_null_phase.sh [-help] -# usage: vio_null_phase.sh [-lib_map_path] -# usage: vio_null_phase.sh [-noclean_files] -# usage: vio_null_phase.sh [-reset_run] +# usage: vio_rf_control.sh [-help] +# usage: vio_rf_control.sh [-lib_map_path] +# usage: vio_rf_control.sh [-noclean_files] +# usage: vio_rf_control.sh [-reset_run] # #********************************************************************************************************* @@ -27,7 +27,7 @@ xvlog_opts="--relax" # Script info -echo -e "vio_null_phase.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" +echo -e "vio_rf_control.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" # Main steps run() @@ -50,13 +50,13 @@ compile() # RUN_STEP: elaborate() { - xelab --relax --debug typical --mt auto -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot vio_null_phase xil_defaultlib.vio_null_phase xil_defaultlib.glbl -log elaborate.log + xelab --relax --debug typical --mt auto -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot vio_rf_control xil_defaultlib.vio_rf_control xil_defaultlib.glbl -log elaborate.log } # RUN_STEP: simulate() { - xsim vio_null_phase -key {Behavioral:sim_1:Functional:vio_null_phase} -tclbatch cmd.tcl -log simulate.log + xsim vio_rf_control -key {Behavioral:sim_1:Functional:vio_rf_control} -tclbatch cmd.tcl -log simulate.log } # STEP: setup @@ -65,7 +65,7 @@ setup() case $1 in "-lib_map_path" ) if [[ ($2 == "") ]]; then - echo -e "ERROR: Simulation library directory path not specified (type \"./vio_null_phase.sh -help\" for more information)\n" + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_rf_control.sh -help\" for more information)\n" exit 1 fi copy_setup_file $2 @@ -168,7 +168,7 @@ map_local_libs() # Delete generated data from the previous run reset_run() { - files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb vio_null_phase.wdb xsim.dir) + files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb vio_rf_control.wdb xsim.dir) for (( i=0; i<${#files_to_remove[*]}; i++ )); do file="${files_to_remove[i]}" if [[ -e $file ]]; then @@ -181,7 +181,7 @@ reset_run() check_args() { if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then - echo -e "ERROR: Unknown option specified '$2' (type \"./vio_null_phase.sh -help\" for more information)\n" + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_rf_control.sh -help\" for more information)\n" exit 1 fi @@ -193,10 +193,10 @@ check_args() # Script usage usage() { - msg="Usage: vio_null_phase.sh [-help]\n\ -Usage: vio_null_phase.sh [-lib_map_path]\n\ -Usage: vio_null_phase.sh [-reset_run]\n\ -Usage: vio_null_phase.sh [-noclean_files]\n\n\ + msg="Usage: vio_rf_control.sh [-help]\n\ +Usage: vio_rf_control.sh [-lib_map_path]\n\ +Usage: vio_rf_control.sh [-reset_run]\n\ +Usage: vio_rf_control.sh [-noclean_files]\n\n\ [-help] -- Print help information for this script\n\n\ [-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ diff --git a/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xsim/vlog.prj b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xsim/vlog.prj new file mode 100644 index 00000000..b28359a7 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xsim/vlog.prj @@ -0,0 +1,6 @@ +verilog xil_defaultlib --include "../../../ip/vio_rf_control/hdl/verilog" --include "../../../ip/vio_rf_control/hdl" \ +"../../../ip/vio_rf_control/sim/vio_rf_control.v" \ + +verilog xil_defaultlib "glbl.v" + +nosort diff --git a/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/0789e4a10aba5413/0789e4a10aba5413.xci b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/0789e4a10aba5413/0789e4a10aba5413.xci new file mode 100644 index 00000000..ef9d34d2 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/0789e4a10aba5413/0789e4a10aba5413.xci @@ -0,0 +1,109 @@ + + + xilinx.com + ipcache + 0789e4a10aba5413 + 0 + + + rom_freq_word + + + 100000000 + 4 + Memory_Slave + AXI4_Full + false + Minimum_Area + false + 9 + NONE + ../coe/freq_word.coe + ALL + rom_freq_word + false + false + false + false + false + false + false + false + false + Always_Enabled + Always_Enabled + Single_Bit_Error_Injection + false + Native + true + no_mem_loaded + Single_Port_ROM + WRITE_FIRST + WRITE_FIRST + 0 + 0 + BRAM + 0 + 100 + 100 + 0 + 0 + 0 + 0 + 8kx2 + false + false + 1 + 1 + 11 + 11 + false + true + false + false + 0 + false + false + CE + CE + SYNC + false + false + false + false + false + false + false + 81 + 11 + 11 + No_ECC + false + false + false + Stand_Alone + zynq + xc7z100 + ffg900 + VERILOG + + -2 + + + TRUE + TRUE + 0789e4a10aba5413 + 0137cb81 + 42 + IP_Unknown + 3 + TRUE + . + + . + 2019.1.3 + GLOBAL + + + + diff --git a/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/0789e4a10aba5413/rom_freq_word.dcp b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/0789e4a10aba5413/rom_freq_word.dcp new file mode 100644 index 00000000..1df86faa --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/0789e4a10aba5413/rom_freq_word.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:fc1be69239719f0fd3eef9f40b77e07263f777ee9a1bdd6d3239c1b5c908e590 +size 25932 diff --git a/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/0789e4a10aba5413/rom_freq_word_sim_netlist.v b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/0789e4a10aba5413/rom_freq_word_sim_netlist.v new file mode 100755 index 00000000..1138426b --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/0789e4a10aba5413/rom_freq_word_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:c8863a7436d3a7e705252dc609290565df5ba97112e23a395887a831161aaee6 +size 28875 diff --git a/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/0789e4a10aba5413/rom_freq_word_sim_netlist.vhdl b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/0789e4a10aba5413/rom_freq_word_sim_netlist.vhdl new file mode 100755 index 00000000..b32d2444 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/0789e4a10aba5413/rom_freq_word_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:b8c205d7844ce045523bd9915ebb342f79637c8d36a5047015902b4ccf7d8b65 +size 44740 diff --git a/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/0789e4a10aba5413/rom_freq_word_stub.v b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/0789e4a10aba5413/rom_freq_word_stub.v new file mode 100755 index 00000000..cd2f58a5 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/0789e4a10aba5413/rom_freq_word_stub.v @@ -0,0 +1,22 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Mon May 8 18:56:10 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ rom_freq_word_stub.v +// Design : rom_freq_word +// Purpose : Stub declaration of top-level module interface +// Device : xc7z100ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "blk_mem_gen_v8_4_3,Vivado 2019.1.3" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clka, addra, douta) +/* synthesis syn_black_box black_box_pad_pin="clka,addra[6:0],douta[10:0]" */; + input clka; + input [6:0]addra; + output [10:0]douta; +endmodule diff --git a/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/0789e4a10aba5413/rom_freq_word_stub.vhdl b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/0789e4a10aba5413/rom_freq_word_stub.vhdl new file mode 100755 index 00000000..c060bdb7 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/0789e4a10aba5413/rom_freq_word_stub.vhdl @@ -0,0 +1,32 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Mon May 8 18:56:10 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ rom_freq_word_stub.vhdl +-- Design : rom_freq_word +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + Port ( + clka : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR ( 6 downto 0 ); + douta : out STD_LOGIC_VECTOR ( 10 downto 0 ) + ); + +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clka,addra[6:0],douta[10:0]"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_3,Vivado 2019.1.3"; +begin +end; diff --git a/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/6c6203d172e581d2/6c6203d172e581d2.xci b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/6c6203d172e581d2/6c6203d172e581d2.xci new file mode 100644 index 00000000..24581bff --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/6c6203d172e581d2/6c6203d172e581d2.xci @@ -0,0 +1,810 @@ + + + xilinx.com + ipcache + 6c6203d172e581d2 + 0 + + + vio_rf_control + + + 100000000 + 0 + 1 + 1 + 14 + 11 + 1 + 1 + 1 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b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/6c6203d172e581d2/vio_rf_control.dcp new file mode 100644 index 00000000..6412a3c4 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/6c6203d172e581d2/vio_rf_control.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:3b4410080039a3dcfb464d8b84ebf3c2fce7cfc4c930081fec93fd2dfc92e22e +size 158846 diff --git a/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/6c6203d172e581d2/vio_rf_control_sim_netlist.v b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/6c6203d172e581d2/vio_rf_control_sim_netlist.v new file mode 100755 index 00000000..f5411698 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/6c6203d172e581d2/vio_rf_control_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:1a377e907e4c1862468589fc034a5d64ec916ca30b0834d8f9576f01db965871 +size 376176 diff --git a/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/6c6203d172e581d2/vio_rf_control_sim_netlist.vhdl b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/6c6203d172e581d2/vio_rf_control_sim_netlist.vhdl new file mode 100755 index 00000000..58e506d6 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/6c6203d172e581d2/vio_rf_control_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:16567dd0947209a5e3572fa3482fcf3fede36d7283acddef2745b3e6797e2ca6 +size 705727 diff --git a/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/6c6203d172e581d2/vio_rf_control_stub.v b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/6c6203d172e581d2/vio_rf_control_stub.v new file mode 100755 index 00000000..19c5de2c --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/6c6203d172e581d2/vio_rf_control_stub.v @@ -0,0 +1,37 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Sun May 7 19:30:42 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_rf_control_stub.v +// Design : vio_rf_control +// Purpose : Stub declaration of top-level module interface +// Device : xc7z100ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "vio,Vivado 2019.1.3" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe_in0, probe_out0, probe_out1, + probe_out2, probe_out3, probe_out4, probe_out5, probe_out6, probe_out7, probe_out8, probe_out9, + probe_out10, probe_out11, probe_out12, probe_out13) +/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[10:0],probe_out0[0:0],probe_out1[1:0],probe_out2[0:0],probe_out3[5:0],probe_out4[5:0],probe_out5[10:0],probe_out6[0:0],probe_out7[0:0],probe_out8[0:0],probe_out9[0:0],probe_out10[0:0],probe_out11[0:0],probe_out12[0:0],probe_out13[15:0]" */; + input clk; + input [10:0]probe_in0; + output [0:0]probe_out0; + output [1:0]probe_out1; + output [0:0]probe_out2; + output [5:0]probe_out3; + output [5:0]probe_out4; + output [10:0]probe_out5; + output [0:0]probe_out6; + output [0:0]probe_out7; + output [0:0]probe_out8; + output [0:0]probe_out9; + output [0:0]probe_out10; + output [0:0]probe_out11; + output [0:0]probe_out12; + output [15:0]probe_out13; +endmodule diff --git a/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/6c6203d172e581d2/vio_rf_control_stub.vhdl b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/6c6203d172e581d2/vio_rf_control_stub.vhdl new file mode 100755 index 00000000..313783ad --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/6c6203d172e581d2/vio_rf_control_stub.vhdl @@ -0,0 +1,45 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Sun May 7 19:30:42 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_rf_control_stub.vhdl +-- Design : vio_rf_control +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + Port ( + clk : in STD_LOGIC; + probe_in0 : in STD_LOGIC_VECTOR ( 10 downto 0 ); + probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out1 : out STD_LOGIC_VECTOR ( 1 downto 0 ); + probe_out2 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out3 : out STD_LOGIC_VECTOR ( 5 downto 0 ); + probe_out4 : out STD_LOGIC_VECTOR ( 5 downto 0 ); + probe_out5 : out STD_LOGIC_VECTOR ( 10 downto 0 ); + probe_out6 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out7 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out8 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out9 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out10 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out11 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out12 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out13 : out STD_LOGIC_VECTOR ( 15 downto 0 ) + ); + +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[10:0],probe_out0[0:0],probe_out1[1:0],probe_out2[0:0],probe_out3[5:0],probe_out4[5:0],probe_out5[10:0],probe_out6[0:0],probe_out7[0:0],probe_out8[0:0],probe_out9[0:0],probe_out10[0:0],probe_out11[0:0],probe_out12[0:0],probe_out13[15:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3"; +begin +end; diff --git a/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/af26366c91bcf19e/af26366c91bcf19e.xci b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/af26366c91bcf19e/af26366c91bcf19e.xci new file mode 100644 index 00000000..b3b99e1e --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/af26366c91bcf19e/af26366c91bcf19e.xci @@ -0,0 +1,810 @@ + + + xilinx.com + ipcache + af26366c91bcf19e + 0 + + + vio_manual_ctrl + + + 100000000 + 0 + 1 + 0 + 5 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 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mode 100644 index 00000000..56de7bb8 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/af26366c91bcf19e/vio_manual_ctrl.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:be465582ee86c6c71050c881d6849a69826700b65bec767372e49531f61d9433 +size 145067 diff --git a/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/af26366c91bcf19e/vio_manual_ctrl_sim_netlist.v b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/af26366c91bcf19e/vio_manual_ctrl_sim_netlist.v new file mode 100755 index 00000000..ccc2f537 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/af26366c91bcf19e/vio_manual_ctrl_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:ba64402ef87fa7cf0612f20096dc39f48c6a0441f266fddb26a2b5538c3c242f +size 353387 diff --git a/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/af26366c91bcf19e/vio_manual_ctrl_sim_netlist.vhdl b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/af26366c91bcf19e/vio_manual_ctrl_sim_netlist.vhdl new file mode 100755 index 00000000..d158c084 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/af26366c91bcf19e/vio_manual_ctrl_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:9e506290eb6188999540083616ec4fdf679a657aebbf2f58879a577f12d46ffe +size 669971 diff --git a/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/af26366c91bcf19e/vio_manual_ctrl_stub.v b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/af26366c91bcf19e/vio_manual_ctrl_stub.v new file mode 100755 index 00000000..6a1391f8 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/af26366c91bcf19e/vio_manual_ctrl_stub.v @@ -0,0 +1,26 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Mon May 8 17:56:00 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_manual_ctrl_stub.v +// Design : vio_manual_ctrl +// Purpose : Stub declaration of top-level module interface +// Device : xc7z100ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "vio,Vivado 2019.1.3" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe_out0, probe_out1, probe_out2, + probe_out3, probe_out4) +/* synthesis syn_black_box black_box_pad_pin="clk,probe_out0[2:0],probe_out1[0:0],probe_out2[31:0],probe_out3[1:0],probe_out4[3:0]" */; + input clk; + output [2:0]probe_out0; + output [0:0]probe_out1; + output [31:0]probe_out2; + output [1:0]probe_out3; + output [3:0]probe_out4; +endmodule diff --git a/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/af26366c91bcf19e/vio_manual_ctrl_stub.vhdl b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/af26366c91bcf19e/vio_manual_ctrl_stub.vhdl new file mode 100755 index 00000000..db37386f --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/af26366c91bcf19e/vio_manual_ctrl_stub.vhdl @@ -0,0 +1,35 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Mon May 8 17:56:00 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_manual_ctrl_stub.vhdl +-- Design : vio_manual_ctrl +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + Port ( + clk : in STD_LOGIC; + probe_out0 : out STD_LOGIC_VECTOR ( 2 downto 0 ); + probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out2 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + probe_out3 : out STD_LOGIC_VECTOR ( 1 downto 0 ); + probe_out4 : out STD_LOGIC_VECTOR ( 3 downto 0 ) + ); + +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk,probe_out0[2:0],probe_out1[0:0],probe_out2[31:0],probe_out3[1:0],probe_out4[3:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3"; +begin +end; diff --git a/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/e64b5bd88b1a9e5c/e64b5bd88b1a9e5c.xci b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/e64b5bd88b1a9e5c/e64b5bd88b1a9e5c.xci new file mode 100644 index 00000000..c7f2b8b8 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/e64b5bd88b1a9e5c/e64b5bd88b1a9e5c.xci @@ -0,0 +1,109 @@ + + + xilinx.com + ipcache + e64b5bd88b1a9e5c + 0 + + + rom_freq_word + + + 100000000 + 4 + Memory_Slave + AXI4_Full + false + Minimum_Area + false + 9 + NONE + ../coe/freq_word.coe + ALL + rom_freq_word + false + false + false + false + false + false + false + false + false + Always_Enabled + Always_Enabled + Single_Bit_Error_Injection + false + Native + true + no_mem_loaded + Single_Port_ROM + WRITE_FIRST + WRITE_FIRST + 0 + 0 + BRAM + 0 + 100 + 100 + 0 + 0 + 0 + 0 + 8kx2 + false + false + 1 + 1 + 11 + 11 + false + true + false + false + 0 + false + false + CE + CE + SYNC + false + false + false + false + false + false + false + 81 + 11 + 11 + No_ECC + false + false + false + Stand_Alone + zynq + xc7z100 + ffg900 + VERILOG + + -2 + + + TRUE + TRUE + e64b5bd88b1a9e5c + 0137cb81 + 42 + IP_Unknown + 3 + TRUE + . + + . + 2019.1.3 + GLOBAL + + + + diff --git a/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/e64b5bd88b1a9e5c/rom_freq_word.dcp b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/e64b5bd88b1a9e5c/rom_freq_word.dcp new file mode 100644 index 00000000..efe6b55c --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/e64b5bd88b1a9e5c/rom_freq_word.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:f96d74795d18bcf73097952088143f65568b2cc188dfac35ffe84f776371de1c +size 25874 diff --git a/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/e64b5bd88b1a9e5c/rom_freq_word_sim_netlist.v b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/e64b5bd88b1a9e5c/rom_freq_word_sim_netlist.v new file mode 100755 index 00000000..bbb064fb --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/e64b5bd88b1a9e5c/rom_freq_word_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:16051672c9348609da16879fccb89024402fddae4bd46743b3a36561dd648603 +size 28875 diff --git a/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/e64b5bd88b1a9e5c/rom_freq_word_sim_netlist.vhdl b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/e64b5bd88b1a9e5c/rom_freq_word_sim_netlist.vhdl new file mode 100755 index 00000000..8a9f76c8 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/e64b5bd88b1a9e5c/rom_freq_word_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:7de45451f808c9c0ca85bb25409f21c3a387a7abe5b133ff12a54232b17241ac +size 44740 diff --git a/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/e64b5bd88b1a9e5c/rom_freq_word_stub.v b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/e64b5bd88b1a9e5c/rom_freq_word_stub.v new file mode 100755 index 00000000..8f66d363 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/e64b5bd88b1a9e5c/rom_freq_word_stub.v @@ -0,0 +1,22 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Sun May 7 19:30:29 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ rom_freq_word_stub.v +// Design : rom_freq_word +// Purpose : Stub declaration of top-level module interface +// Device : xc7z100ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "blk_mem_gen_v8_4_3,Vivado 2019.1.3" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clka, addra, douta) +/* synthesis syn_black_box black_box_pad_pin="clka,addra[6:0],douta[10:0]" */; + input clka; + input [6:0]addra; + output [10:0]douta; +endmodule diff --git a/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/e64b5bd88b1a9e5c/rom_freq_word_stub.vhdl b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/e64b5bd88b1a9e5c/rom_freq_word_stub.vhdl new file mode 100755 index 00000000..1219c641 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/e64b5bd88b1a9e5c/rom_freq_word_stub.vhdl @@ -0,0 +1,32 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Sun May 7 19:30:29 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ rom_freq_word_stub.vhdl +-- Design : rom_freq_word +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + Port ( + clka : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR ( 6 downto 0 ); + douta : out STD_LOGIC_VECTOR ( 10 downto 0 ) + ); + +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clka,addra[6:0],douta[10:0]"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_3,Vivado 2019.1.3"; +begin +end; diff --git a/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/wt/gui_handlers.wdf b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/wt/gui_handlers.wdf index d1dc7507..446e5f22 100644 --- a/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/wt/gui_handlers.wdf +++ b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/wt/gui_handlers.wdf @@ -1,15 +1,32 @@ version:1 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:32:00:00 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b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/wt/java_command_handlers.wdf @@ -1,6 +1,9 @@ version:1 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6164646578697374696e67697068616e646c6572:31:00:00 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:636c6f736570726f6a656374:31:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6164646578697374696e67697068616e646c6572:35:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:636c6f736570726f6a656374:35:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6564697464656c657465:32:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6d616e616765636f6d706f7369746574617267657473:31:00:00 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a/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/wt/synthesis.wdf b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/wt/synthesis.wdf new file mode 100644 index 00000000..06338888 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/wt/synthesis.wdf @@ -0,0 +1,39 @@ +version:1 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:7863377a3130306666673930302d32:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:726f6d5f667265715f776f7264:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e636c7564655f64697273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 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+73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a333473:00:00 +73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:323135302e3135364d42:00:00 +73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3734392e3233384d42:00:00 +eof:1256184425 diff --git a/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/wt/webtalk_pa.xml b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/wt/webtalk_pa.xml index f9e8521b..d9e025ef 100644 --- a/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/wt/webtalk_pa.xml +++ b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/wt/webtalk_pa.xml @@ -3,7 +3,7 @@ - +
@@ -17,30 +17,50 @@ This means code written to parse this file will need to be revisited each subseq - - + + + + + - - + + + + + - - + + + + + + + + + + + + - - + + - - + + + + + + - + - +
diff --git a/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_1.xml b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_1.xml new file mode 100644 index 00000000..62b77e3c --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_1.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_2.xml b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_2.xml new file mode 100644 index 00000000..6abe9d9f --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_2.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_3.xml b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_3.xml new file mode 100644 index 00000000..e9efe6b0 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_3.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_4.xml b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_4.xml new file mode 100644 index 00000000..62b77e3c --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_4.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_dmf_invert_prbs7_deci8_synth_1/.Vivado_Synthesis.queue.rst b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/.Vivado_Synthesis.queue.rst similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_dmf_invert_prbs7_deci8_synth_1/.Vivado_Synthesis.queue.rst rename to projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/.Vivado_Synthesis.queue.rst diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/.vivado.begin.rst b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/.vivado.begin.rst similarity index 75% rename from projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/.vivado.begin.rst rename to projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/.vivado.begin.rst index c4cc8a9e..25ac4ba3 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/.vivado.begin.rst +++ b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/.vivado.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_dmf_invert_prbs7_deci8_synth_1/.vivado.end.rst b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/.vivado.end.rst similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_dmf_invert_prbs7_deci8_synth_1/.vivado.end.rst rename to projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/.vivado.end.rst diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_dmf_invert_prbs7_deci8_synth_1/ISEWrap.js b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/ISEWrap.js similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_dmf_invert_prbs7_deci8_synth_1/ISEWrap.js rename to projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/ISEWrap.js diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_dmf_invert_prbs7_deci8_synth_1/ISEWrap.sh b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/ISEWrap.sh similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_dmf_invert_prbs7_deci8_synth_1/ISEWrap.sh rename to projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/ISEWrap.sh diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_dmf_invert_prbs7_deci8_synth_1/__synthesis_is_complete__ b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/__synthesis_is_complete__ similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_dmf_invert_prbs7_deci8_synth_1/__synthesis_is_complete__ rename to projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/__synthesis_is_complete__ diff --git a/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/dont_touch.xdc b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/dont_touch.xdc new file mode 100644 index 00000000..411db9c9 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/dont_touch.xdc @@ -0,0 +1,16 @@ +# This file is automatically generated. +# It contains project source information necessary for synthesis and implementation. + +# IP: /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/rom_freq_word/rom_freq_word.xci +# IP: The module: 'rom_freq_word' is the root of the design. Do not add the DONT_TOUCH constraint. + +# XDC: /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/rom_freq_word/rom_freq_word_ooc.xdc +# XDC: The top module name and the constraint reference have the same name: 'rom_freq_word'. Do not add the DONT_TOUCH constraint. +set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet + +# IP: /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/rom_freq_word/rom_freq_word.xci +# IP: The module: 'rom_freq_word' is the root of the design. Do not add the DONT_TOUCH constraint. + +# XDC: /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/rom_freq_word/rom_freq_word_ooc.xdc +# XDC: The top module name and the constraint reference have the same name: 'rom_freq_word'. Do not add the DONT_TOUCH constraint. +#dup# set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet diff --git a/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/gen_run.xml b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/gen_run.xml new file mode 100644 index 00000000..028ada61 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/gen_run.xml @@ -0,0 +1,62 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_null_phase_synth_1/htr.txt b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/htr.txt similarity index 68% rename from projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_null_phase_synth_1/htr.txt rename to projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/htr.txt index eb656772..144dc12a 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_null_phase_synth_1/htr.txt +++ b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/htr.txt @@ -6,4 +6,4 @@ # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. # -vivado -log vio_null_phase.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_null_phase.tcl +vivado -log rom_freq_word.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source rom_freq_word.tcl diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/project.wdf b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/project.wdf similarity index 80% rename from projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/project.wdf rename to projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/project.wdf index 76684d54..0e0ee1e6 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/project.wdf +++ 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+70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f72665f636f6e74726f6c:636f72655f636f6e7461696e6572:74727565:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:30:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00 @@ -34,5 +33,5 @@ version:1 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:3131:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3131:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3131:00:00 -5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3966393835363732626435303431393139633038356339623061353561633562:506172656e742050412070726f6a656374204944:00 -eof:47557159 +5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3665393633363431666561663437633339616462383862306139303537636232:506172656e742050412070726f6a656374204944:00 +eof:3296966126 diff --git a/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word.dcp b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word.dcp new file mode 100644 index 00000000..8ee615a3 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:e7aa363f04a2c88ad0f7fec91589fbdfb8231f3ba895d79d4fc70d52ab5ae877 +size 26124 diff --git a/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word.tcl b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word.tcl new file mode 100644 index 00000000..b2834e1c --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word.tcl @@ -0,0 +1,158 @@ +# +# Synthesis run script generated by Vivado +# + +set TIME_start [clock seconds] +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +set_param simulator.modelsimInstallPath /home/josh/Software/Mentor/modeltech/bin +set_param simulator.vcsmxInstallPath /usr/synopsys/vcs/T-2022.06/bin +set_param chipscope.maxJobs 5 +set_msg_config -id {Common 17-41} -limit 10000000 +set_param project.vivado.isBlockSynthRun true +set_msg_config -msgmgr_mode ooc_run +create_project -in_memory -part xc7z100ffg900-2 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info +set_property webtalk.parent_dir /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/wt [current_project] +set_property parent.project_path /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.xpr [current_project] +set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language Verilog [current_project] +set_property ip_output_repo /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +read_ip -quiet /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/rom_freq_word/rom_freq_word.xci +set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/rom_freq_word/rom_freq_word_ooc.xdc] + +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +read_xdc dont_touch.xdc +set_property used_in_implementation false [get_files dont_touch.xdc] +set_param ips.enableIPCacheLiteLoad 1 + +set cached_ip [config_ip_cache -export -no_bom -dir /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1 -new_name rom_freq_word -ip [get_ips rom_freq_word]] + +if { $cached_ip eq {} } { +close [open __synthesis_is_running__ w] + +synth_design -top rom_freq_word -part xc7z100ffg900-2 -mode out_of_context + +#--------------------------------------------------------- +# Generate Checkpoint/Stub/Simulation Files For IP Cache +#--------------------------------------------------------- +# disable binary constraint mode for IPCache checkpoints +set_param constraints.enableBinaryConstraints false + +catch { + write_checkpoint -force -noxdef -rename_prefix rom_freq_word_ rom_freq_word.dcp + + set ipCachedFiles {} + write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ rom_freq_word_stub.v + lappend ipCachedFiles rom_freq_word_stub.v + + write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ rom_freq_word_stub.vhdl + lappend ipCachedFiles rom_freq_word_stub.vhdl + + write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ rom_freq_word_sim_netlist.v + lappend ipCachedFiles rom_freq_word_sim_netlist.v + + write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ rom_freq_word_sim_netlist.vhdl + lappend ipCachedFiles rom_freq_word_sim_netlist.vhdl +set TIME_taken [expr [clock seconds] - $TIME_start] + + config_ip_cache -add -dcp rom_freq_word.dcp -move_files $ipCachedFiles -use_project_ipc -synth_runtime $TIME_taken -ip [get_ips rom_freq_word] +} + +rename_ref -prefix_all rom_freq_word_ + +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef rom_freq_word.dcp +create_report "rom_freq_word_synth_1_synth_report_utilization_0" "report_utilization -file rom_freq_word_utilization_synth.rpt -pb rom_freq_word_utilization_synth.pb" + +if { [catch { + write_verilog -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + write_vhdl -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + write_verilog -force -mode funcsim /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_sim_netlist.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + +if { [catch { + write_vhdl -force -mode funcsim /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_sim_netlist.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + + +} else { + + +}; # end if cached_ip + +add_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/rom_freq_word/rom_freq_word.xci] + +add_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/rom_freq_word/rom_freq_word.xci] + +add_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_sim_netlist.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/rom_freq_word/rom_freq_word.xci] + +add_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_sim_netlist.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/rom_freq_word/rom_freq_word.xci] + +add_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word.dcp -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/rom_freq_word/rom_freq_word.xci] + +if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/rom_freq_word]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_sim_netlist.v /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/rom_freq_word + } +} + +if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/rom_freq_word]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_sim_netlist.vhdl /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/rom_freq_word + } +} + +if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/rom_freq_word]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.v /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/rom_freq_word + } +} + +if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/rom_freq_word]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.vhdl /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/rom_freq_word + } +} +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] diff --git a/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word.vds b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word.vds new file mode 100644 index 00000000..67cd3fcc --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word.vds @@ -0,0 +1,451 @@ +#----------------------------------------------------------- +# Vivado v2019.1.3 (64-bit) +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 +# Start of session at: Mon May 8 18:55:25 2023 +# Process ID: 2631099 +# Current directory: /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1 +# Command line: vivado -log rom_freq_word.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source rom_freq_word.tcl +# Log file: /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word.vds +# Journal file: /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/vivado.jou +#----------------------------------------------------------- +source rom_freq_word.tcl -notrace +Command: synth_design -top rom_freq_word -part xc7z100ffg900-2 -mode out_of_context +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7z100' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z100' +INFO: [Device 21-403] Loading part xc7z100ffg900-2 +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 2631153 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 1855.602 ; gain = 153.688 ; free physical = 3731 ; free virtual = 46738 +--------------------------------------------------------------------------------- +INFO: [Synth 8-638] synthesizing module 'rom_freq_word' [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/rom_freq_word/synth/rom_freq_word.vhd:67] + Parameter C_FAMILY bound to: zynq - type: string + Parameter C_XDEVICEFAMILY bound to: zynq - type: string + Parameter C_ELABORATION_DIR bound to: ./ - type: string + Parameter C_INTERFACE_TYPE bound to: 0 - type: integer + Parameter C_AXI_TYPE bound to: 1 - type: integer + Parameter C_AXI_SLAVE_TYPE bound to: 0 - type: integer + Parameter C_USE_BRAM_BLOCK bound to: 0 - type: integer + Parameter C_ENABLE_32BIT_ADDRESS bound to: 0 - type: integer + Parameter C_CTRL_ECC_ALGO bound to: NONE - type: string + Parameter C_HAS_AXI_ID bound to: 0 - type: integer + Parameter C_AXI_ID_WIDTH bound to: 4 - type: integer + Parameter C_MEM_TYPE bound to: 3 - type: integer + Parameter C_BYTE_SIZE bound to: 9 - type: integer + Parameter C_ALGORITHM bound to: 1 - type: integer + Parameter C_PRIM_TYPE bound to: 1 - type: integer + Parameter C_LOAD_INIT_FILE bound to: 1 - type: integer + Parameter C_INIT_FILE_NAME bound to: rom_freq_word.mif - type: string + Parameter C_INIT_FILE bound to: rom_freq_word.mem - type: string + Parameter C_USE_DEFAULT_DATA bound to: 0 - type: integer + Parameter C_DEFAULT_DATA bound to: 0 - type: string + Parameter C_HAS_RSTA bound to: 0 - type: integer + Parameter C_RST_PRIORITY_A bound to: CE - type: string + Parameter C_RSTRAM_A bound to: 0 - type: integer + Parameter C_INITA_VAL bound to: 0 - type: string + Parameter C_HAS_ENA bound to: 0 - type: integer + Parameter C_HAS_REGCEA bound to: 0 - type: integer + Parameter C_USE_BYTE_WEA bound to: 0 - type: integer + Parameter C_WEA_WIDTH bound to: 1 - type: integer + Parameter C_WRITE_MODE_A bound to: WRITE_FIRST - type: string + Parameter C_WRITE_WIDTH_A bound to: 11 - type: integer + Parameter C_READ_WIDTH_A bound to: 11 - type: integer + Parameter C_WRITE_DEPTH_A bound to: 81 - type: integer + Parameter C_READ_DEPTH_A bound to: 81 - type: integer + Parameter C_ADDRA_WIDTH bound to: 7 - type: integer + Parameter C_HAS_RSTB bound to: 0 - type: integer + Parameter C_RST_PRIORITY_B bound to: CE - type: string + Parameter C_RSTRAM_B bound to: 0 - type: integer + Parameter C_INITB_VAL bound to: 0 - type: string + Parameter C_HAS_ENB bound to: 0 - type: integer + Parameter C_HAS_REGCEB bound to: 0 - type: integer + Parameter C_USE_BYTE_WEB bound to: 0 - type: integer + Parameter C_WEB_WIDTH bound to: 1 - type: integer + Parameter C_WRITE_MODE_B bound to: WRITE_FIRST - type: string + Parameter C_WRITE_WIDTH_B bound to: 11 - type: integer + Parameter C_READ_WIDTH_B bound to: 11 - type: integer + Parameter C_WRITE_DEPTH_B bound to: 81 - type: integer + Parameter C_READ_DEPTH_B bound to: 81 - type: integer + Parameter C_ADDRB_WIDTH bound to: 7 - type: integer + Parameter C_HAS_MEM_OUTPUT_REGS_A bound to: 1 - type: integer + Parameter C_HAS_MEM_OUTPUT_REGS_B bound to: 0 - type: integer + Parameter C_HAS_MUX_OUTPUT_REGS_A bound to: 0 - type: integer + Parameter C_HAS_MUX_OUTPUT_REGS_B bound to: 0 - type: integer + Parameter C_MUX_PIPELINE_STAGES bound to: 0 - type: integer + Parameter C_HAS_SOFTECC_INPUT_REGS_A bound to: 0 - type: integer + Parameter C_HAS_SOFTECC_OUTPUT_REGS_B bound to: 0 - type: integer + Parameter C_USE_SOFTECC bound to: 0 - type: integer + Parameter C_USE_ECC bound to: 0 - type: integer + Parameter C_EN_ECC_PIPE bound to: 0 - type: integer + Parameter C_READ_LATENCY_A bound to: 1 - type: integer + Parameter C_READ_LATENCY_B bound to: 1 - type: integer + Parameter C_HAS_INJECTERR bound to: 0 - type: integer + Parameter C_SIM_COLLISION_CHECK bound to: ALL - type: string + Parameter C_COMMON_CLK bound to: 0 - type: integer + Parameter C_DISABLE_WARN_BHV_COLL bound to: 0 - type: integer + Parameter C_EN_SLEEP_PIN bound to: 0 - type: integer + Parameter C_USE_URAM bound to: 0 - type: integer + Parameter C_EN_RDADDRA_CHG bound to: 0 - type: integer + Parameter C_EN_RDADDRB_CHG bound to: 0 - type: integer + Parameter C_EN_DEEPSLEEP_PIN bound to: 0 - type: integer + Parameter C_EN_SHUTDOWN_PIN bound to: 0 - type: integer + Parameter C_EN_SAFETY_CKT bound to: 0 - type: integer + Parameter C_DISABLE_WARN_BHV_RANGE bound to: 0 - type: integer + Parameter C_COUNT_36K_BRAM bound to: 0 - type: string + Parameter C_COUNT_18K_BRAM bound to: 1 - type: string + Parameter C_EST_POWER_SUMMARY bound to: Estimated Power for IP : 2.5016 mW - type: string +INFO: [Synth 8-3491] module 'blk_mem_gen_v8_4_3' declared at '/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/rom_freq_word/hdl/blk_mem_gen_v8_4_vhsyn_rfs.vhd:195321' bound to instance 'U0' of component 'blk_mem_gen_v8_4_3' [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/rom_freq_word/synth/rom_freq_word.vhd:230] +INFO: [Synth 8-256] done synthesizing module 'rom_freq_word' (9#1) [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/rom_freq_word/synth/rom_freq_word.vhd:67] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port SSRA +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port CLKB +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port SSRB +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ENB +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port REGCEB +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port WEB[0] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[8] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[7] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[6] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[5] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[4] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[3] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[2] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[1] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[0] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[35] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[34] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[33] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[32] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[31] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[30] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[29] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[28] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[27] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[26] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[25] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[24] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[23] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[22] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[21] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[20] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[19] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[18] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[17] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[16] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[15] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[14] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[13] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[12] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[11] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[10] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[9] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[8] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[7] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[6] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[5] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[4] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[3] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[2] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[1] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[0] +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port SLEEP +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port INJECTSBITERR +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port INJECTDBITERR +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ECCPIPECE +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ram_rstram_b +WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ram_rstreg_b +WARNING: [Synth 8-3331] design blk_mem_gen_generic_cstr has unconnected port RSTA[0] +WARNING: [Synth 8-3331] design blk_mem_gen_generic_cstr has unconnected port WEA[1] +WARNING: [Synth 8-3331] design blk_mem_gen_generic_cstr has unconnected port REGCEB[0] +WARNING: [Synth 8-3331] design blk_mem_gen_generic_cstr has unconnected port WEB[1] +WARNING: [Synth 8-3331] design blk_mem_gen_generic_cstr has unconnected port INJECTSBITERR +WARNING: [Synth 8-3331] design blk_mem_gen_generic_cstr has unconnected port INJECTDBITERR +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port CLKB +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[10] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[9] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[8] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[7] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[6] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[5] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[4] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[3] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[2] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[1] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[0] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port SBITERR_I +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DBITERR_I +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[6] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[5] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[4] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[3] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[2] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[1] +WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[0] +WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port RSTA +WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port ENA +WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port REGCEA +WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port WEA[0] +WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port DINA[10] +WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port DINA[9] +WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port DINA[8] +WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port DINA[7] +WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port DINA[6] +WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port DINA[5] +WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port DINA[4] +WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port DINA[3] +WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port DINA[2] +WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port DINA[1] +WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port DINA[0] +WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port CLKB +INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:27 ; elapsed = 00:00:32 . Memory (MB): peak = 2071.281 ; gain = 369.367 ; free physical = 3720 ; free virtual = 46728 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:27 ; elapsed = 00:00:32 . Memory (MB): peak = 2080.188 ; gain = 378.273 ; free physical = 3723 ; free virtual = 46730 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:27 ; elapsed = 00:00:32 . Memory (MB): peak = 2080.188 ; gain = 378.273 ; free physical = 3723 ; free virtual = 46730 +--------------------------------------------------------------------------------- +INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/rom_freq_word/rom_freq_word_ooc.xdc] for cell 'U0' +Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/rom_freq_word/rom_freq_word_ooc.xdc] for cell 'U0' +Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/dont_touch.xdc] +Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/dont_touch.xdc] +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2150.156 ; gain = 0.000 ; free physical = 3640 ; free virtual = 46647 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2150.156 ; gain = 0.000 ; free physical = 3639 ; free virtual = 46646 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 2150.156 ; gain = 448.242 ; free physical = 3713 ; free virtual = 46720 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7z100ffg900-2 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 2150.156 ; gain = 448.242 ; free physical = 3713 ; free virtual = 46720 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +Applied set_property DONT_TOUCH = true for U0. (constraint file /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/dont_touch.xdc, line 9). +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 2150.156 ; gain = 448.242 ; free physical = 3713 ; free virtual = 46720 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 2150.156 ; gain = 448.242 ; free physical = 3715 ; free virtual = 46723 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 2020 (col length:140) +BRAMs: 1510 (col length: RAMB18 140 RAMB36 70) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 2150.156 ; gain = 448.242 ; free physical = 3713 ; free virtual = 46727 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2150.156 ; gain = 448.242 ; free physical = 3602 ; free virtual = 46616 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2150.156 ; gain = 448.242 ; free physical = 3602 ; free virtual = 46616 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2150.156 ; gain = 448.242 ; free physical = 3596 ; free virtual = 46611 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 2150.156 ; gain = 448.242 ; free physical = 3607 ; free virtual = 46623 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 2150.156 ; gain = 448.242 ; free physical = 3607 ; free virtual = 46623 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 2150.156 ; gain = 448.242 ; free physical = 3607 ; free virtual = 46623 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 2150.156 ; gain = 448.242 ; free physical = 3607 ; free virtual = 46623 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 2150.156 ; gain = 448.242 ; free physical = 3607 ; free virtual = 46623 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 2150.156 ; gain = 448.242 ; free physical = 3607 ; free virtual = 46623 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+---------+------+ +| |Cell |Count | ++------+---------+------+ +|1 |RAMB18E1 | 1| ++------+---------+------+ + +Report Instance Areas: ++------+---------------------------------------------+------------------------------+------+ +| |Instance |Module |Cells | ++------+---------------------------------------------+------------------------------+------+ +|1 |top | | 1| +|2 | U0 |blk_mem_gen_v8_4_3 | 1| +|3 | inst_blk_mem_gen |blk_mem_gen_v8_4_3_synth | 1| +|4 | \gnbram.gnativebmg.native_blk_mem_gen |blk_mem_gen_top | 1| +|5 | \valid.cstr |blk_mem_gen_generic_cstr | 1| +|6 | \ramloop[0].ram.r |blk_mem_gen_prim_width | 1| +|7 | \prim_init.ram |blk_mem_gen_prim_wrapper_init | 1| ++------+---------------------------------------------+------------------------------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 2150.156 ; gain = 448.242 ; free physical = 3607 ; free virtual = 46623 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 164 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:31 ; elapsed = 00:00:36 . Memory (MB): peak = 2150.156 ; gain = 378.273 ; free physical = 3661 ; free virtual = 46677 +Synthesis Optimization Complete : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 2150.156 ; gain = 448.242 ; free physical = 3661 ; free virtual = 46677 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2150.156 ; gain = 0.000 ; free physical = 3602 ; free virtual = 46618 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Common 17-83] Releasing license: Synthesis +17 Infos, 100 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:40 . Memory (MB): peak = 2150.156 ; gain = 755.176 ; free physical = 3689 ; free virtual = 46705 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2150.156 ; gain = 0.000 ; free physical = 3689 ; free virtual = 46705 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word.dcp' has been generated. +WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. +INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP rom_freq_word, cache-ID = 0789e4a10aba5413 +INFO: [Coretcl 2-1174] Renamed 6 cell refs. +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2150.156 ; gain = 0.000 ; free physical = 3681 ; free virtual = 46697 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file rom_freq_word_utilization_synth.rpt -pb rom_freq_word_utilization_synth.pb +INFO: [Common 17-206] Exiting Vivado at Mon May 8 18:56:10 2023... diff --git a/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_sim_netlist.v b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_sim_netlist.v new file mode 100644 index 00000000..54bf9fd2 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:ee77aa9f5f241d950e00888da443f80b8cee570bf6d9cdbc74f9dc67dbacb994 +size 28824 diff --git a/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_sim_netlist.vhdl b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_sim_netlist.vhdl new file mode 100644 index 00000000..4360a2e5 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:1e0611322da5d005a87134e1c1c1dc2480c3dce787dd976b1d92348a3ba5286c +size 42610 diff --git a/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.v b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.v new file mode 100644 index 00000000..3acbc634 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.v @@ -0,0 +1,22 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Mon May 8 18:56:10 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub +// /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.v +// Design : rom_freq_word +// Purpose : Stub declaration of top-level module interface +// Device : xc7z100ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "blk_mem_gen_v8_4_3,Vivado 2019.1.3" *) +module rom_freq_word(clka, addra, douta) +/* synthesis syn_black_box black_box_pad_pin="clka,addra[6:0],douta[10:0]" */; + input clka; + input [6:0]addra; + output [10:0]douta; +endmodule diff --git a/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.vhdl b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.vhdl new file mode 100644 index 00000000..fc4a414f --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.vhdl @@ -0,0 +1,32 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Mon May 8 18:56:10 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.vhdl +-- Design : rom_freq_word +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity rom_freq_word is + Port ( + clka : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR ( 6 downto 0 ); + douta : out STD_LOGIC_VECTOR ( 10 downto 0 ) + ); + +end rom_freq_word; + +architecture stub of rom_freq_word is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clka,addra[6:0],douta[10:0]"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_3,Vivado 2019.1.3"; +begin +end; diff --git a/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_utilization_synth.pb b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_utilization_synth.pb new file mode 100644 index 00000000..343f2870 Binary files /dev/null and b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_utilization_synth.pb differ diff --git a/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_utilization_synth.rpt b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_utilization_synth.rpt new file mode 100644 index 00000000..73c82509 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_utilization_synth.rpt @@ -0,0 +1,175 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +| Date : Mon May 8 18:56:10 2023 +| Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +| Command : report_utilization -file rom_freq_word_utilization_synth.rpt -pb rom_freq_word_utilization_synth.pb +| Design : rom_freq_word +| Device : 7z100ffg900-2 +| Design State : Synthesized +--------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs* | 0 | 0 | 277400 | 0.00 | +| LUT as Logic | 0 | 0 | 277400 | 0.00 | +| LUT as Memory | 0 | 0 | 108200 | 0.00 | +| Slice Registers | 0 | 0 | 554800 | 0.00 | +| Register as Flip Flop | 0 | 0 | 554800 | 0.00 | +| Register as Latch | 0 | 0 | 554800 | 0.00 | +| F7 Muxes | 0 | 0 | 138700 | 0.00 | +| F8 Muxes | 0 | 0 | 69350 | 0.00 | ++-------------------------+------+-------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 0 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++-------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------+------+-------+-----------+-------+ +| Block RAM Tile | 0.5 | 0 | 755 | 0.07 | +| RAMB36/FIFO* | 0 | 0 | 755 | 0.00 | +| RAMB18 | 1 | 0 | 1510 | 0.07 | +| RAMB18E1 only | 1 | | | | ++-------------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 2020 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 0 | 0 | 362 | 0.00 | +| Bonded IPADs | 0 | 0 | 50 | 0.00 | +| Bonded OPADs | 0 | 0 | 32 | 0.00 | +| Bonded IOPADs | 0 | 0 | 130 | 0.00 | +| PHY_CONTROL | 0 | 0 | 8 | 0.00 | +| PHASER_REF | 0 | 0 | 8 | 0.00 | +| OUT_FIFO | 0 | 0 | 32 | 0.00 | +| IN_FIFO | 0 | 0 | 32 | 0.00 | +| IDELAYCTRL | 0 | 0 | 8 | 0.00 | +| IBUFDS | 0 | 0 | 348 | 0.00 | +| GTXE2_COMMON | 0 | 0 | 4 | 0.00 | +| GTXE2_CHANNEL | 0 | 0 | 16 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 32 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 32 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 400 | 0.00 | +| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 | +| IBUFDS_GTE2 | 0 | 0 | 8 | 0.00 | +| ILOGIC | 0 | 0 | 362 | 0.00 | +| OLOGIC | 0 | 0 | 362 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 0 | 0 | 32 | 0.00 | +| BUFIO | 0 | 0 | 32 | 0.00 | +| MMCME2_ADV | 0 | 0 | 8 | 0.00 | +| PLLE2_ADV | 0 | 0 | 8 | 0.00 | +| BUFMRCE | 0 | 0 | 16 | 0.00 | +| BUFHCE | 0 | 0 | 168 | 0.00 | +| BUFR | 0 | 0 | 32 | 0.00 | ++------------+------+-------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +7. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| RAMB18E1 | 1 | Block Memory | ++----------+------+---------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_null_phase_synth_1/rundef.js b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rundef.js similarity index 90% rename from projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_null_phase_synth_1/rundef.js rename to projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rundef.js index b6ac5005..f8e5a2e8 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_null_phase_synth_1/rundef.js +++ b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rundef.js @@ -27,7 +27,7 @@ eval( EAInclude(ISEJScriptLib) ); ISEStep( "vivado", - "-log vio_null_phase.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_null_phase.tcl" ); + "-log rom_freq_word.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source rom_freq_word.tcl" ); diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_dmf_invert_prbs7_deci8_synth_1/runme.bat b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/runme.bat similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_dmf_invert_prbs7_deci8_synth_1/runme.bat rename to projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/runme.bat diff --git a/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/runme.sh b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/runme.sh new file mode 100755 index 00000000..5fc368be --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/runme.sh @@ -0,0 +1,39 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# + +if [ -z "$PATH" ]; then + PATH=/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2019.1/bin +else + PATH=/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2019.1/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +EAStep vivado -log rom_freq_word.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source rom_freq_word.tcl diff --git a/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/vivado.pb b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/vivado.pb new file mode 100644 index 00000000..1aaa1dab Binary files /dev/null and b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/vivado.pb differ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_hop_data_synth_1/.Vivado_Synthesis.queue.rst b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/.Vivado_Synthesis.queue.rst similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_hop_data_synth_1/.Vivado_Synthesis.queue.rst rename to projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/.Vivado_Synthesis.queue.rst diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_null_phase_synth_1/.vivado.begin.rst b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/.vivado.begin.rst similarity index 75% rename from projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_null_phase_synth_1/.vivado.begin.rst rename to projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/.vivado.begin.rst index 46840cc8..5477b9b4 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_null_phase_synth_1/.vivado.begin.rst +++ b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/.vivado.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_hop_data_synth_1/.vivado.end.rst b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/.vivado.end.rst similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_hop_data_synth_1/.vivado.end.rst rename to projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/.vivado.end.rst diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_hop_data_synth_1/ISEWrap.js b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/ISEWrap.js similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_hop_data_synth_1/ISEWrap.js rename to projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/ISEWrap.js diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_hop_data_synth_1/ISEWrap.sh b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/ISEWrap.sh similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_hop_data_synth_1/ISEWrap.sh rename to projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/ISEWrap.sh diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_hop_data_synth_1/__synthesis_is_complete__ b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/__synthesis_is_complete__ similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_hop_data_synth_1/__synthesis_is_complete__ rename to projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/__synthesis_is_complete__ diff --git a/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/gen_run.xml b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/gen_run.xml new file mode 100644 index 00000000..da0b2271 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/gen_run.xml @@ -0,0 +1,59 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_dmf_invert_prbs7_deci8_synth_1/htr.txt b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/htr.txt similarity index 64% rename from projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_dmf_invert_prbs7_deci8_synth_1/htr.txt rename to projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/htr.txt index 04308aeb..998ecb35 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_dmf_invert_prbs7_deci8_synth_1/htr.txt +++ b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/htr.txt @@ -6,4 +6,4 @@ # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. # -vivado -log fir_dmf_invert_prbs7_deci8.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source fir_dmf_invert_prbs7_deci8.tcl +vivado -log vio_manual_ctrl.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_manual_ctrl.tcl diff --git a/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/project.wdf b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/project.wdf new file mode 100644 index 00000000..68d10e56 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/project.wdf @@ -0,0 +1,37 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:3130:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:33:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:33:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:74727565:00:00 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+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3130:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3130:00:00 +5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3665393633363431666561663437633339616462383862306139303537636232:506172656e742050412070726f6a656374204944:00 +eof:1725321426 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_dmf_invert_prbs7_deci8_synth_1/rundef.js b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/rundef.js similarity index 89% rename from projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_dmf_invert_prbs7_deci8_synth_1/rundef.js rename to projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/rundef.js index 6ecc369e..33a47a99 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_dmf_invert_prbs7_deci8_synth_1/rundef.js +++ b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/rundef.js @@ -27,7 +27,7 @@ eval( EAInclude(ISEJScriptLib) ); ISEStep( "vivado", - "-log fir_dmf_invert_prbs7_deci8.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source fir_dmf_invert_prbs7_deci8.tcl" ); + "-log vio_manual_ctrl.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_manual_ctrl.tcl" ); diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_hop_data_synth_1/runme.bat b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/runme.bat similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_hop_data_synth_1/runme.bat rename to projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/runme.bat diff --git a/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/runme.sh b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/runme.sh new file mode 100755 index 00000000..a2412a07 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/runme.sh @@ -0,0 +1,39 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# + +if [ -z "$PATH" ]; then + PATH=/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2019.1/bin +else + PATH=/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2019.1/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +EAStep vivado -log vio_manual_ctrl.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_manual_ctrl.tcl diff --git a/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.dcp b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.dcp new file mode 100644 index 00000000..dcc3e3bd --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:126e2b8371bf84e12573a21740ebe52096d272c63293f528f35f6a48b1c9c3b2 +size 145343 diff --git a/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.tcl b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.tcl new file mode 100644 index 00000000..33a0aa85 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.tcl @@ -0,0 +1,155 @@ +# +# Synthesis run script generated by Vivado +# + +set TIME_start [clock seconds] +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +set_param simulator.modelsimInstallPath /home/josh/Software/Mentor/modeltech/bin +set_param simulator.vcsmxInstallPath /usr/synopsys/vcs/T-2022.06/bin +set_param project.vivado.isBlockSynthRun true +set_msg_config -msgmgr_mode ooc_run +create_project -in_memory -part xc7z100ffg900-2 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info +set_property webtalk.parent_dir /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/wt [current_project] +set_property parent.project_path /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.xpr [current_project] +set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language Verilog [current_project] +set_property ip_output_repo /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +read_ip -quiet /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/vio_manual_ctrl/vio_manual_ctrl.xci +set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/vio_manual_ctrl/vio_manual_ctrl.xdc] +set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/vio_manual_ctrl/vio_manual_ctrl_ooc.xdc] + +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +set_param ips.enableIPCacheLiteLoad 1 + +set cached_ip [config_ip_cache -export -no_bom -dir /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1 -new_name vio_manual_ctrl -ip [get_ips vio_manual_ctrl]] + +if { $cached_ip eq {} } { +close [open __synthesis_is_running__ w] + +synth_design -top vio_manual_ctrl -part xc7z100ffg900-2 -mode out_of_context + +#--------------------------------------------------------- +# Generate Checkpoint/Stub/Simulation Files For IP Cache +#--------------------------------------------------------- +# disable binary constraint mode for IPCache checkpoints +set_param constraints.enableBinaryConstraints false + +catch { + write_checkpoint -force -noxdef -rename_prefix vio_manual_ctrl_ vio_manual_ctrl.dcp + + set ipCachedFiles {} + write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_manual_ctrl_stub.v + lappend ipCachedFiles vio_manual_ctrl_stub.v + + write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_manual_ctrl_stub.vhdl + lappend ipCachedFiles vio_manual_ctrl_stub.vhdl + + write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_manual_ctrl_sim_netlist.v + lappend ipCachedFiles vio_manual_ctrl_sim_netlist.v + + write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_manual_ctrl_sim_netlist.vhdl + lappend ipCachedFiles vio_manual_ctrl_sim_netlist.vhdl +set TIME_taken [expr [clock seconds] - $TIME_start] + + config_ip_cache -add -dcp vio_manual_ctrl.dcp -move_files $ipCachedFiles -use_project_ipc -synth_runtime $TIME_taken -ip [get_ips vio_manual_ctrl] +} + +rename_ref -prefix_all vio_manual_ctrl_ + +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef vio_manual_ctrl.dcp +create_report "vio_manual_ctrl_synth_1_synth_report_utilization_0" "report_utilization -file vio_manual_ctrl_utilization_synth.rpt -pb vio_manual_ctrl_utilization_synth.pb" + +if { [catch { + write_verilog -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + write_vhdl -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + write_verilog -force -mode funcsim /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + +if { [catch { + write_vhdl -force -mode funcsim /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + + +} else { + + +}; # end if cached_ip + +add_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/vio_manual_ctrl/vio_manual_ctrl.xci] + +add_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/vio_manual_ctrl/vio_manual_ctrl.xci] + +add_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/vio_manual_ctrl/vio_manual_ctrl.xci] + +add_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/vio_manual_ctrl/vio_manual_ctrl.xci] + +add_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.dcp -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/vio_manual_ctrl/vio_manual_ctrl.xci] + +if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/vio_manual_ctrl]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.v /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/vio_manual_ctrl + } +} + +if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/vio_manual_ctrl]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.vhdl /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/vio_manual_ctrl + } +} + +if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/vio_manual_ctrl]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.v /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/vio_manual_ctrl + } +} + +if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/vio_manual_ctrl]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.vhdl /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/vio_manual_ctrl + } +} +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] diff --git a/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.vds b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.vds new file mode 100644 index 00000000..c99630a3 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.vds @@ -0,0 +1,574 @@ +#----------------------------------------------------------- +# Vivado v2019.1.3 (64-bit) +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 +# Start of session at: Mon May 8 17:55:43 2023 +# Process ID: 2601945 +# Current directory: /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1 +# Command line: vivado -log vio_manual_ctrl.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_manual_ctrl.tcl +# Log file: /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.vds +# Journal file: /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vivado.jou +#----------------------------------------------------------- +source vio_manual_ctrl.tcl -notrace +Command: synth_design -top vio_manual_ctrl -part xc7z100ffg900-2 -mode out_of_context +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7z100' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z100' +INFO: [Device 21-403] Loading part xc7z100ffg900-2 +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 2602036 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 1860.445 ; gain = 150.688 ; free physical = 550 ; free virtual = 42199 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'vio_manual_ctrl' [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/vio_manual_ctrl/synth/vio_manual_ctrl.v:59] +WARNING: [Synth 8-3848] Net sl_iport0 in module/entity vio_manual_ctrl does not have driver. [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/vio_manual_ctrl/synth/vio_manual_ctrl.v:79] +INFO: [Synth 8-6155] done synthesizing module 'vio_manual_ctrl' (7#1) [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/vio_manual_ctrl/synth/vio_manual_ctrl.v:59] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Read +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[15] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[14] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[13] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[12] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[11] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[10] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[9] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[8] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[7] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[6] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[5] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[4] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Internal_cnt_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Read +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[15] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[14] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[13] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[12] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[11] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[10] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[9] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[8] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[7] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[6] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[5] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[4] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[3] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[2] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Internal_cnt_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Read +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[15] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[14] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[13] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[12] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[11] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[10] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[9] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[8] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[7] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[6] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[5] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[4] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[3] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[2] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[1] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Internal_cnt_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Read +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[15] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[14] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[13] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[12] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[11] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[10] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[9] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[8] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[7] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[6] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[5] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[4] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[3] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Internal_cnt_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in0[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in1[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in2[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in3[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in4[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in5[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in6[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in7[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in8[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in9[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in10[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in11[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in12[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in13[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in14[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in15[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in16[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in17[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in18[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in19[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in20[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in21[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in22[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in23[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in24[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in25[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in26[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in27[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in28[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in29[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in30[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in31[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in32[0] +INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1922.133 ; gain = 212.375 ; free physical = 654 ; free virtual = 42213 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1926.102 ; gain = 216.344 ; free physical = 646 ; free virtual = 42206 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1926.102 ; gain = 216.344 ; free physical = 646 ; free virtual = 42205 +--------------------------------------------------------------------------------- +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/vio_manual_ctrl/vio_manual_ctrl_ooc.xdc] +Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/vio_manual_ctrl/vio_manual_ctrl_ooc.xdc] +Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/vio_manual_ctrl/vio_manual_ctrl.xdc] +Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/vio_manual_ctrl/vio_manual_ctrl.xdc] +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2099.789 ; gain = 0.000 ; free physical = 1133 ; free virtual = 42662 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2105.727 ; gain = 5.938 ; free physical = 1130 ; free virtual = 42659 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2105.727 ; gain = 395.969 ; free physical = 1217 ; free virtual = 42714 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7z100ffg900-2 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2105.727 ; gain = 395.969 ; free physical = 1217 ; free virtual = 42714 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2105.727 ; gain = 395.969 ; free physical = 1219 ; free virtual = 42715 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2105.727 ; gain = 395.969 ; free physical = 1209 ; free virtual = 42706 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 2 Input 2 Bit Adders := 2 ++---Registers : + 128 Bit Registers := 1 + 32 Bit Registers := 1 + 16 Bit Registers := 13 + 9 Bit Registers := 1 + 7 Bit Registers := 1 + 5 Bit Registers := 1 + 4 Bit Registers := 1 + 3 Bit Registers := 4 + 2 Bit Registers := 3 + 1 Bit Registers := 18 ++---Muxes : + 2 Input 16 Bit Muxes := 3 + 3 Input 9 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 10 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +Module vio_v3_0_20_probe_out_one +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 + 3 Bit Registers := 1 ++---Muxes : + 2 Input 1 Bit Muxes := 1 +Module vio_v3_0_20_probe_out_one__parameterized0 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 + 1 Bit Registers := 1 ++---Muxes : + 2 Input 1 Bit Muxes := 1 +Module vio_v3_0_20_probe_out_one__parameterized1 +Detailed RTL Component Info : ++---Adders : + 2 Input 2 Bit Adders := 1 ++---Registers : + 32 Bit Registers := 1 + 16 Bit Registers := 3 + 2 Bit Registers := 1 ++---Muxes : + 2 Input 16 Bit Muxes := 1 +Module vio_v3_0_20_probe_out_one__parameterized2 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 + 2 Bit Registers := 1 ++---Muxes : + 2 Input 1 Bit Muxes := 1 +Module vio_v3_0_20_probe_out_one__parameterized3 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 + 4 Bit Registers := 1 ++---Muxes : + 2 Input 1 Bit Muxes := 1 +Module vio_v3_0_20_probe_out_all +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 + 3 Bit Registers := 1 + 1 Bit Registers := 7 ++---Muxes : + 2 Input 1 Bit Muxes := 2 +Module vio_v3_0_20_probe_width +Detailed RTL Component Info : ++---Adders : + 2 Input 2 Bit Adders := 1 ++---Registers : + 9 Bit Registers := 1 + 2 Bit Registers := 1 ++---Muxes : + 3 Input 9 Bit Muxes := 1 +Module xsdbs_v1_0_2_xsdbs +Detailed RTL Component Info : ++---Registers : + 128 Bit Registers := 1 + 16 Bit Registers := 2 + 1 Bit Registers := 1 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 1 +Module vio_v3_0_20_decoder +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 2 + 7 Bit Registers := 1 + 5 Bit Registers := 1 + 3 Bit Registers := 2 + 1 Bit Registers := 9 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 3 +Module vio_v3_0_20_vio +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 2020 (col length:140) +BRAMs: 1510 (col length: RAMB18 140 RAMB36 70) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[6]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[6]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[6]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[6]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[7]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[7]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[7]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[7]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[8]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[8]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[8]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[8]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[10]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[10]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[10]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[10]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[11]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[11]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[11]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[11]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[12]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[12]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[12]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[12]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[13]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[13]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[13]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[13]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[14]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[14]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[14]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[14]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[15]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[15]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[15]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[15]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[2]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[3]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[4]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[8]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[5]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[6]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[6]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[7]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_WIDTH_INST/probe_width_int_reg[7] ) +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2105.727 ; gain = 395.969 ; free physical = 1145 ; free virtual = 42646 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2105.727 ; gain = 395.969 ; free physical = 1153 ; free virtual = 42653 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2105.727 ; gain = 395.969 ; free physical = 1146 ; free virtual = 42647 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2105.727 ; gain = 395.969 ; free physical = 1142 ; free virtual = 42642 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[36] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[35] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[34] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[33] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[32] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[31] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[30] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[29] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[28] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[27] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[26] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[25] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[24] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[23] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[22] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[21] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[20] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[19] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[18] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[17] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[16] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[15] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[14] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[13] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[12] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[11] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[10] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[9] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[8] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[7] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[6] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[5] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[4] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[3] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[2] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[1] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[0] to constant 0 +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2105.727 ; gain = 395.969 ; free physical = 1154 ; free virtual = 42655 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2105.727 ; gain = 395.969 ; free physical = 1154 ; free virtual = 42655 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2105.727 ; gain = 395.969 ; free physical = 1154 ; free virtual = 42655 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2105.727 ; gain = 395.969 ; free physical = 1154 ; free virtual = 42655 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2105.727 ; gain = 395.969 ; free physical = 1154 ; free virtual = 42655 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2105.727 ; gain = 395.969 ; free physical = 1154 ; free virtual = 42655 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+-----+------+ +| |Cell |Count | ++------+-----+------+ +|1 |LUT2 | 7| +|2 |LUT3 | 59| +|3 |LUT4 | 10| +|4 |LUT5 | 25| +|5 |LUT6 | 82| +|6 |FDRE | 350| +|7 |FDSE | 6| ++------+-----+------+ + +Report Instance Areas: ++------+---------------------------------------+------------------------------------------+------+ +| |Instance |Module |Cells | ++------+---------------------------------------+------------------------------------------+------+ +|1 |top | | 539| +|2 | inst |vio_v3_0_20_vio | 539| +|3 | U_XSDB_SLAVE |xsdbs_v1_0_2_xsdbs | 248| +|4 | DECODER_INST |vio_v3_0_20_decoder | 82| +|5 | PROBE_OUT_ALL_INST |vio_v3_0_20_probe_out_all | 183| +|6 | \G_PROBE_OUT[0].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one | 9| +|7 | \G_PROBE_OUT[1].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized0 | 3| +|8 | \G_PROBE_OUT[2].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized1 | 104| +|9 | \G_PROBE_OUT[3].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized2 | 6| +|10 | \G_PROBE_OUT[4].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized3 | 8| +|11 | PROBE_OUT_WIDTH_INST |vio_v3_0_20_probe_width | 10| ++------+---------------------------------------+------------------------------------------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2105.727 ; gain = 395.969 ; free physical = 1154 ; free virtual = 42655 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 293 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 2105.727 ; gain = 216.344 ; free physical = 1213 ; free virtual = 42714 +Synthesis Optimization Complete : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2105.727 ; gain = 395.969 ; free physical = 1229 ; free virtual = 42729 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2105.727 ; gain = 0.000 ; free physical = 1135 ; free virtual = 42636 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Common 17-83] Releasing license: Synthesis +72 Infos, 138 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 2105.727 ; gain = 706.809 ; free physical = 1185 ; free virtual = 42685 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2105.727 ; gain = 0.000 ; free physical = 1185 ; free virtual = 42685 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.dcp' has been generated. +WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. +INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP vio_manual_ctrl, cache-ID = af26366c91bcf19e +INFO: [Coretcl 2-1174] Renamed 10 cell refs. +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2129.738 ; gain = 0.000 ; free physical = 1203 ; free virtual = 42705 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file vio_manual_ctrl_utilization_synth.rpt -pb vio_manual_ctrl_utilization_synth.pb +INFO: [Common 17-206] Exiting Vivado at Mon May 8 17:56:01 2023... diff --git a/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.v b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.v new file mode 100644 index 00000000..c7abe00f --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:cb065d0eddb5b655bab77fb0852a87bb5011a810896d8e714356346485691606 +size 353149 diff --git a/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.vhdl b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.vhdl new file mode 100644 index 00000000..69476f18 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:ce8bf1803b3191b816081504adefaa817efc0507189277d23ceb58cfe1deba32 +size 635009 diff --git a/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.v b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.v new file mode 100644 index 00000000..4ca646b3 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.v @@ -0,0 +1,26 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Mon May 8 17:56:01 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub +// /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.v +// Design : vio_manual_ctrl +// Purpose : Stub declaration of top-level module interface +// Device : xc7z100ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "vio,Vivado 2019.1.3" *) +module vio_manual_ctrl(clk, probe_out0, probe_out1, probe_out2, + probe_out3, probe_out4) +/* synthesis syn_black_box black_box_pad_pin="clk,probe_out0[2:0],probe_out1[0:0],probe_out2[31:0],probe_out3[1:0],probe_out4[3:0]" */; + input clk; + output [2:0]probe_out0; + output [0:0]probe_out1; + output [31:0]probe_out2; + output [1:0]probe_out3; + output [3:0]probe_out4; +endmodule diff --git a/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.vhdl b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.vhdl new file mode 100644 index 00000000..7883d1ed --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.vhdl @@ -0,0 +1,35 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Mon May 8 17:56:01 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.vhdl +-- Design : vio_manual_ctrl +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity vio_manual_ctrl is + Port ( + clk : in STD_LOGIC; + probe_out0 : out STD_LOGIC_VECTOR ( 2 downto 0 ); + probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out2 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + probe_out3 : out STD_LOGIC_VECTOR ( 1 downto 0 ); + probe_out4 : out STD_LOGIC_VECTOR ( 3 downto 0 ) + ); + +end vio_manual_ctrl; + +architecture stub of vio_manual_ctrl is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk,probe_out0[2:0],probe_out1[0:0],probe_out2[31:0],probe_out3[1:0],probe_out4[3:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3"; +begin +end; diff --git a/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_utilization_synth.pb b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_utilization_synth.pb new file mode 100644 index 00000000..fba31ae8 Binary files /dev/null and b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_utilization_synth.pb differ diff --git a/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_utilization_synth.rpt b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_utilization_synth.rpt new file mode 100644 index 00000000..353de78c --- /dev/null +++ b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_utilization_synth.rpt @@ -0,0 +1,180 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +| Date : Mon May 8 17:56:01 2023 +| Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +| Command : report_utilization -file vio_manual_ctrl_utilization_synth.rpt -pb vio_manual_ctrl_utilization_synth.pb +| Design : vio_manual_ctrl +| Device : 7z100ffg900-2 +| Design State : Synthesized +------------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs* | 150 | 0 | 277400 | 0.05 | +| LUT as Logic | 150 | 0 | 277400 | 0.05 | +| LUT as Memory | 0 | 0 | 108200 | 0.00 | +| Slice Registers | 356 | 0 | 554800 | 0.06 | +| Register as Flip Flop | 356 | 0 | 554800 | 0.06 | +| Register as Latch | 0 | 0 | 554800 | 0.00 | +| F7 Muxes | 0 | 0 | 138700 | 0.00 | +| F8 Muxes | 0 | 0 | 69350 | 0.00 | ++-------------------------+------+-------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 6 | Yes | Set | - | +| 350 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 755 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 755 | 0.00 | +| RAMB18 | 0 | 0 | 1510 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 2020 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 0 | 0 | 362 | 0.00 | +| Bonded IPADs | 0 | 0 | 50 | 0.00 | +| Bonded OPADs | 0 | 0 | 32 | 0.00 | +| Bonded IOPADs | 0 | 0 | 130 | 0.00 | +| PHY_CONTROL | 0 | 0 | 8 | 0.00 | +| PHASER_REF | 0 | 0 | 8 | 0.00 | +| OUT_FIFO | 0 | 0 | 32 | 0.00 | +| IN_FIFO | 0 | 0 | 32 | 0.00 | +| IDELAYCTRL | 0 | 0 | 8 | 0.00 | +| IBUFDS | 0 | 0 | 348 | 0.00 | +| GTXE2_COMMON | 0 | 0 | 4 | 0.00 | +| GTXE2_CHANNEL | 0 | 0 | 16 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 32 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 32 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 400 | 0.00 | +| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 | +| IBUFDS_GTE2 | 0 | 0 | 8 | 0.00 | +| ILOGIC | 0 | 0 | 362 | 0.00 | +| OLOGIC | 0 | 0 | 362 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 0 | 0 | 32 | 0.00 | +| BUFIO | 0 | 0 | 32 | 0.00 | +| MMCME2_ADV | 0 | 0 | 8 | 0.00 | +| PLLE2_ADV | 0 | 0 | 8 | 0.00 | +| BUFMRCE | 0 | 0 | 16 | 0.00 | +| BUFHCE | 0 | 0 | 168 | 0.00 | +| BUFR | 0 | 0 | 32 | 0.00 | ++------------+------+-------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +7. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| FDRE | 350 | Flop & Latch | +| LUT6 | 82 | LUT | +| LUT3 | 59 | LUT | +| LUT5 | 25 | LUT | +| LUT4 | 10 | LUT | +| LUT2 | 7 | LUT | +| FDSE | 6 | Flop & Latch | ++----------+------+---------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vivado.pb b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vivado.pb new file mode 100644 index 00000000..3c75efdb Binary files /dev/null and b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vivado.pb differ diff --git a/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.xpr b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.xpr index 108f9e32..e793ad93 100644 --- a/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.xpr +++ b/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.xpr @@ -39,13 +39,13 @@