diff --git a/modules/xc7k410tffg900-2/var_cal/rtl/var_cal.v b/modules/xc7k410tffg900-2/var_cal/rtl/var_cal.v index 0bc0f9ca..0b67fa4d 100644 --- a/modules/xc7k410tffg900-2/var_cal/rtl/var_cal.v +++ b/modules/xc7k410tffg900-2/var_cal/rtl/var_cal.v @@ -19,7 +19,9 @@ // Dependencies: // // Revision: -// Revision 0.01 - File Created +// Revision 0.01 - File Created +// 20230730-1427 - 修改输入位宽小于乘法器位宽时的处理，由补零变为符号位扩展； +// 修改；修改累加和输出截位方式，依托原始数据位宽进行处理。 // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// @@ -30,7 +32,7 @@ module var_cal parameter ACCUM_NUM = 16384, parameter DATA_I_WIDTH = 30, parameter DATA_O_WIDTH = 32, - parameter CMPY_WIDTH = 18 + parameter CMPY_I_WIDTH = 18 ) ( input clk , @@ -50,11 +52,13 @@ module var_cal integer i; -localparam CMPY_VALID_WIDTH = CMPY_WIDTH-1; // 17-bit valid data to protect cmpy from overflow -localparam DATA_MULT_FULL_WIDTH = 2*CMPY_VALID_WIDTH+1; -localparam DATA_MULT_VALID_WIDTH = 2*CMPY_VALID_WIDTH; -localparam AXIS_DATA_I_WIDTH = 8*((CMPY_VALID_WIDTH-1)/8+1) ; // axis data width of input real/image data -localparam AXIS_DATA_P_WIDTH = 8*((DATA_MULT_FULL_WIDTH-1)/8+1); // axis data width of cmpy output real/image data +localparam CMPY_P_WIDTH = 2*CMPY_I_WIDTH+1; +localparam AXIS_CMPY_I_WIDTH = 8*((CMPY_I_WIDTH-1)/8+1) ; // axis data width of input real/image data +localparam AXIS_CMPY_P_WIDTH = 8*((CMPY_P_WIDTH-1)/8+1); // axis data width of cmpy output real/image data +localparam CMPY_P_VALID_WIDTH = (DATA_I_WIDTH > CMPY_I_WIDTH) ? 2*CMPY_I_WIDTH : 2*DATA_I_WIDTH; + + +localparam ACCUM_WIDTH = CMPY_P_VALID_WIDTH + $clog2(ACCUM_NUM); // status control reg cal_start_auto = 'b0; @@ -63,7 +67,7 @@ reg cal_start_d2 = 'b0; reg cal_busy_buf = 'b0; reg [$clog2(ACCUM_NUM)-1 : 0] cnt_accum = 'b0; reg last_data = 'b0; -reg last_data_d [0:6]; // 6 for cmpy, 1 for register output +reg [6:0] last_data_d = 'b0; // 1 for register input, 6 for cmpy, 1 for register output assign cal_busy = cal_busy_buf; assign var_valid = last_data_d[6]; @@ -73,11 +77,16 @@ always @(posedge clk) begin cal_start_auto <= 'b0; end else begin - if (~cal_busy_buf) begin - cal_start_auto = ~cal_start_auto; + if (cal_auto_en) begin + if (~cal_busy_buf) begin + cal_start_auto <= ~cal_start_auto; + end + else begin + cal_start_auto <= cal_start_auto; + end end else begin - cal_start_auto <= cal_start_auto; + cal_start_auto <= 'b0; end end end @@ -123,50 +132,72 @@ always @(posedge clk) begin end always @(posedge clk) begin - last_data_d[0] <= last_data; - - for (i = 0; i < 6; i = i + 1) begin - last_data_d[i+1] <= last_data_d[i]; + if (rst) begin + last_data_d[6:0] <= 'b0; + end + else begin + last_data_d[6:0] <= {last_data_d[5:0],last_data}; end end + // cmpy -wire [AXIS_DATA_I_WIDTH-1 : 0] cmpy_i_real; -wire [AXIS_DATA_I_WIDTH-1 : 0] cmpy_i_imag; -wire [AXIS_DATA_P_WIDTH-1 : 0] cmpy_p_raw_real; -wire [AXIS_DATA_P_WIDTH-1 : 0] cmpy_p_raw_imag; -wire [DATA_O_WIDTH-1 : 0] cmpy_p_real; -wire [DATA_O_WIDTH-1 : 0] cmpy_p_imag; +reg [AXIS_CMPY_I_WIDTH-1 : 0] cmpy_a_real = 'b0; +reg [AXIS_CMPY_I_WIDTH-1 : 0] cmpy_a_imag = 'b0; +reg [AXIS_CMPY_I_WIDTH-1 : 0] cmpy_b_real = 'b0; +reg [AXIS_CMPY_I_WIDTH-1 : 0] cmpy_b_imag = 'b0; +wire [AXIS_CMPY_P_WIDTH-1 : 0] cmpy_p_raw_real; +wire [AXIS_CMPY_P_WIDTH-1 : 0] cmpy_p_raw_imag; +wire [CMPY_P_VALID_WIDTH-1 : 0] cmpy_p_real; +wire [CMPY_P_VALID_WIDTH-1 : 0] cmpy_p_imag; -if (CMPY_WIDTH > DATA_I_WIDTH) begin - // append zeros - assign cmpy_i_real = {{(AXIS_DATA_I_WIDTH-CMPY_VALID_WIDTH){din_real[DATA_I_WIDTH-1]}},din_real,{(CMPY_VALID_WIDTH-DATA_I_WIDTH){1'b0}}}; - assign cmpy_i_imag = {{(AXIS_DATA_I_WIDTH-CMPY_VALID_WIDTH){din_imag[DATA_I_WIDTH-1]}},din_imag,{(CMPY_VALID_WIDTH-DATA_I_WIDTH){1'b0}}}; +if (CMPY_I_WIDTH > DATA_I_WIDTH) begin + // sign-bit extension to fit cmpy input data width + always @(posedge clk) begin + if (rst) begin + cmpy_a_real <= 'b0; + cmpy_a_imag <= 'b0; + cmpy_b_real <= 'b0; + cmpy_b_imag <= 'b0; + end + else begin + cmpy_a_real <= {{(AXIS_CMPY_I_WIDTH-DATA_I_WIDTH){din_real[DATA_I_WIDTH-1]}},din_real}; + cmpy_a_imag <= {{(AXIS_CMPY_I_WIDTH-DATA_I_WIDTH){din_imag[DATA_I_WIDTH-1]}},din_imag}; + cmpy_b_real <= {{(AXIS_CMPY_I_WIDTH-DATA_I_WIDTH){din_real[DATA_I_WIDTH-1]}},din_real}; + cmpy_b_imag <= (din_imag == {1'b1,{(DATA_I_WIDTH-1){1'b0}}}) ? {{(AXIS_CMPY_I_WIDTH-DATA_I_WIDTH+1){1'b0}},{(DATA_I_WIDTH-1){1'b1}}} : -{{(AXIS_CMPY_I_WIDTH-DATA_I_WIDTH){din_imag[DATA_I_WIDTH-1]}},din_imag}; + end + end end else begin // truncate msb - assign cmpy_i_real = {{(AXIS_DATA_I_WIDTH-CMPY_VALID_WIDTH){din_real[DATA_I_WIDTH-1]}},din_real[DATA_I_WIDTH-1 -: CMPY_VALID_WIDTH]}; - assign cmpy_i_imag = {{(AXIS_DATA_I_WIDTH-CMPY_VALID_WIDTH){din_imag[DATA_I_WIDTH-1]}},din_imag[DATA_I_WIDTH-1 -: CMPY_VALID_WIDTH]}; + always @(posedge clk) begin + if (rst) begin + cmpy_a_real <= 'b0; + cmpy_a_imag <= 'b0; + cmpy_b_real <= 'b0; + cmpy_b_imag <= 'b0; + end + else begin + cmpy_a_real <= {{(AXIS_CMPY_I_WIDTH-CMPY_I_WIDTH){din_real[DATA_I_WIDTH-1]}},din_real[DATA_I_WIDTH-1 -: CMPY_I_WIDTH]}; + cmpy_a_imag <= {{(AXIS_CMPY_I_WIDTH-CMPY_I_WIDTH){din_imag[DATA_I_WIDTH-1]}},din_imag[DATA_I_WIDTH-1 -: CMPY_I_WIDTH]}; + cmpy_b_real <= {{(AXIS_CMPY_I_WIDTH-CMPY_I_WIDTH){din_real[DATA_I_WIDTH-1]}},din_real[DATA_I_WIDTH-1 -: CMPY_I_WIDTH]}; + cmpy_b_imag <= (din_imag[DATA_I_WIDTH-1 -: CMPY_I_WIDTH] == {1'b1,{(CMPY_I_WIDTH-1){1'b0}}}) ? {{(AXIS_CMPY_I_WIDTH-CMPY_I_WIDTH+1){1'b0}},{(CMPY_I_WIDTH-1){1'b1}}} : -{{(AXIS_CMPY_I_WIDTH-CMPY_I_WIDTH){din_imag[DATA_I_WIDTH-1]}},din_imag[DATA_I_WIDTH-1 -: CMPY_I_WIDTH]}; + end + end end -if (DATA_O_WIDTH > DATA_MULT_VALID_WIDTH) begin - // append zeros - assign cmpy_p_real = {cmpy_p_raw_real[0 +: DATA_MULT_VALID_WIDTH],{(DATA_O_WIDTH-DATA_MULT_VALID_WIDTH){1'b0}}}; - assign cmpy_p_imag = {cmpy_p_raw_imag[0 +: DATA_MULT_VALID_WIDTH],{(DATA_O_WIDTH-DATA_MULT_VALID_WIDTH){1'b0}}}; -end -else begin - // truncate msb - assign cmpy_p_real = cmpy_p_raw_real[DATA_MULT_VALID_WIDTH-1 -: DATA_O_WIDTH]; - assign cmpy_p_imag = cmpy_p_raw_imag[DATA_MULT_VALID_WIDTH-1 -: DATA_O_WIDTH]; -end +// truncate valid bits +assign cmpy_p_real = cmpy_p_raw_real[0 +: CMPY_P_VALID_WIDTH]; +assign cmpy_p_imag = cmpy_p_raw_imag[0 +: CMPY_P_VALID_WIDTH]; -wire [2*AXIS_DATA_I_WIDTH-1:0] cmpy_a; -wire [2*AXIS_DATA_I_WIDTH-1:0] cmpy_b; -wire [2*AXIS_DATA_P_WIDTH-1:0] cmpy_p; + +wire [2*AXIS_CMPY_I_WIDTH-1:0] cmpy_a; +wire [2*AXIS_CMPY_I_WIDTH-1:0] cmpy_b; +wire [2*AXIS_CMPY_P_WIDTH-1:0] cmpy_p; wire cmpy_p_vld; -assign cmpy_a = {cmpy_i_imag,cmpy_i_real}; -assign cmpy_b = {-cmpy_i_imag,cmpy_i_real}; +assign cmpy_a = {cmpy_a_imag,cmpy_a_real}; +assign cmpy_b = {cmpy_b_imag,cmpy_b_real}; assign {cmpy_p_raw_imag,cmpy_p_raw_real} = cmpy_p; cmpy_18x18_mult u_cmpy_18x18 @@ -180,8 +211,9 @@ cmpy_18x18_mult u_cmpy_18x18 .m_axis_dout_tdata (cmpy_p ) // output wire [63 : 0] m_axis_dout_tdata ); + // accumulation -reg [DATA_O_WIDTH+$clog2(ACCUM_NUM) : 0] accum = 'b0; +reg [ACCUM_WIDTH-1 : 0] accum = 'b0; reg [DATA_O_WIDTH-1 : 0] var_buf = 'b0; assign var = var_buf; @@ -200,12 +232,26 @@ always @(posedge clk) begin end end -always @(posedge clk) begin - if (rst) begin - var_buf <= 'b0; +if (DATA_O_WIDTH > ACCUM_WIDTH) begin + // sign-bit extension to fit output data width + always @(posedge clk) begin + if (rst) begin + var_buf <= 'b0; + end + else if (last_data_d[5]) begin + var_buf <= {{(DATA_O_WIDTH-ACCUM_WIDTH){accum[ACCUM_WIDTH-1]}},accum}; + end end - else if (last_data_d[5]) begin - var_buf <= accum[DATA_O_WIDTH+$clog2(ACCUM_NUM) -: DATA_O_WIDTH]; +end +else begin + // truncate msb + always @(posedge clk) begin + if (rst) begin + var_buf <= 'b0; + end + else if (last_data_d[5]) begin + var_buf <= accum[ACCUM_WIDTH-1 -: DATA_O_WIDTH]; + end end end diff --git a/modules/xc7k410tffg900-2/var_cal/testbenches/tb_var_cal.v b/modules/xc7k410tffg900-2/var_cal/testbenches/tb_var_cal.v index 80de18a3..ac0519a3 100644 --- a/modules/xc7k410tffg900-2/var_cal/testbenches/tb_var_cal.v +++ b/modules/xc7k410tffg900-2/var_cal/testbenches/tb_var_cal.v @@ -22,7 +22,10 @@ module tb_var_cal; +localparam DATA_I_WIDTH = 30; + reg clk = 1'b1; +reg clk_init = 1'b1; reg rst = 1'b1; reg cal_start = 1'b0; @@ -30,13 +33,22 @@ reg cal_auto_en = 1'b0; wire cal_busy; reg din_valid = 1'b0; -reg [29:0] din_real = 'b0; -reg [29:0] din_imag = 'b0; +reg [29:0] din_file_real = 'b0; +reg [29:0] din_file_imag = 'b0; +wire [DATA_I_WIDTH-1:0] din_real; +wire [DATA_I_WIDTH-1:0] din_imag; + +assign din_real = din_file_real[29 -: DATA_I_WIDTH]; +assign din_imag = din_file_imag[29 -: DATA_I_WIDTH]; wire var_valid; wire [31:0] var; -var_cal u_var_cal +var_cal #( + .ACCUM_NUM (16384 ), + .DATA_I_WIDTH (DATA_I_WIDTH ), + .DATA_O_WIDTH (32 ) +) u_var_cal ( .clk (clk ), .rst (rst ), @@ -67,12 +79,16 @@ initial begin r_file = $fopen("./../../../../../testbenches/singletone.csv","r"); for (i = 0; i <= 32768; i = i + 1) begin @(posedge clk) - $fscanf(r_file,"%d,%d",din_real,din_imag); + $fscanf(r_file,"%d,%d",din_file_real,din_file_imag); end $fclose(r_file); $stop; end -always #10 clk = ~clk; +always #10 clk_init = ~clk_init; + +always @(posedge clk_init) begin + clk <= ~clk; +end endmodule diff --git a/projects/dl814_dj/dl814_dj_new_48m/constraints/z7100_ad9528_ad9371.xdc b/projects/dl814_dj/dl814_dj_new_48m/constraints/z7100_ad9528_ad9371.xdc index 9ef2d8eb..c5f789d0 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/constraints/z7100_ad9528_ad9371.xdc +++ b/projects/dl814_dj/dl814_dj_new_48m/constraints/z7100_ad9528_ad9371.xdc @@ -59,5 +59,5 @@ set_property -dict {PACKAGE_PIN V23 IOSTANDARD LVCMOS25} [get_ports hop_wor set_property -dict {PACKAGE_PIN W24 IOSTANDARD LVCMOS25} [get_ports freq_hop_switch ] # Sync Signal -# set_property -dict {PACKAGE_PIN AD19 IOSTANDARD LVCMOS25} [get_ports sync_signal_out ] ;# Bank9, not used before -# set_property -dict {PACKAGE_PIN AD18 IOSTANDARD LVCMOS25} [get_ports sync_gnd ] ;# Bank9, not used before \ No newline at end of file +set_property -dict {PACKAGE_PIN AD19 IOSTANDARD LVCMOS25} [get_ports sync_signal_out ] ;# Bank9, not used before +set_property -dict {PACKAGE_PIN AD18 IOSTANDARD LVCMOS25} [get_ports sync_gnd ] ;# Bank9, not used before \ No newline at end of file diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/coe/freq_word.coe b/projects/dl814_dj/dl814_dj_new_48m/ip/coe/freq_word.coe index 590747a4..20ed79a7 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/coe/freq_word.coe +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/coe/freq_word.coe @@ -1,83 +1,83 @@ MEMORY_INITIALIZATION_RADIX = 10; MEMORY_INITIALIZATION_VECTOR = -1624, -1611, -1598, -1585, -1572, -1559, -1546, -1533, -1520, -1507, -1494, -1481, -1468, -1455, -1442, -1429, -1416, -1403, -1390, -1377, -1364, -1351, -1338, -1325, -1312, -1299, -1286, -1273, -1260, -1247, -1234, -1221, -1208, -1195, -1182, -1169, -1156, -1143, -1130, -1117, -1104, -1091, -1078, -1065, -1052, -1039, -1026, -1013, -1000, -987, -974, -961, -948, -935, -922, -909, -896, -883, -870, -857, -844, -831, -818, -805, -792, -779, -766, -753, -740, -727, -714, -701, -688, -675, -662, -649, -636, -623, -610, -597, -584, +2124, +2111, +2098, +2085, +2072, +2059, +2046, +2033, +2020, +2007, +1994, +1981, +1968, +1955, +1942, +1929, +1916, +1903, +1890, +1877, +1864, +1851, +1838, +1825, +1812, +1799, +1786, +1773, +1760, +1747, +1734, +1721, +1708, +1695, +1682, +1669, +1656, +1643, +1630, +1617, +1604, +1591, +1578, +1565, +1552, +1539, +1526, +1513, +1500, +1487, +1474, +1461, +1448, +1435, +1422, +1409, +1396, +1383, +1370, +1357, +1344, +1331, +1318, +1305, +1292, +1279, +1266, +1253, +1240, +1227, +1214, +1201, +1188, +1175, +1162, +1149, +1136, +1123, +1110, +1097, +1084, diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/rom_freq_word/rom_freq_word.veo b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/rom_freq_word/rom_freq_word.veo index b92dae58..b925006b 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/rom_freq_word/rom_freq_word.veo +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/rom_freq_word/rom_freq_word.veo @@ -57,7 +57,7 @@ rom_freq_word your_instance_name ( .clka(clka), // input wire clka .addra(addra), // input wire [6 : 0] addra - .douta(douta) // output wire [10 : 0] douta + .douta(douta) // output wire [11 : 0] douta ); // INST_TAG_END ------ End INSTANTIATION Template --------- diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/rom_freq_word/rom_freq_word.vho b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/rom_freq_word/rom_freq_word.vho index ab09483f..8e5cfd80 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/rom_freq_word/rom_freq_word.vho +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/rom_freq_word/rom_freq_word.vho @@ -56,7 +56,7 @@ COMPONENT rom_freq_word PORT ( clka : IN STD_LOGIC; addra : IN STD_LOGIC_VECTOR(6 DOWNTO 0); - douta : OUT STD_LOGIC_VECTOR(10 DOWNTO 0) + douta : OUT STD_LOGIC_VECTOR(11 DOWNTO 0) ); END COMPONENT; -- COMP_TAG_END ------ End COMPONENT Declaration ------------ diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_sim_netlist.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_sim_netlist.v index 13c0897c..32ec870b 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_sim_netlist.v +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_sim_netlist.v @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:482fe668adab92087b21160a6d0e10fb3ffa2fc995638d5d08dd4a52b8409893 -size 28455 +oid sha256:1b6e74d5170c09b3c51111bd307f37e9ec527ade285f9da64d8b2b3e32070b27 +size 28801 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_sim_netlist.vhdl b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_sim_netlist.vhdl index 7611f3f6..5e879ca8 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_sim_netlist.vhdl +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_sim_netlist.vhdl @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:cd58c0a4fa0a7a6a3fcc40039a214c48be722a8e4f124787effaeb782108b146 -size 41688 +oid sha256:10778d6c1d2d23d93c6785c749bf15e581375d5e69edda1c0f7840bb8b7a928d +size 42530 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_stub.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_stub.v index 7a83bbe0..e44fe31b 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_stub.v +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_stub.v @@ -1,10 +1,10 @@ // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 -// Date : Mon May 8 18:56:10 2023 +// Date : Sun Jul 30 18:06:27 2023 // Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS -// Command : write_verilog -force -mode synth_stub -rename_top rom_freq_word -prefix -// rom_freq_word_ rom_freq_word_stub.v +// Command : write_verilog -force -mode synth_stub +// /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.v // Design : rom_freq_word // Purpose : Stub declaration of top-level module interface // Device : xc7z100ffg900-2 @@ -15,8 +15,8 @@ // Please paste the declaration into a Verilog source file or add the file as an additional source. (* x_core_info = "blk_mem_gen_v8_4_3,Vivado 2019.1.3" *) module rom_freq_word(clka, addra, douta) -/* synthesis syn_black_box black_box_pad_pin="clka,addra[6:0],douta[10:0]" */; +/* synthesis syn_black_box black_box_pad_pin="clka,addra[6:0],douta[11:0]" */; input clka; input [6:0]addra; - output [10:0]douta; + output [11:0]douta; endmodule diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_stub.vhdl b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_stub.vhdl index c8c7c48b..7fb2bf0b 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_stub.vhdl +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_stub.vhdl @@ -1,10 +1,10 @@ -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 --- Date : Mon May 8 18:56:10 2023 +-- Date : Sun Jul 30 18:06:27 2023 -- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS --- Command : write_vhdl -force -mode synth_stub -rename_top rom_freq_word -prefix --- rom_freq_word_ rom_freq_word_stub.vhdl +-- Command : write_vhdl -force -mode synth_stub +-- /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.vhdl -- Design : rom_freq_word -- Purpose : Stub declaration of top-level module interface -- Device : xc7z100ffg900-2 @@ -16,7 +16,7 @@ entity rom_freq_word is Port ( clka : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 6 downto 0 ); - douta : out STD_LOGIC_VECTOR ( 10 downto 0 ) + douta : out STD_LOGIC_VECTOR ( 11 downto 0 ) ); end rom_freq_word; @@ -25,7 +25,7 @@ architecture stub of rom_freq_word is attribute syn_black_box : boolean; attribute black_box_pad_pin : string; attribute syn_black_box of stub : architecture is true; -attribute black_box_pad_pin of stub : architecture is "clka,addra[6:0],douta[10:0]"; +attribute black_box_pad_pin of stub : architecture is "clka,addra[6:0],douta[11:0]"; attribute x_core_info : string; attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_3,Vivado 2019.1.3"; begin diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/rom_freq_word/sim/rom_freq_word.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/rom_freq_word/sim/rom_freq_word.v index bca88b77..370c963e 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/rom_freq_word/sim/rom_freq_word.v +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/rom_freq_word/sim/rom_freq_word.v @@ -65,7 +65,7 @@ input wire clka; input wire [6 : 0] addra; (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1" *) (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *) -output wire [10 : 0] douta; +output wire [11 : 0] douta; blk_mem_gen_v8_4_3 #( .C_FAMILY("zynq"), @@ -97,8 +97,8 @@ output wire [10 : 0] douta; .C_USE_BYTE_WEA(0), .C_WEA_WIDTH(1), .C_WRITE_MODE_A("WRITE_FIRST"), - .C_WRITE_WIDTH_A(11), - .C_READ_WIDTH_A(11), + .C_WRITE_WIDTH_A(12), + .C_READ_WIDTH_A(12), .C_WRITE_DEPTH_A(81), .C_READ_DEPTH_A(81), .C_ADDRA_WIDTH(7), @@ -111,8 +111,8 @@ output wire [10 : 0] douta; .C_USE_BYTE_WEB(0), .C_WEB_WIDTH(1), .C_WRITE_MODE_B("WRITE_FIRST"), - .C_WRITE_WIDTH_B(11), - .C_READ_WIDTH_B(11), + .C_WRITE_WIDTH_B(12), + .C_READ_WIDTH_B(12), .C_WRITE_DEPTH_B(81), .C_READ_DEPTH_B(81), .C_ADDRB_WIDTH(7), @@ -142,7 +142,7 @@ output wire [10 : 0] douta; .C_DISABLE_WARN_BHV_RANGE(0), .C_COUNT_36K_BRAM("0"), .C_COUNT_18K_BRAM("1"), - .C_EST_POWER_SUMMARY("Estimated Power for IP : 2.5016 mW") + .C_EST_POWER_SUMMARY("Estimated Power for IP : 2.5432 mW") ) inst ( .clka(clka), .rsta(1'D0), @@ -150,7 +150,7 @@ output wire [10 : 0] douta; .regcea(1'D0), .wea(1'B0), .addra(addra), - .dina(11'B0), + .dina(12'B0), .douta(douta), .clkb(1'D0), .rstb(1'D0), @@ -158,7 +158,7 @@ output wire [10 : 0] douta; .regceb(1'D0), .web(1'B0), .addrb(7'B0), - .dinb(11'B0), + .dinb(12'B0), .doutb(), .injectsbiterr(1'D0), .injectdbiterr(1'D0), @@ -180,7 +180,7 @@ output wire [10 : 0] douta; .s_axi_awburst(2'B0), .s_axi_awvalid(1'D0), .s_axi_awready(), - .s_axi_wdata(11'B0), + .s_axi_wdata(12'B0), .s_axi_wstrb(1'B0), .s_axi_wlast(1'D0), .s_axi_wvalid(1'D0), diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_RF_control/sim/vio_RF_control.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_RF_control/sim/vio_RF_control.v index 2c99c0a3..9a40cad6 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_RF_control/sim/vio_RF_control.v +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_RF_control/sim/vio_RF_control.v @@ -48,7 +48,7 @@ `timescale 1ns / 1ps module vio_RF_control ( clk, - +probe_in0, probe_out0, probe_out1, probe_out2, @@ -57,10 +57,18 @@ probe_out4, probe_out5, probe_out6, probe_out7, -probe_out8 +probe_out8, +probe_out9, +probe_out10, +probe_out11, +probe_out12, +probe_out13, +probe_out14, +probe_out15 ); input clk; +input [11 : 0] probe_in0; output reg [0 : 0] probe_out0 = 'h0 ; output reg [1 : 0] probe_out1 = 'h0 ; @@ -71,6 +79,13 @@ output reg [11 : 0] probe_out5 = 'h3E8 ; output reg [0 : 0] probe_out6 = 'h0 ; output reg [0 : 0] probe_out7 = 'h0 ; output reg [0 : 0] probe_out8 = 'h0 ; +output reg [0 : 0] probe_out9 = 'h0 ; +output reg [0 : 0] probe_out10 = 'h0 ; +output reg [0 : 0] probe_out11 = 'h0 ; +output reg [0 : 0] probe_out12 = 'h0 ; +output reg [31 : 0] probe_out13 = 'h0002EE00 ; +output reg [0 : 0] probe_out14 = 'h0 ; +output reg [31 : 0] probe_out15 = 'h0B71B000 ; endmodule diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_RF_control/vio_RF_control.veo b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_RF_control/vio_RF_control.veo index 13870dbc..149e4916 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_RF_control/vio_RF_control.veo +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_RF_control/vio_RF_control.veo @@ -55,16 +55,24 @@ //----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG vio_RF_control your_instance_name ( - .clk(clk), // input wire clk - .probe_out0(probe_out0), // output wire [0 : 0] probe_out0 - .probe_out1(probe_out1), // output wire [1 : 0] probe_out1 - .probe_out2(probe_out2), // output wire [0 : 0] probe_out2 - .probe_out3(probe_out3), // output wire [7 : 0] probe_out3 - .probe_out4(probe_out4), // output wire [7 : 0] probe_out4 - .probe_out5(probe_out5), // output wire [11 : 0] probe_out5 - .probe_out6(probe_out6), // output wire [0 : 0] probe_out6 - .probe_out7(probe_out7), // output wire [0 : 0] probe_out7 - .probe_out8(probe_out8) // output wire [0 : 0] probe_out8 + .clk(clk), // input wire clk + .probe_in0(probe_in0), // input wire [11 : 0] probe_in0 + .probe_out0(probe_out0), // output wire [0 : 0] probe_out0 + .probe_out1(probe_out1), // output wire [1 : 0] probe_out1 + .probe_out2(probe_out2), // output wire [0 : 0] probe_out2 + .probe_out3(probe_out3), // output wire [7 : 0] probe_out3 + .probe_out4(probe_out4), // output wire [7 : 0] probe_out4 + .probe_out5(probe_out5), // output wire [11 : 0] probe_out5 + .probe_out6(probe_out6), // output wire [0 : 0] probe_out6 + .probe_out7(probe_out7), // output wire [0 : 0] probe_out7 + .probe_out8(probe_out8), // output wire [0 : 0] probe_out8 + .probe_out9(probe_out9), // output wire [0 : 0] probe_out9 + .probe_out10(probe_out10), // output wire [0 : 0] probe_out10 + .probe_out11(probe_out11), // output wire [0 : 0] probe_out11 + .probe_out12(probe_out12), // output wire [0 : 0] probe_out12 + .probe_out13(probe_out13), // output wire [31 : 0] probe_out13 + .probe_out14(probe_out14), // output wire [0 : 0] probe_out14 + .probe_out15(probe_out15) // output wire [31 : 0] probe_out15 ); // INST_TAG_END ------ End INSTANTIATION Template --------- diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_RF_control/vio_RF_control.vho b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_RF_control/vio_RF_control.vho index ebb4dc98..343267ff 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_RF_control/vio_RF_control.vho +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_RF_control/vio_RF_control.vho @@ -55,6 +55,7 @@ COMPONENT vio_RF_control PORT ( clk : IN STD_LOGIC; + probe_in0 : IN STD_LOGIC_VECTOR(11 DOWNTO 0); probe_out0 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); probe_out1 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); probe_out2 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); @@ -63,7 +64,14 @@ COMPONENT vio_RF_control probe_out5 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); probe_out6 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); probe_out7 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); - probe_out8 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) + probe_out8 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + probe_out9 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + probe_out10 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + probe_out11 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + probe_out12 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + probe_out13 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + probe_out14 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + probe_out15 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END COMPONENT; -- COMP_TAG_END ------ End COMPONENT Declaration ------------ @@ -75,6 +83,7 @@ END COMPONENT; your_instance_name : vio_RF_control PORT MAP ( clk => clk, + probe_in0 => probe_in0, probe_out0 => probe_out0, probe_out1 => probe_out1, probe_out2 => probe_out2, @@ -83,7 +92,14 @@ your_instance_name : vio_RF_control probe_out5 => probe_out5, probe_out6 => probe_out6, probe_out7 => probe_out7, - probe_out8 => probe_out8 + probe_out8 => probe_out8, + probe_out9 => probe_out9, + probe_out10 => probe_out10, + probe_out11 => probe_out11, + probe_out12 => probe_out12, + probe_out13 => probe_out13, + probe_out14 => probe_out14, + probe_out15 => probe_out15 ); -- INST_TAG_END ------ End INSTANTIATION Template --------- diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_RF_control/vio_RF_control_sim_netlist.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_RF_control/vio_RF_control_sim_netlist.v index d2027514..f15721e9 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_RF_control/vio_RF_control_sim_netlist.v +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_RF_control/vio_RF_control_sim_netlist.v @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:b9b77ac176e8ad7e093daf0c8fddbc4e9f9b57df2bec9eca440122e742975871 -size 346446 +oid sha256:ba1ba841643badc5c1347838c1be97020a44c661ac3bfa7361c3eb9da92ce4ca +size 424588 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_RF_control/vio_RF_control_sim_netlist.vhdl b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_RF_control/vio_RF_control_sim_netlist.vhdl index 104bb3cf..95a8f1e2 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_RF_control/vio_RF_control_sim_netlist.vhdl +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_RF_control/vio_RF_control_sim_netlist.vhdl @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:363e7fd5368c994b30b8a7c879fab160cc73f2325814afb439ab825e5a209448 -size 624784 +oid sha256:1ac752b031bf31290755a15ea0f1d589241d6d7b6d0151c37451a33e22c33214 +size 735950 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_RF_control/vio_RF_control_stub.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_RF_control/vio_RF_control_stub.v index 2e62ebac..931473ee 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_RF_control/vio_RF_control_stub.v +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_RF_control/vio_RF_control_stub.v @@ -1,10 +1,10 @@ // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 -// Date : Tue Jun 27 16:05:58 2023 +// Date : Sun Jul 30 18:20:42 2023 // Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS // Command : write_verilog -force -mode synth_stub -// /home/josh/Workspace/datalink_814/phy/dl814_dj_phy_ber/dl814_dj_phy_ber.runs/vio_RF_control_synth_1/vio_RF_control_stub.v +// /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/vio_RF_control_stub.v // Design : vio_RF_control // Purpose : Stub declaration of top-level module interface // Device : xc7z100ffg900-2 @@ -14,10 +14,12 @@ // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. // Please paste the declaration into a Verilog source file or add the file as an additional source. (* X_CORE_INFO = "vio,Vivado 2019.1.3" *) -module vio_RF_control(clk, probe_out0, probe_out1, probe_out2, - probe_out3, probe_out4, probe_out5, probe_out6, probe_out7, probe_out8) -/* synthesis syn_black_box black_box_pad_pin="clk,probe_out0[0:0],probe_out1[1:0],probe_out2[0:0],probe_out3[7:0],probe_out4[7:0],probe_out5[11:0],probe_out6[0:0],probe_out7[0:0],probe_out8[0:0]" */; +module vio_RF_control(clk, probe_in0, probe_out0, probe_out1, + probe_out2, probe_out3, probe_out4, probe_out5, probe_out6, probe_out7, probe_out8, probe_out9, + probe_out10, probe_out11, probe_out12, probe_out13, probe_out14, probe_out15) +/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[11:0],probe_out0[0:0],probe_out1[1:0],probe_out2[0:0],probe_out3[7:0],probe_out4[7:0],probe_out5[11:0],probe_out6[0:0],probe_out7[0:0],probe_out8[0:0],probe_out9[0:0],probe_out10[0:0],probe_out11[0:0],probe_out12[0:0],probe_out13[31:0],probe_out14[0:0],probe_out15[31:0]" */; input clk; + input [11:0]probe_in0; output [0:0]probe_out0; output [1:0]probe_out1; output [0:0]probe_out2; @@ -27,4 +29,11 @@ module vio_RF_control(clk, probe_out0, probe_out1, probe_out2, output [0:0]probe_out6; output [0:0]probe_out7; output [0:0]probe_out8; + output [0:0]probe_out9; + output [0:0]probe_out10; + output [0:0]probe_out11; + output [0:0]probe_out12; + output [31:0]probe_out13; + output [0:0]probe_out14; + output [31:0]probe_out15; endmodule diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_RF_control/vio_RF_control_stub.vhdl b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_RF_control/vio_RF_control_stub.vhdl index adddb59d..8b4afdd8 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_RF_control/vio_RF_control_stub.vhdl +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_RF_control/vio_RF_control_stub.vhdl @@ -1,10 +1,10 @@ -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 --- Date : Tue Jun 27 16:05:58 2023 +-- Date : Sun Jul 30 18:20:42 2023 -- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS -- Command : write_vhdl -force -mode synth_stub --- /home/josh/Workspace/datalink_814/phy/dl814_dj_phy_ber/dl814_dj_phy_ber.runs/vio_RF_control_synth_1/vio_RF_control_stub.vhdl +-- /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/vio_RF_control_stub.vhdl -- Design : vio_RF_control -- Purpose : Stub declaration of top-level module interface -- Device : xc7z100ffg900-2 @@ -15,6 +15,7 @@ use IEEE.STD_LOGIC_1164.ALL; entity vio_RF_control is Port ( clk : in STD_LOGIC; + probe_in0 : in STD_LOGIC_VECTOR ( 11 downto 0 ); probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 ); probe_out1 : out STD_LOGIC_VECTOR ( 1 downto 0 ); probe_out2 : out STD_LOGIC_VECTOR ( 0 to 0 ); @@ -23,7 +24,14 @@ entity vio_RF_control is probe_out5 : out STD_LOGIC_VECTOR ( 11 downto 0 ); probe_out6 : out STD_LOGIC_VECTOR ( 0 to 0 ); probe_out7 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out8 : out STD_LOGIC_VECTOR ( 0 to 0 ) + probe_out8 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out9 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out10 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out11 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out12 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out13 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + probe_out14 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out15 : out STD_LOGIC_VECTOR ( 31 downto 0 ) ); end vio_RF_control; @@ -32,7 +40,7 @@ architecture stub of vio_RF_control is attribute syn_black_box : boolean; attribute black_box_pad_pin : string; attribute syn_black_box of stub : architecture is true; -attribute black_box_pad_pin of stub : architecture is "clk,probe_out0[0:0],probe_out1[1:0],probe_out2[0:0],probe_out3[7:0],probe_out4[7:0],probe_out5[11:0],probe_out6[0:0],probe_out7[0:0],probe_out8[0:0]"; +attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[11:0],probe_out0[0:0],probe_out1[1:0],probe_out2[0:0],probe_out3[7:0],probe_out4[7:0],probe_out5[11:0],probe_out6[0:0],probe_out7[0:0],probe_out8[0:0],probe_out9[0:0],probe_out10[0:0],probe_out11[0:0],probe_out12[0:0],probe_out13[31:0],probe_out14[0:0],probe_out15[31:0]"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3"; begin diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/mem_init_files/freq_word.coe b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/mem_init_files/freq_word.coe index 590747a4..20ed79a7 100755 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/mem_init_files/freq_word.coe +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/mem_init_files/freq_word.coe @@ -1,83 +1,83 @@ MEMORY_INITIALIZATION_RADIX = 10; MEMORY_INITIALIZATION_VECTOR = -1624, -1611, -1598, -1585, -1572, -1559, -1546, -1533, -1520, -1507, -1494, -1481, -1468, -1455, -1442, -1429, -1416, -1403, -1390, -1377, -1364, -1351, -1338, -1325, -1312, -1299, -1286, -1273, -1260, -1247, -1234, -1221, -1208, -1195, -1182, -1169, -1156, -1143, -1130, -1117, -1104, -1091, -1078, -1065, -1052, -1039, -1026, -1013, -1000, -987, -974, -961, -948, -935, -922, -909, -896, -883, -870, -857, -844, -831, -818, -805, -792, -779, -766, -753, -740, -727, -714, -701, -688, -675, -662, -649, -636, -623, -610, -597, -584, +2124, +2111, +2098, +2085, +2072, +2059, +2046, +2033, +2020, +2007, +1994, +1981, +1968, +1955, +1942, +1929, +1916, +1903, +1890, +1877, +1864, +1851, +1838, +1825, +1812, +1799, +1786, +1773, +1760, +1747, +1734, +1721, +1708, +1695, +1682, +1669, +1656, +1643, +1630, +1617, +1604, +1591, +1578, +1565, +1552, +1539, +1526, +1513, +1500, +1487, +1474, +1461, +1448, +1435, +1422, +1409, +1396, +1383, +1370, +1357, +1344, +1331, +1318, +1305, +1292, +1279, +1266, +1253, +1240, +1227, +1214, +1201, +1188, +1175, +1162, +1149, +1136, +1123, +1110, +1097, +1084, diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/mem_init_files/rom_freq_word.mif b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/mem_init_files/rom_freq_word.mif index 355400b4..692cd517 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/mem_init_files/rom_freq_word.mif +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/mem_init_files/rom_freq_word.mif @@ -1,81 +1,81 @@ -11001011000 -11001001011 -11000111110 -11000110001 -11000100100 -11000010111 -11000001010 -10111111101 -10111110000 -10111100011 -10111010110 -10111001001 -10110111100 -10110101111 -10110100010 -10110010101 -10110001000 -10101111011 -10101101110 -10101100001 -10101010100 -10101000111 -10100111010 -10100101101 -10100100000 -10100010011 -10100000110 -10011111001 -10011101100 -10011011111 -10011010010 -10011000101 -10010111000 -10010101011 -10010011110 -10010010001 -10010000100 -10001110111 -10001101010 -10001011101 -10001010000 -10001000011 -10000110110 -10000101001 -10000011100 -10000001111 -10000000010 -01111110101 -01111101000 -01111011011 -01111001110 -01111000001 -01110110100 -01110100111 -01110011010 -01110001101 -01110000000 -01101110011 -01101100110 -01101011001 -01101001100 -01100111111 -01100110010 -01100100101 -01100011000 -01100001011 -01011111110 -01011110001 -01011100100 -01011010111 -01011001010 -01010111101 -01010110000 -01010100011 -01010010110 -01010001001 -01001111100 -01001101111 -01001100010 -01001010101 -01001001000 +100001001100 +100000111111 +100000110010 +100000100101 +100000011000 +100000001011 +011111111110 +011111110001 +011111100100 +011111010111 +011111001010 +011110111101 +011110110000 +011110100011 +011110010110 +011110001001 +011101111100 +011101101111 +011101100010 +011101010101 +011101001000 +011100111011 +011100101110 +011100100001 +011100010100 +011100000111 +011011111010 +011011101101 +011011100000 +011011010011 +011011000110 +011010111001 +011010101100 +011010011111 +011010010010 +011010000101 +011001111000 +011001101011 +011001011110 +011001010001 +011001000100 +011000110111 +011000101010 +011000011101 +011000010000 +011000000011 +010111110110 +010111101001 +010111011100 +010111001111 +010111000010 +010110110101 +010110101000 +010110011011 +010110001110 +010110000001 +010101110100 +010101100111 +010101011010 +010101001101 +010101000000 +010100110011 +010100100110 +010100011001 +010100001100 +010011111111 +010011110010 +010011100101 +010011011000 +010011001011 +010010111110 +010010110001 +010010100100 +010010010111 +010010001010 +010001111101 +010001110000 +010001100011 +010001010110 +010001001001 +010000111100 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/README.txt index 13d33d7c..33c0284f 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/README.txt +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Thu May 18 11:49:45 CST 2023 +# Generated by export_simulation on Sun Jul 30 18:05:42 CST 2023 # ################################################################################ diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/compile.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/compile.do index 1e5ae39c..074951e0 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/compile.do +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/compile.do @@ -10,11 +10,11 @@ vmap xpm activehdl/xpm vmap blk_mem_gen_v8_4_3 activehdl/blk_mem_gen_v8_4_3 vlog -work xil_defaultlib -sv2k12 \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ vcom -work xpm -93 \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ vlog -work blk_mem_gen_v8_4_3 -v2k5 \ "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/file_info.txt index 78704c4b..8f86cd6a 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/file_info.txt +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/file_info.txt @@ -1,6 +1,6 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, -xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, -xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, rom_freq_word.v,verilog,xil_defaultlib,../../../ip/rom_freq_word/sim/rom_freq_word.v, glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/freq_word.coe b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/freq_word.coe index 590747a4..20ed79a7 100755 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/freq_word.coe +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/freq_word.coe @@ -1,83 +1,83 @@ MEMORY_INITIALIZATION_RADIX = 10; MEMORY_INITIALIZATION_VECTOR = -1624, -1611, -1598, -1585, -1572, -1559, -1546, -1533, -1520, -1507, -1494, -1481, -1468, -1455, -1442, -1429, -1416, -1403, -1390, -1377, -1364, -1351, -1338, -1325, -1312, -1299, -1286, -1273, -1260, -1247, -1234, -1221, -1208, -1195, -1182, -1169, -1156, -1143, -1130, -1117, -1104, -1091, -1078, -1065, -1052, -1039, -1026, -1013, -1000, -987, -974, -961, -948, -935, -922, -909, -896, -883, -870, -857, -844, -831, -818, -805, -792, -779, -766, -753, -740, -727, -714, -701, -688, -675, -662, -649, -636, -623, -610, -597, -584, +2124, +2111, +2098, +2085, +2072, +2059, +2046, +2033, +2020, +2007, +1994, +1981, +1968, +1955, +1942, +1929, +1916, +1903, +1890, +1877, +1864, +1851, +1838, +1825, +1812, +1799, +1786, +1773, +1760, +1747, +1734, +1721, +1708, +1695, +1682, +1669, +1656, +1643, +1630, +1617, +1604, +1591, +1578, +1565, +1552, +1539, +1526, +1513, +1500, +1487, +1474, +1461, +1448, +1435, +1422, +1409, +1396, +1383, +1370, +1357, +1344, +1331, +1318, +1305, +1292, +1279, +1266, +1253, +1240, +1227, +1214, +1201, +1188, +1175, +1162, +1149, +1136, +1123, +1110, +1097, +1084, diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/rom_freq_word.mif b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/rom_freq_word.mif index 355400b4..692cd517 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/rom_freq_word.mif +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/rom_freq_word.mif @@ -1,81 +1,81 @@ -11001011000 -11001001011 -11000111110 -11000110001 -11000100100 -11000010111 -11000001010 -10111111101 -10111110000 -10111100011 -10111010110 -10111001001 -10110111100 -10110101111 -10110100010 -10110010101 -10110001000 -10101111011 -10101101110 -10101100001 -10101010100 -10101000111 -10100111010 -10100101101 -10100100000 -10100010011 -10100000110 -10011111001 -10011101100 -10011011111 -10011010010 -10011000101 -10010111000 -10010101011 -10010011110 -10010010001 -10010000100 -10001110111 -10001101010 -10001011101 -10001010000 -10001000011 -10000110110 -10000101001 -10000011100 -10000001111 -10000000010 -01111110101 -01111101000 -01111011011 -01111001110 -01111000001 -01110110100 -01110100111 -01110011010 -01110001101 -01110000000 -01101110011 -01101100110 -01101011001 -01101001100 -01100111111 -01100110010 -01100100101 -01100011000 -01100001011 -01011111110 -01011110001 -01011100100 -01011010111 -01011001010 -01010111101 -01010110000 -01010100011 -01010010110 -01010001001 -01001111100 -01001101111 -01001100010 -01001010101 -01001001000 +100001001100 +100000111111 +100000110010 +100000100101 +100000011000 +100000001011 +011111111110 +011111110001 +011111100100 +011111010111 +011111001010 +011110111101 +011110110000 +011110100011 +011110010110 +011110001001 +011101111100 +011101101111 +011101100010 +011101010101 +011101001000 +011100111011 +011100101110 +011100100001 +011100010100 +011100000111 +011011111010 +011011101101 +011011100000 +011011010011 +011011000110 +011010111001 +011010101100 +011010011111 +011010010010 +011010000101 +011001111000 +011001101011 +011001011110 +011001010001 +011001000100 +011000110111 +011000101010 +011000011101 +011000010000 +011000000011 +010111110110 +010111101001 +010111011100 +010111001111 +010111000010 +010110110101 +010110101000 +010110011011 +010110001110 +010110000001 +010101110100 +010101100111 +010101011010 +010101001101 +010101000000 +010100110011 +010100100110 +010100011001 +010100001100 +010011111111 +010011110010 +010011100101 +010011011000 +010011001011 +010010111110 +010010110001 +010010100100 +010010010111 +010010001010 +010001111101 +010001110000 +010001100011 +010001010110 +010001001001 +010000111100 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/rom_freq_word.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/rom_freq_word.sh index df34cfa1..62ae23c7 100755 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/rom_freq_word.sh +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/rom_freq_word.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Thu May 18 11:49:45 CST 2023 +# Generated by Vivado on Sun Jul 30 18:05:42 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/ies/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/ies/README.txt index 76068bd4..0994464c 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/ies/README.txt +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/ies/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Thu May 18 11:49:45 CST 2023 +# Generated by export_simulation on Sun Jul 30 18:05:42 CST 2023 # ################################################################################ diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/ies/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/ies/file_info.txt index 78704c4b..8f86cd6a 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/ies/file_info.txt +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/ies/file_info.txt @@ -1,6 +1,6 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, -xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, -xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, rom_freq_word.v,verilog,xil_defaultlib,../../../ip/rom_freq_word/sim/rom_freq_word.v, glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/ies/freq_word.coe b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/ies/freq_word.coe index 590747a4..20ed79a7 100755 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/ies/freq_word.coe +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/ies/freq_word.coe @@ -1,83 +1,83 @@ MEMORY_INITIALIZATION_RADIX = 10; MEMORY_INITIALIZATION_VECTOR = -1624, -1611, -1598, -1585, -1572, -1559, -1546, -1533, -1520, -1507, -1494, -1481, -1468, -1455, -1442, -1429, -1416, -1403, -1390, -1377, -1364, -1351, -1338, -1325, -1312, -1299, -1286, -1273, -1260, -1247, -1234, -1221, -1208, -1195, -1182, -1169, -1156, -1143, -1130, -1117, -1104, -1091, -1078, -1065, -1052, -1039, -1026, -1013, -1000, -987, -974, -961, -948, -935, -922, -909, -896, -883, -870, -857, -844, -831, -818, -805, -792, -779, -766, -753, -740, -727, -714, -701, -688, -675, -662, -649, -636, -623, -610, -597, -584, +2124, +2111, +2098, +2085, +2072, +2059, +2046, +2033, +2020, +2007, +1994, +1981, +1968, +1955, +1942, +1929, +1916, +1903, +1890, +1877, +1864, +1851, +1838, +1825, +1812, +1799, +1786, +1773, +1760, +1747, +1734, +1721, +1708, +1695, +1682, +1669, +1656, +1643, +1630, +1617, +1604, +1591, +1578, +1565, +1552, +1539, +1526, +1513, +1500, +1487, +1474, +1461, +1448, +1435, +1422, +1409, +1396, +1383, +1370, +1357, +1344, +1331, +1318, +1305, +1292, +1279, +1266, +1253, +1240, +1227, +1214, +1201, +1188, +1175, +1162, +1149, +1136, +1123, +1110, +1097, +1084, diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/ies/rom_freq_word.mif b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/ies/rom_freq_word.mif index 355400b4..692cd517 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/ies/rom_freq_word.mif +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/ies/rom_freq_word.mif @@ -1,81 +1,81 @@ -11001011000 -11001001011 -11000111110 -11000110001 -11000100100 -11000010111 -11000001010 -10111111101 -10111110000 -10111100011 -10111010110 -10111001001 -10110111100 -10110101111 -10110100010 -10110010101 -10110001000 -10101111011 -10101101110 -10101100001 -10101010100 -10101000111 -10100111010 -10100101101 -10100100000 -10100010011 -10100000110 -10011111001 -10011101100 -10011011111 -10011010010 -10011000101 -10010111000 -10010101011 -10010011110 -10010010001 -10010000100 -10001110111 -10001101010 -10001011101 -10001010000 -10001000011 -10000110110 -10000101001 -10000011100 -10000001111 -10000000010 -01111110101 -01111101000 -01111011011 -01111001110 -01111000001 -01110110100 -01110100111 -01110011010 -01110001101 -01110000000 -01101110011 -01101100110 -01101011001 -01101001100 -01100111111 -01100110010 -01100100101 -01100011000 -01100001011 -01011111110 -01011110001 -01011100100 -01011010111 -01011001010 -01010111101 -01010110000 -01010100011 -01010010110 -01010001001 -01001111100 -01001101111 -01001100010 -01001010101 -01001001000 +100001001100 +100000111111 +100000110010 +100000100101 +100000011000 +100000001011 +011111111110 +011111110001 +011111100100 +011111010111 +011111001010 +011110111101 +011110110000 +011110100011 +011110010110 +011110001001 +011101111100 +011101101111 +011101100010 +011101010101 +011101001000 +011100111011 +011100101110 +011100100001 +011100010100 +011100000111 +011011111010 +011011101101 +011011100000 +011011010011 +011011000110 +011010111001 +011010101100 +011010011111 +011010010010 +011010000101 +011001111000 +011001101011 +011001011110 +011001010001 +011001000100 +011000110111 +011000101010 +011000011101 +011000010000 +011000000011 +010111110110 +010111101001 +010111011100 +010111001111 +010111000010 +010110110101 +010110101000 +010110011011 +010110001110 +010110000001 +010101110100 +010101100111 +010101011010 +010101001101 +010101000000 +010100110011 +010100100110 +010100011001 +010100001100 +010011111111 +010011110010 +010011100101 +010011011000 +010011001011 +010010111110 +010010110001 +010010100100 +010010010111 +010010001010 +010001111101 +010001110000 +010001100011 +010001010110 +010001001001 +010000111100 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/ies/rom_freq_word.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/ies/rom_freq_word.sh index 41e3e518..2ea903ab 100755 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/ies/rom_freq_word.sh +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/ies/rom_freq_word.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Thu May 18 11:49:45 CST 2023 +# Generated by Vivado on Sun Jul 30 18:05:42 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/ies/run.f b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/ies/run.f index 09c85501..ba7fe8a7 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/ies/run.f +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/ies/run.f @@ -1,9 +1,9 @@ -makelib ies_lib/xil_defaultlib -sv \ - "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ - "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + "/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ -endlib -makelib ies_lib/xpm \ - "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + "/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ -endlib -makelib ies_lib/blk_mem_gen_v8_4_3 \ "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/README.txt index 13d33d7c..33c0284f 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/README.txt +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Thu May 18 11:49:45 CST 2023 +# Generated by export_simulation on Sun Jul 30 18:05:42 CST 2023 # ################################################################################ diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/freq_word.coe b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/freq_word.coe index 590747a4..20ed79a7 100755 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/freq_word.coe +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/freq_word.coe @@ -1,83 +1,83 @@ MEMORY_INITIALIZATION_RADIX = 10; MEMORY_INITIALIZATION_VECTOR = -1624, -1611, -1598, -1585, -1572, -1559, -1546, -1533, -1520, -1507, -1494, -1481, -1468, -1455, -1442, -1429, -1416, -1403, -1390, -1377, -1364, -1351, -1338, -1325, -1312, -1299, -1286, -1273, -1260, -1247, -1234, -1221, -1208, -1195, -1182, -1169, -1156, -1143, -1130, -1117, -1104, -1091, -1078, -1065, -1052, -1039, -1026, -1013, -1000, -987, -974, -961, -948, -935, -922, -909, -896, -883, -870, -857, -844, -831, -818, -805, -792, -779, -766, -753, -740, -727, -714, -701, -688, -675, -662, -649, -636, -623, -610, -597, -584, +2124, +2111, +2098, +2085, +2072, +2059, +2046, +2033, +2020, +2007, +1994, +1981, +1968, +1955, +1942, +1929, +1916, +1903, +1890, +1877, +1864, +1851, +1838, +1825, +1812, +1799, +1786, +1773, +1760, +1747, +1734, +1721, +1708, +1695, +1682, +1669, +1656, +1643, +1630, +1617, +1604, +1591, +1578, +1565, +1552, +1539, +1526, +1513, +1500, +1487, +1474, +1461, +1448, +1435, +1422, +1409, +1396, +1383, +1370, +1357, +1344, +1331, +1318, +1305, +1292, +1279, +1266, +1253, +1240, +1227, +1214, +1201, +1188, +1175, +1162, +1149, +1136, +1123, +1110, +1097, +1084, diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/rom_freq_word.mif b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/rom_freq_word.mif index 355400b4..692cd517 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/rom_freq_word.mif +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/rom_freq_word.mif @@ -1,81 +1,81 @@ -11001011000 -11001001011 -11000111110 -11000110001 -11000100100 -11000010111 -11000001010 -10111111101 -10111110000 -10111100011 -10111010110 -10111001001 -10110111100 -10110101111 -10110100010 -10110010101 -10110001000 -10101111011 -10101101110 -10101100001 -10101010100 -10101000111 -10100111010 -10100101101 -10100100000 -10100010011 -10100000110 -10011111001 -10011101100 -10011011111 -10011010010 -10011000101 -10010111000 -10010101011 -10010011110 -10010010001 -10010000100 -10001110111 -10001101010 -10001011101 -10001010000 -10001000011 -10000110110 -10000101001 -10000011100 -10000001111 -10000000010 -01111110101 -01111101000 -01111011011 -01111001110 -01111000001 -01110110100 -01110100111 -01110011010 -01110001101 -01110000000 -01101110011 -01101100110 -01101011001 -01101001100 -01100111111 -01100110010 -01100100101 -01100011000 -01100001011 -01011111110 -01011110001 -01011100100 -01011010111 -01011001010 -01010111101 -01010110000 -01010100011 -01010010110 -01010001001 -01001111100 -01001101111 -01001100010 -01001010101 -01001001000 +100001001100 +100000111111 +100000110010 +100000100101 +100000011000 +100000001011 +011111111110 +011111110001 +011111100100 +011111010111 +011111001010 +011110111101 +011110110000 +011110100011 +011110010110 +011110001001 +011101111100 +011101101111 +011101100010 +011101010101 +011101001000 +011100111011 +011100101110 +011100100001 +011100010100 +011100000111 +011011111010 +011011101101 +011011100000 +011011010011 +011011000110 +011010111001 +011010101100 +011010011111 +011010010010 +011010000101 +011001111000 +011001101011 +011001011110 +011001010001 +011001000100 +011000110111 +011000101010 +011000011101 +011000010000 +011000000011 +010111110110 +010111101001 +010111011100 +010111001111 +010111000010 +010110110101 +010110101000 +010110011011 +010110001110 +010110000001 +010101110100 +010101100111 +010101011010 +010101001101 +010101000000 +010100110011 +010100100110 +010100011001 +010100001100 +010011111111 +010011110010 +010011100101 +010011011000 +010011001011 +010010111110 +010010110001 +010010100100 +010010010111 +010010001010 +010001111101 +010001110000 +010001100011 +010001010110 +010001001001 +010000111100 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/rom_freq_word.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/rom_freq_word.sh index 4b14ed75..e81a1f7b 100755 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/rom_freq_word.sh +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/rom_freq_word.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Thu May 18 11:49:45 CST 2023 +# Generated by Vivado on Sun Jul 30 18:05:42 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/README.txt index 13d33d7c..33c0284f 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/README.txt +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Thu May 18 11:49:45 CST 2023 +# Generated by export_simulation on Sun Jul 30 18:05:42 CST 2023 # ################################################################################ diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/compile.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/compile.do index bd408354..96d8db93 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/compile.do +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/compile.do @@ -10,11 +10,11 @@ vmap xpm questa_lib/msim/xpm vmap blk_mem_gen_v8_4_3 questa_lib/msim/blk_mem_gen_v8_4_3 vlog -work xil_defaultlib -64 -sv \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ vcom -work xpm -64 -93 \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ vlog -work blk_mem_gen_v8_4_3 -64 \ "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/file_info.txt index 78704c4b..8f86cd6a 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/file_info.txt +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/file_info.txt @@ -1,6 +1,6 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, -xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, -xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, rom_freq_word.v,verilog,xil_defaultlib,../../../ip/rom_freq_word/sim/rom_freq_word.v, glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/freq_word.coe b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/freq_word.coe index 590747a4..20ed79a7 100755 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/freq_word.coe +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/freq_word.coe @@ -1,83 +1,83 @@ MEMORY_INITIALIZATION_RADIX = 10; MEMORY_INITIALIZATION_VECTOR = -1624, -1611, -1598, -1585, -1572, -1559, -1546, -1533, -1520, -1507, -1494, -1481, -1468, -1455, -1442, -1429, -1416, -1403, -1390, -1377, -1364, -1351, -1338, -1325, -1312, -1299, -1286, -1273, -1260, -1247, -1234, -1221, -1208, -1195, -1182, -1169, -1156, -1143, -1130, -1117, -1104, -1091, -1078, -1065, -1052, -1039, -1026, -1013, -1000, -987, -974, -961, -948, -935, -922, -909, -896, -883, -870, -857, -844, -831, -818, -805, -792, -779, -766, -753, -740, -727, -714, -701, -688, -675, -662, -649, -636, -623, -610, -597, -584, +2124, +2111, +2098, +2085, +2072, +2059, +2046, +2033, +2020, +2007, +1994, +1981, +1968, +1955, +1942, +1929, +1916, +1903, +1890, +1877, +1864, +1851, +1838, +1825, +1812, +1799, +1786, +1773, +1760, +1747, +1734, +1721, +1708, +1695, +1682, +1669, +1656, +1643, +1630, +1617, +1604, +1591, +1578, +1565, +1552, +1539, +1526, +1513, +1500, +1487, +1474, +1461, +1448, +1435, +1422, +1409, +1396, +1383, +1370, +1357, +1344, +1331, +1318, +1305, +1292, +1279, +1266, +1253, +1240, +1227, +1214, +1201, +1188, +1175, +1162, +1149, +1136, +1123, +1110, +1097, +1084, diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/rom_freq_word.mif b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/rom_freq_word.mif index 355400b4..692cd517 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/rom_freq_word.mif +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/rom_freq_word.mif @@ -1,81 +1,81 @@ -11001011000 -11001001011 -11000111110 -11000110001 -11000100100 -11000010111 -11000001010 -10111111101 -10111110000 -10111100011 -10111010110 -10111001001 -10110111100 -10110101111 -10110100010 -10110010101 -10110001000 -10101111011 -10101101110 -10101100001 -10101010100 -10101000111 -10100111010 -10100101101 -10100100000 -10100010011 -10100000110 -10011111001 -10011101100 -10011011111 -10011010010 -10011000101 -10010111000 -10010101011 -10010011110 -10010010001 -10010000100 -10001110111 -10001101010 -10001011101 -10001010000 -10001000011 -10000110110 -10000101001 -10000011100 -10000001111 -10000000010 -01111110101 -01111101000 -01111011011 -01111001110 -01111000001 -01110110100 -01110100111 -01110011010 -01110001101 -01110000000 -01101110011 -01101100110 -01101011001 -01101001100 -01100111111 -01100110010 -01100100101 -01100011000 -01100001011 -01011111110 -01011110001 -01011100100 -01011010111 -01011001010 -01010111101 -01010110000 -01010100011 -01010010110 -01010001001 -01001111100 -01001101111 -01001100010 -01001010101 -01001001000 +100001001100 +100000111111 +100000110010 +100000100101 +100000011000 +100000001011 +011111111110 +011111110001 +011111100100 +011111010111 +011111001010 +011110111101 +011110110000 +011110100011 +011110010110 +011110001001 +011101111100 +011101101111 +011101100010 +011101010101 +011101001000 +011100111011 +011100101110 +011100100001 +011100010100 +011100000111 +011011111010 +011011101101 +011011100000 +011011010011 +011011000110 +011010111001 +011010101100 +011010011111 +011010010010 +011010000101 +011001111000 +011001101011 +011001011110 +011001010001 +011001000100 +011000110111 +011000101010 +011000011101 +011000010000 +011000000011 +010111110110 +010111101001 +010111011100 +010111001111 +010111000010 +010110110101 +010110101000 +010110011011 +010110001110 +010110000001 +010101110100 +010101100111 +010101011010 +010101001101 +010101000000 +010100110011 +010100100110 +010100011001 +010100001100 +010011111111 +010011110010 +010011100101 +010011011000 +010011001011 +010010111110 +010010110001 +010010100100 +010010010111 +010010001010 +010001111101 +010001110000 +010001100011 +010001010110 +010001001001 +010000111100 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/rom_freq_word.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/rom_freq_word.sh index 4bea2f53..06f4774b 100755 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/rom_freq_word.sh +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/rom_freq_word.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Thu May 18 11:49:45 CST 2023 +# Generated by Vivado on Sun Jul 30 18:05:42 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/README.txt index 13d33d7c..33c0284f 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/README.txt +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Thu May 18 11:49:45 CST 2023 +# Generated by export_simulation on Sun Jul 30 18:05:42 CST 2023 # ################################################################################ diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/compile.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/compile.do index 1baef140..4d4c7fa9 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/compile.do +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/compile.do @@ -10,11 +10,11 @@ vmap xpm riviera/xpm vmap blk_mem_gen_v8_4_3 riviera/blk_mem_gen_v8_4_3 vlog -work xil_defaultlib -sv2k12 \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ vcom -work xpm -93 \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ vlog -work blk_mem_gen_v8_4_3 -v2k5 \ "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/file_info.txt index 78704c4b..8f86cd6a 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/file_info.txt +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/file_info.txt @@ -1,6 +1,6 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, -xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, -xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, rom_freq_word.v,verilog,xil_defaultlib,../../../ip/rom_freq_word/sim/rom_freq_word.v, glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/freq_word.coe b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/freq_word.coe index 590747a4..20ed79a7 100755 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/freq_word.coe +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/freq_word.coe @@ -1,83 +1,83 @@ MEMORY_INITIALIZATION_RADIX = 10; MEMORY_INITIALIZATION_VECTOR = -1624, -1611, -1598, -1585, -1572, -1559, -1546, -1533, -1520, -1507, -1494, -1481, -1468, -1455, -1442, -1429, -1416, -1403, -1390, -1377, -1364, -1351, -1338, -1325, -1312, -1299, -1286, -1273, -1260, -1247, -1234, -1221, -1208, -1195, -1182, -1169, -1156, -1143, -1130, -1117, -1104, -1091, -1078, -1065, -1052, -1039, -1026, -1013, -1000, -987, -974, -961, -948, -935, -922, -909, -896, -883, -870, -857, -844, -831, -818, -805, -792, -779, -766, -753, -740, -727, -714, -701, -688, -675, -662, -649, -636, -623, -610, -597, -584, +2124, +2111, +2098, +2085, +2072, +2059, +2046, +2033, +2020, +2007, +1994, +1981, +1968, +1955, +1942, +1929, +1916, +1903, +1890, +1877, +1864, +1851, +1838, +1825, +1812, +1799, +1786, +1773, +1760, +1747, +1734, +1721, +1708, +1695, +1682, +1669, +1656, +1643, +1630, +1617, +1604, +1591, +1578, +1565, +1552, +1539, +1526, +1513, +1500, +1487, +1474, +1461, +1448, +1435, +1422, +1409, +1396, +1383, +1370, +1357, +1344, +1331, +1318, +1305, +1292, +1279, +1266, +1253, +1240, +1227, +1214, +1201, +1188, +1175, +1162, +1149, +1136, +1123, +1110, +1097, +1084, diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/rom_freq_word.mif b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/rom_freq_word.mif index 355400b4..692cd517 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/rom_freq_word.mif +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/rom_freq_word.mif @@ -1,81 +1,81 @@ -11001011000 -11001001011 -11000111110 -11000110001 -11000100100 -11000010111 -11000001010 -10111111101 -10111110000 -10111100011 -10111010110 -10111001001 -10110111100 -10110101111 -10110100010 -10110010101 -10110001000 -10101111011 -10101101110 -10101100001 -10101010100 -10101000111 -10100111010 -10100101101 -10100100000 -10100010011 -10100000110 -10011111001 -10011101100 -10011011111 -10011010010 -10011000101 -10010111000 -10010101011 -10010011110 -10010010001 -10010000100 -10001110111 -10001101010 -10001011101 -10001010000 -10001000011 -10000110110 -10000101001 -10000011100 -10000001111 -10000000010 -01111110101 -01111101000 -01111011011 -01111001110 -01111000001 -01110110100 -01110100111 -01110011010 -01110001101 -01110000000 -01101110011 -01101100110 -01101011001 -01101001100 -01100111111 -01100110010 -01100100101 -01100011000 -01100001011 -01011111110 -01011110001 -01011100100 -01011010111 -01011001010 -01010111101 -01010110000 -01010100011 -01010010110 -01010001001 -01001111100 -01001101111 -01001100010 -01001010101 -01001001000 +100001001100 +100000111111 +100000110010 +100000100101 +100000011000 +100000001011 +011111111110 +011111110001 +011111100100 +011111010111 +011111001010 +011110111101 +011110110000 +011110100011 +011110010110 +011110001001 +011101111100 +011101101111 +011101100010 +011101010101 +011101001000 +011100111011 +011100101110 +011100100001 +011100010100 +011100000111 +011011111010 +011011101101 +011011100000 +011011010011 +011011000110 +011010111001 +011010101100 +011010011111 +011010010010 +011010000101 +011001111000 +011001101011 +011001011110 +011001010001 +011001000100 +011000110111 +011000101010 +011000011101 +011000010000 +011000000011 +010111110110 +010111101001 +010111011100 +010111001111 +010111000010 +010110110101 +010110101000 +010110011011 +010110001110 +010110000001 +010101110100 +010101100111 +010101011010 +010101001101 +010101000000 +010100110011 +010100100110 +010100011001 +010100001100 +010011111111 +010011110010 +010011100101 +010011011000 +010011001011 +010010111110 +010010110001 +010010100100 +010010010111 +010010001010 +010001111101 +010001110000 +010001100011 +010001010110 +010001001001 +010000111100 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/rom_freq_word.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/rom_freq_word.sh index aad4981f..22cb32fd 100755 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/rom_freq_word.sh +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/rom_freq_word.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Thu May 18 11:49:45 CST 2023 +# Generated by Vivado on Sun Jul 30 18:05:42 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/README.txt index 13d33d7c..33c0284f 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/README.txt +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Thu May 18 11:49:45 CST 2023 +# Generated by export_simulation on Sun Jul 30 18:05:42 CST 2023 # ################################################################################ diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/freq_word.coe b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/freq_word.coe index 590747a4..20ed79a7 100755 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/freq_word.coe +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/freq_word.coe @@ -1,83 +1,83 @@ MEMORY_INITIALIZATION_RADIX = 10; MEMORY_INITIALIZATION_VECTOR = -1624, -1611, -1598, -1585, -1572, -1559, -1546, -1533, -1520, -1507, -1494, -1481, -1468, -1455, -1442, -1429, -1416, -1403, -1390, -1377, -1364, -1351, -1338, -1325, -1312, -1299, -1286, -1273, -1260, -1247, -1234, -1221, -1208, -1195, -1182, -1169, -1156, -1143, -1130, -1117, -1104, -1091, -1078, -1065, -1052, -1039, -1026, -1013, -1000, -987, -974, -961, -948, -935, -922, -909, -896, -883, -870, -857, -844, -831, -818, -805, -792, -779, -766, -753, -740, -727, -714, -701, -688, -675, -662, -649, -636, -623, -610, -597, -584, +2124, +2111, +2098, +2085, +2072, +2059, +2046, +2033, +2020, +2007, +1994, +1981, +1968, +1955, +1942, +1929, +1916, +1903, +1890, +1877, +1864, +1851, +1838, +1825, +1812, +1799, +1786, +1773, +1760, +1747, +1734, +1721, +1708, +1695, +1682, +1669, +1656, +1643, +1630, +1617, +1604, +1591, +1578, +1565, +1552, +1539, +1526, +1513, +1500, +1487, +1474, +1461, +1448, +1435, +1422, +1409, +1396, +1383, +1370, +1357, +1344, +1331, +1318, +1305, +1292, +1279, +1266, +1253, +1240, +1227, +1214, +1201, +1188, +1175, +1162, +1149, +1136, +1123, +1110, +1097, +1084, diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/rom_freq_word.mif b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/rom_freq_word.mif index 355400b4..692cd517 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/rom_freq_word.mif +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/rom_freq_word.mif @@ -1,81 +1,81 @@ -11001011000 -11001001011 -11000111110 -11000110001 -11000100100 -11000010111 -11000001010 -10111111101 -10111110000 -10111100011 -10111010110 -10111001001 -10110111100 -10110101111 -10110100010 -10110010101 -10110001000 -10101111011 -10101101110 -10101100001 -10101010100 -10101000111 -10100111010 -10100101101 -10100100000 -10100010011 -10100000110 -10011111001 -10011101100 -10011011111 -10011010010 -10011000101 -10010111000 -10010101011 -10010011110 -10010010001 -10010000100 -10001110111 -10001101010 -10001011101 -10001010000 -10001000011 -10000110110 -10000101001 -10000011100 -10000001111 -10000000010 -01111110101 -01111101000 -01111011011 -01111001110 -01111000001 -01110110100 -01110100111 -01110011010 -01110001101 -01110000000 -01101110011 -01101100110 -01101011001 -01101001100 -01100111111 -01100110010 -01100100101 -01100011000 -01100001011 -01011111110 -01011110001 -01011100100 -01011010111 -01011001010 -01010111101 -01010110000 -01010100011 -01010010110 -01010001001 -01001111100 -01001101111 -01001100010 -01001010101 -01001001000 +100001001100 +100000111111 +100000110010 +100000100101 +100000011000 +100000001011 +011111111110 +011111110001 +011111100100 +011111010111 +011111001010 +011110111101 +011110110000 +011110100011 +011110010110 +011110001001 +011101111100 +011101101111 +011101100010 +011101010101 +011101001000 +011100111011 +011100101110 +011100100001 +011100010100 +011100000111 +011011111010 +011011101101 +011011100000 +011011010011 +011011000110 +011010111001 +011010101100 +011010011111 +011010010010 +011010000101 +011001111000 +011001101011 +011001011110 +011001010001 +011001000100 +011000110111 +011000101010 +011000011101 +011000010000 +011000000011 +010111110110 +010111101001 +010111011100 +010111001111 +010111000010 +010110110101 +010110101000 +010110011011 +010110001110 +010110000001 +010101110100 +010101100111 +010101011010 +010101001101 +010101000000 +010100110011 +010100100110 +010100011001 +010100001100 +010011111111 +010011110010 +010011100101 +010011011000 +010011001011 +010010111110 +010010110001 +010010100100 +010010010111 +010010001010 +010001111101 +010001110000 +010001100011 +010001010110 +010001001001 +010000111100 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/rom_freq_word.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/rom_freq_word.sh index d943a270..9b4558a1 100755 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/rom_freq_word.sh +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/rom_freq_word.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Thu May 18 11:49:45 CST 2023 +# Generated by Vivado on Sun Jul 30 18:05:42 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/README.txt index 76068bd4..0994464c 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/README.txt +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Thu May 18 11:49:45 CST 2023 +# Generated by export_simulation on Sun Jul 30 18:05:42 CST 2023 # ################################################################################ diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/file_info.txt index 78704c4b..8f86cd6a 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/file_info.txt +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/file_info.txt @@ -1,6 +1,6 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, -xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, -xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, rom_freq_word.v,verilog,xil_defaultlib,../../../ip/rom_freq_word/sim/rom_freq_word.v, glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/freq_word.coe b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/freq_word.coe index 590747a4..20ed79a7 100755 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/freq_word.coe +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/freq_word.coe @@ -1,83 +1,83 @@ MEMORY_INITIALIZATION_RADIX = 10; MEMORY_INITIALIZATION_VECTOR = -1624, -1611, -1598, -1585, -1572, -1559, -1546, -1533, -1520, -1507, -1494, -1481, -1468, -1455, -1442, -1429, -1416, -1403, -1390, -1377, -1364, -1351, -1338, -1325, -1312, -1299, -1286, -1273, -1260, -1247, -1234, -1221, -1208, -1195, -1182, -1169, -1156, -1143, -1130, -1117, -1104, -1091, -1078, -1065, -1052, -1039, -1026, -1013, -1000, -987, -974, -961, -948, -935, -922, -909, -896, -883, -870, -857, -844, -831, -818, -805, -792, -779, -766, -753, -740, -727, -714, -701, -688, -675, -662, -649, -636, -623, -610, -597, -584, +2124, +2111, +2098, +2085, +2072, +2059, +2046, +2033, +2020, +2007, +1994, +1981, +1968, +1955, +1942, +1929, +1916, +1903, +1890, +1877, +1864, +1851, +1838, +1825, +1812, +1799, +1786, +1773, +1760, +1747, +1734, +1721, +1708, +1695, +1682, +1669, +1656, +1643, +1630, +1617, +1604, +1591, +1578, +1565, +1552, +1539, +1526, +1513, +1500, +1487, +1474, +1461, +1448, +1435, +1422, +1409, +1396, +1383, +1370, +1357, +1344, +1331, +1318, +1305, +1292, +1279, +1266, +1253, +1240, +1227, +1214, +1201, +1188, +1175, +1162, +1149, +1136, +1123, +1110, +1097, +1084, diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/rom_freq_word.mif b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/rom_freq_word.mif index 355400b4..692cd517 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/rom_freq_word.mif +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/rom_freq_word.mif @@ -1,81 +1,81 @@ -11001011000 -11001001011 -11000111110 -11000110001 -11000100100 -11000010111 -11000001010 -10111111101 -10111110000 -10111100011 -10111010110 -10111001001 -10110111100 -10110101111 -10110100010 -10110010101 -10110001000 -10101111011 -10101101110 -10101100001 -10101010100 -10101000111 -10100111010 -10100101101 -10100100000 -10100010011 -10100000110 -10011111001 -10011101100 -10011011111 -10011010010 -10011000101 -10010111000 -10010101011 -10010011110 -10010010001 -10010000100 -10001110111 -10001101010 -10001011101 -10001010000 -10001000011 -10000110110 -10000101001 -10000011100 -10000001111 -10000000010 -01111110101 -01111101000 -01111011011 -01111001110 -01111000001 -01110110100 -01110100111 -01110011010 -01110001101 -01110000000 -01101110011 -01101100110 -01101011001 -01101001100 -01100111111 -01100110010 -01100100101 -01100011000 -01100001011 -01011111110 -01011110001 -01011100100 -01011010111 -01011001010 -01010111101 -01010110000 -01010100011 -01010010110 -01010001001 -01001111100 -01001101111 -01001100010 -01001010101 -01001001000 +100001001100 +100000111111 +100000110010 +100000100101 +100000011000 +100000001011 +011111111110 +011111110001 +011111100100 +011111010111 +011111001010 +011110111101 +011110110000 +011110100011 +011110010110 +011110001001 +011101111100 +011101101111 +011101100010 +011101010101 +011101001000 +011100111011 +011100101110 +011100100001 +011100010100 +011100000111 +011011111010 +011011101101 +011011100000 +011011010011 +011011000110 +011010111001 +011010101100 +011010011111 +011010010010 +011010000101 +011001111000 +011001101011 +011001011110 +011001010001 +011001000100 +011000110111 +011000101010 +011000011101 +011000010000 +011000000011 +010111110110 +010111101001 +010111011100 +010111001111 +010111000010 +010110110101 +010110101000 +010110011011 +010110001110 +010110000001 +010101110100 +010101100111 +010101011010 +010101001101 +010101000000 +010100110011 +010100100110 +010100011001 +010100001100 +010011111111 +010011110010 +010011100101 +010011011000 +010011001011 +010010111110 +010010110001 +010010100100 +010010010111 +010010001010 +010001111101 +010001110000 +010001100011 +010001010110 +010001001001 +010000111100 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/rom_freq_word.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/rom_freq_word.sh index 890369be..ed4bee5d 100755 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/rom_freq_word.sh +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/rom_freq_word.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Thu May 18 11:49:45 CST 2023 +# Generated by Vivado on Sun Jul 30 18:05:42 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/run.f b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/run.f index 7720194b..b275f819 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/run.f +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/run.f @@ -1,9 +1,9 @@ -makelib xcelium_lib/xil_defaultlib -sv \ - "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ - "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + "/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ -endlib -makelib xcelium_lib/xpm \ - "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + "/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ -endlib -makelib xcelium_lib/blk_mem_gen_v8_4_3 \ "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/README.txt index 13d33d7c..33c0284f 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/README.txt +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Thu May 18 11:49:45 CST 2023 +# Generated by export_simulation on Sun Jul 30 18:05:42 CST 2023 # ################################################################################ diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/freq_word.coe b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/freq_word.coe index 590747a4..20ed79a7 100755 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/freq_word.coe +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/freq_word.coe @@ -1,83 +1,83 @@ MEMORY_INITIALIZATION_RADIX = 10; MEMORY_INITIALIZATION_VECTOR = -1624, -1611, -1598, -1585, -1572, -1559, -1546, -1533, -1520, -1507, -1494, -1481, -1468, -1455, -1442, -1429, -1416, -1403, -1390, -1377, -1364, -1351, -1338, -1325, -1312, -1299, -1286, -1273, -1260, -1247, -1234, -1221, -1208, -1195, -1182, -1169, -1156, -1143, -1130, -1117, -1104, -1091, -1078, -1065, -1052, -1039, -1026, -1013, -1000, -987, -974, -961, -948, -935, -922, -909, -896, -883, -870, -857, -844, -831, -818, -805, -792, -779, -766, -753, -740, -727, -714, -701, -688, -675, -662, -649, -636, -623, -610, -597, -584, +2124, +2111, +2098, +2085, +2072, +2059, +2046, +2033, +2020, +2007, +1994, +1981, +1968, +1955, +1942, +1929, +1916, +1903, +1890, +1877, +1864, +1851, +1838, +1825, +1812, +1799, +1786, +1773, +1760, +1747, +1734, +1721, +1708, +1695, +1682, +1669, +1656, +1643, +1630, +1617, +1604, +1591, +1578, +1565, +1552, +1539, +1526, +1513, +1500, +1487, +1474, +1461, +1448, +1435, +1422, +1409, +1396, +1383, +1370, +1357, +1344, +1331, +1318, +1305, +1292, +1279, +1266, +1253, +1240, +1227, +1214, +1201, +1188, +1175, +1162, +1149, +1136, +1123, +1110, +1097, +1084, diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/rom_freq_word.mif b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/rom_freq_word.mif index 355400b4..692cd517 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/rom_freq_word.mif +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/rom_freq_word.mif @@ -1,81 +1,81 @@ -11001011000 -11001001011 -11000111110 -11000110001 -11000100100 -11000010111 -11000001010 -10111111101 -10111110000 -10111100011 -10111010110 -10111001001 -10110111100 -10110101111 -10110100010 -10110010101 -10110001000 -10101111011 -10101101110 -10101100001 -10101010100 -10101000111 -10100111010 -10100101101 -10100100000 -10100010011 -10100000110 -10011111001 -10011101100 -10011011111 -10011010010 -10011000101 -10010111000 -10010101011 -10010011110 -10010010001 -10010000100 -10001110111 -10001101010 -10001011101 -10001010000 -10001000011 -10000110110 -10000101001 -10000011100 -10000001111 -10000000010 -01111110101 -01111101000 -01111011011 -01111001110 -01111000001 -01110110100 -01110100111 -01110011010 -01110001101 -01110000000 -01101110011 -01101100110 -01101011001 -01101001100 -01100111111 -01100110010 -01100100101 -01100011000 -01100001011 -01011111110 -01011110001 -01011100100 -01011010111 -01011001010 -01010111101 -01010110000 -01010100011 -01010010110 -01010001001 -01001111100 -01001101111 -01001100010 -01001010101 -01001001000 +100001001100 +100000111111 +100000110010 +100000100101 +100000011000 +100000001011 +011111111110 +011111110001 +011111100100 +011111010111 +011111001010 +011110111101 +011110110000 +011110100011 +011110010110 +011110001001 +011101111100 +011101101111 +011101100010 +011101010101 +011101001000 +011100111011 +011100101110 +011100100001 +011100010100 +011100000111 +011011111010 +011011101101 +011011100000 +011011010011 +011011000110 +011010111001 +011010101100 +011010011111 +011010010010 +011010000101 +011001111000 +011001101011 +011001011110 +011001010001 +011001000100 +011000110111 +011000101010 +011000011101 +011000010000 +011000000011 +010111110110 +010111101001 +010111011100 +010111001111 +010111000010 +010110110101 +010110101000 +010110011011 +010110001110 +010110000001 +010101110100 +010101100111 +010101011010 +010101001101 +010101000000 +010100110011 +010100100110 +010100011001 +010100001100 +010011111111 +010011110010 +010011100101 +010011011000 +010011001011 +010010111110 +010010110001 +010010100100 +010010010111 +010010001010 +010001111101 +010001110000 +010001100011 +010001010110 +010001001001 +010000111100 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/rom_freq_word.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/rom_freq_word.sh index 21276799..359e3430 100755 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/rom_freq_word.sh +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/rom_freq_word.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Thu May 18 11:49:45 CST 2023 +# Generated by Vivado on Sun Jul 30 18:05:42 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. @@ -22,7 +22,7 @@ #********************************************************************************************************* # Command line options -xv_boost_lib_path=/tools/Xilinx/Vivado/2019.1/tps/boost_1_64_0 +xv_boost_lib_path=/home/josh/Software/Xilinx/Vivado/2019.1/tps/boost_1_64_0 xvlog_opts="--relax" @@ -92,7 +92,7 @@ setup() copy_setup_file() { file="xsim.ini" - lib_map_path="/tools/Xilinx/Vivado/2019.1/data/xsim" + lib_map_path="/home/josh/Software/Xilinx/Vivado/2019.1/data/xsim" if [[ ($1 != "") ]]; then lib_map_path="$1" fi diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/activehdl/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/activehdl/README.txt index a4eb3478..1f3c23fe 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/activehdl/README.txt +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/activehdl/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Mon Jul 03 19:45:40 CST 2023 +# Generated by export_simulation on Sun Jul 30 18:20:24 CST 2023 # ################################################################################ diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/activehdl/vio_RF_control.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/activehdl/vio_RF_control.sh index e2cb0877..e2933a5e 100755 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/activehdl/vio_RF_control.sh +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/activehdl/vio_RF_control.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon Jul 03 19:45:40 CST 2023 +# Generated by Vivado on Sun Jul 30 18:20:24 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/ies/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/ies/README.txt index aae61794..3d8008db 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/ies/README.txt +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/ies/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Mon Jul 03 19:45:40 CST 2023 +# Generated by export_simulation on Sun Jul 30 18:20:24 CST 2023 # ################################################################################ diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/ies/vio_RF_control.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/ies/vio_RF_control.sh index 751d965d..2af0a932 100755 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/ies/vio_RF_control.sh +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/ies/vio_RF_control.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon Jul 03 19:45:40 CST 2023 +# Generated by Vivado on Sun Jul 30 18:20:24 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/modelsim/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/modelsim/README.txt index a4eb3478..1f3c23fe 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/modelsim/README.txt +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/modelsim/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Mon Jul 03 19:45:40 CST 2023 +# Generated by export_simulation on Sun Jul 30 18:20:24 CST 2023 # ################################################################################ diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/modelsim/vio_RF_control.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/modelsim/vio_RF_control.sh index 1e9ea471..72381a6e 100755 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/modelsim/vio_RF_control.sh +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/modelsim/vio_RF_control.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon Jul 03 19:45:40 CST 2023 +# Generated by Vivado on Sun Jul 30 18:20:24 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/questa/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/questa/README.txt index a4eb3478..1f3c23fe 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/questa/README.txt +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/questa/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Mon Jul 03 19:45:40 CST 2023 +# Generated by export_simulation on Sun Jul 30 18:20:24 CST 2023 # ################################################################################ diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/questa/vio_RF_control.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/questa/vio_RF_control.sh index 2474d59a..83d30908 100755 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/questa/vio_RF_control.sh +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/questa/vio_RF_control.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon Jul 03 19:45:40 CST 2023 +# Generated by Vivado on Sun Jul 30 18:20:24 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/riviera/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/riviera/README.txt index a4eb3478..1f3c23fe 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/riviera/README.txt +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/riviera/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Mon Jul 03 19:45:40 CST 2023 +# Generated by export_simulation on Sun Jul 30 18:20:24 CST 2023 # ################################################################################ diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/riviera/vio_RF_control.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/riviera/vio_RF_control.sh index 3cdb9372..15978e12 100755 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/riviera/vio_RF_control.sh +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/riviera/vio_RF_control.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon Jul 03 19:45:40 CST 2023 +# Generated by Vivado on Sun Jul 30 18:20:24 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/vcs/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/vcs/README.txt index a4eb3478..1f3c23fe 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/vcs/README.txt +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/vcs/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Mon Jul 03 19:45:40 CST 2023 +# Generated by export_simulation on Sun Jul 30 18:20:24 CST 2023 # ################################################################################ diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/vcs/vio_RF_control.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/vcs/vio_RF_control.sh index 49685cc8..a3ecd1a4 100755 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/vcs/vio_RF_control.sh +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/vcs/vio_RF_control.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon Jul 03 19:45:40 CST 2023 +# Generated by Vivado on Sun Jul 30 18:20:24 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/xcelium/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/xcelium/README.txt index aae61794..3d8008db 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/xcelium/README.txt +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/xcelium/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Mon Jul 03 19:45:40 CST 2023 +# Generated by export_simulation on Sun Jul 30 18:20:24 CST 2023 # ################################################################################ diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/xcelium/vio_RF_control.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/xcelium/vio_RF_control.sh index b648b8b3..5fbed3e6 100755 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/xcelium/vio_RF_control.sh +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/xcelium/vio_RF_control.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon Jul 03 19:45:40 CST 2023 +# Generated by Vivado on Sun Jul 30 18:20:24 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/xsim/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/xsim/README.txt index a4eb3478..1f3c23fe 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/xsim/README.txt +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/xsim/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Mon Jul 03 19:45:40 CST 2023 +# Generated by export_simulation on Sun Jul 30 18:20:24 CST 2023 # ################################################################################ diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/xsim/vio_RF_control.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/xsim/vio_RF_control.sh index ca3e934e..75ace5f8 100755 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/xsim/vio_RF_control.sh +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_RF_control/xsim/vio_RF_control.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Mon Jul 03 19:45:40 CST 2023 +# Generated by Vivado on Sun Jul 30 18:20:24 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/7727187e03eca7b1/7727187e03eca7b1.xci b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/7727187e03eca7b1/7727187e03eca7b1.xci new file mode 100644 index 00000000..42484ba9 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/7727187e03eca7b1/7727187e03eca7b1.xci @@ -0,0 +1,109 @@ + + + xilinx.com + ipcache + 7727187e03eca7b1 + 0 + + + rom_freq_word + + + 100000000 + 4 + Memory_Slave + AXI4_Full + false + Minimum_Area + false + 9 + NONE + ../coe/freq_word.coe + ALL + rom_freq_word + false + false + false + false + false + false + false + false + false + Always_Enabled + Always_Enabled + Single_Bit_Error_Injection + false + Native + true + no_mem_loaded + Single_Port_ROM + WRITE_FIRST + WRITE_FIRST + 0 + 0 + BRAM + 0 + 100 + 100 + 0 + 0 + 0 + 0 + 8kx2 + false + false + 1 + 1 + 12 + 12 + false + true + false + false + 0 + false + false + CE + CE + SYNC + false + false + false + false + false + false + false + 81 + 12 + 12 + No_ECC + false + false + false + Stand_Alone + zynq + xc7z100 + ffg900 + VERILOG + + -2 + + + TRUE + TRUE + 7727187e03eca7b1 + 0137cb81 + 42 + IP_Unknown + 3 + TRUE + . + + . + 2019.1.3 + GLOBAL + + + + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/7727187e03eca7b1/rom_freq_word.dcp b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/7727187e03eca7b1/rom_freq_word.dcp new file mode 100644 index 00000000..d1cd5903 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/7727187e03eca7b1/rom_freq_word.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:ead1c780a97c4122a92b021f7372d831f9571146dd8584c6a6edfc26a4c2e717 +size 26117 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/7727187e03eca7b1/rom_freq_word_sim_netlist.v b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/7727187e03eca7b1/rom_freq_word_sim_netlist.v new file mode 100755 index 00000000..3d9b1c6f --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/7727187e03eca7b1/rom_freq_word_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:7281c39c833ad9d6c352b643dc5fd875cb45a630aca6072a0800908e6faff0d3 +size 28848 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/7727187e03eca7b1/rom_freq_word_sim_netlist.vhdl b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/7727187e03eca7b1/rom_freq_word_sim_netlist.vhdl new file mode 100755 index 00000000..c0928e76 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/7727187e03eca7b1/rom_freq_word_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:3ed6556f45a525eea4607939c5ee720ae7993f5fb0ef8e375b31cde70fa1ddf7 +size 44656 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/7727187e03eca7b1/rom_freq_word_stub.v b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/7727187e03eca7b1/rom_freq_word_stub.v new file mode 100755 index 00000000..b2a4eb43 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/7727187e03eca7b1/rom_freq_word_stub.v @@ -0,0 +1,22 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Sun Jul 30 18:06:27 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ rom_freq_word_stub.v +// Design : rom_freq_word +// Purpose : Stub declaration of top-level module interface +// Device : xc7z100ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "blk_mem_gen_v8_4_3,Vivado 2019.1.3" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clka, addra, douta) +/* synthesis syn_black_box black_box_pad_pin="clka,addra[6:0],douta[11:0]" */; + input clka; + input [6:0]addra; + output [11:0]douta; +endmodule diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/7727187e03eca7b1/rom_freq_word_stub.vhdl b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/7727187e03eca7b1/rom_freq_word_stub.vhdl new file mode 100755 index 00000000..e12cf09b --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/7727187e03eca7b1/rom_freq_word_stub.vhdl @@ -0,0 +1,32 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Sun Jul 30 18:06:27 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ rom_freq_word_stub.vhdl +-- Design : rom_freq_word +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + Port ( + clka : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR ( 6 downto 0 ); + douta : out STD_LOGIC_VECTOR ( 11 downto 0 ) + ); + +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clka,addra[6:0],douta[11:0]"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_3,Vivado 2019.1.3"; +begin +end; diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/e8e950360ca1fe60/e8e950360ca1fe60.xci b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/e8e950360ca1fe60/e8e950360ca1fe60.xci new file mode 100644 index 00000000..a0a7cc95 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/e8e950360ca1fe60/e8e950360ca1fe60.xci @@ -0,0 +1,810 @@ + + + xilinx.com + ipcache + e8e950360ca1fe60 + 0 + + + vio_RF_control + + + 100000000 + 0 + 1 + 1 + 16 + 12 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b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/e8e950360ca1fe60/vio_RF_control.dcp new file mode 100644 index 00000000..ba572106 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/e8e950360ca1fe60/vio_RF_control.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:8b224fea49a2b5f07d37a64ac4cb645fe5678f99412b881ffe5ec475e8900530 +size 190030 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/e8e950360ca1fe60/vio_RF_control_sim_netlist.v b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/e8e950360ca1fe60/vio_RF_control_sim_netlist.v new file mode 100755 index 00000000..5532d0f4 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/e8e950360ca1fe60/vio_RF_control_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:def8a2ddef014eac2de886f3db5388c7c9ec7fab5fc2cd7270077df8bcf4931f +size 425442 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/e8e950360ca1fe60/vio_RF_control_sim_netlist.vhdl b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/e8e950360ca1fe60/vio_RF_control_sim_netlist.vhdl new file mode 100755 index 00000000..e13b595a --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/e8e950360ca1fe60/vio_RF_control_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:7ae2081ef4b8b321f8b25db8222b2b6419e9fd721e1fdbe7e07e3249c7160cd9 +size 773741 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/e8e950360ca1fe60/vio_RF_control_stub.v b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/e8e950360ca1fe60/vio_RF_control_stub.v new file mode 100755 index 00000000..c0c3cbbd --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/e8e950360ca1fe60/vio_RF_control_stub.v @@ -0,0 +1,39 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Sun Jul 30 18:20:41 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_RF_control_stub.v +// Design : vio_RF_control +// Purpose : Stub declaration of top-level module interface +// Device : xc7z100ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "vio,Vivado 2019.1.3" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe_in0, probe_out0, probe_out1, + probe_out2, probe_out3, probe_out4, probe_out5, probe_out6, probe_out7, probe_out8, probe_out9, + probe_out10, probe_out11, probe_out12, probe_out13, probe_out14, probe_out15) +/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[11:0],probe_out0[0:0],probe_out1[1:0],probe_out2[0:0],probe_out3[7:0],probe_out4[7:0],probe_out5[11:0],probe_out6[0:0],probe_out7[0:0],probe_out8[0:0],probe_out9[0:0],probe_out10[0:0],probe_out11[0:0],probe_out12[0:0],probe_out13[31:0],probe_out14[0:0],probe_out15[31:0]" */; + input clk; + input [11:0]probe_in0; + output [0:0]probe_out0; + output [1:0]probe_out1; + output [0:0]probe_out2; + output [7:0]probe_out3; + output [7:0]probe_out4; + output [11:0]probe_out5; + output [0:0]probe_out6; + output [0:0]probe_out7; + output [0:0]probe_out8; + output [0:0]probe_out9; + output [0:0]probe_out10; + output [0:0]probe_out11; + output [0:0]probe_out12; + output [31:0]probe_out13; + output [0:0]probe_out14; + output [31:0]probe_out15; +endmodule diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/e8e950360ca1fe60/vio_RF_control_stub.vhdl b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/e8e950360ca1fe60/vio_RF_control_stub.vhdl new file mode 100755 index 00000000..1371ef31 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/e8e950360ca1fe60/vio_RF_control_stub.vhdl @@ -0,0 +1,47 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Sun Jul 30 18:20:41 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_RF_control_stub.vhdl +-- Design : vio_RF_control +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + Port ( + clk : in STD_LOGIC; + probe_in0 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out1 : out STD_LOGIC_VECTOR ( 1 downto 0 ); + probe_out2 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out3 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + probe_out4 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + probe_out5 : out STD_LOGIC_VECTOR ( 11 downto 0 ); + probe_out6 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out7 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out8 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out9 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out10 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out11 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out12 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out13 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + probe_out14 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out15 : out STD_LOGIC_VECTOR ( 31 downto 0 ) + ); + +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[11:0],probe_out0[0:0],probe_out1[1:0],probe_out2[0:0],probe_out3[7:0],probe_out4[7:0],probe_out5[11:0],probe_out6[0:0],probe_out7[0:0],probe_out8[0:0],probe_out9[0:0],probe_out10[0:0],probe_out11[0:0],probe_out12[0:0],probe_out13[31:0],probe_out14[0:0],probe_out15[31:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3"; +begin +end; diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/wt/gui_handlers.wdf b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/wt/gui_handlers.wdf index c9f87a9b..b10cb89c 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/wt/gui_handlers.wdf +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/wt/gui_handlers.wdf @@ -1,13 +1,14 @@ version:1 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70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7372636d656e755f69705f646f63756d656e746174696f6e:32:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73796e7468657469636167657474696e6773746172746564766965775f726563656e745f69705f6c6f636174696f6e73:38:00:00 -eof:3676694193 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73796e7468657469636167657474696e6773746172746564766965775f726563656e745f70726f6a65637473:31:00:00 +eof:3632338426 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/wt/java_command_handlers.wdf b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/wt/java_command_handlers.wdf index 5a44be7b..ce1c2a2f 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/wt/java_command_handlers.wdf +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/wt/java_command_handlers.wdf @@ -4,7 +4,7 @@ version:1 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6564697464656c657465:34:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6d616e616765636f6d706f7369746574617267657473:37:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657769706c6f636174696f6e68616e646c6572:31:00:00 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e69706c6f636174696f6e68616e646c6572:32:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e69706c6f636174696f6e68616e646c6572:34:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e70726576696f7573697068616e646c6572:38:00:00 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7265637573746f6d697a65636f7265:3131:00:00 -eof:2683708577 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7265637573746f6d697a65636f7265:3134:00:00 +eof:309752714 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/wt/project.wpc b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/wt/project.wpc index 24316b6b..f29bf625 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/wt/project.wpc +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/wt/project.wpc @@ -1,3 +1,3 @@ version:1 -6d6f64655f636f756e7465727c4755494d6f6465:11 +6d6f64655f636f756e7465727c4755494d6f6465:13 eof: diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/wt/synthesis.wdf b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/wt/synthesis.wdf index 02158322..d75c3cd0 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/wt/synthesis.wdf +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/wt/synthesis.wdf @@ -1,7 +1,7 @@ version:1 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:7863377a3130306666673930302d32:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 -73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:696c615f72665f74657374:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:76696f5f52465f636f6e74726f6c:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e636c7564655f64697273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67656e65726963:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d766572696c6f675f646566696e65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 @@ -33,7 +33,7 @@ version:1 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d617373657274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 -73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a343973:00:00 -73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:323332392e3038364d42:00:00 -73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3931312e3232334d42:00:00 -eof:2301228565 +73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a313173:00:00 +73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:323131342e3039384d42:00:00 +73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3730392e3733304d42:00:00 +eof:1038723330 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/wt/webtalk_pa.xml b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/wt/webtalk_pa.xml index a8d96beb..20d7e337 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/wt/webtalk_pa.xml +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/wt/webtalk_pa.xml @@ -3,7 +3,7 @@ - +
@@ -22,20 +22,21 @@ This means code written to parse this file will need to be revisited each subseq - + - + - + - - - + + + - + + @@ -52,21 +53,23 @@ This means code written to parse this file will need to be revisited each subseq - + + - + + - + - +
diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_8.xml b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_8.xml new file mode 100644 index 00000000..a734ec6b --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_8.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_9.xml b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_9.xml new file mode 100644 index 00000000..5fb1e7b9 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_9.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/.Vivado_Synthesis.queue.rst b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/.Vivado_Synthesis.queue.rst similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/.Vivado_Synthesis.queue.rst rename to projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/.Vivado_Synthesis.queue.rst diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/.vivado.begin.rst b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/.vivado.begin.rst similarity index 75% rename from projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/.vivado.begin.rst rename to projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/.vivado.begin.rst index 28ef12b8..6954548e 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/.vivado.begin.rst +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/.vivado.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/.vivado.end.rst b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/.vivado.end.rst similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/.vivado.end.rst rename to projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/.vivado.end.rst diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/ISEWrap.js b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/ISEWrap.js similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/ISEWrap.js rename to projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/ISEWrap.js diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/ISEWrap.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/ISEWrap.sh similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/ISEWrap.sh rename to projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/ISEWrap.sh diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/__synthesis_is_complete__ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/__synthesis_is_complete__ similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/__synthesis_is_complete__ rename to projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/__synthesis_is_complete__ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/dont_touch.xdc b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/dont_touch.xdc similarity index 61% rename from projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/dont_touch.xdc rename to projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/dont_touch.xdc index d3db8d08..3a0b1816 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/dont_touch.xdc +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/dont_touch.xdc @@ -1,16 +1,16 @@ # This file is automatically generated. # It contains project source information necessary for synthesis and implementation. -# IP: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/rom_freq_word/rom_freq_word.xci +# IP: /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/rom_freq_word/rom_freq_word.xci # IP: The module: 'rom_freq_word' is the root of the design. Do not add the DONT_TOUCH constraint. -# XDC: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/rom_freq_word/rom_freq_word_ooc.xdc +# XDC: /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/rom_freq_word/rom_freq_word_ooc.xdc # XDC: The top module name and the constraint reference have the same name: 'rom_freq_word'. Do not add the DONT_TOUCH constraint. set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet -# IP: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/rom_freq_word/rom_freq_word.xci +# IP: /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/rom_freq_word/rom_freq_word.xci # IP: The module: 'rom_freq_word' is the root of the design. Do not add the DONT_TOUCH constraint. -# XDC: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/rom_freq_word/rom_freq_word_ooc.xdc +# XDC: /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/rom_freq_word/rom_freq_word_ooc.xdc # XDC: The top module name and the constraint reference have the same name: 'rom_freq_word'. Do not add the DONT_TOUCH constraint. #dup# set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/gen_run.xml b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/gen_run.xml similarity index 96% rename from projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/gen_run.xml rename to projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/gen_run.xml index c67d0fda..2abaf015 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/gen_run.xml +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/gen_run.xml @@ -1,20 +1,20 @@ - + + + + - - - - + - + @@ -27,14 +27,14 @@ - + - + diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/htr.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/htr.txt similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/htr.txt rename to projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/htr.txt diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/project.wdf b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/project.wdf similarity index 64% rename from projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/project.wdf rename to projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/project.wdf index dba90573..bc5a0185 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/project.wdf +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/project.wdf @@ -1,30 +1,25 @@ version:1 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:35:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:3132:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 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70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f6d616e75616c5f6374726c:636f72655f636f6e7461696e6572:74727565:00:00 -70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f7266636f6e74726c:636f72655f636f6e7461696e6572:74727565:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:30:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00 @@ -32,12 +27,12 @@ version:1 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:3631:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:3631:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:3631:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:3631:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:3631:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3631:00:00 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+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3234:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3234:00:00 +5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3665393633363431666561663437633339616462383862306139303537636232:506172656e742050412070726f6a656374204944:00 +eof:1369190430 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word.dcp b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word.dcp new file mode 100644 index 00000000..b3dd13a8 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:81e2e89272016bfc4babe89e8e58951184888159333051731a9ef57b462fe2e2 +size 26308 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word.tcl b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word.tcl similarity index 57% rename from projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word.tcl rename to projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word.tcl index 1be7c4d0..93895603 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word.tcl +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word.tcl @@ -18,24 +18,24 @@ proc create_report { reportName command } { } } set_param simulator.modelsimInstallPath /home/josh/Software/Mentor/modeltech/bin -set_param simulator.vcsmxInstallPath /usr/synopsys/vcs/T-2022.06/bin +set_param simulator.vcsmxInstallPath /home/josh/Software/Synopsys/vcs/T-2022.06/bin set_param project.vivado.isBlockSynthRun true set_msg_config -msgmgr_mode ooc_run -create_project -in_memory -part xc7k410tffg900-2 +create_project -in_memory -part xc7z100ffg900-2 set_param project.singleFileAddWarning.threshold 0 set_param project.compositeFile.enableAutoGeneration 0 set_param synth.vivado.isSynthRun true set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info -set_property webtalk.parent_dir /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/wt [current_project] -set_property parent.project_path /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.xpr [current_project] +set_property webtalk.parent_dir /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/wt [current_project] +set_property parent.project_path /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.xpr [current_project] set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project] set_property default_lib xil_defaultlib [current_project] set_property target_language Verilog [current_project] -set_property ip_output_repo /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip [current_project] +set_property ip_output_repo /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip [current_project] set_property ip_cache_permissions {read write} [current_project] -read_ip -quiet /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/rom_freq_word/rom_freq_word.xci -set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/rom_freq_word/rom_freq_word_ooc.xdc] +read_ip -quiet /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/rom_freq_word/rom_freq_word.xci +set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/rom_freq_word/rom_freq_word_ooc.xdc] # Mark all dcp files as not used in implementation to prevent them from being # stitched into the results of this synthesis run. Any black boxes in the @@ -49,12 +49,12 @@ read_xdc dont_touch.xdc set_property used_in_implementation false [get_files dont_touch.xdc] set_param ips.enableIPCacheLiteLoad 1 -set cached_ip [config_ip_cache -export -no_bom -dir /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1 -new_name rom_freq_word -ip [get_ips rom_freq_word]] +set cached_ip [config_ip_cache -export -no_bom -dir /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1 -new_name rom_freq_word -ip [get_ips rom_freq_word]] if { $cached_ip eq {} } { close [open __synthesis_is_running__ w] -synth_design -top rom_freq_word -part xc7k410tffg900-2 -mode out_of_context +synth_design -top rom_freq_word -part xc7z100ffg900-2 -mode out_of_context #--------------------------------------------------------- # Generate Checkpoint/Stub/Simulation Files For IP Cache @@ -90,25 +90,25 @@ write_checkpoint -force -noxdef rom_freq_word.dcp create_report "rom_freq_word_synth_1_synth_report_utilization_0" "report_utilization -file rom_freq_word_utilization_synth.rpt -pb rom_freq_word_utilization_synth.pb" if { [catch { - write_verilog -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.v + write_verilog -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - write_vhdl -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.vhdl + write_vhdl -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" } if { [catch { - write_verilog -force -mode funcsim /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_sim_netlist.v + write_verilog -force -mode funcsim /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_sim_netlist.v } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } if { [catch { - write_vhdl -force -mode funcsim /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_sim_netlist.vhdl + write_vhdl -force -mode funcsim /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_sim_netlist.vhdl } _RESULT ] } { puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" } @@ -119,37 +119,37 @@ if { [catch { }; # end if cached_ip -add_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/rom_freq_word/rom_freq_word.xci] +add_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/rom_freq_word/rom_freq_word.xci] -add_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/rom_freq_word/rom_freq_word.xci] +add_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/rom_freq_word/rom_freq_word.xci] -add_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_sim_netlist.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/rom_freq_word/rom_freq_word.xci] +add_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_sim_netlist.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/rom_freq_word/rom_freq_word.xci] -add_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_sim_netlist.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/rom_freq_word/rom_freq_word.xci] +add_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_sim_netlist.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/rom_freq_word/rom_freq_word.xci] -add_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word.dcp -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/rom_freq_word/rom_freq_word.xci] +add_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word.dcp -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/rom_freq_word/rom_freq_word.xci] -if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/rom_freq_word]} { +if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/rom_freq_word]} { catch { - file copy -force /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_sim_netlist.v /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/rom_freq_word + file copy -force /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_sim_netlist.v /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/rom_freq_word } } -if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/rom_freq_word]} { +if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/rom_freq_word]} { catch { - file copy -force /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_sim_netlist.vhdl /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/rom_freq_word + file copy -force /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_sim_netlist.vhdl /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/rom_freq_word } } -if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/rom_freq_word]} { +if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/rom_freq_word]} { catch { - file copy -force /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.v /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/rom_freq_word + file copy -force /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.v /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/rom_freq_word } } -if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/rom_freq_word]} { +if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/rom_freq_word]} { catch { - file copy -force /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.vhdl /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/rom_freq_word + file copy -force /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.vhdl /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/rom_freq_word } } file delete __synthesis_is_running__ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word.vds b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word.vds similarity index 82% rename from projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word.vds rename to projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word.vds index c05ca12b..dc369c8a 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word.vds +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word.vds @@ -2,27 +2,27 @@ # Vivado v2019.1.3 (64-bit) # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Fri May 12 16:05:33 2023 -# Process ID: 1476113 -# Current directory: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1 +# Start of session at: Sun Jul 30 18:05:42 2023 +# Process ID: 1394945 +# Current directory: /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1 # Command line: vivado -log rom_freq_word.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source rom_freq_word.tcl -# Log file: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word.vds -# Journal file: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/vivado.jou +# Log file: /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word.vds +# Journal file: /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/vivado.jou #----------------------------------------------------------- source rom_freq_word.tcl -notrace -Command: synth_design -top rom_freq_word -part xc7k410tffg900-2 -mode out_of_context +Command: synth_design -top rom_freq_word -part xc7z100ffg900-2 -mode out_of_context Starting synth_design -Attempting to get a license for feature 'Synthesis' and/or device 'xc7k410t' -INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k410t' -INFO: [Device 21-403] Loading part xc7k410tffg900-2 +Attempting to get a license for feature 'Synthesis' and/or device 'xc7z100' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z100' +INFO: [Device 21-403] Loading part xc7z100ffg900-2 INFO: Launching helper process for spawning children vivado processes -INFO: Helper process launched with PID 1476273 +INFO: Helper process launched with PID 1395030 --------------------------------------------------------------------------------- -Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 1824.465 ; gain = 150.719 ; free physical = 851 ; free virtual = 44252 +Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 1855.629 ; gain = 153.719 ; free physical = 1673 ; free virtual = 32470 --------------------------------------------------------------------------------- -INFO: [Synth 8-638] synthesizing module 'rom_freq_word' [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/rom_freq_word/synth/rom_freq_word.vhd:67] - Parameter C_FAMILY bound to: kintex7 - type: string - Parameter C_XDEVICEFAMILY bound to: kintex7 - type: string +INFO: [Synth 8-638] synthesizing module 'rom_freq_word' [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/rom_freq_word/synth/rom_freq_word.vhd:67] + Parameter C_FAMILY bound to: zynq - type: string + Parameter C_XDEVICEFAMILY bound to: zynq - type: string Parameter C_ELABORATION_DIR bound to: ./ - type: string Parameter C_INTERFACE_TYPE bound to: 0 - type: integer Parameter C_AXI_TYPE bound to: 1 - type: integer @@ -50,8 +50,8 @@ INFO: [Synth 8-638] synthesizing module 'rom_freq_word' [/home/josh/Workspace/vi Parameter C_USE_BYTE_WEA bound to: 0 - type: integer Parameter C_WEA_WIDTH bound to: 1 - type: integer Parameter C_WRITE_MODE_A bound to: WRITE_FIRST - type: string - Parameter C_WRITE_WIDTH_A bound to: 16 - type: integer - Parameter C_READ_WIDTH_A bound to: 16 - type: integer + Parameter C_WRITE_WIDTH_A bound to: 12 - type: integer + Parameter C_READ_WIDTH_A bound to: 12 - type: integer Parameter C_WRITE_DEPTH_A bound to: 81 - type: integer Parameter C_READ_DEPTH_A bound to: 81 - type: integer Parameter C_ADDRA_WIDTH bound to: 7 - type: integer @@ -64,8 +64,8 @@ INFO: [Synth 8-638] synthesizing module 'rom_freq_word' [/home/josh/Workspace/vi Parameter C_USE_BYTE_WEB bound to: 0 - type: integer Parameter C_WEB_WIDTH bound to: 1 - type: integer Parameter C_WRITE_MODE_B bound to: WRITE_FIRST - type: string - Parameter C_WRITE_WIDTH_B bound to: 16 - type: integer - Parameter C_READ_WIDTH_B bound to: 16 - type: integer + Parameter C_WRITE_WIDTH_B bound to: 12 - type: integer + Parameter C_READ_WIDTH_B bound to: 12 - type: integer Parameter C_WRITE_DEPTH_B bound to: 81 - type: integer Parameter C_READ_DEPTH_B bound to: 81 - type: integer Parameter C_ADDRB_WIDTH bound to: 7 - type: integer @@ -95,9 +95,9 @@ INFO: [Synth 8-638] synthesizing module 'rom_freq_word' [/home/josh/Workspace/vi Parameter C_DISABLE_WARN_BHV_RANGE bound to: 0 - type: integer Parameter C_COUNT_36K_BRAM bound to: 0 - type: string Parameter C_COUNT_18K_BRAM bound to: 1 - type: string - Parameter C_EST_POWER_SUMMARY bound to: Estimated Power for IP : 2.7096 mW - type: string -INFO: [Synth 8-3491] module 'blk_mem_gen_v8_4_3' declared at '/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/rom_freq_word/hdl/blk_mem_gen_v8_4_vhsyn_rfs.vhd:195321' bound to instance 'U0' of component 'blk_mem_gen_v8_4_3' [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/rom_freq_word/synth/rom_freq_word.vhd:230] -INFO: [Synth 8-256] done synthesizing module 'rom_freq_word' (9#1) [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/rom_freq_word/synth/rom_freq_word.vhd:67] + Parameter C_EST_POWER_SUMMARY bound to: Estimated Power for IP : 2.5432 mW - type: string +INFO: [Synth 8-3491] module 'blk_mem_gen_v8_4_3' declared at '/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/rom_freq_word/hdl/blk_mem_gen_v8_4_vhsyn_rfs.vhd:195321' bound to instance 'U0' of component 'blk_mem_gen_v8_4_3' [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/rom_freq_word/synth/rom_freq_word.vhd:230] +INFO: [Synth 8-256] done synthesizing module 'rom_freq_word' (9#1) [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/rom_freq_word/synth/rom_freq_word.vhd:67] WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port SSRA WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port CLKB WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port SSRB @@ -162,10 +162,6 @@ WARNING: [Synth 8-3331] design blk_mem_gen_generic_cstr has unconnected port WEB WARNING: [Synth 8-3331] design blk_mem_gen_generic_cstr has unconnected port INJECTSBITERR WARNING: [Synth 8-3331] design blk_mem_gen_generic_cstr has unconnected port INJECTDBITERR WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port CLKB -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[15] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[14] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[13] -WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[12] WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[11] WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[10] WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[9] @@ -191,16 +187,20 @@ WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port RSTA WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port ENA WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port REGCEA WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port WEA[0] -WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port DINA[15] -WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port DINA[14] -WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port DINA[13] -WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port DINA[12] WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port DINA[11] WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port DINA[10] WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port DINA[9] +WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port DINA[8] +WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port DINA[7] +WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port DINA[6] +WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port DINA[5] +WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port DINA[4] +WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port DINA[3] +WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port DINA[2] +WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port DINA[1] INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- -Finished RTL Elaboration : Time (s): cpu = 00:00:27 ; elapsed = 00:00:32 . Memory (MB): peak = 2038.176 ; gain = 364.430 ; free physical = 1600 ; free virtual = 45063 +Finished RTL Elaboration : Time (s): cpu = 00:00:27 ; elapsed = 00:00:32 . Memory (MB): peak = 2072.309 ; gain = 370.398 ; free physical = 1652 ; free virtual = 32450 --------------------------------------------------------------------------------- Report Check Netlist: @@ -213,10 +213,10 @@ Report Check Netlist: Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:27 ; elapsed = 00:00:32 . Memory (MB): peak = 2050.051 ; gain = 376.305 ; free physical = 1621 ; free virtual = 45083 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:27 ; elapsed = 00:00:32 . Memory (MB): peak = 2081.215 ; gain = 379.305 ; free physical = 1654 ; free virtual = 32452 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:27 ; elapsed = 00:00:32 . Memory (MB): peak = 2050.051 ; gain = 376.305 ; free physical = 1621 ; free virtual = 45083 +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:27 ; elapsed = 00:00:32 . Memory (MB): peak = 2081.215 ; gain = 379.305 ; free physical = 1654 ; free virtual = 32452 --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds @@ -224,36 +224,36 @@ INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine -Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/rom_freq_word/rom_freq_word_ooc.xdc] for cell 'U0' -Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/rom_freq_word/rom_freq_word_ooc.xdc] for cell 'U0' -Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/dont_touch.xdc] -Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/dont_touch.xdc] +Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/rom_freq_word/rom_freq_word_ooc.xdc] for cell 'U0' +Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/rom_freq_word/rom_freq_word_ooc.xdc] for cell 'U0' +Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/dont_touch.xdc] +Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/dont_touch.xdc] Completed Processing XDC Constraints -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2122.988 ; gain = 0.000 ; free physical = 1591 ; free virtual = 45056 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2154.152 ; gain = 0.000 ; free physical = 1573 ; free virtual = 32371 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. -Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2122.988 ; gain = 0.000 ; free physical = 1590 ; free virtual = 45055 +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2154.152 ; gain = 0.000 ; free physical = 1573 ; free virtual = 32371 --------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 2122.988 ; gain = 449.242 ; free physical = 1596 ; free virtual = 45061 +Finished Constraint Validation : Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 2154.152 ; gain = 452.242 ; free physical = 1645 ; free virtual = 32443 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- -Loading part: xc7k410tffg900-2 +Loading part: xc7z100ffg900-2 --------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 2122.988 ; gain = 449.242 ; free physical = 1595 ; free virtual = 45060 +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 2154.152 ; gain = 452.242 ; free physical = 1645 ; free virtual = 32443 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- -Applied set_property DONT_TOUCH = true for U0. (constraint file /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/dont_touch.xdc, line 9). +Applied set_property DONT_TOUCH = true for U0. (constraint file /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/dont_touch.xdc, line 9). --------------------------------------------------------------------------------- -Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 2122.988 ; gain = 449.242 ; free physical = 1594 ; free virtual = 45059 +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 2154.152 ; gain = 452.242 ; free physical = 1644 ; free virtual = 32442 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 2122.988 ; gain = 449.242 ; free physical = 1585 ; free virtual = 45050 +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 2154.152 ; gain = 452.242 ; free physical = 1657 ; free virtual = 32453 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -279,8 +279,8 @@ Finished RTL Hierarchical Component Statistics Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: -DSPs: 1540 (col length:140) -BRAMs: 1590 (col length: RAMB18 140 RAMB36 70) +DSPs: 2020 (col length:140) +BRAMs: 1510 (col length: RAMB18 140 RAMB36 70) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- @@ -289,7 +289,7 @@ Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Warning: Parallel synthesis criteria is not met --------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 2122.988 ; gain = 449.242 ; free physical = 1607 ; free virtual = 45073 +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 2154.152 ; gain = 452.242 ; free physical = 1655 ; free virtual = 32457 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -301,13 +301,13 @@ Report RTL Partitions: Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2122.988 ; gain = 449.242 ; free physical = 1508 ; free virtual = 44984 +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2154.152 ; gain = 452.242 ; free physical = 1548 ; free virtual = 32351 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2122.988 ; gain = 449.242 ; free physical = 1508 ; free virtual = 44984 +Finished Timing Optimization : Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2154.152 ; gain = 452.242 ; free physical = 1548 ; free virtual = 32351 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -319,7 +319,7 @@ Report RTL Partitions: Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2122.988 ; gain = 449.242 ; free physical = 1507 ; free virtual = 44984 +Finished Technology Mapping : Time (s): cpu = 00:00:32 ; elapsed = 00:00:37 . Memory (MB): peak = 2154.152 ; gain = 452.242 ; free physical = 1543 ; free virtual = 32346 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -343,7 +343,7 @@ Start Final Netlist Cleanup Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 2122.988 ; gain = 449.242 ; free physical = 1519 ; free virtual = 44996 +Finished IO Insertion : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 2154.152 ; gain = 452.242 ; free physical = 1541 ; free virtual = 32343 --------------------------------------------------------------------------------- Report Check Netlist: @@ -356,7 +356,7 @@ Report Check Netlist: Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 2122.988 ; gain = 449.242 ; free physical = 1519 ; free virtual = 44996 +Finished Renaming Generated Instances : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 2154.152 ; gain = 452.242 ; free physical = 1541 ; free virtual = 32343 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -368,25 +368,25 @@ Report RTL Partitions: Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 2122.988 ; gain = 449.242 ; free physical = 1519 ; free virtual = 44996 +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 2154.152 ; gain = 452.242 ; free physical = 1541 ; free virtual = 32343 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 2122.988 ; gain = 449.242 ; free physical = 1519 ; free virtual = 44996 +Finished Renaming Generated Ports : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 2154.152 ; gain = 452.242 ; free physical = 1541 ; free virtual = 32343 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 2122.988 ; gain = 449.242 ; free physical = 1519 ; free virtual = 44996 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 2154.152 ; gain = 452.242 ; free physical = 1541 ; free virtual = 32343 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 2122.988 ; gain = 449.242 ; free physical = 1519 ; free virtual = 44996 +Finished Renaming Generated Nets : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 2154.152 ; gain = 452.242 ; free physical = 1541 ; free virtual = 32343 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report @@ -418,34 +418,34 @@ Report Instance Areas: |7 | \prim_init.ram |blk_mem_gen_prim_wrapper_init | 1| +------+---------------------------------------------+------------------------------+------+ --------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 2122.988 ; gain = 449.242 ; free physical = 1519 ; free virtual = 44996 +Finished Writing Synthesis Report : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 2154.152 ; gain = 452.242 ; free physical = 1541 ; free virtual = 32343 --------------------------------------------------------------------------------- -Synthesis finished with 0 errors, 0 critical warnings and 179 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2122.988 ; gain = 376.305 ; free physical = 1573 ; free virtual = 45050 -Synthesis Optimization Complete : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 2122.988 ; gain = 449.242 ; free physical = 1573 ; free virtual = 45050 +Synthesis finished with 0 errors, 0 critical warnings and 167 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:32 ; elapsed = 00:00:36 . Memory (MB): peak = 2154.152 ; gain = 379.305 ; free physical = 1590 ; free virtual = 32393 +Synthesis Optimization Complete : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 2154.152 ; gain = 452.242 ; free physical = 1590 ; free virtual = 32393 INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2122.988 ; gain = 0.000 ; free physical = 1516 ; free virtual = 44993 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2154.152 ; gain = 0.000 ; free physical = 1528 ; free virtual = 32331 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Common 17-83] Releasing license: Synthesis 17 Infos, 100 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully -synth_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:40 . Memory (MB): peak = 2122.988 ; gain = 728.012 ; free physical = 1605 ; free virtual = 45082 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2122.988 ; gain = 0.000 ; free physical = 1605 ; free virtual = 45082 +synth_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:40 . Memory (MB): peak = 2154.152 ; gain = 759.176 ; free physical = 1617 ; free virtual = 32420 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2154.152 ; gain = 0.000 ; free physical = 1617 ; free virtual = 32420 WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. -INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word.dcp' has been generated. +INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word.dcp' has been generated. WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. -INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP rom_freq_word, cache-ID = 56186d833b788b44 +INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP rom_freq_word, cache-ID = 7727187e03eca7b1 INFO: [Coretcl 2-1174] Renamed 6 cell refs. -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2122.988 ; gain = 0.000 ; free physical = 1595 ; free virtual = 45072 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2154.152 ; gain = 0.000 ; free physical = 1618 ; free virtual = 32421 WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. -INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word.dcp' has been generated. +INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file rom_freq_word_utilization_synth.rpt -pb rom_freq_word_utilization_synth.pb -INFO: [Common 17-206] Exiting Vivado at Fri May 12 16:06:19 2023... +INFO: [Common 17-206] Exiting Vivado at Sun Jul 30 18:06:27 2023... diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_sim_netlist.v b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_sim_netlist.v new file mode 100644 index 00000000..32ec870b --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:1b6e74d5170c09b3c51111bd307f37e9ec527ade285f9da64d8b2b3e32070b27 +size 28801 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_sim_netlist.vhdl b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_sim_netlist.vhdl new file mode 100644 index 00000000..5e879ca8 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:10778d6c1d2d23d93c6785c749bf15e581375d5e69edda1c0f7840bb8b7a928d +size 42530 diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.v b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.v similarity index 82% rename from projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.v rename to projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.v index a485cca8..e44fe31b 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.v +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.v @@ -1,13 +1,13 @@ // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 -// Date : Fri May 12 16:06:19 2023 +// Date : Sun Jul 30 18:06:27 2023 // Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS // Command : write_verilog -force -mode synth_stub -// /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.v +// /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.v // Design : rom_freq_word // Purpose : Stub declaration of top-level module interface -// Device : xc7k410tffg900-2 +// Device : xc7z100ffg900-2 // -------------------------------------------------------------------------------- // This empty module with port declaration file causes synthesis tools to infer a black box for IP. @@ -15,8 +15,8 @@ // Please paste the declaration into a Verilog source file or add the file as an additional source. (* x_core_info = "blk_mem_gen_v8_4_3,Vivado 2019.1.3" *) module rom_freq_word(clka, addra, douta) -/* synthesis syn_black_box black_box_pad_pin="clka,addra[6:0],douta[15:0]" */; +/* synthesis syn_black_box black_box_pad_pin="clka,addra[6:0],douta[11:0]" */; input clka; input [6:0]addra; - output [15:0]douta; + output [11:0]douta; endmodule diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.vhdl b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.vhdl similarity index 81% rename from projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.vhdl rename to projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.vhdl index 20e02f43..7fb2bf0b 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.vhdl +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.vhdl @@ -1,13 +1,13 @@ -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 --- Date : Fri May 12 16:06:19 2023 +-- Date : Sun Jul 30 18:06:27 2023 -- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS -- Command : write_vhdl -force -mode synth_stub --- /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.vhdl +-- /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.vhdl -- Design : rom_freq_word -- Purpose : Stub declaration of top-level module interface --- Device : xc7k410tffg900-2 +-- Device : xc7z100ffg900-2 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; @@ -16,7 +16,7 @@ entity rom_freq_word is Port ( clka : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 6 downto 0 ); - douta : out STD_LOGIC_VECTOR ( 15 downto 0 ) + douta : out STD_LOGIC_VECTOR ( 11 downto 0 ) ); end rom_freq_word; @@ -25,7 +25,7 @@ architecture stub of rom_freq_word is attribute syn_black_box : boolean; attribute black_box_pad_pin : string; attribute syn_black_box of stub : architecture is true; -attribute black_box_pad_pin of stub : architecture is "clka,addra[6:0],douta[15:0]"; +attribute black_box_pad_pin of stub : architecture is "clka,addra[6:0],douta[11:0]"; attribute x_core_info : string; attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_3,Vivado 2019.1.3"; begin diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_utilization_synth.pb b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_utilization_synth.pb new file mode 100644 index 00000000..343f2870 Binary files /dev/null and b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_utilization_synth.pb differ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_utilization_synth.rpt b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_utilization_synth.rpt similarity index 73% rename from projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_utilization_synth.rpt rename to projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_utilization_synth.rpt index 57f696ae..80c64a89 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_utilization_synth.rpt +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_utilization_synth.rpt @@ -1,11 +1,11 @@ Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 -| Date : Fri May 12 16:06:18 2023 +| Date : Sun Jul 30 18:06:27 2023 | Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS | Command : report_utilization -file rom_freq_word_utilization_synth.rpt -pb rom_freq_word_utilization_synth.pb | Design : rom_freq_word -| Device : 7k410tffg900-2 +| Device : 7z100ffg900-2 | Design State : Synthesized --------------------------------------------------------------------------------------------------------------------- @@ -30,14 +30,14 @@ Table of Contents +-------------------------+------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +-------------------------+------+-------+-----------+-------+ -| Slice LUTs* | 0 | 0 | 254200 | 0.00 | -| LUT as Logic | 0 | 0 | 254200 | 0.00 | -| LUT as Memory | 0 | 0 | 90600 | 0.00 | -| Slice Registers | 0 | 0 | 508400 | 0.00 | -| Register as Flip Flop | 0 | 0 | 508400 | 0.00 | -| Register as Latch | 0 | 0 | 508400 | 0.00 | -| F7 Muxes | 0 | 0 | 127100 | 0.00 | -| F8 Muxes | 0 | 0 | 63550 | 0.00 | +| Slice LUTs* | 0 | 0 | 277400 | 0.00 | +| LUT as Logic | 0 | 0 | 277400 | 0.00 | +| LUT as Memory | 0 | 0 | 108200 | 0.00 | +| Slice Registers | 0 | 0 | 554800 | 0.00 | +| Register as Flip Flop | 0 | 0 | 554800 | 0.00 | +| Register as Latch | 0 | 0 | 554800 | 0.00 | +| F7 Muxes | 0 | 0 | 138700 | 0.00 | +| F8 Muxes | 0 | 0 | 69350 | 0.00 | +-------------------------+------+-------+-----------+-------+ * Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. @@ -67,9 +67,9 @@ Table of Contents +-------------------+------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +-------------------+------+-------+-----------+-------+ -| Block RAM Tile | 0.5 | 0 | 795 | 0.06 | -| RAMB36/FIFO* | 0 | 0 | 795 | 0.00 | -| RAMB18 | 1 | 0 | 1590 | 0.06 | +| Block RAM Tile | 0.5 | 0 | 755 | 0.07 | +| RAMB36/FIFO* | 0 | 0 | 755 | 0.00 | +| RAMB18 | 1 | 0 | 1510 | 0.07 | | RAMB18E1 only | 1 | | | | +-------------------+------+-------+-----------+-------+ * Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 @@ -81,7 +81,7 @@ Table of Contents +-----------+------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +-----------+------+-------+-----------+-------+ -| DSPs | 0 | 0 | 1540 | 0.00 | +| DSPs | 0 | 0 | 2020 | 0.00 | +-----------+------+-------+-----------+-------+ @@ -91,24 +91,25 @@ Table of Contents +-----------------------------+------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +-----------------------------+------+-------+-----------+-------+ -| Bonded IOB | 0 | 0 | 500 | 0.00 | +| Bonded IOB | 0 | 0 | 362 | 0.00 | | Bonded IPADs | 0 | 0 | 50 | 0.00 | | Bonded OPADs | 0 | 0 | 32 | 0.00 | -| PHY_CONTROL | 0 | 0 | 10 | 0.00 | -| PHASER_REF | 0 | 0 | 10 | 0.00 | -| OUT_FIFO | 0 | 0 | 40 | 0.00 | -| IN_FIFO | 0 | 0 | 40 | 0.00 | -| IDELAYCTRL | 0 | 0 | 10 | 0.00 | -| IBUFDS | 0 | 0 | 480 | 0.00 | +| Bonded IOPADs | 0 | 0 | 130 | 0.00 | +| PHY_CONTROL | 0 | 0 | 8 | 0.00 | +| PHASER_REF | 0 | 0 | 8 | 0.00 | +| OUT_FIFO | 0 | 0 | 32 | 0.00 | +| IN_FIFO | 0 | 0 | 32 | 0.00 | +| IDELAYCTRL | 0 | 0 | 8 | 0.00 | +| IBUFDS | 0 | 0 | 348 | 0.00 | | GTXE2_COMMON | 0 | 0 | 4 | 0.00 | | GTXE2_CHANNEL | 0 | 0 | 16 | 0.00 | -| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 40 | 0.00 | -| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 40 | 0.00 | -| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 500 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 32 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 32 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 400 | 0.00 | | ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 | | IBUFDS_GTE2 | 0 | 0 | 8 | 0.00 | -| ILOGIC | 0 | 0 | 500 | 0.00 | -| OLOGIC | 0 | 0 | 500 | 0.00 | +| ILOGIC | 0 | 0 | 362 | 0.00 | +| OLOGIC | 0 | 0 | 362 | 0.00 | +-----------------------------+------+-------+-----------+-------+ @@ -119,12 +120,12 @@ Table of Contents | Site Type | Used | Fixed | Available | Util% | +------------+------+-------+-----------+-------+ | BUFGCTRL | 0 | 0 | 32 | 0.00 | -| BUFIO | 0 | 0 | 40 | 0.00 | -| MMCME2_ADV | 0 | 0 | 10 | 0.00 | -| PLLE2_ADV | 0 | 0 | 10 | 0.00 | -| BUFMRCE | 0 | 0 | 20 | 0.00 | +| BUFIO | 0 | 0 | 32 | 0.00 | +| MMCME2_ADV | 0 | 0 | 8 | 0.00 | +| PLLE2_ADV | 0 | 0 | 8 | 0.00 | +| BUFMRCE | 0 | 0 | 16 | 0.00 | | BUFHCE | 0 | 0 | 168 | 0.00 | -| BUFR | 0 | 0 | 40 | 0.00 | +| BUFR | 0 | 0 | 32 | 0.00 | +------------+------+-------+-----------+-------+ diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rundef.js b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rundef.js similarity index 76% rename from projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rundef.js rename to projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rundef.js index f8e5a2e8..28519baf 100644 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rundef.js +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rundef.js @@ -12,9 +12,9 @@ var WshShell = new ActiveXObject( "WScript.Shell" ); var ProcEnv = WshShell.Environment( "Process" ); var PathVal = ProcEnv("PATH"); if ( PathVal.length == 0 ) { - PathVal = "/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/tools/Xilinx/Vivado/2019.1/bin;"; + PathVal = "/home/josh/Software/Xilinx/SDK/2019.1/bin:/home/josh/Software/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/home/josh/Software/Xilinx/Vivado/2019.1/bin;"; } else { - PathVal = "/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/tools/Xilinx/Vivado/2019.1/bin;" + PathVal; + PathVal = "/home/josh/Software/Xilinx/SDK/2019.1/bin:/home/josh/Software/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/home/josh/Software/Xilinx/Vivado/2019.1/bin;" + PathVal; } ProcEnv("PATH") = PathVal; diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/runme.bat b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/runme.bat similarity index 100% rename from projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/runme.bat rename to projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/runme.bat diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/runme.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/runme.sh similarity index 56% rename from projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/runme.sh rename to projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/runme.sh index 8c23de6c..55acd9c6 100755 --- a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/runme.sh +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/runme.sh @@ -7,9 +7,9 @@ # if [ -z "$PATH" ]; then - PATH=/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2019.1/bin + PATH=/home/josh/Software/Xilinx/SDK/2019.1/bin:/home/josh/Software/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/home/josh/Software/Xilinx/Vivado/2019.1/bin else - PATH=/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2019.1/bin:$PATH + PATH=/home/josh/Software/Xilinx/SDK/2019.1/bin:/home/josh/Software/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/home/josh/Software/Xilinx/Vivado/2019.1/bin:$PATH fi export PATH @@ -20,7 +20,7 @@ else fi export LD_LIBRARY_PATH -HD_PWD='/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1' +HD_PWD='/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1' cd "$HD_PWD" HD_LOG=runme.log diff --git a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/vivado.pb b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/vivado.pb similarity index 86% rename from projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/vivado.pb rename to projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/vivado.pb index 4b58cce0..fae26d33 100644 Binary files a/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/vivado.pb and b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/vivado.pb differ diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/.Vivado_Synthesis.queue.rst b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/.Vivado_Synthesis.queue.rst new file mode 100644 index 00000000..e69de29b diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/.vivado.begin.rst b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/.vivado.begin.rst new file mode 100644 index 00000000..dbf37420 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/.vivado.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/.vivado.end.rst b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/.vivado.end.rst new file mode 100644 index 00000000..e69de29b diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/ISEWrap.js b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/ISEWrap.js new file mode 100755 index 00000000..3e83de11 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/ISEWrap.js @@ -0,0 +1,270 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var wbemFlagReturnImmediately = 0x10; + var wbemFlagForwardOnly = 0x20; + var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); + var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); + var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); + var NOC = 0; + var NOLP = 0; + var TPM = 0; + + var cpuInfos = new Enumerator(processor); + for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { + var cpuInfo = cpuInfos.item(); + NOC += cpuInfo.NumberOfCores; + NOLP += cpuInfo.NumberOfLogicalProcessors; + } + var csInfos = new Enumerator(computerSystem); + for(;!csInfos.atEnd(); csInfos.moveNext()) { + var csInfo = csInfos.item(); + TPM += csInfo.TotalPhysicalMemory; + } + + var ISEHOSTCORE = NOLP + var ISEMEMTOTAL = TPM + + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/ISEWrap.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/ISEWrap.sh new file mode 100755 index 00000000..f679f2e8 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/ISEWrap.sh @@ -0,0 +1,67 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. +# + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! +if [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi +ISE_USER=$USER + +ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) +ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) + +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/__synthesis_is_complete__ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/__synthesis_is_complete__ new file mode 100644 index 00000000..e69de29b diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/gen_run.xml b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/gen_run.xml new file mode 100644 index 00000000..784a022a --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/gen_run.xml @@ -0,0 +1,64 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/htr.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/htr.txt new file mode 100644 index 00000000..1f00b537 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/htr.txt @@ -0,0 +1,9 @@ +# +# Vivado(TM) +# htr.txt: a Vivado-generated description of how-to-repeat the +# the basic steps of a run. Note that runme.bat/sh needs +# to be invoked for Vivado to track run status. +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# + +vivado -log vio_RF_control.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_RF_control.tcl diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/project.wdf b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/project.wdf new file mode 100644 index 00000000..41900ddb --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/project.wdf @@ -0,0 +1,38 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:3130:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 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-0,0 +1,40 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// + +echo "This script was generated under a different operating system." +echo "Please update the PATH variable below, before executing this script" +exit + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "/home/josh/Software/Xilinx/SDK/2019.1/bin:/home/josh/Software/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/home/josh/Software/Xilinx/Vivado/2019.1/bin;"; +} else { + PathVal = "/home/josh/Software/Xilinx/SDK/2019.1/bin:/home/josh/Software/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/home/josh/Software/Xilinx/Vivado/2019.1/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +ISEStep( "vivado", + "-log vio_RF_control.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_RF_control.tcl" ); + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/runme.bat b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/runme.bat new file mode 100644 index 00000000..ba55218d --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/runme.bat @@ -0,0 +1,11 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +set PATH=%SYSTEMROOT%\system32;%PATH% +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/runme.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/runme.sh new file mode 100755 index 00000000..4e5ab03f --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/runme.sh @@ -0,0 +1,39 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# + +if [ -z "$PATH" ]; then + PATH=/home/josh/Software/Xilinx/SDK/2019.1/bin:/home/josh/Software/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/home/josh/Software/Xilinx/Vivado/2019.1/bin +else + PATH=/home/josh/Software/Xilinx/SDK/2019.1/bin:/home/josh/Software/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/home/josh/Software/Xilinx/Vivado/2019.1/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +EAStep vivado -log vio_RF_control.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_RF_control.tcl diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/vio_RF_control.dcp b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/vio_RF_control.dcp new file mode 100644 index 00000000..f7ac75c7 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/vio_RF_control.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:bcad0800db9e8934427bd9419c7bdec1f12b476cf657e9042d44a32342617e56 +size 190328 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/vio_RF_control.tcl b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/vio_RF_control.tcl new file mode 100644 index 00000000..1ca16ccf --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/vio_RF_control.tcl @@ -0,0 +1,156 @@ +# +# Synthesis run script generated by Vivado +# + +set TIME_start [clock seconds] +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +set_param simulator.modelsimInstallPath /home/josh/Software/Mentor/modeltech/bin +set_param simulator.vcsmxInstallPath /home/josh/Software/Synopsys/vcs/T-2022.06/bin +set_msg_config -id {Common 17-41} -limit 10000000 +set_param project.vivado.isBlockSynthRun true +set_msg_config -msgmgr_mode ooc_run +create_project -in_memory -part xc7z100ffg900-2 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info +set_property webtalk.parent_dir /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/wt [current_project] +set_property parent.project_path /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.xpr [current_project] +set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language Verilog [current_project] +set_property ip_output_repo /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +read_ip -quiet /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_RF_control/vio_RF_control.xci +set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_RF_control/vio_RF_control.xdc] +set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_RF_control/vio_RF_control_ooc.xdc] + +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +set_param ips.enableIPCacheLiteLoad 1 + +set cached_ip [config_ip_cache -export -no_bom -dir /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1 -new_name vio_RF_control -ip [get_ips vio_RF_control]] + +if { $cached_ip eq {} } { +close [open __synthesis_is_running__ w] + +synth_design -top vio_RF_control -part xc7z100ffg900-2 -mode out_of_context + +#--------------------------------------------------------- +# Generate Checkpoint/Stub/Simulation Files For IP Cache +#--------------------------------------------------------- +# disable binary constraint mode for IPCache checkpoints +set_param constraints.enableBinaryConstraints false + +catch { + write_checkpoint -force -noxdef -rename_prefix vio_RF_control_ vio_RF_control.dcp + + set ipCachedFiles {} + write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_RF_control_stub.v + lappend ipCachedFiles vio_RF_control_stub.v + + write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_RF_control_stub.vhdl + lappend ipCachedFiles vio_RF_control_stub.vhdl + + write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_RF_control_sim_netlist.v + lappend ipCachedFiles vio_RF_control_sim_netlist.v + + write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_RF_control_sim_netlist.vhdl + lappend ipCachedFiles vio_RF_control_sim_netlist.vhdl +set TIME_taken [expr [clock seconds] - $TIME_start] + + config_ip_cache -add -dcp vio_RF_control.dcp -move_files $ipCachedFiles -use_project_ipc -synth_runtime $TIME_taken -ip [get_ips vio_RF_control] +} + +rename_ref -prefix_all vio_RF_control_ + +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef vio_RF_control.dcp +create_report "vio_RF_control_synth_1_synth_report_utilization_0" "report_utilization -file vio_RF_control_utilization_synth.rpt -pb vio_RF_control_utilization_synth.pb" + +if { [catch { + write_verilog -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/vio_RF_control_stub.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + write_vhdl -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/vio_RF_control_stub.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + write_verilog -force -mode funcsim /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/vio_RF_control_sim_netlist.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + +if { [catch { + write_vhdl -force -mode funcsim /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/vio_RF_control_sim_netlist.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + + +} else { + + +}; # end if cached_ip + +add_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/vio_RF_control_stub.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_RF_control/vio_RF_control.xci] + +add_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/vio_RF_control_stub.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_RF_control/vio_RF_control.xci] + +add_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/vio_RF_control_sim_netlist.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_RF_control/vio_RF_control.xci] + +add_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/vio_RF_control_sim_netlist.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_RF_control/vio_RF_control.xci] + +add_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/vio_RF_control.dcp -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_RF_control/vio_RF_control.xci] + +if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_RF_control]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/vio_RF_control_sim_netlist.v /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_RF_control + } +} + +if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_RF_control]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/vio_RF_control_sim_netlist.vhdl /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_RF_control + } +} + +if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_RF_control]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/vio_RF_control_stub.v /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_RF_control + } +} + +if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_RF_control]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/vio_RF_control_stub.vhdl /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_RF_control + } +} +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/vio_RF_control.vds b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/vio_RF_control.vds new file mode 100644 index 00000000..bee8d161 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/vio_RF_control.vds @@ -0,0 +1,674 @@ +#----------------------------------------------------------- +# Vivado v2019.1.3 (64-bit) +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 +# Start of session at: Sun Jul 30 18:20:25 2023 +# Process ID: 1404823 +# Current directory: /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1 +# Command line: vivado -log vio_RF_control.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_RF_control.tcl +# Log file: /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/vio_RF_control.vds +# Journal file: /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/vivado.jou +#----------------------------------------------------------- +source vio_RF_control.tcl -notrace +Command: synth_design -top vio_RF_control -part xc7z100ffg900-2 -mode out_of_context +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7z100' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z100' +INFO: [Device 21-403] Loading part xc7z100ffg900-2 +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 1404898 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 1860.816 ; gain = 153.719 ; free physical = 3207 ; free virtual = 34273 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'vio_RF_control' [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_RF_control/synth/vio_RF_control.v:59] +WARNING: [Synth 8-3848] Net sl_iport0 in module/entity vio_RF_control does not have driver. [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_RF_control/synth/vio_RF_control.v:102] +INFO: [Synth 8-6155] done synthesizing module 'vio_RF_control' (8#1) [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_RF_control/synth/vio_RF_control.v:59] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized5 has unconnected port Bus_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Read +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[15] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[14] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[13] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[12] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[11] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[10] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[9] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[8] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[7] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[6] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[5] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[4] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[3] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[2] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[1] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Internal_cnt_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized4 has unconnected port Bus_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Read +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[15] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[14] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[13] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[12] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Internal_cnt_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Read +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[15] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[14] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[13] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[12] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[11] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[10] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[9] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[8] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Internal_cnt_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Read +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[15] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[14] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[13] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[12] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[11] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[10] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[9] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[8] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Internal_cnt_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Read +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[15] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[14] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[13] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[12] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[11] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[10] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[9] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[8] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[7] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[6] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[5] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[4] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[3] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[2] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Internal_cnt_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_in_one has unconnected port Internal_cnt_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in1[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in2[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in3[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in4[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in5[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in6[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in7[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in8[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in9[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in10[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in11[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in12[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in13[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in14[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in15[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in16[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in17[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in18[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in19[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in20[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in21[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in22[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in23[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in24[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in25[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in26[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in27[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in28[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in29[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in30[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in31[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in32[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in33[0] +INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1922.504 ; gain = 215.406 ; free physical = 3227 ; free virtual = 34293 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1925.473 ; gain = 218.375 ; free physical = 3230 ; free virtual = 34296 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1925.473 ; gain = 218.375 ; free physical = 3230 ; free virtual = 34296 +--------------------------------------------------------------------------------- +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_RF_control/vio_RF_control_ooc.xdc] +Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_RF_control/vio_RF_control_ooc.xdc] +Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_RF_control/vio_RF_control.xdc] +Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_RF_control/vio_RF_control.xdc] +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2107.160 ; gain = 0.000 ; free physical = 3110 ; free virtual = 34175 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2114.098 ; gain = 6.938 ; free physical = 3110 ; free virtual = 34175 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2114.098 ; gain = 407.000 ; free physical = 3205 ; free virtual = 34271 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7z100ffg900-2 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2114.098 ; gain = 407.000 ; free physical = 3205 ; free virtual = 34271 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2114.098 ; gain = 407.000 ; free physical = 3205 ; free virtual = 34271 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2114.098 ; gain = 407.000 ; free physical = 3198 ; free virtual = 34265 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 2 Input 3 Bit Adders := 1 + 2 Input 2 Bit Adders := 2 ++---Registers : + 128 Bit Registers := 1 + 32 Bit Registers := 2 + 16 Bit Registers := 26 + 13 Bit Registers := 1 + 12 Bit Registers := 5 + 8 Bit Registers := 2 + 7 Bit Registers := 1 + 5 Bit Registers := 1 + 4 Bit Registers := 1 + 3 Bit Registers := 3 + 2 Bit Registers := 3 + 1 Bit Registers := 40 ++---Muxes : + 2 Input 16 Bit Muxes := 4 + 8 Input 13 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 21 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +Module vio_v3_0_20_probe_in_one +Detailed RTL Component Info : ++---Registers : + 12 Bit Registers := 4 + 1 Bit Registers := 2 ++---Muxes : + 2 Input 1 Bit Muxes := 1 +Module vio_v3_0_20_probe_out_one +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 + 1 Bit Registers := 1 ++---Muxes : + 2 Input 1 Bit Muxes := 1 +Module vio_v3_0_20_probe_out_one__parameterized0 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 + 2 Bit Registers := 1 ++---Muxes : + 2 Input 1 Bit Muxes := 1 +Module vio_v3_0_20_probe_out_one__parameterized1 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 + 8 Bit Registers := 1 ++---Muxes : + 2 Input 1 Bit Muxes := 1 +Module vio_v3_0_20_probe_out_one__parameterized2 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 + 8 Bit Registers := 1 ++---Muxes : + 2 Input 1 Bit Muxes := 1 +Module vio_v3_0_20_probe_out_one__parameterized3 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 + 12 Bit Registers := 1 ++---Muxes : + 2 Input 1 Bit Muxes := 1 +Module vio_v3_0_20_probe_out_one__parameterized4 +Detailed RTL Component Info : ++---Adders : + 2 Input 2 Bit Adders := 1 ++---Registers : + 32 Bit Registers := 1 + 16 Bit Registers := 3 + 2 Bit Registers := 1 ++---Muxes : + 2 Input 16 Bit Muxes := 1 +Module vio_v3_0_20_probe_out_one__parameterized5 +Detailed RTL Component Info : ++---Adders : + 2 Input 2 Bit Adders := 1 ++---Registers : + 32 Bit Registers := 1 + 16 Bit Registers := 3 + 2 Bit Registers := 1 ++---Muxes : + 2 Input 16 Bit Muxes := 1 +Module vio_v3_0_20_probe_out_all +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 + 4 Bit Registers := 1 + 1 Bit Registers := 18 ++---Muxes : + 2 Input 1 Bit Muxes := 2 +Module vio_v3_0_20_probe_width +Detailed RTL Component Info : ++---Adders : + 2 Input 3 Bit Adders := 1 ++---Registers : + 13 Bit Registers := 1 + 3 Bit Registers := 1 ++---Muxes : + 8 Input 13 Bit Muxes := 1 +Module xsdbs_v1_0_2_xsdbs +Detailed RTL Component Info : ++---Registers : + 128 Bit Registers := 1 + 16 Bit Registers := 2 + 1 Bit Registers := 1 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 1 +Module vio_v3_0_20_decoder +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 2 + 7 Bit Registers := 1 + 5 Bit Registers := 1 + 3 Bit Registers := 2 + 1 Bit Registers := 9 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 3 +Module vio_v3_0_20_vio +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 2020 (col length:140) +BRAMs: 1510 (col length: RAMB18 140 RAMB36 70) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[6]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[6]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[6]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[6]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[6]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[6]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[6]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[6]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[6]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[6]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[6]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[7]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[7]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[7]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[7]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[7]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[7]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[7]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[7]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[7]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[7]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[7]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[8]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[8]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[8]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[8]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[8]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[8]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[8]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[8]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[8]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[8]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[8]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[10]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[10]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[10]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[10]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[10]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[10]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[10]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[10]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[10]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[10]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[10]' +INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_WIDTH_INST/probe_width_int_reg[7] ) +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 2114.098 ; gain = 407.000 ; free physical = 3182 ; free virtual = 34252 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2114.098 ; gain = 407.000 ; free physical = 3066 ; free virtual = 34137 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2114.098 ; gain = 407.000 ; free physical = 3067 ; free virtual = 34137 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2114.098 ; gain = 407.000 ; free physical = 3061 ; free virtual = 34132 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[36] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[35] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[34] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[33] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[32] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[31] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[30] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[29] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[28] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[27] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[26] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[25] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[24] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[23] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[22] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[21] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[20] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[19] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[18] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[17] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[16] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[15] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[14] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[13] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[12] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[11] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[10] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[9] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[8] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[7] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[6] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[5] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[4] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[3] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[2] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[1] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[0] to constant 0 +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2114.098 ; gain = 407.000 ; free physical = 3064 ; free virtual = 34135 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2114.098 ; gain = 407.000 ; free physical = 3064 ; free virtual = 34135 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2114.098 ; gain = 407.000 ; free physical = 3064 ; free virtual = 34134 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2114.098 ; gain = 407.000 ; free physical = 3064 ; free virtual = 34134 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2114.098 ; gain = 407.000 ; free physical = 3064 ; free virtual = 34134 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2114.098 ; gain = 407.000 ; free physical = 3064 ; free virtual = 34134 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+------+------+ +| |Cell |Count | ++------+------+------+ +|1 |LUT1 | 1| +|2 |LUT2 | 14| +|3 |LUT3 | 82| +|4 |LUT4 | 9| +|5 |LUT5 | 31| +|6 |LUT6 | 101| +|7 |MUXF7 | 9| +|8 |MUXF8 | 1| +|9 |FDRE | 509| +|10 |FDSE | 56| ++------+------+------+ + +Report Instance Areas: ++------+----------------------------------------+------------------------------------------+------+ +| |Instance |Module |Cells | ++------+----------------------------------------+------------------------------------------+------+ +|1 |top | | 813| +|2 | inst |vio_v3_0_20_vio | 813| +|3 | U_XSDB_SLAVE |xsdbs_v1_0_2_xsdbs | 248| +|4 | DECODER_INST |vio_v3_0_20_decoder | 88| +|5 | PROBE_IN_INST |vio_v3_0_20_probe_in_one | 62| +|6 | PROBE_OUT_ALL_INST |vio_v3_0_20_probe_out_all | 381| +|7 | \G_PROBE_OUT[0].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one | 3| +|8 | \G_PROBE_OUT[10].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_0 | 3| +|9 | \G_PROBE_OUT[11].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_1 | 3| +|10 | \G_PROBE_OUT[12].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_2 | 3| +|11 | \G_PROBE_OUT[13].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized4 | 101| +|12 | \G_PROBE_OUT[14].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_3 | 3| +|13 | \G_PROBE_OUT[15].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized5 | 106| +|14 | \G_PROBE_OUT[1].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized0 | 6| +|15 | \G_PROBE_OUT[2].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_4 | 3| +|16 | \G_PROBE_OUT[3].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized1 | 16| +|17 | \G_PROBE_OUT[4].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized2 | 16| +|18 | \G_PROBE_OUT[5].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized3 | 24| +|19 | \G_PROBE_OUT[6].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_5 | 3| +|20 | \G_PROBE_OUT[7].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_6 | 3| +|21 | \G_PROBE_OUT[8].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_7 | 3| +|22 | \G_PROBE_OUT[9].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_8 | 3| +|23 | PROBE_OUT_WIDTH_INST |vio_v3_0_20_probe_width | 18| ++------+----------------------------------------+------------------------------------------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2114.098 ; gain = 407.000 ; free physical = 3064 ; free virtual = 34134 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 292 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 2114.098 ; gain = 218.375 ; free physical = 3124 ; free virtual = 34195 +Synthesis Optimization Complete : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2114.098 ; gain = 407.000 ; free physical = 3138 ; free virtual = 34209 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Netlist 29-17] Analyzing 10 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2114.098 ; gain = 0.000 ; free physical = 3060 ; free virtual = 34130 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Common 17-83] Releasing license: Synthesis +130 Infos, 138 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 2114.098 ; gain = 715.668 ; free physical = 3152 ; free virtual = 34223 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2114.098 ; gain = 0.000 ; free physical = 3152 ; free virtual = 34223 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/vio_RF_control.dcp' has been generated. +WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. +INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP vio_RF_control, cache-ID = e8e950360ca1fe60 +INFO: [Coretcl 2-1174] Renamed 22 cell refs. +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2138.109 ; gain = 0.000 ; free physical = 3156 ; free virtual = 34229 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/vio_RF_control.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file vio_RF_control_utilization_synth.rpt -pb vio_RF_control_utilization_synth.pb +INFO: [Common 17-206] Exiting Vivado at Sun Jul 30 18:20:42 2023... diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/vio_RF_control_sim_netlist.v b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/vio_RF_control_sim_netlist.v new file mode 100644 index 00000000..f15721e9 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/vio_RF_control_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:ba1ba841643badc5c1347838c1be97020a44c661ac3bfa7361c3eb9da92ce4ca +size 424588 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/vio_RF_control_sim_netlist.vhdl b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/vio_RF_control_sim_netlist.vhdl new file mode 100644 index 00000000..95a8f1e2 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/vio_RF_control_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:1ac752b031bf31290755a15ea0f1d589241d6d7b6d0151c37451a33e22c33214 +size 735950 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/vio_RF_control_stub.v b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/vio_RF_control_stub.v new file mode 100644 index 00000000..931473ee --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/vio_RF_control_stub.v @@ -0,0 +1,39 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Sun Jul 30 18:20:42 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub +// /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/vio_RF_control_stub.v +// Design : vio_RF_control +// Purpose : Stub declaration of top-level module interface +// Device : xc7z100ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "vio,Vivado 2019.1.3" *) +module vio_RF_control(clk, probe_in0, probe_out0, probe_out1, + probe_out2, probe_out3, probe_out4, probe_out5, probe_out6, probe_out7, probe_out8, probe_out9, + probe_out10, probe_out11, probe_out12, probe_out13, probe_out14, probe_out15) +/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[11:0],probe_out0[0:0],probe_out1[1:0],probe_out2[0:0],probe_out3[7:0],probe_out4[7:0],probe_out5[11:0],probe_out6[0:0],probe_out7[0:0],probe_out8[0:0],probe_out9[0:0],probe_out10[0:0],probe_out11[0:0],probe_out12[0:0],probe_out13[31:0],probe_out14[0:0],probe_out15[31:0]" */; + input clk; + input [11:0]probe_in0; + output [0:0]probe_out0; + output [1:0]probe_out1; + output [0:0]probe_out2; + output [7:0]probe_out3; + output [7:0]probe_out4; + output [11:0]probe_out5; + output [0:0]probe_out6; + output [0:0]probe_out7; + output [0:0]probe_out8; + output [0:0]probe_out9; + output [0:0]probe_out10; + output [0:0]probe_out11; + output [0:0]probe_out12; + output [31:0]probe_out13; + output [0:0]probe_out14; + output [31:0]probe_out15; +endmodule diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/vio_RF_control_stub.vhdl b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/vio_RF_control_stub.vhdl new file mode 100644 index 00000000..8b4afdd8 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/vio_RF_control_stub.vhdl @@ -0,0 +1,47 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Sun Jul 30 18:20:42 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/vio_RF_control_stub.vhdl +-- Design : vio_RF_control +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity vio_RF_control is + Port ( + clk : in STD_LOGIC; + probe_in0 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out1 : out STD_LOGIC_VECTOR ( 1 downto 0 ); + probe_out2 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out3 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + probe_out4 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + probe_out5 : out STD_LOGIC_VECTOR ( 11 downto 0 ); + probe_out6 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out7 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out8 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out9 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out10 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out11 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out12 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out13 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + probe_out14 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out15 : out STD_LOGIC_VECTOR ( 31 downto 0 ) + ); + +end vio_RF_control; + +architecture stub of vio_RF_control is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[11:0],probe_out0[0:0],probe_out1[1:0],probe_out2[0:0],probe_out3[7:0],probe_out4[7:0],probe_out5[11:0],probe_out6[0:0],probe_out7[0:0],probe_out8[0:0],probe_out9[0:0],probe_out10[0:0],probe_out11[0:0],probe_out12[0:0],probe_out13[31:0],probe_out14[0:0],probe_out15[31:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3"; +begin +end; diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/vio_RF_control_utilization_synth.pb b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/vio_RF_control_utilization_synth.pb new file mode 100644 index 00000000..5e1031a6 Binary files /dev/null and b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/vio_RF_control_utilization_synth.pb differ diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/vio_RF_control_utilization_synth.rpt b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/vio_RF_control_utilization_synth.rpt new file mode 100644 index 00000000..a5ef529f --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/vio_RF_control_utilization_synth.rpt @@ -0,0 +1,183 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +| Date : Sun Jul 30 18:20:42 2023 +| Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +| Command : report_utilization -file vio_RF_control_utilization_synth.rpt -pb vio_RF_control_utilization_synth.pb +| Design : vio_RF_control +| Device : 7z100ffg900-2 +| Design State : Synthesized +----------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs* | 194 | 0 | 277400 | 0.07 | +| LUT as Logic | 194 | 0 | 277400 | 0.07 | +| LUT as Memory | 0 | 0 | 108200 | 0.00 | +| Slice Registers | 565 | 0 | 554800 | 0.10 | +| Register as Flip Flop | 565 | 0 | 554800 | 0.10 | +| Register as Latch | 0 | 0 | 554800 | 0.00 | +| F7 Muxes | 9 | 0 | 138700 | <0.01 | +| F8 Muxes | 1 | 0 | 69350 | <0.01 | ++-------------------------+------+-------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 56 | Yes | Set | - | +| 509 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 755 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 755 | 0.00 | +| RAMB18 | 0 | 0 | 1510 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 2020 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 0 | 0 | 362 | 0.00 | +| Bonded IPADs | 0 | 0 | 50 | 0.00 | +| Bonded OPADs | 0 | 0 | 32 | 0.00 | +| Bonded IOPADs | 0 | 0 | 130 | 0.00 | +| PHY_CONTROL | 0 | 0 | 8 | 0.00 | +| PHASER_REF | 0 | 0 | 8 | 0.00 | +| OUT_FIFO | 0 | 0 | 32 | 0.00 | +| IN_FIFO | 0 | 0 | 32 | 0.00 | +| IDELAYCTRL | 0 | 0 | 8 | 0.00 | +| IBUFDS | 0 | 0 | 348 | 0.00 | +| GTXE2_COMMON | 0 | 0 | 4 | 0.00 | +| GTXE2_CHANNEL | 0 | 0 | 16 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 32 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 32 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 400 | 0.00 | +| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 | +| IBUFDS_GTE2 | 0 | 0 | 8 | 0.00 | +| ILOGIC | 0 | 0 | 362 | 0.00 | +| OLOGIC | 0 | 0 | 362 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 0 | 0 | 32 | 0.00 | +| BUFIO | 0 | 0 | 32 | 0.00 | +| MMCME2_ADV | 0 | 0 | 8 | 0.00 | +| PLLE2_ADV | 0 | 0 | 8 | 0.00 | +| BUFMRCE | 0 | 0 | 16 | 0.00 | +| BUFHCE | 0 | 0 | 168 | 0.00 | +| BUFR | 0 | 0 | 32 | 0.00 | ++------------+------+-------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +7. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| FDRE | 509 | Flop & Latch | +| LUT6 | 101 | LUT | +| LUT3 | 82 | LUT | +| FDSE | 56 | Flop & Latch | +| LUT5 | 31 | LUT | +| LUT2 | 14 | LUT | +| MUXF7 | 9 | MuxFx | +| LUT4 | 9 | LUT | +| MUXF8 | 1 | MuxFx | +| LUT1 | 1 | LUT | ++----------+------+---------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/vivado.pb b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/vivado.pb new file mode 100644 index 00000000..9005358a Binary files /dev/null and b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_RF_control_synth_1/vivado.pb differ diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.xpr b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.xpr index 7c2fc2cf..3911e3c4 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.xpr +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.xpr @@ -39,13 +39,13 @@ - - - - - - - - - - - - - - @@ -142,20 +128,6 @@ - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -246,6 +258,26 @@ + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + @@ -278,6 +310,40 @@ + + + + + + + + + + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/rom_freq_word.xcix b/projects/dl814_dj/dl814_dj_new_48m/ip/rom_freq_word.xcix index 1eb11f2e..4cd40d9b 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/rom_freq_word.xcix +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/rom_freq_word.xcix @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:23ec4e23d084d178d24316d6f54d8dcd71b612c1fb375fd559a93237b59d8885 -size 11664035 +oid sha256:b3733d51cd45727c4b4f042b74cc8e3c9612ce9a3ee6d08ba454ce9470d145b7 +size 11664787 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/vio_RF_control.xcix b/projects/dl814_dj/dl814_dj_new_48m/ip/vio_RF_control.xcix index 4637e451..ad9c3547 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/ip/vio_RF_control.xcix +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/vio_RF_control.xcix @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:b54cf031cbee0d69af400dd9711af02e62ed3bb5a7e8cc76fd93edce598c0871 -size 712909 +oid sha256:a6c6b32133447b209425318a40f90ff8b78341d07d111bdd8dd9199c6c314aec +size 781789 diff --git a/projects/dl814_dj/dl814_dj_new_48m/project.tcl b/projects/dl814_dj/dl814_dj_new_48m/project.tcl index a9d91a75..deb82748 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/project.tcl +++ b/projects/dl814_dj/dl814_dj_new_48m/project.tcl @@ -3,7 +3,7 @@ # # project.tcl: Tcl script for re-creating project 'project' # -# Generated by Vivado on Sun Jul 09 14:59:13 CST 2023 +# Generated by Vivado on Sun Jul 30 19:14:09 CST 2023 # IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 # # This file contains the Vivado Tcl commands for re-creating the project to the state* @@ -39,20 +39,20 @@ # "/home/josh/Workspace/vivado-git/modules/xc7z100ffg900-2/tx_qpsk/ip/hrc_64_12_025/hrc_64_12_025.xci" # "/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/lpf_125k/lpf_125k.xci" # "/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/fifo_48m_to_122p88m/fifo_48m_to_122p88m.xci" +# "/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/rom_freq_word/rom_freq_word.xci" # "/home/josh/Workspace/vivado-git/projects/dl814_dj/common_ipi-bd/basic_driver_bd/system_bd.bd" +# "/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/sig_clk_gen/sig_clk_gen.xci" +# "/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/rtl/rf_auto_switch_freq.v" # "/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/rtl/rf_control.v" # "/home/josh/Workspace/vivado-git/projects/dl814_dj/common_ipi-bd/basic_driver_bd/hdl/system_bd_wrapper.v" # "/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/rtl/tx_control.v" # "/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/rtl/tx_pn_seq_6mcps.v" # "/home/josh/Workspace/vivado-git/modules/xc7z100ffg900-2/tx_qpsk/rtl/tx_qpsk.v" # "/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/rtl/system_top.v" -# "/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/rom_freq_word/rom_freq_word.xci" -# "/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/rtl/rf_auto_switch_freq.v" # "/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/coe/lpf_125k.coe" # "/home/josh/Workspace/vivado-git/modules/xc7z100ffg900-2/tx_qpsk/ip/coe/hrc_64_12_025.coe" # "/home/josh/Workspace/vivado-git/modules/xc7z100ffg900-2/tx_qpsk/ip/coe/sweep_freq.coe" # "/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/coe/freq_word.coe" -# "/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/sig_clk_gen/sig_clk_gen.xci" # "/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/constraints/z7100_ad9528_ad9371.xdc" # "/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/testbenches/tb_tx_pn_seq.v" # @@ -159,13 +159,13 @@ set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_use set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj set_property -name "simulator_language" -value "Mixed" -objects $obj set_property -name "target_simulator" -value "IES" -objects $obj -set_property -name "webtalk.activehdl_export_sim" -value "42" -objects $obj -set_property -name "webtalk.ies_export_sim" -value "42" -objects $obj -set_property -name "webtalk.modelsim_export_sim" -value "42" -objects $obj -set_property -name "webtalk.questa_export_sim" -value "42" -objects $obj -set_property -name "webtalk.riviera_export_sim" -value "42" -objects $obj -set_property -name "webtalk.vcs_export_sim" -value "42" -objects $obj -set_property -name "webtalk.xsim_export_sim" -value "42" -objects $obj +set_property -name "webtalk.activehdl_export_sim" -value "46" -objects $obj +set_property -name "webtalk.ies_export_sim" -value "46" -objects $obj +set_property -name "webtalk.modelsim_export_sim" -value "46" -objects $obj +set_property -name "webtalk.questa_export_sim" -value "46" -objects $obj +set_property -name "webtalk.riviera_export_sim" -value "46" -objects $obj +set_property -name "webtalk.vcs_export_sim" -value "46" -objects $obj +set_property -name "webtalk.xsim_export_sim" -value "46" -objects $obj set_property -name "xpm_libraries" -value "XPM_CDC XPM_FIFO XPM_MEMORY" -objects $obj # Create 'sources_1' fileset (if not found) @@ -188,15 +188,16 @@ set files [list \ [file normalize "${origin_dir}/../../../modules/xc7z100ffg900-2/tx_qpsk/ip/hrc_64_12_025/hrc_64_12_025.xci"] \ [file normalize "${origin_dir}/ip/lpf_125k/lpf_125k.xci"] \ [file normalize "${origin_dir}/ip/fifo_48m_to_122p88m/fifo_48m_to_122p88m.xci"] \ + [file normalize "${origin_dir}/ip/rom_freq_word/rom_freq_word.xci"] \ [file normalize "${origin_dir}/../common_ipi-bd/basic_driver_bd/system_bd.bd"] \ + [file normalize "${origin_dir}/ip/sig_clk_gen/sig_clk_gen.xci"] \ + [file normalize "${origin_dir}/rtl/rf_auto_switch_freq.v"] \ [file normalize "${origin_dir}/rtl/rf_control.v"] \ [file normalize "${origin_dir}/../common_ipi-bd/basic_driver_bd/hdl/system_bd_wrapper.v"] \ [file normalize "${origin_dir}/rtl/tx_control.v"] \ [file normalize "${origin_dir}/rtl/tx_pn_seq_6mcps.v"] \ [file normalize "${origin_dir}/../../../modules/xc7z100ffg900-2/tx_qpsk/rtl/tx_qpsk.v"] \ [file normalize "${origin_dir}/rtl/system_top.v"] \ - [file normalize "${origin_dir}/ip/rom_freq_word/rom_freq_word.xci"] \ - [file normalize "${origin_dir}/rtl/rf_auto_switch_freq.v"] \ [file normalize "${origin_dir}/ip/coe/lpf_125k.coe"] \ [file normalize "${origin_dir}/../../../modules/xc7z100ffg900-2/tx_qpsk/ip/coe/hrc_64_12_025.coe"] \ [file normalize "${origin_dir}/../../../modules/xc7z100ffg900-2/tx_qpsk/ip/coe/sweep_freq.coe"] \ @@ -313,12 +314,21 @@ if { ![get_property "is_locked" $file_obj] } { set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj } +set file "$origin_dir/ip/rom_freq_word/rom_freq_word.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + set file "$origin_dir/../common_ipi-bd/basic_driver_bd/system_bd.bd" set file [file normalize $file] set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] set_property -name "registered_with_manager" -value "1" -objects $file_obj -set file "$origin_dir/ip/rom_freq_word/rom_freq_word.xci" +set file "$origin_dir/ip/sig_clk_gen/sig_clk_gen.xci" set file [file normalize $file] set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] set_property -name "generate_files_for_reference" -value "0" -objects $file_obj @@ -336,27 +346,6 @@ set obj [get_filesets sources_1] set_property -name "top" -value "system_top" -objects $obj set_property -name "top_auto_set" -value "0" -objects $obj -# Set 'sources_1' fileset object -set obj [get_filesets sources_1] -set files [list \ - [file normalize "${origin_dir}/ip/sig_clk_gen/sig_clk_gen.xci"] \ -] -add_files -norecurse -fileset $obj $files - -# Set 'sources_1' fileset file properties for remote files -set file "$origin_dir/ip/sig_clk_gen/sig_clk_gen.xci" -set file [file normalize $file] -set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] -set_property -name "generate_files_for_reference" -value "0" -objects $file_obj -set_property -name "registered_with_manager" -value "1" -objects $file_obj -if { ![get_property "is_locked" $file_obj] } { - set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj -} - - -# Set 'sources_1' fileset file properties for local files -# None - # Create 'constrs_1' fileset (if not found) if {[string equal [get_filesets -quiet constrs_1] ""]} { create_fileset -constrset constrs_1 diff --git a/projects/dl814_dj/dl814_dj_new_48m/project/project.runs/impl_1/debug_nets.ltx b/projects/dl814_dj/dl814_dj_new_48m/project/project.runs/impl_1/debug_nets.ltx index c6cf2cfb..01a088f3 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/project/project.runs/impl_1/debug_nets.ltx +++ b/projects/dl814_dj/dl814_dj_new_48m/project/project.runs/impl_1/debug_nets.ltx @@ -982,9 +982,63 @@ "uuid": "364BEEA5FFA15F6D870138E33BF7A4F4", "pins": [ { - "name": "probe_out0", + "name": "probe_in0", "id": 26, "type": "DATA", + "direction": "IN", + "isVector": true, + "leftIndex": 0, + "rightIndex": 11, + "portIndex": 0, + "nets": [ + { + "name": "freq_hop_words_auto", + "isBus": true, + "subnets": [ + { + "name": "freq_hop_words_auto[11]" + }, + { + "name": "freq_hop_words_auto[10]" + }, + { + "name": "freq_hop_words_auto[9]" + }, + { + "name": "freq_hop_words_auto[8]" + }, + { + "name": "freq_hop_words_auto[7]" + }, + { + "name": "freq_hop_words_auto[6]" + }, + { + "name": "freq_hop_words_auto[5]" + }, + { + "name": "freq_hop_words_auto[4]" + }, + { + "name": "freq_hop_words_auto[3]" + }, + { + "name": "freq_hop_words_auto[2]" + }, + { + "name": "freq_hop_words_auto[1]" + }, + { + "name": "freq_hop_words_auto[0]" + } + ] + } + ] + }, + { + "name": "probe_out0", + "id": 27, + "type": "DATA", "direction": "OUT", "isVector": false, "leftIndex": 0, @@ -999,7 +1053,7 @@ }, { "name": "probe_out1", - "id": 27, + "id": 28, "type": "DATA", "direction": "OUT", "isVector": true, @@ -1023,7 +1077,7 @@ }, { "name": "probe_out2", - "id": 28, + "id": 29, "type": "DATA", "direction": "OUT", "isVector": false, @@ -1039,7 +1093,7 @@ }, { "name": "probe_out3", - "id": 29, + "id": 30, "type": "DATA", "direction": "OUT", "isVector": true, @@ -1081,7 +1135,7 @@ }, { "name": "probe_out4", - "id": 30, + "id": 31, "type": "DATA", "direction": "OUT", "isVector": true, @@ -1123,7 +1177,7 @@ }, { "name": "probe_out5", - "id": 31, + "id": 32, "type": "DATA", "direction": "OUT", "isVector": true, @@ -1177,7 +1231,7 @@ }, { "name": "probe_out6", - "id": 32, + "id": 33, "type": "DATA", "direction": "OUT", "isVector": false, @@ -1193,7 +1247,7 @@ }, { "name": "probe_out7", - "id": 33, + "id": 34, "type": "DATA", "direction": "OUT", "isVector": false, @@ -1209,7 +1263,7 @@ }, { "name": "probe_out8", - "id": 34, + "id": 35, "type": "DATA", "direction": "OUT", "isVector": false, @@ -1222,6 +1276,314 @@ "isBus": false } ] + }, + { + "name": "probe_out9", + "id": 36, + "type": "DATA", + "direction": "OUT", + "isVector": false, + "leftIndex": 0, + "rightIndex": 0, + "portIndex": 9, + "nets": [ + { + "name": "rf_auto_start_vio", + "isBus": false + } + ] + }, + { + "name": "probe_out10", + "id": 37, + "type": "DATA", + "direction": "OUT", + "isVector": false, + "leftIndex": 0, + "rightIndex": 0, + "portIndex": 10, + "nets": [ + { + "name": "rf_ctrl_mode_vio", + "isBus": false + } + ] + }, + { + "name": "probe_out11", + "id": 38, + "type": "DATA", + "direction": "OUT", + "isVector": false, + "leftIndex": 0, + "rightIndex": 0, + "portIndex": 11, + "nets": [ + { + "name": "switch_next_freq_vio", + "isBus": false + } + ] + }, + { + "name": "probe_out12", + "id": 39, + "type": "DATA", + "direction": "OUT", + "isVector": false, + "leftIndex": 0, + "rightIndex": 0, + "portIndex": 12, + "nets": [ + { + "name": "switch_last_freq_vio", + "isBus": false + } + ] + }, + { + "name": "probe_out13", + "id": 40, + "type": "DATA", + "direction": "OUT", + "isVector": true, + "leftIndex": 0, + "rightIndex": 31, + "portIndex": 13, + "nets": [ + { + "name": "cnt_valid_to_switch_vio", + "isBus": true, + "subnets": [ + { + "name": "cnt_valid_to_switch_vio[31]" + }, + { + "name": "cnt_valid_to_switch_vio[30]" + }, + { + "name": "cnt_valid_to_switch_vio[29]" + }, + { + "name": "cnt_valid_to_switch_vio[28]" + }, + { + "name": "cnt_valid_to_switch_vio[27]" + }, + { + "name": "cnt_valid_to_switch_vio[26]" + }, + { + "name": "cnt_valid_to_switch_vio[25]" + }, + { + "name": "cnt_valid_to_switch_vio[24]" + }, + { + "name": "cnt_valid_to_switch_vio[23]" + }, + { + "name": "cnt_valid_to_switch_vio[22]" + }, + { + "name": "cnt_valid_to_switch_vio[21]" + }, + { + "name": "cnt_valid_to_switch_vio[20]" + }, + { + "name": "cnt_valid_to_switch_vio[19]" + }, + { + "name": "cnt_valid_to_switch_vio[18]" + }, + { + "name": "cnt_valid_to_switch_vio[17]" + }, + { + "name": "cnt_valid_to_switch_vio[16]" + }, + { + "name": "cnt_valid_to_switch_vio[15]" + }, + { + "name": "cnt_valid_to_switch_vio[14]" + }, + { + "name": "cnt_valid_to_switch_vio[13]" + }, + { + "name": "cnt_valid_to_switch_vio[12]" + }, + { + "name": "cnt_valid_to_switch_vio[11]" + }, + { + "name": "cnt_valid_to_switch_vio[10]" + }, + { + "name": "cnt_valid_to_switch_vio[9]" + }, + { + "name": "cnt_valid_to_switch_vio[8]" + }, + { + "name": "cnt_valid_to_switch_vio[7]" + }, + { + "name": "cnt_valid_to_switch_vio[6]" + }, + { + "name": "cnt_valid_to_switch_vio[5]" + }, + { + "name": "cnt_valid_to_switch_vio[4]" + }, + { + "name": "cnt_valid_to_switch_vio[3]" + }, + { + "name": "cnt_valid_to_switch_vio[2]" + }, + { + "name": "cnt_valid_to_switch_vio[1]" + }, + { + "name": "cnt_valid_to_switch_vio[0]" + } + ] + } + ] + }, + { + "name": "probe_out14", + "id": 41, + "type": "DATA", + "direction": "OUT", + "isVector": false, + "leftIndex": 0, + "rightIndex": 0, + "portIndex": 14, + "nets": [ + { + "name": "auto_test_enable_vio", + "isBus": false + } + ] + }, + { + "name": "probe_out15", + "id": 42, + "type": "DATA", + "direction": "OUT", + "isVector": true, + "leftIndex": 0, + "rightIndex": 31, + "portIndex": 15, + "nets": [ + { + "name": "test_slot_length_vio", + "isBus": true, + "subnets": [ + { + "name": "test_slot_length_vio[31]" + }, + { + "name": "test_slot_length_vio[30]" + }, + { + "name": "test_slot_length_vio[29]" + }, + { + "name": "test_slot_length_vio[28]" + }, + { + "name": "test_slot_length_vio[27]" + }, + { + "name": "test_slot_length_vio[26]" + }, + { + "name": "test_slot_length_vio[25]" + }, + { + "name": "test_slot_length_vio[24]" + }, + { + "name": "test_slot_length_vio[23]" + }, + { + "name": "test_slot_length_vio[22]" + }, + { + "name": "test_slot_length_vio[21]" + }, + { + "name": "test_slot_length_vio[20]" + }, + { + "name": "test_slot_length_vio[19]" + }, + { + "name": "test_slot_length_vio[18]" + }, + { + "name": "test_slot_length_vio[17]" + }, + { + "name": "test_slot_length_vio[16]" + }, + { + "name": "test_slot_length_vio[15]" + }, + { + "name": "test_slot_length_vio[14]" + }, + { + "name": "test_slot_length_vio[13]" + }, + { + "name": "test_slot_length_vio[12]" + }, + { + "name": "test_slot_length_vio[11]" + }, + { + "name": "test_slot_length_vio[10]" + }, + { + "name": "test_slot_length_vio[9]" + }, + { + "name": "test_slot_length_vio[8]" + }, + { + "name": "test_slot_length_vio[7]" + }, + { + "name": "test_slot_length_vio[6]" + }, + { + "name": "test_slot_length_vio[5]" + }, + { + "name": "test_slot_length_vio[4]" + }, + { + "name": "test_slot_length_vio[3]" + }, + { + "name": "test_slot_length_vio[2]" + }, + { + "name": "test_slot_length_vio[1]" + }, + { + "name": "test_slot_length_vio[0]" + } + ] + } + ] } ] } diff --git a/projects/dl814_dj/dl814_dj_new_48m/project/project.runs/impl_1/system_top.bit b/projects/dl814_dj/dl814_dj_new_48m/project/project.runs/impl_1/system_top.bit index a7162a1e..e504109f 100644 Binary files a/projects/dl814_dj/dl814_dj_new_48m/project/project.runs/impl_1/system_top.bit and b/projects/dl814_dj/dl814_dj_new_48m/project/project.runs/impl_1/system_top.bit differ diff --git a/projects/dl814_dj/dl814_dj_new_48m/project/project.runs/impl_1/system_top.ltx b/projects/dl814_dj/dl814_dj_new_48m/project/project.runs/impl_1/system_top.ltx index c6cf2cfb..01a088f3 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/project/project.runs/impl_1/system_top.ltx +++ b/projects/dl814_dj/dl814_dj_new_48m/project/project.runs/impl_1/system_top.ltx @@ -982,9 +982,63 @@ "uuid": "364BEEA5FFA15F6D870138E33BF7A4F4", "pins": [ { - "name": "probe_out0", + "name": "probe_in0", "id": 26, "type": "DATA", + "direction": "IN", + "isVector": true, + "leftIndex": 0, + "rightIndex": 11, + "portIndex": 0, + "nets": [ + { + "name": "freq_hop_words_auto", + "isBus": true, + "subnets": [ + { + "name": "freq_hop_words_auto[11]" + }, + { + "name": "freq_hop_words_auto[10]" + }, + { + "name": "freq_hop_words_auto[9]" + }, + { + "name": "freq_hop_words_auto[8]" + }, + { + "name": "freq_hop_words_auto[7]" + }, + { + "name": "freq_hop_words_auto[6]" + }, + { + "name": "freq_hop_words_auto[5]" + }, + { + "name": "freq_hop_words_auto[4]" + }, + { + "name": "freq_hop_words_auto[3]" + }, + { + "name": "freq_hop_words_auto[2]" + }, + { + "name": "freq_hop_words_auto[1]" + }, + { + "name": "freq_hop_words_auto[0]" + } + ] + } + ] + }, + { + "name": "probe_out0", + "id": 27, + "type": "DATA", "direction": "OUT", "isVector": false, "leftIndex": 0, @@ -999,7 +1053,7 @@ }, { "name": "probe_out1", - "id": 27, + "id": 28, "type": "DATA", "direction": "OUT", "isVector": true, @@ -1023,7 +1077,7 @@ }, { "name": "probe_out2", - "id": 28, + "id": 29, "type": "DATA", "direction": "OUT", "isVector": false, @@ -1039,7 +1093,7 @@ }, { "name": "probe_out3", - "id": 29, + "id": 30, "type": "DATA", "direction": "OUT", "isVector": true, @@ -1081,7 +1135,7 @@ }, { "name": "probe_out4", - "id": 30, + "id": 31, "type": "DATA", "direction": "OUT", "isVector": true, @@ -1123,7 +1177,7 @@ }, { "name": "probe_out5", - "id": 31, + "id": 32, "type": "DATA", "direction": "OUT", "isVector": true, @@ -1177,7 +1231,7 @@ }, { "name": "probe_out6", - "id": 32, + "id": 33, "type": "DATA", "direction": "OUT", "isVector": false, @@ -1193,7 +1247,7 @@ }, { "name": "probe_out7", - "id": 33, + "id": 34, "type": "DATA", "direction": "OUT", "isVector": false, @@ -1209,7 +1263,7 @@ }, { "name": "probe_out8", - "id": 34, + "id": 35, "type": "DATA", "direction": "OUT", "isVector": false, @@ -1222,6 +1276,314 @@ "isBus": false } ] + }, + { + "name": "probe_out9", + "id": 36, + "type": "DATA", + "direction": "OUT", + "isVector": false, + "leftIndex": 0, + "rightIndex": 0, + "portIndex": 9, + "nets": [ + { + "name": "rf_auto_start_vio", + "isBus": false + } + ] + }, + { + "name": "probe_out10", + "id": 37, + "type": "DATA", + "direction": "OUT", + "isVector": false, + "leftIndex": 0, + "rightIndex": 0, + "portIndex": 10, + "nets": [ + { + "name": "rf_ctrl_mode_vio", + "isBus": false + } + ] + }, + { + "name": "probe_out11", + "id": 38, + "type": "DATA", + "direction": "OUT", + "isVector": false, + "leftIndex": 0, + "rightIndex": 0, + "portIndex": 11, + "nets": [ + { + "name": "switch_next_freq_vio", + "isBus": false + } + ] + }, + { + "name": "probe_out12", + "id": 39, + "type": "DATA", + "direction": "OUT", + "isVector": false, + "leftIndex": 0, + "rightIndex": 0, + "portIndex": 12, + "nets": [ + { + "name": "switch_last_freq_vio", + "isBus": false + } + ] + }, + { + "name": "probe_out13", + "id": 40, + "type": "DATA", + "direction": "OUT", + "isVector": true, + "leftIndex": 0, + "rightIndex": 31, + "portIndex": 13, + "nets": [ + { + "name": "cnt_valid_to_switch_vio", + "isBus": true, + "subnets": [ + { + "name": "cnt_valid_to_switch_vio[31]" + }, + { + "name": "cnt_valid_to_switch_vio[30]" + }, + { + "name": "cnt_valid_to_switch_vio[29]" + }, + { + "name": "cnt_valid_to_switch_vio[28]" + }, + { + "name": "cnt_valid_to_switch_vio[27]" + }, + { + "name": "cnt_valid_to_switch_vio[26]" + }, + { + "name": "cnt_valid_to_switch_vio[25]" + }, + { + "name": "cnt_valid_to_switch_vio[24]" + }, + { + "name": "cnt_valid_to_switch_vio[23]" + }, + { + "name": "cnt_valid_to_switch_vio[22]" + }, + { + "name": "cnt_valid_to_switch_vio[21]" + }, + { + "name": "cnt_valid_to_switch_vio[20]" + }, + { + "name": "cnt_valid_to_switch_vio[19]" + }, + { + "name": "cnt_valid_to_switch_vio[18]" + }, + { + "name": "cnt_valid_to_switch_vio[17]" + }, + { + "name": "cnt_valid_to_switch_vio[16]" + }, + { + "name": "cnt_valid_to_switch_vio[15]" + }, + { + "name": "cnt_valid_to_switch_vio[14]" + }, + { + "name": "cnt_valid_to_switch_vio[13]" + }, + { + "name": "cnt_valid_to_switch_vio[12]" + }, + { + "name": "cnt_valid_to_switch_vio[11]" + }, + { + "name": "cnt_valid_to_switch_vio[10]" + }, + { + "name": "cnt_valid_to_switch_vio[9]" + }, + { + "name": "cnt_valid_to_switch_vio[8]" + }, + { + "name": "cnt_valid_to_switch_vio[7]" + }, + { + "name": "cnt_valid_to_switch_vio[6]" + }, + { + "name": "cnt_valid_to_switch_vio[5]" + }, + { + "name": "cnt_valid_to_switch_vio[4]" + }, + { + "name": "cnt_valid_to_switch_vio[3]" + }, + { + "name": "cnt_valid_to_switch_vio[2]" + }, + { + "name": "cnt_valid_to_switch_vio[1]" + }, + { + "name": "cnt_valid_to_switch_vio[0]" + } + ] + } + ] + }, + { + "name": "probe_out14", + "id": 41, + "type": "DATA", + "direction": "OUT", + "isVector": false, + "leftIndex": 0, + "rightIndex": 0, + "portIndex": 14, + "nets": [ + { + "name": "auto_test_enable_vio", + "isBus": false + } + ] + }, + { + "name": "probe_out15", + "id": 42, + "type": "DATA", + "direction": "OUT", + "isVector": true, + "leftIndex": 0, + "rightIndex": 31, + "portIndex": 15, + "nets": [ + { + "name": "test_slot_length_vio", + "isBus": true, + "subnets": [ + { + "name": "test_slot_length_vio[31]" + }, + { + "name": "test_slot_length_vio[30]" + }, + { + "name": "test_slot_length_vio[29]" + }, + { + "name": "test_slot_length_vio[28]" + }, + { + "name": "test_slot_length_vio[27]" + }, + { + "name": "test_slot_length_vio[26]" + }, + { + "name": "test_slot_length_vio[25]" + }, + { + "name": "test_slot_length_vio[24]" + }, + { + "name": "test_slot_length_vio[23]" + }, + { + "name": "test_slot_length_vio[22]" + }, + { + "name": "test_slot_length_vio[21]" + }, + { + "name": "test_slot_length_vio[20]" + }, + { + "name": "test_slot_length_vio[19]" + }, + { + "name": "test_slot_length_vio[18]" + }, + { + "name": "test_slot_length_vio[17]" + }, + { + "name": "test_slot_length_vio[16]" + }, + { + "name": "test_slot_length_vio[15]" + }, + { + "name": "test_slot_length_vio[14]" + }, + { + "name": "test_slot_length_vio[13]" + }, + { + "name": "test_slot_length_vio[12]" + }, + { + "name": "test_slot_length_vio[11]" + }, + { + "name": "test_slot_length_vio[10]" + }, + { + "name": "test_slot_length_vio[9]" + }, + { + "name": "test_slot_length_vio[8]" + }, + { + "name": "test_slot_length_vio[7]" + }, + { + "name": "test_slot_length_vio[6]" + }, + { + "name": "test_slot_length_vio[5]" + }, + { + "name": "test_slot_length_vio[4]" + }, + { + "name": "test_slot_length_vio[3]" + }, + { + "name": "test_slot_length_vio[2]" + }, + { + "name": "test_slot_length_vio[1]" + }, + { + "name": "test_slot_length_vio[0]" + } + ] + } + ] } ] } diff --git a/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/system_top.hdf b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/system_top.hdf index 4c456da9..0817d4be 100644 Binary files a/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/system_top.hdf and b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/system_top.hdf differ diff --git a/projects/dl814_dj/dl814_dj_new_48m/rtl/rf_auto_switch_freq.v b/projects/dl814_dj/dl814_dj_new_48m/rtl/rf_auto_switch_freq.v index be7e9207..585a1773 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/rtl/rf_auto_switch_freq.v +++ b/projects/dl814_dj/dl814_dj_new_48m/rtl/rf_auto_switch_freq.v @@ -110,7 +110,7 @@ always @ (posedge clk) reg [11:0] local_freq_word = 12'd0; reg local_freq_word_valid = 1'b0; reg local_freq_word_switch = 1'b0; -wire [10:0] rom_freq_word_dout; +wire [11:0] rom_freq_word_dout; // 2 clock latency rom_freq_word rom_freq_word_inst( .clka (clk ), diff --git a/projects/dl814_dj/dl814_dj_new_48m/rtl/system_top.v b/projects/dl814_dj/dl814_dj_new_48m/rtl/system_top.v index 93cedf34..6e69c4f2 100644 --- a/projects/dl814_dj/dl814_dj_new_48m/rtl/system_top.v +++ b/projects/dl814_dj/dl814_dj_new_48m/rtl/system_top.v @@ -107,7 +107,12 @@ module system_top inout [53:0] fixed_io_mio , inout fixed_io_ps_clk , inout fixed_io_ps_porb , - inout fixed_io_ps_srstb + inout fixed_io_ps_srstb , + // ************************************************************************* + // ************************* Sync Signal *********************************** + // ************************************************************************* + output sync_signal_out , + output reg sync_gnd = 1'b0 ); @@ -270,6 +275,41 @@ wire [11:0] freq_hop_words_vio ; wire hop_words_valid_vio; wire freq_hop_switch_vio; +// rf auto switch frequency function +wire auto_test_enable_vio; +wire rf_auto_start_vio ; +wire rf_ctrl_mode_vio ; +wire switch_next_freq_vio; +wire switch_last_freq_vio; +wire [31:0] cnt_valid_to_switch_vio; +wire [31:0] test_slot_length_vio; + +wire [11:0] freq_hop_words_auto ; +wire hop_words_valid_auto; +wire freq_hop_switch_auto; + +rf_auto_switch_freq u_rf_auto_switch_freq( + .clk (sig_clk_4x ), + .rst (sig_rst ), + // vio control + .start (rf_auto_start_vio ), // rise-edge active, if start, change freq word to the first + .auto_test_enable (auto_test_enable_vio ), // rise-edge active + .rf_ctrl_mode (rf_ctrl_mode_vio ), // 1 : auto switch, 0 : manual switch + .switch_next_freq (switch_next_freq_vio ), // rise-edge active + .switch_last_freq (switch_last_freq_vio ), // rise-edge active + .cnt_valid_to_switch (cnt_valid_to_switch_vio ), // the clock number from valid to switch + .test_slot_length (test_slot_length_vio[31:0] ), + // input + .freq_hop_words_vio (freq_hop_words_vio[11:0] ), + .hop_words_valid_vio (hop_words_valid_vio ), + .freq_hop_switch_vio (freq_hop_switch_vio ), + // output + .freq_hop_words_auto (freq_hop_words_auto[11:0] ), + .hop_words_valid_auto (hop_words_valid_auto ), + .freq_hop_switch_auto (freq_hop_switch_auto ), + .sync_signal (sync_signal_out ) +); + rf_control u_rf_control ( // clock & reset @@ -292,9 +332,9 @@ rf_control u_rf_control .rf_txrx_vio (rf_txrx_vio[1:0] ), // vio控制收发，1发2收 // vio freq control - .freq_hop_words_vio (freq_hop_words_vio[11:0] ), // vio设置跳频频率控制字 - .hop_words_valid_vio (hop_words_valid_vio ), // vio设置跳频频率控制字有效脉冲 - .freq_hop_switch_vio (freq_hop_switch_vio ), // vio设置频点切换脉冲 + .freq_hop_words_vio (freq_hop_words_auto[11:0] ), // vio设置跳频频率控制字 + .hop_words_valid_vio (hop_words_valid_auto ), // vio设置跳频频率控制字有效脉冲 + .freq_hop_switch_vio (freq_hop_switch_auto ), // vio设置频点切换脉冲 // manual configuration .vio_set_trx (vio_set_trx ), // 0: 网络层控制收发，1: vio控制收发 @@ -431,16 +471,24 @@ vio_manual_ctrl u_vio_manual_ctrl vio_RF_control u_vio_rf_control ( - .clk (sig_clk_4x ), // input wire clk - .probe_out0 (vio_set_trx ), // output wire [0 : 0] probe_out0 - .probe_out1 (rf_txrx_vio[1:0] ), // output wire [1 : 0] probe_out1 - .probe_out2 (vio_set_freq ), // output wire [0 : 0] probe_out2 - .probe_out3 (tx_gain_manual[7:0] ), // output wire [5 : 0] probe_out3 - .probe_out4 (rx_gain_manual[7:0] ), // output wire [5 : 0] probe_out4 - .probe_out5 (freq_hop_words_vio[11:0] ), // output wire [10 : 0] probe_out5 - .probe_out6 (hop_words_valid_vio ), // output wire [0 : 0] probe_out6 - .probe_out7 (freq_hop_switch_vio ), // output wire [0 : 0] probe_out7 - .probe_out8 (rf_config_valid ) // output wire [0 : 0] probe_out8 + .clk (sig_clk_4x ), // input wire clk + .probe_out0 (vio_set_trx ), // output wire [0 : 0] probe_out0 + .probe_out1 (rf_txrx_vio[1:0] ), // output wire [1 : 0] probe_out1 + .probe_out2 (vio_set_freq ), // output wire [0 : 0] probe_out2 + .probe_out3 (tx_gain_manual[7:0] ), // output wire [5 : 0] probe_out3 + .probe_out4 (rx_gain_manual[7:0] ), // output wire [5 : 0] probe_out4 + .probe_out5 (freq_hop_words_vio[11:0] ), // output wire [11 : 0] probe_out5 + .probe_out6 (hop_words_valid_vio ), // output wire [0 : 0] probe_out6 + .probe_out7 (freq_hop_switch_vio ), // output wire [0 : 0] probe_out7 + .probe_out8 (rf_config_valid ), // output wire [0 : 0] probe_out8 + .probe_out9 (rf_auto_start_vio ), // output wire [0 : 0] probe_out9 + .probe_out10(rf_ctrl_mode_vio ), // output wire [0 : 0] probe_out10 + .probe_out11(switch_next_freq_vio ), // output wire [0 : 0] probe_out11 + .probe_out12(switch_last_freq_vio ), // output wire [0 : 0] probe_out12 + .probe_out13(cnt_valid_to_switch_vio[31:0] ), // output wire [31: 0] probe_out13 + .probe_out14(auto_test_enable_vio ), // output wire [0 : 0] probe_out14 + .probe_out15(test_slot_length_vio[31:0] ), // output wire [31: 0] probe_out15 + .probe_in0 (freq_hop_words_auto[11:0] ) // input wire [11: 0] probe_in0 ); ila_rf_test u_ila_rf_test diff --git a/projects/dl814_k7/common_ip/ip_user_files/ip/fifo_weight_cdc/fifo_weight_cdc.veo b/projects/dl814_k7/common_ip/ip_user_files/ip/fifo_weight_cdc/fifo_weight_cdc.veo index b2eeff41..e11a1127 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/ip/fifo_weight_cdc/fifo_weight_cdc.veo +++ b/projects/dl814_k7/common_ip/ip_user_files/ip/fifo_weight_cdc/fifo_weight_cdc.veo @@ -64,7 +64,7 @@ fifo_weight_cdc your_instance_name ( .dout(dout), // output wire [15 : 0] dout .full(full), // output wire full .empty(empty), // output wire empty - .rd_data_count(rd_data_count) // output wire [4 : 0] rd_data_count + .rd_data_count(rd_data_count) // output wire [3 : 0] rd_data_count ); // INST_TAG_END ------ End INSTANTIATION Template --------- diff --git a/projects/dl814_k7/common_ip/ip_user_files/ip/fifo_weight_cdc/fifo_weight_cdc.vho b/projects/dl814_k7/common_ip/ip_user_files/ip/fifo_weight_cdc/fifo_weight_cdc.vho index 63cdea58..6ec60602 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/ip/fifo_weight_cdc/fifo_weight_cdc.vho +++ b/projects/dl814_k7/common_ip/ip_user_files/ip/fifo_weight_cdc/fifo_weight_cdc.vho @@ -63,7 +63,7 @@ COMPONENT fifo_weight_cdc dout : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); full : OUT STD_LOGIC; empty : OUT STD_LOGIC; - rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0) + rd_data_count : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ); END COMPONENT; -- COMP_TAG_END ------ End COMPONENT Declaration ------------ diff --git a/projects/dl814_k7/common_ip/ip_user_files/ip/fifo_weight_cdc/fifo_weight_cdc_sim_netlist.v b/projects/dl814_k7/common_ip/ip_user_files/ip/fifo_weight_cdc/fifo_weight_cdc_sim_netlist.v index 04ed0f14..8bd2576f 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/ip/fifo_weight_cdc/fifo_weight_cdc_sim_netlist.v +++ b/projects/dl814_k7/common_ip/ip_user_files/ip/fifo_weight_cdc/fifo_weight_cdc_sim_netlist.v @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:9f6b9f41e6b750815b3df3f401b33d089932b215b57b5695ece5bddc2051660c -size 122740 +oid sha256:b7e861eb8dae0f9cf48694f53354b61efe7da4098a68c956af72d1769d09ca00 +size 116956 diff --git a/projects/dl814_k7/common_ip/ip_user_files/ip/fifo_weight_cdc/fifo_weight_cdc_sim_netlist.vhdl b/projects/dl814_k7/common_ip/ip_user_files/ip/fifo_weight_cdc/fifo_weight_cdc_sim_netlist.vhdl index e2a6813c..8e0e1848 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/ip/fifo_weight_cdc/fifo_weight_cdc_sim_netlist.vhdl +++ b/projects/dl814_k7/common_ip/ip_user_files/ip/fifo_weight_cdc/fifo_weight_cdc_sim_netlist.vhdl @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:66f705fc665db64823b6184f7ed26098f960cd59a5f6d4dcd7dfbee4299b091f -size 187563 +oid sha256:2136d4696ef8b7d782f4cfc7cc5870c10ad5309f79517600772d820b1f931237 +size 181436 diff --git a/projects/dl814_k7/common_ip/ip_user_files/ip/fifo_weight_cdc/fifo_weight_cdc_stub.v b/projects/dl814_k7/common_ip/ip_user_files/ip/fifo_weight_cdc/fifo_weight_cdc_stub.v index ad8d85bb..0bd41308 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/ip/fifo_weight_cdc/fifo_weight_cdc_stub.v +++ b/projects/dl814_k7/common_ip/ip_user_files/ip/fifo_weight_cdc/fifo_weight_cdc_stub.v @@ -1,10 +1,10 @@ // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 -// Date : Wed Apr 19 16:13:44 2023 +// Date : Thu Jul 27 11:21:03 2023 // Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS -// Command : write_verilog -force -mode synth_stub -rename_top fifo_weight_cdc -prefix -// fifo_weight_cdc_ fifo_weight_cdc_stub.v +// Command : write_verilog -force -mode synth_stub +// /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/fifo_weight_cdc_stub.v // Design : fifo_weight_cdc // Purpose : Stub declaration of top-level module interface // Device : xc7k410tffg900-2 @@ -16,7 +16,7 @@ (* x_core_info = "fifo_generator_v13_2_4,Vivado 2019.1.3" *) module fifo_weight_cdc(rst, wr_clk, rd_clk, din, wr_en, rd_en, dout, full, empty, rd_data_count) -/* synthesis syn_black_box black_box_pad_pin="rst,wr_clk,rd_clk,din[15:0],wr_en,rd_en,dout[15:0],full,empty,rd_data_count[4:0]" */; +/* synthesis syn_black_box black_box_pad_pin="rst,wr_clk,rd_clk,din[15:0],wr_en,rd_en,dout[15:0],full,empty,rd_data_count[3:0]" */; input rst; input wr_clk; input rd_clk; @@ -26,5 +26,5 @@ module fifo_weight_cdc(rst, wr_clk, rd_clk, din, wr_en, rd_en, dout, full, output [15:0]dout; output full; output empty; - output [4:0]rd_data_count; + output [3:0]rd_data_count; endmodule diff --git a/projects/dl814_k7/common_ip/ip_user_files/ip/fifo_weight_cdc/fifo_weight_cdc_stub.vhdl b/projects/dl814_k7/common_ip/ip_user_files/ip/fifo_weight_cdc/fifo_weight_cdc_stub.vhdl index 54fbd7d9..d131c4c0 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/ip/fifo_weight_cdc/fifo_weight_cdc_stub.vhdl +++ b/projects/dl814_k7/common_ip/ip_user_files/ip/fifo_weight_cdc/fifo_weight_cdc_stub.vhdl @@ -1,10 +1,10 @@ -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 --- Date : Wed Apr 19 16:13:44 2023 +-- Date : Thu Jul 27 11:21:03 2023 -- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS --- Command : write_vhdl -force -mode synth_stub -rename_top fifo_weight_cdc -prefix --- fifo_weight_cdc_ fifo_weight_cdc_stub.vhdl +-- Command : write_vhdl -force -mode synth_stub +-- /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/fifo_weight_cdc_stub.vhdl -- Design : fifo_weight_cdc -- Purpose : Stub declaration of top-level module interface -- Device : xc7k410tffg900-2 @@ -23,7 +23,7 @@ entity fifo_weight_cdc is dout : out STD_LOGIC_VECTOR ( 15 downto 0 ); full : out STD_LOGIC; empty : out STD_LOGIC; - rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 ) + rd_data_count : out STD_LOGIC_VECTOR ( 3 downto 0 ) ); end fifo_weight_cdc; @@ -32,7 +32,7 @@ architecture stub of fifo_weight_cdc is attribute syn_black_box : boolean; attribute black_box_pad_pin : string; attribute syn_black_box of stub : architecture is true; -attribute black_box_pad_pin of stub : architecture is "rst,wr_clk,rd_clk,din[15:0],wr_en,rd_en,dout[15:0],full,empty,rd_data_count[4:0]"; +attribute black_box_pad_pin of stub : architecture is "rst,wr_clk,rd_clk,din[15:0],wr_en,rd_en,dout[15:0],full,empty,rd_data_count[3:0]"; attribute x_core_info : string; attribute x_core_info of stub : architecture is "fifo_generator_v13_2_4,Vivado 2019.1.3"; begin diff --git a/projects/dl814_k7/common_ip/ip_user_files/ip/fifo_weight_cdc/sim/fifo_weight_cdc.v b/projects/dl814_k7/common_ip/ip_user_files/ip/fifo_weight_cdc/sim/fifo_weight_cdc.v index 50250ebb..2b218a7d 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/ip/fifo_weight_cdc/sim/fifo_weight_cdc.v +++ b/projects/dl814_k7/common_ip/ip_user_files/ip/fifo_weight_cdc/sim/fifo_weight_cdc.v @@ -85,13 +85,13 @@ output wire [15 : 0] dout; output wire full; (* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY" *) output wire empty; -output wire [4 : 0] rd_data_count; +output wire [3 : 0] rd_data_count; fifo_generator_v13_2_4 #( .C_COMMON_CLOCK(0), .C_SELECT_XPM(0), .C_COUNT_TYPE(0), - .C_DATA_COUNT_WIDTH(5), + .C_DATA_COUNT_WIDTH(4), .C_DEFAULT_VALUE("BlankString"), .C_DIN_WIDTH(16), .C_DOUT_RST_VAL("0"), @@ -127,13 +127,13 @@ output wire [4 : 0] rd_data_count; .C_PROG_EMPTY_THRESH_ASSERT_VAL(2), .C_PROG_EMPTY_THRESH_NEGATE_VAL(3), .C_PROG_EMPTY_TYPE(0), - .C_PROG_FULL_THRESH_ASSERT_VAL(29), - .C_PROG_FULL_THRESH_NEGATE_VAL(28), + .C_PROG_FULL_THRESH_ASSERT_VAL(13), + .C_PROG_FULL_THRESH_NEGATE_VAL(12), .C_PROG_FULL_TYPE(0), - .C_RD_DATA_COUNT_WIDTH(5), - .C_RD_DEPTH(32), + .C_RD_DATA_COUNT_WIDTH(4), + .C_RD_DEPTH(16), .C_RD_FREQ(1), - .C_RD_PNTR_WIDTH(5), + .C_RD_PNTR_WIDTH(4), .C_UNDERFLOW_LOW(0), .C_USE_DOUT_RST(1), .C_USE_ECC(0), @@ -144,10 +144,10 @@ output wire [4 : 0] rd_data_count; .C_USE_FWFT_DATA_COUNT(0), .C_VALID_LOW(0), .C_WR_ACK_LOW(0), - .C_WR_DATA_COUNT_WIDTH(5), - .C_WR_DEPTH(32), + .C_WR_DATA_COUNT_WIDTH(4), + .C_WR_DEPTH(16), .C_WR_FREQ(1), - .C_WR_PNTR_WIDTH(5), + .C_WR_PNTR_WIDTH(4), .C_WR_RESPONSE_LATENCY(1), .C_MSGON_VAL(1), .C_ENABLE_RST_SYNC(1), @@ -303,12 +303,12 @@ output wire [4 : 0] rd_data_count; .din(din), .wr_en(wr_en), .rd_en(rd_en), - .prog_empty_thresh(5'B0), - .prog_empty_thresh_assert(5'B0), - .prog_empty_thresh_negate(5'B0), - .prog_full_thresh(5'B0), - .prog_full_thresh_assert(5'B0), - .prog_full_thresh_negate(5'B0), + .prog_empty_thresh(4'B0), + .prog_empty_thresh_assert(4'B0), + .prog_empty_thresh_negate(4'B0), + .prog_full_thresh(4'B0), + .prog_full_thresh_assert(4'B0), + .prog_full_thresh_negate(4'B0), .int_clk(1'D0), .injectdbiterr(1'D0), .injectsbiterr(1'D0), diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/activehdl/README.txt b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/activehdl/README.txt index 593662a6..86d23fb7 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/activehdl/README.txt +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/activehdl/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Wed Apr 19 16:55:15 CST 2023 +# Generated by export_simulation on Thu Jul 27 11:20:38 CST 2023 # ################################################################################ diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/activehdl/compile.do b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/activehdl/compile.do index 0a56533d..b96faa68 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/activehdl/compile.do +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/activehdl/compile.do @@ -10,11 +10,11 @@ vmap xpm activehdl/xpm vmap fifo_generator_v13_2_4 activehdl/fifo_generator_v13_2_4 vlog -work xil_defaultlib -sv2k12 \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ vcom -work xpm -93 \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ vlog -work fifo_generator_v13_2_4 -v2k5 \ "../../../ipstatic/simulation/fifo_generator_vlog_beh.v" \ diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/activehdl/fifo_weight_cdc.sh b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/activehdl/fifo_weight_cdc.sh index 7ab7372e..61152070 100755 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/activehdl/fifo_weight_cdc.sh +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/activehdl/fifo_weight_cdc.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Wed Apr 19 16:55:15 CST 2023 +# Generated by Vivado on Thu Jul 27 11:20:38 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/activehdl/file_info.txt b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/activehdl/file_info.txt index f713ae5d..04031eec 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/activehdl/file_info.txt +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/activehdl/file_info.txt @@ -1,6 +1,6 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, -xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, -xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_4,../../../ipstatic/simulation/fifo_generator_vlog_beh.v, fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_4,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd, fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_4,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v, diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/ies/README.txt b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/ies/README.txt index ae5407ad..3b5b6e56 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/ies/README.txt +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/ies/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Wed Apr 19 16:55:15 CST 2023 +# Generated by export_simulation on Thu Jul 27 11:20:38 CST 2023 # ################################################################################ diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/ies/fifo_weight_cdc.sh b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/ies/fifo_weight_cdc.sh index 576501c0..86467543 100755 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/ies/fifo_weight_cdc.sh +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/ies/fifo_weight_cdc.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Wed Apr 19 16:55:15 CST 2023 +# Generated by Vivado on Thu Jul 27 11:20:38 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/ies/file_info.txt b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/ies/file_info.txt index f713ae5d..04031eec 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/ies/file_info.txt +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/ies/file_info.txt @@ -1,6 +1,6 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, -xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, -xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_4,../../../ipstatic/simulation/fifo_generator_vlog_beh.v, fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_4,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd, fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_4,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v, diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/ies/run.f b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/ies/run.f index 7f15418b..4a0b992c 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/ies/run.f +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/ies/run.f @@ -1,9 +1,9 @@ -makelib ies_lib/xil_defaultlib -sv \ - "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ - "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + "/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ -endlib -makelib ies_lib/xpm \ - "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + "/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ -endlib -makelib ies_lib/fifo_generator_v13_2_4 \ "../../../ipstatic/simulation/fifo_generator_vlog_beh.v" \ diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/modelsim/README.txt b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/modelsim/README.txt index 593662a6..86d23fb7 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/modelsim/README.txt +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/modelsim/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Wed Apr 19 16:55:15 CST 2023 +# Generated by export_simulation on Thu Jul 27 11:20:38 CST 2023 # ################################################################################ diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/modelsim/compile.do b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/modelsim/compile.do index c98d7d98..6c9f6e63 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/modelsim/compile.do +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/modelsim/compile.do @@ -10,11 +10,11 @@ vmap xpm modelsim_lib/msim/xpm vmap fifo_generator_v13_2_4 modelsim_lib/msim/fifo_generator_v13_2_4 vlog -work xil_defaultlib -64 -incr -sv \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ vcom -work xpm -64 -93 \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ vlog -work fifo_generator_v13_2_4 -64 -incr \ "../../../ipstatic/simulation/fifo_generator_vlog_beh.v" \ diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/modelsim/fifo_weight_cdc.sh b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/modelsim/fifo_weight_cdc.sh index 7eefdb49..4eaa64f4 100755 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/modelsim/fifo_weight_cdc.sh +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/modelsim/fifo_weight_cdc.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Wed Apr 19 16:55:15 CST 2023 +# Generated by Vivado on Thu Jul 27 11:20:38 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/modelsim/file_info.txt b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/modelsim/file_info.txt index f713ae5d..04031eec 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/modelsim/file_info.txt +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/modelsim/file_info.txt @@ -1,6 +1,6 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, -xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, -xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_4,../../../ipstatic/simulation/fifo_generator_vlog_beh.v, fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_4,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd, fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_4,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v, diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/questa/README.txt b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/questa/README.txt index 593662a6..86d23fb7 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/questa/README.txt +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/questa/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Wed Apr 19 16:55:15 CST 2023 +# Generated by export_simulation on Thu Jul 27 11:20:38 CST 2023 # ################################################################################ diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/questa/compile.do b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/questa/compile.do index 30475ae9..5ba0d03c 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/questa/compile.do +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/questa/compile.do @@ -10,11 +10,11 @@ vmap xpm questa_lib/msim/xpm vmap fifo_generator_v13_2_4 questa_lib/msim/fifo_generator_v13_2_4 vlog -work xil_defaultlib -64 -sv \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ vcom -work xpm -64 -93 \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ vlog -work fifo_generator_v13_2_4 -64 \ "../../../ipstatic/simulation/fifo_generator_vlog_beh.v" \ diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/questa/fifo_weight_cdc.sh b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/questa/fifo_weight_cdc.sh index 17fd16ae..5ec7d9f8 100755 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/questa/fifo_weight_cdc.sh +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/questa/fifo_weight_cdc.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Wed Apr 19 16:55:15 CST 2023 +# Generated by Vivado on Thu Jul 27 11:20:38 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/questa/file_info.txt b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/questa/file_info.txt index f713ae5d..04031eec 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/questa/file_info.txt +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/questa/file_info.txt @@ -1,6 +1,6 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, -xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, -xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_4,../../../ipstatic/simulation/fifo_generator_vlog_beh.v, fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_4,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd, fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_4,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v, diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/riviera/README.txt b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/riviera/README.txt index 593662a6..86d23fb7 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/riviera/README.txt +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/riviera/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Wed Apr 19 16:55:15 CST 2023 +# Generated by export_simulation on Thu Jul 27 11:20:38 CST 2023 # ################################################################################ diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/riviera/compile.do b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/riviera/compile.do index 7408bc90..84c9d3e1 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/riviera/compile.do +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/riviera/compile.do @@ -10,11 +10,11 @@ vmap xpm riviera/xpm vmap fifo_generator_v13_2_4 riviera/fifo_generator_v13_2_4 vlog -work xil_defaultlib -sv2k12 \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ vcom -work xpm -93 \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ vlog -work fifo_generator_v13_2_4 -v2k5 \ "../../../ipstatic/simulation/fifo_generator_vlog_beh.v" \ diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/riviera/fifo_weight_cdc.sh b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/riviera/fifo_weight_cdc.sh index f4f2dcd2..bec88cfb 100755 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/riviera/fifo_weight_cdc.sh +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/riviera/fifo_weight_cdc.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Wed Apr 19 16:55:15 CST 2023 +# Generated by Vivado on Thu Jul 27 11:20:38 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/riviera/file_info.txt b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/riviera/file_info.txt index f713ae5d..04031eec 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/riviera/file_info.txt +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/riviera/file_info.txt @@ -1,6 +1,6 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, -xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, -xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_4,../../../ipstatic/simulation/fifo_generator_vlog_beh.v, fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_4,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd, fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_4,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v, diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/vcs/README.txt b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/vcs/README.txt index 593662a6..86d23fb7 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/vcs/README.txt +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/vcs/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Wed Apr 19 16:55:15 CST 2023 +# Generated by export_simulation on Thu Jul 27 11:20:38 CST 2023 # ################################################################################ diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/vcs/fifo_weight_cdc.sh b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/vcs/fifo_weight_cdc.sh index d95ac90c..99762905 100755 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/vcs/fifo_weight_cdc.sh +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/vcs/fifo_weight_cdc.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Wed Apr 19 16:55:15 CST 2023 +# Generated by Vivado on Thu Jul 27 11:20:38 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. @@ -71,12 +71,12 @@ compile() { # Compile design files vlogan -work xil_defaultlib $vlogan_opts -sverilog \ - "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ - "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + "/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ 2>&1 | tee -a vlogan.log vhdlan -work xpm $vhdlan_opts \ - "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + "/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ 2>&1 | tee -a vhdlan.log vlogan -work fifo_generator_v13_2_4 $vlogan_opts +v2k \ diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/vcs/file_info.txt b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/vcs/file_info.txt index f713ae5d..04031eec 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/vcs/file_info.txt +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/vcs/file_info.txt @@ -1,6 +1,6 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, -xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, -xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_4,../../../ipstatic/simulation/fifo_generator_vlog_beh.v, fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_4,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd, fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_4,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v, diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/xcelium/README.txt b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/xcelium/README.txt index ae5407ad..3b5b6e56 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/xcelium/README.txt +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/xcelium/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Wed Apr 19 16:55:15 CST 2023 +# Generated by export_simulation on Thu Jul 27 11:20:38 CST 2023 # ################################################################################ diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/xcelium/fifo_weight_cdc.sh b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/xcelium/fifo_weight_cdc.sh index e1c28890..b6c3319a 100755 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/xcelium/fifo_weight_cdc.sh +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/xcelium/fifo_weight_cdc.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Wed Apr 19 16:55:15 CST 2023 +# Generated by Vivado on Thu Jul 27 11:20:38 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/xcelium/file_info.txt b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/xcelium/file_info.txt index f713ae5d..04031eec 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/xcelium/file_info.txt +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/xcelium/file_info.txt @@ -1,6 +1,6 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, -xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, -xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_4,../../../ipstatic/simulation/fifo_generator_vlog_beh.v, fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_4,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd, fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_4,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v, diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/xcelium/run.f b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/xcelium/run.f index f07b17b7..20d362e1 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/xcelium/run.f +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/xcelium/run.f @@ -1,9 +1,9 @@ -makelib xcelium_lib/xil_defaultlib -sv \ - "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ - "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + "/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ -endlib -makelib xcelium_lib/xpm \ - "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + "/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ -endlib -makelib xcelium_lib/fifo_generator_v13_2_4 \ "../../../ipstatic/simulation/fifo_generator_vlog_beh.v" \ diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/xsim/README.txt b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/xsim/README.txt index 593662a6..86d23fb7 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/xsim/README.txt +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/xsim/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Wed Apr 19 16:55:15 CST 2023 +# Generated by export_simulation on Thu Jul 27 11:20:38 CST 2023 # ################################################################################ diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/xsim/fifo_weight_cdc.sh b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/xsim/fifo_weight_cdc.sh index 3df132d7..38c609de 100755 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/xsim/fifo_weight_cdc.sh +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/fifo_weight_cdc/xsim/fifo_weight_cdc.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Wed Apr 19 16:55:15 CST 2023 +# Generated by Vivado on Thu Jul 27 11:20:38 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. @@ -22,7 +22,7 @@ #********************************************************************************************************* # Command line options -xv_boost_lib_path=/tools/Xilinx/Vivado/2019.1/tps/boost_1_64_0 +xv_boost_lib_path=/home/josh/Software/Xilinx/Vivado/2019.1/tps/boost_1_64_0 xvlog_opts="--relax" xvhdl_opts="--relax" @@ -94,7 +94,7 @@ setup() copy_setup_file() { file="xsim.ini" - lib_map_path="/tools/Xilinx/Vivado/2019.1/data/xsim" + lib_map_path="/home/josh/Software/Xilinx/Vivado/2019.1/data/xsim" if [[ ($1 != "") ]]; then lib_map_path="$1" fi diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/1856916a0c14314d/1856916a0c14314d.xci b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/1856916a0c14314d/1856916a0c14314d.xci new file mode 100644 index 00000000..9492d2a6 --- /dev/null +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/1856916a0c14314d/1856916a0c14314d.xci @@ -0,0 +1,206 @@ + + + xilinx.com + ipcache + 1856916a0c14314d + 0 + + + fifo_weight_cdc + + + 100000000 + 100000000 + 32 + 0 + 0 + false + false + false + 0 + 0 + Slave_Interface_Clock_Enable + Common_Clock + fifo_weight_cdc + 64 + false + 4 + false + false + 0 + 2 + 1022 + 1022 + 1022 + 1022 + 1022 + 1022 + 3 + false + false + false + false + false + false + false + false + false + Hard_ECC + false + false + false + false + false + false + true + false + false + true + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Independent_Clocks_Distributed_RAM + 1 + 13 + 1023 + 1023 + 1023 + 1023 + 1023 + 1023 + 12 + false + false + false + 0 + Native + false + false + false + false + false + false + false + false + false + false + false + false + false + false + 16 + 16 + 1024 + 16 + 1024 + 16 + 1024 + 16 + false + 16 + 16 + Embedded_Reg + false + false + Active_High + Active_High + AXI4 + Standard_FIFO + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + READ_WRITE + 0 + 1 + true + 4 + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + true + Asynchronous_Reset + false + 1 + 0 + 0 + 1 + 1 + 4 + false + false + Active_High + Active_High + true + false + false + false + false + Active_High + 0 + false + Active_High + 1 + false + 4 + false + FIFO + false + false + false + false + FIFO + FIFO + 2 + 2 + false + FIFO + FIFO + FIFO + kintex7 + xc7k410t + ffg900 + VERILOG + + -2 + + + TRUE + TRUE + 1856916a0c14314d + e223bb28 + 21 + IP_Unknown + 4 + TRUE + . + + . + 2019.1.3 + GLOBAL + + + + diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/1856916a0c14314d/fifo_weight_cdc.dcp b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/1856916a0c14314d/fifo_weight_cdc.dcp new file mode 100644 index 00000000..cd719806 --- /dev/null +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/1856916a0c14314d/fifo_weight_cdc.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:bef5871bc540df92af1e2fad32c3defa1e49f1d5031558e996d4b72ae4bc78dd +size 77083 diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/1856916a0c14314d/fifo_weight_cdc_sim_netlist.v b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/1856916a0c14314d/fifo_weight_cdc_sim_netlist.v new file mode 100755 index 00000000..7ddc5fd8 --- /dev/null +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/1856916a0c14314d/fifo_weight_cdc_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:b7960966fea11556213b05dd6662976420fbb4676918217ae62e2b152ec5a165 +size 117334 diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/1856916a0c14314d/fifo_weight_cdc_sim_netlist.vhdl b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/1856916a0c14314d/fifo_weight_cdc_sim_netlist.vhdl new file mode 100755 index 00000000..18490fd6 --- /dev/null +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/1856916a0c14314d/fifo_weight_cdc_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:19d79f2c3b19a96785bc71b9aa71dcd8e9e21d6286a0a1d1c66a1269167f55ed +size 188088 diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/1856916a0c14314d/fifo_weight_cdc_stub.v b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/1856916a0c14314d/fifo_weight_cdc_stub.v new file mode 100755 index 00000000..c4d59ca2 --- /dev/null +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/1856916a0c14314d/fifo_weight_cdc_stub.v @@ -0,0 +1,30 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Thu Jul 27 11:21:03 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fifo_weight_cdc_stub.v +// Design : fifo_weight_cdc +// Purpose : Stub declaration of top-level module interface +// Device : xc7k410tffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "fifo_generator_v13_2_4,Vivado 2019.1.3" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(rst, wr_clk, rd_clk, din, wr_en, rd_en, dout, full, + empty, rd_data_count) +/* synthesis syn_black_box black_box_pad_pin="rst,wr_clk,rd_clk,din[15:0],wr_en,rd_en,dout[15:0],full,empty,rd_data_count[3:0]" */; + input rst; + input wr_clk; + input rd_clk; + input [15:0]din; + input wr_en; + input rd_en; + output [15:0]dout; + output full; + output empty; + output [3:0]rd_data_count; +endmodule diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/1856916a0c14314d/fifo_weight_cdc_stub.vhdl b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/1856916a0c14314d/fifo_weight_cdc_stub.vhdl new file mode 100755 index 00000000..11130647 --- /dev/null +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/1856916a0c14314d/fifo_weight_cdc_stub.vhdl @@ -0,0 +1,39 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Thu Jul 27 11:21:03 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fifo_weight_cdc_stub.vhdl +-- Design : fifo_weight_cdc +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7k410tffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + Port ( + rst : in STD_LOGIC; + wr_clk : in STD_LOGIC; + rd_clk : in STD_LOGIC; + din : in STD_LOGIC_VECTOR ( 15 downto 0 ); + wr_en : in STD_LOGIC; + rd_en : in STD_LOGIC; + dout : out STD_LOGIC_VECTOR ( 15 downto 0 ); + full : out STD_LOGIC; + empty : out STD_LOGIC; + rd_data_count : out STD_LOGIC_VECTOR ( 3 downto 0 ) + ); + +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "rst,wr_clk,rd_clk,din[15:0],wr_en,rd_en,dout[15:0],full,empty,rd_data_count[3:0]"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "fifo_generator_v13_2_4,Vivado 2019.1.3"; +begin +end; diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/wt/gui_handlers.wdf b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/wt/gui_handlers.wdf index 37a243f2..0fb7ad63 100644 --- a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/wt/gui_handlers.wdf +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/wt/gui_handlers.wdf @@ -1,12 +1,12 @@ version:1 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f63616e63656c:3239:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:3637:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f63616e63656c:3330:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:3638:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636d646d73676469616c6f675f6f6b:33:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f7079697068616e646c65725f64657374696e6174696f6e5f69705f6e616d65:3132:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f7265747265657461626c6570616e656c5f636f72655f747265655f7461626c65:3135:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:65787072756e7472656570616e656c5f6578705f72756e5f747265655f7461626c65:3139:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:65787072756e7472656570616e656c5f6578705f72756e5f747265655f7461626c65:3230:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6670676163686f6f7365725f667067615f7461626c65:31:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:333333:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:333336:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6d616e6167655f6970:3131:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6f70656e5f70726f6a656374:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f73746172745f7573696e675f76697661646f5f776974685f69705f636174616c6f67:33:00:00 @@ -34,10 +34,10 @@ version:1 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:726469636f6d6d616e64735f64656c657465:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:72656d6f7665736f75726365736469616c6f675f616c736f5f64656c657465:38:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73696d706c656f757470757470726f647563746469616c6f675f636c6f73655f6469616c6f675f756e73617665645f6368616e6765735f77696c6c:36:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73696d706c656f757470757470726f647563746469616c6f675f67656e65726174655f6f75747075745f70726f64756374735f696d6d6564696174656c79:3231:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73696d706c656f757470757470726f647563746469616c6f675f67656e65726174655f6f75747075745f70726f64756374735f696d6d6564696174656c79:3232:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73696d706c656f757470757470726f647563746469616c6f675f72657365745f6f75747075745f70726f6475637473:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6164645f636f6e666967757261626c655f69705f66696c6573:3135:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6d616b655f6c6f63616c5f636f70795f6f665f74686573655f66696c65735f696e746f:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7372636d656e755f69705f646f63756d656e746174696f6e:3230:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73796e7468657469636167657474696e6773746172746564766965775f726563656e745f69705f6c6f636174696f6e73:36:00:00 -eof:2580322088 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73796e7468657469636167657474696e6773746172746564766965775f726563656e745f69705f6c6f636174696f6e73:37:00:00 +eof:496691848 diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/wt/java_command_handlers.wdf b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/wt/java_command_handlers.wdf index 186d8a6c..c2eef4fb 100644 --- a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/wt/java_command_handlers.wdf +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/wt/java_command_handlers.wdf @@ -7,8 +7,8 @@ version:1 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6d616e616765636f6d706f7369746574617267657473:35:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657769706c6f636174696f6e68616e646c6572:31:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e69706c6f636174696f6e68616e646c6572:3130:00:00 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e70726576696f7573697068616e646c6572:36:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e70726576696f7573697068616e646c6572:37:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e70726f6a656374:31:00:00 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7265637573746f6d697a65636f7265:3632:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7265637573746f6d697a65636f7265:3633:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73686f7776696577:31:00:00 -eof:4145888680 +eof:1592810089 diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/wt/project.wpc b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/wt/project.wpc index f16dd141..aaeed609 100644 --- a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/wt/project.wpc +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/wt/project.wpc @@ -1,3 +1,3 @@ version:1 -6d6f64655f636f756e7465727c4755494d6f6465:16 +6d6f64655f636f756e7465727c4755494d6f6465:17 eof: diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/wt/synthesis.wdf b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/wt/synthesis.wdf index fc53cd97..c1a61fc7 100644 --- a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/wt/synthesis.wdf +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/wt/synthesis.wdf @@ -1,7 +1,7 @@ version:1 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:7863376b343130746666673930302d32:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 -73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:6174616e325f313662:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:6669666f5f7765696768745f636463:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e636c7564655f64697273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67656e65726963:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d766572696c6f675f646566696e65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 @@ -33,7 +33,7 @@ version:1 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d617373657274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 -73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a313773:00:00 -73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:323039312e3437374d42:00:00 -73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3639302e3535394d42:00:00 -eof:3006227906 +73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a313473:00:00 +73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:323131382e3837354d42:00:00 +73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3731362e3935374d42:00:00 +eof:853881911 diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/wt/webtalk_pa.xml b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/wt/webtalk_pa.xml index de01c55c..f5cae69b 100644 --- a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/wt/webtalk_pa.xml +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/wt/webtalk_pa.xml @@ -3,7 +3,7 @@ - +
@@ -25,20 +25,20 @@ This means code written to parse this file will need to be revisited each subseq - + - + - - + + - + - + @@ -66,17 +66,17 @@ This means code written to parse this file will need to be revisited each subseq - + - + - + - +
diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_19.xml b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_19.xml new file mode 100644 index 00000000..e8e2f4b6 --- /dev/null +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_19.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/add_s24_s32_s32_synth_1/gen_run.xml b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/add_s24_s32_s32_synth_1/gen_run.xml index 6de8e637..3917d7e6 100644 --- a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/add_s24_s32_s32_synth_1/gen_run.xml +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/add_s24_s32_s32_synth_1/gen_run.xml @@ -1,7 +1,7 @@ - + diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/ant_clk_gen_stg1_synth_1/gen_run.xml b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/ant_clk_gen_stg1_synth_1/gen_run.xml index 1a66d805..bad8c589 100644 --- a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/ant_clk_gen_stg1_synth_1/gen_run.xml +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/ant_clk_gen_stg1_synth_1/gen_run.xml @@ -1,7 +1,7 @@ - + diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/ant_clk_gen_stg2_synth_1/gen_run.xml b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/ant_clk_gen_stg2_synth_1/gen_run.xml index 0269bb2d..b088159d 100644 --- a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/ant_clk_gen_stg2_synth_1/gen_run.xml +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/ant_clk_gen_stg2_synth_1/gen_run.xml @@ -1,7 +1,7 @@ - + diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/gen_run.xml b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/gen_run.xml index c5dcf6ff..107b8b4e 100644 --- a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/gen_run.xml +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/gen_run.xml @@ -1,14 +1,11 @@ - - + + + - - - - diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/cmpy_12x12_synth_1/gen_run.xml b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/cmpy_12x12_synth_1/gen_run.xml index e6d1c0e1..850ca9c2 100644 --- a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/cmpy_12x12_synth_1/gen_run.xml +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/cmpy_12x12_synth_1/gen_run.xml @@ -1,7 +1,7 @@ - + diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/cmpy_16x12_synth_1/gen_run.xml b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/cmpy_16x12_synth_1/gen_run.xml index d4e79901..e8a863ba 100644 --- a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/cmpy_16x12_synth_1/gen_run.xml +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/cmpy_16x12_synth_1/gen_run.xml @@ -1,7 +1,7 @@ - + diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/gen_run.xml b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/gen_run.xml index abef7aea..5e1352f0 100644 --- a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/gen_run.xml +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/gen_run.xml @@ -1,7 +1,7 @@ - + diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/.Vivado_Synthesis.queue.rst b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/.Vivado_Synthesis.queue.rst new file mode 100644 index 00000000..e69de29b diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/.vivado.begin.rst b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/.vivado.begin.rst new file mode 100644 index 00000000..7a83c02e --- /dev/null +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/.vivado.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/.vivado.end.rst b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/.vivado.end.rst new file mode 100644 index 00000000..e69de29b diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/ISEWrap.js b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/ISEWrap.js new file mode 100755 index 00000000..3e83de11 --- /dev/null +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/ISEWrap.js @@ -0,0 +1,270 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var wbemFlagReturnImmediately = 0x10; + var wbemFlagForwardOnly = 0x20; + var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); + var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); + var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); + var NOC = 0; + var NOLP = 0; + var TPM = 0; + + var cpuInfos = new Enumerator(processor); + for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { + var cpuInfo = cpuInfos.item(); + NOC += cpuInfo.NumberOfCores; + NOLP += cpuInfo.NumberOfLogicalProcessors; + } + var csInfos = new Enumerator(computerSystem); + for(;!csInfos.atEnd(); csInfos.moveNext()) { + var csInfo = csInfos.item(); + TPM += csInfo.TotalPhysicalMemory; + } + + var ISEHOSTCORE = NOLP + var ISEMEMTOTAL = TPM + + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/ISEWrap.sh b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/ISEWrap.sh new file mode 100755 index 00000000..f679f2e8 --- /dev/null +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/ISEWrap.sh @@ -0,0 +1,67 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. +# + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! +if [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi +ISE_USER=$USER + +ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) +ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) + +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/__synthesis_is_complete__ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/__synthesis_is_complete__ new file mode 100644 index 00000000..e69de29b diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/dont_touch.xdc b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/dont_touch.xdc new file mode 100644 index 00000000..d7f6d3b5 --- /dev/null +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/dont_touch.xdc @@ -0,0 +1,32 @@ +# This file is automatically generated. +# It contains project source information necessary for synthesis and implementation. + +# IP: /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/rx_pre_process/fifo_weight_cdc/fifo_weight_cdc.xci +# IP: The module: 'fifo_weight_cdc' is the root of the design. Do not add the DONT_TOUCH constraint. + +# XDC: /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/rx_pre_process/fifo_weight_cdc/fifo_weight_cdc.xdc +# XDC: The top module name and the constraint reference have the same name: 'fifo_weight_cdc'. Do not add the DONT_TOUCH constraint. +set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet + +# XDC: /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/rx_pre_process/fifo_weight_cdc/fifo_weight_cdc_clocks.xdc +# XDC: The top module name and the constraint reference have the same name: 'fifo_weight_cdc'. Do not add the DONT_TOUCH constraint. +#dup# set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet + +# XDC: /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/rx_pre_process/fifo_weight_cdc/fifo_weight_cdc_ooc.xdc +# XDC: The top module name and the constraint reference have the same name: 'fifo_weight_cdc'. Do not add the DONT_TOUCH constraint. +#dup# set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet + +# IP: /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/rx_pre_process/fifo_weight_cdc/fifo_weight_cdc.xci +# IP: The module: 'fifo_weight_cdc' is the root of the design. Do not add the DONT_TOUCH constraint. + +# XDC: /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/rx_pre_process/fifo_weight_cdc/fifo_weight_cdc.xdc +# XDC: The top module name and the constraint reference have the same name: 'fifo_weight_cdc'. Do not add the DONT_TOUCH constraint. +#dup# set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet + +# XDC: /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/rx_pre_process/fifo_weight_cdc/fifo_weight_cdc_clocks.xdc +# XDC: The top module name and the constraint reference have the same name: 'fifo_weight_cdc'. Do not add the DONT_TOUCH constraint. +#dup# set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet + +# XDC: /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/rx_pre_process/fifo_weight_cdc/fifo_weight_cdc_ooc.xdc +# XDC: The top module name and the constraint reference have the same name: 'fifo_weight_cdc'. Do not add the DONT_TOUCH constraint. +#dup# set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/fifo_weight_cdc.dcp b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/fifo_weight_cdc.dcp new file mode 100644 index 00000000..70514485 --- /dev/null +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/fifo_weight_cdc.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:064d19d290cd0a8295b1cd086091175f1be9829f355c02f1e8ce8fe00e30ddfb +size 77477 diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/fifo_weight_cdc.tcl b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/fifo_weight_cdc.tcl new file mode 100644 index 00000000..6e207985 --- /dev/null +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/fifo_weight_cdc.tcl @@ -0,0 +1,158 @@ +# +# Synthesis run script generated by Vivado +# + +set TIME_start [clock seconds] +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +set_param simulator.modelsimInstallPath /home/josh/Software/Mentor/modeltech/bin +set_param simulator.vcsmxInstallPath /home/josh/Software/Synopsys/vcs/T-2022.06/bin +set_param project.vivado.isBlockSynthRun true +set_msg_config -msgmgr_mode ooc_run +create_project -in_memory -part xc7k410tffg900-2 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info +set_property webtalk.parent_dir /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/wt [current_project] +set_property parent.project_path /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.xpr [current_project] +set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language Verilog [current_project] +set_property ip_output_repo /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +read_ip -quiet /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/rx_pre_process/fifo_weight_cdc/fifo_weight_cdc.xci +set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/rx_pre_process/fifo_weight_cdc/fifo_weight_cdc.xdc] +set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/rx_pre_process/fifo_weight_cdc/fifo_weight_cdc_clocks.xdc] +set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/rx_pre_process/fifo_weight_cdc/fifo_weight_cdc_ooc.xdc] + +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +read_xdc dont_touch.xdc +set_property used_in_implementation false [get_files dont_touch.xdc] +set_param ips.enableIPCacheLiteLoad 1 + +set cached_ip [config_ip_cache -export -no_bom -dir /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1 -new_name fifo_weight_cdc -ip [get_ips fifo_weight_cdc]] + +if { $cached_ip eq {} } { +close [open __synthesis_is_running__ w] + +synth_design -top fifo_weight_cdc -part xc7k410tffg900-2 -mode out_of_context + +#--------------------------------------------------------- +# Generate Checkpoint/Stub/Simulation Files For IP Cache +#--------------------------------------------------------- +# disable binary constraint mode for IPCache checkpoints +set_param constraints.enableBinaryConstraints false + +catch { + write_checkpoint -force -noxdef -rename_prefix fifo_weight_cdc_ fifo_weight_cdc.dcp + + set ipCachedFiles {} + write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fifo_weight_cdc_stub.v + lappend ipCachedFiles fifo_weight_cdc_stub.v + + write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fifo_weight_cdc_stub.vhdl + lappend ipCachedFiles fifo_weight_cdc_stub.vhdl + + write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fifo_weight_cdc_sim_netlist.v + lappend ipCachedFiles fifo_weight_cdc_sim_netlist.v + + write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fifo_weight_cdc_sim_netlist.vhdl + lappend ipCachedFiles fifo_weight_cdc_sim_netlist.vhdl +set TIME_taken [expr [clock seconds] - $TIME_start] + + config_ip_cache -add -dcp fifo_weight_cdc.dcp -move_files $ipCachedFiles -use_project_ipc -synth_runtime $TIME_taken -ip [get_ips fifo_weight_cdc] +} + +rename_ref -prefix_all fifo_weight_cdc_ + +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef fifo_weight_cdc.dcp +create_report "fifo_weight_cdc_synth_1_synth_report_utilization_0" "report_utilization -file fifo_weight_cdc_utilization_synth.rpt -pb fifo_weight_cdc_utilization_synth.pb" + +if { [catch { + write_verilog -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/fifo_weight_cdc_stub.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + write_vhdl -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/fifo_weight_cdc_stub.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + write_verilog -force -mode funcsim /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/fifo_weight_cdc_sim_netlist.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + +if { [catch { + write_vhdl -force -mode funcsim /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/fifo_weight_cdc_sim_netlist.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + + +} else { + + +}; # end if cached_ip + +add_files /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/fifo_weight_cdc_stub.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/rx_pre_process/fifo_weight_cdc/fifo_weight_cdc.xci] + +add_files /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/fifo_weight_cdc_stub.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/rx_pre_process/fifo_weight_cdc/fifo_weight_cdc.xci] + +add_files /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/fifo_weight_cdc_sim_netlist.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/rx_pre_process/fifo_weight_cdc/fifo_weight_cdc.xci] + +add_files /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/fifo_weight_cdc_sim_netlist.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/rx_pre_process/fifo_weight_cdc/fifo_weight_cdc.xci] + +add_files /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/fifo_weight_cdc.dcp -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/rx_pre_process/fifo_weight_cdc/fifo_weight_cdc.xci] + +if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/ip_user_files/ip/fifo_weight_cdc]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/fifo_weight_cdc_sim_netlist.v /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/ip_user_files/ip/fifo_weight_cdc + } +} + +if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/ip_user_files/ip/fifo_weight_cdc]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/fifo_weight_cdc_sim_netlist.vhdl /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/ip_user_files/ip/fifo_weight_cdc + } +} + +if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/ip_user_files/ip/fifo_weight_cdc]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/fifo_weight_cdc_stub.v /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/ip_user_files/ip/fifo_weight_cdc + } +} + +if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/ip_user_files/ip/fifo_weight_cdc]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/fifo_weight_cdc_stub.vhdl /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/ip_user_files/ip/fifo_weight_cdc + } +} +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/fifo_weight_cdc.vds b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/fifo_weight_cdc.vds new file mode 100644 index 00000000..083eb709 --- /dev/null +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/fifo_weight_cdc.vds @@ -0,0 +1,735 @@ +#----------------------------------------------------------- +# Vivado v2019.1.3 (64-bit) +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 +# Start of session at: Thu Jul 27 11:20:38 2023 +# Process ID: 226756 +# Current directory: /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1 +# Command line: vivado -log fifo_weight_cdc.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source fifo_weight_cdc.tcl +# Log file: /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/fifo_weight_cdc.vds +# Journal file: /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/vivado.jou +#----------------------------------------------------------- +source fifo_weight_cdc.tcl -notrace +Command: synth_design -top fifo_weight_cdc -part xc7k410tffg900-2 -mode out_of_context +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7k410t' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k410t' +INFO: [Device 21-403] Loading part xc7k410tffg900-2 +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 226880 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:06 . Memory (MB): peak = 1826.406 ; gain = 152.719 ; free physical = 2787 ; free virtual = 33122 +--------------------------------------------------------------------------------- +INFO: [Synth 8-638] synthesizing module 'fifo_weight_cdc' [/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/rx_pre_process/fifo_weight_cdc/synth/fifo_weight_cdc.vhd:74] + Parameter C_COMMON_CLOCK bound to: 0 - type: integer + Parameter C_SELECT_XPM bound to: 0 - type: integer + Parameter C_COUNT_TYPE bound to: 0 - type: integer + Parameter C_DATA_COUNT_WIDTH bound to: 4 - type: integer + Parameter C_DEFAULT_VALUE bound to: BlankString - type: string + Parameter C_DIN_WIDTH bound to: 16 - type: integer + Parameter C_DOUT_RST_VAL bound to: 0 - type: string + Parameter C_DOUT_WIDTH bound to: 16 - type: integer + Parameter C_ENABLE_RLOCS bound to: 0 - type: integer + Parameter C_FAMILY bound to: kintex7 - type: string + Parameter C_FULL_FLAGS_RST_VAL bound to: 1 - type: integer + Parameter C_HAS_ALMOST_EMPTY bound to: 0 - type: integer + Parameter C_HAS_ALMOST_FULL bound to: 0 - type: integer + Parameter C_HAS_BACKUP bound to: 0 - type: integer + Parameter C_HAS_DATA_COUNT bound to: 0 - type: integer + Parameter C_HAS_INT_CLK bound to: 0 - type: integer + Parameter C_HAS_MEMINIT_FILE bound to: 0 - type: integer + Parameter C_HAS_OVERFLOW bound to: 0 - type: integer + Parameter C_HAS_RD_DATA_COUNT bound to: 1 - type: integer + Parameter C_HAS_RD_RST bound to: 0 - type: integer + Parameter C_HAS_RST bound to: 1 - type: integer + Parameter C_HAS_SRST bound to: 0 - type: integer + Parameter C_HAS_UNDERFLOW bound to: 0 - type: integer + Parameter C_HAS_VALID bound to: 0 - type: integer + Parameter C_HAS_WR_ACK bound to: 0 - type: integer + Parameter C_HAS_WR_DATA_COUNT bound to: 0 - type: integer + Parameter C_HAS_WR_RST bound to: 0 - type: integer + Parameter C_IMPLEMENTATION_TYPE bound to: 2 - type: integer + Parameter C_INIT_WR_PNTR_VAL bound to: 0 - type: integer + Parameter C_MEMORY_TYPE bound to: 2 - type: integer + Parameter C_MIF_FILE_NAME bound to: BlankString - type: string + Parameter C_OPTIMIZATION_MODE bound to: 0 - type: integer + Parameter C_OVERFLOW_LOW bound to: 0 - type: integer + Parameter C_PRELOAD_LATENCY bound to: 1 - type: integer + Parameter C_PRELOAD_REGS bound to: 0 - type: integer + Parameter C_PRIM_FIFO_TYPE bound to: 512x36 - type: string + Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL bound to: 2 - type: integer + Parameter C_PROG_EMPTY_THRESH_NEGATE_VAL bound to: 3 - type: integer + Parameter C_PROG_EMPTY_TYPE bound to: 0 - type: integer + Parameter C_PROG_FULL_THRESH_ASSERT_VAL bound to: 13 - type: integer + Parameter C_PROG_FULL_THRESH_NEGATE_VAL bound to: 12 - type: integer + Parameter C_PROG_FULL_TYPE bound to: 0 - type: integer + Parameter C_RD_DATA_COUNT_WIDTH bound to: 4 - type: integer + Parameter C_RD_DEPTH bound to: 16 - type: integer + Parameter C_RD_FREQ bound to: 1 - type: integer + Parameter C_RD_PNTR_WIDTH bound to: 4 - type: integer + Parameter C_UNDERFLOW_LOW bound to: 0 - type: integer + Parameter C_USE_DOUT_RST bound to: 1 - type: integer + Parameter C_USE_ECC bound to: 0 - type: integer + Parameter C_USE_EMBEDDED_REG bound to: 0 - type: integer + Parameter C_USE_PIPELINE_REG bound to: 0 - type: integer + Parameter C_POWER_SAVING_MODE bound to: 0 - type: integer + Parameter C_USE_FIFO16_FLAGS bound to: 0 - type: integer + Parameter C_USE_FWFT_DATA_COUNT bound to: 0 - type: integer + Parameter C_VALID_LOW bound to: 0 - type: integer + Parameter C_WR_ACK_LOW bound to: 0 - type: integer + Parameter C_WR_DATA_COUNT_WIDTH bound to: 4 - type: integer + Parameter C_WR_DEPTH bound to: 16 - type: integer + Parameter C_WR_FREQ bound to: 1 - type: integer + Parameter C_WR_PNTR_WIDTH bound to: 4 - type: integer + Parameter C_WR_RESPONSE_LATENCY bound to: 1 - type: integer + Parameter C_MSGON_VAL bound to: 1 - type: integer + Parameter C_ENABLE_RST_SYNC bound to: 1 - type: integer + Parameter C_EN_SAFETY_CKT bound to: 0 - type: integer + Parameter C_ERROR_INJECTION_TYPE bound to: 0 - type: integer + Parameter C_SYNCHRONIZER_STAGE bound to: 2 - type: integer + Parameter C_INTERFACE_TYPE bound to: 0 - type: integer + Parameter C_AXI_TYPE bound to: 1 - type: integer + Parameter C_HAS_AXI_WR_CHANNEL bound to: 1 - type: integer + Parameter C_HAS_AXI_RD_CHANNEL bound to: 1 - type: integer + Parameter C_HAS_SLAVE_CE bound to: 0 - type: integer + Parameter C_HAS_MASTER_CE bound to: 0 - type: integer + Parameter C_ADD_NGC_CONSTRAINT bound to: 0 - type: integer + Parameter C_USE_COMMON_OVERFLOW bound to: 0 - type: integer + Parameter C_USE_COMMON_UNDERFLOW bound to: 0 - type: integer + Parameter C_USE_DEFAULT_SETTINGS bound to: 0 - type: integer + Parameter C_AXI_ID_WIDTH bound to: 1 - type: integer + Parameter C_AXI_ADDR_WIDTH bound to: 32 - type: integer + Parameter C_AXI_DATA_WIDTH bound to: 64 - type: integer + Parameter C_AXI_LEN_WIDTH bound to: 8 - type: integer + Parameter C_AXI_LOCK_WIDTH bound to: 1 - type: integer + Parameter C_HAS_AXI_ID bound to: 0 - type: integer + Parameter C_HAS_AXI_AWUSER bound to: 0 - type: integer + Parameter C_HAS_AXI_WUSER bound to: 0 - type: integer + Parameter C_HAS_AXI_BUSER bound to: 0 - type: integer + Parameter C_HAS_AXI_ARUSER bound to: 0 - type: integer + Parameter C_HAS_AXI_RUSER bound to: 0 - type: integer + Parameter C_AXI_ARUSER_WIDTH bound to: 1 - type: integer + Parameter C_AXI_AWUSER_WIDTH bound to: 1 - type: integer + Parameter C_AXI_WUSER_WIDTH bound to: 1 - type: integer + Parameter C_AXI_BUSER_WIDTH bound to: 1 - type: integer + Parameter C_AXI_RUSER_WIDTH bound to: 1 - type: integer + Parameter C_HAS_AXIS_TDATA bound to: 1 - type: integer + Parameter C_HAS_AXIS_TID bound to: 0 - type: integer + Parameter C_HAS_AXIS_TDEST bound to: 0 - type: integer + Parameter C_HAS_AXIS_TUSER bound to: 1 - type: integer + Parameter C_HAS_AXIS_TREADY bound to: 1 - type: integer + Parameter C_HAS_AXIS_TLAST bound to: 0 - type: integer + Parameter C_HAS_AXIS_TSTRB bound to: 0 - type: integer + Parameter C_HAS_AXIS_TKEEP bound to: 0 - type: integer + Parameter C_AXIS_TDATA_WIDTH bound to: 8 - type: integer + Parameter C_AXIS_TID_WIDTH bound to: 1 - type: integer + Parameter C_AXIS_TDEST_WIDTH bound to: 1 - type: integer + Parameter C_AXIS_TUSER_WIDTH bound to: 4 - type: integer + Parameter C_AXIS_TSTRB_WIDTH bound to: 1 - type: integer + Parameter C_AXIS_TKEEP_WIDTH bound to: 1 - type: integer + Parameter C_WACH_TYPE bound to: 0 - type: integer + Parameter C_WDCH_TYPE bound to: 0 - type: integer + Parameter C_WRCH_TYPE bound to: 0 - type: integer + Parameter C_RACH_TYPE bound to: 0 - type: integer + Parameter C_RDCH_TYPE bound to: 0 - type: integer + Parameter C_AXIS_TYPE bound to: 0 - type: integer + Parameter C_IMPLEMENTATION_TYPE_WACH bound to: 1 - type: integer + Parameter C_IMPLEMENTATION_TYPE_WDCH bound to: 1 - type: integer + Parameter C_IMPLEMENTATION_TYPE_WRCH bound to: 1 - type: integer + Parameter C_IMPLEMENTATION_TYPE_RACH bound to: 1 - type: integer + Parameter C_IMPLEMENTATION_TYPE_RDCH bound to: 1 - type: integer + Parameter C_IMPLEMENTATION_TYPE_AXIS bound to: 1 - type: integer + Parameter C_APPLICATION_TYPE_WACH bound to: 0 - type: integer + Parameter C_APPLICATION_TYPE_WDCH bound to: 0 - type: integer + Parameter C_APPLICATION_TYPE_WRCH bound to: 0 - type: integer + Parameter C_APPLICATION_TYPE_RACH bound to: 0 - type: integer + Parameter C_APPLICATION_TYPE_RDCH bound to: 0 - type: integer + Parameter C_APPLICATION_TYPE_AXIS bound to: 0 - type: integer + Parameter C_PRIM_FIFO_TYPE_WACH bound to: 512x36 - type: string + Parameter C_PRIM_FIFO_TYPE_WDCH bound to: 1kx36 - type: string + Parameter C_PRIM_FIFO_TYPE_WRCH bound to: 512x36 - type: string + Parameter C_PRIM_FIFO_TYPE_RACH bound to: 512x36 - type: string + Parameter C_PRIM_FIFO_TYPE_RDCH bound to: 1kx36 - type: string + Parameter C_PRIM_FIFO_TYPE_AXIS bound to: 1kx18 - type: string + Parameter C_USE_ECC_WACH bound to: 0 - type: integer + Parameter C_USE_ECC_WDCH bound to: 0 - type: integer + Parameter C_USE_ECC_WRCH bound to: 0 - type: integer + Parameter C_USE_ECC_RACH bound to: 0 - type: integer + Parameter C_USE_ECC_RDCH bound to: 0 - type: integer + Parameter C_USE_ECC_AXIS bound to: 0 - type: integer + Parameter C_ERROR_INJECTION_TYPE_WACH bound to: 0 - type: integer + Parameter C_ERROR_INJECTION_TYPE_WDCH bound to: 0 - type: integer + Parameter C_ERROR_INJECTION_TYPE_WRCH bound to: 0 - type: integer + Parameter C_ERROR_INJECTION_TYPE_RACH bound to: 0 - type: integer + Parameter C_ERROR_INJECTION_TYPE_RDCH bound to: 0 - type: integer + Parameter C_ERROR_INJECTION_TYPE_AXIS bound to: 0 - type: integer + Parameter C_DIN_WIDTH_WACH bound to: 1 - type: integer + Parameter C_DIN_WIDTH_WDCH bound to: 64 - type: integer + Parameter C_DIN_WIDTH_WRCH bound to: 2 - type: integer + Parameter C_DIN_WIDTH_RACH bound to: 32 - type: integer + Parameter C_DIN_WIDTH_RDCH bound to: 64 - type: integer + Parameter C_DIN_WIDTH_AXIS bound to: 1 - type: integer + Parameter C_WR_DEPTH_WACH bound to: 16 - type: integer + Parameter C_WR_DEPTH_WDCH bound to: 1024 - type: integer + Parameter C_WR_DEPTH_WRCH bound to: 16 - type: integer + Parameter C_WR_DEPTH_RACH bound to: 16 - type: integer + Parameter C_WR_DEPTH_RDCH bound to: 1024 - type: integer + Parameter C_WR_DEPTH_AXIS bound to: 1024 - type: integer + Parameter C_WR_PNTR_WIDTH_WACH bound to: 4 - type: integer + Parameter C_WR_PNTR_WIDTH_WDCH bound to: 10 - type: integer + Parameter C_WR_PNTR_WIDTH_WRCH bound to: 4 - type: integer + Parameter C_WR_PNTR_WIDTH_RACH bound to: 4 - type: integer + Parameter C_WR_PNTR_WIDTH_RDCH bound to: 10 - type: integer + Parameter C_WR_PNTR_WIDTH_AXIS bound to: 10 - type: integer + Parameter C_HAS_DATA_COUNTS_WACH bound to: 0 - type: integer + Parameter C_HAS_DATA_COUNTS_WDCH bound to: 0 - type: integer + Parameter C_HAS_DATA_COUNTS_WRCH bound to: 0 - type: integer + Parameter C_HAS_DATA_COUNTS_RACH bound to: 0 - type: integer + Parameter C_HAS_DATA_COUNTS_RDCH bound to: 0 - type: integer + Parameter C_HAS_DATA_COUNTS_AXIS bound to: 0 - type: integer + Parameter C_HAS_PROG_FLAGS_WACH bound to: 0 - type: integer + Parameter C_HAS_PROG_FLAGS_WDCH bound to: 0 - type: integer + Parameter C_HAS_PROG_FLAGS_WRCH bound to: 0 - type: integer + Parameter C_HAS_PROG_FLAGS_RACH bound to: 0 - type: integer + Parameter C_HAS_PROG_FLAGS_RDCH bound to: 0 - type: integer + Parameter C_HAS_PROG_FLAGS_AXIS bound to: 0 - type: integer + Parameter C_PROG_FULL_TYPE_WACH bound to: 0 - type: integer + Parameter C_PROG_FULL_TYPE_WDCH bound to: 0 - type: integer + Parameter C_PROG_FULL_TYPE_WRCH bound to: 0 - type: integer + Parameter C_PROG_FULL_TYPE_RACH bound to: 0 - type: integer + Parameter C_PROG_FULL_TYPE_RDCH bound to: 0 - type: integer + Parameter C_PROG_FULL_TYPE_AXIS bound to: 0 - type: integer + Parameter C_PROG_FULL_THRESH_ASSERT_VAL_WACH bound to: 1023 - type: integer + Parameter C_PROG_FULL_THRESH_ASSERT_VAL_WDCH bound to: 1023 - type: integer + Parameter C_PROG_FULL_THRESH_ASSERT_VAL_WRCH bound to: 1023 - type: integer + Parameter C_PROG_FULL_THRESH_ASSERT_VAL_RACH bound to: 1023 - type: integer + Parameter C_PROG_FULL_THRESH_ASSERT_VAL_RDCH bound to: 1023 - type: integer + Parameter C_PROG_FULL_THRESH_ASSERT_VAL_AXIS bound to: 1023 - type: integer + Parameter C_PROG_EMPTY_TYPE_WACH bound to: 0 - type: integer + Parameter C_PROG_EMPTY_TYPE_WDCH bound to: 0 - type: integer + Parameter C_PROG_EMPTY_TYPE_WRCH bound to: 0 - type: integer + Parameter C_PROG_EMPTY_TYPE_RACH bound to: 0 - type: integer + Parameter C_PROG_EMPTY_TYPE_RDCH bound to: 0 - type: integer + Parameter C_PROG_EMPTY_TYPE_AXIS bound to: 0 - type: integer + Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH bound to: 1022 - type: integer + Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH bound to: 1022 - type: integer + Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH bound to: 1022 - type: integer + Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH bound to: 1022 - type: integer + Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH bound to: 1022 - type: integer + Parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS bound to: 1022 - type: integer + Parameter C_REG_SLICE_MODE_WACH bound to: 0 - type: integer + Parameter C_REG_SLICE_MODE_WDCH bound to: 0 - type: integer + Parameter C_REG_SLICE_MODE_WRCH bound to: 0 - type: integer + Parameter C_REG_SLICE_MODE_RACH bound to: 0 - type: integer + Parameter C_REG_SLICE_MODE_RDCH bound to: 0 - type: integer + Parameter C_REG_SLICE_MODE_AXIS bound to: 0 - type: integer +INFO: [Synth 8-3491] module 'fifo_generator_v13_2_4' declared at '/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/rx_pre_process/fifo_weight_cdc/hdl/fifo_generator_v13_2_vhsyn_rfs.vhd:38586' bound to instance 'U0' of component 'fifo_generator_v13_2_4' [/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/rx_pre_process/fifo_weight_cdc/synth/fifo_weight_cdc.vhd:544] +INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_async_rst' [/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1175] +INFO: [Synth 8-5534] Detected attribute (* ASYNC_REG = "TRUE" *) [/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1226] +INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_async_rst' (1#1) [/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:1175] +INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_single' [/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:153] +INFO: [Synth 8-5534] Detected attribute (* ASYNC_REG = "TRUE" *) [/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:205] +INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_single' (2#1) [/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:153] +INFO: [Synth 8-6157] synthesizing module 'xpm_cdc_gray' [/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284] +INFO: [Synth 8-5534] Detected attribute (* ASYNC_REG = "TRUE" *) [/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:358] +INFO: [Synth 8-6155] done synthesizing module 'xpm_cdc_gray' (7#1) [/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:284] +INFO: [Synth 8-256] done synthesizing module 'fifo_weight_cdc' (22#1) [/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/rx_pre_process/fifo_weight_cdc/synth/fifo_weight_cdc.vhd:74] +WARNING: [Synth 8-3331] design wr_status_flags_as has unconnected port WR_RST +WARNING: [Synth 8-3331] design wr_status_flags_as has unconnected port SRST +WARNING: [Synth 8-3331] design wr_status_flags_as has unconnected port SAFETY_CKT_WR_RST +WARNING: [Synth 8-3331] design wr_status_flags_as has unconnected port WR_PNTR_PLUS3[3] +WARNING: [Synth 8-3331] design wr_status_flags_as has unconnected port WR_PNTR_PLUS3[2] +WARNING: [Synth 8-3331] design wr_status_flags_as has unconnected port WR_PNTR_PLUS3[1] +WARNING: [Synth 8-3331] design wr_status_flags_as has unconnected port WR_PNTR_PLUS3[0] +WARNING: [Synth 8-3331] design wr_bin_cntr has unconnected port SRST +WARNING: [Synth 8-3331] design wr_logic has unconnected port WR_EN_INTO_LOGIC +WARNING: [Synth 8-3331] design wr_logic has unconnected port WR_RST_INTO_LOGIC +WARNING: [Synth 8-3331] design wr_logic has unconnected port RD_EN +WARNING: [Synth 8-3331] design wr_logic has unconnected port SRST_FULL_FF +WARNING: [Synth 8-3331] design wr_logic has unconnected port WR_RST_BUSY +WARNING: [Synth 8-3331] design wr_logic has unconnected port EMPTY +WARNING: [Synth 8-3331] design wr_logic has unconnected port RAM_RD_EN +WARNING: [Synth 8-3331] design wr_logic has unconnected port ALMOST_EMPTY +WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH[3] +WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH[2] +WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH[1] +WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH[0] +WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH_ASSERT[3] +WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH_ASSERT[2] +WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH_ASSERT[1] +WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH_ASSERT[0] +WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH_NEGATE[3] +WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH_NEGATE[2] +WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH_NEGATE[1] +WARNING: [Synth 8-3331] design wr_logic has unconnected port PROG_FULL_THRESH_NEGATE[0] +WARNING: [Synth 8-3331] design rd_dc_as has unconnected port SRST +WARNING: [Synth 8-3331] design rd_status_flags_as has unconnected port SRST +WARNING: [Synth 8-3331] design rd_status_flags_as has unconnected port SAFETY_CKT_RD_RST +WARNING: [Synth 8-3331] design rd_status_flags_as has unconnected port RD_PNTR_PLUS2[3] +WARNING: [Synth 8-3331] design rd_status_flags_as has unconnected port RD_PNTR_PLUS2[2] +WARNING: [Synth 8-3331] design rd_status_flags_as has unconnected port RD_PNTR_PLUS2[1] +WARNING: [Synth 8-3331] design rd_status_flags_as has unconnected port RD_PNTR_PLUS2[0] +WARNING: [Synth 8-3331] design rd_bin_cntr has unconnected port SRST +WARNING: [Synth 8-3331] design rd_logic has unconnected port RD_EN_INTO_LOGIC +WARNING: [Synth 8-3331] design rd_logic has unconnected port RD_RST_INTO_LOGIC +WARNING: [Synth 8-3331] design rd_logic has unconnected port RD_RST_BUSY +WARNING: [Synth 8-3331] design rd_logic has unconnected port RAM_WR_EN +WARNING: [Synth 8-3331] design rd_logic has unconnected port RST_FULL_FF +WARNING: [Synth 8-3331] design rd_logic has unconnected port ALMOST_FULL_FB +WARNING: [Synth 8-3331] design rd_logic has unconnected port FULL +WARNING: [Synth 8-3331] design rd_logic has unconnected port WR_PNTR_PLUS1_RD[3] +WARNING: [Synth 8-3331] design rd_logic has unconnected port WR_PNTR_PLUS1_RD[2] +WARNING: [Synth 8-3331] design rd_logic has unconnected port WR_PNTR_PLUS1_RD[1] +WARNING: [Synth 8-3331] design rd_logic has unconnected port WR_PNTR_PLUS1_RD[0] +WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH[3] +WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH[2] +WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH[1] +WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH[0] +WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH_ASSERT[3] +WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH_ASSERT[2] +WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH_ASSERT[1] +WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH_ASSERT[0] +WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH_NEGATE[3] +WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH_NEGATE[2] +WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH_NEGATE[1] +WARNING: [Synth 8-3331] design rd_logic has unconnected port PROG_EMPTY_THRESH_NEGATE[0] +WARNING: [Synth 8-3331] design clk_x_pntrs has unconnected port WR_RST +WARNING: [Synth 8-3331] design clk_x_pntrs has unconnected port RD_RST +WARNING: [Synth 8-3331] design dmem has unconnected port SRST +WARNING: [Synth 8-3331] design memory has unconnected port RAM_REGOUT_EN +WARNING: [Synth 8-3331] design memory has unconnected port FAB_REGOUT_EN +WARNING: [Synth 8-3331] design memory has unconnected port SFT_RST +WARNING: [Synth 8-3331] design memory has unconnected port SRST +WARNING: [Synth 8-3331] design memory has unconnected port SAFETY_CKT_RD_RST +WARNING: [Synth 8-3331] design memory has unconnected port SLEEP +WARNING: [Synth 8-3331] design memory has unconnected port INJECTDBITERR +WARNING: [Synth 8-3331] design memory has unconnected port INJECTSBITERR +WARNING: [Synth 8-3331] design output_blk has unconnected port ALMOST_FULL_I +WARNING: [Synth 8-3331] design output_blk has unconnected port PROG_FULL_I +WARNING: [Synth 8-3331] design output_blk has unconnected port ALMOST_EMPTY_I +WARNING: [Synth 8-3331] design output_blk has unconnected port PROG_EMPTY_I +WARNING: [Synth 8-3331] design output_blk has unconnected port WR_ACK_I +WARNING: [Synth 8-3331] design output_blk has unconnected port VALID_I +WARNING: [Synth 8-3331] design output_blk has unconnected port OVERFLOW_I +WARNING: [Synth 8-3331] design output_blk has unconnected port UNDERFLOW_I +WARNING: [Synth 8-3331] design output_blk has unconnected port DATA_COUNT_I[4] +WARNING: [Synth 8-3331] design output_blk has unconnected port DATA_COUNT_I[3] +WARNING: [Synth 8-3331] design output_blk has unconnected port DATA_COUNT_I[2] +WARNING: [Synth 8-3331] design output_blk has unconnected port DATA_COUNT_I[1] +WARNING: [Synth 8-3331] design output_blk has unconnected port DATA_COUNT_I[0] +WARNING: [Synth 8-3331] design output_blk has unconnected port WR_DATA_COUNT_I[4] +WARNING: [Synth 8-3331] design output_blk has unconnected port WR_DATA_COUNT_I[3] +WARNING: [Synth 8-3331] design output_blk has unconnected port WR_DATA_COUNT_I[2] +WARNING: [Synth 8-3331] design output_blk has unconnected port WR_DATA_COUNT_I[1] +WARNING: [Synth 8-3331] design output_blk has unconnected port WR_DATA_COUNT_I[0] +WARNING: [Synth 8-3331] design output_blk has unconnected port RD_DATA_COUNT_I[0] +WARNING: [Synth 8-3331] design output_blk has unconnected port SBITERR_I +WARNING: [Synth 8-3331] design output_blk has unconnected port DBITERR_I +WARNING: [Synth 8-3331] design input_blk has unconnected port CLK +WARNING: [Synth 8-3331] design input_blk has unconnected port INT_CLK +WARNING: [Synth 8-3331] design input_blk has unconnected port PROG_EMPTY_THRESH[3] +WARNING: [Synth 8-3331] design input_blk has unconnected port PROG_EMPTY_THRESH[2] +WARNING: [Synth 8-3331] design input_blk has unconnected port PROG_EMPTY_THRESH[1] +WARNING: [Synth 8-3331] design input_blk has unconnected port PROG_EMPTY_THRESH[0] +WARNING: [Synth 8-3331] design input_blk has unconnected port PROG_EMPTY_THRESH_ASSERT[3] +WARNING: [Synth 8-3331] design input_blk has unconnected port PROG_EMPTY_THRESH_ASSERT[2] +WARNING: [Synth 8-3331] design input_blk has unconnected port PROG_EMPTY_THRESH_ASSERT[1] +INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:11 . Memory (MB): peak = 1973.125 ; gain = 299.438 ; free physical = 2696 ; free virtual = 33032 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:06 ; elapsed = 00:00:12 . Memory (MB): peak = 1976.094 ; gain = 302.406 ; free physical = 2698 ; free virtual = 33033 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:12 . Memory (MB): peak = 1976.094 ; gain = 302.406 ; free physical = 2698 ; free virtual = 33033 +--------------------------------------------------------------------------------- +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/rx_pre_process/fifo_weight_cdc/fifo_weight_cdc_ooc.xdc] for cell 'U0' +Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/rx_pre_process/fifo_weight_cdc/fifo_weight_cdc_ooc.xdc] for cell 'U0' +Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/rx_pre_process/fifo_weight_cdc/fifo_weight_cdc.xdc] for cell 'U0' +Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/rx_pre_process/fifo_weight_cdc/fifo_weight_cdc.xdc] for cell 'U0' +Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/dont_touch.xdc] +Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/dont_touch.xdc] +Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/rx_pre_process/fifo_weight_cdc/fifo_weight_cdc_clocks.xdc] for cell 'U0' +Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/rx_pre_process/fifo_weight_cdc/fifo_weight_cdc_clocks.xdc] for cell 'U0' +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/rx_pre_process/fifo_weight_cdc/fifo_weight_cdc_clocks.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/fifo_weight_cdc_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/fifo_weight_cdc_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +Sourcing Tcl File [/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' +Finished Sourcing Tcl File [/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst' +Sourcing Tcl File [/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' +Finished Sourcing Tcl File [/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl] for cell 'U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst' +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_async_rst.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/fifo_weight_cdc_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/fifo_weight_cdc_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +Sourcing Tcl File [/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' +Finished Sourcing Tcl File [/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst' +Sourcing Tcl File [/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' +Finished Sourcing Tcl File [/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst' +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/fifo_weight_cdc_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/fifo_weight_cdc_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +Sourcing Tcl File [/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' +Finished Sourcing Tcl File [/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr' +Sourcing Tcl File [/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' +Finished Sourcing Tcl File [/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'U0/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd' +INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/fifo_weight_cdc_propImpl.xdc]. +Resolution: To avoid this warning, move constraints listed in [.Xil/fifo_weight_cdc_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2118.875 ; gain = 0.000 ; free physical = 2615 ; free virtual = 32951 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2118.875 ; gain = 0.000 ; free physical = 2616 ; free virtual = 32951 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 2118.875 ; gain = 445.188 ; free physical = 2682 ; free virtual = 33017 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7k410tffg900-2 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 2118.875 ; gain = 445.188 ; free physical = 2682 ; free virtual = 33017 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +Applied set_property DONT_TOUCH = true for U0. (constraint file /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/dont_touch.xdc, line 9). +Applied set_property DONT_TOUCH = true for U0/inst_fifo_gen/\gconvfifo.rf /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst . (constraint file auto generated constraint, line ). +Applied set_property DONT_TOUCH = true for U0/inst_fifo_gen/\gconvfifo.rf /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst . (constraint file auto generated constraint, line ). +Applied set_property DONT_TOUCH = true for U0/inst_fifo_gen/\gconvfifo.rf /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /rd_pntr_cdc_inst. (constraint file auto generated constraint, line ). +Applied set_property DONT_TOUCH = true for U0/inst_fifo_gen/\gconvfifo.rf /\grf.rf /\gntv_or_sync_fifo.gcx.clkx /wr_pntr_cdc_inst. (constraint file auto generated constraint, line ). +Applied set_property DONT_TOUCH = true for U0/inst_fifo_gen/\gconvfifo.rf /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr . (constraint file auto generated constraint, line ). +Applied set_property DONT_TOUCH = true for U0/inst_fifo_gen/\gconvfifo.rf /\grf.rf /rstblk/\ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd . (constraint file auto generated constraint, line ). +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:09 ; elapsed = 00:00:14 . Memory (MB): peak = 2118.875 ; gain = 445.188 ; free physical = 2682 ; free virtual = 33017 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 2118.875 ; gain = 445.188 ; free physical = 2678 ; free virtual = 33014 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 2 + 3 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 4 Bit XORs := 2 + 2 Input 1 Bit XORs := 22 ++---Registers : + 16 Bit Registers := 1 + 4 Bit Registers := 17 + 2 Bit Registers := 3 + 1 Bit Registers := 10 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +Module xpm_cdc_async_rst +Detailed RTL Component Info : ++---Registers : + 2 Bit Registers := 1 +Module xpm_cdc_single +Detailed RTL Component Info : ++---Registers : + 4 Bit Registers := 1 +Module reset_blk_ramfifo +Detailed RTL Component Info : ++---Registers : + 4 Bit Registers := 1 + 2 Bit Registers := 1 + 1 Bit Registers := 6 +Module dmem +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xpm_cdc_gray +Detailed RTL Component Info : ++---XORs : + 2 Input 4 Bit XORs := 1 + 2 Input 1 Bit XORs := 3 ++---Registers : + 4 Bit Registers := 4 +Module rd_bin_cntr +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---Registers : + 4 Bit Registers := 2 +Module compare +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 4 +Module rd_status_flags_as +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 2 +Module rd_dc_as +Detailed RTL Component Info : ++---Adders : + 3 Input 4 Bit Adders := 1 ++---Registers : + 4 Bit Registers := 1 +Module wr_bin_cntr +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---Registers : + 4 Bit Registers := 3 +Module wr_status_flags_as +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 2 +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 1540 (col length:140) +BRAMs: 1590 (col length: RAMB18 140 RAMB36 70) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:09 ; elapsed = 00:00:15 . Memory (MB): peak = 2118.875 ; gain = 445.188 ; free physical = 2661 ; free virtual = 32999 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP and Shift Register Reporting +--------------------------------------------------------------------------------- + +Distributed RAM: Preliminary Mapping Report (see note below) ++------------+-------------------------------------------------------------------------------+----------------+----------------------+--------------+ +|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | ++------------+-------------------------------------------------------------------------------+----------------+----------------------+--------------+ +|U0 | inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 16 | RAM32M x 3 | ++------------+-------------------------------------------------------------------------------+----------------+----------------------+--------------+ + +Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once. +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP and Shift Register Reporting +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:11 ; elapsed = 00:00:17 . Memory (MB): peak = 2118.875 ; gain = 445.188 ; free physical = 2586 ; free virtual = 32923 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:11 ; elapsed = 00:00:17 . Memory (MB): peak = 2118.875 ; gain = 445.188 ; free physical = 2581 ; free virtual = 32917 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP and Shift Register Reporting +--------------------------------------------------------------------------------- + +Distributed RAM: Final Mapping Report ++------------+-------------------------------------------------------------------------------+----------------+----------------------+--------------+ +|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | ++------------+-------------------------------------------------------------------------------+----------------+----------------------+--------------+ +|U0 | inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg | User Attribute | 16 x 16 | RAM32M x 3 | ++------------+-------------------------------------------------------------------------------+----------------+----------------------+--------------+ + +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP and Shift Register Reporting +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:11 ; elapsed = 00:00:17 . Memory (MB): peak = 2118.875 ; gain = 445.188 ; free physical = 2581 ; free virtual = 32917 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:12 ; elapsed = 00:00:18 . Memory (MB): peak = 2118.875 ; gain = 445.188 ; free physical = 2581 ; free virtual = 32918 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:12 ; elapsed = 00:00:18 . Memory (MB): peak = 2118.875 ; gain = 445.188 ; free physical = 2581 ; free virtual = 32918 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:12 ; elapsed = 00:00:18 . Memory (MB): peak = 2118.875 ; gain = 445.188 ; free physical = 2581 ; free virtual = 32918 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:12 ; elapsed = 00:00:18 . Memory (MB): peak = 2118.875 ; gain = 445.188 ; free physical = 2581 ; free virtual = 32918 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:12 ; elapsed = 00:00:18 . Memory (MB): peak = 2118.875 ; gain = 445.188 ; free physical = 2581 ; free virtual = 32918 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:12 ; elapsed = 00:00:18 . Memory (MB): peak = 2118.875 ; gain = 445.188 ; free physical = 2581 ; free virtual = 32918 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+-------+------+ +| |Cell |Count | ++------+-------+------+ +|1 |LUT1 | 2| +|2 |LUT2 | 15| +|3 |LUT3 | 5| +|4 |LUT4 | 11| +|5 |LUT5 | 2| +|6 |LUT6 | 5| +|7 |RAM32M | 3| +|8 |FDCE | 43| +|9 |FDPE | 17| +|10 |FDRE | 40| ++------+-------+------+ + +Report Instance Areas: ++------+-------------------------------------------------------------------------------------+-----------------------------+------+ +| |Instance |Module |Cells | ++------+-------------------------------------------------------------------------------------+-----------------------------+------+ +|1 |top | | 143| +|2 | U0 |fifo_generator_v13_2_4 | 143| +|3 | inst_fifo_gen |fifo_generator_v13_2_4_synth | 143| +|4 | \gconvfifo.rf |fifo_generator_top | 143| +|5 | \grf.rf |fifo_generator_ramfifo | 143| +|6 | \gntv_or_sync_fifo.gcx.clkx |clk_x_pntrs | 48| +|7 | wr_pntr_cdc_inst |xpm_cdc_gray__2 | 22| +|8 | rd_pntr_cdc_inst |xpm_cdc_gray | 22| +|9 | \gntv_or_sync_fifo.gl0.rd |rd_logic | 26| +|10 | \gras.grdc1.rdc |rd_dc_as | 4| +|11 | \gras.rsts |rd_status_flags_as | 3| +|12 | rpntr |rd_bin_cntr | 19| +|13 | \gntv_or_sync_fifo.gl0.wr |wr_logic | 22| +|14 | \gwas.wsts |wr_status_flags_as | 4| +|15 | wpntr |wr_bin_cntr | 18| +|16 | \gntv_or_sync_fifo.mem |memory | 19| +|17 | \gdm.dm_gen.dm |dmem | 19| +|18 | rstblk |reset_blk_ramfifo | 28| +|19 | \ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst |xpm_cdc_async_rst__2 | 2| +|20 | \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.rst_rd_reg2_inst |xpm_cdc_async_rst | 2| +|21 | \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_wrst_rd |xpm_cdc_single__2 | 4| +|22 | \ngwrdrst.grst.g7serrst.gnsckt_wrst.gic_rst.xpm_cdc_single_inst_rrst_wr |xpm_cdc_single | 4| ++------+-------------------------------------------------------------------------------------+-----------------------------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:12 ; elapsed = 00:00:18 . Memory (MB): peak = 2118.875 ; gain = 445.188 ; free physical = 2581 ; free virtual = 32918 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 439 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:11 ; elapsed = 00:00:16 . Memory (MB): peak = 2118.875 ; gain = 302.406 ; free physical = 2635 ; free virtual = 32972 +Synthesis Optimization Complete : Time (s): cpu = 00:00:12 ; elapsed = 00:00:18 . Memory (MB): peak = 2118.875 ; gain = 445.188 ; free physical = 2635 ; free virtual = 32972 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Netlist 29-17] Analyzing 3 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2118.875 ; gain = 0.000 ; free physical = 2587 ; free virtual = 32923 +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 3 instances were transformed. + RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 3 instances + +INFO: [Common 17-83] Releasing license: Synthesis +28 Infos, 100 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:20 . Memory (MB): peak = 2118.875 ; gain = 722.895 ; free physical = 2679 ; free virtual = 33016 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2118.875 ; gain = 0.000 ; free physical = 2679 ; free virtual = 33016 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/fifo_weight_cdc.dcp' has been generated. +WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. +INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP fifo_weight_cdc, cache-ID = 1856916a0c14314d +INFO: [Coretcl 2-1174] Renamed 21 cell refs. +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2142.887 ; gain = 0.000 ; free physical = 2668 ; free virtual = 33005 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/fifo_weight_cdc.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file fifo_weight_cdc_utilization_synth.rpt -pb fifo_weight_cdc_utilization_synth.pb +INFO: [Common 17-206] Exiting Vivado at Thu Jul 27 11:21:03 2023... diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/fifo_weight_cdc_sim_netlist.v b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/fifo_weight_cdc_sim_netlist.v new file mode 100644 index 00000000..8bd2576f --- /dev/null +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/fifo_weight_cdc_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:b7e861eb8dae0f9cf48694f53354b61efe7da4098a68c956af72d1769d09ca00 +size 116956 diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/fifo_weight_cdc_sim_netlist.vhdl b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/fifo_weight_cdc_sim_netlist.vhdl new file mode 100644 index 00000000..8e0e1848 --- /dev/null +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/fifo_weight_cdc_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:2136d4696ef8b7d782f4cfc7cc5870c10ad5309f79517600772d820b1f931237 +size 181436 diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/fifo_weight_cdc_stub.v b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/fifo_weight_cdc_stub.v new file mode 100644 index 00000000..0bd41308 --- /dev/null +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/fifo_weight_cdc_stub.v @@ -0,0 +1,30 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Thu Jul 27 11:21:03 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub +// /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/fifo_weight_cdc_stub.v +// Design : fifo_weight_cdc +// Purpose : Stub declaration of top-level module interface +// Device : xc7k410tffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "fifo_generator_v13_2_4,Vivado 2019.1.3" *) +module fifo_weight_cdc(rst, wr_clk, rd_clk, din, wr_en, rd_en, dout, full, + empty, rd_data_count) +/* synthesis syn_black_box black_box_pad_pin="rst,wr_clk,rd_clk,din[15:0],wr_en,rd_en,dout[15:0],full,empty,rd_data_count[3:0]" */; + input rst; + input wr_clk; + input rd_clk; + input [15:0]din; + input wr_en; + input rd_en; + output [15:0]dout; + output full; + output empty; + output [3:0]rd_data_count; +endmodule diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/fifo_weight_cdc_stub.vhdl b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/fifo_weight_cdc_stub.vhdl new file mode 100644 index 00000000..d131c4c0 --- /dev/null +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/fifo_weight_cdc_stub.vhdl @@ -0,0 +1,39 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Thu Jul 27 11:21:03 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/fifo_weight_cdc_stub.vhdl +-- Design : fifo_weight_cdc +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7k410tffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity fifo_weight_cdc is + Port ( + rst : in STD_LOGIC; + wr_clk : in STD_LOGIC; + rd_clk : in STD_LOGIC; + din : in STD_LOGIC_VECTOR ( 15 downto 0 ); + wr_en : in STD_LOGIC; + rd_en : in STD_LOGIC; + dout : out STD_LOGIC_VECTOR ( 15 downto 0 ); + full : out STD_LOGIC; + empty : out STD_LOGIC; + rd_data_count : out STD_LOGIC_VECTOR ( 3 downto 0 ) + ); + +end fifo_weight_cdc; + +architecture stub of fifo_weight_cdc is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "rst,wr_clk,rd_clk,din[15:0],wr_en,rd_en,dout[15:0],full,empty,rd_data_count[3:0]"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "fifo_generator_v13_2_4,Vivado 2019.1.3"; +begin +end; diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/fifo_weight_cdc_utilization_synth.pb b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/fifo_weight_cdc_utilization_synth.pb new file mode 100644 index 00000000..506e6017 Binary files /dev/null and b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/fifo_weight_cdc_utilization_synth.pb differ diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/fifo_weight_cdc_utilization_synth.rpt b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/fifo_weight_cdc_utilization_synth.rpt new file mode 100644 index 00000000..59c69555 --- /dev/null +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/fifo_weight_cdc_utilization_synth.rpt @@ -0,0 +1,185 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +| Date : Thu Jul 27 11:21:03 2023 +| Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +| Command : report_utilization -file fifo_weight_cdc_utilization_synth.rpt -pb fifo_weight_cdc_utilization_synth.pb +| Design : fifo_weight_cdc +| Device : 7k410tffg900-2 +| Design State : Synthesized +------------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------------------+------+-------+-----------+-------+ +| Slice LUTs* | 46 | 0 | 254200 | 0.02 | +| LUT as Logic | 34 | 0 | 254200 | 0.01 | +| LUT as Memory | 12 | 0 | 90600 | 0.01 | +| LUT as Distributed RAM | 12 | 0 | | | +| LUT as Shift Register | 0 | 0 | | | +| Slice Registers | 100 | 0 | 508400 | 0.02 | +| Register as Flip Flop | 100 | 0 | 508400 | 0.02 | +| Register as Latch | 0 | 0 | 508400 | 0.00 | +| F7 Muxes | 0 | 0 | 127100 | 0.00 | +| F8 Muxes | 0 | 0 | 63550 | 0.00 | ++----------------------------+------+-------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 17 | Yes | - | Set | +| 43 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 40 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 795 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 795 | 0.00 | +| RAMB18 | 0 | 0 | 1590 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 1540 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 0 | 0 | 500 | 0.00 | +| Bonded IPADs | 0 | 0 | 50 | 0.00 | +| Bonded OPADs | 0 | 0 | 32 | 0.00 | +| PHY_CONTROL | 0 | 0 | 10 | 0.00 | +| PHASER_REF | 0 | 0 | 10 | 0.00 | +| OUT_FIFO | 0 | 0 | 40 | 0.00 | +| IN_FIFO | 0 | 0 | 40 | 0.00 | +| IDELAYCTRL | 0 | 0 | 10 | 0.00 | +| IBUFDS | 0 | 0 | 480 | 0.00 | +| GTXE2_COMMON | 0 | 0 | 4 | 0.00 | +| GTXE2_CHANNEL | 0 | 0 | 16 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 40 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 40 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 500 | 0.00 | +| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 | +| IBUFDS_GTE2 | 0 | 0 | 8 | 0.00 | +| ILOGIC | 0 | 0 | 500 | 0.00 | +| OLOGIC | 0 | 0 | 500 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 0 | 0 | 32 | 0.00 | +| BUFIO | 0 | 0 | 40 | 0.00 | +| MMCME2_ADV | 0 | 0 | 10 | 0.00 | +| PLLE2_ADV | 0 | 0 | 10 | 0.00 | +| BUFMRCE | 0 | 0 | 20 | 0.00 | +| BUFHCE | 0 | 0 | 168 | 0.00 | +| BUFR | 0 | 0 | 40 | 0.00 | ++------------+------+-------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +7. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| FDCE | 43 | Flop & Latch | +| FDRE | 40 | Flop & Latch | +| RAMD32 | 18 | Distributed Memory | +| FDPE | 17 | Flop & Latch | +| LUT2 | 15 | LUT | +| LUT4 | 11 | LUT | +| RAMS32 | 6 | Distributed Memory | +| LUT6 | 5 | LUT | +| LUT3 | 5 | LUT | +| LUT5 | 2 | LUT | +| LUT1 | 2 | LUT | ++----------+------+---------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/gen_run.xml b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/gen_run.xml new file mode 100644 index 00000000..9924030c --- /dev/null +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/gen_run.xml @@ -0,0 +1,64 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/htr.txt b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/htr.txt new file mode 100644 index 00000000..b2335e28 --- /dev/null +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/htr.txt @@ -0,0 +1,9 @@ +# +# Vivado(TM) +# htr.txt: a Vivado-generated description of how-to-repeat the +# the basic steps of a run. Note that runme.bat/sh needs +# to be invoked for Vivado to track run status. +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# + +vivado -log fifo_weight_cdc.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source fifo_weight_cdc.tcl diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/project.wdf b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/project.wdf new file mode 100644 index 00000000..999af200 --- /dev/null +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/project.wdf @@ -0,0 +1,63 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:3238:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 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a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/rundef.js b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/rundef.js new file mode 100644 index 00000000..664dc816 --- /dev/null +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/rundef.js @@ -0,0 +1,40 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// + +echo "This script was generated under a different operating system." +echo "Please update the PATH variable below, before executing this script" +exit + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "/home/josh/Software/Xilinx/SDK/2019.1/bin:/home/josh/Software/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/home/josh/Software/Xilinx/Vivado/2019.1/bin;"; +} else { + PathVal = "/home/josh/Software/Xilinx/SDK/2019.1/bin:/home/josh/Software/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/home/josh/Software/Xilinx/Vivado/2019.1/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +ISEStep( "vivado", + "-log fifo_weight_cdc.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source fifo_weight_cdc.tcl" ); + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/runme.bat b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/runme.bat new file mode 100644 index 00000000..ba55218d --- /dev/null +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/runme.bat @@ -0,0 +1,11 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +set PATH=%SYSTEMROOT%\system32;%PATH% +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/runme.sh b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/runme.sh new file mode 100755 index 00000000..9c06cb52 --- /dev/null +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/runme.sh @@ -0,0 +1,39 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# + +if [ -z "$PATH" ]; then + PATH=/home/josh/Software/Xilinx/SDK/2019.1/bin:/home/josh/Software/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/home/josh/Software/Xilinx/Vivado/2019.1/bin +else + PATH=/home/josh/Software/Xilinx/SDK/2019.1/bin:/home/josh/Software/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/home/josh/Software/Xilinx/Vivado/2019.1/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +EAStep vivado -log fifo_weight_cdc.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source fifo_weight_cdc.tcl diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/vivado.pb b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/vivado.pb new file mode 100644 index 00000000..427d5d46 Binary files /dev/null and b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_weight_cdc_synth_1/vivado.pb differ diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/ila_2x12x1024_synth_1/gen_run.xml b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/ila_2x12x1024_synth_1/gen_run.xml index dfa0ae10..dc43793a 100644 --- a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/ila_2x12x1024_synth_1/gen_run.xml +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/ila_2x12x1024_synth_1/gen_run.xml @@ -1,7 +1,7 @@ - + diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/ila_8x12_2x30_131072_synth_1/gen_run.xml b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/ila_8x12_2x30_131072_synth_1/gen_run.xml index 6943ab02..06fd15ee 100644 --- a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/ila_8x12_2x30_131072_synth_1/gen_run.xml +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/ila_8x12_2x30_131072_synth_1/gen_run.xml @@ -1,7 +1,7 @@ - + diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/ila_8x12_2x30_8192_synth_1/gen_run.xml b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/ila_8x12_2x30_8192_synth_1/gen_run.xml index b81e9054..a328d9be 100644 --- a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/ila_8x12_2x30_8192_synth_1/gen_run.xml +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/ila_8x12_2x30_8192_synth_1/gen_run.xml @@ -1,7 +1,7 @@ - + diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/ila_8x12_8192_synth_1/gen_run.xml b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/ila_8x12_8192_synth_1/gen_run.xml index 54556369..e087e8f5 100644 --- a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/ila_8x12_8192_synth_1/gen_run.xml +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/ila_8x12_8192_synth_1/gen_run.xml @@ -1,7 +1,7 @@ - + diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/ram_hop_data_synth_1/gen_run.xml b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/ram_hop_data_synth_1/gen_run.xml index 949cfac7..47ab99f8 100644 --- a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/ram_hop_data_synth_1/gen_run.xml +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/ram_hop_data_synth_1/gen_run.xml @@ -1,7 +1,7 @@ - + diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/gen_run.xml b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/gen_run.xml index 21118384..4dbd4fc7 100644 --- a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/gen_run.xml +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/gen_run.xml @@ -1,14 +1,11 @@ - - + + + - - - - diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/vio_ant_rd_synth_1/gen_run.xml b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/vio_ant_rd_synth_1/gen_run.xml index 21f1f99b..fecb9acc 100644 --- a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/vio_ant_rd_synth_1/gen_run.xml +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/vio_ant_rd_synth_1/gen_run.xml @@ -1,7 +1,7 @@ - + diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/vio_ant_test_synth_1/gen_run.xml b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/vio_ant_test_synth_1/gen_run.xml index 1139622c..5fffc742 100644 --- a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/vio_ant_test_synth_1/gen_run.xml +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/vio_ant_test_synth_1/gen_run.xml @@ -1,7 +1,7 @@ - + diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/vio_rf_rd_synth_1/gen_run.xml b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/vio_rf_rd_synth_1/gen_run.xml index 15e03312..0ad9ede3 100644 --- a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/vio_rf_rd_synth_1/gen_run.xml +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/vio_rf_rd_synth_1/gen_run.xml @@ -1,7 +1,7 @@ - + diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/gen_run.xml b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/gen_run.xml index b6c1cc72..8eccd470 100644 --- a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/gen_run.xml +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/gen_run.xml @@ -1,7 +1,7 @@ - + diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.xpr b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.xpr index ed4573c0..cfe93753 100644 --- a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.xpr +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.xpr @@ -39,13 +39,13 @@ - - - - - - - - - - - - - - @@ -637,6 +623,26 @@ + + + + + + + + + + + + + + + + + + @@ -824,6 +830,17 @@ + + + + Vivado Synthesis Defaults + + + + + + + @@ -1112,6 +1129,24 @@ + + + + Default settings for Implementation. + + + + + + + + + + + + + + diff --git a/projects/dl814_k7/common_ip/rx_pre_process/fifo_weight_cdc.xcix b/projects/dl814_k7/common_ip/rx_pre_process/fifo_weight_cdc.xcix index 371bbb20..1b79b8b9 100644 --- a/projects/dl814_k7/common_ip/rx_pre_process/fifo_weight_cdc.xcix +++ b/projects/dl814_k7/common_ip/rx_pre_process/fifo_weight_cdc.xcix @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:4f11a0a2a600f96ff6a3ff6e5932873385fe6c6202fc993049eaa1fa16dad7f5 -size 15315654 +oid sha256:e873d724b94c6fdebea8c28c632a43863588e4d210528c33642d65e14d87db67 +size 15311103 diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_phase_comp/sim/vio_phase_comp.v b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_phase_comp/sim/vio_phase_comp.v index 83468daf..51949397 100644 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_phase_comp/sim/vio_phase_comp.v +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_phase_comp/sim/vio_phase_comp.v @@ -48,7 +48,7 @@ `timescale 1ns / 1ps module vio_phase_comp ( clk, -probe_in0,probe_in1, +probe_in0,probe_in1,probe_in2,probe_in3,probe_in4,probe_in5, probe_out0, probe_out1, probe_out2, @@ -56,21 +56,27 @@ probe_out3, probe_out4, probe_out5, probe_out6, -probe_out7 +probe_out7, +probe_out8 ); input clk; -input [31 : 0] probe_in0; -input [0 : 0] probe_in1; +input [0 : 0] probe_in0; +input [31 : 0] probe_in1; +input [31 : 0] probe_in2; +input [31 : 0] probe_in3; +input [31 : 0] probe_in4; +input [31 : 0] probe_in5; -output reg [0 : 0] probe_out0 = 'h0 ; -output reg [0 : 0] probe_out1 = 'h0 ; -output reg [0 : 0] probe_out2 = 'h1 ; -output reg [0 : 0] probe_out3 = 'h0 ; -output reg [15 : 0] probe_out4 = 'h0000 ; -output reg [15 : 0] probe_out5 = 'h0000 ; -output reg [15 : 0] probe_out6 = 'h0000 ; -output reg [15 : 0] probe_out7 = 'h0000 ; +output reg [15 : 0] probe_out0 = 'h0000 ; +output reg [15 : 0] probe_out1 = 'h0000 ; +output reg [15 : 0] probe_out2 = 'h0000 ; +output reg [15 : 0] probe_out3 = 'h0000 ; +output reg [0 : 0] probe_out4 = 'h0 ; +output reg [0 : 0] probe_out5 = 'h1 ; +output reg [0 : 0] probe_out6 = 'h0 ; +output reg [0 : 0] probe_out7 = 'h0 ; +output reg [0 : 0] probe_out8 = 'h0 ; endmodule diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_phase_comp/vio_phase_comp.veo b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_phase_comp/vio_phase_comp.veo index befd1a65..789bfdcb 100644 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_phase_comp/vio_phase_comp.veo +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_phase_comp/vio_phase_comp.veo @@ -56,16 +56,21 @@ //----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG vio_phase_comp your_instance_name ( .clk(clk), // input wire clk - .probe_in0(probe_in0), // input wire [31 : 0] probe_in0 - .probe_in1(probe_in1), // input wire [0 : 0] probe_in1 - .probe_out0(probe_out0), // output wire [0 : 0] probe_out0 - .probe_out1(probe_out1), // output wire [0 : 0] probe_out1 - .probe_out2(probe_out2), // output wire [0 : 0] probe_out2 - .probe_out3(probe_out3), // output wire [0 : 0] probe_out3 - .probe_out4(probe_out4), // output wire [15 : 0] probe_out4 - .probe_out5(probe_out5), // output wire [15 : 0] probe_out5 - .probe_out6(probe_out6), // output wire [15 : 0] probe_out6 - .probe_out7(probe_out7) // output wire [15 : 0] probe_out7 + .probe_in0(probe_in0), // input wire [0 : 0] probe_in0 + .probe_in1(probe_in1), // input wire [31 : 0] probe_in1 + .probe_in2(probe_in2), // input wire [31 : 0] probe_in2 + .probe_in3(probe_in3), // input wire [31 : 0] probe_in3 + .probe_in4(probe_in4), // input wire [31 : 0] probe_in4 + .probe_in5(probe_in5), // input wire [31 : 0] probe_in5 + .probe_out0(probe_out0), // output wire [15 : 0] probe_out0 + .probe_out1(probe_out1), // output wire [15 : 0] probe_out1 + .probe_out2(probe_out2), // output wire [15 : 0] probe_out2 + .probe_out3(probe_out3), // output wire [15 : 0] probe_out3 + .probe_out4(probe_out4), // output wire [0 : 0] probe_out4 + .probe_out5(probe_out5), // output wire [0 : 0] probe_out5 + .probe_out6(probe_out6), // output wire [0 : 0] probe_out6 + .probe_out7(probe_out7), // output wire [0 : 0] probe_out7 + .probe_out8(probe_out8) // output wire [0 : 0] probe_out8 ); // INST_TAG_END ------ End INSTANTIATION Template --------- diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_phase_comp/vio_phase_comp.vho b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_phase_comp/vio_phase_comp.vho index 5bbf64ad..978aacdb 100644 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_phase_comp/vio_phase_comp.vho +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_phase_comp/vio_phase_comp.vho @@ -55,16 +55,21 @@ COMPONENT vio_phase_comp PORT ( clk : IN STD_LOGIC; - probe_in0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - probe_in1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); - probe_out0 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); - probe_out1 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); - probe_out2 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); - probe_out3 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); - probe_out4 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); - probe_out5 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); - probe_out6 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); - probe_out7 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) + probe_in0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + probe_in1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + probe_in2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + probe_in3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + probe_in4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + probe_in5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + probe_out0 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + probe_out1 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + probe_out2 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + probe_out3 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + probe_out4 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + probe_out5 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + probe_out6 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + probe_out7 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + probe_out8 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) ); END COMPONENT; -- COMP_TAG_END ------ End COMPONENT Declaration ------------ @@ -78,6 +83,10 @@ your_instance_name : vio_phase_comp clk => clk, probe_in0 => probe_in0, probe_in1 => probe_in1, + probe_in2 => probe_in2, + probe_in3 => probe_in3, + probe_in4 => probe_in4, + probe_in5 => probe_in5, probe_out0 => probe_out0, probe_out1 => probe_out1, probe_out2 => probe_out2, @@ -85,7 +94,8 @@ your_instance_name : vio_phase_comp probe_out4 => probe_out4, probe_out5 => probe_out5, probe_out6 => probe_out6, - probe_out7 => probe_out7 + probe_out7 => probe_out7, + probe_out8 => probe_out8 ); -- INST_TAG_END ------ End INSTANTIATION Template --------- diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_phase_comp/vio_phase_comp_sim_netlist.v b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_phase_comp/vio_phase_comp_sim_netlist.v index ab5fcf5a..ca7cf69b 100644 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_phase_comp/vio_phase_comp_sim_netlist.v +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_phase_comp/vio_phase_comp_sim_netlist.v @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:c54161de531f62c9b95a7d5c71ab9df4313489ff5f13778d75d6765db5339e9c -size 425691 +oid sha256:342e53512cd5a0261c780f4413b9b4d7b4d6ec714358837dfb8b900919ec4908 +size 677448 diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_phase_comp/vio_phase_comp_sim_netlist.vhdl b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_phase_comp/vio_phase_comp_sim_netlist.vhdl index efa6cc2d..969f0c15 100644 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_phase_comp/vio_phase_comp_sim_netlist.vhdl +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_phase_comp/vio_phase_comp_sim_netlist.vhdl @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:06d97b70737529844e27698b1b03e7a08b33b9958b620aa283bd7a6be042800f -size 736925 +oid sha256:5fc6d35a6908ab3c6d9d9c766167802ccbc0e94cf45fcbe327eb98379f236aad +size 1095960 diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_phase_comp/vio_phase_comp_stub.v b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_phase_comp/vio_phase_comp_stub.v index 2a0bcfb0..9e83bd15 100644 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_phase_comp/vio_phase_comp_stub.v +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_phase_comp/vio_phase_comp_stub.v @@ -1,7 +1,7 @@ // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 -// Date : Thu Jun 15 10:54:16 2023 +// Date : Thu Jul 27 10:38:10 2023 // Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS // Command : write_verilog -force -mode synth_stub // /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_stub.v @@ -14,18 +14,24 @@ // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. // Please paste the declaration into a Verilog source file or add the file as an additional source. (* X_CORE_INFO = "vio,Vivado 2019.1.3" *) -module vio_phase_comp(clk, probe_in0, probe_in1, probe_out0, - probe_out1, probe_out2, probe_out3, probe_out4, probe_out5, probe_out6, probe_out7) -/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[31:0],probe_in1[0:0],probe_out0[0:0],probe_out1[0:0],probe_out2[0:0],probe_out3[0:0],probe_out4[15:0],probe_out5[15:0],probe_out6[15:0],probe_out7[15:0]" */; +module vio_phase_comp(clk, probe_in0, probe_in1, probe_in2, probe_in3, + probe_in4, probe_in5, probe_out0, probe_out1, probe_out2, probe_out3, probe_out4, probe_out5, + probe_out6, probe_out7, probe_out8) +/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[0:0],probe_in1[31:0],probe_in2[31:0],probe_in3[31:0],probe_in4[31:0],probe_in5[31:0],probe_out0[15:0],probe_out1[15:0],probe_out2[15:0],probe_out3[15:0],probe_out4[0:0],probe_out5[0:0],probe_out6[0:0],probe_out7[0:0],probe_out8[0:0]" */; input clk; - input [31:0]probe_in0; - input [0:0]probe_in1; - output [0:0]probe_out0; - output [0:0]probe_out1; - output [0:0]probe_out2; - output [0:0]probe_out3; - output [15:0]probe_out4; - output [15:0]probe_out5; - output [15:0]probe_out6; - output [15:0]probe_out7; + input [0:0]probe_in0; + input [31:0]probe_in1; + input [31:0]probe_in2; + input [31:0]probe_in3; + input [31:0]probe_in4; + input [31:0]probe_in5; + output [15:0]probe_out0; + output [15:0]probe_out1; + output [15:0]probe_out2; + output [15:0]probe_out3; + output [0:0]probe_out4; + output [0:0]probe_out5; + output [0:0]probe_out6; + output [0:0]probe_out7; + output [0:0]probe_out8; endmodule diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_phase_comp/vio_phase_comp_stub.vhdl b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_phase_comp/vio_phase_comp_stub.vhdl index 60751ac0..5781802a 100644 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_phase_comp/vio_phase_comp_stub.vhdl +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_phase_comp/vio_phase_comp_stub.vhdl @@ -1,7 +1,7 @@ -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 --- Date : Thu Jun 15 10:54:16 2023 +-- Date : Thu Jul 27 10:38:10 2023 -- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS -- Command : write_vhdl -force -mode synth_stub -- /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_stub.vhdl @@ -15,16 +15,21 @@ use IEEE.STD_LOGIC_1164.ALL; entity vio_phase_comp is Port ( clk : in STD_LOGIC; - probe_in0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); - probe_in1 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out2 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out3 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out4 : out STD_LOGIC_VECTOR ( 15 downto 0 ); - probe_out5 : out STD_LOGIC_VECTOR ( 15 downto 0 ); - probe_out6 : out STD_LOGIC_VECTOR ( 15 downto 0 ); - probe_out7 : out STD_LOGIC_VECTOR ( 15 downto 0 ) + probe_in0 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + probe_in2 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + probe_in3 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + probe_in4 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + probe_in5 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + probe_out0 : out STD_LOGIC_VECTOR ( 15 downto 0 ); + probe_out1 : out STD_LOGIC_VECTOR ( 15 downto 0 ); + probe_out2 : out STD_LOGIC_VECTOR ( 15 downto 0 ); + probe_out3 : out STD_LOGIC_VECTOR ( 15 downto 0 ); + probe_out4 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out5 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out6 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out7 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out8 : out STD_LOGIC_VECTOR ( 0 to 0 ) ); end vio_phase_comp; @@ -33,7 +38,7 @@ architecture stub of vio_phase_comp is attribute syn_black_box : boolean; attribute black_box_pad_pin : string; attribute syn_black_box of stub : architecture is true; -attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[31:0],probe_in1[0:0],probe_out0[0:0],probe_out1[0:0],probe_out2[0:0],probe_out3[0:0],probe_out4[15:0],probe_out5[15:0],probe_out6[15:0],probe_out7[15:0]"; +attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[0:0],probe_in1[31:0],probe_in2[31:0],probe_in3[31:0],probe_in4[31:0],probe_in5[31:0],probe_out0[15:0],probe_out1[15:0],probe_out2[15:0],probe_out3[15:0],probe_out4[0:0],probe_out5[0:0],probe_out6[0:0],probe_out7[0:0],probe_out8[0:0]"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3"; begin diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/activehdl/README.txt b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/activehdl/README.txt index 703b82e1..0c350518 100644 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/activehdl/README.txt +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/activehdl/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Thu Jun 15 10:53:59 CST 2023 +# Generated by export_simulation on Thu Jul 27 10:37:51 CST 2023 # ################################################################################ diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/activehdl/vio_phase_comp.sh b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/activehdl/vio_phase_comp.sh index d223ae8f..71da3efd 100755 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/activehdl/vio_phase_comp.sh +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/activehdl/vio_phase_comp.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Thu Jun 15 10:53:59 CST 2023 +# Generated by Vivado on Thu Jul 27 10:37:51 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/ies/README.txt b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/ies/README.txt index f116af74..30ff3daf 100644 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/ies/README.txt +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/ies/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Thu Jun 15 10:53:59 CST 2023 +# Generated by export_simulation on Thu Jul 27 10:37:51 CST 2023 # ################################################################################ diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/ies/vio_phase_comp.sh b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/ies/vio_phase_comp.sh index d74cfbde..9fff442e 100755 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/ies/vio_phase_comp.sh +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/ies/vio_phase_comp.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Thu Jun 15 10:53:59 CST 2023 +# Generated by Vivado on Thu Jul 27 10:37:51 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/modelsim/README.txt b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/modelsim/README.txt index 703b82e1..0c350518 100644 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/modelsim/README.txt +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/modelsim/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Thu Jun 15 10:53:59 CST 2023 +# Generated by export_simulation on Thu Jul 27 10:37:51 CST 2023 # ################################################################################ diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/modelsim/vio_phase_comp.sh b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/modelsim/vio_phase_comp.sh index f2e6683c..e35e72ea 100755 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/modelsim/vio_phase_comp.sh +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/modelsim/vio_phase_comp.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Thu Jun 15 10:53:59 CST 2023 +# Generated by Vivado on Thu Jul 27 10:37:51 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/questa/README.txt b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/questa/README.txt index 703b82e1..0c350518 100644 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/questa/README.txt +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/questa/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Thu Jun 15 10:53:59 CST 2023 +# Generated by export_simulation on Thu Jul 27 10:37:51 CST 2023 # ################################################################################ diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/questa/vio_phase_comp.sh b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/questa/vio_phase_comp.sh index 6738f0b4..de3c086e 100755 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/questa/vio_phase_comp.sh +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/questa/vio_phase_comp.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Thu Jun 15 10:53:59 CST 2023 +# Generated by Vivado on Thu Jul 27 10:37:51 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/riviera/README.txt b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/riviera/README.txt index 703b82e1..0c350518 100644 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/riviera/README.txt +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/riviera/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Thu Jun 15 10:53:59 CST 2023 +# Generated by export_simulation on Thu Jul 27 10:37:51 CST 2023 # ################################################################################ diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/riviera/vio_phase_comp.sh b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/riviera/vio_phase_comp.sh index 7fdd6f28..7dd560d1 100755 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/riviera/vio_phase_comp.sh +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/riviera/vio_phase_comp.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Thu Jun 15 10:53:59 CST 2023 +# Generated by Vivado on Thu Jul 27 10:37:51 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/vcs/README.txt b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/vcs/README.txt index 703b82e1..0c350518 100644 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/vcs/README.txt +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/vcs/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Thu Jun 15 10:53:59 CST 2023 +# Generated by export_simulation on Thu Jul 27 10:37:51 CST 2023 # ################################################################################ diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/vcs/vio_phase_comp.sh b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/vcs/vio_phase_comp.sh index 482c03df..7e1930c2 100755 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/vcs/vio_phase_comp.sh +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/vcs/vio_phase_comp.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Thu Jun 15 10:53:59 CST 2023 +# Generated by Vivado on Thu Jul 27 10:37:51 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/xcelium/README.txt b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/xcelium/README.txt index f116af74..30ff3daf 100644 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/xcelium/README.txt +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/xcelium/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Thu Jun 15 10:53:59 CST 2023 +# Generated by export_simulation on Thu Jul 27 10:37:51 CST 2023 # ################################################################################ diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/xcelium/vio_phase_comp.sh b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/xcelium/vio_phase_comp.sh index 23c979de..f7674689 100755 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/xcelium/vio_phase_comp.sh +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/xcelium/vio_phase_comp.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Thu Jun 15 10:53:59 CST 2023 +# Generated by Vivado on Thu Jul 27 10:37:51 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/xsim/README.txt b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/xsim/README.txt index 703b82e1..0c350518 100644 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/xsim/README.txt +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/xsim/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Thu Jun 15 10:53:59 CST 2023 +# Generated by export_simulation on Thu Jul 27 10:37:51 CST 2023 # ################################################################################ diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/xsim/vio_phase_comp.sh b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/xsim/vio_phase_comp.sh index b7d777ef..0a142db4 100755 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/xsim/vio_phase_comp.sh +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/xsim/vio_phase_comp.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Thu Jun 15 10:53:59 CST 2023 +# Generated by Vivado on Thu Jul 27 10:37:51 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/115dfcf85af89900/115dfcf85af89900.xci b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/115dfcf85af89900/115dfcf85af89900.xci new file mode 100644 index 00000000..54cffd6a --- /dev/null +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/115dfcf85af89900/115dfcf85af89900.xci @@ -0,0 +1,810 @@ + + + xilinx.com + ipcache + 115dfcf85af89900 + 0 + + + vio_phase_comp + + + 100000000 + 1 + 1 + 6 + 9 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 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1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x000 + 12 + vio_phase_comp + kintex7 + xc7k410t + ffg900 + VERILOG + + -2 + + + TRUE + TRUE + 115dfcf85af89900 + 9a10a187 + 15 + IP_Unknown + 20 + TRUE + . + + . + 2019.1.3 + GLOBAL + + + + diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/115dfcf85af89900/vio_phase_comp.dcp b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/115dfcf85af89900/vio_phase_comp.dcp new file mode 100644 index 00000000..af656c74 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/115dfcf85af89900/vio_phase_comp.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:b027ad7e05dffb615603d6a668a6e4cc080853c79614bb3f232d29d7e8078f18 +size 293260 diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/115dfcf85af89900/vio_phase_comp_sim_netlist.v b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/115dfcf85af89900/vio_phase_comp_sim_netlist.v new file mode 100755 index 00000000..2c1d71ff --- /dev/null +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/115dfcf85af89900/vio_phase_comp_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:e40e9b8b77aae92a38b59778e1c3aeab9297c94fd17ea00f55d7fae814551525 +size 677975 diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/115dfcf85af89900/vio_phase_comp_sim_netlist.vhdl b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/115dfcf85af89900/vio_phase_comp_sim_netlist.vhdl new file mode 100755 index 00000000..2d467c72 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/115dfcf85af89900/vio_phase_comp_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:66498415559c78b33d4b88845afdb98c359b79e6f3318c3b84289a9f3386a66b +size 1132938 diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/115dfcf85af89900/vio_phase_comp_stub.v b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/115dfcf85af89900/vio_phase_comp_stub.v new file mode 100755 index 00000000..35b68b86 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/115dfcf85af89900/vio_phase_comp_stub.v @@ -0,0 +1,37 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Thu Jul 27 10:38:09 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_phase_comp_stub.v +// Design : vio_phase_comp +// Purpose : Stub declaration of top-level module interface +// Device : xc7k410tffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "vio,Vivado 2019.1.3" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe_in0, probe_in1, probe_in2, probe_in3, + probe_in4, probe_in5, probe_out0, probe_out1, probe_out2, probe_out3, probe_out4, probe_out5, + probe_out6, probe_out7, probe_out8) +/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[0:0],probe_in1[31:0],probe_in2[31:0],probe_in3[31:0],probe_in4[31:0],probe_in5[31:0],probe_out0[15:0],probe_out1[15:0],probe_out2[15:0],probe_out3[15:0],probe_out4[0:0],probe_out5[0:0],probe_out6[0:0],probe_out7[0:0],probe_out8[0:0]" */; + input clk; + input [0:0]probe_in0; + input [31:0]probe_in1; + input [31:0]probe_in2; + input [31:0]probe_in3; + input [31:0]probe_in4; + input [31:0]probe_in5; + output [15:0]probe_out0; + output [15:0]probe_out1; + output [15:0]probe_out2; + output [15:0]probe_out3; + output [0:0]probe_out4; + output [0:0]probe_out5; + output [0:0]probe_out6; + output [0:0]probe_out7; + output [0:0]probe_out8; +endmodule diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/115dfcf85af89900/vio_phase_comp_stub.vhdl b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/115dfcf85af89900/vio_phase_comp_stub.vhdl new file mode 100755 index 00000000..ded7dc25 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/115dfcf85af89900/vio_phase_comp_stub.vhdl @@ -0,0 +1,45 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Thu Jul 27 10:38:09 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_phase_comp_stub.vhdl +-- Design : vio_phase_comp +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7k410tffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + Port ( + clk : in STD_LOGIC; + probe_in0 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + probe_in2 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + probe_in3 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + probe_in4 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + probe_in5 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + probe_out0 : out STD_LOGIC_VECTOR ( 15 downto 0 ); + probe_out1 : out STD_LOGIC_VECTOR ( 15 downto 0 ); + probe_out2 : out STD_LOGIC_VECTOR ( 15 downto 0 ); + probe_out3 : out STD_LOGIC_VECTOR ( 15 downto 0 ); + probe_out4 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out5 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out6 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out7 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out8 : out STD_LOGIC_VECTOR ( 0 to 0 ) + ); + +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[0:0],probe_in1[31:0],probe_in2[31:0],probe_in3[31:0],probe_in4[31:0],probe_in5[31:0],probe_out0[15:0],probe_out1[15:0],probe_out2[15:0],probe_out3[15:0],probe_out4[0:0],probe_out5[0:0],probe_out6[0:0],probe_out7[0:0],probe_out8[0:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3"; +begin +end; diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/17d0bba61bd53938/17d0bba61bd53938.xci b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/17d0bba61bd53938/17d0bba61bd53938.xci new file mode 100644 index 00000000..bde2b8fd --- /dev/null +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/17d0bba61bd53938/17d0bba61bd53938.xci @@ -0,0 +1,810 @@ + + + xilinx.com + ipcache + 17d0bba61bd53938 + 0 + + + vio_phase_comp + + + 100000000 + 1 + 1 + 6 + 8 + 1 + 1 + 1 + 1 + 1 + 1 + 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+ 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x1 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 000000000000 + 12 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x000 + 12 + vio_phase_comp + kintex7 + xc7k410t + ffg900 + VERILOG + + -2 + + + TRUE + TRUE + 17d0bba61bd53938 + 9a10a187 + 15 + IP_Unknown + 20 + TRUE + . + + . + 2019.1.3 + GLOBAL + + + + diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/17d0bba61bd53938/vio_phase_comp.dcp b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/17d0bba61bd53938/vio_phase_comp.dcp new file mode 100644 index 00000000..0d6da3a1 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/17d0bba61bd53938/vio_phase_comp.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:499bb825da7cf04af33672d0174c33ee1a2545586771ec5c1baaaa8306d88a9f +size 289893 diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/17d0bba61bd53938/vio_phase_comp_sim_netlist.v b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/17d0bba61bd53938/vio_phase_comp_sim_netlist.v new file mode 100755 index 00000000..62a27839 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/17d0bba61bd53938/vio_phase_comp_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:2f2400033e04e185ab92ae43bb81ec436d087155fa57510268740f6328f9c8bf +size 668988 diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/17d0bba61bd53938/vio_phase_comp_sim_netlist.vhdl b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/17d0bba61bd53938/vio_phase_comp_sim_netlist.vhdl new file mode 100755 index 00000000..30d1dd2f --- /dev/null +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/17d0bba61bd53938/vio_phase_comp_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:63ba29cf60a6ad552a06a12c93166196860501dc9107f8bb7c012265455a1ece +size 1123841 diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/17d0bba61bd53938/vio_phase_comp_stub.v b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/17d0bba61bd53938/vio_phase_comp_stub.v new file mode 100755 index 00000000..7fc02e7c --- /dev/null +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/17d0bba61bd53938/vio_phase_comp_stub.v @@ -0,0 +1,36 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Thu Jul 27 10:36:54 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_phase_comp_stub.v +// Design : vio_phase_comp +// Purpose : Stub declaration of top-level module interface +// Device : xc7k410tffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "vio,Vivado 2019.1.3" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe_in0, probe_in1, probe_in2, probe_in3, + probe_in4, probe_in5, probe_out0, probe_out1, probe_out2, probe_out3, probe_out4, probe_out5, + probe_out6, probe_out7) +/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[0:0],probe_in1[31:0],probe_in2[31:0],probe_in3[31:0],probe_in4[31:0],probe_in5[31:0],probe_out0[15:0],probe_out1[15:0],probe_out2[15:0],probe_out3[15:0],probe_out4[0:0],probe_out5[0:0],probe_out6[0:0],probe_out7[0:0]" */; + input clk; + input [0:0]probe_in0; + input [31:0]probe_in1; + input [31:0]probe_in2; + input [31:0]probe_in3; + input [31:0]probe_in4; + input [31:0]probe_in5; + output [15:0]probe_out0; + output [15:0]probe_out1; + output [15:0]probe_out2; + output [15:0]probe_out3; + output [0:0]probe_out4; + output [0:0]probe_out5; + output [0:0]probe_out6; + output [0:0]probe_out7; +endmodule diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/17d0bba61bd53938/vio_phase_comp_stub.vhdl b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/17d0bba61bd53938/vio_phase_comp_stub.vhdl new file mode 100755 index 00000000..13295ca3 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/17d0bba61bd53938/vio_phase_comp_stub.vhdl @@ -0,0 +1,44 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Thu Jul 27 10:36:54 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_phase_comp_stub.vhdl +-- Design : vio_phase_comp +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7k410tffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + Port ( + clk : in STD_LOGIC; + probe_in0 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + probe_in2 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + probe_in3 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + probe_in4 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + probe_in5 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + probe_out0 : out STD_LOGIC_VECTOR ( 15 downto 0 ); + probe_out1 : out STD_LOGIC_VECTOR ( 15 downto 0 ); + probe_out2 : out STD_LOGIC_VECTOR ( 15 downto 0 ); + probe_out3 : out STD_LOGIC_VECTOR ( 15 downto 0 ); + probe_out4 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out5 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out6 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out7 : out STD_LOGIC_VECTOR ( 0 to 0 ) + ); + +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[0:0],probe_in1[31:0],probe_in2[31:0],probe_in3[31:0],probe_in4[31:0],probe_in5[31:0],probe_out0[15:0],probe_out1[15:0],probe_out2[15:0],probe_out3[15:0],probe_out4[0:0],probe_out5[0:0],probe_out6[0:0],probe_out7[0:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3"; +begin +end; diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/gui_handlers.wdf b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/gui_handlers.wdf index d50d0e71..6886d158 100644 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/gui_handlers.wdf +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/gui_handlers.wdf @@ -1,29 +1,29 @@ version:1 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f63616e63656c:3137:00:00 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+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73796e7468657469636167657474696e6773746172746564766965775f726563656e745f69705f6c6f636174696f6e73:3132:00:00 +eof:3503364654 diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/java_command_handlers.wdf b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/java_command_handlers.wdf index 9b6b7ccb..aa9df4a7 100644 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/java_command_handlers.wdf +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/java_command_handlers.wdf @@ -1,12 +1,12 @@ version:1 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6164646578697374696e67697068616e646c6572:35:00:00 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:636c6f736570726f6a656374:39:00:00 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b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/project.wpc @@ -1,3 +1,3 @@ version:1 -6d6f64655f636f756e7465727c4755494d6f6465:18 +6d6f64655f636f756e7465727c4755494d6f6465:19 eof: diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/synthesis.wdf b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/synthesis.wdf index 6de04bd4..0ec34306 100644 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/synthesis.wdf +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/synthesis.wdf @@ -33,7 +33,7 @@ version:1 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d617373657274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 -73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a313073:00:00 -73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:323038332e3139314d42:00:00 -73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3638302e3330394d42:00:00 -eof:1838207814 +73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a313273:00:00 +73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:323039332e3033394d42:00:00 +73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3637362e3733384d42:00:00 +eof:3042245255 diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/webtalk_pa.xml b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/webtalk_pa.xml index 68c3f126..949b9b9e 100644 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/webtalk_pa.xml +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/webtalk_pa.xml @@ -3,7 +3,7 @@ - +
@@ -18,49 +18,49 @@ This means code written to parse this file will need to be revisited each subseq - + - - + + - - + + - + - + - + - + - + - + - + - +
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_20.xml b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_20.xml new file mode 100644 index 00000000..7aae5b27 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_20.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_21.xml b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_21.xml new file mode 100644 index 00000000..7aae5b27 --- /dev/null +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_21.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/rom_hop_data_synth_1/gen_run.xml b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/rom_hop_data_synth_1/gen_run.xml index c5bda25b..cb43132a 100644 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/rom_hop_data_synth_1/gen_run.xml +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/rom_hop_data_synth_1/gen_run.xml @@ -1,7 +1,7 @@ - + diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/gen_run.xml b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/gen_run.xml index 714eee8c..235708bb 100644 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/gen_run.xml +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/gen_run.xml @@ -1,7 +1,7 @@ - + diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/.vivado.begin.rst b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/.vivado.begin.rst index cdb808b3..05c47269 100644 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/.vivado.begin.rst +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/.vivado.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/gen_run.xml b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/gen_run.xml index b751b4e8..77678ded 100644 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/gen_run.xml +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/gen_run.xml @@ -1,5 +1,5 @@ - + diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/project.wdf b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/project.wdf index d50b80fb..cafb86d0 100644 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/project.wdf +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/project.wdf @@ -24,12 +24,12 @@ version:1 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00 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+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3238:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3238:00:00 5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3966393835363732626435303431393139633038356339623061353561633562:506172656e742050412070726f6a656374204944:00 -eof:2018463593 +eof:296298308 diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp.dcp b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp.dcp index 4ed7044e..f0247de4 100644 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp.dcp +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp.dcp @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:3dc35a34a7119eefa9d697832940cd52e1981c03235c2e4159dc2da6879f2062 -size 181180 +oid sha256:cde5fabbdd14121a6a0721246f45f283831582b9b1876bd7aac7c0b3fab4a76e +size 293498 diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp.tcl b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp.tcl index 3573a0b4..c9f340b9 100644 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp.tcl +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp.tcl @@ -17,6 +17,8 @@ proc create_report { reportName command } { send_msg_id runtcl-5 warning "$msg" } } +set_param simulator.modelsimInstallPath /home/josh/Software/Mentor/modeltech/bin +set_param simulator.vcsmxInstallPath /home/josh/Software/Synopsys/vcs/T-2022.06/bin set_param project.vivado.isBlockSynthRun true set_msg_config -msgmgr_mode ooc_run create_project -in_memory -part xc7k410tffg900-2 diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp.vds b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp.vds index 976ff382..28a36260 100644 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp.vds +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp.vds @@ -2,8 +2,8 @@ # Vivado v2019.1.3 (64-bit) # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Thu Jun 15 10:53:59 2023 -# Process ID: 658851 +# Start of session at: Thu Jul 27 10:37:52 2023 +# Process ID: 203930 # Current directory: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1 # Command line: vivado -log vio_phase_comp.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_phase_comp.tcl # Log file: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp.vds @@ -16,34 +16,13 @@ Attempting to get a license for feature 'Synthesis' and/or device 'xc7k410t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k410t' INFO: [Device 21-403] Loading part xc7k410tffg900-2 INFO: Launching helper process for spawning children vivado processes -INFO: Helper process launched with PID 658962 +INFO: Helper process launched with PID 204191 --------------------------------------------------------------------------------- -Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 1829.910 ; gain = 149.719 ; free physical = 1052 ; free virtual = 31239 +Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 1830.883 ; gain = 153.719 ; free physical = 2320 ; free virtual = 33631 --------------------------------------------------------------------------------- INFO: [Synth 8-6157] synthesizing module 'vio_phase_comp' [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/rx_pre_process/vio_phase_comp/synth/vio_phase_comp.v:59] -WARNING: [Synth 8-3848] Net sl_iport0 in module/entity vio_phase_comp does not have driver. [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/rx_pre_process/vio_phase_comp/synth/vio_phase_comp.v:87] +WARNING: [Synth 8-3848] Net sl_iport0 in module/entity vio_phase_comp does not have driver. [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/rx_pre_process/vio_phase_comp/synth/vio_phase_comp.v:93] INFO: [Synth 8-6155] done synthesizing module 'vio_phase_comp' (8#1) [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/rx_pre_process/vio_phase_comp/synth/vio_phase_comp.v:59] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_rst -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Read -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Internal_cnt_rst -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_rst -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Read -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[15] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[14] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[13] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[12] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[11] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[10] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[9] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[8] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[7] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[6] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[5] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[4] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[3] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[2] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[1] -WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Internal_cnt_rst WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_rst WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Read WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[15] @@ -62,10 +41,27 @@ WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unc WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[2] WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[1] WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Internal_cnt_rst -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in2[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in3[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in4[0] -WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in5[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Read +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[15] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[14] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[13] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[12] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[11] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[10] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[9] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[8] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[7] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[6] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[5] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[4] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[3] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[2] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[1] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Internal_cnt_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Read +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Internal_cnt_rst WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in6[0] WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in7[0] WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in8[0] @@ -123,9 +119,13 @@ WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in59[0 WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in60[0] WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in61[0] WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in62[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in63[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in64[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in65[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in66[0] INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- -Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1891.629 ; gain = 211.438 ; free physical = 1310 ; free virtual = 31095 +Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1891.602 ; gain = 214.438 ; free physical = 2307 ; free virtual = 33620 --------------------------------------------------------------------------------- Report Check Netlist: @@ -138,10 +138,10 @@ Report Check Netlist: Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1894.598 ; gain = 214.406 ; free physical = 1267 ; free virtual = 31042 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1903.477 ; gain = 226.312 ; free physical = 2314 ; free virtual = 33628 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1894.598 ; gain = 214.406 ; free physical = 1267 ; free virtual = 31042 +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1903.477 ; gain = 226.312 ; free physical = 2314 ; free virtual = 33628 --------------------------------------------------------------------------------- INFO: [Project 1-570] Preparing netlist for logic optimization @@ -153,29 +153,29 @@ Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/rx_pre_process/vio_phase_comp/vio_phase_comp.xdc] Completed Processing XDC Constraints -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2077.254 ; gain = 0.000 ; free physical = 1178 ; free virtual = 30970 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2087.102 ; gain = 0.000 ; free physical = 2211 ; free virtual = 33525 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. -Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2083.191 ; gain = 5.938 ; free physical = 1178 ; free virtual = 30970 +Constraint Validation Runtime : Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2093.039 ; gain = 5.938 ; free physical = 2211 ; free virtual = 33525 --------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2083.191 ; gain = 403.000 ; free physical = 1269 ; free virtual = 31062 +Finished Constraint Validation : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2093.039 ; gain = 415.875 ; free physical = 2306 ; free virtual = 33621 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7k410tffg900-2 --------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2083.191 ; gain = 403.000 ; free physical = 1269 ; free virtual = 31062 +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2093.039 ; gain = 415.875 ; free physical = 2306 ; free virtual = 33621 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2083.191 ; gain = 403.000 ; free physical = 1271 ; free virtual = 31064 +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2093.039 ; gain = 415.875 ; free physical = 2303 ; free virtual = 33617 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2083.191 ; gain = 403.000 ; free physical = 1265 ; free virtual = 31058 +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2093.039 ; gain = 415.875 ; free physical = 2280 ; free virtual = 33596 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -188,22 +188,27 @@ Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : - 2 Input 4 Bit Adders := 1 + 2 Input 6 Bit Adders := 1 + 2 Input 3 Bit Adders := 1 2 Input 2 Bit Adders := 1 +---Registers : + 161 Bit Registers := 3 128 Bit Registers := 1 - 33 Bit Registers := 5 - 16 Bit Registers := 19 + 16 Bit Registers := 20 + 13 Bit Registers := 1 12 Bit Registers := 1 7 Bit Registers := 1 + 6 Bit Registers := 1 5 Bit Registers := 1 4 Bit Registers := 1 3 Bit Registers := 3 2 Bit Registers := 1 - 1 Bit Registers := 26 + 1 Bit Registers := 28 +---Muxes : 2 Input 16 Bit Muxes := 2 - 2 Input 1 Bit Muxes := 10 + 3 Input 13 Bit Muxes := 1 + 5 Input 12 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 11 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- @@ -214,19 +219,25 @@ Hierarchical RTL Component report Module vio_v3_0_20_probe_in_one Detailed RTL Component Info : +---Adders : - 2 Input 4 Bit Adders := 1 + 2 Input 6 Bit Adders := 1 +---Registers : - 33 Bit Registers := 5 + 161 Bit Registers := 3 16 Bit Registers := 1 - 4 Bit Registers := 1 + 6 Bit Registers := 1 1 Bit Registers := 2 +Module vio_v3_0_20_probe_width +Detailed RTL Component Info : ++---Adders : + 2 Input 2 Bit Adders := 1 ++---Registers : + 13 Bit Registers := 1 + 2 Bit Registers := 1 ++---Muxes : + 3 Input 13 Bit Muxes := 1 Module vio_v3_0_20_probe_out_one Detailed RTL Component Info : +---Registers : - 16 Bit Registers := 1 - 1 Bit Registers := 1 -+---Muxes : - 2 Input 1 Bit Muxes := 1 + 16 Bit Registers := 2 Module vio_v3_0_20_probe_out_one__parameterized0 Detailed RTL Component Info : +---Registers : @@ -237,22 +248,27 @@ Detailed RTL Component Info : Module vio_v3_0_20_probe_out_one__parameterized1 Detailed RTL Component Info : +---Registers : - 16 Bit Registers := 2 + 16 Bit Registers := 1 + 1 Bit Registers := 1 ++---Muxes : + 2 Input 1 Bit Muxes := 1 Module vio_v3_0_20_probe_out_all Detailed RTL Component Info : +---Registers : 16 Bit Registers := 1 - 3 Bit Registers := 1 - 1 Bit Registers := 10 + 4 Bit Registers := 1 + 1 Bit Registers := 11 +---Muxes : 2 Input 1 Bit Muxes := 2 -Module vio_v3_0_20_probe_width +Module vio_v3_0_20_probe_width__parameterized0 Detailed RTL Component Info : +---Adders : - 2 Input 2 Bit Adders := 1 + 2 Input 3 Bit Adders := 1 +---Registers : 12 Bit Registers := 1 - 2 Bit Registers := 1 + 3 Bit Registers := 1 ++---Muxes : + 5 Input 12 Bit Muxes := 1 Module xsdbs_v1_0_2_xsdbs Detailed RTL Component Info : +---Registers : @@ -293,79 +309,108 @@ Finished Part Resource Summary Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Warning: Parallel synthesis criteria is not met -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[2]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[2]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[2]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[2]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[3]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[4]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[4]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[4]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[4]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[5]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[5]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[5]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[5]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[6]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[6]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[6]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[6]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[7]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[7]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[7]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[7]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[8]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[8]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[8]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[8]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[9]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[9]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[9]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[9]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[10]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[10]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[10]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[10]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[11]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[11]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[11]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[11]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[12]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[12]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[12]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[12]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[13]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[13]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[13]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[13]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[14]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[14]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[14]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[14]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[15]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[15]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[15]' -INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[15]' -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[15] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[15] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[15] ) -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[6]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[6]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[6]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[6]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[6]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[7]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[7]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[7]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[7]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[7]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[8]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[8]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[8]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[8]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[8]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[10]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[10]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[10]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[10]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[10]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[11]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[11]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[11]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[11]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[11]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[12]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[12]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[12]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[12]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[12]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[13]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[13]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[13]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[13]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[13]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[14]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[14]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[14]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[14]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[14]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[15]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[15]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[15]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[15]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[15]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/addr_p1_reg[0]' (FD) to 'inst/DECODER_INST/xsdb_addr_2_0_p1_reg[0]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/addr_p1_reg[1]' (FD) to 'inst/DECODER_INST/xsdb_addr_2_0_p1_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/addr_p1_reg[2]' (FD) to 'inst/DECODER_INST/xsdb_addr_2_0_p1_reg[2]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[0]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[0]' (FD) to 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[1]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[1]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[1]' (FD) to 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[2]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[2]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[2]' (FD) to 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[3]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[3]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[8]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[3]' (FD) to 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[4]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[4]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[7]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[5]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[7]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[5]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[7]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[6]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[7]' -INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_WIDTH_INST/probe_width_int_reg[7] ) +INFO: [Synth 8-3886] merging instance 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[6]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[7]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[7]' (FD) to 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[7]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_IN_WIDTH_INST/probe_width_int_reg[7] ) INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[8]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[8]' (FD) to 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[9]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[9]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[10]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[9]' (FD) to 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[10]' INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[10]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[11]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[10]' (FD) to 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[11]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[11]' (FD) to 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[12]' --------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 2083.191 ; gain = 403.000 ; free physical = 1250 ; free virtual = 31049 +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:06 ; elapsed = 00:00:08 . Memory (MB): peak = 2093.039 ; gain = 415.875 ; free physical = 2277 ; free virtual = 33605 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -377,13 +422,13 @@ Report RTL Partitions: Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2083.191 ; gain = 403.000 ; free physical = 1187 ; free virtual = 30983 +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2093.039 ; gain = 415.875 ; free physical = 2120 ; free virtual = 33434 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2083.191 ; gain = 403.000 ; free physical = 1187 ; free virtual = 30983 +Finished Timing Optimization : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2093.039 ; gain = 415.875 ; free physical = 2119 ; free virtual = 33433 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -395,7 +440,7 @@ Report RTL Partitions: Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2083.191 ; gain = 403.000 ; free physical = 1206 ; free virtual = 30981 +Finished Technology Mapping : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2093.039 ; gain = 415.875 ; free physical = 2138 ; free virtual = 33428 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -415,6 +460,9 @@ Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- +INFO: [Synth 8-4618] Found max_fanout attribute set to 100 on net \PROBE_IN_INST/addr_count [0]. Fanout reduced from 135 to 68 by creating 1 replicas. +INFO: [Synth 8-4618] Found max_fanout attribute set to 100 on net \PROBE_IN_INST/addr_count [1]. Fanout reduced from 134 to 67 by creating 1 replicas. +INFO: [Synth 8-4618] Found max_fanout attribute set to 200 on net \PROBE_IN_INST/read_done . Fanout reduced from 322 to 161 by creating 1 replicas. --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- @@ -456,7 +504,7 @@ WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[2] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[1] to constant 0 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[0] to constant 0 --------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2083.191 ; gain = 403.000 ; free physical = 1206 ; free virtual = 30980 +Finished IO Insertion : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2093.039 ; gain = 415.875 ; free physical = 2150 ; free virtual = 33410 --------------------------------------------------------------------------------- Report Check Netlist: @@ -469,7 +517,7 @@ Report Check Netlist: Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2083.191 ; gain = 403.000 ; free physical = 1206 ; free virtual = 30980 +Finished Renaming Generated Instances : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2093.039 ; gain = 415.875 ; free physical = 2148 ; free virtual = 33409 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -481,25 +529,25 @@ Report RTL Partitions: Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2083.191 ; gain = 403.000 ; free physical = 1206 ; free virtual = 30980 +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2093.039 ; gain = 415.875 ; free physical = 2148 ; free virtual = 33409 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2083.191 ; gain = 403.000 ; free physical = 1206 ; free virtual = 30980 +Finished Renaming Generated Ports : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2093.039 ; gain = 415.875 ; free physical = 2148 ; free virtual = 33409 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2083.191 ; gain = 403.000 ; free physical = 1206 ; free virtual = 30980 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2093.039 ; gain = 415.875 ; free physical = 2148 ; free virtual = 33409 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2083.191 ; gain = 403.000 ; free physical = 1206 ; free virtual = 30980 +Finished Renaming Generated Nets : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2093.039 ; gain = 415.875 ; free physical = 2148 ; free virtual = 33409 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report @@ -515,14 +563,14 @@ Report Cell Usage: +------+------+------+ | |Cell |Count | +------+------+------+ -|1 |LUT1 | 3| -|2 |LUT2 | 12| -|3 |LUT3 | 30| -|4 |LUT4 | 82| -|5 |LUT5 | 24| -|6 |LUT6 | 122| -|7 |MUXF7 | 1| -|8 |FDRE | 577| +|1 |LUT1 | 2| +|2 |LUT2 | 27| +|3 |LUT3 | 363| +|4 |LUT4 | 11| +|5 |LUT5 | 28| +|6 |LUT6 | 237| +|7 |MUXF7 | 51| +|8 |FDRE | 1232| |9 |FDSE | 2| +------+------+------+ @@ -530,51 +578,53 @@ Report Instance Areas: +------+---------------------------------------+--------------------------------------------+------+ | |Instance |Module |Cells | +------+---------------------------------------+--------------------------------------------+------+ -|1 |top | | 853| -|2 | inst |vio_v3_0_20_vio | 853| +|1 |top | | 1953| +|2 | inst |vio_v3_0_20_vio | 1953| |3 | U_XSDB_SLAVE |xsdbs_v1_0_2_xsdbs | 248| -|4 | DECODER_INST |vio_v3_0_20_decoder | 90| -|5 | PROBE_IN_INST |vio_v3_0_20_probe_in_one | 296| -|6 | PROBE_OUT_ALL_INST |vio_v3_0_20_probe_out_all | 198| -|7 | \G_PROBE_OUT[0].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one | 3| -|8 | \G_PROBE_OUT[1].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_0 | 3| -|9 | \G_PROBE_OUT[2].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized0 | 3| -|10 | \G_PROBE_OUT[3].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_1 | 3| -|11 | \G_PROBE_OUT[4].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized1 | 32| -|12 | \G_PROBE_OUT[5].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized1_2 | 32| -|13 | \G_PROBE_OUT[6].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized1_3 | 32| -|14 | \G_PROBE_OUT[7].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized1_4 | 32| -|15 | PROBE_OUT_WIDTH_INST |vio_v3_0_20_probe_width | 5| +|4 | DECODER_INST |vio_v3_0_20_decoder | 95| +|5 | PROBE_IN_INST |vio_v3_0_20_probe_in_one | 1360| +|6 | PROBE_IN_WIDTH_INST |vio_v3_0_20_probe_width | 8| +|7 | PROBE_OUT_ALL_INST |vio_v3_0_20_probe_out_all | 218| +|8 | \G_PROBE_OUT[0].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one | 32| +|9 | \G_PROBE_OUT[1].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_0 | 32| +|10 | \G_PROBE_OUT[2].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_1 | 32| +|11 | \G_PROBE_OUT[3].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_2 | 47| +|12 | \G_PROBE_OUT[4].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized0 | 3| +|13 | \G_PROBE_OUT[5].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized1 | 3| +|14 | \G_PROBE_OUT[6].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized0_3 | 3| +|15 | \G_PROBE_OUT[7].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized0_4 | 3| +|16 | \G_PROBE_OUT[8].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized0_5 | 3| +|17 | PROBE_OUT_WIDTH_INST |vio_v3_0_20_probe_width__parameterized0 | 8| +------+---------------------------------------+--------------------------------------------+------+ --------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2083.191 ; gain = 403.000 ; free physical = 1206 ; free virtual = 30980 +Finished Writing Synthesis Report : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2093.039 ; gain = 415.875 ; free physical = 2148 ; free virtual = 33409 --------------------------------------------------------------------------------- -Synthesis finished with 0 errors, 0 critical warnings and 291 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 2083.191 ; gain = 214.406 ; free physical = 1262 ; free virtual = 31037 -Synthesis Optimization Complete : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2083.191 ; gain = 403.000 ; free physical = 1276 ; free virtual = 31050 +Synthesis finished with 0 errors, 0 critical warnings and 289 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2093.039 ; gain = 226.312 ; free physical = 2200 ; free virtual = 33461 +Synthesis Optimization Complete : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2093.039 ; gain = 415.875 ; free physical = 2214 ; free virtual = 33474 INFO: [Project 1-571] Translating synthesized netlist -INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement +INFO: [Netlist 29-17] Analyzing 51 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2083.191 ; gain = 0.000 ; free physical = 1192 ; free virtual = 30968 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2093.039 ; gain = 0.000 ; free physical = 2137 ; free virtual = 33397 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Common 17-83] Releasing license: Synthesis -85 Infos, 138 Warnings, 0 Critical Warnings and 0 Errors encountered. +117 Infos, 138 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully -synth_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 2083.191 ; gain = 684.277 ; free physical = 1284 ; free virtual = 31060 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2083.191 ; gain = 0.000 ; free physical = 1283 ; free virtual = 31059 +synth_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 2093.039 ; gain = 676.738 ; free physical = 2226 ; free virtual = 33486 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2093.039 ; gain = 0.000 ; free physical = 2226 ; free virtual = 33486 WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp.dcp' has been generated. WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. -INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP vio_phase_comp, cache-ID = 0ddc3e874811cad5 -INFO: [Coretcl 2-1174] Renamed 14 cell refs. -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2107.203 ; gain = 0.000 ; free physical = 1286 ; free virtual = 31064 +INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP vio_phase_comp, cache-ID = 115dfcf85af89900 +INFO: [Coretcl 2-1174] Renamed 16 cell refs. +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2117.051 ; gain = 0.000 ; free physical = 2170 ; free virtual = 33426 WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file vio_phase_comp_utilization_synth.rpt -pb vio_phase_comp_utilization_synth.pb -INFO: [Common 17-206] Exiting Vivado at Thu Jun 15 10:54:16 2023... +INFO: [Common 17-206] Exiting Vivado at Thu Jul 27 10:38:10 2023... diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_sim_netlist.v b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_sim_netlist.v index ab5fcf5a..ca7cf69b 100644 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_sim_netlist.v +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_sim_netlist.v @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:c54161de531f62c9b95a7d5c71ab9df4313489ff5f13778d75d6765db5339e9c -size 425691 +oid sha256:342e53512cd5a0261c780f4413b9b4d7b4d6ec714358837dfb8b900919ec4908 +size 677448 diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_sim_netlist.vhdl b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_sim_netlist.vhdl index efa6cc2d..969f0c15 100644 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_sim_netlist.vhdl +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_sim_netlist.vhdl @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:06d97b70737529844e27698b1b03e7a08b33b9958b620aa283bd7a6be042800f -size 736925 +oid sha256:5fc6d35a6908ab3c6d9d9c766167802ccbc0e94cf45fcbe327eb98379f236aad +size 1095960 diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_stub.v b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_stub.v index 2a0bcfb0..9e83bd15 100644 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_stub.v +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_stub.v @@ -1,7 +1,7 @@ // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 -// Date : Thu Jun 15 10:54:16 2023 +// Date : Thu Jul 27 10:38:10 2023 // Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS // Command : write_verilog -force -mode synth_stub // /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_stub.v @@ -14,18 +14,24 @@ // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. // Please paste the declaration into a Verilog source file or add the file as an additional source. (* X_CORE_INFO = "vio,Vivado 2019.1.3" *) -module vio_phase_comp(clk, probe_in0, probe_in1, probe_out0, - probe_out1, probe_out2, probe_out3, probe_out4, probe_out5, probe_out6, probe_out7) -/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[31:0],probe_in1[0:0],probe_out0[0:0],probe_out1[0:0],probe_out2[0:0],probe_out3[0:0],probe_out4[15:0],probe_out5[15:0],probe_out6[15:0],probe_out7[15:0]" */; +module vio_phase_comp(clk, probe_in0, probe_in1, probe_in2, probe_in3, + probe_in4, probe_in5, probe_out0, probe_out1, probe_out2, probe_out3, probe_out4, probe_out5, + probe_out6, probe_out7, probe_out8) +/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[0:0],probe_in1[31:0],probe_in2[31:0],probe_in3[31:0],probe_in4[31:0],probe_in5[31:0],probe_out0[15:0],probe_out1[15:0],probe_out2[15:0],probe_out3[15:0],probe_out4[0:0],probe_out5[0:0],probe_out6[0:0],probe_out7[0:0],probe_out8[0:0]" */; input clk; - input [31:0]probe_in0; - input [0:0]probe_in1; - output [0:0]probe_out0; - output [0:0]probe_out1; - output [0:0]probe_out2; - output [0:0]probe_out3; - output [15:0]probe_out4; - output [15:0]probe_out5; - output [15:0]probe_out6; - output [15:0]probe_out7; + input [0:0]probe_in0; + input [31:0]probe_in1; + input [31:0]probe_in2; + input [31:0]probe_in3; + input [31:0]probe_in4; + input [31:0]probe_in5; + output [15:0]probe_out0; + output [15:0]probe_out1; + output [15:0]probe_out2; + output [15:0]probe_out3; + output [0:0]probe_out4; + output [0:0]probe_out5; + output [0:0]probe_out6; + output [0:0]probe_out7; + output [0:0]probe_out8; endmodule diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_stub.vhdl b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_stub.vhdl index 60751ac0..5781802a 100644 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_stub.vhdl +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_stub.vhdl @@ -1,7 +1,7 @@ -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 --- Date : Thu Jun 15 10:54:16 2023 +-- Date : Thu Jul 27 10:38:10 2023 -- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS -- Command : write_vhdl -force -mode synth_stub -- /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_stub.vhdl @@ -15,16 +15,21 @@ use IEEE.STD_LOGIC_1164.ALL; entity vio_phase_comp is Port ( clk : in STD_LOGIC; - probe_in0 : in STD_LOGIC_VECTOR ( 31 downto 0 ); - probe_in1 : in STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out2 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out3 : out STD_LOGIC_VECTOR ( 0 to 0 ); - probe_out4 : out STD_LOGIC_VECTOR ( 15 downto 0 ); - probe_out5 : out STD_LOGIC_VECTOR ( 15 downto 0 ); - probe_out6 : out STD_LOGIC_VECTOR ( 15 downto 0 ); - probe_out7 : out STD_LOGIC_VECTOR ( 15 downto 0 ) + probe_in0 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe_in1 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + probe_in2 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + probe_in3 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + probe_in4 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + probe_in5 : in STD_LOGIC_VECTOR ( 31 downto 0 ); + probe_out0 : out STD_LOGIC_VECTOR ( 15 downto 0 ); + probe_out1 : out STD_LOGIC_VECTOR ( 15 downto 0 ); + probe_out2 : out STD_LOGIC_VECTOR ( 15 downto 0 ); + probe_out3 : out STD_LOGIC_VECTOR ( 15 downto 0 ); + probe_out4 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out5 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out6 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out7 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out8 : out STD_LOGIC_VECTOR ( 0 to 0 ) ); end vio_phase_comp; @@ -33,7 +38,7 @@ architecture stub of vio_phase_comp is attribute syn_black_box : boolean; attribute black_box_pad_pin : string; attribute syn_black_box of stub : architecture is true; -attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[31:0],probe_in1[0:0],probe_out0[0:0],probe_out1[0:0],probe_out2[0:0],probe_out3[0:0],probe_out4[15:0],probe_out5[15:0],probe_out6[15:0],probe_out7[15:0]"; +attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[0:0],probe_in1[31:0],probe_in2[31:0],probe_in3[31:0],probe_in4[31:0],probe_in5[31:0],probe_out0[15:0],probe_out1[15:0],probe_out2[15:0],probe_out3[15:0],probe_out4[0:0],probe_out5[0:0],probe_out6[0:0],probe_out7[0:0],probe_out8[0:0]"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3"; begin diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_utilization_synth.pb b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_utilization_synth.pb index e9407593..ff7a6d89 100644 Binary files a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_utilization_synth.pb and b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_utilization_synth.pb differ diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_utilization_synth.rpt b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_utilization_synth.rpt index 2ee2edd8..6d3f7667 100644 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_utilization_synth.rpt +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_utilization_synth.rpt @@ -1,7 +1,7 @@ Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. ----------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 -| Date : Thu Jun 15 10:54:16 2023 +| Date : Thu Jul 27 10:38:10 2023 | Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS | Command : report_utilization -file vio_phase_comp_utilization_synth.rpt -pb vio_phase_comp_utilization_synth.pb | Design : vio_phase_comp @@ -30,13 +30,13 @@ Table of Contents +-------------------------+------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +-------------------------+------+-------+-----------+-------+ -| Slice LUTs* | 250 | 0 | 254200 | 0.10 | -| LUT as Logic | 250 | 0 | 254200 | 0.10 | +| Slice LUTs* | 637 | 0 | 254200 | 0.25 | +| LUT as Logic | 637 | 0 | 254200 | 0.25 | | LUT as Memory | 0 | 0 | 90600 | 0.00 | -| Slice Registers | 579 | 0 | 508400 | 0.11 | -| Register as Flip Flop | 579 | 0 | 508400 | 0.11 | +| Slice Registers | 1234 | 0 | 508400 | 0.24 | +| Register as Flip Flop | 1234 | 0 | 508400 | 0.24 | | Register as Latch | 0 | 0 | 508400 | 0.00 | -| F7 Muxes | 1 | 0 | 127100 | <0.01 | +| F7 Muxes | 51 | 0 | 127100 | 0.04 | | F8 Muxes | 0 | 0 | 63550 | 0.00 | +-------------------------+------+-------+-----------+-------+ * Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. @@ -57,7 +57,7 @@ Table of Contents | 0 | Yes | - | Set | | 0 | Yes | - | Reset | | 2 | Yes | Set | - | -| 577 | Yes | Reset | - | +| 1232 | Yes | Reset | - | +-------+--------------+-------------+--------------+ @@ -151,15 +151,15 @@ Table of Contents +----------+------+---------------------+ | Ref Name | Used | Functional Category | +----------+------+---------------------+ -| FDRE | 577 | Flop & Latch | -| LUT6 | 122 | LUT | -| LUT4 | 82 | LUT | -| LUT3 | 30 | LUT | -| LUT5 | 24 | LUT | -| LUT2 | 12 | LUT | -| LUT1 | 3 | LUT | +| FDRE | 1232 | Flop & Latch | +| LUT3 | 363 | LUT | +| LUT6 | 237 | LUT | +| MUXF7 | 51 | MuxFx | +| LUT5 | 28 | LUT | +| LUT2 | 27 | LUT | +| LUT4 | 11 | LUT | +| LUT1 | 2 | LUT | | FDSE | 2 | Flop & Latch | -| MUXF7 | 1 | MuxFx | +----------+------+---------------------+ diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vivado.pb b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vivado.pb index 4fa78054..28cf2237 100644 Binary files a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vivado.pb and b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vivado.pb differ diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.xpr b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.xpr index daf7efb9..399e748f 100644 --- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.xpr +++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.xpr @@ -39,13 +39,13 @@