Archived
first commit after restructuring
This commit is contained in:
@@ -0,0 +1,68 @@
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####################################################################################
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## Copyright 2018(c) Analog Devices, Inc.
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## Auto-generated, do not modify!
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####################################################################################
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LIBRARY_NAME := axi_ad9361
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GENERIC_DEPS += ../common/ad_addsub.v
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GENERIC_DEPS += ../common/ad_datafmt.v
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GENERIC_DEPS += ../common/ad_dds.v
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GENERIC_DEPS += ../common/ad_dds_1.v
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GENERIC_DEPS += ../common/ad_dds_2.v
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GENERIC_DEPS += ../common/ad_dds_cordic_pipe.v
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GENERIC_DEPS += ../common/ad_dds_sine.v
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GENERIC_DEPS += ../common/ad_dds_sine_cordic.v
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GENERIC_DEPS += ../common/ad_iqcor.v
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GENERIC_DEPS += ../common/ad_pnmon.v
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GENERIC_DEPS += ../common/ad_pps_receiver.v
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GENERIC_DEPS += ../common/ad_rst.v
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GENERIC_DEPS += ../common/ad_tdd_control.v
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GENERIC_DEPS += ../common/up_adc_channel.v
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GENERIC_DEPS += ../common/up_adc_common.v
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GENERIC_DEPS += ../common/up_axi.v
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GENERIC_DEPS += ../common/up_clock_mon.v
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GENERIC_DEPS += ../common/up_dac_channel.v
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GENERIC_DEPS += ../common/up_dac_common.v
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GENERIC_DEPS += ../common/up_delay_cntrl.v
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GENERIC_DEPS += ../common/up_tdd_cntrl.v
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GENERIC_DEPS += ../common/up_xfer_cntrl.v
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GENERIC_DEPS += ../common/up_xfer_status.v
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GENERIC_DEPS += axi_ad9361.v
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GENERIC_DEPS += axi_ad9361_rx.v
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GENERIC_DEPS += axi_ad9361_rx_channel.v
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GENERIC_DEPS += axi_ad9361_rx_pnmon.v
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GENERIC_DEPS += axi_ad9361_tdd.v
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GENERIC_DEPS += axi_ad9361_tdd_if.v
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GENERIC_DEPS += axi_ad9361_tx.v
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GENERIC_DEPS += axi_ad9361_tx_channel.v
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XILINX_DEPS += ../common/ad_pps_receiver_constr.ttcl
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XILINX_DEPS += ../xilinx/common/ad_data_clk.v
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XILINX_DEPS += ../xilinx/common/ad_data_in.v
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XILINX_DEPS += ../xilinx/common/ad_data_out.v
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XILINX_DEPS += ../xilinx/common/ad_dcfilter.v
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XILINX_DEPS += ../xilinx/common/ad_mul.v
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XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc
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XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc
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XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
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XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc
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XILINX_DEPS += axi_ad9361_constr.xdc
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XILINX_DEPS += axi_ad9361_ip.tcl
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XILINX_DEPS += xilinx/axi_ad9361_cmos_if.v
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XILINX_DEPS += xilinx/axi_ad9361_lvds_if.v
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INTEL_DEPS += ../intel/common/ad_dcfilter.v
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INTEL_DEPS += ../intel/common/ad_mul.v
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INTEL_DEPS += ../intel/common/up_clock_mon_constr.sdc
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INTEL_DEPS += ../intel/common/up_rst_constr.sdc
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INTEL_DEPS += ../intel/common/up_xfer_cntrl_constr.sdc
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INTEL_DEPS += ../intel/common/up_xfer_status_constr.sdc
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INTEL_DEPS += axi_ad9361_constr.sdc
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INTEL_DEPS += axi_ad9361_hw.tcl
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INTEL_DEPS += intel/axi_ad9361_cmos_if.v
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INTEL_DEPS += intel/axi_ad9361_lvds_if.v
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INTEL_DEPS += intel/axi_ad9361_lvds_if_10.v
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INTEL_DEPS += intel/axi_ad9361_lvds_if_c5.v
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include ../scripts/library.mk
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@@ -0,0 +1,3 @@
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version:1
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6d6f64655f636f756e7465727c42617463684d6f6465:1
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eof:
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@@ -0,0 +1,6 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
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<!-- -->
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<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
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<labtools version="1" minor="0"/>
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@@ -0,0 +1,752 @@
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// ***************************************************************************
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||||
// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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||||
// In this HDL repository, there are many different and unique modules, consisting
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||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
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||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
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||||
//
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||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
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||||
//
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||||
// Redistribution and use of source or resulting binaries, with or without modification
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||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
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||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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||||
//
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||||
// OR
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||||
//
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||||
// 2. An ADI specific BSD license, which can be found in the top level directory
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||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
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||||
// as long as it attaches to an ADI device.
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||||
//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_ad9361 #(
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// parameters
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parameter ID = 0,
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parameter MODE_1R1T = 0,
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parameter FPGA_TECHNOLOGY = 0,
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parameter FPGA_FAMILY = 0,
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parameter SPEED_GRADE = 0,
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parameter DEV_PACKAGE = 0,
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parameter TDD_DISABLE = 0,
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parameter PPS_RECEIVER_ENABLE = 0,
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parameter CMOS_OR_LVDS_N = 0,
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parameter ADC_INIT_DELAY = 0,
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parameter ADC_DATAPATH_DISABLE = 0,
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parameter ADC_USERPORTS_DISABLE = 0,
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parameter ADC_DATAFORMAT_DISABLE = 0,
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parameter ADC_DCFILTER_DISABLE = 0,
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parameter ADC_IQCORRECTION_DISABLE = 0,
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parameter DAC_INIT_DELAY = 0,
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parameter DAC_CLK_EDGE_SEL = 0,
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parameter DAC_IODELAY_ENABLE = 0,
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parameter DAC_DATAPATH_DISABLE = 0,
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parameter DAC_DDS_DISABLE = 0,
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parameter DAC_DDS_TYPE = 1,
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parameter DAC_DDS_CORDIC_DW = 14,
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parameter DAC_DDS_CORDIC_PHASE_DW = 13,
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parameter DAC_USERPORTS_DISABLE = 0,
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parameter DAC_IQCORRECTION_DISABLE = 0,
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parameter IO_DELAY_GROUP = "dev_if_delay_group",
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parameter MIMO_ENABLE = 0,
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parameter USE_SSI_CLK = 1,
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parameter DELAY_REFCLK_FREQUENCY = 200,
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parameter RX_NODPA = 0) (
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// physical interface (receive-lvds)
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input rx_clk_in_p,
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input rx_clk_in_n,
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input rx_frame_in_p,
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input rx_frame_in_n,
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input [ 5:0] rx_data_in_p,
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input [ 5:0] rx_data_in_n,
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// physical interface (receive-cmos)
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input rx_clk_in,
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input rx_frame_in,
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input [11:0] rx_data_in,
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// physical interface (transmit-lvds)
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output tx_clk_out_p,
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output tx_clk_out_n,
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output tx_frame_out_p,
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output tx_frame_out_n,
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output [ 5:0] tx_data_out_p,
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output [ 5:0] tx_data_out_n,
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// physical interface (transmit-cmos)
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output tx_clk_out,
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output tx_frame_out,
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output [11:0] tx_data_out,
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// ensm control
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output enable,
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output txnrx,
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// transmit master/slave
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input dac_sync_in,
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output dac_sync_out,
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// tdd sync
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input tdd_sync,
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output tdd_sync_cntr,
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input gps_pps,
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output gps_pps_irq,
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// delay clock
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input delay_clk,
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// master interface
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output l_clk,
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input clk,
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output rst,
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// dma interface
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output adc_enable_i0,
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output adc_valid_i0,
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output [15:0] adc_data_i0,
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output adc_enable_q0,
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output adc_valid_q0,
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output [15:0] adc_data_q0,
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output adc_enable_i1,
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output adc_valid_i1,
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output [15:0] adc_data_i1,
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output adc_enable_q1,
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output adc_valid_q1,
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output [15:0] adc_data_q1,
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input adc_dovf,
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output adc_r1_mode,
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output dac_enable_i0,
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output dac_valid_i0,
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input [15:0] dac_data_i0,
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output dac_enable_q0,
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output dac_valid_q0,
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input [15:0] dac_data_q0,
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output dac_enable_i1,
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output dac_valid_i1,
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input [15:0] dac_data_i1,
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output dac_enable_q1,
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output dac_valid_q1,
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input [15:0] dac_data_q1,
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input dac_dunf,
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output dac_r1_mode,
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// axi interface
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input s_axi_aclk,
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input s_axi_aresetn,
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input s_axi_awvalid,
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input [15:0] s_axi_awaddr,
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input [ 2:0] s_axi_awprot,
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output s_axi_awready,
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input s_axi_wvalid,
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input [31:0] s_axi_wdata,
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input [ 3:0] s_axi_wstrb,
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output s_axi_wready,
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output s_axi_bvalid,
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output [ 1:0] s_axi_bresp,
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input s_axi_bready,
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input s_axi_arvalid,
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input [15:0] s_axi_araddr,
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input [ 2:0] s_axi_arprot,
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output s_axi_arready,
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output s_axi_rvalid,
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output [31:0] s_axi_rdata,
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output [ 1:0] s_axi_rresp,
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input s_axi_rready,
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// gpio
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input up_enable,
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input up_txnrx,
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input [31:0] up_dac_gpio_in,
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output [31:0] up_dac_gpio_out,
|
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input [31:0] up_adc_gpio_in,
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output [31:0] up_adc_gpio_out);
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|
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// derived parameters
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|
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localparam ADC_USERPORTS_DISABLE_INT = (ADC_DATAPATH_DISABLE == 1) ? 1 : ADC_USERPORTS_DISABLE;
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localparam ADC_DATAFORMAT_DISABLE_INT = (ADC_DATAPATH_DISABLE == 1) ? 1 : ADC_DATAFORMAT_DISABLE;
|
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localparam ADC_DCFILTER_DISABLE_INT = (ADC_DATAPATH_DISABLE == 1) ? 1 : ADC_DCFILTER_DISABLE;
|
||||
localparam ADC_IQCORRECTION_DISABLE_INT = (ADC_DATAPATH_DISABLE == 1) ? 1 : ADC_IQCORRECTION_DISABLE;
|
||||
localparam DAC_DDS_DISABLE_INT = (DAC_DATAPATH_DISABLE == 1) ? 1 : DAC_DDS_DISABLE;
|
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localparam DAC_USERPORTS_DISABLE_INT = (DAC_DATAPATH_DISABLE == 1) ? 1 : DAC_USERPORTS_DISABLE;
|
||||
localparam DAC_DELAYCNTRL_DISABLE_INT = (DAC_IODELAY_ENABLE == 1) ? 0 : 1;
|
||||
localparam DAC_IQCORRECTION_DISABLE_INT = (DAC_DATAPATH_DISABLE == 1) ? 1 : DAC_IQCORRECTION_DISABLE;
|
||||
|
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// internal registers
|
||||
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reg adc_valid_i0_int = 'd0;
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reg adc_valid_q0_int = 'd0;
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reg adc_valid_i1_int = 'd0;
|
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reg adc_valid_q1_int = 'd0;
|
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reg [15:0] adc_data_i0_int = 'd0;
|
||||
reg [15:0] adc_data_q0_int = 'd0;
|
||||
reg [15:0] adc_data_i1_int = 'd0;
|
||||
reg [15:0] adc_data_q1_int = 'd0;
|
||||
reg dac_valid_i0_int = 'd0;
|
||||
reg dac_valid_q0_int = 'd0;
|
||||
reg dac_valid_i1_int = 'd0;
|
||||
reg dac_valid_q1_int = 'd0;
|
||||
reg up_wack = 'd0;
|
||||
reg up_rack = 'd0;
|
||||
reg [31:0] up_rdata = 'd0;
|
||||
|
||||
// internal clocks and resets
|
||||
|
||||
wire up_clk;
|
||||
wire up_rstn;
|
||||
wire mmcm_rst;
|
||||
wire delay_rst;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire adc_ddr_edgesel_s;
|
||||
wire adc_valid_s;
|
||||
wire adc_valid_i0_s;
|
||||
wire adc_valid_q0_s;
|
||||
wire adc_valid_i1_s;
|
||||
wire adc_valid_q1_s;
|
||||
wire [15:0] adc_data_i0_s;
|
||||
wire [15:0] adc_data_q0_s;
|
||||
wire [15:0] adc_data_i1_s;
|
||||
wire [15:0] adc_data_q1_s;
|
||||
wire [47:0] adc_data_s;
|
||||
wire adc_status_s;
|
||||
wire dac_clksel_s;
|
||||
wire dac_valid_s;
|
||||
wire [47:0] dac_data_s;
|
||||
wire dac_valid_i0_s;
|
||||
wire dac_valid_q0_s;
|
||||
wire dac_valid_i1_s;
|
||||
wire dac_valid_q1_s;
|
||||
wire dac_data_i0_s;
|
||||
wire dac_data_q0_s;
|
||||
wire dac_data_i1_s;
|
||||
wire dac_data_q1_s;
|
||||
wire dac_sync_enable;
|
||||
wire [12:0] up_adc_dld_s;
|
||||
wire [64:0] up_adc_dwdata_s;
|
||||
wire [64:0] up_adc_drdata_s;
|
||||
wire [15:0] up_dac_dld_s;
|
||||
wire [79:0] up_dac_dwdata_s;
|
||||
wire [79:0] up_dac_drdata_s;
|
||||
wire delay_locked_s;
|
||||
wire up_wreq_s;
|
||||
wire [13:0] up_waddr_s;
|
||||
wire [31:0] up_wdata_s;
|
||||
wire up_wack_rx_s;
|
||||
wire up_wack_tx_s;
|
||||
wire up_rreq_s;
|
||||
wire [13:0] up_raddr_s;
|
||||
wire [31:0] up_rdata_rx_s;
|
||||
wire up_rack_rx_s;
|
||||
wire [31:0] up_rdata_tx_s;
|
||||
wire up_rack_tx_s;
|
||||
wire up_wack_tdd_s;
|
||||
wire up_rack_tdd_s;
|
||||
wire [31:0] up_rdata_tdd_s;
|
||||
wire tdd_enable_s;
|
||||
wire tdd_txnrx_s;
|
||||
wire tdd_mode_s;
|
||||
wire tdd_tx_valid_s;
|
||||
wire tdd_rx_valid_s;
|
||||
wire tdd_rx_vco_en_s;
|
||||
wire tdd_tx_vco_en_s;
|
||||
wire tdd_rx_rf_en_s;
|
||||
wire tdd_tx_rf_en_s;
|
||||
wire [ 7:0] tdd_status_s;
|
||||
wire up_drp_sel;
|
||||
wire up_drp_wr;
|
||||
wire [11:0] up_drp_addr;
|
||||
wire [31:0] up_drp_wdata;
|
||||
wire [31:0] up_drp_rdata;
|
||||
wire up_drp_ready;
|
||||
wire up_drp_locked;
|
||||
|
||||
wire [31:0] up_pps_rcounter_s;
|
||||
wire up_pps_status_s;
|
||||
wire up_irq_mask_s;
|
||||
wire adc_up_pps_irq_mask_s;
|
||||
wire dac_up_pps_irq_mask_s;
|
||||
|
||||
// signal name changes
|
||||
|
||||
assign up_clk = s_axi_aclk;
|
||||
assign up_rstn = s_axi_aresetn;
|
||||
|
||||
// processor read interface
|
||||
|
||||
always @(negedge up_rstn or posedge up_clk) begin
|
||||
if (up_rstn == 0) begin
|
||||
up_wack <= 'd0;
|
||||
up_rack <= 'd0;
|
||||
up_rdata <= 'd0;
|
||||
end else begin
|
||||
up_wack <= up_wack_rx_s | up_wack_tx_s | up_wack_tdd_s;
|
||||
up_rack <= up_rack_rx_s | up_rack_tx_s | up_rack_tdd_s;
|
||||
up_rdata <= up_rdata_rx_s | up_rdata_tx_s | up_rdata_tdd_s;
|
||||
end
|
||||
end
|
||||
|
||||
// device interface
|
||||
|
||||
generate
|
||||
if (CMOS_OR_LVDS_N == 1) begin
|
||||
|
||||
assign tx_clk_out_p = 1'd0;
|
||||
assign tx_clk_out_n = 1'd1;
|
||||
assign tx_frame_out_p = 1'd0;
|
||||
assign tx_frame_out_n = 1'd0;
|
||||
assign tx_data_out_p = 6'h00;
|
||||
assign tx_data_out_n = 6'h3f;
|
||||
|
||||
axi_ad9361_cmos_if #(
|
||||
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
|
||||
.DAC_IODELAY_ENABLE (DAC_IODELAY_ENABLE),
|
||||
.IO_DELAY_GROUP (IO_DELAY_GROUP),
|
||||
.CLK_DESKEW (MIMO_ENABLE),
|
||||
.USE_SSI_CLK (USE_SSI_CLK),
|
||||
.DELAY_REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
|
||||
i_dev_if (
|
||||
.rx_clk_in (rx_clk_in),
|
||||
.rx_frame_in (rx_frame_in),
|
||||
.rx_data_in (rx_data_in),
|
||||
.tx_clk_out (tx_clk_out),
|
||||
.tx_frame_out (tx_frame_out),
|
||||
.tx_data_out (tx_data_out),
|
||||
.enable (enable),
|
||||
.txnrx (txnrx),
|
||||
.rst (rst),
|
||||
.clk (clk),
|
||||
.l_clk (l_clk),
|
||||
.adc_valid (adc_valid_s),
|
||||
.adc_data (adc_data_s),
|
||||
.adc_status (adc_status_s),
|
||||
.adc_r1_mode (adc_r1_mode),
|
||||
.adc_ddr_edgesel (adc_ddr_edgesel_s),
|
||||
.dac_valid (dac_valid_s),
|
||||
.dac_data (dac_data_s),
|
||||
.dac_clksel (dac_clksel_s),
|
||||
.dac_r1_mode (dac_r1_mode),
|
||||
.tdd_enable (tdd_enable_s),
|
||||
.tdd_txnrx (tdd_txnrx_s),
|
||||
.tdd_mode (tdd_mode_s),
|
||||
.mmcm_rst (mmcm_rst),
|
||||
.up_clk (up_clk),
|
||||
.up_rstn (up_rstn),
|
||||
.up_enable (up_enable),
|
||||
.up_txnrx (up_txnrx),
|
||||
.up_adc_dld (up_adc_dld_s),
|
||||
.up_adc_dwdata (up_adc_dwdata_s),
|
||||
.up_adc_drdata (up_adc_drdata_s),
|
||||
.up_dac_dld (up_dac_dld_s),
|
||||
.up_dac_dwdata (up_dac_dwdata_s),
|
||||
.up_dac_drdata (up_dac_drdata_s),
|
||||
.delay_clk (delay_clk),
|
||||
.delay_rst (delay_rst),
|
||||
.delay_locked (delay_locked_s),
|
||||
.up_drp_sel (up_drp_sel),
|
||||
.up_drp_wr (up_drp_wr),
|
||||
.up_drp_addr (up_drp_addr),
|
||||
.up_drp_wdata (up_drp_wdata),
|
||||
.up_drp_rdata (up_drp_rdata),
|
||||
.up_drp_ready (up_drp_ready),
|
||||
.up_drp_locked(up_drp_locked));
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate
|
||||
if (CMOS_OR_LVDS_N == 0) begin
|
||||
|
||||
assign tx_clk_out = 1'd0;
|
||||
assign tx_frame_out = 1'd0;
|
||||
assign tx_data_out = 12'd0;
|
||||
assign up_adc_drdata_s[64:35] = 30'd0;
|
||||
assign up_dac_drdata_s[79:50] = 30'd0;
|
||||
|
||||
axi_ad9361_lvds_if #(
|
||||
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
|
||||
.DAC_IODELAY_ENABLE (DAC_IODELAY_ENABLE),
|
||||
.IO_DELAY_GROUP (IO_DELAY_GROUP),
|
||||
.CLK_DESKEW (MIMO_ENABLE),
|
||||
.USE_SSI_CLK (USE_SSI_CLK),
|
||||
.DELAY_REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY),
|
||||
.RX_NODPA (RX_NODPA))
|
||||
i_dev_if (
|
||||
.rx_clk_in_p (rx_clk_in_p),
|
||||
.rx_clk_in_n (rx_clk_in_n),
|
||||
.rx_frame_in_p (rx_frame_in_p),
|
||||
.rx_frame_in_n (rx_frame_in_n),
|
||||
.rx_data_in_p (rx_data_in_p),
|
||||
.rx_data_in_n (rx_data_in_n),
|
||||
.tx_clk_out_p (tx_clk_out_p),
|
||||
.tx_clk_out_n (tx_clk_out_n),
|
||||
.tx_frame_out_p (tx_frame_out_p),
|
||||
.tx_frame_out_n (tx_frame_out_n),
|
||||
.tx_data_out_p (tx_data_out_p),
|
||||
.tx_data_out_n (tx_data_out_n),
|
||||
.enable (enable),
|
||||
.txnrx (txnrx),
|
||||
.rst (rst),
|
||||
.clk (clk),
|
||||
.l_clk (l_clk),
|
||||
.adc_valid (adc_valid_s),
|
||||
.adc_data (adc_data_s),
|
||||
.adc_status (adc_status_s),
|
||||
.adc_r1_mode (adc_r1_mode),
|
||||
.adc_ddr_edgesel (adc_ddr_edgesel_s),
|
||||
.dac_valid (dac_valid_s),
|
||||
.dac_data (dac_data_s),
|
||||
.dac_clksel (dac_clksel_s),
|
||||
.dac_r1_mode (dac_r1_mode),
|
||||
.tdd_enable (tdd_enable_s),
|
||||
.tdd_txnrx (tdd_txnrx_s),
|
||||
.tdd_mode (tdd_mode_s),
|
||||
.mmcm_rst (mmcm_rst),
|
||||
.up_clk (up_clk),
|
||||
.up_rstn (up_rstn),
|
||||
.up_enable (up_enable),
|
||||
.up_txnrx (up_txnrx),
|
||||
.up_adc_dld (up_adc_dld_s[6:0]),
|
||||
.up_adc_dwdata (up_adc_dwdata_s[34:0]),
|
||||
.up_adc_drdata (up_adc_drdata_s[34:0]),
|
||||
.up_dac_dld (up_dac_dld_s[9:0]),
|
||||
.up_dac_dwdata (up_dac_dwdata_s[49:0]),
|
||||
.up_dac_drdata (up_dac_drdata_s[49:0]),
|
||||
.delay_clk (delay_clk),
|
||||
.delay_rst (delay_rst),
|
||||
.delay_locked (delay_locked_s),
|
||||
.up_drp_sel (up_drp_sel),
|
||||
.up_drp_wr (up_drp_wr),
|
||||
.up_drp_addr (up_drp_addr),
|
||||
.up_drp_wdata (up_drp_wdata),
|
||||
.up_drp_rdata (up_drp_rdata),
|
||||
.up_drp_ready (up_drp_ready),
|
||||
.up_drp_locked(up_drp_locked));
|
||||
end
|
||||
endgenerate
|
||||
|
||||
assign adc_valid_i0 = adc_valid_i0_int;
|
||||
assign adc_valid_q0 = adc_valid_q0_int;
|
||||
assign adc_valid_i1 = adc_valid_i1_int;
|
||||
assign adc_valid_q1 = adc_valid_q1_int;
|
||||
|
||||
always @(posedge clk) begin
|
||||
adc_valid_i0_int <= tdd_rx_valid_s & adc_valid_i0_s;
|
||||
adc_valid_q0_int <= tdd_rx_valid_s & adc_valid_q0_s;
|
||||
adc_valid_i1_int <= tdd_rx_valid_s & adc_valid_i1_s;
|
||||
adc_valid_q1_int <= tdd_rx_valid_s & adc_valid_q1_s;
|
||||
end
|
||||
|
||||
assign adc_data_i0 = adc_data_i0_int;
|
||||
assign adc_data_q0 = adc_data_q0_int;
|
||||
assign adc_data_i1 = adc_data_i1_int;
|
||||
assign adc_data_q1 = adc_data_q1_int;
|
||||
|
||||
always @(posedge clk) begin
|
||||
adc_data_i0_int <= adc_data_i0_s;
|
||||
adc_data_q0_int <= adc_data_q0_s;
|
||||
adc_data_i1_int <= adc_data_i1_s;
|
||||
adc_data_q1_int <= adc_data_q1_s;
|
||||
end
|
||||
|
||||
assign dac_valid_i0 = dac_valid_i0_int;
|
||||
assign dac_valid_q0 = dac_valid_q0_int;
|
||||
assign dac_valid_i1 = dac_valid_i1_int;
|
||||
assign dac_valid_q1 = dac_valid_q1_int;
|
||||
|
||||
always @(posedge clk) begin
|
||||
dac_valid_i0_int <= tdd_tx_valid_s & dac_valid_i0_s;
|
||||
dac_valid_q0_int <= tdd_tx_valid_s & dac_valid_q0_s;
|
||||
dac_valid_i1_int <= tdd_tx_valid_s & dac_valid_i1_s;
|
||||
dac_valid_q1_int <= tdd_tx_valid_s & dac_valid_q1_s;
|
||||
end
|
||||
|
||||
// tdd
|
||||
|
||||
generate
|
||||
if (TDD_DISABLE == 1) begin
|
||||
assign tdd_enable_s = 1'b0;
|
||||
assign tdd_txnrx_s = 1'b0;
|
||||
assign tdd_txnrx_s = 1'b0;
|
||||
assign tdd_mode_s = 1'b0;
|
||||
assign tdd_rx_vco_en_s = 1'b0;
|
||||
assign tdd_tx_vco_en_s = 1'b0;
|
||||
assign tdd_rx_rf_en_s = 1'b0;
|
||||
assign tdd_tx_rf_en_s = 1'b0;
|
||||
assign tdd_status_s = 8'd0;
|
||||
assign tdd_sync_cntr = 1'b0;
|
||||
assign tdd_tx_valid_s = 1'b1;
|
||||
assign tdd_rx_valid_s = 1'b1;
|
||||
assign up_wack_tdd_s = 1'b0;
|
||||
assign up_rack_tdd_s = 1'b0;
|
||||
assign up_rdata_tdd_s = 32'b0;
|
||||
assign dac_sync_enable = adc_valid_s;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate
|
||||
if (TDD_DISABLE == 0) begin
|
||||
axi_ad9361_tdd_if #(.LEVEL_OR_PULSE_N(1)) i_tdd_if (
|
||||
.clk (clk),
|
||||
.rst (rst),
|
||||
.tdd_rx_vco_en (tdd_rx_vco_en_s),
|
||||
.tdd_tx_vco_en (tdd_tx_vco_en_s),
|
||||
.tdd_rx_rf_en (tdd_rx_rf_en_s),
|
||||
.tdd_tx_rf_en (tdd_tx_rf_en_s),
|
||||
.ad9361_txnrx (tdd_txnrx_s),
|
||||
.ad9361_enable (tdd_enable_s),
|
||||
.ad9361_tdd_status (tdd_status_s));
|
||||
|
||||
axi_ad9361_tdd i_tdd (
|
||||
.clk (clk),
|
||||
.rst (rst),
|
||||
.tdd_rx_vco_en (tdd_rx_vco_en_s),
|
||||
.tdd_tx_vco_en (tdd_tx_vco_en_s),
|
||||
.tdd_rx_rf_en (tdd_rx_rf_en_s),
|
||||
.tdd_tx_rf_en (tdd_tx_rf_en_s),
|
||||
.tdd_enabled (tdd_mode_s),
|
||||
.tdd_status (tdd_status_s),
|
||||
.tdd_sync (tdd_sync),
|
||||
.tdd_sync_cntr (tdd_sync_cntr),
|
||||
.tdd_tx_valid (tdd_tx_valid_s),
|
||||
.tdd_rx_valid (tdd_rx_valid_s),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq_s),
|
||||
.up_waddr (up_waddr_s),
|
||||
.up_wdata (up_wdata_s),
|
||||
.up_wack (up_wack_tdd_s),
|
||||
.up_rreq (up_rreq_s),
|
||||
.up_raddr (up_raddr_s),
|
||||
.up_rdata (up_rdata_tdd_s),
|
||||
.up_rack (up_rack_tdd_s));
|
||||
|
||||
assign dac_sync_enable = adc_valid_s || tdd_mode_s;
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (PPS_RECEIVER_ENABLE == 1) begin
|
||||
// GPS's PPS receiver
|
||||
ad_pps_receiver i_pps_receiver (
|
||||
.clk (clk),
|
||||
.rst (rst),
|
||||
.gps_pps (gps_pps),
|
||||
.up_clk (up_clk),
|
||||
.up_rstn (up_rstn),
|
||||
.up_pps_rcounter (up_pps_rcounter_s),
|
||||
.up_pps_status (up_pps_status_s),
|
||||
.up_irq_mask (up_irq_mask_s),
|
||||
.up_irq (gps_pps_irq));
|
||||
assign up_irq_mask_s = adc_up_pps_irq_mask_s | dac_up_pps_irq_mask_s;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (PPS_RECEIVER_ENABLE == 0) begin
|
||||
assign up_pps_rcounter_s = 32'b0;
|
||||
assign up_pps_status_s = 1'b1;
|
||||
assign gps_pps_irq = 1'b0;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// receive
|
||||
|
||||
axi_ad9361_rx #(
|
||||
.ID (ID),
|
||||
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
|
||||
.FPGA_FAMILY (FPGA_FAMILY),
|
||||
.SPEED_GRADE (SPEED_GRADE),
|
||||
.DEV_PACKAGE (DEV_PACKAGE),
|
||||
.MODE_1R1T (MODE_1R1T),
|
||||
.CMOS_OR_LVDS_N (CMOS_OR_LVDS_N),
|
||||
.PPS_RECEIVER_ENABLE (PPS_RECEIVER_ENABLE),
|
||||
.INIT_DELAY (ADC_INIT_DELAY),
|
||||
.USERPORTS_DISABLE (ADC_USERPORTS_DISABLE_INT),
|
||||
.DATAFORMAT_DISABLE (ADC_DATAFORMAT_DISABLE_INT),
|
||||
.DCFILTER_DISABLE (ADC_DCFILTER_DISABLE_INT),
|
||||
.IQCORRECTION_DISABLE (ADC_IQCORRECTION_DISABLE_INT))
|
||||
i_rx (
|
||||
.mmcm_rst (mmcm_rst),
|
||||
.adc_rst (rst),
|
||||
.adc_clk (clk),
|
||||
|
||||
.adc_valid (adc_valid_s),
|
||||
.adc_data (adc_data_s),
|
||||
.adc_status (adc_status_s),
|
||||
.adc_r1_mode (adc_r1_mode),
|
||||
.adc_ddr_edgesel (adc_ddr_edgesel_s),
|
||||
.dac_data (dac_data_s),
|
||||
.up_dld (up_adc_dld_s),
|
||||
.up_dwdata (up_adc_dwdata_s),
|
||||
.up_drdata (up_adc_drdata_s),
|
||||
.delay_clk (delay_clk),
|
||||
.delay_rst (delay_rst),
|
||||
.delay_locked (delay_locked_s),
|
||||
.adc_enable_i0 (adc_enable_i0),
|
||||
.adc_valid_i0 (adc_valid_i0_s),
|
||||
.adc_data_i0 (adc_data_i0_s),
|
||||
.adc_enable_q0 (adc_enable_q0),
|
||||
.adc_valid_q0 (adc_valid_q0_s),
|
||||
.adc_data_q0 (adc_data_q0_s),
|
||||
.adc_enable_i1 (adc_enable_i1),
|
||||
.adc_valid_i1 (adc_valid_i1_s),
|
||||
.adc_data_i1 (adc_data_i1_s),
|
||||
.adc_enable_q1 (adc_enable_q1),
|
||||
.adc_valid_q1 (adc_valid_q1_s),
|
||||
.adc_data_q1 (adc_data_q1_s),
|
||||
.adc_dovf (adc_dovf),
|
||||
.up_adc_gpio_in (up_adc_gpio_in),
|
||||
.up_adc_gpio_out (up_adc_gpio_out),
|
||||
.up_pps_rcounter (up_pps_rcounter_s),
|
||||
.up_pps_status (up_pps_status_s),
|
||||
.up_pps_irq_mask (adc_up_pps_irq_mask_s),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq_s),
|
||||
.up_waddr (up_waddr_s),
|
||||
.up_wdata (up_wdata_s),
|
||||
.up_wack (up_wack_rx_s),
|
||||
.up_rreq (up_rreq_s),
|
||||
.up_raddr (up_raddr_s),
|
||||
.up_rdata (up_rdata_rx_s),
|
||||
.up_rack (up_rack_rx_s),
|
||||
.up_drp_sel (up_drp_sel),
|
||||
.up_drp_wr (up_drp_wr),
|
||||
.up_drp_addr (up_drp_addr),
|
||||
.up_drp_wdata (up_drp_wdata),
|
||||
.up_drp_rdata (up_drp_rdata),
|
||||
.up_drp_ready (up_drp_ready),
|
||||
.up_drp_locked(up_drp_locked));
|
||||
|
||||
// transmit
|
||||
|
||||
axi_ad9361_tx #(
|
||||
.ID (ID),
|
||||
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
|
||||
.FPGA_FAMILY (FPGA_FAMILY),
|
||||
.SPEED_GRADE (SPEED_GRADE),
|
||||
.DEV_PACKAGE (DEV_PACKAGE),
|
||||
.MODE_1R1T (MODE_1R1T),
|
||||
.CLK_EDGE_SEL (DAC_CLK_EDGE_SEL),
|
||||
.CMOS_OR_LVDS_N (CMOS_OR_LVDS_N),
|
||||
.PPS_RECEIVER_ENABLE (PPS_RECEIVER_ENABLE),
|
||||
.INIT_DELAY (DAC_INIT_DELAY),
|
||||
.DAC_DDS_DISABLE (DAC_DDS_DISABLE_INT),
|
||||
.DAC_DDS_TYPE (DAC_DDS_TYPE),
|
||||
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
|
||||
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
|
||||
.USERPORTS_DISABLE (DAC_USERPORTS_DISABLE_INT),
|
||||
.DELAYCNTRL_DISABLE (DAC_DELAYCNTRL_DISABLE_INT),
|
||||
.IQCORRECTION_DISABLE (DAC_IQCORRECTION_DISABLE_INT))
|
||||
i_tx (
|
||||
.dac_clk (clk),
|
||||
.dac_valid (dac_valid_s),
|
||||
.dac_data (dac_data_s),
|
||||
.dac_clksel (dac_clksel_s),
|
||||
.dac_r1_mode (dac_r1_mode),
|
||||
.adc_data (adc_data_s),
|
||||
.up_dld (up_dac_dld_s),
|
||||
.up_dwdata (up_dac_dwdata_s),
|
||||
.up_drdata (up_dac_drdata_s),
|
||||
.delay_clk (delay_clk),
|
||||
.delay_rst (),
|
||||
.delay_locked (delay_locked_s),
|
||||
.dac_sync_enable (dac_sync_enable),
|
||||
.dac_sync_in (dac_sync_in),
|
||||
.dac_sync_out (dac_sync_out),
|
||||
.dac_enable_i0 (dac_enable_i0),
|
||||
.dac_valid_i0 (dac_valid_i0_s),
|
||||
.dac_data_i0 (dac_data_i0),
|
||||
.dac_enable_q0 (dac_enable_q0),
|
||||
.dac_valid_q0 (dac_valid_q0_s),
|
||||
.dac_data_q0 (dac_data_q0),
|
||||
.dac_enable_i1 (dac_enable_i1),
|
||||
.dac_valid_i1 (dac_valid_i1_s),
|
||||
.dac_data_i1 (dac_data_i1),
|
||||
.dac_enable_q1 (dac_enable_q1),
|
||||
.dac_valid_q1 (dac_valid_q1_s),
|
||||
.dac_data_q1 (dac_data_q1),
|
||||
.dac_dunf(dac_dunf),
|
||||
.up_pps_rcounter (up_pps_rcounter_s),
|
||||
.up_pps_status (up_pps_status_s),
|
||||
.up_pps_irq_mask (dac_up_pps_irq_mask_s),
|
||||
.up_dac_gpio_in (up_dac_gpio_in),
|
||||
.up_dac_gpio_out (up_dac_gpio_out),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq_s),
|
||||
.up_waddr (up_waddr_s),
|
||||
.up_wdata (up_wdata_s),
|
||||
.up_wack (up_wack_tx_s),
|
||||
.up_rreq (up_rreq_s),
|
||||
.up_raddr (up_raddr_s),
|
||||
.up_rdata (up_rdata_tx_s),
|
||||
.up_rack (up_rack_tx_s));
|
||||
|
||||
// axi interface
|
||||
|
||||
up_axi i_up_axi (
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_axi_awvalid (s_axi_awvalid),
|
||||
.up_axi_awaddr (s_axi_awaddr),
|
||||
.up_axi_awready (s_axi_awready),
|
||||
.up_axi_wvalid (s_axi_wvalid),
|
||||
.up_axi_wdata (s_axi_wdata),
|
||||
.up_axi_wstrb (s_axi_wstrb),
|
||||
.up_axi_wready (s_axi_wready),
|
||||
.up_axi_bvalid (s_axi_bvalid),
|
||||
.up_axi_bresp (s_axi_bresp),
|
||||
.up_axi_bready (s_axi_bready),
|
||||
.up_axi_arvalid (s_axi_arvalid),
|
||||
.up_axi_araddr (s_axi_araddr),
|
||||
.up_axi_arready (s_axi_arready),
|
||||
.up_axi_rvalid (s_axi_rvalid),
|
||||
.up_axi_rresp (s_axi_rresp),
|
||||
.up_axi_rdata (s_axi_rdata),
|
||||
.up_axi_rready (s_axi_rready),
|
||||
.up_wreq (up_wreq_s),
|
||||
.up_waddr (up_waddr_s),
|
||||
.up_wdata (up_wdata_s),
|
||||
.up_wack (up_wack),
|
||||
.up_rreq (up_rreq_s),
|
||||
.up_raddr (up_raddr_s),
|
||||
.up_rdata (up_rdata),
|
||||
.up_rack (up_rack));
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
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// ***************************************************************************
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<Option Name="TopModule" Val="axi_ad9361"/>
|
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</File>
|
||||
<File Path="$PPRDIR/../xilinx/common/ad_rst_constr.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../xilinx/common/up_xfer_status_constr.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../xilinx/common/up_clock_mon_constr.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/axi_ad9361_constr.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="IES">
|
||||
<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Xcelium">
|
||||
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="VCS">
|
||||
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="10">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Vivado 12-1790"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="1"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="Evaluation"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="features"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="should"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="NOT"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="be"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="used"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="in"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="production"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="systems."/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Place 30-73"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="10"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="axi_spi"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val=""/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="11"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1343"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="2"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1306"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="3"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="ERROR"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1276"/>
|
||||
<MsgAttr Name="Severity" Val="CRITICAL WARNING"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="4"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-3656"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="5"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-4623"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="6"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-459"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="7"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Synth 8-3331"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="8"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Designutils 20-3303"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="9"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="HDPYFinalizeIO"/>
|
||||
</MsgRule>
|
||||
<Board/>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
<BootPmcSettings Version="1" Minor="0">
|
||||
<Parameters>
|
||||
<Parameter Name="PMC_CDO.ATTRS.LOADADDR" Value="" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_FB_CLK" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_FREQ" Value="300" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_BUS_WIDTH" Value="x1" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_DATA_MODE" Value="Single" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_FREQ" Value="200" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_SLOT_TYPE" Value="SD 2.0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_FREQ" Value="200" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_SLOT_TYPE" Value="SD 2.0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSPI_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSPI_FREQ" Value="300" Type="string"/>
|
||||
<Parameter Name="BOOT.USB_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SMAP_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SMAP_DATA_WIDTH" Value="32 Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSC_FREQ" Value="33.333" Type="string"/>
|
||||
<Parameter Name="BOOT.SECONDARY.PCIE_ENABLE" Value="0" Type="string"/>
|
||||
</Parameters>
|
||||
</BootPmcSettings>
|
||||
</Project>
|
||||
@@ -0,0 +1,7 @@
|
||||
|
||||
set_false_path -from [get_registers *i_dev_if|up_enable_int*] -to [get_registers *i_dev_if|enable_up_m1*]
|
||||
set_false_path -from [get_registers *i_dev_if|up_txnrx_int*] -to [get_registers *i_dev_if|txnrx_up_m1*]
|
||||
set_false_path -from [get_registers *up_xfer_cntrl:i_xfer_tdd_control|d_xfer_toggle*] -to [get_registers *up_xfer_cntrl:i_xfer_tdd_control|up_xfer_state_m1*]
|
||||
set_false_path -from [get_registers *up_xfer_cntrl:i_xfer_tdd_control|up_xfer_toggle*] -to [get_registers *up_xfer_cntrl:i_xfer_tdd_control|d_xfer_toggle_m1*]
|
||||
set_false_path -from [get_registers *up_xfer_cntrl:i_xfer_tdd_control|up_xfer_data*] -to [get_registers *up_xfer_cntrl:i_xfer_tdd_control|d_data_cntrl*]
|
||||
|
||||
@@ -0,0 +1,10 @@
|
||||
|
||||
set_property ASYNC_REG TRUE \
|
||||
[get_cells -hier *enable_up_*] \
|
||||
[get_cells -hier *txnrx_up_*] \
|
||||
[get_cells -hier *tdd_sync_d*]
|
||||
|
||||
set_false_path -from [get_cells -hier -filter {name =~ *up_enable_int_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *enable_up_m1_reg && IS_SEQUENTIAL}]
|
||||
set_false_path -from [get_cells -hier -filter {name =~ *up_txnrx_int_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *txnrx_up_m1_reg && IS_SEQUENTIAL}]
|
||||
set_false_path -quiet -to [get_cells -quiet -hier -filter {name =~ *tdd_sync_d1_reg && IS_SEQUENTIAL}]
|
||||
|
||||
@@ -0,0 +1,43 @@
|
||||
# report delays
|
||||
|
||||
set m_file [open "axi_ad9361_delay.log" w]
|
||||
set m_ios [get_ports -filter {NAME =~ rx_*_in*}]
|
||||
set m_ddr_ios [get_pins -hierarchical -filter {NAME =~ *i_rx_data_iddr/C || NAME =~ *i_rx_data_iddr/D}]
|
||||
set m_info [report_timing -no_header -return_string -from $m_ios -to $m_ddr_ios -max_paths 100]
|
||||
|
||||
set m_sources {}
|
||||
set m_string $m_info
|
||||
while {[regexp {\s+Source:\s+(.*?)\s+(.*)} $m_string m1 m_value m_string] == 1} {
|
||||
lappend m_sources $m_value
|
||||
}
|
||||
set m_destinations {}
|
||||
set m_string $m_info
|
||||
while {[regexp {\s+Destination:\s+(.*?)\s+(.*)} $m_string m1 m_value m_string] == 1} {
|
||||
lappend m_destinations $m_value
|
||||
}
|
||||
set m_delays {}
|
||||
set m_string $m_info
|
||||
while {[regexp {\s+Data\s+Path\s+Delay:\s+(.*?)\s+(.*)} $m_string m1 m_value m_string] == 1} {
|
||||
lappend m_delays $m_value
|
||||
}
|
||||
|
||||
set m_size [llength $m_sources]
|
||||
if {[llength $m_destinations] != $m_size} {
|
||||
puts "CRITICAL WARNING: axi_ad9361_delay.tcl, source-destination size mismatch"
|
||||
}
|
||||
if {[llength $m_delays] != $m_size} {
|
||||
puts "CRITICAL WARNING: axi_ad9361_delay.tcl, source-delay size mismatch"
|
||||
}
|
||||
|
||||
for {set m_index 0} {$m_index < $m_size} {incr m_index} {
|
||||
set m_delay [lindex $m_delays $m_index]
|
||||
set m_source [lindex $m_sources $m_index]
|
||||
set m_destination [lindex $m_destinations $m_index]
|
||||
puts "$m_source $m_destination $m_delay"
|
||||
puts $m_file "$m_source $m_destination $m_delay"
|
||||
}
|
||||
|
||||
puts $m_file "\nDetails:\n"
|
||||
puts $m_file $m_info
|
||||
close $m_file
|
||||
|
||||
@@ -0,0 +1,249 @@
|
||||
|
||||
package require qsys
|
||||
package require quartus::device
|
||||
|
||||
source ../scripts/adi_env.tcl
|
||||
source ../scripts/adi_ip_intel.tcl
|
||||
|
||||
ad_ip_create axi_ad9361 {AXI AD9361 Interface} axi_ad9361_elab
|
||||
set_module_property VALIDATION_CALLBACK info_param_validate
|
||||
|
||||
ad_ip_files axi_ad9361 [list\
|
||||
$ad_hdl_dir/library/intel/common/ad_mul.v \
|
||||
$ad_hdl_dir/library/intel/common/ad_dcfilter.v \
|
||||
$ad_hdl_dir/library/common/ad_rst.v \
|
||||
$ad_hdl_dir/library/common/ad_pnmon.v \
|
||||
$ad_hdl_dir/library/common/ad_dds_cordic_pipe.v \
|
||||
$ad_hdl_dir/library/common/ad_dds_sine_cordic.v \
|
||||
$ad_hdl_dir/library/common/ad_dds_sine.v \
|
||||
$ad_hdl_dir/library/common/ad_dds_2.v \
|
||||
$ad_hdl_dir/library/common/ad_dds_1.v \
|
||||
$ad_hdl_dir/library/common/ad_dds.v \
|
||||
$ad_hdl_dir/library/common/ad_datafmt.v \
|
||||
$ad_hdl_dir/library/common/ad_iqcor.v \
|
||||
$ad_hdl_dir/library/common/ad_addsub.v \
|
||||
$ad_hdl_dir/library/common/ad_tdd_control.v \
|
||||
$ad_hdl_dir/library/common/ad_pps_receiver.v \
|
||||
$ad_hdl_dir/library/common/up_axi.v \
|
||||
$ad_hdl_dir/library/common/up_xfer_cntrl.v \
|
||||
$ad_hdl_dir/library/common/up_xfer_status.v \
|
||||
$ad_hdl_dir/library/common/up_clock_mon.v \
|
||||
$ad_hdl_dir/library/common/up_delay_cntrl.v \
|
||||
$ad_hdl_dir/library/common/up_adc_common.v \
|
||||
$ad_hdl_dir/library/common/up_adc_channel.v \
|
||||
$ad_hdl_dir/library/common/up_dac_common.v \
|
||||
$ad_hdl_dir/library/common/up_dac_channel.v \
|
||||
$ad_hdl_dir/library/common/up_tdd_cntrl.v \
|
||||
intel/axi_ad9361_lvds_if_10.v \
|
||||
intel/axi_ad9361_lvds_if_c5.v \
|
||||
intel/axi_ad9361_lvds_if.v \
|
||||
intel/axi_ad9361_cmos_if.v \
|
||||
axi_ad9361_rx_pnmon.v \
|
||||
axi_ad9361_rx_channel.v \
|
||||
axi_ad9361_rx.v \
|
||||
axi_ad9361_tx_channel.v \
|
||||
axi_ad9361_tx.v \
|
||||
axi_ad9361_tdd.v \
|
||||
axi_ad9361_tdd_if.v \
|
||||
axi_ad9361.v \
|
||||
$ad_hdl_dir/library/intel/common/up_xfer_cntrl_constr.sdc \
|
||||
$ad_hdl_dir/library/intel/common/up_xfer_status_constr.sdc \
|
||||
$ad_hdl_dir/library/intel/common/up_clock_mon_constr.sdc \
|
||||
$ad_hdl_dir/library/intel/common/up_rst_constr.sdc \
|
||||
axi_ad9361_constr.sdc]
|
||||
|
||||
# parameters
|
||||
|
||||
ad_ip_parameter ID INTEGER 0
|
||||
ad_ip_parameter MODE_1R1T INTEGER 0
|
||||
ad_ip_parameter TDD_DISABLE INTEGER 0
|
||||
ad_ip_parameter CMOS_OR_LVDS_N INTEGER 0
|
||||
ad_ip_parameter ADC_DATAPATH_DISABLE INTEGER 0
|
||||
ad_ip_parameter ADC_USERPORTS_DISABLE INTEGER 0
|
||||
ad_ip_parameter ADC_DATAFORMAT_DISABLE INTEGER 0
|
||||
ad_ip_parameter ADC_DCFILTER_DISABLE INTEGER 0
|
||||
ad_ip_parameter ADC_IQCORRECTION_DISABLE INTEGER 0
|
||||
ad_ip_parameter DAC_IODELAY_ENABLE INTEGER 0
|
||||
ad_ip_parameter DAC_DATAPATH_DISABLE INTEGER 0
|
||||
ad_ip_parameter DAC_DDS_DISABLE INTEGER 0
|
||||
ad_ip_parameter DAC_USERPORTS_DISABLE INTEGER 0
|
||||
ad_ip_parameter DAC_IQCORRECTION_DISABLE INTEGER 0
|
||||
ad_ip_parameter IO_DELAY_GROUP STRING {dev_if_delay_group}
|
||||
ad_ip_parameter MIMO_ENABLE INTEGER 0
|
||||
ad_ip_parameter RX_NODPA INTEGER 0
|
||||
|
||||
adi_add_auto_fpga_spec_params
|
||||
|
||||
# interfaces
|
||||
|
||||
ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn
|
||||
|
||||
ad_interface signal dac_sync_in input 1
|
||||
ad_interface signal dac_sync_out output 1
|
||||
ad_interface signal tdd_sync input 1
|
||||
ad_interface signal tdd_sync_cntr output 1
|
||||
|
||||
ad_interface clock delay_clk input 1
|
||||
ad_interface clock l_clk output 1
|
||||
ad_interface clock clk input 1
|
||||
|
||||
ad_interface reset rst output 1 if_clk
|
||||
set_interface_property if_rst associatedResetSinks s_axi_reset
|
||||
|
||||
add_interface adc_ch_0 conduit end
|
||||
add_interface_port adc_ch_0 adc_enable_i0 enable Output 1
|
||||
add_interface_port adc_ch_0 adc_valid_i0 valid Output 1
|
||||
add_interface_port adc_ch_0 adc_data_i0 data Output 16
|
||||
|
||||
set_interface_property adc_ch_0 associatedClock if_clk
|
||||
set_interface_property adc_ch_0 associatedReset none
|
||||
|
||||
add_interface adc_ch_1 conduit end
|
||||
add_interface_port adc_ch_1 adc_enable_q0 enable Output 1
|
||||
add_interface_port adc_ch_1 adc_valid_q0 valid Output 1
|
||||
add_interface_port adc_ch_1 adc_data_q0 data Output 16
|
||||
|
||||
set_interface_property adc_ch_1 associatedClock if_clk
|
||||
set_interface_property adc_ch_1 associatedReset none
|
||||
|
||||
add_interface adc_ch_2 conduit end
|
||||
add_interface_port adc_ch_2 adc_enable_i1 enable Output 1
|
||||
add_interface_port adc_ch_2 adc_valid_i1 valid Output 1
|
||||
add_interface_port adc_ch_2 adc_data_i1 data Output 16
|
||||
|
||||
set_interface_property adc_ch_2 associatedClock if_clk
|
||||
set_interface_property adc_ch_2 associatedReset none
|
||||
|
||||
add_interface adc_ch_3 conduit end
|
||||
add_interface_port adc_ch_3 adc_enable_q1 enable Output 1
|
||||
add_interface_port adc_ch_3 adc_valid_q1 valid Output 1
|
||||
add_interface_port adc_ch_3 adc_data_q1 data Output 16
|
||||
|
||||
set_interface_property adc_ch_3 associatedClock if_clk
|
||||
set_interface_property adc_ch_3 associatedReset none
|
||||
|
||||
ad_interface signal adc_dovf input 1 ovf
|
||||
ad_interface signal adc_r1_mode output 1 r1_mode
|
||||
|
||||
add_interface dac_ch_0 conduit end
|
||||
add_interface_port dac_ch_0 dac_enable_i0 enable Output 1
|
||||
add_interface_port dac_ch_0 dac_valid_i0 valid Output 1
|
||||
add_interface_port dac_ch_0 dac_data_i0 data Input 16
|
||||
|
||||
set_interface_property dac_ch_0 associatedClock if_clk
|
||||
set_interface_property dac_ch_0 associatedReset none
|
||||
|
||||
add_interface dac_ch_1 conduit end
|
||||
add_interface_port dac_ch_1 dac_enable_q0 enable Output 1
|
||||
add_interface_port dac_ch_1 dac_valid_q0 valid Output 1
|
||||
add_interface_port dac_ch_1 dac_data_q0 data Input 16
|
||||
|
||||
set_interface_property dac_ch_1 associatedClock if_clk
|
||||
set_interface_property dac_ch_1 associatedReset none
|
||||
|
||||
add_interface dac_ch_2 conduit end
|
||||
add_interface_port dac_ch_2 dac_enable_i1 enable Output 1
|
||||
add_interface_port dac_ch_2 dac_valid_i1 valid Output 1
|
||||
add_interface_port dac_ch_2 dac_data_i1 data Input 16
|
||||
|
||||
set_interface_property dac_ch_2 associatedClock if_clk
|
||||
set_interface_property dac_ch_2 associatedReset none
|
||||
|
||||
add_interface dac_ch_3 conduit end
|
||||
add_interface_port dac_ch_3 dac_enable_q1 enable Output 1
|
||||
add_interface_port dac_ch_3 dac_valid_q1 valid Output 1
|
||||
add_interface_port dac_ch_3 dac_data_q1 data Input 16
|
||||
|
||||
set_interface_property dac_ch_3 associatedClock if_clk
|
||||
set_interface_property dac_ch_3 associatedReset none
|
||||
|
||||
ad_interface signal dac_dunf input 1 unf
|
||||
ad_interface signal dac_r1_mode output 1 r1_mode
|
||||
|
||||
ad_interface signal up_enable input 1
|
||||
ad_interface signal up_txnrx input 1
|
||||
ad_interface signal up_dac_gpio_in input 32
|
||||
ad_interface signal up_dac_gpio_out output 32
|
||||
ad_interface signal up_adc_gpio_in input 32
|
||||
ad_interface signal up_adc_gpio_out output 32
|
||||
|
||||
# updates
|
||||
|
||||
proc axi_ad9361_elab {} {
|
||||
|
||||
set m_fpga_technology [get_parameter_value "FPGA_TECHNOLOGY"]
|
||||
set m_cmos_or_lvds_n [get_parameter_value "CMOS_OR_LVDS_N"]
|
||||
set rx_nodpa [get_parameter_value "RX_NODPA"]
|
||||
|
||||
# 103 - stands for "Arria 10" see adi_intel_device_info_enc.tcl
|
||||
if {$m_fpga_technology == 103} {
|
||||
|
||||
add_hdl_instance axi_ad9361_serdes_clk intel_serdes 1.0
|
||||
set_instance_parameter_value axi_ad9361_serdes_clk {DEVICE_FAMILY} {Arria 10}
|
||||
set_instance_parameter_value axi_ad9361_serdes_clk {MODE} {CLK}
|
||||
set_instance_parameter_value axi_ad9361_serdes_clk {DDR_OR_SDR_N} {1}
|
||||
set_instance_parameter_value axi_ad9361_serdes_clk {SERDES_FACTOR} {4}
|
||||
set_instance_parameter_value axi_ad9361_serdes_clk {CLKIN_FREQUENCY} {250.0}
|
||||
|
||||
set rx_serdes_mode IN
|
||||
if {$rx_nodpa == 1} {set rx_serdes_mode IN_NODPA}
|
||||
|
||||
add_hdl_instance axi_ad9361_serdes_in intel_serdes 1.0
|
||||
set_instance_parameter_value axi_ad9361_serdes_in {DEVICE_FAMILY} {Arria 10}
|
||||
set_instance_parameter_value axi_ad9361_serdes_in {MODE} $rx_serdes_mode
|
||||
set_instance_parameter_value axi_ad9361_serdes_in {DDR_OR_SDR_N} {1}
|
||||
set_instance_parameter_value axi_ad9361_serdes_in {SERDES_FACTOR} {4}
|
||||
set_instance_parameter_value axi_ad9361_serdes_in {CLKIN_FREQUENCY} {250.0}
|
||||
|
||||
add_hdl_instance axi_ad9361_serdes_out intel_serdes 1.0
|
||||
set_instance_parameter_value axi_ad9361_serdes_out {DEVICE_FAMILY} {Arria 10}
|
||||
set_instance_parameter_value axi_ad9361_serdes_out {MODE} {OUT}
|
||||
set_instance_parameter_value axi_ad9361_serdes_out {DDR_OR_SDR_N} {1}
|
||||
set_instance_parameter_value axi_ad9361_serdes_out {SERDES_FACTOR} {4}
|
||||
set_instance_parameter_value axi_ad9361_serdes_out {CLKIN_FREQUENCY} {250.0}
|
||||
|
||||
add_hdl_instance axi_ad9361_data_out altera_gpio 19.1
|
||||
set_instance_parameter_value axi_ad9361_data_out {DEVICE_FAMILY} {Arria 10}
|
||||
set_instance_parameter_value axi_ad9361_data_out {PIN_TYPE_GUI} {Output}
|
||||
set_instance_parameter_value axi_ad9361_data_out {SIZE} {1}
|
||||
set_instance_parameter_value axi_ad9361_data_out {gui_io_reg_mode} {DDIO}
|
||||
|
||||
add_hdl_instance clk_buffer altclkctrl 19.1
|
||||
set_instance_parameter_value clk_buffer {DEVICE_FAMILY} {Arria 10}
|
||||
|
||||
}
|
||||
|
||||
add_interface device_if conduit end
|
||||
set_interface_property device_if associatedClock none
|
||||
set_interface_property device_if associatedReset none
|
||||
|
||||
if {$m_cmos_or_lvds_n == 1} {
|
||||
|
||||
add_interface_port device_if rx_clk_in rx_clk_in Input 1
|
||||
add_interface_port device_if rx_frame_in rx_frame_in Input 1
|
||||
add_interface_port device_if rx_data_in rx_data_in Input 12
|
||||
add_interface_port device_if tx_clk_out tx_clk_out Output 1
|
||||
add_interface_port device_if tx_frame_out tx_frame_out Output 1
|
||||
add_interface_port device_if tx_data_out tx_data_out Output 12
|
||||
}
|
||||
|
||||
if {$m_cmos_or_lvds_n == 0} {
|
||||
|
||||
add_interface_port device_if rx_clk_in_p rx_clk_in_p Input 1
|
||||
add_interface_port device_if rx_clk_in_n rx_clk_in_n Input 1
|
||||
add_interface_port device_if rx_frame_in_p rx_frame_in_p Input 1
|
||||
add_interface_port device_if rx_frame_in_n rx_frame_in_n Input 1
|
||||
add_interface_port device_if rx_data_in_p rx_data_in_p Input 6
|
||||
add_interface_port device_if rx_data_in_n rx_data_in_n Input 6
|
||||
add_interface_port device_if tx_clk_out_p tx_clk_out_p Output 1
|
||||
add_interface_port device_if tx_clk_out_n tx_clk_out_n Output 1
|
||||
add_interface_port device_if tx_frame_out_p tx_frame_out_p Output 1
|
||||
add_interface_port device_if tx_frame_out_n tx_frame_out_n Output 1
|
||||
add_interface_port device_if tx_data_out_p tx_data_out_p Output 6
|
||||
add_interface_port device_if tx_data_out_n tx_data_out_n Output 6
|
||||
}
|
||||
|
||||
add_interface_port device_if enable enable Output 1
|
||||
add_interface_port device_if txnrx txnrx Output 1
|
||||
}
|
||||
|
||||
@@ -0,0 +1,111 @@
|
||||
# ip
|
||||
|
||||
source ../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
|
||||
adi_ip_create axi_ad9361
|
||||
adi_ip_files axi_ad9361 [list \
|
||||
"$ad_hdl_dir/library/common/ad_rst.v" \
|
||||
"$ad_hdl_dir/library/xilinx/common/ad_data_clk.v" \
|
||||
"$ad_hdl_dir/library/xilinx/common/ad_data_in.v" \
|
||||
"$ad_hdl_dir/library/xilinx/common/ad_data_out.v" \
|
||||
"$ad_hdl_dir/library/xilinx/common/ad_dcfilter.v" \
|
||||
"$ad_hdl_dir/library/xilinx/common/ad_mul.v" \
|
||||
"$ad_hdl_dir/library/common/ad_pnmon.v" \
|
||||
"$ad_hdl_dir/library/common/ad_dds_cordic_pipe.v" \
|
||||
"$ad_hdl_dir/library/common/ad_dds_sine_cordic.v" \
|
||||
"$ad_hdl_dir/library/common/ad_dds_sine.v" \
|
||||
"$ad_hdl_dir/library/common/ad_dds_2.v" \
|
||||
"$ad_hdl_dir/library/common/ad_dds_1.v" \
|
||||
"$ad_hdl_dir/library/common/ad_dds.v" \
|
||||
"$ad_hdl_dir/library/common/ad_datafmt.v" \
|
||||
"$ad_hdl_dir/library/common/ad_iqcor.v" \
|
||||
"$ad_hdl_dir/library/common/ad_addsub.v" \
|
||||
"$ad_hdl_dir/library/common/ad_tdd_control.v" \
|
||||
"$ad_hdl_dir/library/common/ad_pps_receiver.v" \
|
||||
"$ad_hdl_dir/library/common/up_axi.v" \
|
||||
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
|
||||
"$ad_hdl_dir/library/common/up_xfer_status.v" \
|
||||
"$ad_hdl_dir/library/common/up_clock_mon.v" \
|
||||
"$ad_hdl_dir/library/common/up_delay_cntrl.v" \
|
||||
"$ad_hdl_dir/library/common/up_adc_common.v" \
|
||||
"$ad_hdl_dir/library/common/up_adc_channel.v" \
|
||||
"$ad_hdl_dir/library/common/up_dac_common.v" \
|
||||
"$ad_hdl_dir/library/common/up_dac_channel.v" \
|
||||
"$ad_hdl_dir/library/common/up_tdd_cntrl.v" \
|
||||
"$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \
|
||||
"$ad_hdl_dir/library/common/ad_pps_receiver_constr.ttcl" \
|
||||
"$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \
|
||||
"$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \
|
||||
"$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \
|
||||
"axi_ad9361_constr.xdc" \
|
||||
"xilinx/axi_ad9361_lvds_if.v" \
|
||||
"xilinx/axi_ad9361_cmos_if.v" \
|
||||
"axi_ad9361_rx_pnmon.v" \
|
||||
"axi_ad9361_rx_channel.v" \
|
||||
"axi_ad9361_rx.v" \
|
||||
"axi_ad9361_tx_channel.v" \
|
||||
"axi_ad9361_tx.v" \
|
||||
"axi_ad9361_tdd.v" \
|
||||
"axi_ad9361_tdd_if.v" \
|
||||
"axi_ad9361.v" ]
|
||||
|
||||
adi_ip_properties axi_ad9361
|
||||
adi_ip_ttcl axi_ad9361 "../common/ad_pps_receiver_constr.ttcl"
|
||||
|
||||
adi_init_bd_tcl
|
||||
adi_ip_bd axi_ad9361 "bd/bd.tcl"
|
||||
|
||||
set_property driver_value 0 [ipx::get_ports *rx_clk_in* -of_objects [ipx::current_core]]
|
||||
set_property driver_value 0 [ipx::get_ports *rx_frame_in* -of_objects [ipx::current_core]]
|
||||
set_property driver_value 0 [ipx::get_ports *rx_data_in* -of_objects [ipx::current_core]]
|
||||
set_property driver_value 0 [ipx::get_ports *dac_sync_in* -of_objects [ipx::current_core]]
|
||||
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
|
||||
set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
|
||||
set_property driver_value 0 [ipx::get_ports *gpio_in* -of_objects [ipx::current_core]]
|
||||
set_property driver_value 0 [ipx::get_ports *gps_pps* -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.CMOS_OR_LVDS_N')) == 0} \
|
||||
[ipx::get_ports rx_clk_in_p -of_objects [ipx::current_core]] \
|
||||
[ipx::get_ports rx_clk_in_n -of_objects [ipx::current_core]] \
|
||||
[ipx::get_ports rx_frame_in_p -of_objects [ipx::current_core]] \
|
||||
[ipx::get_ports rx_frame_in_n -of_objects [ipx::current_core]] \
|
||||
[ipx::get_ports rx_data_in_p -of_objects [ipx::current_core]] \
|
||||
[ipx::get_ports rx_data_in_n -of_objects [ipx::current_core]] \
|
||||
[ipx::get_ports tx_clk_out_p -of_objects [ipx::current_core]] \
|
||||
[ipx::get_ports tx_clk_out_n -of_objects [ipx::current_core]] \
|
||||
[ipx::get_ports tx_frame_out_p -of_objects [ipx::current_core]] \
|
||||
[ipx::get_ports tx_frame_out_n -of_objects [ipx::current_core]] \
|
||||
[ipx::get_ports tx_data_out_p -of_objects [ipx::current_core]] \
|
||||
[ipx::get_ports tx_data_out_n -of_objects [ipx::current_core]]
|
||||
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.CMOS_OR_LVDS_N')) == 1} \
|
||||
[ipx::get_ports rx_clk_in -of_objects [ipx::current_core]] \
|
||||
[ipx::get_ports rx_frame_in -of_objects [ipx::current_core]] \
|
||||
[ipx::get_ports rx_data_in -of_objects [ipx::current_core]] \
|
||||
[ipx::get_ports tx_clk_out -of_objects [ipx::current_core]] \
|
||||
[ipx::get_ports tx_frame_out -of_objects [ipx::current_core]] \
|
||||
[ipx::get_ports tx_data_out -of_objects [ipx::current_core]]
|
||||
|
||||
ipx::add_bus_parameter ASSOCIATED_BUSIF [ipx::get_bus_interfaces s_axi_aclk \
|
||||
-of_objects [ipx::current_core]]
|
||||
set_property value s_axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \
|
||||
-of_objects [ipx::get_bus_interfaces s_axi_aclk \
|
||||
-of_objects [ipx::current_core]]]
|
||||
|
||||
ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
ipx::infer_bus_interface l_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
ipx::infer_bus_interface delay_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
set reset_intf [ipx::infer_bus_interface rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]]
|
||||
set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_intf]
|
||||
set_property value "ACTIVE_HIGH" $reset_polarity
|
||||
|
||||
ipx::infer_bus_interface gps_pps_irq xilinx.com:signal:interrupt_rtl:1.0 [ipx::current_core]
|
||||
|
||||
ipgui::remove_param -component [ipx::current_core] [ipgui::get_guiparamspec -name "RX_NODPA" -component [ipx::current_core]]
|
||||
|
||||
adi_add_auto_fpga_spec_params
|
||||
ipx::create_xgui_files [ipx::current_core]
|
||||
|
||||
ipx::save_core [ipx::current_core]
|
||||
|
||||
@@ -0,0 +1,423 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// ADC channel-need to work on dual mode for pn sequence
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module axi_ad9361_rx #(
|
||||
|
||||
// parameters
|
||||
|
||||
parameter ID = 0,
|
||||
parameter FPGA_TECHNOLOGY = 0,
|
||||
parameter FPGA_FAMILY = 0,
|
||||
parameter SPEED_GRADE = 0,
|
||||
parameter DEV_PACKAGE = 0,
|
||||
parameter MODE_1R1T = 0,
|
||||
parameter CMOS_OR_LVDS_N = 0,
|
||||
parameter PPS_RECEIVER_ENABLE = 0,
|
||||
parameter INIT_DELAY = 0,
|
||||
parameter USERPORTS_DISABLE = 0,
|
||||
parameter DATAFORMAT_DISABLE = 0,
|
||||
parameter DCFILTER_DISABLE = 0,
|
||||
parameter IQCORRECTION_DISABLE = 0) (
|
||||
|
||||
// common
|
||||
|
||||
output mmcm_rst,
|
||||
|
||||
// adc interface
|
||||
|
||||
output adc_rst,
|
||||
input adc_clk,
|
||||
input adc_valid,
|
||||
input [47:0] adc_data,
|
||||
input adc_status,
|
||||
output adc_r1_mode,
|
||||
output adc_ddr_edgesel,
|
||||
input [47:0] dac_data,
|
||||
|
||||
// delay interface
|
||||
|
||||
output [12:0] up_dld,
|
||||
output [64:0] up_dwdata,
|
||||
input [64:0] up_drdata,
|
||||
input delay_clk,
|
||||
output delay_rst,
|
||||
input delay_locked,
|
||||
|
||||
// dma interface
|
||||
|
||||
output adc_enable_i0,
|
||||
output adc_valid_i0,
|
||||
output [15:0] adc_data_i0,
|
||||
output adc_enable_q0,
|
||||
output adc_valid_q0,
|
||||
output [15:0] adc_data_q0,
|
||||
output adc_enable_i1,
|
||||
output adc_valid_i1,
|
||||
output [15:0] adc_data_i1,
|
||||
output adc_enable_q1,
|
||||
output adc_valid_q1,
|
||||
output [15:0] adc_data_q1,
|
||||
input adc_dovf,
|
||||
|
||||
// gpio
|
||||
|
||||
input [31:0] up_adc_gpio_in,
|
||||
output [31:0] up_adc_gpio_out,
|
||||
|
||||
// 1PPS reporting counter and interrupt
|
||||
|
||||
input [31:0] up_pps_rcounter,
|
||||
input up_pps_status,
|
||||
output up_pps_irq_mask,
|
||||
|
||||
// processor interface
|
||||
|
||||
input up_rstn,
|
||||
input up_clk,
|
||||
input up_wreq,
|
||||
input [13:0] up_waddr,
|
||||
input [31:0] up_wdata,
|
||||
output up_wack,
|
||||
input up_rreq,
|
||||
input [13:0] up_raddr,
|
||||
output [31:0] up_rdata,
|
||||
output up_rack,
|
||||
|
||||
// drp interface
|
||||
|
||||
output up_drp_sel,
|
||||
output up_drp_wr,
|
||||
output [11:0] up_drp_addr,
|
||||
output [31:0] up_drp_wdata,
|
||||
input [31:0] up_drp_rdata,
|
||||
input up_drp_ready,
|
||||
input up_drp_locked);
|
||||
|
||||
// configuration settings
|
||||
|
||||
localparam CONFIG = (PPS_RECEIVER_ENABLE * 256) +
|
||||
(CMOS_OR_LVDS_N * 128) +
|
||||
(MODE_1R1T * 16) +
|
||||
(USERPORTS_DISABLE * 8) +
|
||||
(DATAFORMAT_DISABLE * 4) +
|
||||
(DCFILTER_DISABLE * 2) +
|
||||
(IQCORRECTION_DISABLE * 1);
|
||||
|
||||
// internal registers
|
||||
|
||||
reg up_status_pn_err = 'd0;
|
||||
reg up_status_pn_oos = 'd0;
|
||||
reg up_status_or = 'd0;
|
||||
reg [31:0] up_rdata_int = 'd0;
|
||||
reg up_rack_int = 'd0;
|
||||
reg up_wack_int = 'd0;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire [15:0] adc_dcfilter_data_out_0_s;
|
||||
wire [15:0] adc_dcfilter_data_out_1_s;
|
||||
wire [15:0] adc_dcfilter_data_out_2_s;
|
||||
wire [15:0] adc_dcfilter_data_out_3_s;
|
||||
wire [ 3:0] up_adc_pn_err_s;
|
||||
wire [ 3:0] up_adc_pn_oos_s;
|
||||
wire [ 3:0] up_adc_or_s;
|
||||
wire [31:0] up_rdata_s[0:5];
|
||||
wire [ 5:0] up_rack_s;
|
||||
wire [ 5:0] up_wack_s;
|
||||
|
||||
// processor read interface
|
||||
|
||||
assign up_wack = up_wack_int;
|
||||
assign up_rack = up_rack_int;
|
||||
assign up_rdata = up_rdata_int;
|
||||
|
||||
always @(negedge up_rstn or posedge up_clk) begin
|
||||
if (up_rstn == 0) begin
|
||||
up_status_pn_err <= 'd0;
|
||||
up_status_pn_oos <= 'd0;
|
||||
up_status_or <= 'd0;
|
||||
up_rdata_int <= 'd0;
|
||||
up_rack_int <= 'd0;
|
||||
up_wack_int <= 'd0;
|
||||
end else begin
|
||||
up_status_pn_err <= | up_adc_pn_err_s;
|
||||
up_status_pn_oos <= | up_adc_pn_oos_s;
|
||||
up_status_or <= | up_adc_or_s;
|
||||
up_rdata_int <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] |
|
||||
up_rdata_s[3] | up_rdata_s[4] | up_rdata_s[5];
|
||||
up_rack_int <= | up_rack_s;
|
||||
up_wack_int <= | up_wack_s;
|
||||
end
|
||||
end
|
||||
|
||||
// channel 0 (i)
|
||||
|
||||
axi_ad9361_rx_channel #(
|
||||
.Q_OR_I_N (0),
|
||||
.CHANNEL_ID (0),
|
||||
.DISABLE (0),
|
||||
.USERPORTS_DISABLE (USERPORTS_DISABLE),
|
||||
.DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
|
||||
.DCFILTER_DISABLE (DCFILTER_DISABLE),
|
||||
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE))
|
||||
i_rx_channel_0 (
|
||||
.adc_clk (adc_clk),
|
||||
.adc_rst (adc_rst),
|
||||
.adc_valid (adc_valid),
|
||||
.adc_data (adc_data[11:0]),
|
||||
.adc_data_q (adc_data[23:12]),
|
||||
.adc_or (1'b0),
|
||||
.dac_data (dac_data[11:0]),
|
||||
.adc_dcfilter_data_out (adc_dcfilter_data_out_0_s),
|
||||
.adc_dcfilter_data_in (adc_dcfilter_data_out_1_s),
|
||||
.adc_iqcor_valid (adc_valid_i0),
|
||||
.adc_iqcor_data (adc_data_i0),
|
||||
.adc_enable (adc_enable_i0),
|
||||
.up_adc_pn_err (up_adc_pn_err_s[0]),
|
||||
.up_adc_pn_oos (up_adc_pn_oos_s[0]),
|
||||
.up_adc_or (up_adc_or_s[0]),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq),
|
||||
.up_waddr (up_waddr),
|
||||
.up_wdata (up_wdata),
|
||||
.up_wack (up_wack_s[0]),
|
||||
.up_rreq (up_rreq),
|
||||
.up_raddr (up_raddr),
|
||||
.up_rdata (up_rdata_s[0]),
|
||||
.up_rack (up_rack_s[0]));
|
||||
|
||||
// channel 1 (q)
|
||||
|
||||
axi_ad9361_rx_channel #(
|
||||
.Q_OR_I_N (1),
|
||||
.CHANNEL_ID (1),
|
||||
.DISABLE (0),
|
||||
.USERPORTS_DISABLE (USERPORTS_DISABLE),
|
||||
.DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
|
||||
.DCFILTER_DISABLE (DCFILTER_DISABLE),
|
||||
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE))
|
||||
i_rx_channel_1 (
|
||||
.adc_clk (adc_clk),
|
||||
.adc_rst (adc_rst),
|
||||
.adc_valid (adc_valid),
|
||||
.adc_data (adc_data[23:12]),
|
||||
.adc_data_q (adc_data[11:0]),
|
||||
.adc_or (1'b0),
|
||||
.dac_data (dac_data[23:12]),
|
||||
.adc_dcfilter_data_out (adc_dcfilter_data_out_1_s),
|
||||
.adc_dcfilter_data_in (adc_dcfilter_data_out_0_s),
|
||||
.adc_iqcor_valid (adc_valid_q0),
|
||||
.adc_iqcor_data (adc_data_q0),
|
||||
.adc_enable (adc_enable_q0),
|
||||
.up_adc_pn_err (up_adc_pn_err_s[1]),
|
||||
.up_adc_pn_oos (up_adc_pn_oos_s[1]),
|
||||
.up_adc_or (up_adc_or_s[1]),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq),
|
||||
.up_waddr (up_waddr),
|
||||
.up_wdata (up_wdata),
|
||||
.up_wack (up_wack_s[1]),
|
||||
.up_rreq (up_rreq),
|
||||
.up_raddr (up_raddr),
|
||||
.up_rdata (up_rdata_s[1]),
|
||||
.up_rack (up_rack_s[1]));
|
||||
|
||||
// channel 2 (i)
|
||||
|
||||
axi_ad9361_rx_channel #(
|
||||
.Q_OR_I_N (0),
|
||||
.CHANNEL_ID (2),
|
||||
.DISABLE (MODE_1R1T),
|
||||
.USERPORTS_DISABLE (USERPORTS_DISABLE),
|
||||
.DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
|
||||
.DCFILTER_DISABLE (DCFILTER_DISABLE),
|
||||
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE))
|
||||
i_rx_channel_2 (
|
||||
.adc_clk (adc_clk),
|
||||
.adc_rst (adc_rst),
|
||||
.adc_valid (adc_valid),
|
||||
.adc_data (adc_data[35:24]),
|
||||
.adc_data_q (adc_data[47:36]),
|
||||
.adc_or (1'b0),
|
||||
.dac_data (dac_data[35:24]),
|
||||
.adc_dcfilter_data_out (adc_dcfilter_data_out_2_s),
|
||||
.adc_dcfilter_data_in (adc_dcfilter_data_out_3_s),
|
||||
.adc_iqcor_valid (adc_valid_i1),
|
||||
.adc_iqcor_data (adc_data_i1),
|
||||
.adc_enable (adc_enable_i1),
|
||||
.up_adc_pn_err (up_adc_pn_err_s[2]),
|
||||
.up_adc_pn_oos (up_adc_pn_oos_s[2]),
|
||||
.up_adc_or (up_adc_or_s[2]),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq),
|
||||
.up_waddr (up_waddr),
|
||||
.up_wdata (up_wdata),
|
||||
.up_wack (up_wack_s[2]),
|
||||
.up_rreq (up_rreq),
|
||||
.up_raddr (up_raddr),
|
||||
.up_rdata (up_rdata_s[2]),
|
||||
.up_rack (up_rack_s[2]));
|
||||
|
||||
// channel 3 (q)
|
||||
|
||||
axi_ad9361_rx_channel #(
|
||||
.Q_OR_I_N (1),
|
||||
.CHANNEL_ID (3),
|
||||
.DISABLE (MODE_1R1T),
|
||||
.USERPORTS_DISABLE (USERPORTS_DISABLE),
|
||||
.DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
|
||||
.DCFILTER_DISABLE (DCFILTER_DISABLE),
|
||||
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE))
|
||||
i_rx_channel_3 (
|
||||
.adc_clk (adc_clk),
|
||||
.adc_rst (adc_rst),
|
||||
.adc_valid (adc_valid),
|
||||
.adc_data (adc_data[47:36]),
|
||||
.adc_data_q (adc_data[35:24]),
|
||||
.adc_or (1'b0),
|
||||
.dac_data (dac_data[47:36]),
|
||||
.adc_dcfilter_data_out (adc_dcfilter_data_out_3_s),
|
||||
.adc_dcfilter_data_in (adc_dcfilter_data_out_2_s),
|
||||
.adc_iqcor_valid (adc_valid_q1),
|
||||
.adc_iqcor_data (adc_data_q1),
|
||||
.adc_enable (adc_enable_q1),
|
||||
.up_adc_pn_err (up_adc_pn_err_s[3]),
|
||||
.up_adc_pn_oos (up_adc_pn_oos_s[3]),
|
||||
.up_adc_or (up_adc_or_s[3]),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq),
|
||||
.up_waddr (up_waddr),
|
||||
.up_wdata (up_wdata),
|
||||
.up_wack (up_wack_s[3]),
|
||||
.up_rreq (up_rreq),
|
||||
.up_raddr (up_raddr),
|
||||
.up_rdata (up_rdata_s[3]),
|
||||
.up_rack (up_rack_s[3]));
|
||||
|
||||
// common processor control
|
||||
|
||||
up_adc_common #(
|
||||
.ID (ID),
|
||||
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
|
||||
.FPGA_FAMILY (FPGA_FAMILY),
|
||||
.SPEED_GRADE (SPEED_GRADE),
|
||||
.DEV_PACKAGE (DEV_PACKAGE),
|
||||
.CONFIG (CONFIG),
|
||||
.DRP_DISABLE (1),
|
||||
.USERPORTS_DISABLE (USERPORTS_DISABLE),
|
||||
.GPIO_DISABLE (0),
|
||||
.START_CODE_DISABLE (0))
|
||||
i_up_adc_common (
|
||||
.mmcm_rst (mmcm_rst),
|
||||
.adc_clk (adc_clk),
|
||||
.adc_rst (adc_rst),
|
||||
.adc_r1_mode (adc_r1_mode),
|
||||
.adc_ddr_edgesel (adc_ddr_edgesel),
|
||||
.adc_pin_mode (),
|
||||
.adc_status (adc_status),
|
||||
.adc_sync_status (1'd0),
|
||||
.adc_status_ovf (adc_dovf),
|
||||
.adc_clk_ratio (32'd1),
|
||||
.adc_start_code (),
|
||||
.adc_sref_sync (),
|
||||
.adc_sync (),
|
||||
.adc_num_lanes (),
|
||||
.adc_sdr_ddr_n (),
|
||||
.up_adc_ce (),
|
||||
.up_pps_rcounter (up_pps_rcounter),
|
||||
.up_pps_status (up_pps_status),
|
||||
.up_pps_irq_mask (up_pps_irq_mask),
|
||||
.up_adc_r1_mode (),
|
||||
.up_status_pn_err (up_status_pn_err),
|
||||
.up_status_pn_oos (up_status_pn_oos),
|
||||
.up_status_or (up_status_or),
|
||||
.up_drp_sel (up_drp_sel),
|
||||
.up_drp_wr (up_drp_wr),
|
||||
.up_drp_addr (up_drp_addr),
|
||||
.up_drp_wdata (up_drp_wdata),
|
||||
.up_drp_rdata (up_drp_rdata),
|
||||
.up_drp_ready (up_drp_ready),
|
||||
.up_drp_locked (up_drp_locked),
|
||||
.up_usr_chanmax_out (),
|
||||
.up_usr_chanmax_in (8'd3),
|
||||
.up_adc_gpio_in (up_adc_gpio_in),
|
||||
.up_adc_gpio_out (up_adc_gpio_out),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq),
|
||||
.up_waddr (up_waddr),
|
||||
.up_wdata (up_wdata),
|
||||
.up_wack (up_wack_s[4]),
|
||||
.up_rreq (up_rreq),
|
||||
.up_raddr (up_raddr),
|
||||
.up_rdata (up_rdata_s[4]),
|
||||
.up_rack (up_rack_s[4]));
|
||||
|
||||
// adc delay control
|
||||
|
||||
up_delay_cntrl #(
|
||||
.INIT_DELAY (INIT_DELAY),
|
||||
.DATA_WIDTH (13),
|
||||
.BASE_ADDRESS (6'h02))
|
||||
i_delay_cntrl (
|
||||
.delay_clk (delay_clk),
|
||||
.delay_rst (delay_rst),
|
||||
.delay_locked (delay_locked),
|
||||
.up_dld (up_dld),
|
||||
.up_dwdata (up_dwdata),
|
||||
.up_drdata (up_drdata),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq),
|
||||
.up_waddr (up_waddr),
|
||||
.up_wdata (up_wdata),
|
||||
.up_wack (up_wack_s[5]),
|
||||
.up_rreq (up_rreq),
|
||||
.up_raddr (up_raddr),
|
||||
.up_rdata (up_rdata_s[5]),
|
||||
.up_rack (up_rack_s[5]));
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
@@ -0,0 +1,240 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module axi_ad9361_rx_channel #(
|
||||
|
||||
// parameters
|
||||
|
||||
parameter Q_OR_I_N = 0,
|
||||
parameter CHANNEL_ID = 0,
|
||||
parameter DISABLE = 0,
|
||||
parameter USERPORTS_DISABLE = 0,
|
||||
parameter DATAFORMAT_DISABLE = 0,
|
||||
parameter DCFILTER_DISABLE = 0,
|
||||
parameter IQCORRECTION_DISABLE = 0) (
|
||||
|
||||
// adc interface
|
||||
|
||||
input adc_clk,
|
||||
input adc_rst,
|
||||
input adc_valid,
|
||||
input [11:0] adc_data,
|
||||
input [11:0] adc_data_q,
|
||||
input adc_or,
|
||||
input [11:0] dac_data,
|
||||
|
||||
// channel interface
|
||||
|
||||
output [15:0] adc_dcfilter_data_out,
|
||||
input [15:0] adc_dcfilter_data_in,
|
||||
output adc_iqcor_valid,
|
||||
output [15:0] adc_iqcor_data,
|
||||
output adc_enable,
|
||||
output up_adc_pn_err,
|
||||
output up_adc_pn_oos,
|
||||
output up_adc_or,
|
||||
|
||||
// processor interface
|
||||
|
||||
input up_rstn,
|
||||
input up_clk,
|
||||
input up_wreq,
|
||||
input [13:0] up_waddr,
|
||||
input [31:0] up_wdata,
|
||||
output up_wack,
|
||||
input up_rreq,
|
||||
input [13:0] up_raddr,
|
||||
output [31:0] up_rdata,
|
||||
output up_rack);
|
||||
|
||||
// internal signals
|
||||
|
||||
wire [11:0] adc_data_s;
|
||||
wire adc_dfmt_valid_s;
|
||||
wire [15:0] adc_dfmt_data_s;
|
||||
wire adc_dcfilter_valid_s;
|
||||
wire [15:0] adc_dcfilter_data_s;
|
||||
wire adc_iqcor_enb_s;
|
||||
wire adc_dcfilt_enb_s;
|
||||
wire adc_dfmt_se_s;
|
||||
wire adc_dfmt_type_s;
|
||||
wire adc_dfmt_enable_s;
|
||||
wire [15:0] adc_dcfilt_offset_s;
|
||||
wire [15:0] adc_dcfilt_coeff_s;
|
||||
wire [15:0] adc_iqcor_coeff_1_s;
|
||||
wire [15:0] adc_iqcor_coeff_2_s;
|
||||
wire [ 3:0] adc_pnseq_sel_s;
|
||||
wire [ 3:0] adc_data_sel_s;
|
||||
wire adc_pn_err_s;
|
||||
wire adc_pn_oos_s;
|
||||
|
||||
// data-path disable
|
||||
|
||||
generate
|
||||
if (DISABLE == 1) begin
|
||||
assign adc_dcfilter_data_out = 16'd0;
|
||||
assign adc_iqcor_valid = 1'd0;
|
||||
assign adc_iqcor_data = 16'd0;
|
||||
assign adc_enable = 1'd0;
|
||||
assign up_adc_pn_err = 1'd0;
|
||||
assign up_adc_pn_oos = 1'd0;
|
||||
assign up_adc_or = 1'd0;
|
||||
assign up_wack = 1'd0;
|
||||
assign up_rdata = 32'd0;
|
||||
assign up_rack = 1'd0;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate
|
||||
if (DISABLE == 0) begin
|
||||
|
||||
// iq correction inputs
|
||||
|
||||
assign adc_data_s = (adc_data_sel_s == 4'h0) ? adc_data : dac_data;
|
||||
assign adc_dcfilter_data_out = adc_dcfilter_data_s;
|
||||
|
||||
axi_ad9361_rx_pnmon #(
|
||||
.Q_OR_I_N (Q_OR_I_N),
|
||||
.PRBS_SEL (CHANNEL_ID))
|
||||
i_rx_pnmon (
|
||||
.adc_clk (adc_clk),
|
||||
.adc_valid (adc_valid),
|
||||
.adc_data_i (adc_data),
|
||||
.adc_data_q (adc_data_q),
|
||||
.adc_pnseq_sel (adc_pnseq_sel_s),
|
||||
.adc_pn_oos (adc_pn_oos_s),
|
||||
.adc_pn_err (adc_pn_err_s));
|
||||
|
||||
ad_datafmt #(
|
||||
.DATA_WIDTH (12),
|
||||
.DISABLE (DATAFORMAT_DISABLE))
|
||||
i_ad_datafmt (
|
||||
.clk (adc_clk),
|
||||
.valid (adc_valid),
|
||||
.data (adc_data_s),
|
||||
.valid_out (adc_dfmt_valid_s),
|
||||
.data_out (adc_dfmt_data_s),
|
||||
.dfmt_enable (adc_dfmt_enable_s),
|
||||
.dfmt_type (adc_dfmt_type_s),
|
||||
.dfmt_se (adc_dfmt_se_s));
|
||||
|
||||
ad_dcfilter #(
|
||||
.DISABLE (DCFILTER_DISABLE))
|
||||
i_ad_dcfilter (
|
||||
.clk (adc_clk),
|
||||
.valid (adc_dfmt_valid_s),
|
||||
.data (adc_dfmt_data_s),
|
||||
.valid_out (adc_dcfilter_valid_s),
|
||||
.data_out (adc_dcfilter_data_s),
|
||||
.dcfilt_enb (adc_dcfilt_enb_s),
|
||||
.dcfilt_coeff (adc_dcfilt_coeff_s),
|
||||
.dcfilt_offset (adc_dcfilt_offset_s));
|
||||
|
||||
ad_iqcor #(
|
||||
.Q_OR_I_N (Q_OR_I_N),
|
||||
.DISABLE (IQCORRECTION_DISABLE))
|
||||
i_ad_iqcor (
|
||||
.clk (adc_clk),
|
||||
.valid (adc_dcfilter_valid_s),
|
||||
.data_in (adc_dcfilter_data_s),
|
||||
.data_iq (adc_dcfilter_data_in),
|
||||
.valid_out (adc_iqcor_valid),
|
||||
.data_out (adc_iqcor_data),
|
||||
.iqcor_enable (adc_iqcor_enb_s),
|
||||
.iqcor_coeff_1 (adc_iqcor_coeff_1_s),
|
||||
.iqcor_coeff_2 (adc_iqcor_coeff_2_s));
|
||||
|
||||
up_adc_channel #(
|
||||
.CHANNEL_ID (CHANNEL_ID),
|
||||
.USERPORTS_DISABLE (USERPORTS_DISABLE),
|
||||
.DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
|
||||
.DCFILTER_DISABLE (DCFILTER_DISABLE),
|
||||
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE))
|
||||
i_up_adc_channel (
|
||||
.adc_clk (adc_clk),
|
||||
.adc_rst (adc_rst),
|
||||
.adc_enable (adc_enable),
|
||||
.adc_iqcor_enb (adc_iqcor_enb_s),
|
||||
.adc_dcfilt_enb (adc_dcfilt_enb_s),
|
||||
.adc_dfmt_se (adc_dfmt_se_s),
|
||||
.adc_dfmt_type (adc_dfmt_type_s),
|
||||
.adc_dfmt_enable (adc_dfmt_enable_s),
|
||||
.adc_dcfilt_offset (adc_dcfilt_offset_s),
|
||||
.adc_dcfilt_coeff (adc_dcfilt_coeff_s),
|
||||
.adc_iqcor_coeff_1 (adc_iqcor_coeff_1_s),
|
||||
.adc_iqcor_coeff_2 (adc_iqcor_coeff_2_s),
|
||||
.adc_pnseq_sel (adc_pnseq_sel_s),
|
||||
.adc_data_sel (adc_data_sel_s),
|
||||
.adc_pn_err (adc_pn_err_s),
|
||||
.adc_pn_oos (adc_pn_oos_s),
|
||||
.adc_or (adc_or),
|
||||
.up_adc_pn_err (up_adc_pn_err),
|
||||
.up_adc_pn_oos (up_adc_pn_oos),
|
||||
.up_adc_or (up_adc_or),
|
||||
.up_usr_datatype_be (),
|
||||
.up_usr_datatype_signed (),
|
||||
.up_usr_datatype_shift (),
|
||||
.up_usr_datatype_total_bits (),
|
||||
.up_usr_datatype_bits (),
|
||||
.up_usr_decimation_m (),
|
||||
.up_usr_decimation_n (),
|
||||
.adc_usr_datatype_be (1'b0),
|
||||
.adc_usr_datatype_signed (1'b1),
|
||||
.adc_usr_datatype_shift (8'd0),
|
||||
.adc_usr_datatype_total_bits (8'd16),
|
||||
.adc_usr_datatype_bits (8'd16),
|
||||
.adc_usr_decimation_m (16'd1),
|
||||
.adc_usr_decimation_n (16'd1),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq),
|
||||
.up_waddr (up_waddr),
|
||||
.up_wdata (up_wdata),
|
||||
.up_wack (up_wack),
|
||||
.up_rreq (up_rreq),
|
||||
.up_raddr (up_raddr),
|
||||
.up_rdata (up_rdata),
|
||||
.up_rack (up_rack));
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
@@ -0,0 +1,303 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// PN monitors
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module axi_ad9361_rx_pnmon #(
|
||||
|
||||
parameter Q_OR_I_N = 0,
|
||||
parameter PRBS_SEL = 0) (
|
||||
|
||||
// adc interface
|
||||
|
||||
input adc_clk,
|
||||
input adc_valid,
|
||||
input [11:0] adc_data_i,
|
||||
input [11:0] adc_data_q,
|
||||
|
||||
// pn out of sync and error
|
||||
|
||||
input [ 3:0] adc_pnseq_sel,
|
||||
output adc_pn_oos,
|
||||
output adc_pn_err);
|
||||
|
||||
localparam PRBS_P09 = 0;
|
||||
localparam PRBS_P11 = 1;
|
||||
localparam PRBS_P15 = 2;
|
||||
localparam PRBS_P20 = 3;
|
||||
|
||||
// internal registers
|
||||
|
||||
reg adc_pn0_valid = 'd0;
|
||||
reg [15:0] adc_pn0_data = 'd0;
|
||||
reg adc_pn0_valid_in = 'd0;
|
||||
reg [15:0] adc_pn0_data_in = 'd0;
|
||||
reg [15:0] adc_pn0_data_pn = 'd0;
|
||||
reg adc_pn1_valid_t = 'd0;
|
||||
reg [11:0] adc_pn1_data_d = 'd0;
|
||||
reg adc_pn1_valid_in = 'd0;
|
||||
reg [23:0] adc_pn1_data_in = 'd0;
|
||||
reg [23:0] adc_pn1_data_pn = 'd0;
|
||||
reg adc_pn_valid_in = 'd0;
|
||||
reg [23:0] adc_pn_data_in = 'd0;
|
||||
reg [23:0] adc_pn_data_pn = 'd0;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire [11:0] adc_pn0_data_i_s;
|
||||
wire [11:0] adc_pn0_data_q_s;
|
||||
wire [11:0] adc_pn0_data_q_rev_s;
|
||||
wire [15:0] adc_pn0_data_s;
|
||||
wire adc_pn0_iq_match_s;
|
||||
wire [15:0] adc_pn0_data_pn_s;
|
||||
wire adc_pn1_valid_s;
|
||||
wire [23:0] adc_pn1_data_pn_s;
|
||||
|
||||
// bit reversal function
|
||||
|
||||
function [11:0] brfn;
|
||||
input [11:0] din;
|
||||
reg [11:0] dout;
|
||||
begin
|
||||
dout[11] = din[ 0];
|
||||
dout[10] = din[ 1];
|
||||
dout[ 9] = din[ 2];
|
||||
dout[ 8] = din[ 3];
|
||||
dout[ 7] = din[ 4];
|
||||
dout[ 6] = din[ 5];
|
||||
dout[ 5] = din[ 6];
|
||||
dout[ 4] = din[ 7];
|
||||
dout[ 3] = din[ 8];
|
||||
dout[ 2] = din[ 9];
|
||||
dout[ 1] = din[10];
|
||||
dout[ 0] = din[11];
|
||||
brfn = dout;
|
||||
end
|
||||
endfunction
|
||||
|
||||
// device-specific prbs function
|
||||
|
||||
function [15:0] pn0fn;
|
||||
input [15:0] din;
|
||||
reg [15:0] dout;
|
||||
begin
|
||||
dout = {din[14:0], ((^din[15:4]) ^ (^din[2:1]))};
|
||||
pn0fn = dout;
|
||||
end
|
||||
endfunction
|
||||
|
||||
// standard prbs functions
|
||||
|
||||
function [23:0] pn1fn;
|
||||
input [23:0] din;
|
||||
reg [23:0] dout;
|
||||
begin
|
||||
case (PRBS_SEL)
|
||||
PRBS_P09: begin
|
||||
dout[23] = din[ 8] ^ din[ 4];
|
||||
dout[22] = din[ 7] ^ din[ 3];
|
||||
dout[21] = din[ 6] ^ din[ 2];
|
||||
dout[20] = din[ 5] ^ din[ 1];
|
||||
dout[19] = din[ 4] ^ din[ 0];
|
||||
dout[18] = din[ 3] ^ din[ 8] ^ din[ 4];
|
||||
dout[17] = din[ 2] ^ din[ 7] ^ din[ 3];
|
||||
dout[16] = din[ 1] ^ din[ 6] ^ din[ 2];
|
||||
dout[15] = din[ 0] ^ din[ 5] ^ din[ 1];
|
||||
dout[14] = din[ 8] ^ din[ 0];
|
||||
dout[13] = din[ 7] ^ din[ 8] ^ din[ 4];
|
||||
dout[12] = din[ 6] ^ din[ 7] ^ din[ 3];
|
||||
dout[11] = din[ 5] ^ din[ 6] ^ din[ 2];
|
||||
dout[10] = din[ 4] ^ din[ 5] ^ din[ 1];
|
||||
dout[ 9] = din[ 3] ^ din[ 4] ^ din[ 0];
|
||||
dout[ 8] = din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4];
|
||||
dout[ 7] = din[ 1] ^ din[ 2] ^ din[ 7] ^ din[ 3];
|
||||
dout[ 6] = din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 2];
|
||||
dout[ 5] = din[ 8] ^ din[ 0] ^ din[ 4] ^ din[ 5] ^ din[ 1];
|
||||
dout[ 4] = din[ 7] ^ din[ 8] ^ din[ 3] ^ din[ 0];
|
||||
dout[ 3] = din[ 6] ^ din[ 7] ^ din[ 2] ^ din[ 8] ^ din[ 4];
|
||||
dout[ 2] = din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 7] ^ din[ 3];
|
||||
dout[ 1] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6] ^ din[ 2];
|
||||
dout[ 0] = din[ 3] ^ din[ 8] ^ din[ 5] ^ din[ 1];
|
||||
end
|
||||
PRBS_P11: begin
|
||||
dout[23] = din[10] ^ din[ 8];
|
||||
dout[22] = din[ 9] ^ din[ 7];
|
||||
dout[21] = din[ 8] ^ din[ 6];
|
||||
dout[20] = din[ 7] ^ din[ 5];
|
||||
dout[19] = din[ 6] ^ din[ 4];
|
||||
dout[18] = din[ 5] ^ din[ 3];
|
||||
dout[17] = din[ 4] ^ din[ 2];
|
||||
dout[16] = din[ 3] ^ din[ 1];
|
||||
dout[15] = din[ 2] ^ din[ 0];
|
||||
dout[14] = din[ 1] ^ din[10] ^ din[ 8];
|
||||
dout[13] = din[ 0] ^ din[ 9] ^ din[ 7];
|
||||
dout[12] = din[10] ^ din[ 6];
|
||||
dout[11] = din[ 9] ^ din[ 5];
|
||||
dout[10] = din[ 8] ^ din[ 4];
|
||||
dout[ 9] = din[ 7] ^ din[ 3];
|
||||
dout[ 8] = din[ 6] ^ din[ 2];
|
||||
dout[ 7] = din[ 5] ^ din[ 1];
|
||||
dout[ 6] = din[ 4] ^ din[ 0];
|
||||
dout[ 5] = din[ 3] ^ din[10] ^ din[ 8];
|
||||
dout[ 4] = din[ 2] ^ din[ 9] ^ din[ 7];
|
||||
dout[ 3] = din[ 1] ^ din[ 8] ^ din[ 6];
|
||||
dout[ 2] = din[ 0] ^ din[ 7] ^ din[ 5];
|
||||
dout[ 1] = din[10] ^ din[ 6] ^ din[ 8] ^ din[ 4];
|
||||
dout[ 0] = din[ 9] ^ din[ 5] ^ din[ 7] ^ din[ 3];
|
||||
end
|
||||
PRBS_P15: begin
|
||||
dout[23] = din[14] ^ din[13];
|
||||
dout[22] = din[13] ^ din[12];
|
||||
dout[21] = din[12] ^ din[11];
|
||||
dout[20] = din[11] ^ din[10];
|
||||
dout[19] = din[10] ^ din[ 9];
|
||||
dout[18] = din[ 9] ^ din[ 8];
|
||||
dout[17] = din[ 8] ^ din[ 7];
|
||||
dout[16] = din[ 7] ^ din[ 6];
|
||||
dout[15] = din[ 6] ^ din[ 5];
|
||||
dout[14] = din[ 5] ^ din[ 4];
|
||||
dout[13] = din[ 4] ^ din[ 3];
|
||||
dout[12] = din[ 3] ^ din[ 2];
|
||||
dout[11] = din[ 2] ^ din[ 1];
|
||||
dout[10] = din[ 1] ^ din[ 0];
|
||||
dout[ 9] = din[ 0] ^ din[14] ^ din[13];
|
||||
dout[ 8] = din[14] ^ din[12];
|
||||
dout[ 7] = din[13] ^ din[11];
|
||||
dout[ 6] = din[12] ^ din[10];
|
||||
dout[ 5] = din[11] ^ din[ 9];
|
||||
dout[ 4] = din[10] ^ din[ 8];
|
||||
dout[ 3] = din[ 9] ^ din[ 7];
|
||||
dout[ 2] = din[ 8] ^ din[ 6];
|
||||
dout[ 1] = din[ 7] ^ din[ 5];
|
||||
dout[ 0] = din[ 6] ^ din[ 4];
|
||||
end
|
||||
PRBS_P20: begin
|
||||
dout[23] = din[19] ^ din[ 2];
|
||||
dout[22] = din[18] ^ din[ 1];
|
||||
dout[21] = din[17] ^ din[ 0];
|
||||
dout[20] = din[16] ^ din[19] ^ din[ 2];
|
||||
dout[19] = din[15] ^ din[18] ^ din[ 1];
|
||||
dout[18] = din[14] ^ din[17] ^ din[ 0];
|
||||
dout[17] = din[13] ^ din[16] ^ din[19] ^ din[ 2];
|
||||
dout[16] = din[12] ^ din[15] ^ din[18] ^ din[ 1];
|
||||
dout[15] = din[11] ^ din[14] ^ din[17] ^ din[ 0];
|
||||
dout[14] = din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2];
|
||||
dout[13] = din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1];
|
||||
dout[12] = din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0];
|
||||
dout[11] = din[ 7] ^ din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2];
|
||||
dout[10] = din[ 6] ^ din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1];
|
||||
dout[ 9] = din[ 5] ^ din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0];
|
||||
dout[ 8] = din[ 4] ^ din[ 7] ^ din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2];
|
||||
dout[ 7] = din[ 3] ^ din[ 6] ^ din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1];
|
||||
dout[ 6] = din[ 2] ^ din[ 5] ^ din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0];
|
||||
dout[ 5] = din[ 1] ^ din[ 4] ^ din[ 7] ^ din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2];
|
||||
dout[ 4] = din[ 0] ^ din[ 3] ^ din[ 6] ^ din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1];
|
||||
dout[ 3] = din[19] ^ din[ 5] ^ din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0];
|
||||
dout[ 2] = din[18] ^ din[ 4] ^ din[ 7] ^ din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2];
|
||||
dout[ 1] = din[17] ^ din[ 3] ^ din[ 6] ^ din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1];
|
||||
dout[ 0] = din[16] ^ din[ 2] ^ din[ 5] ^ din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0];
|
||||
end
|
||||
endcase
|
||||
pn1fn = dout;
|
||||
end
|
||||
endfunction
|
||||
|
||||
// device specific, assuming lower nibble is lost-
|
||||
|
||||
assign adc_pn0_data_i_s = (Q_OR_I_N == 1) ? adc_data_q : adc_data_i;
|
||||
assign adc_pn0_data_q_s = (Q_OR_I_N == 1) ? adc_data_i : adc_data_q;
|
||||
assign adc_pn0_data_q_rev_s = brfn(adc_pn0_data_q_s);
|
||||
assign adc_pn0_data_s = {adc_pn0_data_i_s, adc_pn0_data_q_rev_s[3:0]};
|
||||
assign adc_pn0_iq_match_s = (adc_pn0_data_i_s[7:0] == adc_pn0_data_q_rev_s[11:4]) ? 1'b1 : 1'b0;
|
||||
assign adc_pn0_data_pn_s = (adc_pn_oos == 1'b1) ? adc_pn0_data_in : adc_pn0_data_pn;
|
||||
|
||||
always @(posedge adc_clk) begin
|
||||
adc_pn0_valid <= adc_valid;
|
||||
adc_pn0_data <= (adc_pn0_iq_match_s == 1'b0) ? 16'hdead : adc_pn0_data_s;
|
||||
adc_pn0_valid_in <= adc_pn0_valid;
|
||||
if (adc_pn0_valid == 1'b1) begin
|
||||
adc_pn0_data_in <= adc_pn0_data;
|
||||
adc_pn0_data_pn <= pn0fn(adc_pn0_data_pn_s);
|
||||
end
|
||||
end
|
||||
|
||||
// standard, runs on 24bit
|
||||
|
||||
assign adc_pn1_valid_s = adc_pn1_valid_t & adc_valid;
|
||||
assign adc_pn1_data_pn_s = (adc_pn_oos == 1'b1) ? adc_pn1_data_in : adc_pn1_data_pn;
|
||||
|
||||
always @(posedge adc_clk) begin
|
||||
if (adc_valid == 1'b1) begin
|
||||
adc_pn1_valid_t <= ~adc_pn1_valid_t;
|
||||
adc_pn1_data_d <= adc_data_i;
|
||||
end
|
||||
adc_pn1_valid_in <= adc_pn1_valid_s;
|
||||
if (adc_pn1_valid_s == 1'b1) begin
|
||||
adc_pn1_data_in <= {adc_pn1_data_d, adc_data_i};
|
||||
adc_pn1_data_pn <= pn1fn(adc_pn1_data_pn_s);
|
||||
end
|
||||
end
|
||||
|
||||
// pn mux
|
||||
|
||||
always @(posedge adc_clk) begin
|
||||
if (adc_pnseq_sel == 4'h9) begin
|
||||
adc_pn_valid_in <= adc_pn1_valid_in;
|
||||
adc_pn_data_in <= adc_pn1_data_in;
|
||||
adc_pn_data_pn <= adc_pn1_data_pn;
|
||||
end else begin
|
||||
adc_pn_valid_in <= adc_pn0_valid_in;
|
||||
adc_pn_data_in <= {adc_pn0_data_in[7:0], adc_pn0_data_in};
|
||||
adc_pn_data_pn <= {adc_pn0_data_pn[7:0], adc_pn0_data_pn};
|
||||
end
|
||||
end
|
||||
|
||||
// pn oos & pn err
|
||||
|
||||
ad_pnmon #(.DATA_WIDTH(24)) i_pnmon (
|
||||
.adc_clk (adc_clk),
|
||||
.adc_valid_in (adc_pn_valid_in),
|
||||
.adc_data_in (adc_pn_data_in),
|
||||
.adc_data_pn (adc_pn_data_pn),
|
||||
.adc_pattern_has_zero (1'b0),
|
||||
.adc_pn_oos (adc_pn_oos),
|
||||
.adc_pn_err (adc_pn_err));
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
@@ -0,0 +1,253 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
module axi_ad9361_tdd (
|
||||
|
||||
// clock
|
||||
|
||||
input clk,
|
||||
input rst,
|
||||
|
||||
// control signals from the tdd control
|
||||
|
||||
output tdd_rx_vco_en,
|
||||
output tdd_tx_vco_en,
|
||||
output tdd_rx_rf_en,
|
||||
output tdd_tx_rf_en,
|
||||
|
||||
// status signal
|
||||
|
||||
output tdd_enabled,
|
||||
input [ 7:0] tdd_status,
|
||||
|
||||
// sync signal
|
||||
|
||||
input tdd_sync,
|
||||
output reg tdd_sync_cntr,
|
||||
|
||||
// tx/rx data flow control
|
||||
|
||||
output reg tdd_tx_valid,
|
||||
output reg tdd_rx_valid,
|
||||
|
||||
// bus interface
|
||||
|
||||
input up_rstn,
|
||||
input up_clk,
|
||||
input up_wreq,
|
||||
input [13:0] up_waddr,
|
||||
input [31:0] up_wdata,
|
||||
output up_wack,
|
||||
input up_rreq,
|
||||
input [13:0] up_raddr,
|
||||
output [31:0] up_rdata,
|
||||
output up_rack);
|
||||
|
||||
// internal signals
|
||||
|
||||
wire tdd_enable_s;
|
||||
wire tdd_secondary_s;
|
||||
wire [ 7:0] tdd_burst_count_s;
|
||||
wire tdd_rx_only_s;
|
||||
wire tdd_tx_only_s;
|
||||
wire tdd_gated_rx_dmapath_s;
|
||||
wire tdd_gated_tx_dmapath_s;
|
||||
wire [23:0] tdd_counter_init_s;
|
||||
wire [23:0] tdd_frame_length_s;
|
||||
wire tdd_terminal_type_s;
|
||||
wire tdd_sync_enable_s;
|
||||
wire [23:0] tdd_vco_rx_on_1_s;
|
||||
wire [23:0] tdd_vco_rx_off_1_s;
|
||||
wire [23:0] tdd_vco_tx_on_1_s;
|
||||
wire [23:0] tdd_vco_tx_off_1_s;
|
||||
wire [23:0] tdd_rx_on_1_s;
|
||||
wire [23:0] tdd_rx_off_1_s;
|
||||
wire [23:0] tdd_rx_dp_on_1_s;
|
||||
wire [23:0] tdd_rx_dp_off_1_s;
|
||||
wire [23:0] tdd_tx_on_1_s;
|
||||
wire [23:0] tdd_tx_off_1_s;
|
||||
wire [23:0] tdd_tx_dp_on_1_s;
|
||||
wire [23:0] tdd_tx_dp_off_1_s;
|
||||
wire [23:0] tdd_vco_rx_on_2_s;
|
||||
wire [23:0] tdd_vco_rx_off_2_s;
|
||||
wire [23:0] tdd_vco_tx_on_2_s;
|
||||
wire [23:0] tdd_vco_tx_off_2_s;
|
||||
wire [23:0] tdd_rx_on_2_s;
|
||||
wire [23:0] tdd_rx_off_2_s;
|
||||
wire [23:0] tdd_rx_dp_on_2_s;
|
||||
wire [23:0] tdd_rx_dp_off_2_s;
|
||||
wire [23:0] tdd_tx_on_2_s;
|
||||
wire [23:0] tdd_tx_off_2_s;
|
||||
wire [23:0] tdd_tx_dp_on_2_s;
|
||||
wire [23:0] tdd_tx_dp_off_2_s;
|
||||
|
||||
wire [23:0] tdd_counter_status;
|
||||
|
||||
wire tdd_rx_dp_en_s;
|
||||
wire tdd_tx_dp_en_s;
|
||||
|
||||
assign tdd_enabled = tdd_enable_s;
|
||||
|
||||
// syncronization control signal
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (tdd_enable_s == 1'b1) begin
|
||||
tdd_sync_cntr <= ~tdd_terminal_type_s;
|
||||
end else begin
|
||||
tdd_sync_cntr <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
// tx/rx data flow control
|
||||
|
||||
always @(posedge clk) begin
|
||||
if((tdd_enable_s == 1) && (tdd_gated_tx_dmapath_s == 1)) begin
|
||||
tdd_tx_valid <= tdd_tx_dp_en_s;
|
||||
end else begin
|
||||
tdd_tx_valid <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if((tdd_enable_s == 1) && (tdd_gated_tx_dmapath_s == 1)) begin
|
||||
tdd_rx_valid <= tdd_rx_dp_en_s;
|
||||
end else begin
|
||||
tdd_rx_valid <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
// instantiations
|
||||
|
||||
up_tdd_cntrl i_up_tdd_cntrl(
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
.tdd_enable(tdd_enable_s),
|
||||
.tdd_secondary(tdd_secondary_s),
|
||||
.tdd_burst_count(tdd_burst_count_s),
|
||||
.tdd_tx_only(tdd_tx_only_s),
|
||||
.tdd_rx_only(tdd_rx_only_s),
|
||||
.tdd_gated_rx_dmapath(tdd_gated_rx_dmapath_s),
|
||||
.tdd_gated_tx_dmapath(tdd_gated_tx_dmapath_s),
|
||||
.tdd_counter_init(tdd_counter_init_s),
|
||||
.tdd_frame_length(tdd_frame_length_s),
|
||||
.tdd_terminal_type(tdd_terminal_type_s),
|
||||
.tdd_vco_rx_on_1(tdd_vco_rx_on_1_s),
|
||||
.tdd_vco_rx_off_1(tdd_vco_rx_off_1_s),
|
||||
.tdd_vco_tx_on_1(tdd_vco_tx_on_1_s),
|
||||
.tdd_vco_tx_off_1(tdd_vco_tx_off_1_s),
|
||||
.tdd_rx_on_1(tdd_rx_on_1_s),
|
||||
.tdd_rx_off_1(tdd_rx_off_1_s),
|
||||
.tdd_rx_dp_on_1(tdd_rx_dp_on_1_s),
|
||||
.tdd_rx_dp_off_1(tdd_rx_dp_off_1_s),
|
||||
.tdd_tx_on_1(tdd_tx_on_1_s),
|
||||
.tdd_tx_off_1(tdd_tx_off_1_s),
|
||||
.tdd_tx_dp_on_1(tdd_tx_dp_on_1_s),
|
||||
.tdd_tx_dp_off_1(tdd_tx_dp_off_1_s),
|
||||
.tdd_vco_rx_on_2(tdd_vco_rx_on_2_s),
|
||||
.tdd_vco_rx_off_2(tdd_vco_rx_off_2_s),
|
||||
.tdd_vco_tx_on_2(tdd_vco_tx_on_2_s),
|
||||
.tdd_vco_tx_off_2(tdd_vco_tx_off_2_s),
|
||||
.tdd_rx_on_2(tdd_rx_on_2_s),
|
||||
.tdd_rx_off_2(tdd_rx_off_2_s),
|
||||
.tdd_rx_dp_on_2(tdd_rx_dp_on_2_s),
|
||||
.tdd_rx_dp_off_2(tdd_rx_dp_off_2_s),
|
||||
.tdd_tx_on_2(tdd_tx_on_2_s),
|
||||
.tdd_tx_off_2(tdd_tx_off_2_s),
|
||||
.tdd_tx_dp_on_2(tdd_tx_dp_on_2_s),
|
||||
.tdd_tx_dp_off_2(tdd_tx_dp_off_2_s),
|
||||
.tdd_status(tdd_status),
|
||||
.up_rstn(up_rstn),
|
||||
.up_clk(up_clk),
|
||||
.up_wreq(up_wreq),
|
||||
.up_waddr(up_waddr),
|
||||
.up_wdata(up_wdata),
|
||||
.up_wack(up_wack),
|
||||
.up_rreq(up_rreq),
|
||||
.up_raddr(up_raddr),
|
||||
.up_rdata(up_rdata),
|
||||
.up_rack(up_rack));
|
||||
|
||||
// the TX_DATA_PATH_DELAY and CONTROL_PATH_DELAY are specificly defined
|
||||
// for the axi_ad9361 core
|
||||
|
||||
ad_tdd_control #(
|
||||
.TX_DATA_PATH_DELAY(),
|
||||
.CONTROL_PATH_DELAY())
|
||||
i_tdd_control(
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
.tdd_enable(tdd_enable_s),
|
||||
.tdd_secondary(tdd_secondary_s),
|
||||
.tdd_counter_init(tdd_counter_init_s),
|
||||
.tdd_frame_length(tdd_frame_length_s),
|
||||
.tdd_burst_count(tdd_burst_count_s),
|
||||
.tdd_rx_only(tdd_rx_only_s),
|
||||
.tdd_tx_only(tdd_tx_only_s),
|
||||
.tdd_sync (tdd_sync),
|
||||
.tdd_vco_rx_on_1(tdd_vco_rx_on_1_s),
|
||||
.tdd_vco_rx_off_1(tdd_vco_rx_off_1_s),
|
||||
.tdd_vco_tx_on_1(tdd_vco_tx_on_1_s),
|
||||
.tdd_vco_tx_off_1(tdd_vco_tx_off_1_s),
|
||||
.tdd_rx_on_1(tdd_rx_on_1_s),
|
||||
.tdd_rx_off_1(tdd_rx_off_1_s),
|
||||
.tdd_rx_dp_on_1(tdd_rx_dp_on_1_s),
|
||||
.tdd_rx_dp_off_1(tdd_rx_dp_off_1_s),
|
||||
.tdd_tx_on_1(tdd_tx_on_1_s),
|
||||
.tdd_tx_off_1(tdd_tx_off_1_s),
|
||||
.tdd_tx_dp_on_1(tdd_tx_dp_on_1_s),
|
||||
.tdd_tx_dp_off_1(tdd_tx_dp_off_1_s),
|
||||
.tdd_vco_rx_on_2(tdd_vco_rx_on_2_s),
|
||||
.tdd_vco_rx_off_2(tdd_vco_rx_off_2_s),
|
||||
.tdd_vco_tx_on_2(tdd_vco_tx_on_2_s),
|
||||
.tdd_vco_tx_off_2(tdd_vco_tx_off_2_s),
|
||||
.tdd_rx_on_2(tdd_rx_on_2_s),
|
||||
.tdd_rx_off_2(tdd_rx_off_2_s),
|
||||
.tdd_rx_dp_on_2(tdd_rx_dp_on_2_s),
|
||||
.tdd_rx_dp_off_2(tdd_rx_dp_off_2_s),
|
||||
.tdd_tx_on_2(tdd_tx_on_2_s),
|
||||
.tdd_tx_off_2(tdd_tx_off_2_s),
|
||||
.tdd_tx_dp_on_2(tdd_tx_dp_on_2_s),
|
||||
.tdd_tx_dp_off_2(tdd_tx_dp_off_2_s),
|
||||
.tdd_rx_dp_en(tdd_rx_dp_en_s),
|
||||
.tdd_tx_dp_en(tdd_tx_dp_en_s),
|
||||
.tdd_rx_vco_en(tdd_rx_vco_en),
|
||||
.tdd_tx_vco_en(tdd_tx_vco_en),
|
||||
.tdd_rx_rf_en(tdd_rx_rf_en),
|
||||
.tdd_tx_rf_en(tdd_tx_rf_en),
|
||||
.tdd_counter_status(tdd_counter_status));
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,109 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
module axi_ad9361_tdd_if#(
|
||||
|
||||
parameter LEVEL_OR_PULSE_N = 0) (
|
||||
|
||||
// clock
|
||||
|
||||
input clk,
|
||||
input rst,
|
||||
|
||||
// control signals from the tdd control
|
||||
|
||||
input tdd_rx_vco_en,
|
||||
input tdd_tx_vco_en,
|
||||
input tdd_rx_rf_en,
|
||||
input tdd_tx_rf_en,
|
||||
|
||||
// device interface
|
||||
|
||||
output ad9361_txnrx,
|
||||
output ad9361_enable,
|
||||
|
||||
// interface status
|
||||
|
||||
output [ 7:0] ad9361_tdd_status);
|
||||
|
||||
|
||||
localparam PULSE_MODE = 0;
|
||||
localparam LEVEL_MODE = 1;
|
||||
|
||||
// internal registers
|
||||
|
||||
|
||||
reg tdd_vco_overlap = 1'b0;
|
||||
reg tdd_rf_overlap = 1'b0;
|
||||
|
||||
wire ad9361_txnrx_s;
|
||||
wire ad9361_enable_s;
|
||||
|
||||
// just one VCO can be enabled at a time
|
||||
assign ad9361_txnrx_s = tdd_tx_vco_en & ~tdd_rx_vco_en;
|
||||
|
||||
generate
|
||||
if (LEVEL_OR_PULSE_N == PULSE_MODE) begin
|
||||
reg tdd_rx_rf_en_d = 1'b0;
|
||||
reg tdd_tx_rf_en_d = 1'b0;
|
||||
always @(posedge clk) begin
|
||||
tdd_rx_rf_en_d <= tdd_rx_rf_en;
|
||||
tdd_tx_rf_en_d <= tdd_tx_rf_en;
|
||||
end
|
||||
assign ad9361_enable_s = (tdd_rx_rf_en_d ^ tdd_rx_rf_en) ||
|
||||
(tdd_tx_rf_en_d ^ tdd_tx_rf_en);
|
||||
end else
|
||||
assign ad9361_enable_s = (tdd_rx_rf_en | tdd_tx_rf_en);
|
||||
endgenerate
|
||||
|
||||
always @(posedge clk) begin
|
||||
if(rst == 1'b1) begin
|
||||
tdd_vco_overlap <= 1'b0;
|
||||
tdd_rf_overlap <= 1'b0;
|
||||
end else begin
|
||||
tdd_vco_overlap <= tdd_rx_vco_en & tdd_tx_vco_en;
|
||||
tdd_rf_overlap <= tdd_rx_rf_en & tdd_tx_rf_en;
|
||||
end
|
||||
end
|
||||
|
||||
assign ad9361_tdd_status = {6'b0, tdd_rf_overlap, tdd_vco_overlap};
|
||||
|
||||
assign ad9361_txnrx = ad9361_txnrx_s;
|
||||
assign ad9361_enable = ad9361_enable_s;
|
||||
|
||||
endmodule
|
||||
|
||||
@@ -0,0 +1,444 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module axi_ad9361_tx #(
|
||||
|
||||
// parameters
|
||||
|
||||
parameter ID = 0,
|
||||
parameter FPGA_TECHNOLOGY = 0,
|
||||
parameter FPGA_FAMILY = 0,
|
||||
parameter SPEED_GRADE = 0,
|
||||
parameter DEV_PACKAGE = 0,
|
||||
parameter MODE_1R1T = 0,
|
||||
parameter CLK_EDGE_SEL = 0,
|
||||
parameter CMOS_OR_LVDS_N = 0,
|
||||
parameter PPS_RECEIVER_ENABLE = 0,
|
||||
parameter INIT_DELAY = 0,
|
||||
parameter DAC_DDS_DISABLE = 0,
|
||||
parameter DAC_DDS_TYPE = 1,
|
||||
parameter DAC_DDS_CORDIC_DW = 14,
|
||||
parameter DAC_DDS_CORDIC_PHASE_DW = 13,
|
||||
parameter USERPORTS_DISABLE = 0,
|
||||
parameter DELAYCNTRL_DISABLE = 0,
|
||||
parameter IQCORRECTION_DISABLE = 0) (
|
||||
|
||||
// dac interface
|
||||
|
||||
input dac_clk,
|
||||
output dac_valid,
|
||||
output [47:0] dac_data,
|
||||
output dac_clksel,
|
||||
output dac_r1_mode,
|
||||
input [47:0] adc_data,
|
||||
|
||||
// delay interface
|
||||
|
||||
output [15:0] up_dld,
|
||||
output [79:0] up_dwdata,
|
||||
input [79:0] up_drdata,
|
||||
input delay_clk,
|
||||
output delay_rst,
|
||||
input delay_locked,
|
||||
|
||||
// master/slave
|
||||
|
||||
input dac_sync_enable,
|
||||
input dac_sync_in,
|
||||
output dac_sync_out,
|
||||
|
||||
// dma interface
|
||||
|
||||
output dac_enable_i0,
|
||||
output dac_valid_i0,
|
||||
input [15:0] dac_data_i0,
|
||||
output dac_enable_q0,
|
||||
output dac_valid_q0,
|
||||
input [15:0] dac_data_q0,
|
||||
output dac_enable_i1,
|
||||
output dac_valid_i1,
|
||||
input [15:0] dac_data_i1,
|
||||
output dac_enable_q1,
|
||||
output dac_valid_q1,
|
||||
input [15:0] dac_data_q1,
|
||||
input dac_dunf,
|
||||
|
||||
// gpio
|
||||
|
||||
input [31:0] up_dac_gpio_in,
|
||||
output [31:0] up_dac_gpio_out,
|
||||
|
||||
// 1PPS reporting counter and interrupt
|
||||
|
||||
input [31:0] up_pps_rcounter,
|
||||
input up_pps_status,
|
||||
output up_pps_irq_mask,
|
||||
|
||||
// processor interface
|
||||
|
||||
input up_rstn,
|
||||
input up_clk,
|
||||
input up_wreq,
|
||||
input [13:0] up_waddr,
|
||||
input [31:0] up_wdata,
|
||||
output up_wack,
|
||||
input up_rreq,
|
||||
input [13:0] up_raddr,
|
||||
output [31:0] up_rdata,
|
||||
output up_rack);
|
||||
|
||||
// configuration settings
|
||||
|
||||
localparam CONFIG = (PPS_RECEIVER_ENABLE * 256) +
|
||||
(CMOS_OR_LVDS_N * 128) +
|
||||
(DAC_DDS_DISABLE * 64) +
|
||||
(DELAYCNTRL_DISABLE * 32) +
|
||||
(MODE_1R1T * 16) +
|
||||
(USERPORTS_DISABLE * 8) +
|
||||
(IQCORRECTION_DISABLE * 1);
|
||||
|
||||
// internal registers
|
||||
|
||||
reg dac_data_sync = 'd0;
|
||||
reg [15:0] dac_rate_cnt = 'd0;
|
||||
reg dac_valid_int = 'd0;
|
||||
reg dac_valid_i0_int = 'd0;
|
||||
reg dac_valid_q0_int = 'd0;
|
||||
reg dac_valid_i1_int = 'd0;
|
||||
reg dac_valid_q1_int = 'd0;
|
||||
reg up_wack_int = 'd0;
|
||||
reg up_rack_int = 'd0;
|
||||
reg [31:0] up_rdata_int = 'd0;
|
||||
|
||||
// internal clock and resets
|
||||
|
||||
wire dac_rst;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire dac_data_sync_s;
|
||||
wire dac_dds_format_s;
|
||||
wire [15:0] dac_datarate_s;
|
||||
wire [47:0] dac_data_int_s;
|
||||
wire [ 5:0] up_wack_s;
|
||||
wire [ 5:0] up_rack_s;
|
||||
wire [31:0] up_rdata_s[0:5];
|
||||
|
||||
// master/slave
|
||||
|
||||
assign dac_data_sync_s = (ID == 0) ? dac_sync_out : dac_sync_in;
|
||||
assign dac_sync_out = dac_sync & dac_sync_enable;
|
||||
|
||||
always @(posedge dac_clk) begin
|
||||
dac_data_sync <= dac_data_sync_s;
|
||||
end
|
||||
|
||||
// rate counters and data sync signals
|
||||
|
||||
always @(posedge dac_clk) begin
|
||||
if (dac_rst == 1'b1) begin
|
||||
dac_rate_cnt <= 16'b0;
|
||||
end else begin
|
||||
if ((dac_data_sync == 1'b1) || (dac_rate_cnt == 16'd0)) begin
|
||||
dac_rate_cnt <= dac_datarate_s;
|
||||
end else begin
|
||||
dac_rate_cnt <= dac_rate_cnt - 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// dma interface
|
||||
|
||||
assign dac_valid = dac_valid_int;
|
||||
assign dac_valid_i0 = dac_valid_i0_int;
|
||||
assign dac_valid_q0 = dac_valid_q0_int;
|
||||
assign dac_valid_i1 = dac_valid_i1_int;
|
||||
assign dac_valid_q1 = dac_valid_q1_int;
|
||||
|
||||
always @(posedge dac_clk) begin
|
||||
dac_valid_int <= (dac_rate_cnt == 16'd0) ? 1'b1 : 1'b0;
|
||||
dac_valid_i0_int <= dac_valid_int;
|
||||
dac_valid_q0_int <= dac_valid_int;
|
||||
dac_valid_i1_int <= dac_valid_int & ~dac_r1_mode;
|
||||
dac_valid_q1_int <= dac_valid_int & ~dac_r1_mode;
|
||||
end
|
||||
|
||||
// processor read interface
|
||||
|
||||
assign up_wack = up_wack_int;
|
||||
assign up_rack = up_rack_int;
|
||||
assign up_rdata = up_rdata_int;
|
||||
|
||||
always @(negedge up_rstn or posedge up_clk) begin
|
||||
if (up_rstn == 0) begin
|
||||
up_wack_int <= 'd0;
|
||||
up_rack_int <= 'd0;
|
||||
up_rdata_int <= 'd0;
|
||||
end else begin
|
||||
up_wack_int <= | up_wack_s;
|
||||
up_rack_int <= | up_rack_s;
|
||||
up_rdata_int <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] |
|
||||
up_rdata_s[3] | up_rdata_s[4] | up_rdata_s[5];
|
||||
end
|
||||
end
|
||||
|
||||
// dac channel
|
||||
|
||||
axi_ad9361_tx_channel #(
|
||||
.CHANNEL_ID (0),
|
||||
.Q_OR_I_N (0),
|
||||
.DISABLE (0),
|
||||
.DAC_DDS_DISABLE (DAC_DDS_DISABLE),
|
||||
.DAC_DDS_TYPE (DAC_DDS_TYPE),
|
||||
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
|
||||
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
|
||||
.USERPORTS_DISABLE (USERPORTS_DISABLE),
|
||||
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE))
|
||||
i_tx_channel_0 (
|
||||
.dac_clk (dac_clk),
|
||||
.dac_rst (dac_rst),
|
||||
.dac_valid (dac_valid_int),
|
||||
.dma_data (dac_data_i0),
|
||||
.adc_data (adc_data[11:0]),
|
||||
.dac_data (dac_data[11:0]),
|
||||
.dac_data_out (dac_data_int_s[11:0]),
|
||||
.dac_data_in (dac_data_int_s[23:12]),
|
||||
.dac_enable (dac_enable_i0),
|
||||
.dac_data_sync (dac_data_sync),
|
||||
.dac_dds_format (dac_dds_format_s),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq),
|
||||
.up_waddr (up_waddr),
|
||||
.up_wdata (up_wdata),
|
||||
.up_wack (up_wack_s[0]),
|
||||
.up_rreq (up_rreq),
|
||||
.up_raddr (up_raddr),
|
||||
.up_rdata (up_rdata_s[0]),
|
||||
.up_rack (up_rack_s[0]));
|
||||
|
||||
// dac channel
|
||||
|
||||
axi_ad9361_tx_channel #(
|
||||
.CHANNEL_ID (1),
|
||||
.Q_OR_I_N (1),
|
||||
.DISABLE (0),
|
||||
.DAC_DDS_DISABLE (DAC_DDS_DISABLE),
|
||||
.DAC_DDS_TYPE (DAC_DDS_TYPE),
|
||||
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
|
||||
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
|
||||
.USERPORTS_DISABLE (USERPORTS_DISABLE),
|
||||
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE))
|
||||
i_tx_channel_1 (
|
||||
.dac_clk (dac_clk),
|
||||
.dac_rst (dac_rst),
|
||||
.dac_valid (dac_valid_int),
|
||||
.dma_data (dac_data_q0),
|
||||
.adc_data (adc_data[23:12]),
|
||||
.dac_data (dac_data[23:12]),
|
||||
.dac_data_out (dac_data_int_s[23:12]),
|
||||
.dac_data_in (dac_data_int_s[11:0]),
|
||||
.dac_enable (dac_enable_q0),
|
||||
.dac_data_sync (dac_data_sync),
|
||||
.dac_dds_format (dac_dds_format_s),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq),
|
||||
.up_waddr (up_waddr),
|
||||
.up_wdata (up_wdata),
|
||||
.up_wack (up_wack_s[1]),
|
||||
.up_rreq (up_rreq),
|
||||
.up_raddr (up_raddr),
|
||||
.up_rdata (up_rdata_s[1]),
|
||||
.up_rack (up_rack_s[1]));
|
||||
|
||||
// dac channel
|
||||
|
||||
axi_ad9361_tx_channel #(
|
||||
.CHANNEL_ID (2),
|
||||
.Q_OR_I_N (0),
|
||||
.DISABLE (MODE_1R1T),
|
||||
.DAC_DDS_DISABLE (DAC_DDS_DISABLE),
|
||||
.DAC_DDS_TYPE (DAC_DDS_TYPE),
|
||||
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
|
||||
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
|
||||
.USERPORTS_DISABLE (USERPORTS_DISABLE),
|
||||
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE))
|
||||
i_tx_channel_2 (
|
||||
.dac_clk (dac_clk),
|
||||
.dac_rst (dac_rst),
|
||||
.dac_valid (dac_valid_int),
|
||||
.dma_data (dac_data_i1),
|
||||
.adc_data (adc_data[35:24]),
|
||||
.dac_data (dac_data[35:24]),
|
||||
.dac_data_out (dac_data_int_s[35:24]),
|
||||
.dac_data_in (dac_data_int_s[47:36]),
|
||||
.dac_enable (dac_enable_i1),
|
||||
.dac_data_sync (dac_data_sync),
|
||||
.dac_dds_format (dac_dds_format_s),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq),
|
||||
.up_waddr (up_waddr),
|
||||
.up_wdata (up_wdata),
|
||||
.up_wack (up_wack_s[2]),
|
||||
.up_rreq (up_rreq),
|
||||
.up_raddr (up_raddr),
|
||||
.up_rdata (up_rdata_s[2]),
|
||||
.up_rack (up_rack_s[2]));
|
||||
|
||||
// dac channel
|
||||
|
||||
axi_ad9361_tx_channel #(
|
||||
.CHANNEL_ID (3),
|
||||
.Q_OR_I_N (1),
|
||||
.DISABLE (MODE_1R1T),
|
||||
.DAC_DDS_DISABLE (DAC_DDS_DISABLE),
|
||||
.DAC_DDS_TYPE (DAC_DDS_TYPE),
|
||||
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
|
||||
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
|
||||
.USERPORTS_DISABLE (USERPORTS_DISABLE),
|
||||
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE))
|
||||
i_tx_channel_3 (
|
||||
.dac_clk (dac_clk),
|
||||
.dac_rst (dac_rst),
|
||||
.dac_valid (dac_valid_int),
|
||||
.dma_data (dac_data_q1),
|
||||
.adc_data (adc_data[47:36]),
|
||||
.dac_data (dac_data[47:36]),
|
||||
.dac_data_out (dac_data_int_s[47:36]),
|
||||
.dac_data_in (dac_data_int_s[35:24]),
|
||||
.dac_enable (dac_enable_q1),
|
||||
.dac_data_sync (dac_data_sync),
|
||||
.dac_dds_format (dac_dds_format_s),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq),
|
||||
.up_waddr (up_waddr),
|
||||
.up_wdata (up_wdata),
|
||||
.up_wack (up_wack_s[3]),
|
||||
.up_rreq (up_rreq),
|
||||
.up_raddr (up_raddr),
|
||||
.up_rdata (up_rdata_s[3]),
|
||||
.up_rack (up_rack_s[3]));
|
||||
|
||||
// dac common processor interface
|
||||
|
||||
up_dac_common #(
|
||||
.ID (ID),
|
||||
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
|
||||
.FPGA_FAMILY (FPGA_FAMILY),
|
||||
.SPEED_GRADE (SPEED_GRADE),
|
||||
.DEV_PACKAGE (DEV_PACKAGE),
|
||||
.CONFIG (CONFIG),
|
||||
.CLK_EDGE_SEL (CLK_EDGE_SEL),
|
||||
.DRP_DISABLE (1),
|
||||
.USERPORTS_DISABLE (USERPORTS_DISABLE),
|
||||
.GPIO_DISABLE (0))
|
||||
i_up_dac_common (
|
||||
.mmcm_rst (),
|
||||
.dac_clk (dac_clk),
|
||||
.dac_rst (dac_rst),
|
||||
.dac_num_lanes (),
|
||||
.dac_sdr_ddr_n (),
|
||||
.dac_sync (dac_sync),
|
||||
.dac_frame (),
|
||||
.dac_clksel (dac_clksel),
|
||||
.dac_par_type (),
|
||||
.dac_par_enb (),
|
||||
.dac_r1_mode (dac_r1_mode),
|
||||
.dac_datafmt (dac_dds_format_s),
|
||||
.dac_datarate (dac_datarate_s),
|
||||
.dac_status (1'b1),
|
||||
.dac_sync_in_status (1'b1),
|
||||
.dac_status_unf (dac_dunf),
|
||||
.dac_clk_ratio (32'd1),
|
||||
.up_dac_ce (),
|
||||
.up_pps_rcounter (up_pps_rcounter),
|
||||
.up_pps_status (up_pps_status),
|
||||
.up_pps_irq_mask (up_pps_irq_mask),
|
||||
.up_drp_sel (),
|
||||
.up_drp_wr (),
|
||||
.up_drp_addr (),
|
||||
.up_drp_wdata (),
|
||||
.up_drp_rdata (32'd0),
|
||||
.up_drp_ready (1'd0),
|
||||
.up_drp_locked (1'd1),
|
||||
.up_usr_chanmax (),
|
||||
.dac_usr_chanmax (8'd3),
|
||||
.up_dac_gpio_in (up_dac_gpio_in),
|
||||
.up_dac_gpio_out (up_dac_gpio_out),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq),
|
||||
.up_waddr (up_waddr),
|
||||
.up_wdata (up_wdata),
|
||||
.up_wack (up_wack_s[4]),
|
||||
.up_rreq (up_rreq),
|
||||
.up_raddr (up_raddr),
|
||||
.up_rdata (up_rdata_s[4]),
|
||||
.up_rack (up_rack_s[4]));
|
||||
|
||||
// dac delay control
|
||||
|
||||
up_delay_cntrl #(
|
||||
.DISABLE (DELAYCNTRL_DISABLE),
|
||||
.INIT_DELAY (INIT_DELAY),
|
||||
.DATA_WIDTH(16),
|
||||
.BASE_ADDRESS(6'h12))
|
||||
i_delay_cntrl (
|
||||
.delay_clk (delay_clk),
|
||||
.delay_rst (delay_rst),
|
||||
.delay_locked (delay_locked),
|
||||
.up_dld (up_dld),
|
||||
.up_dwdata (up_dwdata),
|
||||
.up_drdata (up_drdata),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq),
|
||||
.up_waddr (up_waddr),
|
||||
.up_wdata (up_wdata),
|
||||
.up_wack (up_wack_s[5]),
|
||||
.up_rreq (up_rreq),
|
||||
.up_raddr (up_raddr),
|
||||
.up_rdata (up_rdata_s[5]),
|
||||
.up_rack (up_rack_s[5]));
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
@@ -0,0 +1,396 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module axi_ad9361_tx_channel #(
|
||||
|
||||
// parameters
|
||||
|
||||
parameter Q_OR_I_N = 0,
|
||||
parameter CHANNEL_ID = 32'h0,
|
||||
parameter DISABLE = 0,
|
||||
parameter DAC_DDS_DISABLE = 0,
|
||||
parameter DAC_DDS_TYPE = 1,
|
||||
parameter DAC_DDS_CORDIC_DW = 14,
|
||||
parameter DAC_DDS_CORDIC_PHASE_DW = 13,
|
||||
parameter USERPORTS_DISABLE = 0,
|
||||
parameter IQCORRECTION_DISABLE = 0) (
|
||||
|
||||
// dac interface
|
||||
|
||||
input dac_clk,
|
||||
input dac_rst,
|
||||
input dac_valid,
|
||||
input [15:0] dma_data,
|
||||
input [11:0] adc_data,
|
||||
output [11:0] dac_data,
|
||||
output [11:0] dac_data_out,
|
||||
input [11:0] dac_data_in,
|
||||
|
||||
// processor interface
|
||||
|
||||
output dac_enable,
|
||||
input dac_data_sync,
|
||||
input dac_dds_format,
|
||||
|
||||
// bus interface
|
||||
|
||||
input up_rstn,
|
||||
input up_clk,
|
||||
input up_wreq,
|
||||
input [13:0] up_waddr,
|
||||
input [31:0] up_wdata,
|
||||
output up_wack,
|
||||
input up_rreq,
|
||||
input [13:0] up_raddr,
|
||||
output [31:0] up_rdata,
|
||||
output up_rack);
|
||||
|
||||
// parameters
|
||||
|
||||
localparam PRBS_SEL = CHANNEL_ID;
|
||||
localparam PRBS_P09 = 0;
|
||||
localparam PRBS_P11 = 1;
|
||||
localparam PRBS_P15 = 2;
|
||||
localparam PRBS_P20 = 3;
|
||||
|
||||
// internal registers
|
||||
|
||||
reg dac_valid_sel = 'd0;
|
||||
reg dac_enable_int = 'd0;
|
||||
reg [11:0] dac_data_int = 'd0;
|
||||
reg [11:0] dac_data_out_int = 'd0;
|
||||
reg [23:0] dac_pn_seq = 'd0;
|
||||
reg [11:0] dac_pn_data = 'd0;
|
||||
reg [15:0] dac_pat_data = 'd0;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire dac_iqcor_valid_s;
|
||||
wire [15:0] dac_iqcor_data_s;
|
||||
wire [11:0] dac_dds_data_s;
|
||||
wire [15:0] dac_dds_scale_1_s;
|
||||
wire [15:0] dac_dds_init_1_s;
|
||||
wire [15:0] dac_dds_incr_1_s;
|
||||
wire [15:0] dac_dds_scale_2_s;
|
||||
wire [15:0] dac_dds_init_2_s;
|
||||
wire [15:0] dac_dds_incr_2_s;
|
||||
wire [15:0] dac_pat_data_1_s;
|
||||
wire [15:0] dac_pat_data_2_s;
|
||||
wire [ 3:0] dac_data_sel_s;
|
||||
wire dac_iqcor_enb_s;
|
||||
wire [15:0] dac_iqcor_coeff_1_s;
|
||||
wire [15:0] dac_iqcor_coeff_2_s;
|
||||
wire up_wack_s;
|
||||
wire up_rack_s;
|
||||
wire [31:0] up_rdata_s;
|
||||
|
||||
// standard prbs functions
|
||||
|
||||
function [23:0] pn1fn;
|
||||
input [23:0] din;
|
||||
reg [23:0] dout;
|
||||
begin
|
||||
case (PRBS_SEL)
|
||||
PRBS_P09: begin
|
||||
dout[23] = din[ 8] ^ din[ 4];
|
||||
dout[22] = din[ 7] ^ din[ 3];
|
||||
dout[21] = din[ 6] ^ din[ 2];
|
||||
dout[20] = din[ 5] ^ din[ 1];
|
||||
dout[19] = din[ 4] ^ din[ 0];
|
||||
dout[18] = din[ 3] ^ din[ 8] ^ din[ 4];
|
||||
dout[17] = din[ 2] ^ din[ 7] ^ din[ 3];
|
||||
dout[16] = din[ 1] ^ din[ 6] ^ din[ 2];
|
||||
dout[15] = din[ 0] ^ din[ 5] ^ din[ 1];
|
||||
dout[14] = din[ 8] ^ din[ 0];
|
||||
dout[13] = din[ 7] ^ din[ 8] ^ din[ 4];
|
||||
dout[12] = din[ 6] ^ din[ 7] ^ din[ 3];
|
||||
dout[11] = din[ 5] ^ din[ 6] ^ din[ 2];
|
||||
dout[10] = din[ 4] ^ din[ 5] ^ din[ 1];
|
||||
dout[ 9] = din[ 3] ^ din[ 4] ^ din[ 0];
|
||||
dout[ 8] = din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4];
|
||||
dout[ 7] = din[ 1] ^ din[ 2] ^ din[ 7] ^ din[ 3];
|
||||
dout[ 6] = din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 2];
|
||||
dout[ 5] = din[ 8] ^ din[ 0] ^ din[ 4] ^ din[ 5] ^ din[ 1];
|
||||
dout[ 4] = din[ 7] ^ din[ 8] ^ din[ 3] ^ din[ 0];
|
||||
dout[ 3] = din[ 6] ^ din[ 7] ^ din[ 2] ^ din[ 8] ^ din[ 4];
|
||||
dout[ 2] = din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 7] ^ din[ 3];
|
||||
dout[ 1] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6] ^ din[ 2];
|
||||
dout[ 0] = din[ 3] ^ din[ 8] ^ din[ 5] ^ din[ 1];
|
||||
end
|
||||
PRBS_P11: begin
|
||||
dout[23] = din[10] ^ din[ 8];
|
||||
dout[22] = din[ 9] ^ din[ 7];
|
||||
dout[21] = din[ 8] ^ din[ 6];
|
||||
dout[20] = din[ 7] ^ din[ 5];
|
||||
dout[19] = din[ 6] ^ din[ 4];
|
||||
dout[18] = din[ 5] ^ din[ 3];
|
||||
dout[17] = din[ 4] ^ din[ 2];
|
||||
dout[16] = din[ 3] ^ din[ 1];
|
||||
dout[15] = din[ 2] ^ din[ 0];
|
||||
dout[14] = din[ 1] ^ din[10] ^ din[ 8];
|
||||
dout[13] = din[ 0] ^ din[ 9] ^ din[ 7];
|
||||
dout[12] = din[10] ^ din[ 6];
|
||||
dout[11] = din[ 9] ^ din[ 5];
|
||||
dout[10] = din[ 8] ^ din[ 4];
|
||||
dout[ 9] = din[ 7] ^ din[ 3];
|
||||
dout[ 8] = din[ 6] ^ din[ 2];
|
||||
dout[ 7] = din[ 5] ^ din[ 1];
|
||||
dout[ 6] = din[ 4] ^ din[ 0];
|
||||
dout[ 5] = din[ 3] ^ din[10] ^ din[ 8];
|
||||
dout[ 4] = din[ 2] ^ din[ 9] ^ din[ 7];
|
||||
dout[ 3] = din[ 1] ^ din[ 8] ^ din[ 6];
|
||||
dout[ 2] = din[ 0] ^ din[ 7] ^ din[ 5];
|
||||
dout[ 1] = din[10] ^ din[ 6] ^ din[ 8] ^ din[ 4];
|
||||
dout[ 0] = din[ 9] ^ din[ 5] ^ din[ 7] ^ din[ 3];
|
||||
end
|
||||
PRBS_P15: begin
|
||||
dout[23] = din[14] ^ din[13];
|
||||
dout[22] = din[13] ^ din[12];
|
||||
dout[21] = din[12] ^ din[11];
|
||||
dout[20] = din[11] ^ din[10];
|
||||
dout[19] = din[10] ^ din[ 9];
|
||||
dout[18] = din[ 9] ^ din[ 8];
|
||||
dout[17] = din[ 8] ^ din[ 7];
|
||||
dout[16] = din[ 7] ^ din[ 6];
|
||||
dout[15] = din[ 6] ^ din[ 5];
|
||||
dout[14] = din[ 5] ^ din[ 4];
|
||||
dout[13] = din[ 4] ^ din[ 3];
|
||||
dout[12] = din[ 3] ^ din[ 2];
|
||||
dout[11] = din[ 2] ^ din[ 1];
|
||||
dout[10] = din[ 1] ^ din[ 0];
|
||||
dout[ 9] = din[ 0] ^ din[14] ^ din[13];
|
||||
dout[ 8] = din[14] ^ din[12];
|
||||
dout[ 7] = din[13] ^ din[11];
|
||||
dout[ 6] = din[12] ^ din[10];
|
||||
dout[ 5] = din[11] ^ din[ 9];
|
||||
dout[ 4] = din[10] ^ din[ 8];
|
||||
dout[ 3] = din[ 9] ^ din[ 7];
|
||||
dout[ 2] = din[ 8] ^ din[ 6];
|
||||
dout[ 1] = din[ 7] ^ din[ 5];
|
||||
dout[ 0] = din[ 6] ^ din[ 4];
|
||||
end
|
||||
PRBS_P20: begin
|
||||
dout[23] = din[19] ^ din[ 2];
|
||||
dout[22] = din[18] ^ din[ 1];
|
||||
dout[21] = din[17] ^ din[ 0];
|
||||
dout[20] = din[16] ^ din[19] ^ din[ 2];
|
||||
dout[19] = din[15] ^ din[18] ^ din[ 1];
|
||||
dout[18] = din[14] ^ din[17] ^ din[ 0];
|
||||
dout[17] = din[13] ^ din[16] ^ din[19] ^ din[ 2];
|
||||
dout[16] = din[12] ^ din[15] ^ din[18] ^ din[ 1];
|
||||
dout[15] = din[11] ^ din[14] ^ din[17] ^ din[ 0];
|
||||
dout[14] = din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2];
|
||||
dout[13] = din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1];
|
||||
dout[12] = din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0];
|
||||
dout[11] = din[ 7] ^ din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2];
|
||||
dout[10] = din[ 6] ^ din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1];
|
||||
dout[ 9] = din[ 5] ^ din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0];
|
||||
dout[ 8] = din[ 4] ^ din[ 7] ^ din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2];
|
||||
dout[ 7] = din[ 3] ^ din[ 6] ^ din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1];
|
||||
dout[ 6] = din[ 2] ^ din[ 5] ^ din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0];
|
||||
dout[ 5] = din[ 1] ^ din[ 4] ^ din[ 7] ^ din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2];
|
||||
dout[ 4] = din[ 0] ^ din[ 3] ^ din[ 6] ^ din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1];
|
||||
dout[ 3] = din[19] ^ din[ 5] ^ din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0];
|
||||
dout[ 2] = din[18] ^ din[ 4] ^ din[ 7] ^ din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2];
|
||||
dout[ 1] = din[17] ^ din[ 3] ^ din[ 6] ^ din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1];
|
||||
dout[ 0] = din[16] ^ din[ 2] ^ din[ 5] ^ din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0];
|
||||
end
|
||||
endcase
|
||||
pn1fn = dout;
|
||||
end
|
||||
endfunction
|
||||
|
||||
// global toggle
|
||||
|
||||
always @(posedge dac_clk) begin
|
||||
if (dac_data_sync == 1'b1) begin
|
||||
dac_valid_sel <= 1'b0;
|
||||
end else if (dac_valid == 1'b1) begin
|
||||
dac_valid_sel <= ~dac_valid_sel;
|
||||
end
|
||||
end
|
||||
|
||||
// dac iq correction
|
||||
|
||||
assign dac_enable = (DISABLE == 1) ? 1'd0 : dac_enable_int;
|
||||
assign dac_data = (DISABLE == 1) ? 12'd0 : dac_data_int;
|
||||
|
||||
always @(posedge dac_clk) begin
|
||||
dac_enable_int <= (dac_data_sel_s == 4'h2) ? 1'b1 : 1'b0;
|
||||
if (dac_iqcor_valid_s == 1'b1) begin
|
||||
dac_data_int <= dac_iqcor_data_s[15:4];
|
||||
end
|
||||
end
|
||||
|
||||
ad_iqcor #(
|
||||
.Q_OR_I_N (Q_OR_I_N),
|
||||
.DISABLE (IQCORRECTION_DISABLE))
|
||||
i_ad_iqcor (
|
||||
.clk (dac_clk),
|
||||
.valid (dac_valid),
|
||||
.data_in ({dac_data_out_int, 4'd0}),
|
||||
.data_iq ({dac_data_in, 4'd0}),
|
||||
.valid_out (dac_iqcor_valid_s),
|
||||
.data_out (dac_iqcor_data_s),
|
||||
.iqcor_enable (dac_iqcor_enb_s),
|
||||
.iqcor_coeff_1 (dac_iqcor_coeff_1_s),
|
||||
.iqcor_coeff_2 (dac_iqcor_coeff_2_s));
|
||||
|
||||
// dac mux
|
||||
|
||||
assign dac_data_out = (DISABLE == 1) ? 12'd0 : dac_data_out_int;
|
||||
|
||||
always @(posedge dac_clk) begin
|
||||
case (dac_data_sel_s)
|
||||
4'h9: dac_data_out_int <= dac_pn_data;
|
||||
4'h8: dac_data_out_int <= adc_data;
|
||||
4'h3: dac_data_out_int <= 12'd0;
|
||||
4'h2: dac_data_out_int <= dma_data[15:4];
|
||||
4'h1: dac_data_out_int <= dac_pat_data[15:4];
|
||||
default: dac_data_out_int <= dac_dds_data_s;
|
||||
endcase
|
||||
end
|
||||
|
||||
// prbs sequences
|
||||
|
||||
always @(posedge dac_clk) begin
|
||||
if (dac_data_sync == 1'b1) begin
|
||||
dac_pn_seq <= 24'hffffff;
|
||||
dac_pn_data <= 12'd0;
|
||||
end else if (dac_valid == 1'b1) begin
|
||||
if (dac_valid_sel == 1'b1) begin
|
||||
dac_pn_seq <= pn1fn(dac_pn_seq);
|
||||
dac_pn_data <= dac_pn_seq[11: 0];
|
||||
end else begin
|
||||
dac_pn_seq <= dac_pn_seq;
|
||||
dac_pn_data <= dac_pn_seq[23:12];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// pattern
|
||||
|
||||
always @(posedge dac_clk) begin
|
||||
if (dac_valid == 1'b1) begin
|
||||
if (dac_valid_sel == 1'b0) begin
|
||||
dac_pat_data <= dac_pat_data_1_s;
|
||||
end else begin
|
||||
dac_pat_data <= dac_pat_data_2_s;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// dds
|
||||
|
||||
ad_dds #(
|
||||
.DISABLE (DAC_DDS_DISABLE),
|
||||
.DDS_DW (12),
|
||||
.PHASE_DW (16),
|
||||
.DDS_TYPE (DAC_DDS_TYPE),
|
||||
.CORDIC_DW (DAC_DDS_CORDIC_DW),
|
||||
.CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
|
||||
.CLK_RATIO (1))
|
||||
i_dds (
|
||||
.clk (dac_clk),
|
||||
.dac_dds_format (dac_dds_format),
|
||||
.dac_data_sync (dac_data_sync),
|
||||
.dac_valid (dac_valid),
|
||||
.tone_1_scale (dac_dds_scale_1_s),
|
||||
.tone_2_scale (dac_dds_scale_2_s),
|
||||
.tone_1_init_offset (dac_dds_init_1_s),
|
||||
.tone_2_init_offset (dac_dds_init_2_s),
|
||||
.tone_1_freq_word (dac_dds_incr_1_s),
|
||||
.tone_2_freq_word (dac_dds_incr_2_s),
|
||||
.dac_dds_data (dac_dds_data_s));
|
||||
|
||||
// single channel processor
|
||||
|
||||
assign up_wack = (DISABLE == 1) ? 1'd0 : up_wack_s;
|
||||
assign up_rack = (DISABLE == 1) ? 1'd0 : up_rack_s;
|
||||
assign up_rdata = (DISABLE == 1) ? 32'd0 : up_rdata_s;
|
||||
|
||||
up_dac_channel #(
|
||||
.COMMON_ID (6'h11),
|
||||
.CHANNEL_ID (CHANNEL_ID),
|
||||
.DDS_DISABLE (DAC_DDS_DISABLE),
|
||||
.USERPORTS_DISABLE (USERPORTS_DISABLE),
|
||||
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE))
|
||||
i_up_dac_channel (
|
||||
.dac_clk (dac_clk),
|
||||
.dac_rst (dac_rst),
|
||||
.dac_dds_scale_1 (dac_dds_scale_1_s),
|
||||
.dac_dds_init_1 (dac_dds_init_1_s),
|
||||
.dac_dds_incr_1 (dac_dds_incr_1_s),
|
||||
.dac_dds_scale_2 (dac_dds_scale_2_s),
|
||||
.dac_dds_init_2 (dac_dds_init_2_s),
|
||||
.dac_dds_incr_2 (dac_dds_incr_2_s),
|
||||
.dac_pat_data_1 (dac_pat_data_1_s),
|
||||
.dac_pat_data_2 (dac_pat_data_2_s),
|
||||
.dac_data_sel (dac_data_sel_s),
|
||||
.dac_iq_mode (),
|
||||
.dac_iqcor_enb (dac_iqcor_enb_s),
|
||||
.dac_iqcor_coeff_1 (dac_iqcor_coeff_1_s),
|
||||
.dac_iqcor_coeff_2 (dac_iqcor_coeff_2_s),
|
||||
.up_usr_datatype_be (),
|
||||
.up_usr_datatype_signed (),
|
||||
.up_usr_datatype_shift (),
|
||||
.up_usr_datatype_total_bits (),
|
||||
.up_usr_datatype_bits (),
|
||||
.up_usr_interpolation_m (),
|
||||
.up_usr_interpolation_n (),
|
||||
.dac_usr_datatype_be (1'b0),
|
||||
.dac_usr_datatype_signed (1'b1),
|
||||
.dac_usr_datatype_shift (8'd0),
|
||||
.dac_usr_datatype_total_bits (8'd16),
|
||||
.dac_usr_datatype_bits (8'd16),
|
||||
.dac_usr_interpolation_m (16'd1),
|
||||
.dac_usr_interpolation_n (16'd1),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq),
|
||||
.up_waddr (up_waddr),
|
||||
.up_wdata (up_wdata),
|
||||
.up_wack (up_wack_s),
|
||||
.up_rreq (up_rreq),
|
||||
.up_raddr (up_raddr),
|
||||
.up_rdata (up_rdata_s),
|
||||
.up_rack (up_rack_s));
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
@@ -0,0 +1,47 @@
|
||||
# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!
|
||||
proc init {cellpath otherInfo} {
|
||||
set ip [get_bd_cells $cellpath]
|
||||
|
||||
bd::mark_propagate_only $ip " \
|
||||
DEV_PACKAGE \
|
||||
SPEED_GRADE \
|
||||
FPGA_FAMILY \
|
||||
FPGA_TECHNOLOGY"
|
||||
|
||||
adi_auto_assign_device_spec $cellpath
|
||||
}
|
||||
|
||||
# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)
|
||||
proc adi_auto_assign_device_spec {cellpath} {
|
||||
|
||||
set ip [get_bd_cells $cellpath]
|
||||
set ip_param_list [list_property $ip]
|
||||
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
|
||||
|
||||
set parent_dir "../"
|
||||
for {set x 1} {$x<=4} {incr x} {
|
||||
set linkname ${ip_path}${parent_dir}scripts/adi_xilinx_device_info_enc.tcl
|
||||
if { [file exists $linkname] } {
|
||||
source ${ip_path}${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl
|
||||
break
|
||||
}
|
||||
append parent_dir "../"
|
||||
}
|
||||
|
||||
# Find predefindes auto assignable parameters
|
||||
foreach i $auto_set_param_list {
|
||||
if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
|
||||
set val [adi_device_spec $cellpath $i]
|
||||
set_property CONFIG.$i $val $ip
|
||||
}
|
||||
}
|
||||
|
||||
# Find predefindes auto assignable/overwritable parameters
|
||||
foreach i $auto_set_param_list_overwritable {
|
||||
if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
|
||||
set val [adi_device_spec $cellpath $i]
|
||||
set_property CONFIG.$i $val $ip
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,200 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module axi_ad9361_alt_lvds_rx (
|
||||
|
||||
// physical interface (receive)
|
||||
|
||||
rx_clk_in_p,
|
||||
rx_clk_in_n,
|
||||
rx_frame_in_p,
|
||||
rx_frame_in_n,
|
||||
rx_data_in_p,
|
||||
rx_data_in_n,
|
||||
|
||||
// data interface
|
||||
|
||||
clk,
|
||||
rx_frame,
|
||||
rx_data_0,
|
||||
rx_data_1,
|
||||
rx_data_2,
|
||||
rx_data_3,
|
||||
rx_locked);
|
||||
|
||||
// physical interface (receive)
|
||||
|
||||
input rx_clk_in_p;
|
||||
input rx_clk_in_n;
|
||||
input rx_frame_in_p;
|
||||
input rx_frame_in_n;
|
||||
input [ 5:0] rx_data_in_p;
|
||||
input [ 5:0] rx_data_in_n;
|
||||
|
||||
// data interface
|
||||
|
||||
output clk;
|
||||
output [ 3:0] rx_frame;
|
||||
output [ 5:0] rx_data_0;
|
||||
output [ 5:0] rx_data_1;
|
||||
output [ 5:0] rx_data_2;
|
||||
output [ 5:0] rx_data_3;
|
||||
output rx_locked;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire [27:0] rx_data_s;
|
||||
|
||||
// instantiations
|
||||
|
||||
assign rx_frame[3] = rx_data_s[24];
|
||||
assign rx_frame[2] = rx_data_s[25];
|
||||
assign rx_frame[1] = rx_data_s[26];
|
||||
assign rx_frame[0] = rx_data_s[27];
|
||||
assign rx_data_3[5] = rx_data_s[20];
|
||||
assign rx_data_3[4] = rx_data_s[16];
|
||||
assign rx_data_3[3] = rx_data_s[12];
|
||||
assign rx_data_3[2] = rx_data_s[ 8];
|
||||
assign rx_data_3[1] = rx_data_s[ 4];
|
||||
assign rx_data_3[0] = rx_data_s[ 0];
|
||||
assign rx_data_2[5] = rx_data_s[21];
|
||||
assign rx_data_2[4] = rx_data_s[17];
|
||||
assign rx_data_2[3] = rx_data_s[13];
|
||||
assign rx_data_2[2] = rx_data_s[ 9];
|
||||
assign rx_data_2[1] = rx_data_s[ 5];
|
||||
assign rx_data_2[0] = rx_data_s[ 1];
|
||||
assign rx_data_1[5] = rx_data_s[22];
|
||||
assign rx_data_1[4] = rx_data_s[18];
|
||||
assign rx_data_1[3] = rx_data_s[14];
|
||||
assign rx_data_1[2] = rx_data_s[10];
|
||||
assign rx_data_1[1] = rx_data_s[ 6];
|
||||
assign rx_data_1[0] = rx_data_s[ 2];
|
||||
assign rx_data_0[5] = rx_data_s[23];
|
||||
assign rx_data_0[4] = rx_data_s[19];
|
||||
assign rx_data_0[3] = rx_data_s[15];
|
||||
assign rx_data_0[2] = rx_data_s[11];
|
||||
assign rx_data_0[1] = rx_data_s[ 7];
|
||||
assign rx_data_0[0] = rx_data_s[ 3];
|
||||
|
||||
altlvds_rx #(
|
||||
.buffer_implementation ("RAM"),
|
||||
.cds_mode ("UNUSED"),
|
||||
.common_rx_tx_pll ("ON"),
|
||||
.data_align_rollover (4),
|
||||
.data_rate ("500.0 Mbps"),
|
||||
.deserialization_factor (4),
|
||||
.dpa_initial_phase_value (0),
|
||||
.dpll_lock_count (0),
|
||||
.dpll_lock_window (0),
|
||||
.enable_clock_pin_mode ("UNUSED"),
|
||||
.enable_dpa_align_to_rising_edge_only ("OFF"),
|
||||
.enable_dpa_calibration ("ON"),
|
||||
.enable_dpa_fifo ("UNUSED"),
|
||||
.enable_dpa_initial_phase_selection ("OFF"),
|
||||
.enable_dpa_mode ("OFF"),
|
||||
.enable_dpa_pll_calibration ("OFF"),
|
||||
.enable_soft_cdr_mode ("OFF"),
|
||||
.implement_in_les ("OFF"),
|
||||
.inclock_boost (0),
|
||||
.inclock_data_alignment ("EDGE_ALIGNED"),
|
||||
.inclock_period (4000),
|
||||
.inclock_phase_shift (0),
|
||||
.input_data_rate (500),
|
||||
.intended_device_family ("Cyclone V"),
|
||||
.lose_lock_on_one_change ("UNUSED"),
|
||||
.lpm_hint ("CBX_MODULE_PREFIX=axi_ad9361_alt_lvds_rx"),
|
||||
.lpm_type ("altlvds_rx"),
|
||||
.number_of_channels (7),
|
||||
.outclock_resource ("Regional clock"),
|
||||
.pll_operation_mode ("NORMAL"),
|
||||
.pll_self_reset_on_loss_lock ("UNUSED"),
|
||||
.port_rx_channel_data_align ("PORT_UNUSED"),
|
||||
.port_rx_data_align ("PORT_UNUSED"),
|
||||
.refclk_frequency ("250.000000 MHz"),
|
||||
.registered_data_align_input ("UNUSED"),
|
||||
.registered_output ("ON"),
|
||||
.reset_fifo_at_first_lock ("UNUSED"),
|
||||
.rx_align_data_reg ("RISING_EDGE"),
|
||||
.sim_dpa_is_negative_ppm_drift ("OFF"),
|
||||
.sim_dpa_net_ppm_variation (0),
|
||||
.sim_dpa_output_clock_phase_shift (0),
|
||||
.use_coreclock_input ("OFF"),
|
||||
.use_dpll_rawperror ("OFF"),
|
||||
.use_external_pll ("OFF"),
|
||||
.use_no_phase_shift ("ON"),
|
||||
.x_on_bitslip ("ON"),
|
||||
.clk_src_is_pll ("off"))
|
||||
i_altlvds_rx (
|
||||
.rx_inclock (rx_clk_in_p),
|
||||
.rx_in ({rx_frame_in_p, rx_data_in_p}),
|
||||
.rx_outclock (clk),
|
||||
.rx_out (rx_data_s),
|
||||
.rx_locked (rx_locked),
|
||||
.dpa_pll_cal_busy (),
|
||||
.dpa_pll_recal (1'b0),
|
||||
.pll_areset (1'b0),
|
||||
.pll_phasecounterselect (),
|
||||
.pll_phasedone (1'b1),
|
||||
.pll_phasestep (),
|
||||
.pll_phaseupdown (),
|
||||
.pll_scanclk (),
|
||||
.rx_cda_max (),
|
||||
.rx_cda_reset ({7{1'b0}}),
|
||||
.rx_channel_data_align ({7{1'b0}}),
|
||||
.rx_coreclk ({7{1'b1}}),
|
||||
.rx_data_align (1'b0),
|
||||
.rx_data_align_reset (1'b0),
|
||||
.rx_data_reset (1'b0),
|
||||
.rx_deskew (1'b0),
|
||||
.rx_divfwdclk (),
|
||||
.rx_dpa_lock_reset ({7{1'b0}}),
|
||||
.rx_dpa_locked (),
|
||||
.rx_dpaclock (1'b0),
|
||||
.rx_dpll_enable ({7{1'b1}}),
|
||||
.rx_dpll_hold ({7{1'b0}}),
|
||||
.rx_dpll_reset ({7{1'b0}}),
|
||||
.rx_enable (1'b1),
|
||||
.rx_fifo_reset ({7{1'b0}}),
|
||||
.rx_pll_enable (1'b1),
|
||||
.rx_readclock (1'b0),
|
||||
.rx_reset ({7{1'b0}}),
|
||||
.rx_syncclock (1'b0));
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
@@ -0,0 +1,184 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module axi_ad9361_alt_lvds_tx (
|
||||
|
||||
// physical interface (transmit)
|
||||
|
||||
tx_clk_out_p,
|
||||
tx_clk_out_n,
|
||||
tx_frame_out_p,
|
||||
tx_frame_out_n,
|
||||
tx_data_out_p,
|
||||
tx_data_out_n,
|
||||
|
||||
// data interface
|
||||
|
||||
tx_clk,
|
||||
clk,
|
||||
tx_frame,
|
||||
tx_data_0,
|
||||
tx_data_1,
|
||||
tx_data_2,
|
||||
tx_data_3,
|
||||
tx_locked);
|
||||
|
||||
// physical interface (transmit)
|
||||
|
||||
output tx_clk_out_p;
|
||||
output tx_clk_out_n;
|
||||
output tx_frame_out_p;
|
||||
output tx_frame_out_n;
|
||||
output [ 5:0] tx_data_out_p;
|
||||
output [ 5:0] tx_data_out_n;
|
||||
|
||||
// data interface
|
||||
|
||||
input tx_clk;
|
||||
input clk;
|
||||
input [ 3:0] tx_frame;
|
||||
input [ 5:0] tx_data_0;
|
||||
input [ 5:0] tx_data_1;
|
||||
input [ 5:0] tx_data_2;
|
||||
input [ 5:0] tx_data_3;
|
||||
output tx_locked;
|
||||
|
||||
// internal registers
|
||||
|
||||
reg [27:0] tx_data_n = 'd0;
|
||||
reg [27:0] tx_data_p = 'd0;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire core_clk;
|
||||
wire [27:0] tx_data_s;
|
||||
|
||||
// instantiations
|
||||
|
||||
assign tx_clk_out_n = 1'd0;
|
||||
assign tx_frame_out_n = 1'd0;
|
||||
assign tx_data_out_n = 6'd0;
|
||||
|
||||
assign tx_data_s[24] = tx_frame[3];
|
||||
assign tx_data_s[25] = tx_frame[2];
|
||||
assign tx_data_s[26] = tx_frame[1];
|
||||
assign tx_data_s[27] = tx_frame[0];
|
||||
assign tx_data_s[20] = tx_data_3[5];
|
||||
assign tx_data_s[16] = tx_data_3[4];
|
||||
assign tx_data_s[12] = tx_data_3[3];
|
||||
assign tx_data_s[ 8] = tx_data_3[2];
|
||||
assign tx_data_s[ 4] = tx_data_3[1];
|
||||
assign tx_data_s[ 0] = tx_data_3[0];
|
||||
assign tx_data_s[21] = tx_data_2[5];
|
||||
assign tx_data_s[17] = tx_data_2[4];
|
||||
assign tx_data_s[13] = tx_data_2[3];
|
||||
assign tx_data_s[ 9] = tx_data_2[2];
|
||||
assign tx_data_s[ 5] = tx_data_2[1];
|
||||
assign tx_data_s[ 1] = tx_data_2[0];
|
||||
assign tx_data_s[22] = tx_data_1[5];
|
||||
assign tx_data_s[18] = tx_data_1[4];
|
||||
assign tx_data_s[14] = tx_data_1[3];
|
||||
assign tx_data_s[10] = tx_data_1[2];
|
||||
assign tx_data_s[ 6] = tx_data_1[1];
|
||||
assign tx_data_s[ 2] = tx_data_1[0];
|
||||
assign tx_data_s[23] = tx_data_0[5];
|
||||
assign tx_data_s[19] = tx_data_0[4];
|
||||
assign tx_data_s[15] = tx_data_0[3];
|
||||
assign tx_data_s[11] = tx_data_0[2];
|
||||
assign tx_data_s[ 7] = tx_data_0[1];
|
||||
assign tx_data_s[ 3] = tx_data_0[0];
|
||||
|
||||
always @(negedge clk) begin
|
||||
tx_data_n <= tx_data_s;
|
||||
end
|
||||
|
||||
always @(posedge core_clk) begin
|
||||
tx_data_p <= tx_data_n;
|
||||
end
|
||||
|
||||
altlvds_tx #(
|
||||
.center_align_msb ("UNUSED"),
|
||||
.common_rx_tx_pll ("ON"),
|
||||
.coreclock_divide_by (1),
|
||||
.data_rate ("500.0 Mbps"),
|
||||
.deserialization_factor (4),
|
||||
.differential_drive (0),
|
||||
.enable_clock_pin_mode ("UNUSED"),
|
||||
.implement_in_les ("OFF"),
|
||||
.inclock_boost (0),
|
||||
.inclock_data_alignment ("EDGE_ALIGNED"),
|
||||
.inclock_period (4000),
|
||||
.inclock_phase_shift (0),
|
||||
.intended_device_family ("Cyclone V"),
|
||||
.lpm_hint ("CBX_MODULE_PREFIX=axi_ad9361_alt_lvds_tx"),
|
||||
.lpm_type ("altlvds_tx"),
|
||||
.multi_clock ("OFF"),
|
||||
.number_of_channels (7),
|
||||
.outclock_alignment ("EDGE_ALIGNED"),
|
||||
.outclock_divide_by (2),
|
||||
.outclock_duty_cycle (50),
|
||||
.outclock_multiply_by (1),
|
||||
.outclock_phase_shift (0),
|
||||
.outclock_resource ("Regional clock"),
|
||||
.output_data_rate (500),
|
||||
.pll_compensation_mode ("AUTO"),
|
||||
.pll_self_reset_on_loss_lock ("OFF"),
|
||||
.preemphasis_setting (0),
|
||||
.refclk_frequency ("250.000000 MHz"),
|
||||
.registered_input ("TX_CORECLK"),
|
||||
.use_external_pll ("OFF"),
|
||||
.use_no_phase_shift ("ON"),
|
||||
.vod_setting (0),
|
||||
.clk_src_is_pll ("off"))
|
||||
i_altlvds_tx (
|
||||
.tx_inclock (tx_clk),
|
||||
.tx_coreclock (core_clk),
|
||||
.tx_in (tx_data_p),
|
||||
.tx_outclock (tx_clk_out_p),
|
||||
.tx_out ({tx_frame_out_p, tx_data_out_p}),
|
||||
.tx_locked (tx_locked),
|
||||
.pll_areset (1'b0),
|
||||
.sync_inclock (1'b0),
|
||||
.tx_data_reset (1'b0),
|
||||
.tx_enable (1'b1),
|
||||
.tx_pll_enable (1'b1),
|
||||
.tx_syncclock (1'b0));
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
@@ -0,0 +1,141 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module axi_ad9361_cmos_if #(
|
||||
|
||||
parameter FPGA_TECHNOLOGY = 0,
|
||||
parameter DAC_IODELAY_ENABLE = 0,
|
||||
parameter CLK_DESKEW = 0,
|
||||
parameter USE_SSI_CLK = 1,
|
||||
|
||||
// Dummy parameters, required keep the code consistency(used on Xilinx)
|
||||
parameter IO_DELAY_GROUP = "dev_if_delay_group",
|
||||
parameter DELAY_REFCLK_FREQUENCY = 0) (
|
||||
|
||||
// physical interface (receive)
|
||||
|
||||
input rx_clk_in,
|
||||
input rx_frame_in,
|
||||
input [11:0] rx_data_in,
|
||||
|
||||
// physical interface (transmit)
|
||||
|
||||
output tx_clk_out,
|
||||
output tx_frame_out,
|
||||
output [11:0] tx_data_out,
|
||||
|
||||
// ensm control
|
||||
|
||||
output enable,
|
||||
output txnrx,
|
||||
|
||||
// clock (common to both receive and transmit)
|
||||
|
||||
input rst,
|
||||
input clk,
|
||||
output l_clk,
|
||||
|
||||
// receive data path interface
|
||||
|
||||
output adc_valid,
|
||||
output [47:0] adc_data,
|
||||
output adc_status,
|
||||
input adc_r1_mode,
|
||||
input adc_ddr_edgesel,
|
||||
|
||||
// transmit data path interface
|
||||
|
||||
input dac_valid,
|
||||
input [47:0] dac_data,
|
||||
input dac_clksel,
|
||||
input dac_r1_mode,
|
||||
|
||||
// tdd interface
|
||||
|
||||
input tdd_enable,
|
||||
input tdd_txnrx,
|
||||
input tdd_mode,
|
||||
|
||||
// delay interface
|
||||
|
||||
input mmcm_rst,
|
||||
input up_clk,
|
||||
input up_rstn,
|
||||
input up_enable,
|
||||
input up_txnrx,
|
||||
input [12:0] up_adc_dld,
|
||||
input [64:0] up_adc_dwdata,
|
||||
output [64:0] up_adc_drdata,
|
||||
input [15:0] up_dac_dld,
|
||||
input [79:0] up_dac_dwdata,
|
||||
output [79:0] up_dac_drdata,
|
||||
input delay_clk,
|
||||
input delay_rst,
|
||||
output delay_locked,
|
||||
|
||||
// drp interface
|
||||
|
||||
input up_drp_sel,
|
||||
input up_drp_wr,
|
||||
input [11:0] up_drp_addr,
|
||||
input [31:0] up_drp_wdata,
|
||||
output [31:0] up_drp_rdata,
|
||||
output up_drp_ready,
|
||||
output up_drp_locked);
|
||||
|
||||
// cmos is not supported on intel platforms yet.
|
||||
|
||||
assign tx_clk_out = 1'd0;
|
||||
assign tx_frame_out = 1'd0;
|
||||
assign tx_data_out = 12'd0;
|
||||
assign enable = 1'd0;
|
||||
assign txnrx = 1'd0;
|
||||
assign l_clk = 1'd0;
|
||||
assign adc_valid = 1'd0;
|
||||
assign adc_data = 48'd0;
|
||||
assign adc_status = 1'd0;
|
||||
assign up_adc_drdata = 65'd0;
|
||||
assign up_dac_drdata = 80'd0;
|
||||
assign delay_locked = 1'd0;
|
||||
assign up_drp_rdata = 32'd0;
|
||||
assign up_drp_ready = 1'd0;
|
||||
assign up_drp_locked = 1'd0;
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
@@ -0,0 +1,571 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module axi_ad9361_lvds_if #(
|
||||
|
||||
parameter FPGA_TECHNOLOGY = 0,
|
||||
parameter DAC_IODELAY_ENABLE = 0,
|
||||
parameter CLK_DESKEW = 0,
|
||||
|
||||
// Dummy parameters, required keep the code consistency(used on Xilinx)
|
||||
parameter USE_SSI_CLK = 1,
|
||||
parameter IO_DELAY_GROUP = "dev_if_delay_group",
|
||||
parameter DELAY_REFCLK_FREQUENCY = 0,
|
||||
parameter RX_NODPA = 0) (
|
||||
|
||||
// physical interface (receive)
|
||||
|
||||
input rx_clk_in_p,
|
||||
input rx_clk_in_n,
|
||||
input rx_frame_in_p,
|
||||
input rx_frame_in_n,
|
||||
input [ 5:0] rx_data_in_p,
|
||||
input [ 5:0] rx_data_in_n,
|
||||
|
||||
// physical interface (transmit)
|
||||
|
||||
output tx_clk_out_p,
|
||||
output tx_clk_out_n,
|
||||
output tx_frame_out_p,
|
||||
output tx_frame_out_n,
|
||||
output [ 5:0] tx_data_out_p,
|
||||
output [ 5:0] tx_data_out_n,
|
||||
|
||||
// ensm control
|
||||
|
||||
output enable,
|
||||
output txnrx,
|
||||
|
||||
// clock (common to both receive and transmit)
|
||||
|
||||
input rst,
|
||||
input clk,
|
||||
output l_clk,
|
||||
|
||||
// receive data path interface
|
||||
|
||||
output adc_valid,
|
||||
output [47:0] adc_data,
|
||||
output adc_status,
|
||||
input adc_r1_mode,
|
||||
input adc_ddr_edgesel,
|
||||
|
||||
// transmit data path interface
|
||||
|
||||
input dac_valid,
|
||||
input [47:0] dac_data,
|
||||
input dac_clksel,
|
||||
input dac_r1_mode,
|
||||
|
||||
// tdd interface
|
||||
|
||||
input tdd_enable,
|
||||
input tdd_txnrx,
|
||||
input tdd_mode,
|
||||
|
||||
// delay interface
|
||||
|
||||
input mmcm_rst,
|
||||
input up_clk,
|
||||
input up_rstn,
|
||||
input up_enable,
|
||||
input up_txnrx,
|
||||
input [ 6:0] up_adc_dld,
|
||||
input [34:0] up_adc_dwdata,
|
||||
output [34:0] up_adc_drdata,
|
||||
input [ 9:0] up_dac_dld,
|
||||
input [49:0] up_dac_dwdata,
|
||||
output [49:0] up_dac_drdata,
|
||||
input delay_clk,
|
||||
input delay_rst,
|
||||
output delay_locked,
|
||||
|
||||
// drp interface
|
||||
|
||||
input up_drp_sel,
|
||||
input up_drp_wr,
|
||||
input [11:0] up_drp_addr,
|
||||
input [31:0] up_drp_wdata,
|
||||
output [31:0] up_drp_rdata,
|
||||
output up_drp_ready,
|
||||
output up_drp_locked);
|
||||
|
||||
// internal registers
|
||||
|
||||
reg up_drp_locked_m1 = 1'd0;
|
||||
reg up_drp_locked_int = 1'd0;
|
||||
reg rx_r1_mode = 'd0;
|
||||
reg [ 3:0] rx_frame_d = 'd0;
|
||||
reg [ 5:0] rx_data_3 = 'd0;
|
||||
reg [ 5:0] rx_data_2 = 'd0;
|
||||
reg [ 5:0] rx_data_1 = 'd0;
|
||||
reg adc_valid_p = 'd0;
|
||||
reg [47:0] adc_data_p = 'd0;
|
||||
reg adc_status_p = 'd0;
|
||||
reg adc_valid_int = 'd0;
|
||||
reg [47:0] adc_data_int = 'd0;
|
||||
reg adc_status_int = 'd0;
|
||||
reg tx_valid = 'd0;
|
||||
reg [47:0] tx_data = 'd0;
|
||||
reg [ 3:0] tx_frame_p = 'd0;
|
||||
reg [ 5:0] tx_data_0_p = 'd0;
|
||||
reg [ 5:0] tx_data_1_p = 'd0;
|
||||
reg [ 5:0] tx_data_2_p = 'd0;
|
||||
reg [ 5:0] tx_data_3_p = 'd0;
|
||||
reg [ 3:0] tx_frame = 'd0;
|
||||
reg [ 5:0] tx_data_0 = 'd0;
|
||||
reg [ 5:0] tx_data_1 = 'd0;
|
||||
reg [ 5:0] tx_data_2 = 'd0;
|
||||
reg [ 5:0] tx_data_3 = 'd0;
|
||||
reg up_enable_int = 'd0;
|
||||
reg up_txnrx_int = 'd0;
|
||||
reg enable_up_m1 = 'd0;
|
||||
reg txnrx_up_m1 = 'd0;
|
||||
reg enable_up = 'd0;
|
||||
reg txnrx_up = 'd0;
|
||||
reg enable_int = 'd0;
|
||||
reg txnrx_int = 'd0;
|
||||
reg enable_int_p = 'd0;
|
||||
reg txnrx_int_p = 'd0;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire locked_s;
|
||||
wire [ 3:0] rx_frame_s;
|
||||
wire [ 5:0] rx_data_3_s;
|
||||
wire [ 5:0] rx_data_2_s;
|
||||
wire [ 5:0] rx_data_1_s;
|
||||
wire [ 5:0] rx_data_0_s;
|
||||
|
||||
// local parameters
|
||||
|
||||
localparam CYCLONE5 = 101;
|
||||
localparam ARRIA10 = 103;
|
||||
|
||||
// unused interface signals
|
||||
|
||||
assign up_adc_drdata = 35'b0;
|
||||
assign up_dac_drdata = 50'b0;
|
||||
assign delay_locked = 1'b1;
|
||||
|
||||
// drp locked must be on up-clock
|
||||
|
||||
assign up_drp_locked = up_drp_locked_int;
|
||||
|
||||
always @(negedge up_rstn or posedge up_clk) begin
|
||||
if (up_rstn == 1'b0) begin
|
||||
up_drp_locked_m1 <= 1'd0;
|
||||
up_drp_locked_int <= 1'd0;
|
||||
end else begin
|
||||
up_drp_locked_m1 <= locked_s;
|
||||
up_drp_locked_int <= up_drp_locked_m1;
|
||||
end
|
||||
end
|
||||
|
||||
// r1mode
|
||||
|
||||
generate if (CLK_DESKEW) begin
|
||||
|
||||
reg adc_r1_mode_n = 'd0;
|
||||
|
||||
always @(negedge clk) begin
|
||||
adc_r1_mode_n <= adc_r1_mode;
|
||||
end
|
||||
|
||||
always @(posedge l_clk) begin
|
||||
rx_r1_mode <= adc_r1_mode_n;
|
||||
end
|
||||
|
||||
end else begin /* CLK_DESKEW == 0 */
|
||||
|
||||
always @(posedge l_clk) begin
|
||||
rx_r1_mode <= adc_r1_mode;
|
||||
end
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// frame check
|
||||
|
||||
always @(posedge l_clk) begin
|
||||
if (rx_r1_mode == 1'd1) begin
|
||||
rx_frame_d <= rx_frame_s;
|
||||
end else begin
|
||||
rx_frame_d <= ~rx_frame_s;
|
||||
end
|
||||
end
|
||||
|
||||
// data hold
|
||||
|
||||
always @(posedge l_clk) begin
|
||||
rx_data_3 <= rx_data_3_s;
|
||||
rx_data_2 <= rx_data_2_s;
|
||||
rx_data_1 <= rx_data_1_s;
|
||||
end
|
||||
|
||||
// delineation
|
||||
|
||||
always @(posedge l_clk) begin
|
||||
case ({rx_r1_mode, rx_frame_s})
|
||||
5'b01111: begin
|
||||
adc_valid_p <= 1'b0;
|
||||
adc_data_p[47:24] <= 24'd0;
|
||||
adc_data_p[23:12] <= {rx_data_1_s, rx_data_3_s};
|
||||
adc_data_p[11: 0] <= {rx_data_0_s, rx_data_2_s};
|
||||
end
|
||||
5'b00000: begin
|
||||
adc_valid_p <= 1'b1;
|
||||
adc_data_p[47:36] <= {rx_data_1_s, rx_data_3_s};
|
||||
adc_data_p[35:24] <= {rx_data_0_s, rx_data_2_s};
|
||||
adc_data_p[23: 0] <= adc_data_p[23:0];
|
||||
end
|
||||
5'b00111: begin
|
||||
adc_valid_p <= 1'b0;
|
||||
adc_data_p[47:24] <= 24'd0;
|
||||
adc_data_p[23:12] <= {rx_data_0_s, rx_data_2_s};
|
||||
adc_data_p[11: 0] <= {rx_data_3, rx_data_1_s};
|
||||
end
|
||||
5'b01000: begin
|
||||
adc_valid_p <= 1'b1;
|
||||
adc_data_p[47:36] <= {rx_data_0_s, rx_data_2_s};
|
||||
adc_data_p[35:24] <= {rx_data_3, rx_data_1_s};
|
||||
adc_data_p[23: 0] <= adc_data_p[23:0];
|
||||
end
|
||||
5'b00011: begin
|
||||
adc_valid_p <= 1'b0;
|
||||
adc_data_p[47:24] <= 24'd0;
|
||||
adc_data_p[23:12] <= {rx_data_3, rx_data_1_s};
|
||||
adc_data_p[11: 0] <= {rx_data_2, rx_data_0_s};
|
||||
end
|
||||
5'b01100: begin
|
||||
adc_valid_p <= 1'b1;
|
||||
adc_data_p[47:36] <= {rx_data_3, rx_data_1_s};
|
||||
adc_data_p[35:24] <= {rx_data_2, rx_data_0_s};
|
||||
adc_data_p[23: 0] <= adc_data_p[23:0];
|
||||
end
|
||||
5'b00001: begin
|
||||
adc_valid_p <= 1'b0;
|
||||
adc_data_p[47:24] <= 24'd0;
|
||||
adc_data_p[23:12] <= {rx_data_2, rx_data_0_s};
|
||||
adc_data_p[11: 0] <= {rx_data_1, rx_data_3};
|
||||
end
|
||||
5'b01110: begin
|
||||
adc_valid_p <= 1'b1;
|
||||
adc_data_p[47:36] <= {rx_data_2, rx_data_0_s};
|
||||
adc_data_p[35:24] <= {rx_data_1, rx_data_3};
|
||||
adc_data_p[23: 0] <= adc_data_p[23:0];
|
||||
end
|
||||
5'b10011: begin
|
||||
adc_valid_p <= 1'b1;
|
||||
adc_data_p[47:24] <= 24'd0;
|
||||
adc_data_p[23:12] <= {rx_data_1_s, rx_data_3_s};
|
||||
adc_data_p[11: 0] <= {rx_data_0_s, rx_data_2_s};
|
||||
end
|
||||
5'b11001: begin
|
||||
adc_valid_p <= 1'b1;
|
||||
adc_data_p[47:24] <= 24'd0;
|
||||
adc_data_p[23:12] <= {rx_data_0_s, rx_data_2_s};
|
||||
adc_data_p[11: 0] <= {rx_data_3, rx_data_1_s};
|
||||
end
|
||||
5'b11100: begin
|
||||
adc_valid_p <= 1'b1;
|
||||
adc_data_p[47:24] <= 24'd0;
|
||||
adc_data_p[23:12] <= {rx_data_3, rx_data_1_s};
|
||||
adc_data_p[11: 0] <= {rx_data_2, rx_data_0_s};
|
||||
end
|
||||
5'b10110: begin
|
||||
adc_valid_p <= 1'b1;
|
||||
adc_data_p[47:24] <= 24'd0;
|
||||
adc_data_p[23:12] <= {rx_data_2, rx_data_0_s};
|
||||
adc_data_p[11: 0] <= {rx_data_1, rx_data_3};
|
||||
end
|
||||
default: begin
|
||||
adc_valid_p <= 1'b0;
|
||||
adc_data_p <= 48'd0;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
// adc-status
|
||||
|
||||
always @(posedge l_clk) begin
|
||||
if (rx_frame_d == rx_frame_s) begin
|
||||
adc_status_p <= locked_s;
|
||||
end else begin
|
||||
adc_status_p <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
// transfer to common clock
|
||||
|
||||
generate if (CLK_DESKEW) begin
|
||||
|
||||
reg adc_valid_n = 'd0;
|
||||
reg [47:0] adc_data_n = 'd0;
|
||||
reg adc_status_n = 'd0;
|
||||
|
||||
always @(negedge l_clk) begin
|
||||
adc_valid_n <= adc_valid_p;
|
||||
adc_data_n <= adc_data_p;
|
||||
adc_status_n <= adc_status_p;
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
adc_valid_int <= adc_valid_n;
|
||||
adc_data_int <= adc_data_n;
|
||||
adc_status_int <= adc_status_n;
|
||||
end
|
||||
|
||||
end else begin /* CLK_DESKEW == 0 */
|
||||
|
||||
always @(posedge l_clk) begin
|
||||
adc_valid_int <= adc_valid_p;
|
||||
adc_data_int <= adc_data_p;
|
||||
adc_status_int <= adc_status_p;
|
||||
end
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
assign adc_valid = adc_valid_int;
|
||||
assign adc_data = adc_data_int;
|
||||
assign adc_status = adc_status_int;
|
||||
|
||||
// dac-tx interface
|
||||
|
||||
always @(posedge clk) begin
|
||||
tx_valid <= dac_valid;
|
||||
if (dac_valid == 1'b1) begin
|
||||
tx_data <= dac_data;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (dac_r1_mode == 1'b1) begin
|
||||
tx_frame_p <= 4'b0011;
|
||||
tx_data_0_p <= tx_data[11: 6];
|
||||
tx_data_1_p <= tx_data[23:18];
|
||||
tx_data_2_p <= tx_data[ 5: 0];
|
||||
tx_data_3_p <= tx_data[17:12];
|
||||
end else if (tx_valid == 1'b1) begin
|
||||
tx_frame_p <= 4'b1111;
|
||||
tx_data_0_p <= tx_data[11: 6];
|
||||
tx_data_1_p <= tx_data[23:18];
|
||||
tx_data_2_p <= tx_data[ 5: 0];
|
||||
tx_data_3_p <= tx_data[17:12];
|
||||
end else begin
|
||||
tx_frame_p <= 4'b0000;
|
||||
tx_data_0_p <= tx_data[35:30];
|
||||
tx_data_1_p <= tx_data[47:42];
|
||||
tx_data_2_p <= tx_data[29:24];
|
||||
tx_data_3_p <= tx_data[41:36];
|
||||
end
|
||||
end
|
||||
|
||||
// transfer to local clock
|
||||
|
||||
generate if (CLK_DESKEW) begin
|
||||
|
||||
reg tx_frame_n = 'd0;
|
||||
reg [ 5:0] tx_data_0_n = 'd0;
|
||||
reg [ 5:0] tx_data_1_n = 'd0;
|
||||
reg [ 5:0] tx_data_2_n = 'd0;
|
||||
reg [ 5:0] tx_data_3_n = 'd0;
|
||||
|
||||
always @(negedge clk) begin
|
||||
tx_frame_n <= tx_frame_p;
|
||||
tx_data_0_n <= tx_data_0_p;
|
||||
tx_data_1_n <= tx_data_1_p;
|
||||
tx_data_2_n <= tx_data_2_p;
|
||||
tx_data_3_n <= tx_data_3_p;
|
||||
end
|
||||
|
||||
always @(posedge l_clk) begin
|
||||
tx_frame <= tx_frame_n;
|
||||
tx_data_0 <= tx_data_0_n;
|
||||
tx_data_1 <= tx_data_1_n;
|
||||
tx_data_2 <= tx_data_2_n;
|
||||
tx_data_3 <= tx_data_3_n;
|
||||
end
|
||||
|
||||
end else begin /* CLK_DESKEW == 0 */
|
||||
|
||||
always @(posedge l_clk) begin
|
||||
tx_frame <= tx_frame_p;
|
||||
tx_data_0 <= tx_data_0_p;
|
||||
tx_data_1 <= tx_data_1_p;
|
||||
tx_data_2 <= tx_data_2_p;
|
||||
tx_data_3 <= tx_data_3_p;
|
||||
end
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// tdd/ensm control
|
||||
|
||||
always @(posedge up_clk) begin
|
||||
up_enable_int <= up_enable;
|
||||
up_txnrx_int <= up_txnrx;
|
||||
end
|
||||
|
||||
always @(posedge clk or posedge rst) begin
|
||||
if (rst == 1'b1) begin
|
||||
enable_up_m1 <= 1'b0;
|
||||
txnrx_up_m1 <= 1'b0;
|
||||
enable_up <= 1'b0;
|
||||
txnrx_up <= 1'b0;
|
||||
end else begin
|
||||
enable_up_m1 <= up_enable_int;
|
||||
txnrx_up_m1 <= up_txnrx_int;
|
||||
enable_up <= enable_up_m1;
|
||||
txnrx_up <= txnrx_up_m1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (tdd_mode == 1'b1) begin
|
||||
enable_int <= tdd_enable;
|
||||
txnrx_int <= tdd_txnrx;
|
||||
end else begin
|
||||
enable_int <= enable_up;
|
||||
txnrx_int <= txnrx_up;
|
||||
end
|
||||
end
|
||||
|
||||
generate if (CLK_DESKEW) begin
|
||||
|
||||
reg enable_int_n = 'd0;
|
||||
reg txnrx_int_n = 'd0;
|
||||
|
||||
always @(negedge clk) begin
|
||||
enable_int_n <= enable_int;
|
||||
txnrx_int_n <= txnrx_int;
|
||||
end
|
||||
|
||||
always @(posedge l_clk) begin
|
||||
enable_int_p <= enable_int_n;
|
||||
txnrx_int_p <= txnrx_int_n;
|
||||
end
|
||||
|
||||
end else begin /* CLK_DESKEW == 0 */
|
||||
|
||||
always @(posedge l_clk) begin
|
||||
enable_int_p <= enable_int;
|
||||
txnrx_int_p <= txnrx_int;
|
||||
end
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate
|
||||
if (FPGA_TECHNOLOGY == CYCLONE5) begin
|
||||
axi_ad9361_lvds_if_c5 i_axi_ad9361_lvds_if_c5 (
|
||||
.rx_clk_in_p (rx_clk_in_p),
|
||||
.rx_clk_in_n (rx_clk_in_n),
|
||||
.rx_frame_in_p (rx_frame_in_p),
|
||||
.rx_frame_in_n (rx_frame_in_n),
|
||||
.rx_data_in_p (rx_data_in_p),
|
||||
.rx_data_in_n (rx_data_in_n),
|
||||
.tx_clk_out_p (tx_clk_out_p),
|
||||
.tx_clk_out_n (tx_clk_out_n),
|
||||
.tx_frame_out_p (tx_frame_out_p),
|
||||
.tx_frame_out_n (tx_frame_out_n),
|
||||
.tx_data_out_p (tx_data_out_p),
|
||||
.tx_data_out_n (tx_data_out_n),
|
||||
.enable (enable),
|
||||
.txnrx (txnrx),
|
||||
.clk (l_clk),
|
||||
.rx_frame (rx_frame_s),
|
||||
.rx_data_0 (rx_data_0_s),
|
||||
.rx_data_1 (rx_data_1_s),
|
||||
.rx_data_2 (rx_data_2_s),
|
||||
.rx_data_3 (rx_data_3_s),
|
||||
.tx_frame (tx_frame),
|
||||
.tx_data_0 (tx_data_0),
|
||||
.tx_data_1 (tx_data_1),
|
||||
.tx_data_2 (tx_data_2),
|
||||
.tx_data_3 (tx_data_3),
|
||||
.tx_enable (enable_int_p),
|
||||
.tx_txnrx (txnrx_int_p),
|
||||
.locked (locked_s),
|
||||
.up_clk (up_clk),
|
||||
.up_rstn (up_rstn));
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate
|
||||
if (FPGA_TECHNOLOGY == ARRIA10) begin
|
||||
axi_ad9361_lvds_if_10 #(
|
||||
.RX_NODPA (RX_NODPA))
|
||||
i_axi_ad9361_lvds_if_10 (
|
||||
.rx_clk_in_p (rx_clk_in_p),
|
||||
.rx_clk_in_n (rx_clk_in_n),
|
||||
.rx_frame_in_p (rx_frame_in_p),
|
||||
.rx_frame_in_n (rx_frame_in_n),
|
||||
.rx_data_in_p (rx_data_in_p),
|
||||
.rx_data_in_n (rx_data_in_n),
|
||||
.tx_clk_out_p (tx_clk_out_p),
|
||||
.tx_clk_out_n (tx_clk_out_n),
|
||||
.tx_frame_out_p (tx_frame_out_p),
|
||||
.tx_frame_out_n (tx_frame_out_n),
|
||||
.tx_data_out_p (tx_data_out_p),
|
||||
.tx_data_out_n (tx_data_out_n),
|
||||
.enable (enable),
|
||||
.txnrx (txnrx),
|
||||
.clk (l_clk),
|
||||
.rx_frame (rx_frame_s),
|
||||
.rx_data_0 (rx_data_0_s),
|
||||
.rx_data_1 (rx_data_1_s),
|
||||
.rx_data_2 (rx_data_2_s),
|
||||
.rx_data_3 (rx_data_3_s),
|
||||
.tx_frame (tx_frame),
|
||||
.tx_data_0 (tx_data_0),
|
||||
.tx_data_1 (tx_data_1),
|
||||
.tx_data_2 (tx_data_2),
|
||||
.tx_data_3 (tx_data_3),
|
||||
.tx_enable (enable_int_p),
|
||||
.tx_txnrx (txnrx_int_p),
|
||||
.locked (locked_s),
|
||||
.up_clk (up_clk),
|
||||
.up_rstn (up_rstn));
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
@@ -0,0 +1,307 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module axi_ad9361_lvds_if_10 #(
|
||||
|
||||
parameter RX_NODPA = 0) (
|
||||
|
||||
// physical interface (receive)
|
||||
|
||||
input rx_clk_in_p,
|
||||
input rx_clk_in_n,
|
||||
input rx_frame_in_p,
|
||||
input rx_frame_in_n,
|
||||
input [ 5:0] rx_data_in_p,
|
||||
input [ 5:0] rx_data_in_n,
|
||||
|
||||
// physical interface (transmit)
|
||||
|
||||
output tx_clk_out_p,
|
||||
output tx_clk_out_n,
|
||||
output tx_frame_out_p,
|
||||
output tx_frame_out_n,
|
||||
output [ 5:0] tx_data_out_p,
|
||||
output [ 5:0] tx_data_out_n,
|
||||
|
||||
// ensm control
|
||||
|
||||
output enable,
|
||||
output txnrx,
|
||||
|
||||
// clock (common to both receive and transmit)
|
||||
|
||||
output clk,
|
||||
|
||||
// receive data path interface
|
||||
|
||||
output [ 3:0] rx_frame,
|
||||
output [ 5:0] rx_data_0,
|
||||
output [ 5:0] rx_data_1,
|
||||
output [ 5:0] rx_data_2,
|
||||
output [ 5:0] rx_data_3,
|
||||
|
||||
// transmit data path interface
|
||||
|
||||
input [ 3:0] tx_frame,
|
||||
input [ 5:0] tx_data_0,
|
||||
input [ 5:0] tx_data_1,
|
||||
input [ 5:0] tx_data_2,
|
||||
input [ 5:0] tx_data_3,
|
||||
input tx_enable,
|
||||
input tx_txnrx,
|
||||
|
||||
// locked (status)
|
||||
|
||||
output locked,
|
||||
|
||||
// delay interface
|
||||
|
||||
input up_clk,
|
||||
input up_rstn);
|
||||
|
||||
// internal registers
|
||||
|
||||
reg pll_rst = 1'd1;
|
||||
reg locked_int = 'd0;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire [27:0] rx_data_s;
|
||||
wire [ 6:0] rx_data_locked_s;
|
||||
wire [ 6:0] rx_delay_locked_s;
|
||||
wire [27:0] tx_data_s;
|
||||
wire locked_s;
|
||||
wire lvds_clk;
|
||||
wire lvds_loaden;
|
||||
wire [ 7:0] lvds_phase;
|
||||
wire rx_clk;
|
||||
|
||||
// pll reset
|
||||
|
||||
always @(negedge up_rstn or posedge up_clk) begin
|
||||
if (up_rstn == 0) begin
|
||||
pll_rst <= 1'b1;
|
||||
end else begin
|
||||
pll_rst <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
assign locked = locked_int;
|
||||
|
||||
always @(posedge clk) begin
|
||||
locked_int <= locked_s & (& rx_data_locked_s) &
|
||||
(& rx_delay_locked_s);
|
||||
end
|
||||
|
||||
// receive
|
||||
|
||||
assign rx_frame[3] = rx_data_s[24];
|
||||
assign rx_frame[2] = rx_data_s[25];
|
||||
assign rx_frame[1] = rx_data_s[26];
|
||||
assign rx_frame[0] = rx_data_s[27];
|
||||
|
||||
assign rx_data_3[5] = rx_data_s[20];
|
||||
assign rx_data_3[4] = rx_data_s[16];
|
||||
assign rx_data_3[3] = rx_data_s[12];
|
||||
assign rx_data_3[2] = rx_data_s[ 8];
|
||||
assign rx_data_3[1] = rx_data_s[ 4];
|
||||
assign rx_data_3[0] = rx_data_s[ 0];
|
||||
assign rx_data_2[5] = rx_data_s[21];
|
||||
assign rx_data_2[4] = rx_data_s[17];
|
||||
assign rx_data_2[3] = rx_data_s[13];
|
||||
assign rx_data_2[2] = rx_data_s[ 9];
|
||||
assign rx_data_2[1] = rx_data_s[ 5];
|
||||
assign rx_data_2[0] = rx_data_s[ 1];
|
||||
assign rx_data_1[5] = rx_data_s[22];
|
||||
assign rx_data_1[4] = rx_data_s[18];
|
||||
assign rx_data_1[3] = rx_data_s[14];
|
||||
assign rx_data_1[2] = rx_data_s[10];
|
||||
assign rx_data_1[1] = rx_data_s[ 6];
|
||||
assign rx_data_1[0] = rx_data_s[ 2];
|
||||
assign rx_data_0[5] = rx_data_s[23];
|
||||
assign rx_data_0[4] = rx_data_s[19];
|
||||
assign rx_data_0[3] = rx_data_s[15];
|
||||
assign rx_data_0[2] = rx_data_s[11];
|
||||
assign rx_data_0[1] = rx_data_s[ 7];
|
||||
assign rx_data_0[0] = rx_data_s[ 3];
|
||||
|
||||
// transmit
|
||||
|
||||
assign tx_clk_out_n = 1'd0;
|
||||
assign tx_frame_out_n = 1'd0;
|
||||
assign tx_data_out_n = 6'd0;
|
||||
|
||||
assign tx_data_s[24] = tx_frame[3];
|
||||
assign tx_data_s[25] = tx_frame[2];
|
||||
assign tx_data_s[26] = tx_frame[1];
|
||||
assign tx_data_s[27] = tx_frame[0];
|
||||
|
||||
assign tx_data_s[20] = tx_data_3[5];
|
||||
assign tx_data_s[16] = tx_data_3[4];
|
||||
assign tx_data_s[12] = tx_data_3[3];
|
||||
assign tx_data_s[ 8] = tx_data_3[2];
|
||||
assign tx_data_s[ 4] = tx_data_3[1];
|
||||
assign tx_data_s[ 0] = tx_data_3[0];
|
||||
assign tx_data_s[21] = tx_data_2[5];
|
||||
assign tx_data_s[17] = tx_data_2[4];
|
||||
assign tx_data_s[13] = tx_data_2[3];
|
||||
assign tx_data_s[ 9] = tx_data_2[2];
|
||||
assign tx_data_s[ 5] = tx_data_2[1];
|
||||
assign tx_data_s[ 1] = tx_data_2[0];
|
||||
assign tx_data_s[22] = tx_data_1[5];
|
||||
assign tx_data_s[18] = tx_data_1[4];
|
||||
assign tx_data_s[14] = tx_data_1[3];
|
||||
assign tx_data_s[10] = tx_data_1[2];
|
||||
assign tx_data_s[ 6] = tx_data_1[1];
|
||||
assign tx_data_s[ 2] = tx_data_1[0];
|
||||
assign tx_data_s[23] = tx_data_0[5];
|
||||
assign tx_data_s[19] = tx_data_0[4];
|
||||
assign tx_data_s[15] = tx_data_0[3];
|
||||
assign tx_data_s[11] = tx_data_0[2];
|
||||
assign tx_data_s[ 7] = tx_data_0[1];
|
||||
assign tx_data_s[ 3] = tx_data_0[0];
|
||||
|
||||
// instantiations
|
||||
|
||||
genvar i;
|
||||
generate
|
||||
for (i = 0; i < 6; i = i + 1) begin: g_rx_data
|
||||
if (RX_NODPA == 0) begin
|
||||
axi_ad9361_serdes_in i_rx_data (
|
||||
.data_in_export (rx_data_in_p[i]),
|
||||
.clk_export (lvds_clk),
|
||||
.loaden_export (lvds_loaden),
|
||||
.div_clk_export (clk),
|
||||
.hs_phase_export (lvds_phase),
|
||||
.locked_export (rx_data_locked_s[i]),
|
||||
.data_s_export (rx_data_s[((i*4)+3):(i*4)]),
|
||||
.delay_locked_export (rx_delay_locked_s[i]));
|
||||
end else begin
|
||||
axi_ad9361_serdes_in i_rx_data (
|
||||
.data_in_export (rx_data_in_p[i]),
|
||||
.clk_export (lvds_clk),
|
||||
.loaden_export (lvds_loaden),
|
||||
.div_clk_export (clk),
|
||||
.data_s_export (rx_data_s[((i*4)+3):(i*4)]));
|
||||
|
||||
assign rx_data_locked_s[i] = 1'b1;
|
||||
assign rx_delay_locked_s[i] = 1'b1;
|
||||
|
||||
end
|
||||
end
|
||||
|
||||
if (RX_NODPA == 0) begin
|
||||
|
||||
axi_ad9361_serdes_in i_rx_frame (
|
||||
.data_in_export (rx_frame_in_p),
|
||||
.clk_export (lvds_clk),
|
||||
.loaden_export (lvds_loaden),
|
||||
.div_clk_export (clk),
|
||||
.hs_phase_export (lvds_phase),
|
||||
.locked_export (rx_data_locked_s[6]),
|
||||
.data_s_export (rx_data_s[27:24]),
|
||||
.delay_locked_export (rx_delay_locked_s[6]));
|
||||
|
||||
assign rx_clk = rx_clk_in_p;
|
||||
|
||||
end else begin
|
||||
|
||||
axi_ad9361_serdes_in i_rx_frame (
|
||||
.data_in_export (rx_frame_in_p),
|
||||
.clk_export (lvds_clk),
|
||||
.loaden_export (lvds_loaden),
|
||||
.div_clk_export (clk),
|
||||
.data_s_export (rx_data_s[27:24]) );
|
||||
|
||||
assign rx_data_locked_s[6] = 1'b1;
|
||||
assign rx_delay_locked_s[6] = 1'b1;
|
||||
|
||||
clk_buffer clk_buf (
|
||||
.inclk (rx_clk_in_p),
|
||||
.outclk (rx_clk));
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate
|
||||
for (i = 0; i < 6; i = i + 1) begin: g_tx_data
|
||||
axi_ad9361_serdes_out i_tx_data (
|
||||
.data_out_export (tx_data_out_p[i]),
|
||||
.clk_export (lvds_clk),
|
||||
.loaden_export (lvds_loaden),
|
||||
.div_clk_export (clk),
|
||||
.data_s_export (tx_data_s[((i*4)+3):(i*4)]));
|
||||
end
|
||||
endgenerate
|
||||
|
||||
axi_ad9361_serdes_out i_tx_frame (
|
||||
.data_out_export (tx_frame_out_p),
|
||||
.clk_export (lvds_clk),
|
||||
.loaden_export (lvds_loaden),
|
||||
.div_clk_export (clk),
|
||||
.data_s_export (tx_data_s[27:24]));
|
||||
|
||||
axi_ad9361_serdes_out i_tx_clk (
|
||||
.data_out_export (tx_clk_out_p),
|
||||
.clk_export (lvds_clk),
|
||||
.loaden_export (lvds_loaden),
|
||||
.div_clk_export (clk),
|
||||
.data_s_export (4'b1010));
|
||||
|
||||
axi_ad9361_data_out i_enable (
|
||||
.ck (clk),
|
||||
.din ({tx_enable, tx_enable}),
|
||||
.pad_out (enable));
|
||||
|
||||
axi_ad9361_data_out i_txnrx (
|
||||
.ck (clk),
|
||||
.din ({tx_txnrx, tx_txnrx}),
|
||||
.pad_out (txnrx));
|
||||
|
||||
axi_ad9361_serdes_clk i_clk (
|
||||
.rst_reset (pll_rst),
|
||||
.ref_clk_clk (rx_clk),
|
||||
.locked_export (locked_s),
|
||||
.hs_phase_phout (lvds_phase),
|
||||
.hs_clk_lvds_clk (lvds_clk),
|
||||
.loaden_loaden (lvds_loaden),
|
||||
.ls_clk_clk (clk));
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
@@ -0,0 +1,397 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module axi_ad9361_lvds_if_c5 (
|
||||
|
||||
// physical interface (receive)
|
||||
|
||||
input rx_clk_in_p,
|
||||
input rx_clk_in_n,
|
||||
input rx_frame_in_p,
|
||||
input rx_frame_in_n,
|
||||
input [ 5:0] rx_data_in_p,
|
||||
input [ 5:0] rx_data_in_n,
|
||||
|
||||
// physical interface (transmit)
|
||||
|
||||
output tx_clk_out_p,
|
||||
output tx_clk_out_n,
|
||||
output tx_frame_out_p,
|
||||
output tx_frame_out_n,
|
||||
output [ 5:0] tx_data_out_p,
|
||||
output [ 5:0] tx_data_out_n,
|
||||
|
||||
// ensm control
|
||||
|
||||
output enable,
|
||||
output txnrx,
|
||||
|
||||
// clock (common to both receive and transmit)
|
||||
|
||||
output clk,
|
||||
|
||||
// receive data path interface
|
||||
|
||||
output [ 3:0] rx_frame,
|
||||
output [ 5:0] rx_data_0,
|
||||
output [ 5:0] rx_data_1,
|
||||
output [ 5:0] rx_data_2,
|
||||
output [ 5:0] rx_data_3,
|
||||
|
||||
// transmit data path interface
|
||||
|
||||
input [ 3:0] tx_frame,
|
||||
input [ 5:0] tx_data_0,
|
||||
input [ 5:0] tx_data_1,
|
||||
input [ 5:0] tx_data_2,
|
||||
input [ 5:0] tx_data_3,
|
||||
input tx_enable,
|
||||
input tx_txnrx,
|
||||
|
||||
// locked (status)
|
||||
|
||||
output locked,
|
||||
|
||||
// delay interface
|
||||
|
||||
input up_clk,
|
||||
input up_rstn);
|
||||
|
||||
// internal registers
|
||||
|
||||
reg pll_rst = 1'd1;
|
||||
reg locked_int = 'd0;
|
||||
reg tx_core_enable_int = 'd0;
|
||||
reg tx_core_txnrx_int = 'd0;
|
||||
reg [27:0] tx_core_data_int = 'd0;
|
||||
reg tx_core_enable = 'd0;
|
||||
reg tx_core_txnrx = 'd0;
|
||||
reg [27:0] tx_core_data = 'd0;
|
||||
reg tx_locked_int = 'd0;
|
||||
reg tx_locked = 'd0;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire [27:0] rx_core_data_s;
|
||||
wire rx_locked_s;
|
||||
wire tx_core_clk;
|
||||
wire tx_locked_s;
|
||||
|
||||
// pll reset
|
||||
|
||||
always @(negedge up_rstn or posedge up_clk) begin
|
||||
if (up_rstn == 0) begin
|
||||
pll_rst <= 1'b1;
|
||||
end else begin
|
||||
pll_rst <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
assign locked = locked_int;
|
||||
|
||||
always @(posedge clk) begin
|
||||
locked_int <= rx_locked_s & tx_locked;
|
||||
end
|
||||
|
||||
// receive
|
||||
|
||||
assign rx_frame[3] = rx_core_data_s[24];
|
||||
assign rx_frame[2] = rx_core_data_s[25];
|
||||
assign rx_frame[1] = rx_core_data_s[26];
|
||||
assign rx_frame[0] = rx_core_data_s[27];
|
||||
|
||||
assign rx_data_3[5] = rx_core_data_s[20];
|
||||
assign rx_data_3[4] = rx_core_data_s[16];
|
||||
assign rx_data_3[3] = rx_core_data_s[12];
|
||||
assign rx_data_3[2] = rx_core_data_s[ 8];
|
||||
assign rx_data_3[1] = rx_core_data_s[ 4];
|
||||
assign rx_data_3[0] = rx_core_data_s[ 0];
|
||||
assign rx_data_2[5] = rx_core_data_s[21];
|
||||
assign rx_data_2[4] = rx_core_data_s[17];
|
||||
assign rx_data_2[3] = rx_core_data_s[13];
|
||||
assign rx_data_2[2] = rx_core_data_s[ 9];
|
||||
assign rx_data_2[1] = rx_core_data_s[ 5];
|
||||
assign rx_data_2[0] = rx_core_data_s[ 1];
|
||||
assign rx_data_1[5] = rx_core_data_s[22];
|
||||
assign rx_data_1[4] = rx_core_data_s[18];
|
||||
assign rx_data_1[3] = rx_core_data_s[14];
|
||||
assign rx_data_1[2] = rx_core_data_s[10];
|
||||
assign rx_data_1[1] = rx_core_data_s[ 6];
|
||||
assign rx_data_1[0] = rx_core_data_s[ 2];
|
||||
assign rx_data_0[5] = rx_core_data_s[23];
|
||||
assign rx_data_0[4] = rx_core_data_s[19];
|
||||
assign rx_data_0[3] = rx_core_data_s[15];
|
||||
assign rx_data_0[2] = rx_core_data_s[11];
|
||||
assign rx_data_0[1] = rx_core_data_s[ 7];
|
||||
assign rx_data_0[0] = rx_core_data_s[ 3];
|
||||
|
||||
// transmit (by definition, tx_core_clk and clk are the same (shared pll))
|
||||
// however, we safe guard transition - incase you keep them separate
|
||||
|
||||
assign tx_clk_out_n = 1'd0;
|
||||
assign tx_frame_out_n = 1'd0;
|
||||
assign tx_data_out_n = 6'd0;
|
||||
|
||||
always @(negedge clk) begin
|
||||
tx_core_enable_int <= tx_enable;
|
||||
tx_core_txnrx_int <= tx_txnrx;
|
||||
tx_core_data_int[24] <= tx_frame[3];
|
||||
tx_core_data_int[25] <= tx_frame[2];
|
||||
tx_core_data_int[26] <= tx_frame[1];
|
||||
tx_core_data_int[27] <= tx_frame[0];
|
||||
tx_core_data_int[20] <= tx_data_3[5];
|
||||
tx_core_data_int[16] <= tx_data_3[4];
|
||||
tx_core_data_int[12] <= tx_data_3[3];
|
||||
tx_core_data_int[ 8] <= tx_data_3[2];
|
||||
tx_core_data_int[ 4] <= tx_data_3[1];
|
||||
tx_core_data_int[ 0] <= tx_data_3[0];
|
||||
tx_core_data_int[21] <= tx_data_2[5];
|
||||
tx_core_data_int[17] <= tx_data_2[4];
|
||||
tx_core_data_int[13] <= tx_data_2[3];
|
||||
tx_core_data_int[ 9] <= tx_data_2[2];
|
||||
tx_core_data_int[ 5] <= tx_data_2[1];
|
||||
tx_core_data_int[ 1] <= tx_data_2[0];
|
||||
tx_core_data_int[22] <= tx_data_1[5];
|
||||
tx_core_data_int[18] <= tx_data_1[4];
|
||||
tx_core_data_int[14] <= tx_data_1[3];
|
||||
tx_core_data_int[10] <= tx_data_1[2];
|
||||
tx_core_data_int[ 6] <= tx_data_1[1];
|
||||
tx_core_data_int[ 2] <= tx_data_1[0];
|
||||
tx_core_data_int[23] <= tx_data_0[5];
|
||||
tx_core_data_int[19] <= tx_data_0[4];
|
||||
tx_core_data_int[15] <= tx_data_0[3];
|
||||
tx_core_data_int[11] <= tx_data_0[2];
|
||||
tx_core_data_int[ 7] <= tx_data_0[1];
|
||||
tx_core_data_int[ 3] <= tx_data_0[0];
|
||||
end
|
||||
|
||||
always @(posedge tx_core_clk) begin
|
||||
tx_core_enable <= tx_core_enable_int;
|
||||
tx_core_txnrx <= tx_core_txnrx_int;
|
||||
tx_core_data <= tx_core_data_int;
|
||||
end
|
||||
|
||||
always @(negedge tx_core_clk) begin
|
||||
tx_locked_int <= tx_locked_s;
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
tx_locked <= tx_locked_int;
|
||||
end
|
||||
|
||||
// instantiations
|
||||
|
||||
altlvds_rx #(
|
||||
.buffer_implementation ("RAM"),
|
||||
.cds_mode ("UNUSED"),
|
||||
.common_rx_tx_pll ("ON"),
|
||||
.data_align_rollover (4),
|
||||
.data_rate ("500.0 Mbps"),
|
||||
.deserialization_factor (4),
|
||||
.dpa_initial_phase_value (0),
|
||||
.dpll_lock_count (0),
|
||||
.dpll_lock_window (0),
|
||||
.enable_clock_pin_mode ("UNUSED"),
|
||||
.enable_dpa_align_to_rising_edge_only ("OFF"),
|
||||
.enable_dpa_calibration ("ON"),
|
||||
.enable_dpa_fifo ("UNUSED"),
|
||||
.enable_dpa_initial_phase_selection ("OFF"),
|
||||
.enable_dpa_mode ("OFF"),
|
||||
.enable_dpa_pll_calibration ("OFF"),
|
||||
.enable_soft_cdr_mode ("OFF"),
|
||||
.implement_in_les ("OFF"),
|
||||
.inclock_boost (0),
|
||||
.inclock_data_alignment ("EDGE_ALIGNED"),
|
||||
.inclock_period (4000),
|
||||
.inclock_phase_shift (0),
|
||||
.input_data_rate (500),
|
||||
.intended_device_family ("Cyclone V"),
|
||||
.lose_lock_on_one_change ("UNUSED"),
|
||||
.lpm_hint ("CBX_MODULE_PREFIX=axi_ad9361_lvds_if_c5_rx"),
|
||||
.lpm_type ("altlvds_rx"),
|
||||
.number_of_channels (7),
|
||||
.outclock_resource ("Global clock"),
|
||||
.pll_operation_mode ("NORMAL"),
|
||||
.pll_self_reset_on_loss_lock ("UNUSED"),
|
||||
.port_rx_channel_data_align ("PORT_UNUSED"),
|
||||
.port_rx_data_align ("PORT_UNUSED"),
|
||||
.refclk_frequency ("250.000000 MHz"),
|
||||
.registered_data_align_input ("UNUSED"),
|
||||
.registered_output ("ON"),
|
||||
.reset_fifo_at_first_lock ("UNUSED"),
|
||||
.rx_align_data_reg ("RISING_EDGE"),
|
||||
.sim_dpa_is_negative_ppm_drift ("OFF"),
|
||||
.sim_dpa_net_ppm_variation (0),
|
||||
.sim_dpa_output_clock_phase_shift (0),
|
||||
.use_coreclock_input ("OFF"),
|
||||
.use_dpll_rawperror ("OFF"),
|
||||
.use_external_pll ("OFF"),
|
||||
.use_no_phase_shift ("ON"),
|
||||
.x_on_bitslip ("ON"),
|
||||
.clk_src_is_pll ("off"))
|
||||
i_altlvds_rx (
|
||||
.pll_areset (pll_rst),
|
||||
.rx_in ({rx_frame_in_p, rx_data_in_p}),
|
||||
.rx_inclock (rx_clk_in_p),
|
||||
.rx_locked (rx_locked_s),
|
||||
.rx_out (rx_core_data_s),
|
||||
.rx_outclock (clk),
|
||||
.dpa_pll_cal_busy (),
|
||||
.dpa_pll_recal (1'b0),
|
||||
.pll_phasecounterselect (),
|
||||
.pll_phasedone (1'b1),
|
||||
.pll_phasestep (),
|
||||
.pll_phaseupdown (),
|
||||
.pll_scanclk (),
|
||||
.rx_cda_max (),
|
||||
.rx_cda_reset ({7{1'b0}}),
|
||||
.rx_channel_data_align ({7{1'b0}}),
|
||||
.rx_coreclk ({7{1'b1}}),
|
||||
.rx_data_align (1'b0),
|
||||
.rx_data_align_reset (1'b0),
|
||||
.rx_data_reset (1'b0),
|
||||
.rx_deskew (1'b0),
|
||||
.rx_divfwdclk (),
|
||||
.rx_dpa_lock_reset ({7{1'b0}}),
|
||||
.rx_dpa_locked (),
|
||||
.rx_dpaclock (1'b0),
|
||||
.rx_dpll_enable ({7{1'b1}}),
|
||||
.rx_dpll_hold ({7{1'b0}}),
|
||||
.rx_dpll_reset ({7{1'b0}}),
|
||||
.rx_enable (1'b1),
|
||||
.rx_fifo_reset ({7{1'b0}}),
|
||||
.rx_pll_enable (1'b1),
|
||||
.rx_readclock (1'b0),
|
||||
.rx_reset ({7{1'b0}}),
|
||||
.rx_syncclock (1'b0));
|
||||
|
||||
altlvds_tx #(
|
||||
.center_align_msb ("UNUSED"),
|
||||
.common_rx_tx_pll ("ON"),
|
||||
.coreclock_divide_by (1),
|
||||
.data_rate ("500.0 Mbps"),
|
||||
.deserialization_factor (4),
|
||||
.differential_drive (0),
|
||||
.enable_clock_pin_mode ("UNUSED"),
|
||||
.implement_in_les ("OFF"),
|
||||
.inclock_boost (0),
|
||||
.inclock_data_alignment ("EDGE_ALIGNED"),
|
||||
.inclock_period (4000),
|
||||
.inclock_phase_shift (0),
|
||||
.intended_device_family ("Cyclone V"),
|
||||
.lpm_hint ("CBX_MODULE_PREFIX=axi_ad9361_lvds_if_c5_tx"),
|
||||
.lpm_type ("altlvds_tx"),
|
||||
.multi_clock ("OFF"),
|
||||
.number_of_channels (7),
|
||||
.outclock_alignment ("EDGE_ALIGNED"),
|
||||
.outclock_divide_by (2),
|
||||
.outclock_duty_cycle (50),
|
||||
.outclock_multiply_by (1),
|
||||
.outclock_phase_shift (0),
|
||||
.outclock_resource ("Global clock"),
|
||||
.output_data_rate (500),
|
||||
.pll_compensation_mode ("AUTO"),
|
||||
.pll_self_reset_on_loss_lock ("OFF"),
|
||||
.preemphasis_setting (0),
|
||||
.refclk_frequency ("250.000000 MHz"),
|
||||
.registered_input ("TX_CORECLK"),
|
||||
.use_external_pll ("OFF"),
|
||||
.use_no_phase_shift ("ON"),
|
||||
.vod_setting (0),
|
||||
.clk_src_is_pll ("off"))
|
||||
i_altlvds_tx (
|
||||
.pll_areset (pll_rst),
|
||||
.tx_in (tx_core_data),
|
||||
.tx_inclock (rx_clk_in_p),
|
||||
.tx_coreclock (tx_core_clk),
|
||||
.tx_locked (tx_locked_s),
|
||||
.tx_out ({tx_frame_out_p, tx_data_out_p}),
|
||||
.tx_outclock (tx_clk_out_p),
|
||||
.sync_inclock (1'b0),
|
||||
.tx_data_reset (1'b0),
|
||||
.tx_enable (1'b1),
|
||||
.tx_pll_enable (1'b1),
|
||||
.tx_syncclock (1'b0));
|
||||
|
||||
altddio_out #(
|
||||
.extend_oe_disable ("OFF"),
|
||||
.intended_device_family ("Cyclone V"),
|
||||
.invert_output ("OFF"),
|
||||
.lpm_hint ("UNUSED"),
|
||||
.lpm_type ("altddio_out"),
|
||||
.oe_reg ("UNREGISTERED"),
|
||||
.power_up_high ("OFF"),
|
||||
.width (1))
|
||||
i_altddio_enable (
|
||||
.datain_h (tx_core_enable),
|
||||
.datain_l (tx_core_enable),
|
||||
.outclock (tx_core_clk),
|
||||
.dataout (enable),
|
||||
.aclr (1'b0),
|
||||
.aset (1'b0),
|
||||
.oe (1'b1),
|
||||
.oe_out (),
|
||||
.outclocken (1'b1),
|
||||
.sclr (1'b0),
|
||||
.sset (1'b0));
|
||||
|
||||
altddio_out #(
|
||||
.extend_oe_disable ("OFF"),
|
||||
.intended_device_family ("Cyclone V"),
|
||||
.invert_output ("OFF"),
|
||||
.lpm_hint ("UNUSED"),
|
||||
.lpm_type ("altddio_out"),
|
||||
.oe_reg ("UNREGISTERED"),
|
||||
.power_up_high ("OFF"),
|
||||
.width (1))
|
||||
i_altddio_txnrx (
|
||||
.datain_h (tx_core_txnrx),
|
||||
.datain_l (tx_core_txnrx),
|
||||
.outclock (tx_core_clk),
|
||||
.dataout (txnrx),
|
||||
.aclr (1'b0),
|
||||
.aset (1'b0),
|
||||
.oe (1'b1),
|
||||
.oe_out (),
|
||||
.outclocken (1'b1),
|
||||
.sclr (1'b0),
|
||||
.sset (1'b0));
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
@@ -0,0 +1,2 @@
|
||||
CLEAN_TARGET += bd
|
||||
CLEAN_TARGET += temporary_case_dependencies.mk
|
||||
@@ -0,0 +1,462 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||
ipgui::add_param $IPINST -name "ADC_DATAFORMAT_DISABLE" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "ADC_DATAPATH_DISABLE" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "ADC_DCFILTER_DISABLE" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "ADC_INIT_DELAY" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "ADC_IQCORRECTION_DISABLE" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "ADC_USERPORTS_DISABLE" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "CMOS_OR_LVDS_N" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "DAC_CLK_EDGE_SEL" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "DAC_DATAPATH_DISABLE" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "DAC_DDS_CORDIC_DW" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "DAC_DDS_CORDIC_PHASE_DW" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "DAC_DDS_DISABLE" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "DAC_DDS_TYPE" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "DAC_INIT_DELAY" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "DAC_IODELAY_ENABLE" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "DAC_IQCORRECTION_DISABLE" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "DAC_USERPORTS_DISABLE" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "DELAY_REFCLK_FREQUENCY" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "ID" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "IO_DELAY_GROUP" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "MIMO_ENABLE" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "MODE_1R1T" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "PPS_RECEIVER_ENABLE" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "TDD_DISABLE" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "USE_SSI_CLK" -parent ${Page_0}
|
||||
#Adding Group
|
||||
set FPGA_info [ipgui::add_group $IPINST -name "FPGA info" -parent ${Page_0}]
|
||||
ipgui::add_param $IPINST -name "FPGA_TECHNOLOGY" -parent ${FPGA_info} -widget comboBox
|
||||
ipgui::add_param $IPINST -name "FPGA_FAMILY" -parent ${FPGA_info} -widget comboBox
|
||||
ipgui::add_param $IPINST -name "SPEED_GRADE" -parent ${FPGA_info} -widget comboBox
|
||||
ipgui::add_param $IPINST -name "DEV_PACKAGE" -parent ${FPGA_info} -widget comboBox
|
||||
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ADC_DATAFORMAT_DISABLE { PARAM_VALUE.ADC_DATAFORMAT_DISABLE } {
|
||||
# Procedure called to update ADC_DATAFORMAT_DISABLE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ADC_DATAFORMAT_DISABLE { PARAM_VALUE.ADC_DATAFORMAT_DISABLE } {
|
||||
# Procedure called to validate ADC_DATAFORMAT_DISABLE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ADC_DATAPATH_DISABLE { PARAM_VALUE.ADC_DATAPATH_DISABLE } {
|
||||
# Procedure called to update ADC_DATAPATH_DISABLE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ADC_DATAPATH_DISABLE { PARAM_VALUE.ADC_DATAPATH_DISABLE } {
|
||||
# Procedure called to validate ADC_DATAPATH_DISABLE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ADC_DCFILTER_DISABLE { PARAM_VALUE.ADC_DCFILTER_DISABLE } {
|
||||
# Procedure called to update ADC_DCFILTER_DISABLE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ADC_DCFILTER_DISABLE { PARAM_VALUE.ADC_DCFILTER_DISABLE } {
|
||||
# Procedure called to validate ADC_DCFILTER_DISABLE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ADC_INIT_DELAY { PARAM_VALUE.ADC_INIT_DELAY } {
|
||||
# Procedure called to update ADC_INIT_DELAY when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ADC_INIT_DELAY { PARAM_VALUE.ADC_INIT_DELAY } {
|
||||
# Procedure called to validate ADC_INIT_DELAY
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ADC_IQCORRECTION_DISABLE { PARAM_VALUE.ADC_IQCORRECTION_DISABLE } {
|
||||
# Procedure called to update ADC_IQCORRECTION_DISABLE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ADC_IQCORRECTION_DISABLE { PARAM_VALUE.ADC_IQCORRECTION_DISABLE } {
|
||||
# Procedure called to validate ADC_IQCORRECTION_DISABLE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ADC_USERPORTS_DISABLE { PARAM_VALUE.ADC_USERPORTS_DISABLE } {
|
||||
# Procedure called to update ADC_USERPORTS_DISABLE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ADC_USERPORTS_DISABLE { PARAM_VALUE.ADC_USERPORTS_DISABLE } {
|
||||
# Procedure called to validate ADC_USERPORTS_DISABLE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.CMOS_OR_LVDS_N { PARAM_VALUE.CMOS_OR_LVDS_N } {
|
||||
# Procedure called to update CMOS_OR_LVDS_N when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.CMOS_OR_LVDS_N { PARAM_VALUE.CMOS_OR_LVDS_N } {
|
||||
# Procedure called to validate CMOS_OR_LVDS_N
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DAC_CLK_EDGE_SEL { PARAM_VALUE.DAC_CLK_EDGE_SEL } {
|
||||
# Procedure called to update DAC_CLK_EDGE_SEL when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DAC_CLK_EDGE_SEL { PARAM_VALUE.DAC_CLK_EDGE_SEL } {
|
||||
# Procedure called to validate DAC_CLK_EDGE_SEL
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DAC_DATAPATH_DISABLE { PARAM_VALUE.DAC_DATAPATH_DISABLE } {
|
||||
# Procedure called to update DAC_DATAPATH_DISABLE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DAC_DATAPATH_DISABLE { PARAM_VALUE.DAC_DATAPATH_DISABLE } {
|
||||
# Procedure called to validate DAC_DATAPATH_DISABLE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DAC_DDS_CORDIC_DW { PARAM_VALUE.DAC_DDS_CORDIC_DW } {
|
||||
# Procedure called to update DAC_DDS_CORDIC_DW when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DAC_DDS_CORDIC_DW { PARAM_VALUE.DAC_DDS_CORDIC_DW } {
|
||||
# Procedure called to validate DAC_DDS_CORDIC_DW
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW { PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW } {
|
||||
# Procedure called to update DAC_DDS_CORDIC_PHASE_DW when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW { PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW } {
|
||||
# Procedure called to validate DAC_DDS_CORDIC_PHASE_DW
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DAC_DDS_DISABLE { PARAM_VALUE.DAC_DDS_DISABLE } {
|
||||
# Procedure called to update DAC_DDS_DISABLE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DAC_DDS_DISABLE { PARAM_VALUE.DAC_DDS_DISABLE } {
|
||||
# Procedure called to validate DAC_DDS_DISABLE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DAC_DDS_TYPE { PARAM_VALUE.DAC_DDS_TYPE } {
|
||||
# Procedure called to update DAC_DDS_TYPE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DAC_DDS_TYPE { PARAM_VALUE.DAC_DDS_TYPE } {
|
||||
# Procedure called to validate DAC_DDS_TYPE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DAC_INIT_DELAY { PARAM_VALUE.DAC_INIT_DELAY } {
|
||||
# Procedure called to update DAC_INIT_DELAY when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DAC_INIT_DELAY { PARAM_VALUE.DAC_INIT_DELAY } {
|
||||
# Procedure called to validate DAC_INIT_DELAY
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DAC_IODELAY_ENABLE { PARAM_VALUE.DAC_IODELAY_ENABLE } {
|
||||
# Procedure called to update DAC_IODELAY_ENABLE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DAC_IODELAY_ENABLE { PARAM_VALUE.DAC_IODELAY_ENABLE } {
|
||||
# Procedure called to validate DAC_IODELAY_ENABLE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DAC_IQCORRECTION_DISABLE { PARAM_VALUE.DAC_IQCORRECTION_DISABLE } {
|
||||
# Procedure called to update DAC_IQCORRECTION_DISABLE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DAC_IQCORRECTION_DISABLE { PARAM_VALUE.DAC_IQCORRECTION_DISABLE } {
|
||||
# Procedure called to validate DAC_IQCORRECTION_DISABLE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DAC_USERPORTS_DISABLE { PARAM_VALUE.DAC_USERPORTS_DISABLE } {
|
||||
# Procedure called to update DAC_USERPORTS_DISABLE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DAC_USERPORTS_DISABLE { PARAM_VALUE.DAC_USERPORTS_DISABLE } {
|
||||
# Procedure called to validate DAC_USERPORTS_DISABLE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DELAY_REFCLK_FREQUENCY { PARAM_VALUE.DELAY_REFCLK_FREQUENCY } {
|
||||
# Procedure called to update DELAY_REFCLK_FREQUENCY when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DELAY_REFCLK_FREQUENCY { PARAM_VALUE.DELAY_REFCLK_FREQUENCY } {
|
||||
# Procedure called to validate DELAY_REFCLK_FREQUENCY
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } {
|
||||
# Procedure called to update DEV_PACKAGE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } {
|
||||
# Procedure called to validate DEV_PACKAGE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } {
|
||||
# Procedure called to update FPGA_FAMILY when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } {
|
||||
# Procedure called to validate FPGA_FAMILY
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } {
|
||||
# Procedure called to update FPGA_TECHNOLOGY when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } {
|
||||
# Procedure called to validate FPGA_TECHNOLOGY
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } {
|
||||
# Procedure called to update ID when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } {
|
||||
# Procedure called to validate ID
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.IO_DELAY_GROUP { PARAM_VALUE.IO_DELAY_GROUP } {
|
||||
# Procedure called to update IO_DELAY_GROUP when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.IO_DELAY_GROUP { PARAM_VALUE.IO_DELAY_GROUP } {
|
||||
# Procedure called to validate IO_DELAY_GROUP
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.MIMO_ENABLE { PARAM_VALUE.MIMO_ENABLE } {
|
||||
# Procedure called to update MIMO_ENABLE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.MIMO_ENABLE { PARAM_VALUE.MIMO_ENABLE } {
|
||||
# Procedure called to validate MIMO_ENABLE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.MODE_1R1T { PARAM_VALUE.MODE_1R1T } {
|
||||
# Procedure called to update MODE_1R1T when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.MODE_1R1T { PARAM_VALUE.MODE_1R1T } {
|
||||
# Procedure called to validate MODE_1R1T
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.PPS_RECEIVER_ENABLE { PARAM_VALUE.PPS_RECEIVER_ENABLE } {
|
||||
# Procedure called to update PPS_RECEIVER_ENABLE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.PPS_RECEIVER_ENABLE { PARAM_VALUE.PPS_RECEIVER_ENABLE } {
|
||||
# Procedure called to validate PPS_RECEIVER_ENABLE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.RX_NODPA { PARAM_VALUE.RX_NODPA } {
|
||||
# Procedure called to update RX_NODPA when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.RX_NODPA { PARAM_VALUE.RX_NODPA } {
|
||||
# Procedure called to validate RX_NODPA
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } {
|
||||
# Procedure called to update SPEED_GRADE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } {
|
||||
# Procedure called to validate SPEED_GRADE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.TDD_DISABLE { PARAM_VALUE.TDD_DISABLE } {
|
||||
# Procedure called to update TDD_DISABLE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.TDD_DISABLE { PARAM_VALUE.TDD_DISABLE } {
|
||||
# Procedure called to validate TDD_DISABLE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.USE_SSI_CLK { PARAM_VALUE.USE_SSI_CLK } {
|
||||
# Procedure called to update USE_SSI_CLK when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.USE_SSI_CLK { PARAM_VALUE.USE_SSI_CLK } {
|
||||
# Procedure called to validate USE_SSI_CLK
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.MODE_1R1T { MODELPARAM_VALUE.MODE_1R1T PARAM_VALUE.MODE_1R1T } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.MODE_1R1T}] ${MODELPARAM_VALUE.MODE_1R1T}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.FPGA_TECHNOLOGY { MODELPARAM_VALUE.FPGA_TECHNOLOGY PARAM_VALUE.FPGA_TECHNOLOGY } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.FPGA_TECHNOLOGY}] ${MODELPARAM_VALUE.FPGA_TECHNOLOGY}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.FPGA_FAMILY { MODELPARAM_VALUE.FPGA_FAMILY PARAM_VALUE.FPGA_FAMILY } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.FPGA_FAMILY}] ${MODELPARAM_VALUE.FPGA_FAMILY}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.SPEED_GRADE { MODELPARAM_VALUE.SPEED_GRADE PARAM_VALUE.SPEED_GRADE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.SPEED_GRADE}] ${MODELPARAM_VALUE.SPEED_GRADE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DEV_PACKAGE { MODELPARAM_VALUE.DEV_PACKAGE PARAM_VALUE.DEV_PACKAGE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DEV_PACKAGE}] ${MODELPARAM_VALUE.DEV_PACKAGE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.TDD_DISABLE { MODELPARAM_VALUE.TDD_DISABLE PARAM_VALUE.TDD_DISABLE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.TDD_DISABLE}] ${MODELPARAM_VALUE.TDD_DISABLE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.PPS_RECEIVER_ENABLE { MODELPARAM_VALUE.PPS_RECEIVER_ENABLE PARAM_VALUE.PPS_RECEIVER_ENABLE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.PPS_RECEIVER_ENABLE}] ${MODELPARAM_VALUE.PPS_RECEIVER_ENABLE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.CMOS_OR_LVDS_N { MODELPARAM_VALUE.CMOS_OR_LVDS_N PARAM_VALUE.CMOS_OR_LVDS_N } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.CMOS_OR_LVDS_N}] ${MODELPARAM_VALUE.CMOS_OR_LVDS_N}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.ADC_INIT_DELAY { MODELPARAM_VALUE.ADC_INIT_DELAY PARAM_VALUE.ADC_INIT_DELAY } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ADC_INIT_DELAY}] ${MODELPARAM_VALUE.ADC_INIT_DELAY}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.ADC_DATAPATH_DISABLE { MODELPARAM_VALUE.ADC_DATAPATH_DISABLE PARAM_VALUE.ADC_DATAPATH_DISABLE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ADC_DATAPATH_DISABLE}] ${MODELPARAM_VALUE.ADC_DATAPATH_DISABLE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.ADC_USERPORTS_DISABLE { MODELPARAM_VALUE.ADC_USERPORTS_DISABLE PARAM_VALUE.ADC_USERPORTS_DISABLE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ADC_USERPORTS_DISABLE}] ${MODELPARAM_VALUE.ADC_USERPORTS_DISABLE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.ADC_DATAFORMAT_DISABLE { MODELPARAM_VALUE.ADC_DATAFORMAT_DISABLE PARAM_VALUE.ADC_DATAFORMAT_DISABLE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ADC_DATAFORMAT_DISABLE}] ${MODELPARAM_VALUE.ADC_DATAFORMAT_DISABLE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.ADC_DCFILTER_DISABLE { MODELPARAM_VALUE.ADC_DCFILTER_DISABLE PARAM_VALUE.ADC_DCFILTER_DISABLE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ADC_DCFILTER_DISABLE}] ${MODELPARAM_VALUE.ADC_DCFILTER_DISABLE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.ADC_IQCORRECTION_DISABLE { MODELPARAM_VALUE.ADC_IQCORRECTION_DISABLE PARAM_VALUE.ADC_IQCORRECTION_DISABLE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ADC_IQCORRECTION_DISABLE}] ${MODELPARAM_VALUE.ADC_IQCORRECTION_DISABLE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DAC_INIT_DELAY { MODELPARAM_VALUE.DAC_INIT_DELAY PARAM_VALUE.DAC_INIT_DELAY } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DAC_INIT_DELAY}] ${MODELPARAM_VALUE.DAC_INIT_DELAY}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DAC_CLK_EDGE_SEL { MODELPARAM_VALUE.DAC_CLK_EDGE_SEL PARAM_VALUE.DAC_CLK_EDGE_SEL } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DAC_CLK_EDGE_SEL}] ${MODELPARAM_VALUE.DAC_CLK_EDGE_SEL}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DAC_IODELAY_ENABLE { MODELPARAM_VALUE.DAC_IODELAY_ENABLE PARAM_VALUE.DAC_IODELAY_ENABLE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DAC_IODELAY_ENABLE}] ${MODELPARAM_VALUE.DAC_IODELAY_ENABLE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DAC_DATAPATH_DISABLE { MODELPARAM_VALUE.DAC_DATAPATH_DISABLE PARAM_VALUE.DAC_DATAPATH_DISABLE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DAC_DATAPATH_DISABLE}] ${MODELPARAM_VALUE.DAC_DATAPATH_DISABLE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DAC_DDS_DISABLE { MODELPARAM_VALUE.DAC_DDS_DISABLE PARAM_VALUE.DAC_DDS_DISABLE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DAC_DDS_DISABLE}] ${MODELPARAM_VALUE.DAC_DDS_DISABLE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DAC_DDS_TYPE { MODELPARAM_VALUE.DAC_DDS_TYPE PARAM_VALUE.DAC_DDS_TYPE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DAC_DDS_TYPE}] ${MODELPARAM_VALUE.DAC_DDS_TYPE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DAC_DDS_CORDIC_DW { MODELPARAM_VALUE.DAC_DDS_CORDIC_DW PARAM_VALUE.DAC_DDS_CORDIC_DW } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DAC_DDS_CORDIC_DW}] ${MODELPARAM_VALUE.DAC_DDS_CORDIC_DW}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW { MODELPARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW}] ${MODELPARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DAC_USERPORTS_DISABLE { MODELPARAM_VALUE.DAC_USERPORTS_DISABLE PARAM_VALUE.DAC_USERPORTS_DISABLE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DAC_USERPORTS_DISABLE}] ${MODELPARAM_VALUE.DAC_USERPORTS_DISABLE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DAC_IQCORRECTION_DISABLE { MODELPARAM_VALUE.DAC_IQCORRECTION_DISABLE PARAM_VALUE.DAC_IQCORRECTION_DISABLE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DAC_IQCORRECTION_DISABLE}] ${MODELPARAM_VALUE.DAC_IQCORRECTION_DISABLE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.IO_DELAY_GROUP { MODELPARAM_VALUE.IO_DELAY_GROUP PARAM_VALUE.IO_DELAY_GROUP } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.IO_DELAY_GROUP}] ${MODELPARAM_VALUE.IO_DELAY_GROUP}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.MIMO_ENABLE { MODELPARAM_VALUE.MIMO_ENABLE PARAM_VALUE.MIMO_ENABLE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.MIMO_ENABLE}] ${MODELPARAM_VALUE.MIMO_ENABLE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.USE_SSI_CLK { MODELPARAM_VALUE.USE_SSI_CLK PARAM_VALUE.USE_SSI_CLK } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.USE_SSI_CLK}] ${MODELPARAM_VALUE.USE_SSI_CLK}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DELAY_REFCLK_FREQUENCY { MODELPARAM_VALUE.DELAY_REFCLK_FREQUENCY PARAM_VALUE.DELAY_REFCLK_FREQUENCY } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DELAY_REFCLK_FREQUENCY}] ${MODELPARAM_VALUE.DELAY_REFCLK_FREQUENCY}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.RX_NODPA { MODELPARAM_VALUE.RX_NODPA PARAM_VALUE.RX_NODPA } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.RX_NODPA}] ${MODELPARAM_VALUE.RX_NODPA}
|
||||
}
|
||||
|
||||
@@ -0,0 +1,618 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module axi_ad9361_cmos_if #(
|
||||
|
||||
parameter FPGA_TECHNOLOGY = 0,
|
||||
parameter DAC_IODELAY_ENABLE = 0,
|
||||
parameter IO_DELAY_GROUP = "dev_if_delay_group",
|
||||
parameter CLK_DESKEW = 0,
|
||||
parameter USE_SSI_CLK = 1,
|
||||
parameter DELAY_REFCLK_FREQUENCY = 200) (
|
||||
|
||||
// physical interface (receive)
|
||||
|
||||
input rx_clk_in,
|
||||
input rx_frame_in,
|
||||
input [11:0] rx_data_in,
|
||||
|
||||
// physical interface (transmit)
|
||||
|
||||
output tx_clk_out,
|
||||
output tx_frame_out,
|
||||
output [11:0] tx_data_out,
|
||||
|
||||
// ensm control
|
||||
|
||||
output enable,
|
||||
output txnrx,
|
||||
|
||||
// clock (common to both receive and transmit)
|
||||
|
||||
input rst,
|
||||
input clk,
|
||||
output l_clk,
|
||||
|
||||
// receive data path interface
|
||||
|
||||
output adc_valid,
|
||||
output [47:0] adc_data,
|
||||
output adc_status,
|
||||
input adc_r1_mode,
|
||||
input adc_ddr_edgesel,
|
||||
|
||||
// transmit data path interface
|
||||
|
||||
input dac_valid,
|
||||
input [47:0] dac_data,
|
||||
input dac_clksel,
|
||||
input dac_r1_mode,
|
||||
|
||||
// tdd interface
|
||||
|
||||
input tdd_enable,
|
||||
input tdd_txnrx,
|
||||
input tdd_mode,
|
||||
|
||||
// delay interface
|
||||
|
||||
input mmcm_rst,
|
||||
input up_clk,
|
||||
input up_rstn,
|
||||
input up_enable,
|
||||
input up_txnrx,
|
||||
input [12:0] up_adc_dld,
|
||||
input [64:0] up_adc_dwdata,
|
||||
output [64:0] up_adc_drdata,
|
||||
input [15:0] up_dac_dld,
|
||||
input [79:0] up_dac_dwdata,
|
||||
output [79:0] up_dac_drdata,
|
||||
input delay_clk,
|
||||
input delay_rst,
|
||||
output delay_locked,
|
||||
|
||||
// drp interface
|
||||
|
||||
input up_drp_sel,
|
||||
input up_drp_wr,
|
||||
input [11:0] up_drp_addr,
|
||||
input [31:0] up_drp_wdata,
|
||||
output [31:0] up_drp_rdata,
|
||||
output up_drp_ready,
|
||||
output up_drp_locked);
|
||||
|
||||
// internal registers
|
||||
|
||||
reg adc_r1_mode_n = 'd0;
|
||||
reg rx_r1_mode = 'd0;
|
||||
reg rx_locked_m1 = 'd0;
|
||||
reg rx_locked = 'd0;
|
||||
reg [ 1:0] rx_frame = 'd0;
|
||||
reg [11:0] rx_data_1 = 'd0;
|
||||
reg adc_valid_p = 'd0;
|
||||
reg [47:0] adc_data_p = 'd0;
|
||||
reg adc_status_p = 'd0;
|
||||
reg adc_valid_n = 'd0;
|
||||
reg [47:0] adc_data_n = 'd0;
|
||||
reg adc_status_n = 'd0;
|
||||
reg adc_valid_int = 'd0;
|
||||
reg [47:0] adc_data_int = 'd0;
|
||||
reg adc_status_int = 'd0;
|
||||
reg [ 1:0] tx_clk_p = 'd0;
|
||||
reg [ 1:0] tx_frame_p = 'd0;
|
||||
reg [11:0] tx_data_0_p = 'd0;
|
||||
reg [11:0] tx_data_1_p = 'd0;
|
||||
reg [ 1:0] tx_clk_n = 'd0;
|
||||
reg [ 1:0] tx_frame_n = 'd0;
|
||||
reg [11:0] tx_data_0_n = 'd0;
|
||||
reg [11:0] tx_data_1_n = 'd0;
|
||||
reg [ 1:0] tx_clk = 'd0;
|
||||
reg [ 1:0] tx_frame = 'd0;
|
||||
reg [11:0] tx_data_0 = 'd0;
|
||||
reg [11:0] tx_data_1 = 'd0;
|
||||
reg up_enable_int = 'd0;
|
||||
reg up_txnrx_int = 'd0;
|
||||
reg enable_up_m1 = 'd0;
|
||||
reg txnrx_up_m1 = 'd0;
|
||||
reg enable_up = 'd0;
|
||||
reg txnrx_up = 'd0;
|
||||
reg enable_int = 'd0;
|
||||
reg txnrx_int = 'd0;
|
||||
reg enable_int_p = 'd0;
|
||||
reg txnrx_int_p = 'd0;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire [11:0] rx_data_1_s;
|
||||
wire [11:0] rx_data_0_s;
|
||||
wire [ 1:0] rx_frame_s;
|
||||
wire locked_s;
|
||||
|
||||
// drp interface signals
|
||||
|
||||
assign up_drp_rdata = 32'd0;
|
||||
assign up_drp_ready = 1'd0;
|
||||
assign up_drp_locked = 1'd1;
|
||||
|
||||
// r1mode
|
||||
|
||||
generate if (CLK_DESKEW) begin
|
||||
|
||||
reg adc_r1_mode_n = 'd0;
|
||||
|
||||
always @(negedge clk) begin
|
||||
adc_r1_mode_n <= adc_r1_mode;
|
||||
end
|
||||
|
||||
always @(posedge l_clk) begin
|
||||
rx_r1_mode <= adc_r1_mode_n;
|
||||
end
|
||||
|
||||
end else begin /* CLK_DESKEW == 0 */
|
||||
|
||||
always @(posedge l_clk) begin
|
||||
rx_r1_mode <= adc_r1_mode;
|
||||
end
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// adc-status
|
||||
|
||||
assign delay_locked = locked_s;
|
||||
|
||||
always @(posedge l_clk) begin
|
||||
rx_locked_m1 <= locked_s;
|
||||
rx_locked <= rx_locked_m1;
|
||||
end
|
||||
|
||||
// frame check
|
||||
|
||||
always @(posedge l_clk) begin
|
||||
if (rx_r1_mode == 1'd1) begin
|
||||
rx_frame <= rx_frame_s;
|
||||
end else begin
|
||||
rx_frame <= ~rx_frame_s;
|
||||
end
|
||||
end
|
||||
|
||||
// data hold
|
||||
|
||||
always @(posedge l_clk) begin
|
||||
rx_data_1 <= rx_data_1_s;
|
||||
end
|
||||
|
||||
// delineation
|
||||
|
||||
always @(posedge l_clk) begin
|
||||
case ({rx_r1_mode, rx_frame_s})
|
||||
3'b011: begin
|
||||
adc_valid_p <= 1'b0;
|
||||
adc_data_p[47:24] <= 24'd0;
|
||||
adc_data_p[23: 0] <= {rx_data_1_s, rx_data_0_s};
|
||||
end
|
||||
3'b000: begin
|
||||
adc_valid_p <= 1'b1;
|
||||
adc_data_p[47:24] <= {rx_data_1_s, rx_data_0_s};
|
||||
adc_data_p[23: 0] <= adc_data_p[23:0];
|
||||
end
|
||||
3'b001: begin
|
||||
adc_valid_p <= 1'b0;
|
||||
adc_data_p[47:24] <= 24'd0;
|
||||
adc_data_p[23: 0] <= {rx_data_0_s, rx_data_1};
|
||||
end
|
||||
3'b010: begin
|
||||
adc_valid_p <= 1'b1;
|
||||
adc_data_p[47:24] <= {rx_data_0_s, rx_data_1};
|
||||
adc_data_p[23: 0] <= adc_data_p[23:0];
|
||||
end
|
||||
3'b110: begin
|
||||
adc_valid_p <= 1'b1;
|
||||
adc_data_p[47:24] <= 24'd0;
|
||||
adc_data_p[23: 0] <= {rx_data_0_s, rx_data_1};
|
||||
end
|
||||
3'b101: begin
|
||||
adc_valid_p <= 1'b1;
|
||||
adc_data_p[47:24] <= 24'd0;
|
||||
adc_data_p[23: 0] <= {rx_data_1_s, rx_data_0_s};
|
||||
end
|
||||
default: begin
|
||||
adc_valid_p <= 1'b0;
|
||||
adc_data_p <= 48'd0;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
// adc-status
|
||||
|
||||
always @(posedge l_clk) begin
|
||||
if (rx_frame == rx_frame_s) begin
|
||||
adc_status_p <= rx_locked;
|
||||
end else begin
|
||||
adc_status_p <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
// transfer to common clock
|
||||
|
||||
generate if (CLK_DESKEW) begin
|
||||
|
||||
reg adc_valid_n = 'd0;
|
||||
reg [47:0] adc_data_n = 'd0;
|
||||
reg adc_status_n = 'd0;
|
||||
|
||||
always @(negedge l_clk) begin
|
||||
adc_valid_n <= adc_valid_p;
|
||||
adc_data_n <= adc_data_p;
|
||||
adc_status_n <= adc_status_p;
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
adc_valid_int <= adc_valid_n;
|
||||
adc_data_int <= adc_data_n;
|
||||
adc_status_int <= adc_status_n;
|
||||
end
|
||||
|
||||
assign adc_valid = adc_valid_int;
|
||||
assign adc_data = adc_data_int;
|
||||
assign adc_status = adc_status_int;
|
||||
|
||||
end else begin /* CLK_DESKEW == 0 */
|
||||
|
||||
always @(posedge clk) begin
|
||||
adc_valid_int <= adc_valid_p;
|
||||
adc_data_int <= adc_data_p;
|
||||
adc_status_int <= adc_status_p;
|
||||
end
|
||||
|
||||
assign adc_valid = adc_valid_int;
|
||||
assign adc_data = adc_data_int;
|
||||
assign adc_status = adc_status_int;
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// dac-tx interface
|
||||
|
||||
always @(posedge clk) begin
|
||||
tx_clk_p <= {~dac_clksel, dac_clksel};
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
case ({dac_r1_mode, dac_valid})
|
||||
3'b00: begin
|
||||
tx_frame_p <= 2'b00;
|
||||
tx_data_0_p <= dac_data[35:24];
|
||||
tx_data_1_p <= dac_data[47:36];
|
||||
end
|
||||
2'b01: begin
|
||||
tx_frame_p <= 2'b11;
|
||||
tx_data_0_p <= dac_data[11:0];
|
||||
tx_data_1_p <= dac_data[23:12];
|
||||
end
|
||||
2'b11: begin
|
||||
tx_frame_p <= 2'b01;
|
||||
tx_data_0_p <= dac_data[11:0];
|
||||
tx_data_1_p <= dac_data[23:12];
|
||||
end
|
||||
default: begin
|
||||
tx_frame_p <= 2'd0;
|
||||
tx_data_0_p <= 12'd0;
|
||||
tx_data_1_p <= 12'd0;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
// transfer to local clock
|
||||
|
||||
generate if (CLK_DESKEW) begin
|
||||
|
||||
reg [ 1:0] tx_clk_n = 'd0;
|
||||
reg tx_frame_n = 'd0;
|
||||
reg [ 5:0] tx_data_0_n = 'd0;
|
||||
reg [ 5:0] tx_data_1_n = 'd0;
|
||||
|
||||
always @(negedge clk) begin
|
||||
tx_clk_n <= tx_clk_p;
|
||||
tx_frame_n <= tx_frame_p;
|
||||
tx_data_0_n <= tx_data_0_p;
|
||||
tx_data_1_n <= tx_data_1_p;
|
||||
end
|
||||
|
||||
always @(posedge l_clk) begin
|
||||
tx_clk <= tx_clk_n;
|
||||
tx_frame <= tx_frame_n;
|
||||
tx_data_0 <= tx_data_0_n;
|
||||
tx_data_1 <= tx_data_1_n;
|
||||
end
|
||||
|
||||
end else begin /* CLK_DESKEW == 0 */
|
||||
|
||||
always @(posedge l_clk) begin
|
||||
tx_clk <= tx_clk_p;
|
||||
tx_frame <= tx_frame_p;
|
||||
tx_data_0 <= tx_data_0_p;
|
||||
tx_data_1 <= tx_data_1_p;
|
||||
end
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// tdd/ensm control
|
||||
|
||||
always @(posedge up_clk) begin
|
||||
up_enable_int <= up_enable;
|
||||
up_txnrx_int <= up_txnrx;
|
||||
end
|
||||
|
||||
always @(posedge clk or posedge rst) begin
|
||||
if (rst == 1'b1) begin
|
||||
enable_up_m1 <= 1'b0;
|
||||
txnrx_up_m1 <= 1'b0;
|
||||
enable_up <= 1'b0;
|
||||
txnrx_up <= 1'b0;
|
||||
end else begin
|
||||
enable_up_m1 <= up_enable_int;
|
||||
txnrx_up_m1 <= up_txnrx_int;
|
||||
enable_up <= enable_up_m1;
|
||||
txnrx_up <= txnrx_up_m1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (tdd_mode == 1'b1) begin
|
||||
enable_int <= tdd_enable;
|
||||
txnrx_int <= tdd_txnrx;
|
||||
end else begin
|
||||
enable_int <= enable_up;
|
||||
txnrx_int <= txnrx_up;
|
||||
end
|
||||
end
|
||||
|
||||
generate if (CLK_DESKEW) begin
|
||||
|
||||
reg enable_int_n = 'd0;
|
||||
reg txnrx_int_n = 'd0;
|
||||
|
||||
always @(negedge clk) begin
|
||||
enable_int_n <= enable_int;
|
||||
txnrx_int_n <= txnrx_int;
|
||||
end
|
||||
|
||||
always @(posedge l_clk) begin
|
||||
enable_int_p <= enable_int_n;
|
||||
txnrx_int_p <= txnrx_int_n;
|
||||
end
|
||||
|
||||
end else begin /* CLK_DESKEW == 0 */
|
||||
|
||||
always @(posedge l_clk) begin
|
||||
enable_int_p <= enable_int;
|
||||
txnrx_int_p <= txnrx_int;
|
||||
end
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// receive data interface, ibuf -> idelay -> iddr
|
||||
|
||||
genvar i;
|
||||
generate
|
||||
for (i = 0; i < 12; i = i + 1) begin: g_rx_data
|
||||
ad_data_in #(
|
||||
.SINGLE_ENDED (1),
|
||||
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
|
||||
.IODELAY_CTRL (0),
|
||||
.IODELAY_GROUP (IO_DELAY_GROUP),
|
||||
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
|
||||
i_rx_data (
|
||||
.rx_clk (l_clk),
|
||||
.rx_data_in_p (rx_data_in[i]),
|
||||
.rx_data_in_n (1'd0),
|
||||
.rx_data_p (rx_data_1_s[i]),
|
||||
.rx_data_n (rx_data_0_s[i]),
|
||||
.up_clk (up_clk),
|
||||
.up_dld (up_adc_dld[i]),
|
||||
.up_dwdata (up_adc_dwdata[((i*5)+4):(i*5)]),
|
||||
.up_drdata (up_adc_drdata[((i*5)+4):(i*5)]),
|
||||
.delay_clk (delay_clk),
|
||||
.delay_rst (delay_rst),
|
||||
.delay_locked ());
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// receive frame interface, ibuf -> idelay -> iddr
|
||||
|
||||
ad_data_in #(
|
||||
.SINGLE_ENDED (1),
|
||||
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
|
||||
.IODELAY_CTRL (1),
|
||||
.IODELAY_GROUP (IO_DELAY_GROUP),
|
||||
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
|
||||
i_rx_frame (
|
||||
.rx_clk (l_clk),
|
||||
.rx_data_in_p (rx_frame_in),
|
||||
.rx_data_in_n (1'd0),
|
||||
.rx_data_p (rx_frame_s[1]),
|
||||
.rx_data_n (rx_frame_s[0]),
|
||||
.up_clk (up_clk),
|
||||
.up_dld (up_adc_dld[12]),
|
||||
.up_dwdata (up_adc_dwdata[64:60]),
|
||||
.up_drdata (up_adc_drdata[64:60]),
|
||||
.delay_clk (delay_clk),
|
||||
.delay_rst (delay_rst),
|
||||
.delay_locked (locked_s));
|
||||
|
||||
// transmit data interface, oddr -> obuf
|
||||
|
||||
generate
|
||||
for (i = 0; i < 12; i = i + 1) begin: g_tx_data
|
||||
ad_data_out #(
|
||||
.SINGLE_ENDED (1),
|
||||
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
|
||||
.IODELAY_ENABLE (DAC_IODELAY_ENABLE),
|
||||
.IODELAY_CTRL (0),
|
||||
.IODELAY_GROUP (IO_DELAY_GROUP),
|
||||
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
|
||||
i_tx_data (
|
||||
.tx_clk (l_clk),
|
||||
.tx_data_p (tx_data_1[i]),
|
||||
.tx_data_n (tx_data_0[i]),
|
||||
.tx_data_out_p (tx_data_out[i]),
|
||||
.tx_data_out_n (),
|
||||
.up_clk (up_clk),
|
||||
.up_dld (up_dac_dld[i]),
|
||||
.up_dwdata (up_dac_dwdata[((i*5)+4):(i*5)]),
|
||||
.up_drdata (up_dac_drdata[((i*5)+4):(i*5)]),
|
||||
.delay_clk (delay_clk),
|
||||
.delay_rst (delay_rst),
|
||||
.delay_locked ());
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// transmit frame interface, oddr -> obuf
|
||||
|
||||
ad_data_out #(
|
||||
.SINGLE_ENDED (1),
|
||||
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
|
||||
.IODELAY_ENABLE (DAC_IODELAY_ENABLE),
|
||||
.IODELAY_CTRL (0),
|
||||
.IODELAY_GROUP (IO_DELAY_GROUP),
|
||||
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
|
||||
i_tx_frame (
|
||||
.tx_clk (l_clk),
|
||||
.tx_data_p (tx_frame[1]),
|
||||
.tx_data_n (tx_frame[0]),
|
||||
.tx_data_out_p (tx_frame_out),
|
||||
.tx_data_out_n (),
|
||||
.up_clk (up_clk),
|
||||
.up_dld (up_dac_dld[12]),
|
||||
.up_dwdata (up_dac_dwdata[64:60]),
|
||||
.up_drdata (up_dac_drdata[64:60]),
|
||||
.delay_clk (delay_clk),
|
||||
.delay_rst (delay_rst),
|
||||
.delay_locked ());
|
||||
|
||||
// transmit clock interface, oddr -> obuf
|
||||
|
||||
ad_data_out #(
|
||||
.SINGLE_ENDED (1),
|
||||
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
|
||||
.IODELAY_ENABLE (DAC_IODELAY_ENABLE),
|
||||
.IODELAY_CTRL (0),
|
||||
.IODELAY_GROUP (IO_DELAY_GROUP),
|
||||
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
|
||||
i_tx_clk (
|
||||
.tx_clk (l_clk),
|
||||
.tx_data_p (tx_clk[1]),
|
||||
.tx_data_n (tx_clk[0]),
|
||||
.tx_data_out_p (tx_clk_out),
|
||||
.tx_data_out_n (),
|
||||
.up_clk (up_clk),
|
||||
.up_dld (up_dac_dld[13]),
|
||||
.up_dwdata (up_dac_dwdata[69:65]),
|
||||
.up_drdata (up_dac_drdata[69:65]),
|
||||
.delay_clk (delay_clk),
|
||||
.delay_rst (delay_rst),
|
||||
.delay_locked ());
|
||||
|
||||
// enable, oddr -> obuf
|
||||
|
||||
ad_data_out #(
|
||||
.SINGLE_ENDED (1),
|
||||
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
|
||||
.IODELAY_ENABLE (DAC_IODELAY_ENABLE),
|
||||
.IODELAY_CTRL (0),
|
||||
.IODELAY_GROUP (IO_DELAY_GROUP),
|
||||
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
|
||||
i_enable (
|
||||
.tx_clk (l_clk),
|
||||
.tx_data_p (enable_int_p),
|
||||
.tx_data_n (enable_int_p),
|
||||
.tx_data_out_p (enable),
|
||||
.tx_data_out_n (),
|
||||
.up_clk (up_clk),
|
||||
.up_dld (up_dac_dld[14]),
|
||||
.up_dwdata (up_dac_dwdata[74:70]),
|
||||
.up_drdata (up_dac_drdata[74:70]),
|
||||
.delay_clk (delay_clk),
|
||||
.delay_rst (delay_rst),
|
||||
.delay_locked ());
|
||||
|
||||
// txnrx, oddr -> obuf
|
||||
|
||||
ad_data_out #(
|
||||
.SINGLE_ENDED (1),
|
||||
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
|
||||
.IODELAY_ENABLE (DAC_IODELAY_ENABLE),
|
||||
.IODELAY_CTRL (0),
|
||||
.IODELAY_GROUP (IO_DELAY_GROUP),
|
||||
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
|
||||
i_txnrx (
|
||||
.tx_clk (l_clk),
|
||||
.tx_data_p (txnrx_int_p),
|
||||
.tx_data_n (txnrx_int_p),
|
||||
.tx_data_out_p (txnrx),
|
||||
.tx_data_out_n (),
|
||||
.up_clk (up_clk),
|
||||
.up_dld (up_dac_dld[15]),
|
||||
.up_dwdata (up_dac_dwdata[79:75]),
|
||||
.up_drdata (up_dac_drdata[79:75]),
|
||||
.delay_clk (delay_clk),
|
||||
.delay_rst (delay_rst),
|
||||
.delay_locked ());
|
||||
|
||||
// device clock interface (receive clock)
|
||||
|
||||
generate if (USE_SSI_CLK == 1) begin
|
||||
ad_data_clk #(
|
||||
.SINGLE_ENDED (1))
|
||||
i_clk (
|
||||
.rst (1'd0),
|
||||
.locked (),
|
||||
.clk_in_p (rx_clk_in),
|
||||
.clk_in_n (1'd0),
|
||||
.clk (l_clk));
|
||||
end else begin
|
||||
assign l_clk = clk;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
@@ -0,0 +1,627 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module axi_ad9361_lvds_if #(
|
||||
|
||||
parameter FPGA_TECHNOLOGY = 0,
|
||||
parameter DAC_IODELAY_ENABLE = 0,
|
||||
parameter IO_DELAY_GROUP = "dev_if_delay_group",
|
||||
parameter CLK_DESKEW = 0,
|
||||
parameter USE_SSI_CLK = 1,
|
||||
parameter DELAY_REFCLK_FREQUENCY = 200,
|
||||
parameter RX_NODPA = 0) (
|
||||
|
||||
// physical interface (receive)
|
||||
|
||||
input rx_clk_in_p,
|
||||
input rx_clk_in_n,
|
||||
input rx_frame_in_p,
|
||||
input rx_frame_in_n,
|
||||
input [ 5:0] rx_data_in_p,
|
||||
input [ 5:0] rx_data_in_n,
|
||||
|
||||
// physical interface (transmit)
|
||||
|
||||
output tx_clk_out_p,
|
||||
output tx_clk_out_n,
|
||||
output tx_frame_out_p,
|
||||
output tx_frame_out_n,
|
||||
output [ 5:0] tx_data_out_p,
|
||||
output [ 5:0] tx_data_out_n,
|
||||
|
||||
// ensm control
|
||||
|
||||
output enable,
|
||||
output txnrx,
|
||||
|
||||
// clock (common to both receive and transmit)
|
||||
|
||||
input rst,
|
||||
input clk,
|
||||
output l_clk,
|
||||
|
||||
// receive data path interface
|
||||
|
||||
output adc_valid,
|
||||
output [47:0] adc_data,
|
||||
output adc_status,
|
||||
input adc_r1_mode,
|
||||
input adc_ddr_edgesel,
|
||||
|
||||
// transmit data path interface
|
||||
|
||||
input dac_valid,
|
||||
input [47:0] dac_data,
|
||||
input dac_clksel,
|
||||
input dac_r1_mode,
|
||||
|
||||
// tdd interface
|
||||
|
||||
input tdd_enable,
|
||||
input tdd_txnrx,
|
||||
input tdd_mode,
|
||||
|
||||
// delay interface
|
||||
|
||||
input mmcm_rst,
|
||||
input up_clk,
|
||||
input up_rstn,
|
||||
input up_enable,
|
||||
input up_txnrx,
|
||||
input [ 6:0] up_adc_dld,
|
||||
input [34:0] up_adc_dwdata,
|
||||
output [34:0] up_adc_drdata,
|
||||
input [ 9:0] up_dac_dld,
|
||||
input [49:0] up_dac_dwdata,
|
||||
output [49:0] up_dac_drdata,
|
||||
input delay_clk,
|
||||
input delay_rst,
|
||||
output delay_locked,
|
||||
|
||||
// drp interface
|
||||
|
||||
input up_drp_sel,
|
||||
input up_drp_wr,
|
||||
input [11:0] up_drp_addr,
|
||||
input [31:0] up_drp_wdata,
|
||||
output [31:0] up_drp_rdata,
|
||||
output up_drp_ready,
|
||||
output up_drp_locked);
|
||||
|
||||
// internal registers
|
||||
|
||||
reg rx_r1_mode = 'd0;
|
||||
reg rx_locked_m1 = 'd0;
|
||||
reg rx_locked = 'd0;
|
||||
reg [ 1:0] rx_frame = 'd0;
|
||||
reg [ 5:0] rx_data_1 = 'd0;
|
||||
reg [ 5:0] rx_data_0 = 'd0;
|
||||
reg adc_valid_p = 'd0;
|
||||
reg [47:0] adc_data_p = 'd0;
|
||||
reg adc_status_p = 'd0;
|
||||
reg adc_valid_int = 'd0;
|
||||
reg [47:0] adc_data_int = 'd0;
|
||||
reg adc_status_int = 'd0;
|
||||
reg [ 1:0] tx_data_sel = 'd0;
|
||||
reg [47:0] tx_data = 'd0;
|
||||
reg [ 1:0] tx_clk_p = 'd0;
|
||||
reg tx_frame_p = 'd0;
|
||||
reg [ 5:0] tx_data_0_p = 'd0;
|
||||
reg [ 5:0] tx_data_1_p = 'd0;
|
||||
reg [ 1:0] tx_clk = 'd0;
|
||||
reg tx_frame = 'd0;
|
||||
reg [ 5:0] tx_data_0 = 'd0;
|
||||
reg [ 5:0] tx_data_1 = 'd0;
|
||||
reg up_enable_int = 'd0;
|
||||
reg up_txnrx_int = 'd0;
|
||||
reg enable_up_m1 = 'd0;
|
||||
reg txnrx_up_m1 = 'd0;
|
||||
reg enable_up = 'd0;
|
||||
reg txnrx_up = 'd0;
|
||||
reg enable_int = 'd0;
|
||||
reg txnrx_int = 'd0;
|
||||
reg enable_int_p = 'd0;
|
||||
reg txnrx_int_p = 'd0;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire [ 5:0] rx_data_1_s;
|
||||
wire [ 5:0] rx_data_0_s;
|
||||
wire [ 1:0] rx_frame_s;
|
||||
wire locked_s;
|
||||
|
||||
// drp interface signals
|
||||
|
||||
assign up_drp_rdata = 32'd0;
|
||||
assign up_drp_ready = 1'd0;
|
||||
assign up_drp_locked = 1'd1;
|
||||
|
||||
// r1mode
|
||||
|
||||
generate if (CLK_DESKEW) begin
|
||||
|
||||
reg adc_r1_mode_n = 'd0;
|
||||
|
||||
always @(negedge clk) begin
|
||||
adc_r1_mode_n <= adc_r1_mode;
|
||||
end
|
||||
|
||||
always @(posedge l_clk) begin
|
||||
rx_r1_mode <= adc_r1_mode_n;
|
||||
end
|
||||
|
||||
end else begin /* CLK_DESKEW == 0 */
|
||||
|
||||
always @(posedge l_clk) begin
|
||||
rx_r1_mode <= adc_r1_mode;
|
||||
end
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// adc-status
|
||||
|
||||
assign delay_locked = locked_s;
|
||||
|
||||
always @(posedge l_clk) begin
|
||||
rx_locked_m1 <= locked_s;
|
||||
rx_locked <= rx_locked_m1;
|
||||
end
|
||||
|
||||
// intel-equivalence
|
||||
|
||||
always @(posedge l_clk) begin
|
||||
rx_frame <= rx_frame_s;
|
||||
rx_data_1 <= rx_data_1_s;
|
||||
rx_data_0 <= rx_data_0_s;
|
||||
end
|
||||
|
||||
// frame check
|
||||
|
||||
|
||||
// delineation
|
||||
reg rx_error_r1 = 'd0;
|
||||
reg rx_error_r2 = 'd0;
|
||||
|
||||
always @(posedge l_clk) begin
|
||||
rx_error_r1 <= ~((rx_frame_s == 4'b1100) || (rx_frame_s == 4'b0011));
|
||||
rx_error_r2 <= ~((rx_frame_s == 4'b1111) || (rx_frame_s == 4'b1100) ||
|
||||
(rx_frame_s == 4'b0000) || (rx_frame_s == 4'b0011));
|
||||
end
|
||||
|
||||
always @(posedge l_clk) begin
|
||||
case ({rx_r1_mode, rx_frame_s, rx_frame})
|
||||
5'b01111: begin
|
||||
adc_valid_p <= 1'b0;
|
||||
adc_data_p[23:12] <= {rx_data_1, rx_data_1_s};
|
||||
adc_data_p[11: 0] <= {rx_data_0, rx_data_0_s};
|
||||
end
|
||||
5'b00000: begin
|
||||
adc_valid_p <= 1'b1;
|
||||
adc_data_p[47:36] <= {rx_data_1, rx_data_1_s};
|
||||
adc_data_p[35:24] <= {rx_data_0, rx_data_0_s};
|
||||
end
|
||||
5'b10011: begin
|
||||
adc_valid_p <= 1'b1;
|
||||
adc_data_p[47:24] <= 24'd0;
|
||||
adc_data_p[23:12] <= {rx_data_1, rx_data_1_s};
|
||||
adc_data_p[11: 0] <= {rx_data_0, rx_data_0_s};
|
||||
end
|
||||
default: begin
|
||||
adc_valid_p <= 1'b0;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
// adc-status
|
||||
|
||||
always @(posedge l_clk) begin
|
||||
if (adc_r1_mode == 1'b1) begin
|
||||
adc_status_p <= ~rx_error_r1 & rx_locked;
|
||||
end else begin
|
||||
adc_status_p <= ~rx_error_r2 & rx_locked;
|
||||
end
|
||||
end
|
||||
|
||||
// transfer to common clock
|
||||
|
||||
generate if (CLK_DESKEW) begin
|
||||
|
||||
reg adc_valid_n = 'd0;
|
||||
reg [47:0] adc_data_n = 'd0;
|
||||
reg adc_status_n = 'd0;
|
||||
|
||||
always @(negedge l_clk) begin
|
||||
adc_valid_n <= adc_valid_p;
|
||||
adc_data_n <= adc_data_p;
|
||||
adc_status_n <= adc_status_p;
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
adc_valid_int <= adc_valid_n;
|
||||
adc_data_int <= adc_data_n;
|
||||
adc_status_int <= adc_status_n;
|
||||
end
|
||||
|
||||
assign adc_valid = adc_valid_int;
|
||||
assign adc_data = adc_data_int;
|
||||
assign adc_status = adc_status_int;
|
||||
|
||||
end else begin /* CLK_DESKEW == 0 */
|
||||
|
||||
always @(posedge clk) begin
|
||||
adc_valid_int <= adc_valid_p;
|
||||
adc_data_int <= adc_data_p;
|
||||
adc_status_int <= adc_status_p;
|
||||
end
|
||||
|
||||
assign adc_valid = adc_valid_int;
|
||||
assign adc_data = adc_data_int;
|
||||
assign adc_status = adc_status_int;
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// dac-tx interface
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (dac_valid == 1'b1) begin
|
||||
tx_data_sel <= 2'b00;
|
||||
end else begin
|
||||
tx_data_sel <= tx_data_sel + 1'b1;
|
||||
end
|
||||
if (dac_valid == 1'b1) begin
|
||||
tx_data <= dac_data;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
tx_clk_p <= {~dac_clksel, dac_clksel};
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
case ({dac_r1_mode, tx_data_sel})
|
||||
3'b000: begin
|
||||
tx_frame_p <= 1'b1;
|
||||
tx_data_0_p <= tx_data[11:6];
|
||||
tx_data_1_p <= tx_data[23:18];
|
||||
end
|
||||
3'b001: begin
|
||||
tx_frame_p <= 1'b1;
|
||||
tx_data_0_p <= tx_data[5:0];
|
||||
tx_data_1_p <= tx_data[17:12];
|
||||
end
|
||||
3'b010: begin
|
||||
tx_frame_p <= 1'b0;
|
||||
tx_data_0_p <= tx_data[35:30];
|
||||
tx_data_1_p <= tx_data[47:42];
|
||||
end
|
||||
3'b011: begin
|
||||
tx_frame_p <= 1'b0;
|
||||
tx_data_0_p <= tx_data[29:24];
|
||||
tx_data_1_p <= tx_data[41:36];
|
||||
end
|
||||
3'b100: begin
|
||||
tx_frame_p <= 1'b1;
|
||||
tx_data_0_p <= tx_data[11:6];
|
||||
tx_data_1_p <= tx_data[23:18];
|
||||
end
|
||||
3'b101: begin
|
||||
tx_frame_p <= 1'b0;
|
||||
tx_data_0_p <= tx_data[5:0];
|
||||
tx_data_1_p <= tx_data[17:12];
|
||||
end
|
||||
default: begin
|
||||
tx_frame_p <= 1'b0;
|
||||
tx_data_0_p <= 6'd0;
|
||||
tx_data_1_p <= 6'd0;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
// transfer to local clock
|
||||
|
||||
generate if (CLK_DESKEW) begin
|
||||
|
||||
reg [ 1:0] tx_clk_n = 'd0;
|
||||
reg tx_frame_n = 'd0;
|
||||
reg [ 5:0] tx_data_0_n = 'd0;
|
||||
reg [ 5:0] tx_data_1_n = 'd0;
|
||||
|
||||
always @(negedge clk) begin
|
||||
tx_clk_n <= tx_clk_p;
|
||||
tx_frame_n <= tx_frame_p;
|
||||
tx_data_0_n <= tx_data_0_p;
|
||||
tx_data_1_n <= tx_data_1_p;
|
||||
end
|
||||
|
||||
always @(posedge l_clk) begin
|
||||
tx_clk <= tx_clk_n;
|
||||
tx_frame <= tx_frame_n;
|
||||
tx_data_0 <= tx_data_0_n;
|
||||
tx_data_1 <= tx_data_1_n;
|
||||
end
|
||||
|
||||
end else begin /* CLK_DESKEW == 0 */
|
||||
|
||||
always @(posedge l_clk) begin
|
||||
tx_clk <= tx_clk_p;
|
||||
tx_frame <= tx_frame_p;
|
||||
tx_data_0 <= tx_data_0_p;
|
||||
tx_data_1 <= tx_data_1_p;
|
||||
end
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// tdd/ensm control
|
||||
|
||||
always @(posedge up_clk) begin
|
||||
up_enable_int <= up_enable;
|
||||
up_txnrx_int <= up_txnrx;
|
||||
end
|
||||
|
||||
always @(posedge clk or posedge rst) begin
|
||||
if (rst == 1'b1) begin
|
||||
enable_up_m1 <= 1'b0;
|
||||
txnrx_up_m1 <= 1'b0;
|
||||
enable_up <= 1'b0;
|
||||
txnrx_up <= 1'b0;
|
||||
end else begin
|
||||
enable_up_m1 <= up_enable_int;
|
||||
txnrx_up_m1 <= up_txnrx_int;
|
||||
enable_up <= enable_up_m1;
|
||||
txnrx_up <= txnrx_up_m1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (tdd_mode == 1'b1) begin
|
||||
enable_int <= tdd_enable;
|
||||
txnrx_int <= tdd_txnrx;
|
||||
end else begin
|
||||
enable_int <= enable_up;
|
||||
txnrx_int <= txnrx_up;
|
||||
end
|
||||
end
|
||||
|
||||
generate if (CLK_DESKEW) begin
|
||||
|
||||
reg enable_int_n = 'd0;
|
||||
reg txnrx_int_n = 'd0;
|
||||
|
||||
always @(negedge clk) begin
|
||||
enable_int_n <= enable_int;
|
||||
txnrx_int_n <= txnrx_int;
|
||||
end
|
||||
|
||||
always @(posedge l_clk) begin
|
||||
enable_int_p <= enable_int_n;
|
||||
txnrx_int_p <= txnrx_int_n;
|
||||
end
|
||||
|
||||
end else begin /* CLK_DESKEW == 0 */
|
||||
|
||||
always @(posedge l_clk) begin
|
||||
enable_int_p <= enable_int;
|
||||
txnrx_int_p <= txnrx_int;
|
||||
end
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// receive data interface, ibuf -> idelay -> iddr
|
||||
|
||||
genvar i;
|
||||
generate
|
||||
for (i = 0; i < 6; i = i + 1) begin: g_rx_data
|
||||
ad_data_in #(
|
||||
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
|
||||
.IODELAY_CTRL (0),
|
||||
.IODELAY_GROUP (IO_DELAY_GROUP),
|
||||
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
|
||||
i_rx_data (
|
||||
.rx_clk (l_clk),
|
||||
.rx_data_in_p (rx_data_in_p[i]),
|
||||
.rx_data_in_n (rx_data_in_n[i]),
|
||||
.rx_data_p (rx_data_1_s[i]),
|
||||
.rx_data_n (rx_data_0_s[i]),
|
||||
.up_clk (up_clk),
|
||||
.up_dld (up_adc_dld[i]),
|
||||
.up_dwdata (up_adc_dwdata[((i*5)+4):(i*5)]),
|
||||
.up_drdata (up_adc_drdata[((i*5)+4):(i*5)]),
|
||||
.delay_clk (delay_clk),
|
||||
.delay_rst (delay_rst),
|
||||
.delay_locked ());
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// receive frame interface, ibuf -> idelay -> iddr
|
||||
|
||||
ad_data_in #(
|
||||
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
|
||||
.IODELAY_CTRL (1),
|
||||
.IODELAY_GROUP (IO_DELAY_GROUP),
|
||||
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
|
||||
i_rx_frame (
|
||||
.rx_clk (l_clk),
|
||||
.rx_data_in_p (rx_frame_in_p),
|
||||
.rx_data_in_n (rx_frame_in_n),
|
||||
.rx_data_p (rx_frame_s[1]),
|
||||
.rx_data_n (rx_frame_s[0]),
|
||||
.up_clk (up_clk),
|
||||
.up_dld (up_adc_dld[6]),
|
||||
.up_dwdata (up_adc_dwdata[34:30]),
|
||||
.up_drdata (up_adc_drdata[34:30]),
|
||||
.delay_clk (delay_clk),
|
||||
.delay_rst (delay_rst),
|
||||
.delay_locked (locked_s));
|
||||
|
||||
// transmit data interface, oddr -> obuf
|
||||
|
||||
generate
|
||||
for (i = 0; i < 6; i = i + 1) begin: g_tx_data
|
||||
ad_data_out #(
|
||||
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
|
||||
.IODELAY_ENABLE (DAC_IODELAY_ENABLE),
|
||||
.IODELAY_CTRL (0),
|
||||
.IODELAY_GROUP (IO_DELAY_GROUP),
|
||||
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
|
||||
i_tx_data (
|
||||
.tx_clk (l_clk),
|
||||
.tx_data_p (tx_data_1[i]),
|
||||
.tx_data_n (tx_data_0[i]),
|
||||
.tx_data_out_p (tx_data_out_p[i]),
|
||||
.tx_data_out_n (tx_data_out_n[i]),
|
||||
.up_clk (up_clk),
|
||||
.up_dld (up_dac_dld[i]),
|
||||
.up_dwdata (up_dac_dwdata[((i*5)+4):(i*5)]),
|
||||
.up_drdata (up_dac_drdata[((i*5)+4):(i*5)]),
|
||||
.delay_clk (delay_clk),
|
||||
.delay_rst (delay_rst),
|
||||
.delay_locked ());
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// transmit frame interface, oddr -> obuf
|
||||
|
||||
ad_data_out #(
|
||||
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
|
||||
.IODELAY_ENABLE (DAC_IODELAY_ENABLE),
|
||||
.IODELAY_CTRL (0),
|
||||
.IODELAY_GROUP (IO_DELAY_GROUP),
|
||||
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
|
||||
i_tx_frame (
|
||||
.tx_clk (l_clk),
|
||||
.tx_data_p (tx_frame),
|
||||
.tx_data_n (tx_frame),
|
||||
.tx_data_out_p (tx_frame_out_p),
|
||||
.tx_data_out_n (tx_frame_out_n),
|
||||
.up_clk (up_clk),
|
||||
.up_dld (up_dac_dld[6]),
|
||||
.up_dwdata (up_dac_dwdata[34:30]),
|
||||
.up_drdata (up_dac_drdata[34:30]),
|
||||
.delay_clk (delay_clk),
|
||||
.delay_rst (delay_rst),
|
||||
.delay_locked ());
|
||||
|
||||
// transmit clock interface, oddr -> obuf
|
||||
|
||||
ad_data_out #(
|
||||
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
|
||||
.IODELAY_ENABLE (DAC_IODELAY_ENABLE),
|
||||
.IODELAY_CTRL (0),
|
||||
.IODELAY_GROUP (IO_DELAY_GROUP),
|
||||
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
|
||||
i_tx_clk (
|
||||
.tx_clk (l_clk),
|
||||
.tx_data_p (tx_clk[1]),
|
||||
.tx_data_n (tx_clk[0]),
|
||||
.tx_data_out_p (tx_clk_out_p),
|
||||
.tx_data_out_n (tx_clk_out_n),
|
||||
.up_clk (up_clk),
|
||||
.up_dld (up_dac_dld[7]),
|
||||
.up_dwdata (up_dac_dwdata[39:35]),
|
||||
.up_drdata (up_dac_drdata[39:35]),
|
||||
.delay_clk (delay_clk),
|
||||
.delay_rst (delay_rst),
|
||||
.delay_locked ());
|
||||
|
||||
// enable, oddr -> obuf
|
||||
|
||||
ad_data_out #(
|
||||
.SINGLE_ENDED (1),
|
||||
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
|
||||
.IODELAY_ENABLE (DAC_IODELAY_ENABLE),
|
||||
.IODELAY_CTRL (0),
|
||||
.IODELAY_GROUP (IO_DELAY_GROUP),
|
||||
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
|
||||
i_enable (
|
||||
.tx_clk (l_clk),
|
||||
.tx_data_p (enable_int_p),
|
||||
.tx_data_n (enable_int_p),
|
||||
.tx_data_out_p (enable),
|
||||
.tx_data_out_n (),
|
||||
.up_clk (up_clk),
|
||||
.up_dld (up_dac_dld[8]),
|
||||
.up_dwdata (up_dac_dwdata[44:40]),
|
||||
.up_drdata (up_dac_drdata[44:40]),
|
||||
.delay_clk (delay_clk),
|
||||
.delay_rst (delay_rst),
|
||||
.delay_locked ());
|
||||
|
||||
// txnrx, oddr -> obuf
|
||||
|
||||
ad_data_out #(
|
||||
.SINGLE_ENDED (1),
|
||||
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
|
||||
.IODELAY_ENABLE (DAC_IODELAY_ENABLE),
|
||||
.IODELAY_CTRL (0),
|
||||
.IODELAY_GROUP (IO_DELAY_GROUP),
|
||||
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
|
||||
i_txnrx (
|
||||
.tx_clk (l_clk),
|
||||
.tx_data_p (txnrx_int_p),
|
||||
.tx_data_n (txnrx_int_p),
|
||||
.tx_data_out_p (txnrx),
|
||||
.tx_data_out_n (),
|
||||
.up_clk (up_clk),
|
||||
.up_dld (up_dac_dld[9]),
|
||||
.up_dwdata (up_dac_dwdata[49:45]),
|
||||
.up_drdata (up_dac_drdata[49:45]),
|
||||
.delay_clk (delay_clk),
|
||||
.delay_rst (delay_rst),
|
||||
.delay_locked ());
|
||||
|
||||
// device clock interface (receive clock)
|
||||
generate if (USE_SSI_CLK == 1) begin
|
||||
ad_data_clk
|
||||
i_clk (
|
||||
.rst (1'd0),
|
||||
.locked (),
|
||||
.clk_in_p (rx_clk_in_p),
|
||||
.clk_in_n (rx_clk_in_n),
|
||||
.clk (l_clk));
|
||||
end else begin
|
||||
assign l_clk = clk;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
Reference in New Issue
Block a user