Archived
first commit after restructuring
This commit is contained in:
@@ -0,0 +1,50 @@
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####################################################################################
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## Copyright 2018(c) Analog Devices, Inc.
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## Auto-generated, do not modify!
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||||
####################################################################################
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LIBRARY_NAME := axi_ad9371
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GENERIC_DEPS += ../common/ad_datafmt.v
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GENERIC_DEPS += ../common/ad_dds.v
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GENERIC_DEPS += ../common/ad_dds_1.v
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GENERIC_DEPS += ../common/ad_dds_2.v
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GENERIC_DEPS += ../common/ad_dds_cordic_pipe.v
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GENERIC_DEPS += ../common/ad_dds_sine.v
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GENERIC_DEPS += ../common/ad_dds_sine_cordic.v
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GENERIC_DEPS += ../common/ad_iqcor.v
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GENERIC_DEPS += ../common/ad_rst.v
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||||
GENERIC_DEPS += ../common/ad_xcvr_rx_if.v
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||||
GENERIC_DEPS += ../common/up_adc_channel.v
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GENERIC_DEPS += ../common/up_adc_common.v
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GENERIC_DEPS += ../common/up_axi.v
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GENERIC_DEPS += ../common/up_clock_mon.v
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GENERIC_DEPS += ../common/up_dac_channel.v
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GENERIC_DEPS += ../common/up_dac_common.v
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GENERIC_DEPS += ../common/up_xfer_cntrl.v
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GENERIC_DEPS += ../common/up_xfer_status.v
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GENERIC_DEPS += axi_ad9371.v
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||||
GENERIC_DEPS += axi_ad9371_if.v
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GENERIC_DEPS += axi_ad9371_rx.v
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GENERIC_DEPS += axi_ad9371_rx_channel.v
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GENERIC_DEPS += axi_ad9371_rx_os.v
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GENERIC_DEPS += axi_ad9371_tx.v
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GENERIC_DEPS += axi_ad9371_tx_channel.v
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XILINX_DEPS += ../xilinx/common/ad_dcfilter.v
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XILINX_DEPS += ../xilinx/common/ad_mul.v
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XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc
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XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc
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XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
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XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc
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XILINX_DEPS += axi_ad9371_ip.tcl
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INTEL_DEPS += ../intel/common/ad_dcfilter.v
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INTEL_DEPS += ../intel/common/ad_mul.v
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INTEL_DEPS += ../intel/common/up_clock_mon_constr.sdc
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INTEL_DEPS += ../intel/common/up_rst_constr.sdc
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INTEL_DEPS += ../intel/common/up_xfer_cntrl_constr.sdc
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INTEL_DEPS += ../intel/common/up_xfer_status_constr.sdc
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INTEL_DEPS += axi_ad9371_hw.tcl
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include ../scripts/library.mk
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@@ -0,0 +1,3 @@
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version:1
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6d6f64655f636f756e7465727c42617463684d6f6465:1
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eof:
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@@ -0,0 +1,6 @@
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<?xml version="1.0" encoding="UTF-8"?>
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||||
<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
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||||
<!-- -->
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||||
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
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||||
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||||
<labtools version="1" minor="0"/>
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@@ -0,0 +1,351 @@
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// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
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||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
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||||
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||||
`timescale 1ns/100ps
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||||
module axi_ad9371 #(
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parameter ID = 0,
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parameter FPGA_TECHNOLOGY = 0,
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parameter FPGA_FAMILY = 0,
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parameter SPEED_GRADE = 0,
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||||
parameter DEV_PACKAGE = 0,
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||||
parameter DAC_DDS_TYPE = 1,
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parameter DAC_DDS_CORDIC_DW = 20,
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parameter DAC_DDS_CORDIC_PHASE_DW = 18,
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parameter DAC_DATAPATH_DISABLE = 0,
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||||
parameter ADC_DATAPATH_DISABLE = 0) (
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// receive
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||||
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||||
input adc_clk,
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input adc_rx_valid,
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input [ 3:0] adc_rx_sof,
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input [ 63:0] adc_rx_data,
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||||
output adc_rx_ready,
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input adc_os_clk,
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||||
input adc_rx_os_valid,
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||||
input [ 3:0] adc_rx_os_sof,
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input [ 63:0] adc_rx_os_data,
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||||
output adc_rx_os_ready,
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||||
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||||
// transmit
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input dac_clk,
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output dac_tx_valid,
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output [127:0] dac_tx_data,
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||||
input dac_tx_ready,
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||||
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||||
// master/slave
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||||
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||||
input dac_sync_in,
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output dac_sync_out,
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||||
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||||
// dma interface
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||||
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||||
output adc_enable_i0,
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output adc_valid_i0,
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output [ 15:0] adc_data_i0,
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||||
output adc_enable_q0,
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||||
output adc_valid_q0,
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||||
output [ 15:0] adc_data_q0,
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||||
output adc_enable_i1,
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||||
output adc_valid_i1,
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||||
output [ 15:0] adc_data_i1,
|
||||
output adc_enable_q1,
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||||
output adc_valid_q1,
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||||
output [ 15:0] adc_data_q1,
|
||||
input adc_dovf,
|
||||
|
||||
output adc_os_enable_i0,
|
||||
output adc_os_valid_i0,
|
||||
output [ 31:0] adc_os_data_i0,
|
||||
output adc_os_enable_q0,
|
||||
output adc_os_valid_q0,
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||||
output [ 31:0] adc_os_data_q0,
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||||
input adc_os_dovf,
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||||
|
||||
output dac_enable_i0,
|
||||
output dac_valid_i0,
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||||
input [ 31:0] dac_data_i0,
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||||
output dac_enable_q0,
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||||
output dac_valid_q0,
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||||
input [ 31:0] dac_data_q0,
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||||
output dac_enable_i1,
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||||
output dac_valid_i1,
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||||
input [ 31:0] dac_data_i1,
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||||
output dac_enable_q1,
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output dac_valid_q1,
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input [ 31:0] dac_data_q1,
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||||
input dac_dunf,
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||||
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||||
// axi interface
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||||
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input s_axi_aclk,
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input s_axi_aresetn,
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input s_axi_awvalid,
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input [ 15:0] s_axi_awaddr,
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input [ 2:0] s_axi_awprot,
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output s_axi_awready,
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input s_axi_wvalid,
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input [ 31:0] s_axi_wdata,
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input [ 3:0] s_axi_wstrb,
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output s_axi_wready,
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output s_axi_bvalid,
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output [ 1:0] s_axi_bresp,
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input s_axi_bready,
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input s_axi_arvalid,
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input [ 15:0] s_axi_araddr,
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input [ 2:0] s_axi_arprot,
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output s_axi_arready,
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output s_axi_rvalid,
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output [ 31:0] s_axi_rdata,
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output [ 1:0] s_axi_rresp,
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input s_axi_rready);
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// internal registers
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reg up_wack = 'd0;
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reg up_rack = 'd0;
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reg [ 31:0] up_rdata = 'd0;
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// internal signals
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wire up_clk;
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wire up_rstn;
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wire adc_rst;
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wire adc_os_rst;
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wire [ 63:0] adc_data_s;
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wire adc_os_valid_s;
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wire [ 63:0] adc_os_data_s;
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wire dac_rst;
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wire [127:0] dac_data_s;
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wire up_wreq_s;
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wire [ 13:0] up_waddr_s;
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wire [ 31:0] up_wdata_s;
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wire [ 2:0] up_wack_s;
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wire up_rreq_s;
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wire [ 13:0] up_raddr_s;
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wire [ 31:0] up_rdata_s[0:2];
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wire [ 2:0] up_rack_s;
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// signal name changes
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assign up_clk = s_axi_aclk;
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assign up_rstn = s_axi_aresetn;
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// defaults
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assign dac_tx_valid = 1'b1;
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assign adc_rx_ready = 1'b1;
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assign adc_rx_os_ready = 1'b1;
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// processor read interface
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_wack <= 'd0;
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up_rack <= 'd0;
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up_rdata <= 'd0;
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end else begin
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up_wack <= | up_wack_s;
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up_rack <= | up_rack_s;
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up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2];
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end
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end
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// device interface
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axi_ad9371_if i_if (
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.adc_clk (adc_clk),
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.adc_rx_sof (adc_rx_sof),
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.adc_rx_data (adc_rx_data),
|
||||
.adc_os_clk (adc_os_clk),
|
||||
.adc_rx_os_sof (adc_rx_os_sof),
|
||||
.adc_rx_os_data (adc_rx_os_data),
|
||||
.adc_data (adc_data_s),
|
||||
.adc_os_valid (adc_os_valid_s),
|
||||
.adc_os_data (adc_os_data_s),
|
||||
.dac_clk (dac_clk),
|
||||
.dac_tx_data (dac_tx_data),
|
||||
.dac_data (dac_data_s));
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|
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// receive
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||||
|
||||
axi_ad9371_rx #(
|
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.ID (ID),
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||||
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
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||||
.FPGA_FAMILY (FPGA_FAMILY),
|
||||
.SPEED_GRADE (SPEED_GRADE),
|
||||
.DEV_PACKAGE (DEV_PACKAGE),
|
||||
.DATAPATH_DISABLE (ADC_DATAPATH_DISABLE))
|
||||
i_rx (
|
||||
.adc_rst (adc_rst),
|
||||
.adc_clk (adc_clk),
|
||||
.adc_data (adc_data_s),
|
||||
.adc_enable_i0 (adc_enable_i0),
|
||||
.adc_valid_i0 (adc_valid_i0),
|
||||
.adc_data_i0 (adc_data_i0),
|
||||
.adc_enable_q0 (adc_enable_q0),
|
||||
.adc_valid_q0 (adc_valid_q0),
|
||||
.adc_data_q0 (adc_data_q0),
|
||||
.adc_enable_i1 (adc_enable_i1),
|
||||
.adc_valid_i1 (adc_valid_i1),
|
||||
.adc_data_i1 (adc_data_i1),
|
||||
.adc_enable_q1 (adc_enable_q1),
|
||||
.adc_valid_q1 (adc_valid_q1),
|
||||
.adc_data_q1 (adc_data_q1),
|
||||
.adc_dovf (adc_dovf),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq_s),
|
||||
.up_waddr (up_waddr_s),
|
||||
.up_wdata (up_wdata_s),
|
||||
.up_wack (up_wack_s[0]),
|
||||
.up_rreq (up_rreq_s),
|
||||
.up_raddr (up_raddr_s),
|
||||
.up_rdata (up_rdata_s[0]),
|
||||
.up_rack (up_rack_s[0]));
|
||||
|
||||
// receive (o/s)
|
||||
|
||||
axi_ad9371_rx_os #(
|
||||
.ID (ID),
|
||||
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
|
||||
.FPGA_FAMILY (FPGA_FAMILY),
|
||||
.SPEED_GRADE (SPEED_GRADE),
|
||||
.DEV_PACKAGE (DEV_PACKAGE),
|
||||
.DATAPATH_DISABLE (ADC_DATAPATH_DISABLE))
|
||||
i_rx_os (
|
||||
.adc_os_rst (adc_os_rst),
|
||||
.adc_os_clk (adc_os_clk),
|
||||
.adc_os_valid (adc_os_valid_s),
|
||||
.adc_os_data (adc_os_data_s),
|
||||
.adc_os_enable_i0 (adc_os_enable_i0),
|
||||
.adc_os_valid_i0 (adc_os_valid_i0),
|
||||
.adc_os_data_i0 (adc_os_data_i0),
|
||||
.adc_os_enable_q0 (adc_os_enable_q0),
|
||||
.adc_os_valid_q0 (adc_os_valid_q0),
|
||||
.adc_os_data_q0 (adc_os_data_q0),
|
||||
.adc_os_dovf (adc_os_dovf),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq_s),
|
||||
.up_waddr (up_waddr_s),
|
||||
.up_wdata (up_wdata_s),
|
||||
.up_wack (up_wack_s[1]),
|
||||
.up_rreq (up_rreq_s),
|
||||
.up_raddr (up_raddr_s),
|
||||
.up_rdata (up_rdata_s[1]),
|
||||
.up_rack (up_rack_s[1]));
|
||||
|
||||
// transmit
|
||||
|
||||
axi_ad9371_tx #(
|
||||
.ID (ID),
|
||||
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
|
||||
.FPGA_FAMILY (FPGA_FAMILY),
|
||||
.SPEED_GRADE (SPEED_GRADE),
|
||||
.DEV_PACKAGE (DEV_PACKAGE),
|
||||
.DAC_DDS_TYPE (DAC_DDS_TYPE),
|
||||
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
|
||||
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
|
||||
.DATAPATH_DISABLE (DAC_DATAPATH_DISABLE))
|
||||
i_tx (
|
||||
.dac_rst (dac_rst),
|
||||
.dac_clk (dac_clk),
|
||||
.dac_data (dac_data_s),
|
||||
.dac_sync_in (dac_sync_in),
|
||||
.dac_sync_out (dac_sync_out),
|
||||
.dac_enable_i0 (dac_enable_i0),
|
||||
.dac_valid_i0 (dac_valid_i0),
|
||||
.dac_data_i0 (dac_data_i0),
|
||||
.dac_enable_q0 (dac_enable_q0),
|
||||
.dac_valid_q0 (dac_valid_q0),
|
||||
.dac_data_q0 (dac_data_q0),
|
||||
.dac_enable_i1 (dac_enable_i1),
|
||||
.dac_valid_i1 (dac_valid_i1),
|
||||
.dac_data_i1 (dac_data_i1),
|
||||
.dac_enable_q1 (dac_enable_q1),
|
||||
.dac_valid_q1 (dac_valid_q1),
|
||||
.dac_data_q1 (dac_data_q1),
|
||||
.dac_dunf(dac_dunf),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq_s),
|
||||
.up_waddr (up_waddr_s),
|
||||
.up_wdata (up_wdata_s),
|
||||
.up_wack (up_wack_s[2]),
|
||||
.up_rreq (up_rreq_s),
|
||||
.up_raddr (up_raddr_s),
|
||||
.up_rdata (up_rdata_s[2]),
|
||||
.up_rack (up_rack_s[2]));
|
||||
|
||||
// axi interface
|
||||
|
||||
up_axi i_up_axi (
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_axi_awvalid (s_axi_awvalid),
|
||||
.up_axi_awaddr (s_axi_awaddr),
|
||||
.up_axi_awready (s_axi_awready),
|
||||
.up_axi_wvalid (s_axi_wvalid),
|
||||
.up_axi_wdata (s_axi_wdata),
|
||||
.up_axi_wstrb (s_axi_wstrb),
|
||||
.up_axi_wready (s_axi_wready),
|
||||
.up_axi_bvalid (s_axi_bvalid),
|
||||
.up_axi_bresp (s_axi_bresp),
|
||||
.up_axi_bready (s_axi_bready),
|
||||
.up_axi_arvalid (s_axi_arvalid),
|
||||
.up_axi_araddr (s_axi_araddr),
|
||||
.up_axi_arready (s_axi_arready),
|
||||
.up_axi_rvalid (s_axi_rvalid),
|
||||
.up_axi_rresp (s_axi_rresp),
|
||||
.up_axi_rdata (s_axi_rdata),
|
||||
.up_axi_rready (s_axi_rready),
|
||||
.up_wreq (up_wreq_s),
|
||||
.up_waddr (up_waddr_s),
|
||||
.up_wdata (up_wdata_s),
|
||||
.up_wack (up_wack),
|
||||
.up_rreq (up_rreq_s),
|
||||
.up_raddr (up_raddr_s),
|
||||
.up_rdata (up_rdata),
|
||||
.up_rack (up_rack));
|
||||
|
||||
endmodule
|
||||
|
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// ***************************************************************************
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// ***************************************************************************
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|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="10"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="axi_spi"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val=""/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="11"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1343"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="2"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1306"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="3"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="ERROR"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1276"/>
|
||||
<MsgAttr Name="Severity" Val="CRITICAL WARNING"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="4"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-3656"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="5"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-4623"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="6"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-459"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="7"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Synth 8-3331"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="8"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Designutils 20-3303"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="9"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="HDPYFinalizeIO"/>
|
||||
</MsgRule>
|
||||
<Board/>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
<BootPmcSettings Version="1" Minor="0">
|
||||
<Parameters>
|
||||
<Parameter Name="PMC_CDO.ATTRS.LOADADDR" Value="" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_FB_CLK" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_FREQ" Value="300" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_BUS_WIDTH" Value="x1" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_DATA_MODE" Value="Single" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_FREQ" Value="200" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_SLOT_TYPE" Value="SD 2.0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_FREQ" Value="200" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_SLOT_TYPE" Value="SD 2.0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSPI_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSPI_FREQ" Value="300" Type="string"/>
|
||||
<Parameter Name="BOOT.USB_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SMAP_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SMAP_DATA_WIDTH" Value="32 Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSC_FREQ" Value="33.333" Type="string"/>
|
||||
<Parameter Name="BOOT.SECONDARY.PCIE_ENABLE" Value="0" Type="string"/>
|
||||
</Parameters>
|
||||
</BootPmcSettings>
|
||||
</Project>
|
||||
@@ -0,0 +1,202 @@
|
||||
|
||||
|
||||
package require qsys
|
||||
package require quartus::device
|
||||
|
||||
source ../scripts/adi_env.tcl
|
||||
source ../scripts/adi_ip_intel.tcl
|
||||
|
||||
set_module_property NAME axi_ad9371
|
||||
set_module_property DESCRIPTION "AXI AD9371 Interface"
|
||||
set_module_property VERSION 1.0
|
||||
set_module_property GROUP "Analog Devices"
|
||||
set_module_property DISPLAY_NAME axi_ad9371
|
||||
set_module_property VALIDATION_CALLBACK info_param_validate
|
||||
|
||||
# files
|
||||
|
||||
add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
|
||||
set_fileset_property quartus_synth TOP_LEVEL axi_ad9371
|
||||
add_fileset_file ad_rst.v VERILOG PATH $ad_hdl_dir/library/common/ad_rst.v
|
||||
add_fileset_file ad_mul.v VERILOG PATH $ad_hdl_dir/library/intel/common/ad_mul.v
|
||||
add_fileset_file ad_dds_cordic_pipe.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds_cordic_pipe.v
|
||||
add_fileset_file ad_dds_sine_cordic.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds_sine_cordic.v
|
||||
add_fileset_file ad_dds_sine.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds_sine.v
|
||||
add_fileset_file ad_dds_2.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds_2.v
|
||||
add_fileset_file ad_dds_1.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds_1.v
|
||||
add_fileset_file ad_dds.v VERILOG PATH $ad_hdl_dir/library/common/ad_dds.v
|
||||
add_fileset_file ad_datafmt.v VERILOG PATH $ad_hdl_dir/library/common/ad_datafmt.v
|
||||
add_fileset_file ad_dcfilter.v VERILOG PATH $ad_hdl_dir/library/intel/common/ad_dcfilter.v
|
||||
add_fileset_file ad_iqcor.v VERILOG PATH $ad_hdl_dir/library/common/ad_iqcor.v
|
||||
add_fileset_file up_axi.v VERILOG PATH $ad_hdl_dir/library/common/up_axi.v
|
||||
add_fileset_file up_xfer_cntrl.v VERILOG PATH $ad_hdl_dir/library/common/up_xfer_cntrl.v
|
||||
add_fileset_file up_xfer_status.v VERILOG PATH $ad_hdl_dir/library/common/up_xfer_status.v
|
||||
add_fileset_file up_clock_mon.v VERILOG PATH $ad_hdl_dir/library/common/up_clock_mon.v
|
||||
add_fileset_file up_adc_common.v VERILOG PATH $ad_hdl_dir/library/common/up_adc_common.v
|
||||
add_fileset_file up_adc_channel.v VERILOG PATH $ad_hdl_dir/library/common/up_adc_channel.v
|
||||
add_fileset_file up_dac_common.v VERILOG PATH $ad_hdl_dir/library/common/up_dac_common.v
|
||||
add_fileset_file up_dac_channel.v VERILOG PATH $ad_hdl_dir/library/common/up_dac_channel.v
|
||||
add_fileset_file ad_xcvr_rx_if.v VERILOG PATH $ad_hdl_dir/library/common/ad_xcvr_rx_if.v
|
||||
add_fileset_file axi_ad9371_if.v VERILOG PATH axi_ad9371_if.v
|
||||
add_fileset_file axi_ad9371_rx_channel.v VERILOG PATH axi_ad9371_rx_channel.v
|
||||
add_fileset_file axi_ad9371_rx.v VERILOG PATH axi_ad9371_rx.v
|
||||
add_fileset_file axi_ad9371_rx_os.v VERILOG PATH axi_ad9371_rx_os.v
|
||||
add_fileset_file axi_ad9371_tx_channel.v VERILOG PATH axi_ad9371_tx_channel.v
|
||||
add_fileset_file axi_ad9371_tx.v VERILOG PATH axi_ad9371_tx.v
|
||||
add_fileset_file axi_ad9371.v VERILOG PATH axi_ad9371.v TOP_LEVEL_FILE
|
||||
add_fileset_file up_xfer_cntrl_constr.sdc SDC PATH $ad_hdl_dir/library/intel/common/up_xfer_cntrl_constr.sdc
|
||||
add_fileset_file up_xfer_status_constr.sdc SDC PATH $ad_hdl_dir/library/intel/common/up_xfer_status_constr.sdc
|
||||
add_fileset_file up_clock_mon_constr.sdc SDC PATH $ad_hdl_dir/library/intel/common/up_clock_mon_constr.sdc
|
||||
add_fileset_file up_rst_constr.sdc SDC PATH $ad_hdl_dir/library/intel/common/up_rst_constr.sdc
|
||||
|
||||
# parameters
|
||||
|
||||
add_parameter ID INTEGER 0
|
||||
set_parameter_property ID DEFAULT_VALUE 0
|
||||
set_parameter_property ID DISPLAY_NAME ID
|
||||
set_parameter_property ID UNITS None
|
||||
set_parameter_property ID HDL_PARAMETER true
|
||||
|
||||
add_parameter DAC_DATAPATH_DISABLE INTEGER 0
|
||||
set_parameter_property DAC_DATAPATH_DISABLE DEFAULT_VALUE 0
|
||||
set_parameter_property DAC_DATAPATH_DISABLE DISPLAY_NAME DAC_DATAPATH_DISABLE
|
||||
set_parameter_property DAC_DATAPATH_DISABLE UNITS None
|
||||
set_parameter_property DAC_DATAPATH_DISABLE HDL_PARAMETER true
|
||||
|
||||
add_parameter ADC_DATAPATH_DISABLE INTEGER 0
|
||||
set_parameter_property ADC_DATAPATH_DISABLE DEFAULT_VALUE 0
|
||||
set_parameter_property ADC_DATAPATH_DISABLE DISPLAY_NAME ADC_DATAPATH_DISABLE
|
||||
set_parameter_property ADC_DATAPATH_DISABLE UNITS None
|
||||
set_parameter_property ADC_DATAPATH_DISABLE HDL_PARAMETER true
|
||||
|
||||
adi_add_auto_fpga_spec_params
|
||||
|
||||
# axi4 slave
|
||||
|
||||
ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn
|
||||
|
||||
# transceiver interface
|
||||
|
||||
ad_interface clock adc_clk input 1
|
||||
ad_interface signal adc_rx_sof input 4 export
|
||||
add_interface if_adc_rx_data avalon_streaming sink
|
||||
add_interface_port if_adc_rx_data adc_rx_data data input 64
|
||||
add_interface_port if_adc_rx_data adc_rx_valid valid input 1
|
||||
add_interface_port if_adc_rx_data adc_rx_ready ready output 1
|
||||
set_interface_property if_adc_rx_data associatedClock if_adc_clk
|
||||
set_interface_property if_adc_rx_data dataBitsPerSymbol 64
|
||||
|
||||
ad_interface clock adc_os_clk input 1
|
||||
ad_interface signal adc_rx_os_sof input 4 export
|
||||
add_interface if_adc_rx_os_data avalon_streaming sink
|
||||
add_interface_port if_adc_rx_os_data adc_rx_os_data data input 64
|
||||
add_interface_port if_adc_rx_os_data adc_rx_os_valid valid input 1
|
||||
add_interface_port if_adc_rx_os_data adc_rx_os_ready ready output 1
|
||||
set_interface_property if_adc_rx_os_data associatedClock if_adc_os_clk
|
||||
set_interface_property if_adc_rx_os_data dataBitsPerSymbol 64
|
||||
|
||||
ad_interface clock dac_clk input 1
|
||||
add_interface if_dac_tx_data avalon_streaming source
|
||||
add_interface_port if_dac_tx_data dac_tx_data data output 128
|
||||
add_interface_port if_dac_tx_data dac_tx_valid valid output 1
|
||||
add_interface_port if_dac_tx_data dac_tx_ready ready input 1
|
||||
set_interface_property if_dac_tx_data associatedClock if_dac_clk
|
||||
set_interface_property if_dac_tx_data dataBitsPerSymbol 128
|
||||
|
||||
# master/slave
|
||||
|
||||
ad_interface signal dac_sync_in input 1
|
||||
ad_interface signal dac_sync_out output 1
|
||||
|
||||
# adc-channel interface
|
||||
|
||||
add_interface adc_ch_0 conduit end
|
||||
add_interface_port adc_ch_0 adc_enable_i0 enable Output 1
|
||||
add_interface_port adc_ch_0 adc_valid_i0 valid Output 1
|
||||
add_interface_port adc_ch_0 adc_data_i0 data Output 16
|
||||
|
||||
set_interface_property adc_ch_0 associatedClock if_adc_clk
|
||||
set_interface_property adc_ch_0 associatedReset none
|
||||
|
||||
add_interface adc_ch_1 conduit end
|
||||
add_interface_port adc_ch_1 adc_enable_q0 enable Output 1
|
||||
add_interface_port adc_ch_1 adc_valid_q0 valid Output 1
|
||||
add_interface_port adc_ch_1 adc_data_q0 data Output 16
|
||||
|
||||
set_interface_property adc_ch_1 associatedClock if_adc_clk
|
||||
set_interface_property adc_ch_1 associatedReset none
|
||||
|
||||
add_interface adc_ch_2 conduit end
|
||||
add_interface_port adc_ch_2 adc_enable_i1 enable Output 1
|
||||
add_interface_port adc_ch_2 adc_valid_i1 valid Output 1
|
||||
add_interface_port adc_ch_2 adc_data_i1 data Output 16
|
||||
|
||||
set_interface_property adc_ch_2 associatedClock if_adc_clk
|
||||
set_interface_property adc_ch_2 associatedReset none
|
||||
|
||||
add_interface adc_ch_3 conduit end
|
||||
add_interface_port adc_ch_3 adc_enable_q1 enable Output 1
|
||||
add_interface_port adc_ch_3 adc_valid_q1 valid Output 1
|
||||
add_interface_port adc_ch_3 adc_data_q1 data Output 16
|
||||
|
||||
set_interface_property adc_ch_3 associatedClock if_adc_clk
|
||||
set_interface_property adc_ch_3 associatedReset none
|
||||
|
||||
ad_interface signal adc_dovf input 1 ovf
|
||||
|
||||
# adc-os-channel interface
|
||||
|
||||
add_interface adc_os_ch_0 conduit end
|
||||
add_interface_port adc_os_ch_0 adc_os_enable_i0 enable Output 1
|
||||
add_interface_port adc_os_ch_0 adc_os_valid_i0 valid Output 1
|
||||
add_interface_port adc_os_ch_0 adc_os_data_i0 data Output 32
|
||||
|
||||
set_interface_property adc_os_ch_0 associatedClock if_adc_os_clk
|
||||
set_interface_property adc_os_ch_0 associatedReset none
|
||||
|
||||
add_interface adc_os_ch_1 conduit end
|
||||
add_interface_port adc_os_ch_1 adc_os_enable_q0 enable Output 1
|
||||
add_interface_port adc_os_ch_1 adc_os_valid_q0 valid Output 1
|
||||
add_interface_port adc_os_ch_1 adc_os_data_q0 data Output 32
|
||||
|
||||
set_interface_property adc_os_ch_1 associatedClock if_adc_os_clk
|
||||
set_interface_property adc_os_ch_1 associatedReset none
|
||||
|
||||
ad_interface signal adc_os_dovf input 1 ovf
|
||||
|
||||
# dac-channel interface
|
||||
|
||||
add_interface dac_ch_0 conduit end
|
||||
add_interface_port dac_ch_0 dac_enable_i0 enable Output 1
|
||||
add_interface_port dac_ch_0 dac_valid_i0 valid Output 1
|
||||
add_interface_port dac_ch_0 dac_data_i0 data Input 32
|
||||
|
||||
set_interface_property dac_ch_0 associatedClock if_dac_clk
|
||||
set_interface_property dac_ch_0 associatedReset none
|
||||
|
||||
add_interface dac_ch_1 conduit end
|
||||
add_interface_port dac_ch_1 dac_enable_q0 enable Output 1
|
||||
add_interface_port dac_ch_1 dac_valid_q0 valid Output 1
|
||||
add_interface_port dac_ch_1 dac_data_q0 data Input 32
|
||||
|
||||
set_interface_property dac_ch_1 associatedClock if_dac_clk
|
||||
set_interface_property dac_ch_1 associatedReset none
|
||||
|
||||
add_interface dac_ch_2 conduit end
|
||||
add_interface_port dac_ch_2 dac_enable_i1 enable Output 1
|
||||
add_interface_port dac_ch_2 dac_valid_i1 valid Output 1
|
||||
add_interface_port dac_ch_2 dac_data_i1 data Input 32
|
||||
|
||||
set_interface_property dac_ch_2 associatedClock if_dac_clk
|
||||
set_interface_property dac_ch_2 associatedReset none
|
||||
|
||||
add_interface dac_ch_3 conduit end
|
||||
add_interface_port dac_ch_3 dac_enable_q1 enable Output 1
|
||||
add_interface_port dac_ch_3 dac_valid_q1 valid Output 1
|
||||
add_interface_port dac_ch_3 dac_data_q1 data Input 32
|
||||
|
||||
set_interface_property dac_ch_3 associatedClock if_dac_clk
|
||||
set_interface_property dac_ch_3 associatedReset none
|
||||
|
||||
ad_interface signal dac_dunf input 1 unf
|
||||
|
||||
@@ -0,0 +1,129 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module axi_ad9371_if (
|
||||
// receive
|
||||
|
||||
input adc_clk,
|
||||
input [ 3:0] adc_rx_sof,
|
||||
input [ 63:0] adc_rx_data,
|
||||
input adc_os_clk,
|
||||
input [ 3:0] adc_rx_os_sof,
|
||||
input [ 63:0] adc_rx_os_data,
|
||||
|
||||
output [ 63:0] adc_data,
|
||||
output adc_os_valid,
|
||||
output [ 63:0] adc_os_data,
|
||||
|
||||
// transmit
|
||||
|
||||
input dac_clk,
|
||||
output [127:0] dac_tx_data,
|
||||
|
||||
input [127:0] dac_data);
|
||||
|
||||
|
||||
// internal signals
|
||||
|
||||
wire [ 63:0] adc_rx_data_s;
|
||||
wire [ 63:0] adc_rx_os_data_s;
|
||||
|
||||
// delineating
|
||||
|
||||
assign adc_data[((8* 7)+7):(8* 7)] = adc_rx_data_s[((8* 6)+7):(8* 6)];
|
||||
assign adc_data[((8* 6)+7):(8* 6)] = adc_rx_data_s[((8* 7)+7):(8* 7)];
|
||||
assign adc_data[((8* 5)+7):(8* 5)] = adc_rx_data_s[((8* 4)+7):(8* 4)];
|
||||
assign adc_data[((8* 4)+7):(8* 4)] = adc_rx_data_s[((8* 5)+7):(8* 5)];
|
||||
assign adc_data[((8* 3)+7):(8* 3)] = adc_rx_data_s[((8* 2)+7):(8* 2)];
|
||||
assign adc_data[((8* 2)+7):(8* 2)] = adc_rx_data_s[((8* 3)+7):(8* 3)];
|
||||
assign adc_data[((8* 1)+7):(8* 1)] = adc_rx_data_s[((8* 0)+7):(8* 0)];
|
||||
assign adc_data[((8* 0)+7):(8* 0)] = adc_rx_data_s[((8* 1)+7):(8* 1)];
|
||||
|
||||
assign adc_os_valid = 'd1;
|
||||
assign adc_os_data[((8* 7)+7):(8* 7)] = adc_rx_os_data_s[((8* 6)+7):(8* 6)];
|
||||
assign adc_os_data[((8* 6)+7):(8* 6)] = adc_rx_os_data_s[((8* 7)+7):(8* 7)];
|
||||
assign adc_os_data[((8* 5)+7):(8* 5)] = adc_rx_os_data_s[((8* 4)+7):(8* 4)];
|
||||
assign adc_os_data[((8* 4)+7):(8* 4)] = adc_rx_os_data_s[((8* 5)+7):(8* 5)];
|
||||
assign adc_os_data[((8* 3)+7):(8* 3)] = adc_rx_os_data_s[((8* 2)+7):(8* 2)];
|
||||
assign adc_os_data[((8* 2)+7):(8* 2)] = adc_rx_os_data_s[((8* 3)+7):(8* 3)];
|
||||
assign adc_os_data[((8* 1)+7):(8* 1)] = adc_rx_os_data_s[((8* 0)+7):(8* 0)];
|
||||
assign adc_os_data[((8* 0)+7):(8* 0)] = adc_rx_os_data_s[((8* 1)+7):(8* 1)];
|
||||
|
||||
assign dac_tx_data[((8*15)+7):(8*15)] = dac_data[((8*14)+7):(8*14)];
|
||||
assign dac_tx_data[((8*14)+7):(8*14)] = dac_data[((8*15)+7):(8*15)];
|
||||
assign dac_tx_data[((8*13)+7):(8*13)] = dac_data[((8*12)+7):(8*12)];
|
||||
assign dac_tx_data[((8*12)+7):(8*12)] = dac_data[((8*13)+7):(8*13)];
|
||||
assign dac_tx_data[((8*11)+7):(8*11)] = dac_data[((8*10)+7):(8*10)];
|
||||
assign dac_tx_data[((8*10)+7):(8*10)] = dac_data[((8*11)+7):(8*11)];
|
||||
assign dac_tx_data[((8* 9)+7):(8* 9)] = dac_data[((8* 8)+7):(8* 8)];
|
||||
assign dac_tx_data[((8* 8)+7):(8* 8)] = dac_data[((8* 9)+7):(8* 9)];
|
||||
assign dac_tx_data[((8* 7)+7):(8* 7)] = dac_data[((8* 6)+7):(8* 6)];
|
||||
assign dac_tx_data[((8* 6)+7):(8* 6)] = dac_data[((8* 7)+7):(8* 7)];
|
||||
assign dac_tx_data[((8* 5)+7):(8* 5)] = dac_data[((8* 4)+7):(8* 4)];
|
||||
assign dac_tx_data[((8* 4)+7):(8* 4)] = dac_data[((8* 5)+7):(8* 5)];
|
||||
assign dac_tx_data[((8* 3)+7):(8* 3)] = dac_data[((8* 2)+7):(8* 2)];
|
||||
assign dac_tx_data[((8* 2)+7):(8* 2)] = dac_data[((8* 3)+7):(8* 3)];
|
||||
assign dac_tx_data[((8* 1)+7):(8* 1)] = dac_data[((8* 0)+7):(8* 0)];
|
||||
assign dac_tx_data[((8* 0)+7):(8* 0)] = dac_data[((8* 1)+7):(8* 1)];
|
||||
|
||||
// instantiations
|
||||
|
||||
genvar n;
|
||||
|
||||
generate
|
||||
for (n = 0; n < 2; n = n + 1) begin: g_xcvr_if
|
||||
|
||||
ad_xcvr_rx_if i_xcvr_rx_if (
|
||||
.rx_clk (adc_clk),
|
||||
.rx_ip_sof (adc_rx_sof),
|
||||
.rx_ip_data (adc_rx_data[((n*32)+31):(n*32)]),
|
||||
.rx_sof (),
|
||||
.rx_data (adc_rx_data_s[((n*32)+31):(n*32)]));
|
||||
|
||||
ad_xcvr_rx_if i_xcvr_rx_os_if (
|
||||
.rx_clk (adc_os_clk),
|
||||
.rx_ip_sof (adc_rx_os_sof),
|
||||
.rx_ip_data (adc_rx_os_data[((n*32)+31):(n*32)]),
|
||||
.rx_sof (),
|
||||
.rx_data (adc_rx_os_data_s[((n*32)+31):(n*32)]));
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
@@ -0,0 +1,55 @@
|
||||
# ip
|
||||
|
||||
source ../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
|
||||
adi_ip_create axi_ad9371
|
||||
adi_ip_files axi_ad9371 [list \
|
||||
"$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \
|
||||
"$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \
|
||||
"$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \
|
||||
"$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \
|
||||
"$ad_hdl_dir/library/common/ad_rst.v" \
|
||||
"$ad_hdl_dir/library/xilinx/common/ad_dcfilter.v" \
|
||||
"$ad_hdl_dir/library/xilinx/common/ad_mul.v" \
|
||||
"$ad_hdl_dir/library/common/ad_dds_cordic_pipe.v" \
|
||||
"$ad_hdl_dir/library/common/ad_dds_sine_cordic.v" \
|
||||
"$ad_hdl_dir/library/common/ad_dds_sine.v" \
|
||||
"$ad_hdl_dir/library/common/ad_dds_2.v" \
|
||||
"$ad_hdl_dir/library/common/ad_dds_1.v" \
|
||||
"$ad_hdl_dir/library/common/ad_dds.v" \
|
||||
"$ad_hdl_dir/library/common/ad_datafmt.v" \
|
||||
"$ad_hdl_dir/library/common/ad_iqcor.v" \
|
||||
"$ad_hdl_dir/library/common/up_axi.v" \
|
||||
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
|
||||
"$ad_hdl_dir/library/common/up_xfer_status.v" \
|
||||
"$ad_hdl_dir/library/common/up_clock_mon.v" \
|
||||
"$ad_hdl_dir/library/common/up_adc_common.v" \
|
||||
"$ad_hdl_dir/library/common/up_adc_channel.v" \
|
||||
"$ad_hdl_dir/library/common/up_dac_common.v" \
|
||||
"$ad_hdl_dir/library/common/up_dac_channel.v" \
|
||||
"$ad_hdl_dir/library/common/ad_xcvr_rx_if.v" \
|
||||
"axi_ad9371_if.v" \
|
||||
"axi_ad9371_rx_channel.v" \
|
||||
"axi_ad9371_rx.v" \
|
||||
"axi_ad9371_rx_os.v" \
|
||||
"axi_ad9371_tx_channel.v" \
|
||||
"axi_ad9371_tx.v" \
|
||||
"axi_ad9371.v" ]
|
||||
|
||||
adi_ip_properties axi_ad9371
|
||||
|
||||
adi_init_bd_tcl
|
||||
adi_ip_bd axi_ad9371 "bd/bd.tcl"
|
||||
|
||||
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
|
||||
set_property driver_value 0 [ipx::get_ports *dac_sync_in* -of_objects [ipx::current_core]]
|
||||
set_property driver_value 0 [ipx::get_ports *dac_tx_ready* -of_objects [ipx::current_core]]
|
||||
set_property driver_value 0 [ipx::get_ports *adc_rx_valid* -of_objects [ipx::current_core]]
|
||||
set_property driver_value 0 [ipx::get_ports *adc_rx_os_valid* -of_objects [ipx::current_core]]
|
||||
|
||||
adi_add_auto_fpga_spec_params
|
||||
ipx::create_xgui_files [ipx::current_core]
|
||||
|
||||
ipx::save_core [ipx::current_core]
|
||||
|
||||
@@ -0,0 +1,318 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module axi_ad9371_rx #(
|
||||
|
||||
parameter ID = 0,
|
||||
parameter FPGA_TECHNOLOGY = 0,
|
||||
parameter FPGA_FAMILY = 0,
|
||||
parameter SPEED_GRADE = 0,
|
||||
parameter DEV_PACKAGE = 0,
|
||||
parameter DATAPATH_DISABLE = 0) (
|
||||
|
||||
// adc interface
|
||||
|
||||
output adc_rst,
|
||||
input adc_clk,
|
||||
input [ 63:0] adc_data,
|
||||
|
||||
// dma interface
|
||||
|
||||
output adc_enable_i0,
|
||||
output adc_valid_i0,
|
||||
output [ 15:0] adc_data_i0,
|
||||
output adc_enable_q0,
|
||||
output adc_valid_q0,
|
||||
output [ 15:0] adc_data_q0,
|
||||
output adc_enable_i1,
|
||||
output adc_valid_i1,
|
||||
output [ 15:0] adc_data_i1,
|
||||
output adc_enable_q1,
|
||||
output adc_valid_q1,
|
||||
output [ 15:0] adc_data_q1,
|
||||
input adc_dovf,
|
||||
|
||||
// processor interface
|
||||
|
||||
input up_rstn,
|
||||
input up_clk,
|
||||
input up_wreq,
|
||||
input [ 13:0] up_waddr,
|
||||
input [ 31:0] up_wdata,
|
||||
output reg up_wack,
|
||||
input up_rreq,
|
||||
input [ 13:0] up_raddr,
|
||||
output reg [ 31:0] up_rdata,
|
||||
output reg up_rack);
|
||||
|
||||
|
||||
// internal registers
|
||||
|
||||
reg up_status_pn_err = 'd0;
|
||||
reg up_status_pn_oos = 'd0;
|
||||
reg up_status_or = 'd0;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire [ 15:0] adc_data_iq_i0_s;
|
||||
wire [ 15:0] adc_data_iq_q0_s;
|
||||
wire [ 15:0] adc_data_iq_i1_s;
|
||||
wire [ 15:0] adc_data_iq_q1_s;
|
||||
wire [ 3:0] up_adc_pn_err_s;
|
||||
wire [ 3:0] up_adc_pn_oos_s;
|
||||
wire [ 3:0] up_adc_or_s;
|
||||
wire [ 4:0] up_wack_s;
|
||||
wire [ 4:0] up_rack_s;
|
||||
wire [ 31:0] up_rdata_s[0:4];
|
||||
|
||||
// processor read interface
|
||||
|
||||
always @(negedge up_rstn or posedge up_clk) begin
|
||||
if (up_rstn == 0) begin
|
||||
up_status_pn_err <= 'd0;
|
||||
up_status_pn_oos <= 'd0;
|
||||
up_status_or <= 'd0;
|
||||
up_wack <= 'd0;
|
||||
up_rack <= 'd0;
|
||||
up_rdata <= 'd0;
|
||||
end else begin
|
||||
up_status_pn_err <= | up_adc_pn_err_s;
|
||||
up_status_pn_oos <= | up_adc_pn_oos_s;
|
||||
up_status_or <= | up_adc_or_s;
|
||||
up_wack <= | up_wack_s;
|
||||
up_rack <= | up_rack_s;
|
||||
up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] | up_rdata_s[3] | up_rdata_s[4];
|
||||
end
|
||||
end
|
||||
|
||||
// channel width is 32 bits
|
||||
|
||||
assign adc_valid_i0 = 1'b1;
|
||||
assign adc_valid_q0 = 1'b1;
|
||||
assign adc_valid_i1 = 1'b1;
|
||||
assign adc_valid_q1 = 1'b1;
|
||||
|
||||
// channel 0 (i)
|
||||
|
||||
axi_ad9371_rx_channel #(
|
||||
.Q_OR_I_N (0),
|
||||
.COMMON_ID ('h01),
|
||||
.CHANNEL_ID (0),
|
||||
.DATAPATH_DISABLE (DATAPATH_DISABLE),
|
||||
.DATA_WIDTH (16))
|
||||
i_rx_channel_0 (
|
||||
.adc_clk (adc_clk),
|
||||
.adc_rst (adc_rst),
|
||||
.adc_valid_in (1'b1),
|
||||
.adc_data_in (adc_data[15:0]),
|
||||
.adc_valid_out (),
|
||||
.adc_data_out (adc_data_i0),
|
||||
.adc_data_iq_in (adc_data_iq_q0_s),
|
||||
.adc_data_iq_out (adc_data_iq_i0_s),
|
||||
.adc_enable (adc_enable_i0),
|
||||
.up_adc_pn_err (up_adc_pn_err_s[0]),
|
||||
.up_adc_pn_oos (up_adc_pn_oos_s[0]),
|
||||
.up_adc_or (up_adc_or_s[0]),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq),
|
||||
.up_waddr (up_waddr),
|
||||
.up_wdata (up_wdata),
|
||||
.up_wack (up_wack_s[0]),
|
||||
.up_rreq (up_rreq),
|
||||
.up_raddr (up_raddr),
|
||||
.up_rdata (up_rdata_s[0]),
|
||||
.up_rack (up_rack_s[0]));
|
||||
|
||||
// channel 1 (q)
|
||||
|
||||
axi_ad9371_rx_channel #(
|
||||
.Q_OR_I_N (1),
|
||||
.COMMON_ID ('h01),
|
||||
.CHANNEL_ID (1),
|
||||
.DATAPATH_DISABLE (DATAPATH_DISABLE),
|
||||
.DATA_WIDTH (16))
|
||||
i_rx_channel_1 (
|
||||
.adc_clk (adc_clk),
|
||||
.adc_rst (adc_rst),
|
||||
.adc_valid_in (1'b1),
|
||||
.adc_data_in (adc_data[31:16]),
|
||||
.adc_valid_out (),
|
||||
.adc_data_out (adc_data_q0),
|
||||
.adc_data_iq_in (adc_data_iq_i0_s),
|
||||
.adc_data_iq_out (adc_data_iq_q0_s),
|
||||
.adc_enable (adc_enable_q0),
|
||||
.up_adc_pn_err (up_adc_pn_err_s[1]),
|
||||
.up_adc_pn_oos (up_adc_pn_oos_s[1]),
|
||||
.up_adc_or (up_adc_or_s[1]),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq),
|
||||
.up_waddr (up_waddr),
|
||||
.up_wdata (up_wdata),
|
||||
.up_wack (up_wack_s[1]),
|
||||
.up_rreq (up_rreq),
|
||||
.up_raddr (up_raddr),
|
||||
.up_rdata (up_rdata_s[1]),
|
||||
.up_rack (up_rack_s[1]));
|
||||
|
||||
// channel 2 (i)
|
||||
|
||||
axi_ad9371_rx_channel #(
|
||||
.Q_OR_I_N (0),
|
||||
.COMMON_ID ('h01),
|
||||
.CHANNEL_ID (2),
|
||||
.DATAPATH_DISABLE (DATAPATH_DISABLE),
|
||||
.DATA_WIDTH (16))
|
||||
i_rx_channel_2 (
|
||||
.adc_clk (adc_clk),
|
||||
.adc_rst (adc_rst),
|
||||
.adc_valid_in (1'b1),
|
||||
.adc_data_in (adc_data[47:32]),
|
||||
.adc_valid_out (),
|
||||
.adc_data_out (adc_data_i1),
|
||||
.adc_data_iq_in (adc_data_iq_q1_s),
|
||||
.adc_data_iq_out (adc_data_iq_i1_s),
|
||||
.adc_enable (adc_enable_i1),
|
||||
.up_adc_pn_err (up_adc_pn_err_s[2]),
|
||||
.up_adc_pn_oos (up_adc_pn_oos_s[2]),
|
||||
.up_adc_or (up_adc_or_s[2]),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq),
|
||||
.up_waddr (up_waddr),
|
||||
.up_wdata (up_wdata),
|
||||
.up_wack (up_wack_s[2]),
|
||||
.up_rreq (up_rreq),
|
||||
.up_raddr (up_raddr),
|
||||
.up_rdata (up_rdata_s[2]),
|
||||
.up_rack (up_rack_s[2]));
|
||||
|
||||
// channel 3 (q)
|
||||
|
||||
axi_ad9371_rx_channel #(
|
||||
.Q_OR_I_N (1),
|
||||
.COMMON_ID ('h01),
|
||||
.CHANNEL_ID (3),
|
||||
.DATAPATH_DISABLE (DATAPATH_DISABLE),
|
||||
.DATA_WIDTH (16))
|
||||
i_rx_channel_3 (
|
||||
.adc_clk (adc_clk),
|
||||
.adc_rst (adc_rst),
|
||||
.adc_valid_in (1'b1),
|
||||
.adc_data_in (adc_data[63:48]),
|
||||
.adc_valid_out (),
|
||||
.adc_data_out (adc_data_q1),
|
||||
.adc_data_iq_in (adc_data_iq_i1_s),
|
||||
.adc_data_iq_out (adc_data_iq_q1_s),
|
||||
.adc_enable (adc_enable_q1),
|
||||
.up_adc_pn_err (up_adc_pn_err_s[3]),
|
||||
.up_adc_pn_oos (up_adc_pn_oos_s[3]),
|
||||
.up_adc_or (up_adc_or_s[3]),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq),
|
||||
.up_waddr (up_waddr),
|
||||
.up_wdata (up_wdata),
|
||||
.up_wack (up_wack_s[3]),
|
||||
.up_rreq (up_rreq),
|
||||
.up_raddr (up_raddr),
|
||||
.up_rdata (up_rdata_s[3]),
|
||||
.up_rack (up_rack_s[3]));
|
||||
|
||||
// common processor control
|
||||
|
||||
up_adc_common #(
|
||||
.COMMON_ID ('h00),
|
||||
.ID (ID),
|
||||
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
|
||||
.FPGA_FAMILY (FPGA_FAMILY),
|
||||
.SPEED_GRADE (SPEED_GRADE),
|
||||
.DEV_PACKAGE (DEV_PACKAGE),
|
||||
.CONFIG (0),
|
||||
.DRP_DISABLE (0),
|
||||
.USERPORTS_DISABLE (0),
|
||||
.GPIO_DISABLE (0),
|
||||
.START_CODE_DISABLE (0))
|
||||
i_up_adc_common (
|
||||
.mmcm_rst (),
|
||||
.adc_clk (adc_clk),
|
||||
.adc_rst (adc_rst),
|
||||
.adc_r1_mode (),
|
||||
.adc_ddr_edgesel (),
|
||||
.adc_pin_mode (),
|
||||
.adc_status (1'b1),
|
||||
.adc_sync_status (1'd0),
|
||||
.adc_status_ovf (adc_dovf),
|
||||
.adc_clk_ratio (32'd1),
|
||||
.adc_start_code (),
|
||||
.adc_sref_sync (),
|
||||
.adc_sync (),
|
||||
.up_pps_rcounter (31'b0),
|
||||
.up_pps_status (1'b1),
|
||||
.up_pps_irq_mask (),
|
||||
.up_adc_ce (),
|
||||
.up_status_pn_err (up_status_pn_err),
|
||||
.up_status_pn_oos (up_status_pn_oos),
|
||||
.up_status_or (up_status_or),
|
||||
.up_drp_sel (),
|
||||
.up_drp_wr (),
|
||||
.up_drp_addr (),
|
||||
.up_drp_wdata (),
|
||||
.up_drp_rdata (32'd0),
|
||||
.up_drp_ready (1'd0),
|
||||
.up_drp_locked (1'd1),
|
||||
.up_usr_chanmax_out (),
|
||||
.up_usr_chanmax_in (8'd3),
|
||||
.up_adc_gpio_in (32'd0),
|
||||
.up_adc_gpio_out (),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq),
|
||||
.up_waddr (up_waddr),
|
||||
.up_wdata (up_wdata),
|
||||
.up_wack (up_wack_s[4]),
|
||||
.up_rreq (up_rreq),
|
||||
.up_raddr (up_raddr),
|
||||
.up_rdata (up_rdata_s[4]),
|
||||
.up_rack (up_rack_s[4]));
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
@@ -0,0 +1,222 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module axi_ad9371_rx_channel #(
|
||||
|
||||
parameter Q_OR_I_N = 0,
|
||||
parameter COMMON_ID = 0,
|
||||
parameter CHANNEL_ID = 0,
|
||||
parameter DATAPATH_DISABLE = 0,
|
||||
parameter DATA_WIDTH = 32) (
|
||||
|
||||
// adc interface
|
||||
|
||||
input adc_clk,
|
||||
input adc_rst,
|
||||
input adc_valid_in,
|
||||
input [(DATA_WIDTH-1):0] adc_data_in,
|
||||
output adc_valid_out,
|
||||
output [(DATA_WIDTH-1):0] adc_data_out,
|
||||
input [(DATA_WIDTH-1):0] adc_data_iq_in,
|
||||
output [(DATA_WIDTH-1):0] adc_data_iq_out,
|
||||
output adc_enable,
|
||||
|
||||
// channel interface
|
||||
|
||||
output up_adc_pn_err,
|
||||
output up_adc_pn_oos,
|
||||
output up_adc_or,
|
||||
|
||||
// processor interface
|
||||
|
||||
input up_rstn,
|
||||
input up_clk,
|
||||
input up_wreq,
|
||||
input [13:0] up_waddr,
|
||||
input [31:0] up_wdata,
|
||||
output up_wack,
|
||||
input up_rreq,
|
||||
input [13:0] up_raddr,
|
||||
output [31:0] up_rdata,
|
||||
output up_rack);
|
||||
|
||||
|
||||
localparam NUM_OF_SAMPLES = DATA_WIDTH/16;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire [(NUM_OF_SAMPLES-1):0] adc_dfmt_valid_s;
|
||||
wire [(DATA_WIDTH-1):0] adc_dfmt_data_s;
|
||||
wire [(NUM_OF_SAMPLES-1):0] adc_dcfilter_valid_s;
|
||||
wire [(DATA_WIDTH-1):0] adc_dcfilter_data_s;
|
||||
wire [(NUM_OF_SAMPLES-1):0] adc_valid_out_s;
|
||||
wire adc_pn_err_s;
|
||||
wire adc_pn_oos_s;
|
||||
wire adc_dfmt_se_s;
|
||||
wire adc_dfmt_type_s;
|
||||
wire adc_dfmt_enable_s;
|
||||
wire adc_dcfilt_enb_s;
|
||||
wire [15:0] adc_dcfilt_offset_s;
|
||||
wire [15:0] adc_dcfilt_coeff_s;
|
||||
wire adc_iqcor_enb_s;
|
||||
wire [15:0] adc_iqcor_coeff_1_s;
|
||||
wire [15:0] adc_iqcor_coeff_2_s;
|
||||
|
||||
// variables
|
||||
|
||||
genvar n;
|
||||
|
||||
// iq correction inputs
|
||||
|
||||
assign adc_pn_oos_s = 1'b1;
|
||||
assign adc_pn_err_s = 1'b0;
|
||||
|
||||
generate
|
||||
for (n = 0; n < NUM_OF_SAMPLES; n = n + 1) begin: g_datafmt
|
||||
if (DATAPATH_DISABLE == 1) begin
|
||||
assign adc_dfmt_valid_s[n] = adc_valid_in;
|
||||
assign adc_dfmt_data_s[((16*n)+15):(16*n)] = adc_data_in[((16*n)+15):(16*n)];
|
||||
end else begin
|
||||
ad_datafmt #(.DATA_WIDTH (16)) i_ad_datafmt (
|
||||
.clk (adc_clk),
|
||||
.valid (adc_valid_in),
|
||||
.data (adc_data_in[((16*n)+15):(16*n)]),
|
||||
.valid_out (adc_dfmt_valid_s[n]),
|
||||
.data_out (adc_dfmt_data_s[((16*n)+15):(16*n)]),
|
||||
.dfmt_enable (adc_dfmt_enable_s),
|
||||
.dfmt_type (adc_dfmt_type_s),
|
||||
.dfmt_se (adc_dfmt_se_s));
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate
|
||||
for (n = 0; n < NUM_OF_SAMPLES; n = n + 1) begin: g_dcfilter
|
||||
if (DATAPATH_DISABLE == 1) begin
|
||||
assign adc_dcfilter_valid_s[n] = adc_dfmt_valid_s[n];
|
||||
assign adc_dcfilter_data_s[((16*n)+15):(16*n)] = adc_dfmt_data_s[((16*n)+15):(16*n)];
|
||||
end else begin
|
||||
ad_dcfilter i_ad_dcfilter (
|
||||
.clk (adc_clk),
|
||||
.valid (adc_dfmt_valid_s[n]),
|
||||
.data (adc_dfmt_data_s[((16*n)+15):(16*n)]),
|
||||
.valid_out (adc_dcfilter_valid_s[n]),
|
||||
.data_out (adc_dcfilter_data_s[((16*n)+15):(16*n)]),
|
||||
.dcfilt_enb (adc_dcfilt_enb_s),
|
||||
.dcfilt_coeff (adc_dcfilt_coeff_s),
|
||||
.dcfilt_offset (adc_dcfilt_offset_s));
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
assign adc_valid_out = adc_valid_out_s[0];
|
||||
assign adc_data_iq_out = adc_dcfilter_data_s;
|
||||
|
||||
generate
|
||||
for (n = 0; n < NUM_OF_SAMPLES; n = n + 1) begin: g_iqcor
|
||||
if (DATAPATH_DISABLE == 1) begin
|
||||
assign adc_valid_out_s[n] = adc_dcfilter_valid_s[n];
|
||||
assign adc_data_out[((16*n)+15):(16*n)] = adc_dcfilter_data_s[((16*n)+15):(16*n)];
|
||||
end else begin
|
||||
ad_iqcor #(.Q_OR_I_N (Q_OR_I_N)) i_ad_iqcor (
|
||||
.clk (adc_clk),
|
||||
.valid (adc_dcfilter_valid_s[n]),
|
||||
.data_in (adc_dcfilter_data_s[((16*n)+15):(16*n)]),
|
||||
.data_iq (adc_data_iq_in[((16*n)+15):(16*n)]),
|
||||
.valid_out (adc_valid_out_s[n]),
|
||||
.data_out (adc_data_out[((16*n)+15):(16*n)]),
|
||||
.iqcor_enable (adc_iqcor_enb_s),
|
||||
.iqcor_coeff_1 (adc_iqcor_coeff_1_s),
|
||||
.iqcor_coeff_2 (adc_iqcor_coeff_2_s));
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
up_adc_channel #(
|
||||
.COMMON_ID (COMMON_ID),
|
||||
.CHANNEL_ID (CHANNEL_ID))
|
||||
i_up_adc_channel (
|
||||
.adc_clk (adc_clk),
|
||||
.adc_rst (adc_rst),
|
||||
.adc_enable (adc_enable),
|
||||
.adc_iqcor_enb (adc_iqcor_enb_s),
|
||||
.adc_dcfilt_enb (adc_dcfilt_enb_s),
|
||||
.adc_dfmt_se (adc_dfmt_se_s),
|
||||
.adc_dfmt_type (adc_dfmt_type_s),
|
||||
.adc_dfmt_enable (adc_dfmt_enable_s),
|
||||
.adc_dcfilt_offset (adc_dcfilt_offset_s),
|
||||
.adc_dcfilt_coeff (adc_dcfilt_coeff_s),
|
||||
.adc_iqcor_coeff_1 (adc_iqcor_coeff_1_s),
|
||||
.adc_iqcor_coeff_2 (adc_iqcor_coeff_2_s),
|
||||
.adc_pnseq_sel (),
|
||||
.adc_data_sel (),
|
||||
.adc_pn_err (adc_pn_err_s),
|
||||
.adc_pn_oos (adc_pn_oos_s),
|
||||
.adc_or (1'd0),
|
||||
.up_adc_pn_err (up_adc_pn_err),
|
||||
.up_adc_pn_oos (up_adc_pn_oos),
|
||||
.up_adc_or (up_adc_or),
|
||||
.up_usr_datatype_be (),
|
||||
.up_usr_datatype_signed (),
|
||||
.up_usr_datatype_shift (),
|
||||
.up_usr_datatype_total_bits (),
|
||||
.up_usr_datatype_bits (),
|
||||
.up_usr_decimation_m (),
|
||||
.up_usr_decimation_n (),
|
||||
.adc_usr_datatype_be (1'b0),
|
||||
.adc_usr_datatype_signed (1'b1),
|
||||
.adc_usr_datatype_shift (8'd0),
|
||||
.adc_usr_datatype_total_bits (8'd16),
|
||||
.adc_usr_datatype_bits (8'd16),
|
||||
.adc_usr_decimation_m (16'd1),
|
||||
.adc_usr_decimation_n (16'd1),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq),
|
||||
.up_waddr (up_waddr),
|
||||
.up_wdata (up_wdata),
|
||||
.up_wack (up_wack),
|
||||
.up_rreq (up_rreq),
|
||||
.up_raddr (up_raddr),
|
||||
.up_rdata (up_rdata),
|
||||
.up_rack (up_rack));
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
@@ -0,0 +1,235 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module axi_ad9371_rx_os #(
|
||||
|
||||
parameter ID = 0,
|
||||
parameter FPGA_TECHNOLOGY = 0,
|
||||
parameter FPGA_FAMILY = 0,
|
||||
parameter SPEED_GRADE = 0,
|
||||
parameter DEV_PACKAGE = 0,
|
||||
parameter DATAPATH_DISABLE = 0) (
|
||||
|
||||
// adc interface
|
||||
|
||||
output adc_os_rst,
|
||||
input adc_os_clk,
|
||||
input adc_os_valid,
|
||||
input [ 63:0] adc_os_data,
|
||||
|
||||
// dma interface
|
||||
|
||||
output adc_os_enable_i0,
|
||||
output adc_os_valid_i0,
|
||||
output [ 31:0] adc_os_data_i0,
|
||||
output adc_os_enable_q0,
|
||||
output adc_os_valid_q0,
|
||||
output [ 31:0] adc_os_data_q0,
|
||||
input adc_os_dovf,
|
||||
|
||||
// processor interface
|
||||
|
||||
input up_rstn,
|
||||
input up_clk,
|
||||
input up_wreq,
|
||||
input [ 13:0] up_waddr,
|
||||
input [ 31:0] up_wdata,
|
||||
output reg up_wack,
|
||||
input up_rreq,
|
||||
input [ 13:0] up_raddr,
|
||||
output reg [ 31:0] up_rdata,
|
||||
output reg up_rack);
|
||||
|
||||
|
||||
// internal registers
|
||||
|
||||
reg up_status_pn_err = 'd0;
|
||||
reg up_status_pn_oos = 'd0;
|
||||
reg up_status_or = 'd0;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire [ 31:0] adc_os_data_iq_i0_s;
|
||||
wire [ 31:0] adc_os_data_iq_q0_s;
|
||||
wire [ 1:0] up_adc_pn_err_s;
|
||||
wire [ 1:0] up_adc_pn_oos_s;
|
||||
wire [ 1:0] up_adc_or_s;
|
||||
wire [ 2:0] up_wack_s;
|
||||
wire [ 2:0] up_rack_s;
|
||||
wire [ 31:0] up_rdata_s[0:2];
|
||||
|
||||
// processor read interface
|
||||
|
||||
always @(negedge up_rstn or posedge up_clk) begin
|
||||
if (up_rstn == 0) begin
|
||||
up_status_pn_err <= 'd0;
|
||||
up_status_pn_oos <= 'd0;
|
||||
up_status_or <= 'd0;
|
||||
up_wack <= 'd0;
|
||||
up_rack <= 'd0;
|
||||
up_rdata <= 'd0;
|
||||
end else begin
|
||||
up_status_pn_err <= | up_adc_pn_err_s;
|
||||
up_status_pn_oos <= | up_adc_pn_oos_s;
|
||||
up_status_or <= | up_adc_or_s;
|
||||
up_wack <= | up_wack_s;
|
||||
up_rack <= | up_rack_s;
|
||||
up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2];
|
||||
end
|
||||
end
|
||||
|
||||
// channel o/s (i)
|
||||
|
||||
axi_ad9371_rx_channel #(
|
||||
.Q_OR_I_N (0),
|
||||
.COMMON_ID ('h21),
|
||||
.CHANNEL_ID (0),
|
||||
.DATAPATH_DISABLE (DATAPATH_DISABLE),
|
||||
.DATA_WIDTH (32))
|
||||
i_rx_os_channel_0 (
|
||||
.adc_clk (adc_os_clk),
|
||||
.adc_rst (adc_os_rst),
|
||||
.adc_valid_in (adc_os_valid),
|
||||
.adc_data_in (adc_os_data[31:0]),
|
||||
.adc_valid_out (adc_os_valid_i0),
|
||||
.adc_data_out (adc_os_data_i0),
|
||||
.adc_data_iq_in (adc_os_data_iq_q0_s),
|
||||
.adc_data_iq_out (adc_os_data_iq_i0_s),
|
||||
.adc_enable (adc_os_enable_i0),
|
||||
.up_adc_pn_err (up_adc_pn_err_s[0]),
|
||||
.up_adc_pn_oos (up_adc_pn_oos_s[0]),
|
||||
.up_adc_or (up_adc_or_s[0]),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq),
|
||||
.up_waddr (up_waddr),
|
||||
.up_wdata (up_wdata),
|
||||
.up_wack (up_wack_s[0]),
|
||||
.up_rreq (up_rreq),
|
||||
.up_raddr (up_raddr),
|
||||
.up_rdata (up_rdata_s[0]),
|
||||
.up_rack (up_rack_s[0]));
|
||||
|
||||
// channel o/s (q)
|
||||
|
||||
axi_ad9371_rx_channel #(
|
||||
.Q_OR_I_N (1),
|
||||
.COMMON_ID ('h21),
|
||||
.CHANNEL_ID (1),
|
||||
.DATAPATH_DISABLE (DATAPATH_DISABLE),
|
||||
.DATA_WIDTH (32))
|
||||
i_rx_os_channel_1 (
|
||||
.adc_clk (adc_os_clk),
|
||||
.adc_rst (adc_os_rst),
|
||||
.adc_valid_in (adc_os_valid),
|
||||
.adc_data_in (adc_os_data[63:32]),
|
||||
.adc_valid_out (adc_os_valid_q0),
|
||||
.adc_data_out (adc_os_data_q0),
|
||||
.adc_data_iq_in (adc_os_data_iq_i0_s),
|
||||
.adc_data_iq_out (adc_os_data_iq_q0_s),
|
||||
.adc_enable (adc_os_enable_q0),
|
||||
.up_adc_pn_err (up_adc_pn_err_s[1]),
|
||||
.up_adc_pn_oos (up_adc_pn_oos_s[1]),
|
||||
.up_adc_or (up_adc_or_s[1]),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq),
|
||||
.up_waddr (up_waddr),
|
||||
.up_wdata (up_wdata),
|
||||
.up_wack (up_wack_s[1]),
|
||||
.up_rreq (up_rreq),
|
||||
.up_raddr (up_raddr),
|
||||
.up_rdata (up_rdata_s[1]),
|
||||
.up_rack (up_rack_s[1]));
|
||||
|
||||
// common processor control
|
||||
|
||||
up_adc_common #(
|
||||
.COMMON_ID ('h20),
|
||||
.ID (ID),
|
||||
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
|
||||
.FPGA_FAMILY (FPGA_FAMILY),
|
||||
.SPEED_GRADE (SPEED_GRADE),
|
||||
.DEV_PACKAGE (DEV_PACKAGE)
|
||||
) i_up_adc_common (
|
||||
.mmcm_rst (),
|
||||
.adc_clk (adc_os_clk),
|
||||
.adc_rst (adc_os_rst),
|
||||
.adc_r1_mode (),
|
||||
.adc_ddr_edgesel (),
|
||||
.adc_pin_mode (),
|
||||
.adc_status (1'b1),
|
||||
.adc_sync_status (1'd0),
|
||||
.adc_status_ovf (adc_os_dovf),
|
||||
.adc_clk_ratio (32'd1),
|
||||
.adc_start_code (),
|
||||
.adc_sref_sync (),
|
||||
.adc_sync (),
|
||||
.up_pps_rcounter (32'b0),
|
||||
.up_pps_status (1'b0),
|
||||
.up_pps_irq_mask (),
|
||||
.up_adc_ce (),
|
||||
.up_status_pn_err (up_status_pn_err),
|
||||
.up_status_pn_oos (up_status_pn_oos),
|
||||
.up_status_or (up_status_or),
|
||||
.up_drp_sel (),
|
||||
.up_drp_wr (),
|
||||
.up_drp_addr (),
|
||||
.up_drp_wdata (),
|
||||
.up_drp_rdata (32'd0),
|
||||
.up_drp_ready (1'd0),
|
||||
.up_drp_locked (1'd1),
|
||||
.up_usr_chanmax_out (),
|
||||
.up_usr_chanmax_in (8'd3),
|
||||
.up_adc_gpio_in (32'd0),
|
||||
.up_adc_gpio_out (),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq),
|
||||
.up_waddr (up_waddr),
|
||||
.up_wdata (up_wdata),
|
||||
.up_wack (up_wack_s[2]),
|
||||
.up_rreq (up_rreq),
|
||||
.up_raddr (up_raddr),
|
||||
.up_rdata (up_rdata_s[2]),
|
||||
.up_rack (up_rack_s[2]));
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
@@ -0,0 +1,312 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module axi_ad9371_tx #(
|
||||
|
||||
parameter ID = 0,
|
||||
parameter FPGA_TECHNOLOGY = 0,
|
||||
parameter FPGA_FAMILY = 0,
|
||||
parameter SPEED_GRADE = 0,
|
||||
parameter DEV_PACKAGE = 0,
|
||||
parameter DAC_DDS_TYPE = 1,
|
||||
parameter DAC_DDS_CORDIC_DW = 16,
|
||||
parameter DAC_DDS_CORDIC_PHASE_DW = 16,
|
||||
parameter DATAPATH_DISABLE = 0) (
|
||||
|
||||
// dac interface
|
||||
|
||||
output dac_rst,
|
||||
input dac_clk,
|
||||
output [127:0] dac_data,
|
||||
|
||||
// master/slave
|
||||
|
||||
input dac_sync_in,
|
||||
output dac_sync_out,
|
||||
|
||||
// dma interface
|
||||
|
||||
output dac_enable_i0,
|
||||
output dac_valid_i0,
|
||||
input [ 31:0] dac_data_i0,
|
||||
output dac_enable_q0,
|
||||
output dac_valid_q0,
|
||||
input [ 31:0] dac_data_q0,
|
||||
output dac_enable_i1,
|
||||
output dac_valid_i1,
|
||||
input [ 31:0] dac_data_i1,
|
||||
output dac_enable_q1,
|
||||
output dac_valid_q1,
|
||||
input [ 31:0] dac_data_q1,
|
||||
input dac_dunf,
|
||||
|
||||
// processor interface
|
||||
|
||||
input up_rstn,
|
||||
input up_clk,
|
||||
input up_wreq,
|
||||
input [ 13:0] up_waddr,
|
||||
input [ 31:0] up_wdata,
|
||||
output reg up_wack,
|
||||
input up_rreq,
|
||||
input [ 13:0] up_raddr,
|
||||
output reg [ 31:0] up_rdata,
|
||||
output reg up_rack);
|
||||
|
||||
|
||||
|
||||
|
||||
// internal registers
|
||||
|
||||
reg dac_data_sync = 'd0;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire dac_data_sync_s;
|
||||
wire [ 31:0] dac_data_iq_i0_s;
|
||||
wire [ 31:0] dac_data_iq_q0_s;
|
||||
wire [ 31:0] dac_data_iq_i1_s;
|
||||
wire [ 31:0] dac_data_iq_q1_s;
|
||||
wire dac_dds_format_s;
|
||||
wire [ 4:0] up_wack_s;
|
||||
wire [ 4:0] up_rack_s;
|
||||
wire [ 31:0] up_rdata_s[0:4];
|
||||
|
||||
// master/slave
|
||||
|
||||
assign dac_data_sync_s = (ID == 0) ? dac_sync_out : dac_sync_in;
|
||||
|
||||
always @(posedge dac_clk) begin
|
||||
dac_data_sync <= dac_data_sync_s;
|
||||
end
|
||||
|
||||
// processor read interface
|
||||
|
||||
always @(negedge up_rstn or posedge up_clk) begin
|
||||
if (up_rstn == 0) begin
|
||||
up_wack <= 'd0;
|
||||
up_rack <= 'd0;
|
||||
up_rdata <= 'd0;
|
||||
end else begin
|
||||
up_wack <= | up_wack_s;
|
||||
up_rack <= | up_rack_s;
|
||||
up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] |
|
||||
up_rdata_s[3] | up_rdata_s[4];
|
||||
end
|
||||
end
|
||||
|
||||
// dac channel
|
||||
|
||||
assign dac_valid_i0 = 1'b1;
|
||||
|
||||
axi_ad9371_tx_channel #(
|
||||
.CHANNEL_ID (0),
|
||||
.Q_OR_I_N (0),
|
||||
.DAC_DDS_TYPE (DAC_DDS_TYPE),
|
||||
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
|
||||
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
|
||||
.DATAPATH_DISABLE (DATAPATH_DISABLE))
|
||||
i_tx_channel_0 (
|
||||
.dac_clk (dac_clk),
|
||||
.dac_rst (dac_rst),
|
||||
.dac_data_in (dac_data_i0),
|
||||
.dac_data_out (dac_data[31:0]),
|
||||
.dac_data_iq_in (dac_data_iq_q0_s),
|
||||
.dac_data_iq_out (dac_data_iq_i0_s),
|
||||
.dac_enable (dac_enable_i0),
|
||||
.dac_data_sync (dac_data_sync),
|
||||
.dac_dds_format (dac_dds_format_s),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq),
|
||||
.up_waddr (up_waddr),
|
||||
.up_wdata (up_wdata),
|
||||
.up_wack (up_wack_s[0]),
|
||||
.up_rreq (up_rreq),
|
||||
.up_raddr (up_raddr),
|
||||
.up_rdata (up_rdata_s[0]),
|
||||
.up_rack (up_rack_s[0]));
|
||||
|
||||
// dac channel
|
||||
|
||||
assign dac_valid_q0 = 1'b1;
|
||||
|
||||
axi_ad9371_tx_channel #(
|
||||
.CHANNEL_ID (1),
|
||||
.Q_OR_I_N (1),
|
||||
.DAC_DDS_TYPE (DAC_DDS_TYPE),
|
||||
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
|
||||
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
|
||||
.DATAPATH_DISABLE (DATAPATH_DISABLE))
|
||||
i_tx_channel_1 (
|
||||
.dac_clk (dac_clk),
|
||||
.dac_rst (dac_rst),
|
||||
.dac_data_in (dac_data_q0),
|
||||
.dac_data_out (dac_data[63:32]),
|
||||
.dac_data_iq_in (dac_data_iq_i0_s),
|
||||
.dac_data_iq_out (dac_data_iq_q0_s),
|
||||
.dac_enable (dac_enable_q0),
|
||||
.dac_data_sync (dac_data_sync),
|
||||
.dac_dds_format (dac_dds_format_s),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq),
|
||||
.up_waddr (up_waddr),
|
||||
.up_wdata (up_wdata),
|
||||
.up_wack (up_wack_s[1]),
|
||||
.up_rreq (up_rreq),
|
||||
.up_raddr (up_raddr),
|
||||
.up_rdata (up_rdata_s[1]),
|
||||
.up_rack (up_rack_s[1]));
|
||||
|
||||
// dac channel
|
||||
|
||||
assign dac_valid_i1 = 1'b1;
|
||||
|
||||
axi_ad9371_tx_channel #(
|
||||
.CHANNEL_ID (2),
|
||||
.Q_OR_I_N (0),
|
||||
.DAC_DDS_TYPE (DAC_DDS_TYPE),
|
||||
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
|
||||
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
|
||||
.DATAPATH_DISABLE (DATAPATH_DISABLE))
|
||||
i_tx_channel_2 (
|
||||
.dac_clk (dac_clk),
|
||||
.dac_rst (dac_rst),
|
||||
.dac_data_in (dac_data_i1),
|
||||
.dac_data_out (dac_data[95:64]),
|
||||
.dac_data_iq_in (dac_data_iq_q1_s),
|
||||
.dac_data_iq_out (dac_data_iq_i1_s),
|
||||
.dac_enable (dac_enable_i1),
|
||||
.dac_data_sync (dac_data_sync),
|
||||
.dac_dds_format (dac_dds_format_s),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq),
|
||||
.up_waddr (up_waddr),
|
||||
.up_wdata (up_wdata),
|
||||
.up_wack (up_wack_s[2]),
|
||||
.up_rreq (up_rreq),
|
||||
.up_raddr (up_raddr),
|
||||
.up_rdata (up_rdata_s[2]),
|
||||
.up_rack (up_rack_s[2]));
|
||||
|
||||
// dac channel
|
||||
|
||||
assign dac_valid_q1 = 1'b1;
|
||||
|
||||
axi_ad9371_tx_channel #(
|
||||
.CHANNEL_ID (3),
|
||||
.Q_OR_I_N (1),
|
||||
.DAC_DDS_TYPE (DAC_DDS_TYPE),
|
||||
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
|
||||
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
|
||||
.DATAPATH_DISABLE (DATAPATH_DISABLE))
|
||||
i_tx_channel_3 (
|
||||
.dac_clk (dac_clk),
|
||||
.dac_rst (dac_rst),
|
||||
.dac_data_in (dac_data_q1),
|
||||
.dac_data_out (dac_data[127:96]),
|
||||
.dac_data_iq_in (dac_data_iq_i1_s),
|
||||
.dac_data_iq_out (dac_data_iq_q1_s),
|
||||
.dac_enable (dac_enable_q1),
|
||||
.dac_data_sync (dac_data_sync),
|
||||
.dac_dds_format (dac_dds_format_s),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq),
|
||||
.up_waddr (up_waddr),
|
||||
.up_wdata (up_wdata),
|
||||
.up_wack (up_wack_s[3]),
|
||||
.up_rreq (up_rreq),
|
||||
.up_raddr (up_raddr),
|
||||
.up_rdata (up_rdata_s[3]),
|
||||
.up_rack (up_rack_s[3]));
|
||||
|
||||
// dac common processor interface
|
||||
|
||||
up_dac_common #(
|
||||
.ID (ID),
|
||||
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
|
||||
.FPGA_FAMILY (FPGA_FAMILY),
|
||||
.SPEED_GRADE (SPEED_GRADE),
|
||||
.DEV_PACKAGE (DEV_PACKAGE)
|
||||
) i_up_dac_common (
|
||||
.mmcm_rst (),
|
||||
.dac_clk (dac_clk),
|
||||
.dac_rst (dac_rst),
|
||||
.dac_sync (dac_sync_out),
|
||||
.dac_frame (),
|
||||
.dac_clksel (),
|
||||
.dac_par_type (),
|
||||
.dac_par_enb (),
|
||||
.dac_r1_mode (),
|
||||
.dac_datafmt (dac_dds_format_s),
|
||||
.dac_datarate (),
|
||||
.dac_status (1'b1),
|
||||
.dac_status_unf (dac_dunf),
|
||||
.dac_clk_ratio (32'd2),
|
||||
.up_dac_ce (),
|
||||
.up_pps_rcounter (32'b0),
|
||||
.up_pps_status (1'b0),
|
||||
.up_pps_irq_mask (),
|
||||
.up_drp_sel (),
|
||||
.up_drp_wr (),
|
||||
.up_drp_addr (),
|
||||
.up_drp_wdata (),
|
||||
.up_drp_rdata (32'd0),
|
||||
.up_drp_ready (1'd0),
|
||||
.up_drp_locked (1'd1),
|
||||
.up_usr_chanmax (),
|
||||
.dac_usr_chanmax (8'd3),
|
||||
.up_dac_gpio_in (32'd0),
|
||||
.up_dac_gpio_out (),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq),
|
||||
.up_waddr (up_waddr),
|
||||
.up_wdata (up_wdata),
|
||||
.up_wack (up_wack_s[4]),
|
||||
.up_rreq (up_rreq),
|
||||
.up_raddr (up_raddr),
|
||||
.up_rdata (up_rdata_s[4]),
|
||||
.up_rack (up_rack_s[4]));
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
@@ -0,0 +1,217 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module axi_ad9371_tx_channel #(
|
||||
|
||||
parameter CHANNEL_ID = 32'h0,
|
||||
parameter Q_OR_I_N = 0,
|
||||
parameter DAC_DDS_TYPE = 1,
|
||||
parameter DAC_DDS_CORDIC_DW = 16,
|
||||
parameter DAC_DDS_CORDIC_PHASE_DW = 16,
|
||||
parameter DATAPATH_DISABLE = 0) (
|
||||
|
||||
// dac interface
|
||||
|
||||
input dac_clk,
|
||||
input dac_rst,
|
||||
input [31:0] dac_data_in,
|
||||
output [31:0] dac_data_out,
|
||||
input [31:0] dac_data_iq_in,
|
||||
output reg [31:0] dac_data_iq_out,
|
||||
|
||||
// processor interface
|
||||
|
||||
output reg dac_enable,
|
||||
input dac_data_sync,
|
||||
input dac_dds_format,
|
||||
|
||||
// bus interface
|
||||
|
||||
input up_rstn,
|
||||
input up_clk,
|
||||
input up_wreq,
|
||||
input [13:0] up_waddr,
|
||||
input [31:0] up_wdata,
|
||||
output up_wack,
|
||||
input up_rreq,
|
||||
input [13:0] up_raddr,
|
||||
output [31:0] up_rdata,
|
||||
output up_rack);
|
||||
|
||||
|
||||
// internal registers
|
||||
|
||||
reg [31:0] dac_pat_data = 'd0;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire [31:0] dac_dds_data_s;
|
||||
wire [15:0] dac_dds_scale_1_s;
|
||||
wire [15:0] dac_dds_init_1_s;
|
||||
wire [15:0] dac_dds_incr_1_s;
|
||||
wire [15:0] dac_dds_scale_2_s;
|
||||
wire [15:0] dac_dds_init_2_s;
|
||||
wire [15:0] dac_dds_incr_2_s;
|
||||
wire [15:0] dac_pat_data_1_s;
|
||||
wire [15:0] dac_pat_data_2_s;
|
||||
wire [ 3:0] dac_data_sel_s;
|
||||
wire dac_iqcor_enb_s;
|
||||
wire [15:0] dac_iqcor_coeff_1_s;
|
||||
wire [15:0] dac_iqcor_coeff_2_s;
|
||||
|
||||
// dac iq correction
|
||||
|
||||
generate
|
||||
if (DATAPATH_DISABLE == 1) begin
|
||||
|
||||
assign dac_data_out = dac_data_iq_out;
|
||||
|
||||
end else begin
|
||||
|
||||
ad_iqcor #(.Q_OR_I_N (Q_OR_I_N)) i_ad_iqcor_1 (
|
||||
.clk (dac_clk),
|
||||
.valid (1'b1),
|
||||
.data_in (dac_data_iq_out[31:16]),
|
||||
.data_iq (dac_data_iq_in[31:16]),
|
||||
.valid_out (),
|
||||
.data_out (dac_data_out[31:16]),
|
||||
.iqcor_enable (dac_iqcor_enb_s),
|
||||
.iqcor_coeff_1 (dac_iqcor_coeff_1_s),
|
||||
.iqcor_coeff_2 (dac_iqcor_coeff_2_s));
|
||||
|
||||
ad_iqcor #(.Q_OR_I_N (Q_OR_I_N)) i_ad_iqcor_0 (
|
||||
.clk (dac_clk),
|
||||
.valid (1'b1),
|
||||
.data_in (dac_data_iq_out[15:0]),
|
||||
.data_iq (dac_data_iq_in[15:0]),
|
||||
.valid_out (),
|
||||
.data_out (dac_data_out[15:0]),
|
||||
.iqcor_enable (dac_iqcor_enb_s),
|
||||
.iqcor_coeff_1 (dac_iqcor_coeff_1_s),
|
||||
.iqcor_coeff_2 (dac_iqcor_coeff_2_s));
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// dac mux
|
||||
|
||||
always @(posedge dac_clk) begin
|
||||
dac_enable <= (dac_data_sel_s == 4'h2) ? 1'b1 : 1'b0;
|
||||
case (dac_data_sel_s)
|
||||
4'h3: dac_data_iq_out <= 32'd0;
|
||||
4'h2: dac_data_iq_out <= dac_data_in;
|
||||
4'h1: dac_data_iq_out <= dac_pat_data;
|
||||
default: dac_data_iq_out <= dac_dds_data_s;
|
||||
endcase
|
||||
end
|
||||
|
||||
// pattern
|
||||
|
||||
always @(posedge dac_clk) begin
|
||||
dac_pat_data <= {dac_pat_data_2_s, dac_pat_data_1_s};
|
||||
end
|
||||
|
||||
// dds
|
||||
|
||||
ad_dds #(
|
||||
.DISABLE (DATAPATH_DISABLE),
|
||||
.DDS_DW (16),
|
||||
.PHASE_DW (16),
|
||||
.DDS_TYPE (DAC_DDS_TYPE),
|
||||
.CORDIC_DW (DAC_DDS_CORDIC_DW),
|
||||
.CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
|
||||
.CLK_RATIO (2))
|
||||
i_dds (
|
||||
.clk (dac_clk),
|
||||
.dac_dds_format (dac_dds_format),
|
||||
.dac_data_sync (dac_data_sync),
|
||||
.dac_valid (1'b1),
|
||||
.tone_1_scale (dac_dds_scale_1_s),
|
||||
.tone_2_scale (dac_dds_scale_2_s),
|
||||
.tone_1_init_offset (dac_dds_init_1_s),
|
||||
.tone_2_init_offset (dac_dds_init_2_s),
|
||||
.tone_1_freq_word (dac_dds_incr_1_s),
|
||||
.tone_2_freq_word (dac_dds_incr_2_s),
|
||||
.dac_dds_data (dac_dds_data_s));
|
||||
|
||||
|
||||
// single channel processor
|
||||
|
||||
up_dac_channel #(.CHANNEL_ID (CHANNEL_ID)) i_up_dac_channel (
|
||||
.dac_clk (dac_clk),
|
||||
.dac_rst (dac_rst),
|
||||
.dac_dds_scale_1 (dac_dds_scale_1_s),
|
||||
.dac_dds_init_1 (dac_dds_init_1_s),
|
||||
.dac_dds_incr_1 (dac_dds_incr_1_s),
|
||||
.dac_dds_scale_2 (dac_dds_scale_2_s),
|
||||
.dac_dds_init_2 (dac_dds_init_2_s),
|
||||
.dac_dds_incr_2 (dac_dds_incr_2_s),
|
||||
.dac_pat_data_1 (dac_pat_data_1_s),
|
||||
.dac_pat_data_2 (dac_pat_data_2_s),
|
||||
.dac_data_sel (dac_data_sel_s),
|
||||
.dac_iq_mode (),
|
||||
.dac_iqcor_enb (dac_iqcor_enb_s),
|
||||
.dac_iqcor_coeff_1 (dac_iqcor_coeff_1_s),
|
||||
.dac_iqcor_coeff_2 (dac_iqcor_coeff_2_s),
|
||||
.up_usr_datatype_be (),
|
||||
.up_usr_datatype_signed (),
|
||||
.up_usr_datatype_shift (),
|
||||
.up_usr_datatype_total_bits (),
|
||||
.up_usr_datatype_bits (),
|
||||
.up_usr_interpolation_m (),
|
||||
.up_usr_interpolation_n (),
|
||||
.dac_usr_datatype_be (1'b0),
|
||||
.dac_usr_datatype_signed (1'b1),
|
||||
.dac_usr_datatype_shift (8'd0),
|
||||
.dac_usr_datatype_total_bits (8'd16),
|
||||
.dac_usr_datatype_bits (8'd16),
|
||||
.dac_usr_interpolation_m (16'd1),
|
||||
.dac_usr_interpolation_n (16'd1),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq),
|
||||
.up_waddr (up_waddr),
|
||||
.up_wdata (up_wdata),
|
||||
.up_wack (up_wack),
|
||||
.up_rreq (up_rreq),
|
||||
.up_raddr (up_raddr),
|
||||
.up_rdata (up_rdata),
|
||||
.up_rack (up_rack));
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
@@ -0,0 +1,47 @@
|
||||
# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!
|
||||
proc init {cellpath otherInfo} {
|
||||
set ip [get_bd_cells $cellpath]
|
||||
|
||||
bd::mark_propagate_only $ip " \
|
||||
DEV_PACKAGE \
|
||||
SPEED_GRADE \
|
||||
FPGA_FAMILY \
|
||||
FPGA_TECHNOLOGY"
|
||||
|
||||
adi_auto_assign_device_spec $cellpath
|
||||
}
|
||||
|
||||
# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)
|
||||
proc adi_auto_assign_device_spec {cellpath} {
|
||||
|
||||
set ip [get_bd_cells $cellpath]
|
||||
set ip_param_list [list_property $ip]
|
||||
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
|
||||
|
||||
set parent_dir "../"
|
||||
for {set x 1} {$x<=4} {incr x} {
|
||||
set linkname ${ip_path}${parent_dir}scripts/adi_xilinx_device_info_enc.tcl
|
||||
if { [file exists $linkname] } {
|
||||
source ${ip_path}${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl
|
||||
break
|
||||
}
|
||||
append parent_dir "../"
|
||||
}
|
||||
|
||||
# Find predefindes auto assignable parameters
|
||||
foreach i $auto_set_param_list {
|
||||
if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
|
||||
set val [adi_device_spec $cellpath $i]
|
||||
set_property CONFIG.$i $val $ip
|
||||
}
|
||||
}
|
||||
|
||||
# Find predefindes auto assignable/overwritable parameters
|
||||
foreach i $auto_set_param_list_overwritable {
|
||||
if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
|
||||
set val [adi_device_spec $cellpath $i]
|
||||
set_property CONFIG.$i $val $ip
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,2 @@
|
||||
CLEAN_TARGET += bd
|
||||
CLEAN_TARGET += temporary_case_dependencies.mk
|
||||
@@ -0,0 +1,163 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||
ipgui::add_param $IPINST -name "ADC_DATAPATH_DISABLE" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "DAC_DATAPATH_DISABLE" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "DAC_DDS_CORDIC_DW" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "DAC_DDS_CORDIC_PHASE_DW" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "DAC_DDS_TYPE" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "ID" -parent ${Page_0}
|
||||
#Adding Group
|
||||
set FPGA_info [ipgui::add_group $IPINST -name "FPGA info" -parent ${Page_0}]
|
||||
ipgui::add_param $IPINST -name "FPGA_TECHNOLOGY" -parent ${FPGA_info} -widget comboBox
|
||||
ipgui::add_param $IPINST -name "FPGA_FAMILY" -parent ${FPGA_info} -widget comboBox
|
||||
ipgui::add_param $IPINST -name "SPEED_GRADE" -parent ${FPGA_info} -widget comboBox
|
||||
ipgui::add_param $IPINST -name "DEV_PACKAGE" -parent ${FPGA_info} -widget comboBox
|
||||
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ADC_DATAPATH_DISABLE { PARAM_VALUE.ADC_DATAPATH_DISABLE } {
|
||||
# Procedure called to update ADC_DATAPATH_DISABLE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ADC_DATAPATH_DISABLE { PARAM_VALUE.ADC_DATAPATH_DISABLE } {
|
||||
# Procedure called to validate ADC_DATAPATH_DISABLE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DAC_DATAPATH_DISABLE { PARAM_VALUE.DAC_DATAPATH_DISABLE } {
|
||||
# Procedure called to update DAC_DATAPATH_DISABLE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DAC_DATAPATH_DISABLE { PARAM_VALUE.DAC_DATAPATH_DISABLE } {
|
||||
# Procedure called to validate DAC_DATAPATH_DISABLE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DAC_DDS_CORDIC_DW { PARAM_VALUE.DAC_DDS_CORDIC_DW } {
|
||||
# Procedure called to update DAC_DDS_CORDIC_DW when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DAC_DDS_CORDIC_DW { PARAM_VALUE.DAC_DDS_CORDIC_DW } {
|
||||
# Procedure called to validate DAC_DDS_CORDIC_DW
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW { PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW } {
|
||||
# Procedure called to update DAC_DDS_CORDIC_PHASE_DW when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW { PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW } {
|
||||
# Procedure called to validate DAC_DDS_CORDIC_PHASE_DW
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DAC_DDS_TYPE { PARAM_VALUE.DAC_DDS_TYPE } {
|
||||
# Procedure called to update DAC_DDS_TYPE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DAC_DDS_TYPE { PARAM_VALUE.DAC_DDS_TYPE } {
|
||||
# Procedure called to validate DAC_DDS_TYPE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } {
|
||||
# Procedure called to update DEV_PACKAGE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } {
|
||||
# Procedure called to validate DEV_PACKAGE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } {
|
||||
# Procedure called to update FPGA_FAMILY when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } {
|
||||
# Procedure called to validate FPGA_FAMILY
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } {
|
||||
# Procedure called to update FPGA_TECHNOLOGY when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } {
|
||||
# Procedure called to validate FPGA_TECHNOLOGY
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } {
|
||||
# Procedure called to update ID when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } {
|
||||
# Procedure called to validate ID
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } {
|
||||
# Procedure called to update SPEED_GRADE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } {
|
||||
# Procedure called to validate SPEED_GRADE
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.FPGA_TECHNOLOGY { MODELPARAM_VALUE.FPGA_TECHNOLOGY PARAM_VALUE.FPGA_TECHNOLOGY } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.FPGA_TECHNOLOGY}] ${MODELPARAM_VALUE.FPGA_TECHNOLOGY}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.FPGA_FAMILY { MODELPARAM_VALUE.FPGA_FAMILY PARAM_VALUE.FPGA_FAMILY } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.FPGA_FAMILY}] ${MODELPARAM_VALUE.FPGA_FAMILY}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.SPEED_GRADE { MODELPARAM_VALUE.SPEED_GRADE PARAM_VALUE.SPEED_GRADE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.SPEED_GRADE}] ${MODELPARAM_VALUE.SPEED_GRADE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DEV_PACKAGE { MODELPARAM_VALUE.DEV_PACKAGE PARAM_VALUE.DEV_PACKAGE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DEV_PACKAGE}] ${MODELPARAM_VALUE.DEV_PACKAGE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DAC_DDS_TYPE { MODELPARAM_VALUE.DAC_DDS_TYPE PARAM_VALUE.DAC_DDS_TYPE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DAC_DDS_TYPE}] ${MODELPARAM_VALUE.DAC_DDS_TYPE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DAC_DDS_CORDIC_DW { MODELPARAM_VALUE.DAC_DDS_CORDIC_DW PARAM_VALUE.DAC_DDS_CORDIC_DW } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DAC_DDS_CORDIC_DW}] ${MODELPARAM_VALUE.DAC_DDS_CORDIC_DW}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW { MODELPARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW}] ${MODELPARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DAC_DATAPATH_DISABLE { MODELPARAM_VALUE.DAC_DATAPATH_DISABLE PARAM_VALUE.DAC_DATAPATH_DISABLE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DAC_DATAPATH_DISABLE}] ${MODELPARAM_VALUE.DAC_DATAPATH_DISABLE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.ADC_DATAPATH_DISABLE { MODELPARAM_VALUE.ADC_DATAPATH_DISABLE PARAM_VALUE.ADC_DATAPATH_DISABLE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ADC_DATAPATH_DISABLE}] ${MODELPARAM_VALUE.ADC_DATAPATH_DISABLE}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user