Archived
first commit after restructuring
This commit is contained in:
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####################################################################################
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## Copyright 2018(c) Analog Devices, Inc.
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## Auto-generated, do not modify!
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####################################################################################
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LIBRARY_NAME := axi_ad9671
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GENERIC_DEPS += ../common/ad_datafmt.v
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GENERIC_DEPS += ../common/ad_mem.v
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GENERIC_DEPS += ../common/ad_pnmon.v
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GENERIC_DEPS += ../common/ad_rst.v
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GENERIC_DEPS += ../common/ad_xcvr_rx_if.v
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GENERIC_DEPS += ../common/up_adc_channel.v
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GENERIC_DEPS += ../common/up_adc_common.v
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GENERIC_DEPS += ../common/up_axi.v
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GENERIC_DEPS += ../common/up_clock_mon.v
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GENERIC_DEPS += ../common/up_xfer_cntrl.v
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GENERIC_DEPS += ../common/up_xfer_status.v
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GENERIC_DEPS += axi_ad9671.v
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GENERIC_DEPS += axi_ad9671_channel.v
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GENERIC_DEPS += axi_ad9671_if.v
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GENERIC_DEPS += axi_ad9671_pnmon.v
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XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc
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XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc
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XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
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XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc
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XILINX_DEPS += axi_ad9671_ip.tcl
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INTEL_DEPS += ../intel/common/up_clock_mon_constr.sdc
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INTEL_DEPS += ../intel/common/up_rst_constr.sdc
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INTEL_DEPS += ../intel/common/up_xfer_cntrl_constr.sdc
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INTEL_DEPS += ../intel/common/up_xfer_status_constr.sdc
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INTEL_DEPS += axi_ad9671_hw.tcl
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include ../scripts/library.mk
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@@ -0,0 +1,3 @@
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version:1
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6d6f64655f636f756e7465727c42617463684d6f6465:1
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eof:
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@@ -0,0 +1,6 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
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||||
<!-- -->
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||||
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
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<labtools version="1" minor="0"/>
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@@ -0,0 +1,307 @@
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// ***************************************************************************
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||||
// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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||||
// In this HDL repository, there are many different and unique modules, consisting
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||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
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||||
//
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||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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||||
//
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||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
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||||
// as long as it attaches to an ADI device.
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||||
//
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||||
// ***************************************************************************
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||||
// ***************************************************************************
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||||
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`timescale 1ns/100ps
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module axi_ad9671 #(
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parameter ID = 0,
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parameter FPGA_TECHNOLOGY = 0,
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parameter FPGA_FAMILY = 0,
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parameter SPEED_GRADE = 0,
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parameter DEV_PACKAGE = 0,
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parameter QUAD_OR_DUAL_N = 1) (
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||||
// jesd interface
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// rx_clk is (line-rate/40)
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input rx_clk,
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input [ 3:0] rx_sof,
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input rx_valid,
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input [(64*QUAD_OR_DUAL_N)+63:0] rx_data,
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output rx_ready,
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// dma interface
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output adc_clk,
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output [ 7:0] adc_valid,
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output [ 7:0] adc_enable,
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output [127:0] adc_data,
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input adc_dovf,
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input adc_sync_in,
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output adc_sync_out,
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input [ 3:0] adc_raddr_in,
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output [ 3:0] adc_raddr_out,
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// axi interface
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input s_axi_aclk,
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input s_axi_aresetn,
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input s_axi_awvalid,
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input [ 15:0] s_axi_awaddr,
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input [ 2:0] s_axi_awprot,
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output s_axi_awready,
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input s_axi_wvalid,
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input [ 31:0] s_axi_wdata,
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input [ 3:0] s_axi_wstrb,
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output s_axi_wready,
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output s_axi_bvalid,
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output [ 1:0] s_axi_bresp,
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input s_axi_bready,
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input s_axi_arvalid,
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input [ 15:0] s_axi_araddr,
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input [ 2:0] s_axi_arprot,
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output s_axi_arready,
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output s_axi_rvalid,
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output [ 1:0] s_axi_rresp,
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output [ 31:0] s_axi_rdata,
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input s_axi_rready);
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// internal registers
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reg up_status_pn_err = 'd0;
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reg up_status_pn_oos = 'd0;
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reg up_status_or = 'd0;
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reg [ 31:0] up_rdata = 'd0;
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reg up_rack = 'd0;
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reg up_wack = 'd0;
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// internal clocks & resets
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wire adc_rst;
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wire up_rstn;
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wire up_clk;
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// internal signals
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wire adc_status_s;
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wire adc_sync_status_s;
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wire adc_valid_s;
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wire [ 15:0] adc_data_s[7:0];
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wire [ 7:0] adc_or_s;
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wire [ 7:0] up_adc_pn_err_s;
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wire [ 7:0] up_adc_pn_oos_s;
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wire [ 7:0] up_adc_or_s;
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wire up_wreq_s;
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wire [ 13:0] up_waddr_s;
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wire [ 31:0] up_wdata_s;
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wire up_rreq_s;
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wire [ 13:0] up_raddr_s;
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wire [ 31:0] up_rdata_s[8:0];
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wire up_rack_s[8:0];
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wire up_wack_s[8:0];
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wire [ 31:0] adc_start_code;
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wire adc_sync;
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// signal name changes
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assign rx_ready = 1'b1;
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assign up_clk = s_axi_aclk;
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assign up_rstn = s_axi_aresetn;
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// processor read interface
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_status_pn_err <= 'd0;
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up_status_pn_oos <= 'd0;
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up_status_or <= 'd0;
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up_rdata <= 'd0;
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up_rack <= 'd0;
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up_wack <= 'd0;
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end else begin
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up_status_pn_err <= | up_adc_pn_err_s;
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up_status_pn_oos <= | up_adc_pn_oos_s;
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up_status_or <= | up_adc_or_s;
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up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] | up_rdata_s[3] |
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up_rdata_s[4] | up_rdata_s[5] | up_rdata_s[6] | up_rdata_s[7] | up_rdata_s[8];
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up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2] | up_rack_s[3] |
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up_rack_s[4] | up_rack_s[5] | up_rack_s[6] | up_rack_s[7] | up_rack_s[8];
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up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2] | up_wack_s[3] |
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up_wack_s[4] | up_wack_s[5] | up_wack_s[6] | up_wack_s[7] | up_wack_s[8];
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end
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end
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// main (device interface)
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axi_ad9671_if #(
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.QUAD_OR_DUAL_N (QUAD_OR_DUAL_N),
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.ID (ID))
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i_if (
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.rx_clk (rx_clk),
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.rx_data (rx_data),
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.rx_sof (rx_sof),
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.adc_clk (adc_clk),
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.adc_rst (adc_rst),
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.adc_valid (adc_valid_s),
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.adc_data_a (adc_data_s[0]),
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||||
.adc_or_a (adc_or_s[0]),
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.adc_data_b (adc_data_s[1]),
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.adc_or_b (adc_or_s[1]),
|
||||
.adc_data_c (adc_data_s[2]),
|
||||
.adc_or_c (adc_or_s[2]),
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.adc_data_d (adc_data_s[3]),
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||||
.adc_or_d (adc_or_s[3]),
|
||||
.adc_data_e (adc_data_s[4]),
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.adc_or_e (adc_or_s[4]),
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||||
.adc_data_f (adc_data_s[5]),
|
||||
.adc_or_f (adc_or_s[5]),
|
||||
.adc_data_g (adc_data_s[6]),
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||||
.adc_or_g (adc_or_s[6]),
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||||
.adc_data_h (adc_data_s[7]),
|
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.adc_or_h (adc_or_s[7]),
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.adc_start_code (adc_start_code),
|
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.adc_sync (adc_sync),
|
||||
.adc_sync_in (adc_sync_in),
|
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.adc_sync_out (adc_sync_out),
|
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.adc_sync_status (adc_sync_status_s),
|
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.adc_status (adc_status_s),
|
||||
.adc_raddr_in (adc_raddr_in),
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||||
.adc_raddr_out (adc_raddr_out));
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// channels
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genvar n;
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generate
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for (n = 0; n < 8; n = n + 1) begin: g_channel
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||||
axi_ad9671_channel #(.CHANNEL_ID(n)) i_channel (
|
||||
.adc_clk (adc_clk),
|
||||
.adc_rst (adc_rst),
|
||||
.adc_valid (adc_valid_s),
|
||||
.adc_data (adc_data_s[n]),
|
||||
.adc_or (adc_or_s[n]),
|
||||
.adc_dfmt_valid (adc_valid[n]),
|
||||
.adc_dfmt_data (adc_data[(n*16)+15:(n*16)]),
|
||||
.adc_enable (adc_enable[n]),
|
||||
.up_adc_pn_err (up_adc_pn_err_s[n]),
|
||||
.up_adc_pn_oos (up_adc_pn_oos_s[n]),
|
||||
.up_adc_or (up_adc_or_s[n]),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq_s),
|
||||
.up_waddr (up_waddr_s),
|
||||
.up_wdata (up_wdata_s),
|
||||
.up_wack (up_wack_s[n]),
|
||||
.up_rreq (up_rreq_s),
|
||||
.up_raddr (up_raddr_s),
|
||||
.up_rdata (up_rdata_s[n]),
|
||||
.up_rack (up_rack_s[n]));
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// common processor control
|
||||
|
||||
up_adc_common #(
|
||||
.ID (ID),
|
||||
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
|
||||
.FPGA_FAMILY (FPGA_FAMILY),
|
||||
.SPEED_GRADE (SPEED_GRADE),
|
||||
.DEV_PACKAGE (DEV_PACKAGE)
|
||||
) i_up_adc_common (
|
||||
.mmcm_rst (),
|
||||
.adc_clk (adc_clk),
|
||||
.adc_rst (adc_rst),
|
||||
.adc_r1_mode (),
|
||||
.adc_ddr_edgesel (),
|
||||
.adc_pin_mode (),
|
||||
.adc_status (adc_status_s),
|
||||
.adc_sync_status (adc_sync_status_s),
|
||||
.adc_status_ovf (adc_dovf),
|
||||
.adc_clk_ratio (32'd1),
|
||||
.adc_start_code (adc_start_code),
|
||||
.adc_sref_sync (),
|
||||
.adc_sync (adc_sync),
|
||||
.up_adc_ce (),
|
||||
.up_status_pn_err (up_status_pn_err),
|
||||
.up_status_pn_oos (up_status_pn_oos),
|
||||
.up_status_or (up_status_or),
|
||||
.up_drp_sel (),
|
||||
.up_drp_wr (),
|
||||
.up_drp_addr (),
|
||||
.up_drp_wdata (),
|
||||
.up_drp_rdata (32'd0),
|
||||
.up_drp_ready (1'd0),
|
||||
.up_drp_locked (1'd1),
|
||||
.up_usr_chanmax_out (),
|
||||
.up_usr_chanmax_in (8'd7),
|
||||
.up_adc_gpio_in (32'd0),
|
||||
.up_adc_gpio_out (),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq_s),
|
||||
.up_waddr (up_waddr_s),
|
||||
.up_wdata (up_wdata_s),
|
||||
.up_wack (up_wack_s[8]),
|
||||
.up_rreq (up_rreq_s),
|
||||
.up_raddr (up_raddr_s),
|
||||
.up_rdata (up_rdata_s[8]),
|
||||
.up_rack (up_rack_s[8]));
|
||||
|
||||
// up bus interface
|
||||
|
||||
up_axi i_up_axi (
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_axi_awvalid (s_axi_awvalid),
|
||||
.up_axi_awaddr (s_axi_awaddr),
|
||||
.up_axi_awready (s_axi_awready),
|
||||
.up_axi_wvalid (s_axi_wvalid),
|
||||
.up_axi_wdata (s_axi_wdata),
|
||||
.up_axi_wstrb (s_axi_wstrb),
|
||||
.up_axi_wready (s_axi_wready),
|
||||
.up_axi_bvalid (s_axi_bvalid),
|
||||
.up_axi_bresp (s_axi_bresp),
|
||||
.up_axi_bready (s_axi_bready),
|
||||
.up_axi_arvalid (s_axi_arvalid),
|
||||
.up_axi_araddr (s_axi_araddr),
|
||||
.up_axi_arready (s_axi_arready),
|
||||
.up_axi_rvalid (s_axi_rvalid),
|
||||
.up_axi_rresp (s_axi_rresp),
|
||||
.up_axi_rdata (s_axi_rdata),
|
||||
.up_axi_rready (s_axi_rready),
|
||||
.up_wreq (up_wreq_s),
|
||||
.up_waddr (up_waddr_s),
|
||||
.up_wdata (up_wdata_s),
|
||||
.up_wack (up_wack),
|
||||
.up_rreq (up_rreq_s),
|
||||
.up_raddr (up_raddr_s),
|
||||
.up_rdata (up_rdata),
|
||||
.up_rack (up_rack));
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
@@ -0,0 +1,505 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Version="7" Minor="40" Path="/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9671/axi_ad9671.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="bb516d84070b48f79f958adf196cf464"/>
|
||||
<Option Name="Part" Val="xc7vx485tffg1157-1"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="BoardPart" Val=""/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../library"/>
|
||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../../ghdl/library"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="DSAVendor" Val="xilinx"/>
|
||||
<Option Name="DSANumComputeUnits" Val="60"/>
|
||||
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|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="HDPYFinalizeIO"/>
|
||||
</MsgRule>
|
||||
<Board/>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
<BootPmcSettings Version="1" Minor="0">
|
||||
<Parameters>
|
||||
<Parameter Name="PMC_CDO.ATTRS.LOADADDR" Value="" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_FB_CLK" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_FREQ" Value="300" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_BUS_WIDTH" Value="x1" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_DATA_MODE" Value="Single" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_FREQ" Value="200" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_SLOT_TYPE" Value="SD 2.0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_FREQ" Value="200" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_SLOT_TYPE" Value="SD 2.0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSPI_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSPI_FREQ" Value="300" Type="string"/>
|
||||
<Parameter Name="BOOT.USB_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SMAP_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SMAP_DATA_WIDTH" Value="32 Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSC_FREQ" Value="33.333" Type="string"/>
|
||||
<Parameter Name="BOOT.SECONDARY.PCIE_ENABLE" Value="0" Type="string"/>
|
||||
</Parameters>
|
||||
</BootPmcSettings>
|
||||
</Project>
|
||||
@@ -0,0 +1,153 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// ADC channel-
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module axi_ad9671_channel #(
|
||||
|
||||
parameter CHANNEL_ID = 0) (
|
||||
|
||||
// adc interface
|
||||
|
||||
input adc_clk,
|
||||
input adc_rst,
|
||||
input adc_valid,
|
||||
input [15:0] adc_data,
|
||||
input adc_or,
|
||||
|
||||
// channel interface
|
||||
|
||||
output adc_dfmt_valid,
|
||||
output [15:0] adc_dfmt_data,
|
||||
output adc_enable,
|
||||
output up_adc_pn_err,
|
||||
output up_adc_pn_oos,
|
||||
output up_adc_or,
|
||||
|
||||
// processor interface
|
||||
|
||||
input up_rstn,
|
||||
input up_clk,
|
||||
input up_wreq,
|
||||
input [13:0] up_waddr,
|
||||
input [31:0] up_wdata,
|
||||
output up_wack,
|
||||
input up_rreq,
|
||||
input [13:0] up_raddr,
|
||||
output [31:0] up_rdata,
|
||||
output up_rack);
|
||||
|
||||
|
||||
// internal signals
|
||||
|
||||
wire adc_dfmt_se_s;
|
||||
wire adc_dfmt_type_s;
|
||||
wire adc_dfmt_enable_s;
|
||||
wire [ 3:0] adc_pnseq_sel_s;
|
||||
wire adc_pn_err_s;
|
||||
wire adc_pn_oos_s;
|
||||
|
||||
// instantiations
|
||||
|
||||
axi_ad9671_pnmon i_pnmon (
|
||||
.adc_clk (adc_clk),
|
||||
.adc_valid (adc_valid),
|
||||
.adc_data (adc_data),
|
||||
.adc_pn_oos (adc_pn_oos_s),
|
||||
.adc_pn_err (adc_pn_err_s),
|
||||
.adc_pnseq_sel (adc_pnseq_sel_s));
|
||||
|
||||
ad_datafmt #(.DATA_WIDTH(16)) i_ad_datafmt (
|
||||
.clk (adc_clk),
|
||||
.valid (adc_valid),
|
||||
.data (adc_data),
|
||||
.valid_out (adc_dfmt_valid),
|
||||
.data_out (adc_dfmt_data),
|
||||
.dfmt_enable (adc_dfmt_enable_s),
|
||||
.dfmt_type (adc_dfmt_type_s),
|
||||
.dfmt_se (adc_dfmt_se_s));
|
||||
|
||||
up_adc_channel #(.CHANNEL_ID(CHANNEL_ID)) i_up_adc_channel (
|
||||
.adc_clk (adc_clk),
|
||||
.adc_rst (adc_rst),
|
||||
.adc_enable (adc_enable),
|
||||
.adc_iqcor_enb (),
|
||||
.adc_dcfilt_enb (),
|
||||
.adc_dfmt_se (adc_dfmt_se_s),
|
||||
.adc_dfmt_type (adc_dfmt_type_s),
|
||||
.adc_dfmt_enable (adc_dfmt_enable_s),
|
||||
.adc_dcfilt_offset (),
|
||||
.adc_dcfilt_coeff (),
|
||||
.adc_iqcor_coeff_1 (),
|
||||
.adc_iqcor_coeff_2 (),
|
||||
.adc_pnseq_sel (adc_pnseq_sel_s),
|
||||
.adc_data_sel (),
|
||||
.adc_pn_err (adc_pn_err_s),
|
||||
.adc_pn_oos (adc_pn_oos_s),
|
||||
.adc_or (adc_or),
|
||||
.up_adc_pn_err (up_adc_pn_err),
|
||||
.up_adc_pn_oos (up_adc_pn_oos),
|
||||
.up_adc_or (up_adc_or),
|
||||
.up_usr_datatype_be (),
|
||||
.up_usr_datatype_signed (),
|
||||
.up_usr_datatype_shift (),
|
||||
.up_usr_datatype_total_bits (),
|
||||
.up_usr_datatype_bits (),
|
||||
.up_usr_decimation_m (),
|
||||
.up_usr_decimation_n (),
|
||||
.adc_usr_datatype_be (1'b0),
|
||||
.adc_usr_datatype_signed (1'b1),
|
||||
.adc_usr_datatype_shift (8'd0),
|
||||
.adc_usr_datatype_total_bits (8'd16),
|
||||
.adc_usr_datatype_bits (8'd16),
|
||||
.adc_usr_decimation_m (16'd1),
|
||||
.adc_usr_decimation_n (16'd1),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq),
|
||||
.up_waddr (up_waddr),
|
||||
.up_wdata (up_wdata),
|
||||
.up_wack (up_wack),
|
||||
.up_rreq (up_rreq),
|
||||
.up_raddr (up_raddr),
|
||||
.up_rdata (up_rdata),
|
||||
.up_rack (up_rack));
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
@@ -0,0 +1,93 @@
|
||||
|
||||
|
||||
package require qsys
|
||||
package require quartus::device
|
||||
|
||||
source ../scripts/adi_env.tcl
|
||||
source ../scripts/adi_ip_intel.tcl
|
||||
|
||||
set_module_property NAME axi_ad9671
|
||||
set_module_property DESCRIPTION "AXI AD9671 Interface"
|
||||
set_module_property VERSION 1.0
|
||||
set_module_property GROUP "Analog Devices"
|
||||
set_module_property DISPLAY_NAME axi_ad9671
|
||||
set_module_property VALIDATION_CALLBACK info_param_validate
|
||||
|
||||
# files
|
||||
|
||||
add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
|
||||
set_fileset_property quartus_synth TOP_LEVEL axi_ad9671
|
||||
add_fileset_file ad_rst.v VERILOG PATH $ad_hdl_dir/library/common/ad_rst.v
|
||||
add_fileset_file ad_pnmon.v VERILOG PATH $ad_hdl_dir/library/common/ad_pnmon.v
|
||||
add_fileset_file ad_datafmt.v VERILOG PATH $ad_hdl_dir/library/common/ad_datafmt.v
|
||||
add_fileset_file up_axi.v VERILOG PATH $ad_hdl_dir/library/common/up_axi.v
|
||||
add_fileset_file up_xfer_cntrl.v VERILOG PATH $ad_hdl_dir/library/common/up_xfer_cntrl.v
|
||||
add_fileset_file up_xfer_status.v VERILOG PATH $ad_hdl_dir/library/common/up_xfer_status.v
|
||||
add_fileset_file up_clock_mon.v VERILOG PATH $ad_hdl_dir/library/common/up_clock_mon.v
|
||||
add_fileset_file up_adc_common.v VERILOG PATH $ad_hdl_dir/library/common/up_adc_common.v
|
||||
add_fileset_file up_adc_channel.v VERILOG PATH $ad_hdl_dir/library/common/up_adc_channel.v
|
||||
add_fileset_file ad_xcvr_rx_if.v VERILOG PATH $ad_hdl_dir/library/common/ad_xcvr_rx_if.v
|
||||
add_fileset_file ad_mem.v VERILOG PATH $ad_hdl_dir/library/common/ad_mem.v
|
||||
add_fileset_file axi_ad9671_pnmon.v VERILOG PATH axi_ad9671_pnmon.v
|
||||
add_fileset_file axi_ad9671_if.v VERILOG PATH axi_ad9671_if.v
|
||||
add_fileset_file axi_ad9671_channel.v VERILOG PATH axi_ad9671_channel.v
|
||||
add_fileset_file axi_ad9671.v VERILOG PATH axi_ad9671.v TOP_LEVEL_FILE
|
||||
add_fileset_file up_xfer_cntrl_constr.sdc SDC PATH $ad_hdl_dir/library/intel/common/up_xfer_cntrl_constr.sdc
|
||||
add_fileset_file up_xfer_status_constr.sdc SDC PATH $ad_hdl_dir/library/intel/common/up_xfer_status_constr.sdc
|
||||
add_fileset_file up_clock_mon_constr.sdc SDC PATH $ad_hdl_dir/library/intel/common/up_clock_mon_constr.sdc
|
||||
add_fileset_file up_rst_constr.sdc SDC PATH $ad_hdl_dir/library/intel/common/up_rst_constr.sdc
|
||||
|
||||
# parameters
|
||||
|
||||
add_parameter ID INTEGER 0
|
||||
set_parameter_property ID DEFAULT_VALUE 0
|
||||
set_parameter_property ID DISPLAY_NAME ID
|
||||
set_parameter_property ID UNITS None
|
||||
set_parameter_property ID HDL_PARAMETER true
|
||||
|
||||
add_parameter QUAD_OR_DUAL_N INTEGER 0
|
||||
set_parameter_property QUAD_OR_DUAL_N DEFAULT_VALUE 1
|
||||
set_parameter_property QUAD_OR_DUAL_N DISPLAY_NAME QUAD_OR_DUAL_N
|
||||
set_parameter_property QUAD_OR_DUAL_N UNITS None
|
||||
set_parameter_property QUAD_OR_DUAL_N HDL_PARAMETER true
|
||||
|
||||
adi_add_auto_fpga_spec_params
|
||||
|
||||
# axi4 slave
|
||||
|
||||
ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn
|
||||
|
||||
# transceiver interface
|
||||
|
||||
ad_interface clock rx_clk input 1
|
||||
ad_interface signal rx_sof input 4 export
|
||||
|
||||
add_interface if_rx_data avalon_streaming sink
|
||||
add_interface_port if_rx_data rx_data data input 64*QUAD_OR_DUAL_N+64
|
||||
add_interface_port if_rx_data rx_valid valid input 1
|
||||
add_interface_port if_rx_data rx_ready ready output 1
|
||||
set_interface_property if_rx_data associatedClock if_rx_clk
|
||||
set_interface_property if_rx_data dataBitsPerSymbol 64
|
||||
|
||||
add_interface if_sync conduit end
|
||||
set_interface_property if_sync associatedClock if_clk
|
||||
add_interface_port if_sync adc_sync_in sync_in Input 1
|
||||
add_interface_port if_sync adc_sync_out sync_out Output 1
|
||||
add_interface_port if_sync adc_raddr_in raddr_in Input 4
|
||||
add_interface_port if_sync adc_raddr_out raddr_out Output 4
|
||||
|
||||
# dma interface
|
||||
|
||||
ad_interface clock adc_clk output 1
|
||||
ad_interface reset adc_rst output 1 if_adc_clk
|
||||
|
||||
add_interface adc_ch conduit end
|
||||
add_interface_port adc_ch adc_enable enable Output 8
|
||||
add_interface_port adc_ch adc_valid valid Output 8
|
||||
add_interface_port adc_ch adc_data data Output 128
|
||||
|
||||
set_interface_property adc_ch associatedClock if_rx_clk
|
||||
set_interface_property adc_ch associatedReset none
|
||||
|
||||
ad_interface signal adc_dovf input 1 ovf
|
||||
|
||||
@@ -0,0 +1,216 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module axi_ad9671_if #(
|
||||
|
||||
parameter QUAD_OR_DUAL_N = 1,
|
||||
parameter ID = 0) (
|
||||
|
||||
// jesd interface
|
||||
// rx_clk is (line-rate/40)
|
||||
|
||||
input rx_clk,
|
||||
input [ 3:0] rx_sof,
|
||||
input [(64*QUAD_OR_DUAL_N)+63:0] rx_data,
|
||||
|
||||
// adc data output
|
||||
|
||||
output adc_clk,
|
||||
input adc_rst,
|
||||
output adc_valid,
|
||||
output reg [ 15:0] adc_data_a,
|
||||
output adc_or_a,
|
||||
output reg [ 15:0] adc_data_b,
|
||||
output adc_or_b,
|
||||
output reg [ 15:0] adc_data_c,
|
||||
output adc_or_c,
|
||||
output reg [ 15:0] adc_data_d,
|
||||
output adc_or_d,
|
||||
output reg [ 15:0] adc_data_e,
|
||||
output adc_or_e,
|
||||
output reg [ 15:0] adc_data_f,
|
||||
output adc_or_f,
|
||||
output reg [ 15:0] adc_data_g,
|
||||
output adc_or_g,
|
||||
output reg [ 15:0] adc_data_h,
|
||||
output adc_or_h,
|
||||
input [ 31:0] adc_start_code,
|
||||
input adc_sync_in,
|
||||
output adc_sync_out,
|
||||
input adc_sync,
|
||||
output reg adc_sync_status,
|
||||
output reg adc_status,
|
||||
input [ 3:0] adc_raddr_in,
|
||||
output reg [ 3:0] adc_raddr_out);
|
||||
|
||||
|
||||
// internal wires
|
||||
|
||||
wire [(2*QUAD_OR_DUAL_N)+1:0] rx_sof_s;
|
||||
wire [(64*QUAD_OR_DUAL_N)+63:0] rx_data_s;
|
||||
wire [127:0] adc_wdata;
|
||||
wire [127:0] adc_rdata;
|
||||
wire [ 15:0] adc_data_a_s;
|
||||
wire [ 15:0] adc_data_b_s;
|
||||
wire [ 15:0] adc_data_c_s;
|
||||
wire [ 15:0] adc_data_d_s;
|
||||
wire [ 15:0] adc_data_e_s;
|
||||
wire [ 15:0] adc_data_f_s;
|
||||
wire [ 15:0] adc_data_g_s;
|
||||
wire [ 15:0] adc_data_h_s;
|
||||
wire [ 3:0] adc_raddr_s;
|
||||
wire adc_sync_s;
|
||||
|
||||
// internal registers
|
||||
|
||||
reg int_valid = 'd0;
|
||||
reg [127:0] int_data = 'd0;
|
||||
reg rx_sof_d = 'd0;
|
||||
reg [ 3:0] adc_waddr = 'd0;
|
||||
|
||||
// adc clock & valid
|
||||
|
||||
assign adc_clk = rx_clk;
|
||||
assign adc_valid = int_valid;
|
||||
assign adc_sync_out = adc_sync;
|
||||
|
||||
assign adc_or_a = 'd0;
|
||||
assign adc_or_b = 'd0;
|
||||
assign adc_or_c = 'd0;
|
||||
assign adc_or_d = 'd0;
|
||||
assign adc_or_e = 'd0;
|
||||
assign adc_or_f = 'd0;
|
||||
assign adc_or_g = 'd0;
|
||||
assign adc_or_h = 'd0;
|
||||
|
||||
assign adc_data_a_s = {int_data[ 7: 0], int_data[ 15: 8]};
|
||||
assign adc_data_b_s = {int_data[ 23: 16], int_data[ 31: 24]};
|
||||
assign adc_data_c_s = {int_data[ 39: 32], int_data[ 47: 40]};
|
||||
assign adc_data_d_s = {int_data[ 55: 48], int_data[ 63: 56]};
|
||||
assign adc_data_e_s = {int_data[ 71: 64], int_data[ 79: 72]};
|
||||
assign adc_data_f_s = {int_data[ 87: 80], int_data[ 95: 88]};
|
||||
assign adc_data_g_s = {int_data[103: 96], int_data[111:104]};
|
||||
assign adc_data_h_s = {int_data[119:112], int_data[127:120]};
|
||||
|
||||
assign adc_wdata = {adc_data_h_s, adc_data_g_s, adc_data_f_s, adc_data_e_s,
|
||||
adc_data_d_s, adc_data_c_s, adc_data_b_s, adc_data_a_s};
|
||||
|
||||
assign adc_raddr_s = (ID == 0) ? adc_raddr_out : adc_raddr_in;
|
||||
assign adc_sync_s = (ID == 0) ? adc_sync_out : adc_sync_in;
|
||||
|
||||
always @(posedge rx_clk) begin
|
||||
adc_data_a <= adc_rdata[ 15: 0];
|
||||
adc_data_b <= adc_rdata[ 31: 16];
|
||||
adc_data_c <= adc_rdata[ 47: 32];
|
||||
adc_data_d <= adc_rdata[ 63: 48];
|
||||
adc_data_e <= adc_rdata[ 79: 64];
|
||||
adc_data_f <= adc_rdata[ 95: 80];
|
||||
adc_data_g <= adc_rdata[111: 96];
|
||||
adc_data_h <= adc_rdata[127:112];
|
||||
end
|
||||
|
||||
always @(posedge rx_clk) begin
|
||||
if (adc_rst == 1'b1) begin
|
||||
adc_waddr <= 4'h0;
|
||||
adc_raddr_out <= 4'h8;
|
||||
adc_sync_status <= 1'b0;
|
||||
end else begin
|
||||
if (adc_data_d_s == adc_start_code[15:0] && adc_sync_status == 1'b1) begin
|
||||
adc_sync_status <= 1'b0;
|
||||
end else if(adc_sync_s == 1'b1) begin
|
||||
adc_sync_status <= 1'b1;
|
||||
end
|
||||
if (adc_data_d_s == adc_start_code[15:0] && adc_sync_status == 1'b1) begin
|
||||
adc_waddr <= 4'h0;
|
||||
adc_raddr_out <= 4'h8;
|
||||
end else if (int_valid == 1'b1) begin
|
||||
adc_waddr <= adc_waddr + 1;
|
||||
adc_raddr_out <= adc_raddr_out + 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge rx_clk) begin
|
||||
if (QUAD_OR_DUAL_N == 1'b1) begin
|
||||
int_valid <= 1'b1;
|
||||
int_data <= rx_data_s;
|
||||
end else begin
|
||||
rx_sof_d <= &rx_sof_s;
|
||||
int_valid <= rx_sof_d;
|
||||
int_data[63:0] <= {rx_data_s[31: 0], int_data[ 63:32]};
|
||||
int_data[127:64] <= {rx_data_s[63:32], int_data[127:96]};
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge rx_clk) begin
|
||||
if (adc_rst == 1'b1) begin
|
||||
adc_status <= 1'b0;
|
||||
end else begin
|
||||
adc_status <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
ad_mem #(.ADDRESS_WIDTH(4), .DATA_WIDTH(128)) i_mem (
|
||||
.clka(rx_clk),
|
||||
.wea(int_valid),
|
||||
.addra(adc_waddr),
|
||||
.dina(adc_wdata),
|
||||
.clkb(rx_clk),
|
||||
.reb (1'b1),
|
||||
.addrb(adc_raddr_s),
|
||||
.doutb(adc_rdata));
|
||||
|
||||
// frame-alignment
|
||||
|
||||
genvar n;
|
||||
|
||||
generate
|
||||
for (n = 0; n < ((2*QUAD_OR_DUAL_N)+2); n = n + 1) begin: g_xcvr_if
|
||||
ad_xcvr_rx_if i_xcvr_if (
|
||||
.rx_clk (rx_clk),
|
||||
.rx_ip_sof (rx_sof),
|
||||
.rx_ip_data (rx_data[((n*32)+31):(n*32)]),
|
||||
.rx_sof (rx_sof_s[n]),
|
||||
.rx_data (rx_data_s[((n*32)+31):(n*32)]));
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
@@ -0,0 +1,42 @@
|
||||
# ip
|
||||
|
||||
source ../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
|
||||
adi_ip_create axi_ad9671
|
||||
adi_ip_files axi_ad9671 [list \
|
||||
"$ad_hdl_dir/library/common/ad_rst.v" \
|
||||
"$ad_hdl_dir/library/common/ad_pnmon.v" \
|
||||
"$ad_hdl_dir/library/common/ad_datafmt.v" \
|
||||
"$ad_hdl_dir/library/common/up_axi.v" \
|
||||
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
|
||||
"$ad_hdl_dir/library/common/up_xfer_status.v" \
|
||||
"$ad_hdl_dir/library/common/up_clock_mon.v" \
|
||||
"$ad_hdl_dir/library/common/up_adc_common.v" \
|
||||
"$ad_hdl_dir/library/common/up_adc_channel.v" \
|
||||
"$ad_hdl_dir/library/common/ad_mem.v" \
|
||||
"$ad_hdl_dir/library/common/ad_xcvr_rx_if.v" \
|
||||
"$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \
|
||||
"$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \
|
||||
"$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \
|
||||
"$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \
|
||||
"axi_ad9671_pnmon.v" \
|
||||
"axi_ad9671_channel.v" \
|
||||
"axi_ad9671_if.v" \
|
||||
"axi_ad9671.v" ]
|
||||
|
||||
adi_ip_properties axi_ad9671
|
||||
|
||||
adi_init_bd_tcl
|
||||
adi_ip_bd axi_ad9371 "bd/bd.tcl"
|
||||
|
||||
set_property driver_value 0 [ipx::get_ports *rx_valid* -of_objects [ipx::current_core]]
|
||||
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
|
||||
set_property driver_value 0 [ipx::get_ports *sync_in* -of_objects [ipx::current_core]]
|
||||
set_property driver_value 0 [ipx::get_ports *raddr_in* -of_objects [ipx::current_core]]
|
||||
|
||||
adi_add_auto_fpga_spec_params
|
||||
ipx::create_xgui_files [ipx::current_core]
|
||||
|
||||
ipx::save_core [ipx::current_core]
|
||||
|
||||
@@ -0,0 +1,181 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// PN monitors
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module axi_ad9671_pnmon (
|
||||
|
||||
// adc interface
|
||||
|
||||
input adc_clk,
|
||||
input adc_valid,
|
||||
input [15:0] adc_data,
|
||||
|
||||
// pn out of sync and error
|
||||
|
||||
output adc_pn_oos,
|
||||
output adc_pn_err,
|
||||
input [ 3:0] adc_pnseq_sel);
|
||||
|
||||
// internal registers
|
||||
|
||||
reg adc_pn_valid = 'd0;
|
||||
reg [31:0] adc_pn_data_in = 'd0;
|
||||
reg [31:0] adc_pn_data_pn = 'd0;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire adc_pn_valid_s;
|
||||
wire [31:0] adc_pn_data_pn_s;
|
||||
|
||||
// PN23 function
|
||||
|
||||
function [31:0] pn23;
|
||||
input [31:0] din;
|
||||
reg [31:0] dout;
|
||||
begin
|
||||
dout[31] = din[22] ^ din[17];
|
||||
dout[30] = din[21] ^ din[16];
|
||||
dout[29] = din[20] ^ din[15];
|
||||
dout[28] = din[19] ^ din[14];
|
||||
dout[27] = din[18] ^ din[13];
|
||||
dout[26] = din[17] ^ din[12];
|
||||
dout[25] = din[16] ^ din[11];
|
||||
dout[24] = din[15] ^ din[10];
|
||||
dout[23] = din[14] ^ din[ 9];
|
||||
dout[22] = din[13] ^ din[ 8];
|
||||
dout[21] = din[12] ^ din[ 7];
|
||||
dout[20] = din[11] ^ din[ 6];
|
||||
dout[19] = din[10] ^ din[ 5];
|
||||
dout[18] = din[ 9] ^ din[ 4];
|
||||
dout[17] = din[ 8] ^ din[ 3];
|
||||
dout[16] = din[ 7] ^ din[ 2];
|
||||
dout[15] = din[ 6] ^ din[ 1];
|
||||
dout[14] = din[ 5] ^ din[ 0];
|
||||
dout[13] = din[ 4] ^ din[22] ^ din[17];
|
||||
dout[12] = din[ 3] ^ din[21] ^ din[16];
|
||||
dout[11] = din[ 2] ^ din[20] ^ din[15];
|
||||
dout[10] = din[ 1] ^ din[19] ^ din[14];
|
||||
dout[ 9] = din[ 0] ^ din[18] ^ din[13];
|
||||
dout[ 8] = din[22] ^ din[12];
|
||||
dout[ 7] = din[21] ^ din[11];
|
||||
dout[ 6] = din[20] ^ din[10];
|
||||
dout[ 5] = din[19] ^ din[ 9];
|
||||
dout[ 4] = din[18] ^ din[ 8];
|
||||
dout[ 3] = din[17] ^ din[ 7];
|
||||
dout[ 2] = din[16] ^ din[ 6];
|
||||
dout[ 1] = din[15] ^ din[ 5];
|
||||
dout[ 0] = din[14] ^ din[ 4];
|
||||
pn23 = dout;
|
||||
end
|
||||
endfunction
|
||||
|
||||
// PN9 function
|
||||
|
||||
function [31:0] pn9;
|
||||
input [31:0] din;
|
||||
reg [31:0] dout;
|
||||
begin
|
||||
dout[31] = din[ 8] ^ din[ 4];
|
||||
dout[30] = din[ 7] ^ din[ 3];
|
||||
dout[29] = din[ 6] ^ din[ 2];
|
||||
dout[28] = din[ 5] ^ din[ 1];
|
||||
dout[27] = din[ 4] ^ din[ 0];
|
||||
dout[26] = din[ 3] ^ din[ 8] ^ din[ 4];
|
||||
dout[25] = din[ 2] ^ din[ 7] ^ din[ 3];
|
||||
dout[24] = din[ 1] ^ din[ 6] ^ din[ 2];
|
||||
dout[23] = din[ 0] ^ din[ 5] ^ din[ 1];
|
||||
dout[22] = din[ 8] ^ din[ 0];
|
||||
dout[21] = din[ 7] ^ din[ 8] ^ din[ 4];
|
||||
dout[20] = din[ 6] ^ din[ 7] ^ din[ 3];
|
||||
dout[19] = din[ 5] ^ din[ 6] ^ din[ 2];
|
||||
dout[18] = din[ 4] ^ din[ 5] ^ din[ 1];
|
||||
dout[17] = din[ 3] ^ din[ 4] ^ din[ 0];
|
||||
dout[16] = din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4];
|
||||
dout[15] = din[ 1] ^ din[ 2] ^ din[ 7] ^ din[ 3];
|
||||
dout[14] = din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 2];
|
||||
dout[13] = din[ 8] ^ din[ 0] ^ din[ 4] ^ din[ 5] ^ din[ 1];
|
||||
dout[12] = din[ 7] ^ din[ 8] ^ din[ 3] ^ din[ 0];
|
||||
dout[11] = din[ 6] ^ din[ 7] ^ din[ 2] ^ din[ 8] ^ din[ 4];
|
||||
dout[10] = din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 7] ^ din[ 3];
|
||||
dout[ 9] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6] ^ din[ 2];
|
||||
dout[ 8] = din[ 3] ^ din[ 8] ^ din[ 5] ^ din[ 1];
|
||||
dout[ 7] = din[ 2] ^ din[ 4] ^ din[ 7] ^ din[ 0];
|
||||
dout[ 6] = din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 8] ^ din[ 4];
|
||||
dout[ 5] = din[ 0] ^ din[ 2] ^ din[ 5] ^ din[ 7] ^ din[ 3];
|
||||
dout[ 4] = din[ 8] ^ din[ 1] ^ din[ 6] ^ din[ 2];
|
||||
dout[ 3] = din[ 7] ^ din[ 0] ^ din[ 5] ^ din[ 1];
|
||||
dout[ 2] = din[ 6] ^ din[ 8] ^ din[ 0];
|
||||
dout[ 1] = din[ 5] ^ din[ 7] ^ din[ 8] ^ din[ 4];
|
||||
dout[ 0] = din[ 4] ^ din[ 6] ^ din[ 7] ^ din[ 3];
|
||||
pn9 = dout;
|
||||
end
|
||||
endfunction
|
||||
|
||||
// pn sequence select
|
||||
|
||||
assign adc_pn_valid_s = adc_valid & adc_pn_valid;
|
||||
assign adc_pn_data_pn_s = (adc_pn_oos == 1'b1) ? adc_pn_data_in : adc_pn_data_pn;
|
||||
|
||||
always @(posedge adc_clk) begin
|
||||
if (adc_valid == 1'b1) begin
|
||||
adc_pn_valid <= ~adc_pn_valid;
|
||||
adc_pn_data_in <= {adc_pn_data_in[15:0], ~adc_data[15], adc_data[14:0]};
|
||||
end
|
||||
if (adc_pn_valid_s == 1'b1) begin
|
||||
if (adc_pnseq_sel == 4'd0) begin
|
||||
adc_pn_data_pn <= pn9(adc_pn_data_pn_s);
|
||||
end else begin
|
||||
adc_pn_data_pn <= pn23(adc_pn_data_pn_s);
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// pn oos & pn err
|
||||
|
||||
ad_pnmon #(.DATA_WIDTH(32)) i_pnmon (
|
||||
.adc_clk (adc_clk),
|
||||
.adc_valid_in (adc_pn_valid_s),
|
||||
.adc_data_in (adc_pn_data_in),
|
||||
.adc_data_pn (adc_pn_data_pn),
|
||||
.adc_pn_oos (adc_pn_oos),
|
||||
.adc_pn_err (adc_pn_err));
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
@@ -0,0 +1,47 @@
|
||||
# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!
|
||||
proc init {cellpath otherInfo} {
|
||||
set ip [get_bd_cells $cellpath]
|
||||
|
||||
bd::mark_propagate_only $ip " \
|
||||
DEV_PACKAGE \
|
||||
SPEED_GRADE \
|
||||
FPGA_FAMILY \
|
||||
FPGA_TECHNOLOGY"
|
||||
|
||||
adi_auto_assign_device_spec $cellpath
|
||||
}
|
||||
|
||||
# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)
|
||||
proc adi_auto_assign_device_spec {cellpath} {
|
||||
|
||||
set ip [get_bd_cells $cellpath]
|
||||
set ip_param_list [list_property $ip]
|
||||
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
|
||||
|
||||
set parent_dir "../"
|
||||
for {set x 1} {$x<=4} {incr x} {
|
||||
set linkname ${ip_path}${parent_dir}scripts/adi_xilinx_device_info_enc.tcl
|
||||
if { [file exists $linkname] } {
|
||||
source ${ip_path}${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl
|
||||
break
|
||||
}
|
||||
append parent_dir "../"
|
||||
}
|
||||
|
||||
# Find predefindes auto assignable parameters
|
||||
foreach i $auto_set_param_list {
|
||||
if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
|
||||
set val [adi_device_spec $cellpath $i]
|
||||
set_property CONFIG.$i $val $ip
|
||||
}
|
||||
}
|
||||
|
||||
# Find predefindes auto assignable/overwritable parameters
|
||||
foreach i $auto_set_param_list_overwritable {
|
||||
if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
|
||||
set val [adi_device_spec $cellpath $i]
|
||||
set_property CONFIG.$i $val $ip
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,2 @@
|
||||
CLEAN_TARGET += bd
|
||||
CLEAN_TARGET += temporary_case_dependencies.mk
|
||||
@@ -0,0 +1,103 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||
ipgui::add_param $IPINST -name "ID" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "QUAD_OR_DUAL_N" -parent ${Page_0}
|
||||
#Adding Group
|
||||
set FPGA_info [ipgui::add_group $IPINST -name "FPGA info" -parent ${Page_0}]
|
||||
ipgui::add_param $IPINST -name "FPGA_TECHNOLOGY" -parent ${FPGA_info} -widget comboBox
|
||||
ipgui::add_param $IPINST -name "FPGA_FAMILY" -parent ${FPGA_info} -widget comboBox
|
||||
ipgui::add_param $IPINST -name "SPEED_GRADE" -parent ${FPGA_info} -widget comboBox
|
||||
ipgui::add_param $IPINST -name "DEV_PACKAGE" -parent ${FPGA_info} -widget comboBox
|
||||
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } {
|
||||
# Procedure called to update DEV_PACKAGE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } {
|
||||
# Procedure called to validate DEV_PACKAGE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } {
|
||||
# Procedure called to update FPGA_FAMILY when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } {
|
||||
# Procedure called to validate FPGA_FAMILY
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } {
|
||||
# Procedure called to update FPGA_TECHNOLOGY when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } {
|
||||
# Procedure called to validate FPGA_TECHNOLOGY
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } {
|
||||
# Procedure called to update ID when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } {
|
||||
# Procedure called to validate ID
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.QUAD_OR_DUAL_N { PARAM_VALUE.QUAD_OR_DUAL_N } {
|
||||
# Procedure called to update QUAD_OR_DUAL_N when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.QUAD_OR_DUAL_N { PARAM_VALUE.QUAD_OR_DUAL_N } {
|
||||
# Procedure called to validate QUAD_OR_DUAL_N
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } {
|
||||
# Procedure called to update SPEED_GRADE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } {
|
||||
# Procedure called to validate SPEED_GRADE
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.FPGA_TECHNOLOGY { MODELPARAM_VALUE.FPGA_TECHNOLOGY PARAM_VALUE.FPGA_TECHNOLOGY } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.FPGA_TECHNOLOGY}] ${MODELPARAM_VALUE.FPGA_TECHNOLOGY}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.FPGA_FAMILY { MODELPARAM_VALUE.FPGA_FAMILY PARAM_VALUE.FPGA_FAMILY } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.FPGA_FAMILY}] ${MODELPARAM_VALUE.FPGA_FAMILY}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.SPEED_GRADE { MODELPARAM_VALUE.SPEED_GRADE PARAM_VALUE.SPEED_GRADE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.SPEED_GRADE}] ${MODELPARAM_VALUE.SPEED_GRADE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DEV_PACKAGE { MODELPARAM_VALUE.DEV_PACKAGE PARAM_VALUE.DEV_PACKAGE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DEV_PACKAGE}] ${MODELPARAM_VALUE.DEV_PACKAGE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.QUAD_OR_DUAL_N { MODELPARAM_VALUE.QUAD_OR_DUAL_N PARAM_VALUE.QUAD_OR_DUAL_N } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.QUAD_OR_DUAL_N}] ${MODELPARAM_VALUE.QUAD_OR_DUAL_N}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user