Archived
first commit after restructuring
This commit is contained in:
@@ -0,0 +1,45 @@
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####################################################################################
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## Copyright 2018(c) Analog Devices, Inc.
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## Auto-generated, do not modify!
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||||
####################################################################################
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LIBRARY_NAME := axi_ad9963
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||||
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GENERIC_DEPS += ../common/ad_datafmt.v
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GENERIC_DEPS += ../common/ad_dds.v
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GENERIC_DEPS += ../common/ad_dds_1.v
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||||
GENERIC_DEPS += ../common/ad_dds_2.v
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||||
GENERIC_DEPS += ../common/ad_dds_cordic_pipe.v
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||||
GENERIC_DEPS += ../common/ad_dds_sine.v
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GENERIC_DEPS += ../common/ad_dds_sine_cordic.v
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||||
GENERIC_DEPS += ../common/ad_iqcor.v
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GENERIC_DEPS += ../common/ad_pnmon.v
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||||
GENERIC_DEPS += ../common/ad_rst.v
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GENERIC_DEPS += ../common/up_adc_channel.v
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GENERIC_DEPS += ../common/up_adc_common.v
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GENERIC_DEPS += ../common/up_axi.v
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GENERIC_DEPS += ../common/up_clock_mon.v
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GENERIC_DEPS += ../common/up_dac_channel.v
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GENERIC_DEPS += ../common/up_dac_common.v
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GENERIC_DEPS += ../common/up_delay_cntrl.v
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GENERIC_DEPS += ../common/up_xfer_cntrl.v
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GENERIC_DEPS += ../common/up_xfer_status.v
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GENERIC_DEPS += axi_ad9963.v
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GENERIC_DEPS += axi_ad9963_if.v
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GENERIC_DEPS += axi_ad9963_rx.v
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GENERIC_DEPS += axi_ad9963_rx_channel.v
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GENERIC_DEPS += axi_ad9963_rx_pnmon.v
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||||
GENERIC_DEPS += axi_ad9963_tx.v
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GENERIC_DEPS += axi_ad9963_tx_channel.v
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XILINX_DEPS += ../xilinx/common/ad_data_in.v
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XILINX_DEPS += ../xilinx/common/ad_dcfilter.v
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XILINX_DEPS += ../xilinx/common/ad_mul.v
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XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc
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XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc
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XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
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XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc
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XILINX_DEPS += axi_ad9963_constr.xdc
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XILINX_DEPS += axi_ad9963_ip.tcl
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include ../scripts/library.mk
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@@ -0,0 +1,3 @@
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version:1
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6d6f64655f636f756e7465727c42617463684d6f6465:1
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eof:
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@@ -0,0 +1,6 @@
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<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<labtools version="1" minor="0"/>
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@@ -0,0 +1,342 @@
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// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
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||||
|
||||
module axi_ad9963 #(
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||||
|
||||
// parameters
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||||
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||||
parameter ID = 0,
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||||
parameter FPGA_TECHNOLOGY = 0,
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parameter FPGA_FAMILY = 0,
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parameter SPEED_GRADE = 0,
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||||
parameter DEV_PACKAGE = 0,
|
||||
parameter ADC_IODELAY_ENABLE = 0,
|
||||
parameter IO_DELAY_GROUP = "dev_if_delay_group",
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||||
parameter IODELAY_ENABLE = 0,
|
||||
parameter DAC_DDS_TYPE = 1,
|
||||
parameter DAC_DDS_CORDIC_DW = 14,
|
||||
parameter DAC_DDS_CORDIC_PHASE_DW = 13,
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||||
parameter DAC_DATAPATH_DISABLE = 0,
|
||||
parameter ADC_USERPORTS_DISABLE = 0,
|
||||
parameter ADC_DATAFORMAT_DISABLE = 0,
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parameter ADC_DCFILTER_DISABLE = 0,
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parameter ADC_IQCORRECTION_DISABLE = 0,
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parameter ADC_SCALECORRECTION_ONLY = 1,
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parameter DELAY_REFCLK_FREQUENCY = 200) (
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// physical interface (receive)
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input trx_clk,
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input trx_iq,
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input [11:0] trx_data,
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// physical interface (transmit)
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||||
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input tx_clk,
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output tx_iq,
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output [11:0] tx_data,
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||||
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// transmit master/slave
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input dac_sync_in,
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output dac_sync_out,
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// delay clock
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input delay_clk,
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// master interface
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output adc_clk,
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output dac_clk,
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output adc_rst,
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output dac_rst,
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// dma interface
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output adc_enable_i,
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output adc_valid_i,
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output [15:0] adc_data_i,
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output adc_enable_q,
|
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output adc_valid_q,
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||||
output [15:0] adc_data_q,
|
||||
input adc_dovf,
|
||||
|
||||
output dac_enable_i,
|
||||
output dac_valid_i,
|
||||
input [15:0] dac_data_i,
|
||||
input dma_valid_i,
|
||||
output dac_enable_q,
|
||||
output dac_valid_q,
|
||||
input [15:0] dac_data_q,
|
||||
input dma_valid_q,
|
||||
input dac_dunf,
|
||||
|
||||
input hold_last_sample,
|
||||
|
||||
// axi interface
|
||||
|
||||
input s_axi_aclk,
|
||||
input s_axi_aresetn,
|
||||
input s_axi_awvalid,
|
||||
input [15:0] s_axi_awaddr,
|
||||
input [ 2:0] s_axi_awprot,
|
||||
output s_axi_awready,
|
||||
input s_axi_wvalid,
|
||||
input [31:0] s_axi_wdata,
|
||||
input [ 3:0] s_axi_wstrb,
|
||||
output s_axi_wready,
|
||||
output s_axi_bvalid,
|
||||
output [ 1:0] s_axi_bresp,
|
||||
input s_axi_bready,
|
||||
input s_axi_arvalid,
|
||||
input [15:0] s_axi_araddr,
|
||||
input [ 2:0] s_axi_arprot,
|
||||
output s_axi_arready,
|
||||
output s_axi_rvalid,
|
||||
output [31:0] s_axi_rdata,
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||||
output [ 1:0] s_axi_rresp,
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||||
input s_axi_rready);
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||||
// internal registers
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||||
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reg up_wack = 'd0;
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reg up_rack = 'd0;
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reg [31:0] up_rdata = 'd0;
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// internal clocks and resets
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||||
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wire up_clk;
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wire up_rstn;
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wire delay_rst;
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// internal signals
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||||
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wire adc_valid_s;
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wire [23:0] adc_data_s;
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wire adc_status_s;
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||||
wire [23:0] dac_data_s;
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wire [12:0] up_adc_dld_s;
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wire [64:0] up_adc_dwdata_s;
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wire [64:0] up_adc_drdata_s;
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wire delay_locked_s;
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wire up_wreq_s;
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wire [13:0] up_waddr_s;
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wire [31:0] up_wdata_s;
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wire up_wack_rx_s;
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wire up_wack_tx_s;
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wire up_rreq_s;
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wire [13:0] up_raddr_s;
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wire [31:0] up_rdata_rx_s;
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wire up_rack_rx_s;
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wire [31:0] up_rdata_tx_s;
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wire up_rack_tx_s;
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wire up_adc_ce;
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wire up_dac_ce;
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wire valid_out_q_s;
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wire valid_out_i_s;
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// signal name changes
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assign up_clk = s_axi_aclk;
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assign up_rstn = s_axi_aresetn;
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// processor read interface
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always @(*) begin
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up_wack = up_wack_rx_s | up_wack_tx_s;
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up_rack = up_rack_rx_s | up_rack_tx_s;
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up_rdata = up_rdata_rx_s | up_rdata_tx_s;
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end
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// device interface
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axi_ad9963_if #(
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.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
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.ADC_IODELAY_ENABLE (ADC_IODELAY_ENABLE),
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.IO_DELAY_GROUP (IO_DELAY_GROUP),
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.DELAY_REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
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||||
i_dev_if (
|
||||
.trx_clk (trx_clk),
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||||
.trx_iq (trx_iq),
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.trx_data (trx_data),
|
||||
.tx_clk (tx_clk),
|
||||
.tx_iq (tx_iq),
|
||||
.tx_data (tx_data),
|
||||
.adc_clk (adc_clk),
|
||||
.adc_rst (adc_rst),
|
||||
.dac_clk (dac_clk),
|
||||
.dac_rst (dac_rst),
|
||||
.adc_valid (adc_valid_s),
|
||||
.adc_data (adc_data_s),
|
||||
.adc_status (adc_status_s),
|
||||
.up_adc_ce(up_adc_ce),
|
||||
.dac_data (dac_data_s),
|
||||
.out_valid_q (valid_out_q_s),
|
||||
.out_valid_i (valid_out_i_s),
|
||||
.up_dac_ce(up_dac_ce),
|
||||
.tx_sample_hold (hold_last_sample),
|
||||
.up_clk (up_clk),
|
||||
.up_adc_dld (up_adc_dld_s),
|
||||
.up_adc_dwdata (up_adc_dwdata_s),
|
||||
.up_adc_drdata (up_adc_drdata_s),
|
||||
.delay_clk (delay_clk),
|
||||
.delay_rst (delay_rst),
|
||||
.delay_locked (delay_locked_s));
|
||||
|
||||
// receive
|
||||
|
||||
axi_ad9963_rx #(
|
||||
.ID (ID),
|
||||
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
|
||||
.FPGA_FAMILY (FPGA_FAMILY),
|
||||
.SPEED_GRADE (SPEED_GRADE),
|
||||
.DEV_PACKAGE (DEV_PACKAGE),
|
||||
.USERPORTS_DISABLE (ADC_USERPORTS_DISABLE),
|
||||
.DATAFORMAT_DISABLE (ADC_DATAFORMAT_DISABLE),
|
||||
.DCFILTER_DISABLE (ADC_DCFILTER_DISABLE),
|
||||
.IQCORRECTION_DISABLE (ADC_IQCORRECTION_DISABLE),
|
||||
.SCALECORRECTION_ONLY (ADC_SCALECORRECTION_ONLY),
|
||||
.IODELAY_ENABLE (ADC_IODELAY_ENABLE)
|
||||
) i_rx (
|
||||
.adc_rst (adc_rst),
|
||||
.adc_clk (adc_clk),
|
||||
.adc_valid (adc_valid_s),
|
||||
.adc_data (adc_data_s),
|
||||
.adc_status (adc_status_s),
|
||||
.up_adc_ce(up_adc_ce),
|
||||
.up_dld (up_adc_dld_s),
|
||||
.up_dwdata (up_adc_dwdata_s),
|
||||
.up_drdata (up_adc_drdata_s),
|
||||
.delay_clk (delay_clk),
|
||||
.delay_rst (delay_rst),
|
||||
.delay_locked (delay_locked_s),
|
||||
.adc_enable_i (adc_enable_i),
|
||||
.adc_valid_i (adc_valid_i),
|
||||
.adc_data_i (adc_data_i),
|
||||
.adc_enable_q (adc_enable_q),
|
||||
.adc_valid_q (adc_valid_q),
|
||||
.adc_data_q (adc_data_q),
|
||||
.adc_dovf (adc_dovf),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq_s),
|
||||
.up_waddr (up_waddr_s),
|
||||
.up_wdata (up_wdata_s),
|
||||
.up_wack (up_wack_rx_s),
|
||||
.up_rreq (up_rreq_s),
|
||||
.up_raddr (up_raddr_s),
|
||||
.up_rdata (up_rdata_rx_s),
|
||||
.up_rack (up_rack_rx_s));
|
||||
|
||||
// transmit
|
||||
|
||||
axi_ad9963_tx #(
|
||||
.ID (ID),
|
||||
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
|
||||
.FPGA_FAMILY (FPGA_FAMILY),
|
||||
.SPEED_GRADE (SPEED_GRADE),
|
||||
.DEV_PACKAGE (DEV_PACKAGE),
|
||||
.DAC_DDS_TYPE (DAC_DDS_TYPE),
|
||||
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
|
||||
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
|
||||
.DATAPATH_DISABLE (DAC_DATAPATH_DISABLE))
|
||||
i_tx (
|
||||
.dac_clk (dac_clk),
|
||||
.dac_rst (dac_rst),
|
||||
.dac_data (dac_data_s),
|
||||
.adc_data (adc_data_s),
|
||||
.dac_sync_in (dac_sync_in),
|
||||
.dac_sync_out (dac_sync_out),
|
||||
.dac_enable_i (dac_enable_i),
|
||||
.dac_valid_i (dac_valid_i),
|
||||
.dac_data_i (dac_data_i),
|
||||
.dma_valid_i (dma_valid_i),
|
||||
.out_valid_i (valid_out_i_s),
|
||||
.dac_enable_q (dac_enable_q),
|
||||
.dac_valid_q (dac_valid_q),
|
||||
.dac_data_q (dac_data_q),
|
||||
.dma_valid_q (dma_valid_q),
|
||||
.out_valid_q (valid_out_q_s),
|
||||
.dac_dunf(dac_dunf),
|
||||
.up_dac_ce(up_dac_ce),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq_s),
|
||||
.up_waddr (up_waddr_s),
|
||||
.up_wdata (up_wdata_s),
|
||||
.up_wack (up_wack_tx_s),
|
||||
.up_rreq (up_rreq_s),
|
||||
.up_raddr (up_raddr_s),
|
||||
.up_rdata (up_rdata_tx_s),
|
||||
.up_rack (up_rack_tx_s));
|
||||
|
||||
// axi interface
|
||||
|
||||
up_axi i_up_axi (
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_axi_awvalid (s_axi_awvalid),
|
||||
.up_axi_awaddr (s_axi_awaddr),
|
||||
.up_axi_awready (s_axi_awready),
|
||||
.up_axi_wvalid (s_axi_wvalid),
|
||||
.up_axi_wdata (s_axi_wdata),
|
||||
.up_axi_wstrb (s_axi_wstrb),
|
||||
.up_axi_wready (s_axi_wready),
|
||||
.up_axi_bvalid (s_axi_bvalid),
|
||||
.up_axi_bresp (s_axi_bresp),
|
||||
.up_axi_bready (s_axi_bready),
|
||||
.up_axi_arvalid (s_axi_arvalid),
|
||||
.up_axi_araddr (s_axi_araddr),
|
||||
.up_axi_arready (s_axi_arready),
|
||||
.up_axi_rvalid (s_axi_rvalid),
|
||||
.up_axi_rresp (s_axi_rresp),
|
||||
.up_axi_rdata (s_axi_rdata),
|
||||
.up_axi_rready (s_axi_rready),
|
||||
.up_wreq (up_wreq_s),
|
||||
.up_waddr (up_waddr_s),
|
||||
.up_wdata (up_wdata_s),
|
||||
.up_wack (up_wack),
|
||||
.up_rreq (up_rreq_s),
|
||||
.up_raddr (up_raddr_s),
|
||||
.up_rdata (up_rdata),
|
||||
.up_rack (up_rack));
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
@@ -0,0 +1,609 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Version="7" Minor="40" Path="/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9963/axi_ad9963.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="4dca1da1384f4f0c8b0d249546b05092"/>
|
||||
<Option Name="Part" Val="xc7vx485tffg1157-1"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
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|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val=""/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="11"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1343"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="2"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1306"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="3"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="ERROR"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1276"/>
|
||||
<MsgAttr Name="Severity" Val="CRITICAL WARNING"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="4"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-3656"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="5"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-4623"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="6"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-459"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="7"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Synth 8-3331"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="8"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Designutils 20-3303"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="9"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="HDPYFinalizeIO"/>
|
||||
</MsgRule>
|
||||
<Board/>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
<BootPmcSettings Version="1" Minor="0">
|
||||
<Parameters>
|
||||
<Parameter Name="PMC_CDO.ATTRS.LOADADDR" Value="" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_FB_CLK" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_FREQ" Value="300" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_BUS_WIDTH" Value="x1" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_DATA_MODE" Value="Single" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_FREQ" Value="200" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_SLOT_TYPE" Value="SD 2.0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_FREQ" Value="200" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_SLOT_TYPE" Value="SD 2.0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSPI_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSPI_FREQ" Value="300" Type="string"/>
|
||||
<Parameter Name="BOOT.USB_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SMAP_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SMAP_DATA_WIDTH" Value="32 Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSC_FREQ" Value="33.333" Type="string"/>
|
||||
<Parameter Name="BOOT.SECONDARY.PCIE_ENABLE" Value="0" Type="string"/>
|
||||
</Parameters>
|
||||
</BootPmcSettings>
|
||||
</Project>
|
||||
@@ -0,0 +1 @@
|
||||
set_false_path -from [get_cells -hier -filter {name =~ *up_*clk_enb* && IS_SEQUENTIAL}] -to [get_pins -hier -filter {name =~ *bufgctrl*/S0}]
|
||||
@@ -0,0 +1,275 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module axi_ad9963_if #(
|
||||
|
||||
// this parameter controls the buffer type based on the target device.
|
||||
|
||||
parameter FPGA_TECHNOLOGY = 0,
|
||||
parameter ADC_IODELAY_ENABLE = 0,
|
||||
parameter IO_DELAY_GROUP = "dev_if_delay_group",
|
||||
parameter DELAY_REFCLK_FREQUENCY = 200) (
|
||||
|
||||
// physical interface (receive)
|
||||
|
||||
input trx_clk,
|
||||
input trx_iq,
|
||||
input [11:0] trx_data,
|
||||
|
||||
// physical interface (transmit)
|
||||
|
||||
input tx_clk,
|
||||
output tx_iq,
|
||||
output [11:0] tx_data,
|
||||
|
||||
// clock (common to both receive and transmit)
|
||||
|
||||
input adc_rst,
|
||||
input dac_rst,
|
||||
output adc_clk,
|
||||
output dac_clk,
|
||||
|
||||
// receive data path interface
|
||||
|
||||
output reg adc_valid,
|
||||
output reg [23:0] adc_data,
|
||||
output reg adc_status,
|
||||
input up_adc_ce,
|
||||
|
||||
// transmit data path interface
|
||||
|
||||
input out_valid_q,
|
||||
input out_valid_i,
|
||||
input [23:0] dac_data,
|
||||
input up_dac_ce,
|
||||
input tx_sample_hold,
|
||||
|
||||
// delay interface
|
||||
|
||||
input up_clk,
|
||||
input [12:0] up_adc_dld,
|
||||
input [64:0] up_adc_dwdata,
|
||||
output [64:0] up_adc_drdata,
|
||||
input delay_clk,
|
||||
input delay_rst,
|
||||
output delay_locked);
|
||||
|
||||
// internal registers
|
||||
|
||||
reg [11:0] rx_data_p = 0;
|
||||
reg [11:0] tx_data_p = 'd0;
|
||||
reg [11:0] tx_data_n = 'd0;
|
||||
reg [23:0] constant_sample = 'd0;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire [11:0] rx_data_p_s;
|
||||
wire [11:0] rx_data_n_s;
|
||||
wire rx_iq_p_s;
|
||||
wire rx_iq_n_s;
|
||||
|
||||
wire div_clk;
|
||||
|
||||
genvar l_inst;
|
||||
|
||||
always @(posedge adc_clk) begin
|
||||
if( rx_iq_p_s == 1'b1) begin
|
||||
adc_data <= {rx_data_n_s, rx_data_p_s} ; // data[11:00] I
|
||||
adc_valid <= 1'b1; // data[23:12] Q
|
||||
end else begin
|
||||
rx_data_p <= rx_data_p_s; // if this happens it means that risedge data is sampled on falledge
|
||||
adc_data <= {rx_data_p, rx_data_n_s}; // so we take current N data with previous P data
|
||||
adc_valid <= 1'b1; // in order to have data sampled at the same instance sent to the DMA
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge dac_clk) begin
|
||||
if (dac_rst == 1'b1) begin
|
||||
tx_data_p <= 24'd0;
|
||||
tx_data_n <= 24'd0;
|
||||
constant_sample <= 24'd0;
|
||||
end else begin
|
||||
if(out_valid_i == 1'b1) begin
|
||||
tx_data_p <= dac_data[11: 0];
|
||||
constant_sample[11: 0] <= tx_sample_hold ? dac_data[11: 0] : 12'd0;
|
||||
end else begin
|
||||
tx_data_p <= constant_sample[11:0] ;
|
||||
end
|
||||
if(out_valid_q == 1'b1) begin
|
||||
tx_data_n <= dac_data[23:12];
|
||||
constant_sample[23:12] <= tx_sample_hold ? dac_data[23:12] : 12'd0;
|
||||
end else begin
|
||||
tx_data_n <= constant_sample[23:12];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge adc_clk) begin
|
||||
if (adc_rst == 1'b1) begin
|
||||
adc_status <= 1'b0;
|
||||
end else begin
|
||||
adc_status <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
// device clock interface (receive clock)
|
||||
|
||||
BUFGCTRL #(
|
||||
.INIT_OUT(0),
|
||||
.PRESELECT_I0("FALSE"),
|
||||
.PRESELECT_I1("FALSE")
|
||||
)
|
||||
bufgctrl_adc (
|
||||
.O(adc_clk),
|
||||
.CE0(1'b1),
|
||||
.CE1(1'b0),
|
||||
.I0(trx_clk),
|
||||
.I1(1'b0),
|
||||
.IGNORE0(1'b0),
|
||||
.IGNORE1(1'b0),
|
||||
.S0(up_adc_ce),
|
||||
.S1(1'b0)
|
||||
);
|
||||
|
||||
// receive data interface, ibuf -> idelay -> iddr
|
||||
|
||||
generate
|
||||
for (l_inst = 0; l_inst <= 11; l_inst = l_inst + 1) begin: g_rx_data
|
||||
ad_data_in #(
|
||||
.SINGLE_ENDED (1),
|
||||
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
|
||||
.IODELAY_ENABLE (ADC_IODELAY_ENABLE),
|
||||
.IODELAY_CTRL (0),
|
||||
.IODELAY_GROUP (IO_DELAY_GROUP),
|
||||
.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
|
||||
i_rx_data (
|
||||
.rx_clk (adc_clk),
|
||||
.rx_data_in_p (trx_data[l_inst]),
|
||||
.rx_data_in_n (1'b0),
|
||||
.rx_data_p (rx_data_p_s[l_inst]),
|
||||
.rx_data_n (rx_data_n_s[l_inst]),
|
||||
.up_clk (up_clk),
|
||||
.up_dld (up_adc_dld[l_inst]),
|
||||
.up_dwdata (up_adc_dwdata[((l_inst*5)+4):(l_inst*5)]),
|
||||
.up_drdata (up_adc_drdata[((l_inst*5)+4):(l_inst*5)]),
|
||||
.delay_clk (delay_clk),
|
||||
.delay_rst (delay_rst),
|
||||
.delay_locked ());
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// receive iq interface, ibuf -> idelay -> iddr
|
||||
|
||||
ad_data_in #(
|
||||
.SINGLE_ENDED (1),
|
||||
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
|
||||
.IODELAY_ENABLE (ADC_IODELAY_ENABLE),
|
||||
.IODELAY_CTRL (1),
|
||||
.IODELAY_GROUP (IO_DELAY_GROUP))
|
||||
i_rx_iq (
|
||||
.rx_clk (adc_clk),
|
||||
.rx_data_in_p (trx_iq),
|
||||
.rx_data_in_n (1'b0),
|
||||
.rx_data_p (rx_iq_p_s),
|
||||
.rx_data_n (rx_iq_n_s),
|
||||
.up_clk (up_clk),
|
||||
.up_dld (up_adc_dld[12]),
|
||||
.up_dwdata (up_adc_dwdata[64:60]),
|
||||
.up_drdata (up_adc_drdata[64:60]),
|
||||
.delay_clk (delay_clk),
|
||||
.delay_rst (delay_rst),
|
||||
.delay_locked (delay_locked));
|
||||
|
||||
// transmit data interface
|
||||
|
||||
BUFR #(.BUFR_DIVIDE(2)) i_div_clk_buf (
|
||||
.CLR (1'b0),
|
||||
.CE (1'b1),
|
||||
.I (tx_clk),
|
||||
.O (div_clk));
|
||||
|
||||
BUFGCTRL #(
|
||||
.INIT_OUT(0),
|
||||
.PRESELECT_I0("FALSE"),
|
||||
.PRESELECT_I1("FALSE")
|
||||
)
|
||||
bufgctrl_dac (
|
||||
.O(dac_clk),
|
||||
.CE0(1'b1),
|
||||
.CE1(1'b0),
|
||||
.I0(div_clk),
|
||||
.I1(1'b0),
|
||||
.IGNORE0(1'b0),
|
||||
.IGNORE1(1'b0),
|
||||
.S0(up_dac_ce),
|
||||
.S1(1'b0)
|
||||
);
|
||||
|
||||
generate
|
||||
for (l_inst = 0; l_inst <= 11; l_inst = l_inst + 1) begin: g_tx_data
|
||||
ODDR #(
|
||||
.DDR_CLK_EDGE ("SAME_EDGE"),
|
||||
.INIT (1'b0),
|
||||
.SRTYPE ("SYNC"))
|
||||
i_tx_data_oddr (
|
||||
.CE (1'b1),
|
||||
.R (dac_rst),
|
||||
.S (1'b0),
|
||||
.C (dac_clk),
|
||||
.D1 (tx_data_p[l_inst]),
|
||||
.D2 (tx_data_n[l_inst]),
|
||||
.Q (tx_data[l_inst]));
|
||||
end
|
||||
endgenerate
|
||||
|
||||
ODDR #(
|
||||
.DDR_CLK_EDGE ("SAME_EDGE"),
|
||||
.INIT (1'b0),
|
||||
.SRTYPE ("SYNC"))
|
||||
i_tx_data_oddr (
|
||||
.CE (1'b1),
|
||||
.R (dac_rst),
|
||||
.S (1'b0),
|
||||
.C (dac_clk),
|
||||
.D1 (1'b1),
|
||||
.D2 (1'b0),
|
||||
.Q (tx_iq));
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
@@ -0,0 +1,69 @@
|
||||
# ip
|
||||
|
||||
source ../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
|
||||
adi_ip_create axi_ad9963
|
||||
adi_ip_files axi_ad9963 [list \
|
||||
"$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \
|
||||
"$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \
|
||||
"$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \
|
||||
"$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \
|
||||
"$ad_hdl_dir/library/common/ad_rst.v" \
|
||||
"$ad_hdl_dir/library/xilinx/common/ad_data_in.v" \
|
||||
"$ad_hdl_dir/library/xilinx/common/ad_dcfilter.v" \
|
||||
"$ad_hdl_dir/library/xilinx/common/ad_mul.v" \
|
||||
"$ad_hdl_dir/library/common/ad_pnmon.v" \
|
||||
"$ad_hdl_dir/library/common/ad_dds_cordic_pipe.v" \
|
||||
"$ad_hdl_dir/library/common/ad_dds_sine_cordic.v" \
|
||||
"$ad_hdl_dir/library/common/ad_dds_sine.v" \
|
||||
"$ad_hdl_dir/library/common/ad_dds_2.v" \
|
||||
"$ad_hdl_dir/library/common/ad_dds_1.v" \
|
||||
"$ad_hdl_dir/library/common/ad_dds.v" \
|
||||
"$ad_hdl_dir/library/common/ad_datafmt.v" \
|
||||
"$ad_hdl_dir/library/common/ad_iqcor.v" \
|
||||
"$ad_hdl_dir/library/common/up_axi.v" \
|
||||
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
|
||||
"$ad_hdl_dir/library/common/up_xfer_status.v" \
|
||||
"$ad_hdl_dir/library/common/up_clock_mon.v" \
|
||||
"$ad_hdl_dir/library/common/up_delay_cntrl.v" \
|
||||
"$ad_hdl_dir/library/common/up_adc_common.v" \
|
||||
"$ad_hdl_dir/library/common/up_adc_channel.v" \
|
||||
"$ad_hdl_dir/library/common/up_dac_common.v" \
|
||||
"$ad_hdl_dir/library/common/up_dac_channel.v" \
|
||||
"axi_ad9963_constr.xdc" \
|
||||
"axi_ad9963_if.v" \
|
||||
"axi_ad9963_rx_pnmon.v" \
|
||||
"axi_ad9963_rx_channel.v" \
|
||||
"axi_ad9963_rx.v" \
|
||||
"axi_ad9963_tx_channel.v" \
|
||||
"axi_ad9963_tx.v" \
|
||||
"axi_ad9963.v" ]
|
||||
|
||||
adi_ip_properties axi_ad9963
|
||||
|
||||
adi_init_bd_tcl
|
||||
adi_ip_bd axi_ad9963 "bd/bd.tcl"
|
||||
|
||||
set_property driver_value 0 [ipx::get_ports *dac_sync_in* -of_objects [ipx::current_core]]
|
||||
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
|
||||
set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
|
||||
|
||||
adi_set_ports_dependency "delay_clk" \
|
||||
"(spirit:decode(id('MODELPARAM_VALUE.ADC_IODELAY_ENABLE')) = 1)" 0
|
||||
|
||||
ipx::infer_bus_interface trx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
ipx::infer_bus_interface tx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
ipx::infer_bus_interface delay_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
|
||||
ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
ipx::infer_bus_interface adc_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
|
||||
|
||||
ipx::infer_bus_interface dac_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
ipx::infer_bus_interface dac_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
|
||||
|
||||
adi_add_auto_fpga_spec_params
|
||||
ipx::create_xgui_files [ipx::current_core]
|
||||
|
||||
ipx::save_core [ipx::current_core]
|
||||
|
||||
@@ -0,0 +1,308 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module axi_ad9963_rx #(
|
||||
|
||||
// parameters
|
||||
|
||||
parameter USERPORTS_DISABLE = 0,
|
||||
parameter DATAFORMAT_DISABLE = 0,
|
||||
parameter DCFILTER_DISABLE = 0,
|
||||
parameter IQCORRECTION_DISABLE = 0,
|
||||
parameter SCALECORRECTION_ONLY = 1,
|
||||
parameter IODELAY_ENABLE = 0,
|
||||
parameter ID = 0,
|
||||
parameter FPGA_TECHNOLOGY = 0,
|
||||
parameter FPGA_FAMILY = 0,
|
||||
parameter SPEED_GRADE = 0,
|
||||
parameter DEV_PACKAGE = 0) (
|
||||
|
||||
// adc interface
|
||||
|
||||
output adc_rst,
|
||||
input adc_clk,
|
||||
input adc_valid,
|
||||
input [23:0] adc_data,
|
||||
input adc_status,
|
||||
|
||||
// delay interface
|
||||
|
||||
output [12:0] up_dld,
|
||||
output [64:0] up_dwdata,
|
||||
input [64:0] up_drdata,
|
||||
input delay_clk,
|
||||
output delay_rst,
|
||||
input delay_locked,
|
||||
|
||||
// dma interface
|
||||
|
||||
output adc_enable_i,
|
||||
output adc_valid_i,
|
||||
output [15:0] adc_data_i,
|
||||
output adc_enable_q,
|
||||
output adc_valid_q,
|
||||
output [15:0] adc_data_q,
|
||||
input adc_dovf,
|
||||
|
||||
output up_adc_ce,
|
||||
|
||||
// processor interface
|
||||
|
||||
input up_rstn,
|
||||
input up_clk,
|
||||
input up_wreq,
|
||||
input [13:0] up_waddr,
|
||||
input [31:0] up_wdata,
|
||||
output reg up_wack,
|
||||
input up_rreq,
|
||||
input [13:0] up_raddr,
|
||||
output reg [31:0] up_rdata,
|
||||
output reg up_rack);
|
||||
|
||||
// configuration settings
|
||||
|
||||
localparam CONFIG = (SCALECORRECTION_ONLY * 512) +
|
||||
(0 * 16) +
|
||||
(USERPORTS_DISABLE * 8) +
|
||||
(DATAFORMAT_DISABLE * 4) +
|
||||
(DCFILTER_DISABLE * 2) +
|
||||
(IQCORRECTION_DISABLE * 1);
|
||||
|
||||
// internal registers
|
||||
|
||||
reg up_status_pn_err = 'd0;
|
||||
reg up_status_pn_oos = 'd0;
|
||||
reg up_status_or = 'd0;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire [15:0] adc_dcfilter_data_out_0_s;
|
||||
wire [15:0] adc_dcfilter_data_out_1_s;
|
||||
wire [ 1:0] up_adc_pn_err_s;
|
||||
wire [ 1:0] up_adc_pn_oos_s;
|
||||
wire [ 1:0] up_adc_or_s;
|
||||
wire [31:0] up_rdata_s[0:3];
|
||||
wire up_rack_s[0:3];
|
||||
wire up_wack_s[0:3];
|
||||
|
||||
// processor read interface
|
||||
|
||||
always @(negedge up_rstn or posedge up_clk) begin
|
||||
if (up_rstn == 0) begin
|
||||
up_status_pn_err <= 'd0;
|
||||
up_status_pn_oos <= 'd0;
|
||||
up_status_or <= 'd0;
|
||||
end else begin
|
||||
up_status_pn_err <= | up_adc_pn_err_s;
|
||||
up_status_pn_oos <= | up_adc_pn_oos_s;
|
||||
up_status_or <= | up_adc_or_s;
|
||||
end
|
||||
end
|
||||
|
||||
always @(*) begin
|
||||
up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] | up_rdata_s[3];
|
||||
up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2] | up_rack_s[3];
|
||||
up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2] | up_wack_s[3];
|
||||
end
|
||||
|
||||
// channel 0 (i)
|
||||
|
||||
axi_ad9963_rx_channel #(
|
||||
.Q_OR_I_N(0),
|
||||
.CHANNEL_ID(0),
|
||||
.USERPORTS_DISABLE (USERPORTS_DISABLE),
|
||||
.DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
|
||||
.DCFILTER_DISABLE (DCFILTER_DISABLE),
|
||||
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE),
|
||||
.SCALECORRECTION_ONLY (SCALECORRECTION_ONLY))
|
||||
i_rx_channel_0 (
|
||||
.adc_clk (adc_clk),
|
||||
.adc_rst (adc_rst),
|
||||
.adc_valid (adc_valid),
|
||||
.adc_data (adc_data[11:0]),
|
||||
.adc_or (1'b0),
|
||||
.adc_dcfilter_data_out (adc_dcfilter_data_out_0_s),
|
||||
.adc_dcfilter_data_in (adc_dcfilter_data_out_1_s),
|
||||
.adc_iqcor_valid (adc_valid_i),
|
||||
.adc_iqcor_data (adc_data_i),
|
||||
.adc_enable (adc_enable_i),
|
||||
.up_adc_pn_err (up_adc_pn_err_s[0]),
|
||||
.up_adc_pn_oos (up_adc_pn_oos_s[0]),
|
||||
.up_adc_or (up_adc_or_s[0]),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq),
|
||||
.up_waddr (up_waddr),
|
||||
.up_wdata (up_wdata),
|
||||
.up_wack (up_wack_s[0]),
|
||||
.up_rreq (up_rreq),
|
||||
.up_raddr (up_raddr),
|
||||
.up_rdata (up_rdata_s[0]),
|
||||
.up_rack (up_rack_s[0]));
|
||||
|
||||
// channel 1 (q)
|
||||
|
||||
axi_ad9963_rx_channel #(
|
||||
.Q_OR_I_N(1),
|
||||
.CHANNEL_ID(1),
|
||||
.USERPORTS_DISABLE (USERPORTS_DISABLE),
|
||||
.DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
|
||||
.DCFILTER_DISABLE (DCFILTER_DISABLE),
|
||||
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE),
|
||||
.SCALECORRECTION_ONLY (SCALECORRECTION_ONLY))
|
||||
i_rx_channel_1 (
|
||||
.adc_clk (adc_clk),
|
||||
.adc_rst (adc_rst),
|
||||
.adc_valid (adc_valid),
|
||||
.adc_data (adc_data[23:12]),
|
||||
.adc_or (1'b0),
|
||||
.adc_dcfilter_data_out (adc_dcfilter_data_out_1_s),
|
||||
.adc_dcfilter_data_in (adc_dcfilter_data_out_0_s),
|
||||
.adc_iqcor_valid (adc_valid_q),
|
||||
.adc_iqcor_data (adc_data_q),
|
||||
.adc_enable (adc_enable_q),
|
||||
.up_adc_pn_err (up_adc_pn_err_s[1]),
|
||||
.up_adc_pn_oos (up_adc_pn_oos_s[1]),
|
||||
.up_adc_or (up_adc_or_s[1]),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq),
|
||||
.up_waddr (up_waddr),
|
||||
.up_wdata (up_wdata),
|
||||
.up_wack (up_wack_s[1]),
|
||||
.up_rreq (up_rreq),
|
||||
.up_raddr (up_raddr),
|
||||
.up_rdata (up_rdata_s[1]),
|
||||
.up_rack (up_rack_s[1]));
|
||||
|
||||
// common processor control
|
||||
|
||||
up_adc_common #(
|
||||
.ID (ID),
|
||||
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
|
||||
.FPGA_FAMILY (FPGA_FAMILY),
|
||||
.SPEED_GRADE (SPEED_GRADE),
|
||||
.DEV_PACKAGE (DEV_PACKAGE),
|
||||
.CONFIG (CONFIG),
|
||||
.COMMON_ID(6'h00),
|
||||
.DRP_DISABLE (1),
|
||||
.USERPORTS_DISABLE (1),
|
||||
.GPIO_DISABLE (1),
|
||||
.START_CODE_DISABLE (1)
|
||||
) i_up_adc_common (
|
||||
.mmcm_rst (),
|
||||
.adc_clk (adc_clk),
|
||||
.adc_rst (adc_rst),
|
||||
.adc_r1_mode (),
|
||||
.adc_ddr_edgesel (),
|
||||
.adc_pin_mode (),
|
||||
.adc_status (adc_status),
|
||||
.adc_sync_status (1'd0),
|
||||
.adc_status_ovf (adc_dovf),
|
||||
.adc_clk_ratio (32'd1),
|
||||
.adc_start_code (),
|
||||
.adc_sref_sync (),
|
||||
.adc_sync (),
|
||||
.adc_num_lanes (),
|
||||
.adc_sdr_ddr_n (),
|
||||
.up_pps_rcounter(32'h0),
|
||||
.up_pps_status(1'b0),
|
||||
.up_pps_irq_mask(),
|
||||
.up_adc_r1_mode (),
|
||||
.up_status_pn_err (up_status_pn_err),
|
||||
.up_status_pn_oos (up_status_pn_oos),
|
||||
.up_status_or (up_status_or),
|
||||
.up_drp_sel (),
|
||||
.up_drp_wr (),
|
||||
.up_drp_addr (),
|
||||
.up_drp_wdata (),
|
||||
.up_drp_rdata (16'd0),
|
||||
.up_drp_ready (1'd0),
|
||||
.up_drp_locked (1'd1),
|
||||
.up_usr_chanmax_out (),
|
||||
.up_usr_chanmax_in (8'd1),
|
||||
.up_adc_gpio_in (32'h0),
|
||||
.up_adc_gpio_out (),
|
||||
.up_adc_ce(up_adc_ce),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq),
|
||||
.up_waddr (up_waddr),
|
||||
.up_wdata (up_wdata),
|
||||
.up_wack (up_wack_s[2]),
|
||||
.up_rreq (up_rreq),
|
||||
.up_raddr (up_raddr),
|
||||
.up_rdata (up_rdata_s[2]),
|
||||
.up_rack (up_rack_s[2]));
|
||||
|
||||
// adc delay control
|
||||
|
||||
generate if (IODELAY_ENABLE == 1) begin
|
||||
|
||||
up_delay_cntrl #(.DATA_WIDTH(13), .BASE_ADDRESS(6'h02)) i_delay_cntrl (
|
||||
.delay_clk (delay_clk),
|
||||
.delay_rst (delay_rst),
|
||||
.delay_locked (delay_locked),
|
||||
.up_dld (up_dld),
|
||||
.up_dwdata (up_dwdata),
|
||||
.up_drdata (up_drdata),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq),
|
||||
.up_waddr (up_waddr),
|
||||
.up_wdata (up_wdata),
|
||||
.up_wack (up_wack_s[3]),
|
||||
.up_rreq (up_rreq),
|
||||
.up_raddr (up_raddr),
|
||||
.up_rdata (up_rdata_s[3]),
|
||||
.up_rack (up_rack_s[3]));
|
||||
|
||||
end else begin
|
||||
assign up_dld = 'h00;
|
||||
assign up_dwdata = 'h00;
|
||||
assign delay_rst = 1'b1;
|
||||
assign up_wack_s[3] = 0;
|
||||
assign up_rack_s[3] = 0;
|
||||
assign up_rdata_s[3] = 'h00;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
@@ -0,0 +1,219 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module axi_ad9963_rx_channel #(
|
||||
|
||||
// parameters
|
||||
|
||||
parameter Q_OR_I_N = 0,
|
||||
parameter CHANNEL_ID = 0,
|
||||
parameter USERPORTS_DISABLE = 0,
|
||||
parameter DATAFORMAT_DISABLE = 0,
|
||||
parameter DCFILTER_DISABLE = 0,
|
||||
parameter IQCORRECTION_DISABLE = 0,
|
||||
parameter SCALECORRECTION_ONLY = 1) (
|
||||
|
||||
// adc interface
|
||||
|
||||
input adc_clk,
|
||||
input adc_rst,
|
||||
input adc_valid,
|
||||
input [11:0] adc_data,
|
||||
input adc_or,
|
||||
|
||||
// channel interface
|
||||
|
||||
output [15:0] adc_dcfilter_data_out,
|
||||
input [15:0] adc_dcfilter_data_in,
|
||||
output adc_iqcor_valid,
|
||||
output [15:0] adc_iqcor_data,
|
||||
output adc_enable,
|
||||
output up_adc_pn_err,
|
||||
output up_adc_pn_oos,
|
||||
output up_adc_or,
|
||||
|
||||
// processor interface
|
||||
|
||||
input up_rstn,
|
||||
input up_clk,
|
||||
input up_wreq,
|
||||
input [13:0] up_waddr,
|
||||
input [31:0] up_wdata,
|
||||
output up_wack,
|
||||
input up_rreq,
|
||||
input [13:0] up_raddr,
|
||||
output [31:0] up_rdata,
|
||||
output up_rack);
|
||||
|
||||
// internal signals
|
||||
|
||||
wire adc_dfmt_valid_s;
|
||||
wire [15:0] adc_dfmt_data_s;
|
||||
wire adc_dcfilter_valid_s;
|
||||
wire [15:0] adc_dcfilter_data_s;
|
||||
wire adc_iqcor_enb_s;
|
||||
wire adc_dcfilt_enb_s;
|
||||
wire adc_dfmt_se_s;
|
||||
wire adc_dfmt_type_s;
|
||||
wire adc_dfmt_enable_s;
|
||||
wire [15:0] adc_dcfilt_offset_s;
|
||||
wire [15:0] adc_dcfilt_coeff_s;
|
||||
wire [15:0] adc_iqcor_coeff_1_s;
|
||||
wire [15:0] adc_iqcor_coeff_2_s;
|
||||
wire [ 3:0] adc_pnseq_sel_s;
|
||||
wire [ 3:0] adc_data_sel_s;
|
||||
wire adc_pn_err_s;
|
||||
wire adc_pn_oos_s;
|
||||
|
||||
// iq correction inputs
|
||||
|
||||
assign adc_dcfilter_data_out = adc_dcfilter_data_s;
|
||||
|
||||
axi_ad9963_rx_pnmon i_rx_pnmon (
|
||||
.adc_clk (adc_clk),
|
||||
.adc_valid (adc_valid),
|
||||
.adc_data (adc_data),
|
||||
.adc_pnseq_sel (adc_pnseq_sel_s),
|
||||
.adc_pn_oos (adc_pn_oos_s),
|
||||
.adc_pn_err (adc_pn_err_s));
|
||||
|
||||
generate
|
||||
if (DATAFORMAT_DISABLE == 1) begin
|
||||
assign adc_dfmt_valid_s = adc_valid;
|
||||
assign adc_dfmt_data_s = {{4{adc_data[11]}}, adc_data};
|
||||
end else begin
|
||||
ad_datafmt #(.DATA_WIDTH (12)) i_ad_datafmt (
|
||||
.clk (adc_clk),
|
||||
.valid (adc_valid),
|
||||
.data (adc_data),
|
||||
.valid_out (adc_dfmt_valid_s),
|
||||
.data_out (adc_dfmt_data_s),
|
||||
.dfmt_enable (adc_dfmt_enable_s),
|
||||
.dfmt_type (adc_dfmt_type_s),
|
||||
.dfmt_se (adc_dfmt_se_s));
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate
|
||||
if (DCFILTER_DISABLE == 1) begin
|
||||
assign adc_dcfilter_valid_s = adc_dfmt_valid_s;
|
||||
assign adc_dcfilter_data_s = adc_dfmt_data_s;
|
||||
end else begin
|
||||
ad_dcfilter i_ad_dcfilter (
|
||||
.clk (adc_clk),
|
||||
.valid (adc_dfmt_valid_s),
|
||||
.data (adc_dfmt_data_s),
|
||||
.valid_out (adc_dcfilter_valid_s),
|
||||
.data_out (adc_dcfilter_data_s),
|
||||
.dcfilt_enb (adc_dcfilt_enb_s),
|
||||
.dcfilt_coeff (adc_dcfilt_coeff_s),
|
||||
.dcfilt_offset (adc_dcfilt_offset_s));
|
||||
end
|
||||
endgenerate
|
||||
|
||||
ad_iqcor #(.Q_OR_I_N (Q_OR_I_N),
|
||||
.DISABLE(IQCORRECTION_DISABLE == 1),
|
||||
.SCALE_ONLY(SCALECORRECTION_ONLY))
|
||||
i_ad_iqcor (
|
||||
.clk (adc_clk),
|
||||
.valid (adc_dcfilter_valid_s),
|
||||
.data_in (adc_dcfilter_data_s),
|
||||
.data_iq (adc_dcfilter_data_in),
|
||||
.valid_out (adc_iqcor_valid),
|
||||
.data_out (adc_iqcor_data),
|
||||
.iqcor_enable (adc_iqcor_enb_s),
|
||||
.iqcor_coeff_1 (adc_iqcor_coeff_1_s),
|
||||
.iqcor_coeff_2 (adc_iqcor_coeff_2_s));
|
||||
|
||||
up_adc_channel #(
|
||||
.COMMON_ID (6'h01),
|
||||
.CHANNEL_ID (CHANNEL_ID),
|
||||
.DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
|
||||
.DCFILTER_DISABLE (DCFILTER_DISABLE),
|
||||
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE == 1),
|
||||
.USERPORTS_DISABLE (USERPORTS_DISABLE)
|
||||
) i_up_adc_channel (
|
||||
.adc_clk (adc_clk),
|
||||
.adc_rst (adc_rst),
|
||||
.adc_enable (adc_enable),
|
||||
.adc_iqcor_enb (adc_iqcor_enb_s),
|
||||
.adc_dcfilt_enb (adc_dcfilt_enb_s),
|
||||
.adc_dfmt_se (adc_dfmt_se_s),
|
||||
.adc_dfmt_type (adc_dfmt_type_s),
|
||||
.adc_dfmt_enable (adc_dfmt_enable_s),
|
||||
.adc_dcfilt_offset (adc_dcfilt_offset_s),
|
||||
.adc_dcfilt_coeff (adc_dcfilt_coeff_s),
|
||||
.adc_iqcor_coeff_1 (adc_iqcor_coeff_1_s),
|
||||
.adc_iqcor_coeff_2 (adc_iqcor_coeff_2_s),
|
||||
.adc_pnseq_sel (adc_pnseq_sel_s),
|
||||
.adc_data_sel (adc_data_sel_s),
|
||||
.adc_pn_err (adc_pn_err_s),
|
||||
.adc_pn_oos (adc_pn_oos_s),
|
||||
.adc_or (adc_or),
|
||||
.up_adc_pn_err (up_adc_pn_err),
|
||||
.up_adc_pn_oos (up_adc_pn_oos),
|
||||
.up_adc_or (up_adc_or),
|
||||
.up_usr_datatype_be (),
|
||||
.up_usr_datatype_signed (),
|
||||
.up_usr_datatype_shift (),
|
||||
.up_usr_datatype_total_bits (),
|
||||
.up_usr_datatype_bits (),
|
||||
.up_usr_decimation_m (),
|
||||
.up_usr_decimation_n (),
|
||||
.adc_usr_datatype_be (1'b0),
|
||||
.adc_usr_datatype_signed (1'b1),
|
||||
.adc_usr_datatype_shift (8'd0),
|
||||
.adc_usr_datatype_total_bits (8'd16),
|
||||
.adc_usr_datatype_bits (8'd16),
|
||||
.adc_usr_decimation_m (16'd1),
|
||||
.adc_usr_decimation_n (16'd1),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq),
|
||||
.up_waddr (up_waddr),
|
||||
.up_wdata (up_wdata),
|
||||
.up_wack (up_wack),
|
||||
.up_rreq (up_rreq),
|
||||
.up_raddr (up_raddr),
|
||||
.up_rdata (up_rdata),
|
||||
.up_rack (up_rack));
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
@@ -0,0 +1,120 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// PN monitors
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module axi_ad9963_rx_pnmon (
|
||||
|
||||
// adc interface
|
||||
|
||||
input adc_clk,
|
||||
input adc_valid,
|
||||
input [11:0] adc_data,
|
||||
|
||||
// pn out of sync and error
|
||||
|
||||
input [ 3:0] adc_pnseq_sel,
|
||||
output adc_pn_oos,
|
||||
output adc_pn_err);
|
||||
|
||||
// internal registers
|
||||
|
||||
reg [23:0] adc_pn_data_in = 'd0;
|
||||
reg [23:0] adc_pn_data_pn = 'd0;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire [31:0] adc_pn_data_pn_s;
|
||||
|
||||
// bit reversal function
|
||||
|
||||
function [11:0] brfn;
|
||||
input [11:0] din;
|
||||
reg [11:0] dout;
|
||||
begin
|
||||
dout[11] = din[ 0];
|
||||
dout[10] = din[ 1];
|
||||
dout[ 9] = din[ 2];
|
||||
dout[ 8] = din[ 3];
|
||||
dout[ 7] = din[ 4];
|
||||
dout[ 6] = din[ 5];
|
||||
dout[ 5] = din[ 6];
|
||||
dout[ 4] = din[ 7];
|
||||
dout[ 3] = din[ 8];
|
||||
dout[ 2] = din[ 9];
|
||||
dout[ 1] = din[10];
|
||||
dout[ 0] = din[11];
|
||||
brfn = dout;
|
||||
end
|
||||
endfunction
|
||||
|
||||
// standard prbs functions
|
||||
|
||||
function [23:0] pn23;
|
||||
input [23:0] din;
|
||||
reg [23:0] dout;
|
||||
begin
|
||||
dout = {din[22:0], din[22] ^ din[17]};
|
||||
pn23 = dout;
|
||||
end
|
||||
endfunction
|
||||
|
||||
// standard, runs on 24bit
|
||||
|
||||
assign adc_pn_data_pn_s = (adc_pn_oos == 1'b1) ? adc_pn_data_in : adc_pn_data_pn;
|
||||
|
||||
always @(posedge adc_clk) begin
|
||||
if(adc_valid == 1'b1) begin
|
||||
adc_pn_data_in <= {adc_pn_data_in[22:11], adc_data};
|
||||
adc_pn_data_pn <= pn23(adc_pn_data_pn_s);
|
||||
end
|
||||
end
|
||||
|
||||
// pn oos & pn err
|
||||
|
||||
ad_pnmon #(.DATA_WIDTH(24)) i_pnmon (
|
||||
.adc_clk (adc_clk),
|
||||
.adc_valid_in (adc_valid),
|
||||
.adc_data_in (adc_pn_data_in),
|
||||
.adc_data_pn (adc_pn_data_pn),
|
||||
.adc_pattern_has_zero (1'b0),
|
||||
.adc_pn_oos (adc_pn_oos),
|
||||
.adc_pn_err (adc_pn_err));
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
@@ -0,0 +1,255 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module axi_ad9963_tx #(
|
||||
|
||||
// parameters
|
||||
|
||||
parameter ID = 0,
|
||||
parameter FPGA_TECHNOLOGY = 0,
|
||||
parameter FPGA_FAMILY = 0,
|
||||
parameter SPEED_GRADE = 0,
|
||||
parameter DEV_PACKAGE = 0,
|
||||
parameter DAC_DDS_TYPE = 1,
|
||||
parameter DAC_DDS_CORDIC_DW = 14,
|
||||
parameter DAC_DDS_CORDIC_PHASE_DW = 13,
|
||||
parameter DATAPATH_DISABLE = 0) (
|
||||
|
||||
// dac interface
|
||||
|
||||
input dac_clk,
|
||||
output dac_rst,
|
||||
output [23:0] dac_data,
|
||||
input [23:0] adc_data,
|
||||
|
||||
// master/slave
|
||||
|
||||
input dac_sync_in,
|
||||
output dac_sync_out,
|
||||
|
||||
// dma interface
|
||||
|
||||
output dac_enable_i,
|
||||
output reg dac_valid_i,
|
||||
input [15:0] dac_data_i,
|
||||
input dma_valid_i,
|
||||
output out_valid_i,
|
||||
output dac_enable_q,
|
||||
output reg dac_valid_q,
|
||||
input [15:0] dac_data_q,
|
||||
input dma_valid_q,
|
||||
output out_valid_q,
|
||||
input dac_dunf,
|
||||
|
||||
output up_dac_ce,
|
||||
|
||||
// processor interface
|
||||
|
||||
input up_rstn,
|
||||
input up_clk,
|
||||
input up_wreq,
|
||||
input [13:0] up_waddr,
|
||||
input [31:0] up_wdata,
|
||||
output reg up_wack,
|
||||
input up_rreq,
|
||||
input [13:0] up_raddr,
|
||||
output reg [31:0] up_rdata,
|
||||
output reg up_rack);
|
||||
|
||||
// internal signals
|
||||
|
||||
wire dac_data_sync_s;
|
||||
wire dac_dds_format_s;
|
||||
wire [23:0] dac_data_int_s;
|
||||
wire [31:0] up_rdata_s[0:2];
|
||||
wire up_rack_s[0:2];
|
||||
wire up_wack_s[0:2];
|
||||
|
||||
// master/slave
|
||||
|
||||
assign dac_data_sync_s = (ID == 0) ? dac_sync_out : dac_sync_in;
|
||||
|
||||
// dma interface
|
||||
|
||||
always @(posedge dac_clk) begin
|
||||
if (dac_rst == 1'b1) begin
|
||||
dac_valid_i <= 1'b0;
|
||||
dac_valid_q <= 1'b0;
|
||||
end else begin
|
||||
dac_valid_i <= 1'b1;
|
||||
dac_valid_q <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
// processor read interface
|
||||
|
||||
always @(*) begin
|
||||
up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2];
|
||||
up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2];
|
||||
up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2];
|
||||
end
|
||||
|
||||
// dac channel
|
||||
|
||||
axi_ad9963_tx_channel #(
|
||||
.CHANNEL_ID (0),
|
||||
.Q_OR_I_N (0),
|
||||
.DAC_DDS_TYPE (DAC_DDS_TYPE),
|
||||
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
|
||||
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
|
||||
.DATAPATH_DISABLE (DATAPATH_DISABLE))
|
||||
i_tx_channel_0 (
|
||||
.dac_clk (dac_clk),
|
||||
.dac_rst (dac_rst),
|
||||
.dac_valid (dac_valid_i),
|
||||
.dma_data (dac_data_i),
|
||||
.adc_data (adc_data[11:0]),
|
||||
.dac_data (dac_data[11:0]),
|
||||
.dac_data_out (dac_data_int_s[11:0]),
|
||||
.dac_data_in (dac_data_int_s[23:12]),
|
||||
.dac_enable (dac_enable_i),
|
||||
.dac_data_sync (dac_data_sync_s),
|
||||
.dac_dds_format (dac_dds_format_s),
|
||||
.dma_valid (dma_valid_i),
|
||||
.out_data_valid (out_valid_i),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq),
|
||||
.up_waddr (up_waddr),
|
||||
.up_wdata (up_wdata),
|
||||
.up_wack (up_wack_s[0]),
|
||||
.up_rreq (up_rreq),
|
||||
.up_raddr (up_raddr),
|
||||
.up_rdata (up_rdata_s[0]),
|
||||
.up_rack (up_rack_s[0]));
|
||||
|
||||
// dac channel
|
||||
|
||||
axi_ad9963_tx_channel #(
|
||||
.CHANNEL_ID (1),
|
||||
.Q_OR_I_N (1),
|
||||
.DAC_DDS_TYPE (DAC_DDS_TYPE),
|
||||
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
|
||||
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
|
||||
.DATAPATH_DISABLE (DATAPATH_DISABLE))
|
||||
i_tx_channel_1 (
|
||||
.dac_clk (dac_clk),
|
||||
.dac_rst (dac_rst),
|
||||
.dac_valid (dac_valid_q),
|
||||
.dma_data (dac_data_q),
|
||||
.adc_data (adc_data[23:12]),
|
||||
.dac_data (dac_data[23:12]),
|
||||
.dac_data_out (dac_data_int_s[23:12]),
|
||||
.dac_data_in (dac_data_int_s[11:0]),
|
||||
.dac_enable (dac_enable_q),
|
||||
.dac_data_sync (dac_data_sync_s),
|
||||
.dac_dds_format (dac_dds_format_s),
|
||||
.dma_valid (dma_valid_q),
|
||||
.out_data_valid (out_valid_q),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq),
|
||||
.up_waddr (up_waddr),
|
||||
.up_wdata (up_wdata),
|
||||
.up_wack (up_wack_s[1]),
|
||||
.up_rreq (up_rreq),
|
||||
.up_raddr (up_raddr),
|
||||
.up_rdata (up_rdata_s[1]),
|
||||
.up_rack (up_rack_s[1]));
|
||||
|
||||
// dac common processor interface
|
||||
|
||||
up_dac_common #(
|
||||
.ID (ID),
|
||||
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
|
||||
.FPGA_FAMILY (FPGA_FAMILY),
|
||||
.SPEED_GRADE (SPEED_GRADE),
|
||||
.DEV_PACKAGE (DEV_PACKAGE),
|
||||
.CONFIG(0),
|
||||
.CLK_EDGE_SEL(0),
|
||||
.COMMON_ID(6'h10),
|
||||
.DRP_DISABLE (1),
|
||||
.USERPORTS_DISABLE (1),
|
||||
.GPIO_DISABLE(1)
|
||||
) i_up_dac_common (
|
||||
.mmcm_rst (),
|
||||
.dac_clk (dac_clk),
|
||||
.dac_rst (dac_rst),
|
||||
.dac_num_lanes (),
|
||||
.dac_sdr_ddr_n (),
|
||||
.dac_sync (dac_sync_out),
|
||||
.dac_frame (),
|
||||
.dac_clksel(),
|
||||
.dac_par_type (),
|
||||
.dac_par_enb (),
|
||||
.dac_r1_mode (),
|
||||
.dac_datafmt (dac_dds_format_s),
|
||||
.dac_datarate (),
|
||||
.dac_status (1'b1),
|
||||
.dac_sync_in_status (1'b1),
|
||||
.dac_status_unf (dac_dunf),
|
||||
.dac_clk_ratio (32'd1),
|
||||
.up_dac_ce(up_dac_ce),
|
||||
.up_pps_rcounter(32'h0),
|
||||
.up_pps_status(1'b0),
|
||||
.up_pps_irq_mask(),
|
||||
.up_drp_sel (),
|
||||
.up_drp_wr (),
|
||||
.up_drp_addr (),
|
||||
.up_drp_wdata (),
|
||||
.up_drp_rdata (16'd0),
|
||||
.up_drp_ready (1'd0),
|
||||
.up_drp_locked (1'd1),
|
||||
.up_usr_chanmax (),
|
||||
.dac_usr_chanmax (8'd2),
|
||||
.up_dac_gpio_in (32'h0),
|
||||
.up_dac_gpio_out (),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq),
|
||||
.up_waddr (up_waddr),
|
||||
.up_wdata (up_wdata),
|
||||
.up_wack (up_wack_s[2]),
|
||||
.up_rreq (up_rreq),
|
||||
.up_raddr (up_raddr),
|
||||
.up_rdata (up_rdata_s[2]),
|
||||
.up_rack (up_rack_s[2]));
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
@@ -0,0 +1,274 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module axi_ad9963_tx_channel #(
|
||||
|
||||
// parameters
|
||||
|
||||
parameter CHANNEL_ID = 32'h0,
|
||||
parameter Q_OR_I_N = 0,
|
||||
parameter DAC_DDS_TYPE = 1,
|
||||
parameter DAC_DDS_CORDIC_DW = 14,
|
||||
parameter DAC_DDS_CORDIC_PHASE_DW = 13,
|
||||
parameter DATAPATH_DISABLE = 0) (
|
||||
|
||||
// dac interface
|
||||
|
||||
input dac_clk,
|
||||
input dac_rst,
|
||||
input dac_valid,
|
||||
input [15:0] dma_data,
|
||||
input [11:0] adc_data,
|
||||
output reg [11:0] dac_data,
|
||||
output reg [11:0] dac_data_out,
|
||||
input [11:0] dac_data_in,
|
||||
input dma_valid,
|
||||
output out_data_valid,
|
||||
|
||||
// processor interface
|
||||
|
||||
output reg dac_enable,
|
||||
input dac_data_sync,
|
||||
input dac_dds_format,
|
||||
|
||||
// bus interface
|
||||
|
||||
input up_rstn,
|
||||
input up_clk,
|
||||
input up_wreq,
|
||||
input [13:0] up_waddr,
|
||||
input [31:0] up_wdata,
|
||||
output up_wack,
|
||||
input up_rreq,
|
||||
input [13:0] up_raddr,
|
||||
output [31:0] up_rdata,
|
||||
output up_rack);
|
||||
|
||||
localparam PRBS_SEL = CHANNEL_ID;
|
||||
localparam PRBS_P09 = 0;
|
||||
localparam PRBS_P11 = 1;
|
||||
localparam PRBS_P15 = 2;
|
||||
localparam PRBS_P20 = 3;
|
||||
|
||||
// internal registers
|
||||
|
||||
reg dac_valid_sel = 'd0;
|
||||
reg data_source_valid = 'd0;
|
||||
reg [23:0] dac_test_data = 'd0;
|
||||
reg [15:0] dac_test_counter = 'd0;
|
||||
reg [15:0] dac_pat_data = 'd0;
|
||||
reg dma_valid_m = 1'd0;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire dac_iqcor_valid_s;
|
||||
wire [15:0] dac_iqcor_data_s;
|
||||
wire [11:0] dac_dds_data_s;
|
||||
wire [15:0] dac_dds_scale_1_s;
|
||||
wire [15:0] dac_dds_init_1_s;
|
||||
wire [15:0] dac_dds_incr_1_s;
|
||||
wire [15:0] dac_dds_scale_2_s;
|
||||
wire [15:0] dac_dds_init_2_s;
|
||||
wire [15:0] dac_dds_incr_2_s;
|
||||
wire [15:0] dac_pat_data_1_s;
|
||||
wire [15:0] dac_pat_data_2_s;
|
||||
wire [ 3:0] dac_data_sel_s;
|
||||
wire dac_iqcor_enb_s;
|
||||
wire [15:0] dac_iqcor_coeff_1_s;
|
||||
wire [15:0] dac_iqcor_coeff_2_s;
|
||||
|
||||
assign out_data_valid = dac_iqcor_valid_s;
|
||||
|
||||
// dac iq correction
|
||||
|
||||
always @(posedge dac_clk) begin
|
||||
data_source_valid <= dac_data_sel_s == 4'h2 ? dma_valid_m : dac_valid;
|
||||
dac_enable <= (dac_data_sel_s == 4'h2) ? 1'b1 : 1'b0;
|
||||
if (dac_iqcor_valid_s == 1'b1) begin
|
||||
dac_data <= dac_iqcor_data_s[15:4];
|
||||
end
|
||||
end
|
||||
|
||||
generate
|
||||
if (DATAPATH_DISABLE == 1) begin
|
||||
assign dac_iqcor_valid_s = data_source_valid;
|
||||
assign dac_iqcor_data_s = {dac_data_out, 4'd0};
|
||||
end else begin
|
||||
ad_iqcor #(.Q_OR_I_N (Q_OR_I_N)) i_ad_iqcor (
|
||||
.clk (dac_clk),
|
||||
.valid (data_source_valid),
|
||||
.data_in ({dac_data_out, 4'd0}),
|
||||
.data_iq ({dac_data_in, 4'd0}),
|
||||
.valid_out (dac_iqcor_valid_s),
|
||||
.data_out (dac_iqcor_data_s),
|
||||
.iqcor_enable (dac_iqcor_enb_s),
|
||||
.iqcor_coeff_1 (dac_iqcor_coeff_1_s),
|
||||
.iqcor_coeff_2 (dac_iqcor_coeff_2_s));
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// dac mux
|
||||
|
||||
always @(posedge dac_clk) begin
|
||||
case (dac_data_sel_s)
|
||||
4'h6: dac_data_out <= dac_test_data[11:0];
|
||||
4'h5: dac_data_out <= dac_data_out-1;
|
||||
4'h4: dac_data_out <= dac_data_out+1;
|
||||
4'h3: dac_data_out <= 12'd0;
|
||||
4'h2: dac_data_out <= dma_data[15:4];
|
||||
4'h1: dac_data_out <= dac_pat_data[15:4];
|
||||
default: dac_data_out <= dac_dds_data_s;
|
||||
endcase
|
||||
dma_valid_m <= dma_valid;
|
||||
end
|
||||
|
||||
function [23:0] pn23;
|
||||
input [23:0] din;
|
||||
reg [23:0] dout;
|
||||
begin
|
||||
dout = {din[22:0], din[22] ^ din[17]};
|
||||
pn23 = dout;
|
||||
end
|
||||
endfunction
|
||||
|
||||
always @(posedge dac_clk) begin
|
||||
if(dac_data_sel_s != 6) begin
|
||||
dac_test_data <= 24'hffffff;
|
||||
dac_test_counter <= 16'h0;
|
||||
end else if (dac_test_counter == 1024) begin
|
||||
dac_test_data <= 24'h0;
|
||||
end else begin
|
||||
dac_test_data <= pn23(dac_test_data);
|
||||
dac_test_counter <= dac_test_counter + 1;
|
||||
end
|
||||
end
|
||||
|
||||
// pattern
|
||||
always @(posedge dac_clk) begin
|
||||
if (dac_data_sync == 1'b1) begin
|
||||
dac_valid_sel <= 1'b0;
|
||||
end else if (dac_valid == 1'b1) begin
|
||||
dac_valid_sel <= ~dac_valid_sel;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge dac_clk) begin
|
||||
if (dac_valid == 1'b1) begin
|
||||
if (dac_valid_sel == 1'b0) begin
|
||||
dac_pat_data <= dac_pat_data_1_s;
|
||||
end else begin
|
||||
dac_pat_data <= dac_pat_data_2_s;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// dds
|
||||
|
||||
ad_dds #(
|
||||
.DISABLE (DATAPATH_DISABLE),
|
||||
.DDS_DW (12),
|
||||
.PHASE_DW (16),
|
||||
.DDS_TYPE (DAC_DDS_TYPE),
|
||||
.CORDIC_DW (DAC_DDS_CORDIC_DW),
|
||||
.CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
|
||||
.CLK_RATIO (1))
|
||||
i_dds (
|
||||
.clk (dac_clk),
|
||||
.dac_dds_format (dac_dds_format),
|
||||
.dac_data_sync (dac_data_sync),
|
||||
.dac_valid (dac_valid),
|
||||
.tone_1_scale (dac_dds_scale_1_s),
|
||||
.tone_2_scale (dac_dds_scale_2_s),
|
||||
.tone_1_init_offset (dac_dds_init_1_s),
|
||||
.tone_2_init_offset (dac_dds_init_2_s),
|
||||
.tone_1_freq_word (dac_dds_init_2_s),
|
||||
.tone_2_freq_word (dac_dds_incr_2_s),
|
||||
.dac_dds_data (dac_dds_data_s));
|
||||
|
||||
// single channel processor
|
||||
|
||||
up_dac_channel #(
|
||||
.COMMON_ID (6'h11),
|
||||
.CHANNEL_ID(CHANNEL_ID),
|
||||
.DDS_DISABLE(DATAPATH_DISABLE),
|
||||
.IQCORRECTION_DISABLE(DATAPATH_DISABLE),
|
||||
.USERPORTS_DISABLE(1)
|
||||
) i_up_dac_channel (
|
||||
.dac_clk (dac_clk),
|
||||
.dac_rst (dac_rst),
|
||||
.dac_dds_scale_1 (dac_dds_scale_1_s),
|
||||
.dac_dds_init_1 (dac_dds_init_1_s),
|
||||
.dac_dds_incr_1 (dac_dds_incr_1_s),
|
||||
.dac_dds_scale_2 (dac_dds_scale_2_s),
|
||||
.dac_dds_init_2 (dac_dds_init_2_s),
|
||||
.dac_dds_incr_2 (dac_dds_incr_2_s),
|
||||
.dac_pat_data_1 (dac_pat_data_1_s),
|
||||
.dac_pat_data_2 (dac_pat_data_2_s),
|
||||
.dac_iq_mode(),
|
||||
.dac_data_sel (dac_data_sel_s),
|
||||
.dac_iqcor_enb (dac_iqcor_enb_s),
|
||||
.dac_iqcor_coeff_1 (dac_iqcor_coeff_1_s),
|
||||
.dac_iqcor_coeff_2 (dac_iqcor_coeff_2_s),
|
||||
.up_usr_datatype_be (),
|
||||
.up_usr_datatype_signed (),
|
||||
.up_usr_datatype_shift (),
|
||||
.up_usr_datatype_total_bits (),
|
||||
.up_usr_datatype_bits (),
|
||||
.up_usr_interpolation_m (),
|
||||
.up_usr_interpolation_n (),
|
||||
.dac_usr_datatype_be (1'b0),
|
||||
.dac_usr_datatype_signed (1'b1),
|
||||
.dac_usr_datatype_shift (8'd0),
|
||||
.dac_usr_datatype_total_bits (8'd16),
|
||||
.dac_usr_datatype_bits (8'd16),
|
||||
.dac_usr_interpolation_m (16'd1),
|
||||
.dac_usr_interpolation_n (16'd1),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq),
|
||||
.up_waddr (up_waddr),
|
||||
.up_wdata (up_wdata),
|
||||
.up_wack (up_wack),
|
||||
.up_rreq (up_rreq),
|
||||
.up_raddr (up_raddr),
|
||||
.up_rdata (up_rdata),
|
||||
.up_rack (up_rack));
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
@@ -0,0 +1,47 @@
|
||||
# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!
|
||||
proc init {cellpath otherInfo} {
|
||||
set ip [get_bd_cells $cellpath]
|
||||
|
||||
bd::mark_propagate_only $ip " \
|
||||
DEV_PACKAGE \
|
||||
SPEED_GRADE \
|
||||
FPGA_FAMILY \
|
||||
FPGA_TECHNOLOGY"
|
||||
|
||||
adi_auto_assign_device_spec $cellpath
|
||||
}
|
||||
|
||||
# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)
|
||||
proc adi_auto_assign_device_spec {cellpath} {
|
||||
|
||||
set ip [get_bd_cells $cellpath]
|
||||
set ip_param_list [list_property $ip]
|
||||
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
|
||||
|
||||
set parent_dir "../"
|
||||
for {set x 1} {$x<=4} {incr x} {
|
||||
set linkname ${ip_path}${parent_dir}scripts/adi_xilinx_device_info_enc.tcl
|
||||
if { [file exists $linkname] } {
|
||||
source ${ip_path}${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl
|
||||
break
|
||||
}
|
||||
append parent_dir "../"
|
||||
}
|
||||
|
||||
# Find predefindes auto assignable parameters
|
||||
foreach i $auto_set_param_list {
|
||||
if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
|
||||
set val [adi_device_spec $cellpath $i]
|
||||
set_property CONFIG.$i $val $ip
|
||||
}
|
||||
}
|
||||
|
||||
# Find predefindes auto assignable/overwritable parameters
|
||||
foreach i $auto_set_param_list_overwritable {
|
||||
if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
|
||||
set val [adi_device_spec $cellpath $i]
|
||||
set_property CONFIG.$i $val $ip
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,2 @@
|
||||
CLEAN_TARGET += bd
|
||||
CLEAN_TARGET += temporary_case_dependencies.mk
|
||||
@@ -0,0 +1,283 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||
ipgui::add_param $IPINST -name "ADC_DATAFORMAT_DISABLE" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "ADC_DCFILTER_DISABLE" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "ADC_IODELAY_ENABLE" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "ADC_IQCORRECTION_DISABLE" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "ADC_SCALECORRECTION_ONLY" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "ADC_USERPORTS_DISABLE" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "DAC_DATAPATH_DISABLE" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "DAC_DDS_CORDIC_DW" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "DAC_DDS_CORDIC_PHASE_DW" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "DAC_DDS_TYPE" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "DELAY_REFCLK_FREQUENCY" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "ID" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "IODELAY_ENABLE" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "IO_DELAY_GROUP" -parent ${Page_0}
|
||||
#Adding Group
|
||||
set FPGA_info [ipgui::add_group $IPINST -name "FPGA info" -parent ${Page_0}]
|
||||
ipgui::add_param $IPINST -name "FPGA_TECHNOLOGY" -parent ${FPGA_info} -widget comboBox
|
||||
ipgui::add_param $IPINST -name "FPGA_FAMILY" -parent ${FPGA_info} -widget comboBox
|
||||
ipgui::add_param $IPINST -name "SPEED_GRADE" -parent ${FPGA_info} -widget comboBox
|
||||
ipgui::add_param $IPINST -name "DEV_PACKAGE" -parent ${FPGA_info} -widget comboBox
|
||||
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ADC_DATAFORMAT_DISABLE { PARAM_VALUE.ADC_DATAFORMAT_DISABLE } {
|
||||
# Procedure called to update ADC_DATAFORMAT_DISABLE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ADC_DATAFORMAT_DISABLE { PARAM_VALUE.ADC_DATAFORMAT_DISABLE } {
|
||||
# Procedure called to validate ADC_DATAFORMAT_DISABLE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ADC_DCFILTER_DISABLE { PARAM_VALUE.ADC_DCFILTER_DISABLE } {
|
||||
# Procedure called to update ADC_DCFILTER_DISABLE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ADC_DCFILTER_DISABLE { PARAM_VALUE.ADC_DCFILTER_DISABLE } {
|
||||
# Procedure called to validate ADC_DCFILTER_DISABLE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ADC_IODELAY_ENABLE { PARAM_VALUE.ADC_IODELAY_ENABLE } {
|
||||
# Procedure called to update ADC_IODELAY_ENABLE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ADC_IODELAY_ENABLE { PARAM_VALUE.ADC_IODELAY_ENABLE } {
|
||||
# Procedure called to validate ADC_IODELAY_ENABLE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ADC_IQCORRECTION_DISABLE { PARAM_VALUE.ADC_IQCORRECTION_DISABLE } {
|
||||
# Procedure called to update ADC_IQCORRECTION_DISABLE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ADC_IQCORRECTION_DISABLE { PARAM_VALUE.ADC_IQCORRECTION_DISABLE } {
|
||||
# Procedure called to validate ADC_IQCORRECTION_DISABLE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ADC_SCALECORRECTION_ONLY { PARAM_VALUE.ADC_SCALECORRECTION_ONLY } {
|
||||
# Procedure called to update ADC_SCALECORRECTION_ONLY when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ADC_SCALECORRECTION_ONLY { PARAM_VALUE.ADC_SCALECORRECTION_ONLY } {
|
||||
# Procedure called to validate ADC_SCALECORRECTION_ONLY
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ADC_USERPORTS_DISABLE { PARAM_VALUE.ADC_USERPORTS_DISABLE } {
|
||||
# Procedure called to update ADC_USERPORTS_DISABLE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ADC_USERPORTS_DISABLE { PARAM_VALUE.ADC_USERPORTS_DISABLE } {
|
||||
# Procedure called to validate ADC_USERPORTS_DISABLE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DAC_DATAPATH_DISABLE { PARAM_VALUE.DAC_DATAPATH_DISABLE } {
|
||||
# Procedure called to update DAC_DATAPATH_DISABLE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DAC_DATAPATH_DISABLE { PARAM_VALUE.DAC_DATAPATH_DISABLE } {
|
||||
# Procedure called to validate DAC_DATAPATH_DISABLE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DAC_DDS_CORDIC_DW { PARAM_VALUE.DAC_DDS_CORDIC_DW } {
|
||||
# Procedure called to update DAC_DDS_CORDIC_DW when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DAC_DDS_CORDIC_DW { PARAM_VALUE.DAC_DDS_CORDIC_DW } {
|
||||
# Procedure called to validate DAC_DDS_CORDIC_DW
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW { PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW } {
|
||||
# Procedure called to update DAC_DDS_CORDIC_PHASE_DW when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW { PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW } {
|
||||
# Procedure called to validate DAC_DDS_CORDIC_PHASE_DW
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DAC_DDS_TYPE { PARAM_VALUE.DAC_DDS_TYPE } {
|
||||
# Procedure called to update DAC_DDS_TYPE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DAC_DDS_TYPE { PARAM_VALUE.DAC_DDS_TYPE } {
|
||||
# Procedure called to validate DAC_DDS_TYPE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DELAY_REFCLK_FREQUENCY { PARAM_VALUE.DELAY_REFCLK_FREQUENCY } {
|
||||
# Procedure called to update DELAY_REFCLK_FREQUENCY when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DELAY_REFCLK_FREQUENCY { PARAM_VALUE.DELAY_REFCLK_FREQUENCY } {
|
||||
# Procedure called to validate DELAY_REFCLK_FREQUENCY
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } {
|
||||
# Procedure called to update DEV_PACKAGE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } {
|
||||
# Procedure called to validate DEV_PACKAGE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } {
|
||||
# Procedure called to update FPGA_FAMILY when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } {
|
||||
# Procedure called to validate FPGA_FAMILY
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } {
|
||||
# Procedure called to update FPGA_TECHNOLOGY when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } {
|
||||
# Procedure called to validate FPGA_TECHNOLOGY
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } {
|
||||
# Procedure called to update ID when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } {
|
||||
# Procedure called to validate ID
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.IODELAY_ENABLE { PARAM_VALUE.IODELAY_ENABLE } {
|
||||
# Procedure called to update IODELAY_ENABLE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.IODELAY_ENABLE { PARAM_VALUE.IODELAY_ENABLE } {
|
||||
# Procedure called to validate IODELAY_ENABLE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.IO_DELAY_GROUP { PARAM_VALUE.IO_DELAY_GROUP } {
|
||||
# Procedure called to update IO_DELAY_GROUP when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.IO_DELAY_GROUP { PARAM_VALUE.IO_DELAY_GROUP } {
|
||||
# Procedure called to validate IO_DELAY_GROUP
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } {
|
||||
# Procedure called to update SPEED_GRADE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } {
|
||||
# Procedure called to validate SPEED_GRADE
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.FPGA_TECHNOLOGY { MODELPARAM_VALUE.FPGA_TECHNOLOGY PARAM_VALUE.FPGA_TECHNOLOGY } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.FPGA_TECHNOLOGY}] ${MODELPARAM_VALUE.FPGA_TECHNOLOGY}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.FPGA_FAMILY { MODELPARAM_VALUE.FPGA_FAMILY PARAM_VALUE.FPGA_FAMILY } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.FPGA_FAMILY}] ${MODELPARAM_VALUE.FPGA_FAMILY}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.SPEED_GRADE { MODELPARAM_VALUE.SPEED_GRADE PARAM_VALUE.SPEED_GRADE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.SPEED_GRADE}] ${MODELPARAM_VALUE.SPEED_GRADE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DEV_PACKAGE { MODELPARAM_VALUE.DEV_PACKAGE PARAM_VALUE.DEV_PACKAGE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DEV_PACKAGE}] ${MODELPARAM_VALUE.DEV_PACKAGE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.ADC_IODELAY_ENABLE { MODELPARAM_VALUE.ADC_IODELAY_ENABLE PARAM_VALUE.ADC_IODELAY_ENABLE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ADC_IODELAY_ENABLE}] ${MODELPARAM_VALUE.ADC_IODELAY_ENABLE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.IO_DELAY_GROUP { MODELPARAM_VALUE.IO_DELAY_GROUP PARAM_VALUE.IO_DELAY_GROUP } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.IO_DELAY_GROUP}] ${MODELPARAM_VALUE.IO_DELAY_GROUP}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.IODELAY_ENABLE { MODELPARAM_VALUE.IODELAY_ENABLE PARAM_VALUE.IODELAY_ENABLE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.IODELAY_ENABLE}] ${MODELPARAM_VALUE.IODELAY_ENABLE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DAC_DDS_TYPE { MODELPARAM_VALUE.DAC_DDS_TYPE PARAM_VALUE.DAC_DDS_TYPE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DAC_DDS_TYPE}] ${MODELPARAM_VALUE.DAC_DDS_TYPE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DAC_DDS_CORDIC_DW { MODELPARAM_VALUE.DAC_DDS_CORDIC_DW PARAM_VALUE.DAC_DDS_CORDIC_DW } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DAC_DDS_CORDIC_DW}] ${MODELPARAM_VALUE.DAC_DDS_CORDIC_DW}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW { MODELPARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW}] ${MODELPARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DAC_DATAPATH_DISABLE { MODELPARAM_VALUE.DAC_DATAPATH_DISABLE PARAM_VALUE.DAC_DATAPATH_DISABLE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DAC_DATAPATH_DISABLE}] ${MODELPARAM_VALUE.DAC_DATAPATH_DISABLE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.ADC_USERPORTS_DISABLE { MODELPARAM_VALUE.ADC_USERPORTS_DISABLE PARAM_VALUE.ADC_USERPORTS_DISABLE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ADC_USERPORTS_DISABLE}] ${MODELPARAM_VALUE.ADC_USERPORTS_DISABLE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.ADC_DATAFORMAT_DISABLE { MODELPARAM_VALUE.ADC_DATAFORMAT_DISABLE PARAM_VALUE.ADC_DATAFORMAT_DISABLE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ADC_DATAFORMAT_DISABLE}] ${MODELPARAM_VALUE.ADC_DATAFORMAT_DISABLE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.ADC_DCFILTER_DISABLE { MODELPARAM_VALUE.ADC_DCFILTER_DISABLE PARAM_VALUE.ADC_DCFILTER_DISABLE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ADC_DCFILTER_DISABLE}] ${MODELPARAM_VALUE.ADC_DCFILTER_DISABLE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.ADC_IQCORRECTION_DISABLE { MODELPARAM_VALUE.ADC_IQCORRECTION_DISABLE PARAM_VALUE.ADC_IQCORRECTION_DISABLE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ADC_IQCORRECTION_DISABLE}] ${MODELPARAM_VALUE.ADC_IQCORRECTION_DISABLE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.ADC_SCALECORRECTION_ONLY { MODELPARAM_VALUE.ADC_SCALECORRECTION_ONLY PARAM_VALUE.ADC_SCALECORRECTION_ONLY } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ADC_SCALECORRECTION_ONLY}] ${MODELPARAM_VALUE.ADC_SCALECORRECTION_ONLY}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DELAY_REFCLK_FREQUENCY { MODELPARAM_VALUE.DELAY_REFCLK_FREQUENCY PARAM_VALUE.DELAY_REFCLK_FREQUENCY } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DELAY_REFCLK_FREQUENCY}] ${MODELPARAM_VALUE.DELAY_REFCLK_FREQUENCY}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user