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josh
2023-04-13 13:33:41 +08:00
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adi_library/axi_adc_decimate/Makefile
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####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
LIBRARY_NAME := axi_adc_decimate
GENERIC_DEPS += ../common/ad_iqcor.v
GENERIC_DEPS += ../common/up_axi.v
GENERIC_DEPS += ../common/up_xfer_cntrl.v
GENERIC_DEPS += axi_adc_decimate.v
GENERIC_DEPS += axi_adc_decimate_filter.v
GENERIC_DEPS += axi_adc_decimate_reg.v
GENERIC_DEPS += cic_decim.v
GENERIC_DEPS += fir_decim.v
XILINX_DEPS += ../xilinx/common/ad_mul.v
XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
XILINX_DEPS += axi_adc_decimate_ip.tcl
XILINX_LIB_DEPS += util_cic
include ../scripts/library.mk
adi_library/axi_adc_decimate/axi_adc_decimate.cache/wt/project.wpc
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version:1
6d6f64655f636f756e7465727c42617463684d6f6465:1
eof:
adi_library/axi_adc_decimate/axi_adc_decimate.hw/axi_adc_decimate.lpr
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<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
<labtools version="1" minor="0"/>
adi_library/axi_adc_decimate/axi_adc_decimate.v
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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_adc_decimate #(
parameter CORRECTION_DISABLE = 1) (
input adc_clk,
input adc_rst,
input [15:0] adc_data_a,
input [15:0] adc_data_b,
input adc_valid_a,
input adc_valid_b,
output [15:0] adc_dec_data_a,
output [15:0] adc_dec_data_b,
output adc_dec_valid_a,
output adc_dec_valid_b,
output [ 2:0] adc_data_rate,
output adc_oversampling_en,
// axi interface
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [ 6:0] s_axi_awaddr,
input [ 2:0] s_axi_awprot,
output s_axi_awready,
input s_axi_wvalid,
input [31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [ 6:0] s_axi_araddr,
input [ 2:0] s_axi_arprot,
output s_axi_arready,
output s_axi_rvalid,
output [31:0] s_axi_rdata,
output [ 1:0] s_axi_rresp,
input s_axi_rready);
// internal signals
wire up_clk;
wire up_rstn;
wire [ 4:0] up_waddr;
wire [31:0] up_wdata;
wire up_wack;
wire up_wreq;
wire up_rack;
wire [31:0] up_rdata;
wire up_rreq;
wire [ 4:0] up_raddr;
wire [31:0] decimation_ratio;
wire [ 2:0] filter_mask;
wire adc_correction_enable_a;
wire adc_correction_enable_b;
wire [15:0] adc_correction_coefficient_a;
wire [15:0] adc_correction_coefficient_b;
// signal name changes
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
assign adc_data_rate = filter_mask;
assign adc_oversampling_en = |decimation_ratio;
axi_adc_decimate_filter #(
.CORRECTION_DISABLE(CORRECTION_DISABLE)
) axi_adc_decimate_filter (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.decimation_ratio (decimation_ratio),
.filter_mask (filter_mask),
.adc_correction_enable_a(adc_correction_enable_a),
.adc_correction_enable_b(adc_correction_enable_b),
.adc_correction_coefficient_a(adc_correction_coefficient_a),
.adc_correction_coefficient_b(adc_correction_coefficient_b),
.adc_valid_a(adc_valid_a),
.adc_valid_b(adc_valid_b),
.adc_data_a(adc_data_a[11:0]),
.adc_data_b(adc_data_b[11:0]),
.adc_dec_data_a(adc_dec_data_a),
.adc_dec_data_b(adc_dec_data_b),
.adc_dec_valid_a(adc_dec_valid_a),
.adc_dec_valid_b(adc_dec_valid_b));
axi_adc_decimate_reg axi_adc_decimate_reg (
.clk (adc_clk),
.adc_decimation_ratio (decimation_ratio),
.adc_filter_mask (filter_mask),
.adc_correction_enable_a(adc_correction_enable_a),
.adc_correction_enable_b(adc_correction_enable_b),
.adc_correction_coefficient_a(adc_correction_coefficient_a),
.adc_correction_coefficient_b(adc_correction_coefficient_b),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata),
.up_rack (up_rack));
up_axi #(
.AXI_ADDRESS_WIDTH(7)
) i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************
adi_library/axi_adc_decimate/axi_adc_decimate.xpr
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<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
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<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="9"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
<MsgAttr Name="StringsToMatch" Val="HDPYFinalizeIO"/>
</MsgRule>
<Board/>
<DashboardSummary Version="1" Minor="0">
<Dashboards>
<Dashboard Name="default_dashboard">
<Gadgets>
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
</Gadget>
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
</Gadget>
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
</Gadget>
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
</Gadget>
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
</Gadget>
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
</Gadget>
</Gadgets>
</Dashboard>
<CurrentDashboard>default_dashboard</CurrentDashboard>
</Dashboards>
</DashboardSummary>
<BootPmcSettings Version="1" Minor="0">
<Parameters>
<Parameter Name="PMC_CDO.ATTRS.LOADADDR" Value="" Type="string"/>
<Parameter Name="BOOT.PMC.QSPI_ENABLE" Value="0" Type="string"/>
<Parameter Name="BOOT.PMC.QSPI_FB_CLK" Value="0" Type="string"/>
<Parameter Name="BOOT.PMC.QSPI_FREQ" Value="300" Type="string"/>
<Parameter Name="BOOT.PMC.QSPI_BUS_WIDTH" Value="x1" Type="string"/>
<Parameter Name="BOOT.PMC.QSPI_DATA_MODE" Value="Single" Type="string"/>
<Parameter Name="BOOT.PMC.SD0_ENABLE" Value="0" Type="string"/>
<Parameter Name="BOOT.PMC.SD0_FREQ" Value="200" Type="string"/>
<Parameter Name="BOOT.PMC.SD0_SLOT_TYPE" Value="SD 2.0" Type="string"/>
<Parameter Name="BOOT.PMC.SD0_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
<Parameter Name="BOOT.PMC.SD1_ENABLE" Value="0" Type="string"/>
<Parameter Name="BOOT.PMC.SD1_FREQ" Value="200" Type="string"/>
<Parameter Name="BOOT.PMC.SD1_SLOT_TYPE" Value="SD 2.0" Type="string"/>
<Parameter Name="BOOT.PMC.SD1_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
<Parameter Name="BOOT.PMC.OSPI_ENABLE" Value="0" Type="string"/>
<Parameter Name="BOOT.PMC.OSPI_FREQ" Value="300" Type="string"/>
<Parameter Name="BOOT.USB_ENABLE" Value="0" Type="string"/>
<Parameter Name="BOOT.PMC.SMAP_ENABLE" Value="0" Type="string"/>
<Parameter Name="BOOT.PMC.SMAP_DATA_WIDTH" Value="32 Bit" Type="string"/>
<Parameter Name="BOOT.PMC.OSC_FREQ" Value="33.333" Type="string"/>
<Parameter Name="BOOT.SECONDARY.PCIE_ENABLE" Value="0" Type="string"/>
</Parameters>
</BootPmcSettings>
</Project>
adi_library/axi_adc_decimate/axi_adc_decimate_filter.v
+209
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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_adc_decimate_filter #(
parameter CORRECTION_DISABLE = 1) (
input adc_clk,
input adc_rst,
input [31:0] decimation_ratio,
input [ 2:0] filter_mask,
input adc_correction_enable_a,
input adc_correction_enable_b,
input [15:0] adc_correction_coefficient_a,
input [15:0] adc_correction_coefficient_b,
input adc_valid_a,
input adc_valid_b,
input [11:0] adc_data_a,
input [11:0] adc_data_b,
output [15:0] adc_dec_data_a,
output [15:0] adc_dec_data_b,
output adc_dec_valid_a,
output adc_dec_valid_b
);
// internal signals
reg [31:0] decimation_counter;
reg adc_dec_valid_a_filter;
reg adc_dec_valid_b_filter;
reg [4:0] filter_enable = 5'h00;
reg [15:0] adc_dec_data_a_r;
reg [15:0] adc_dec_data_b_r;
reg adc_dec_valid_a_r;
reg adc_dec_valid_b_r;
wire [25:0] adc_fir_data_a;
wire adc_fir_valid_a;
wire [25:0] adc_fir_data_b;
wire adc_fir_valid_b;
wire [11:0] adc_cic_data_a;
wire adc_cic_valid_a;
wire [11:0] adc_cic_data_b;
wire adc_cic_valid_b;
cic_decim cic_decimation_a (
.clk(adc_clk),
.clk_enable(adc_valid_a),
.filter_enable(filter_enable),
.reset(adc_rst),
.filter_in(adc_data_a[11:0]),
.rate_sel(filter_mask),
.filter_out(adc_cic_data_a),
.ce_out(adc_cic_valid_a));
cic_decim cic_decimation_b (
.clk(adc_clk),
.clk_enable(adc_valid_b),
.filter_enable(filter_enable),
.reset(adc_rst),
.filter_in(adc_data_b[11:0]),
.rate_sel(filter_mask),
.filter_out(adc_cic_data_b),
.ce_out(adc_cic_valid_b));
fir_decim fir_decimation_a (
.clk(adc_clk),
.clk_enable(adc_cic_valid_a),
.reset(adc_rst),
.filter_in(adc_cic_data_a),
.filter_out(adc_fir_data_a),
.ce_out(adc_fir_valid_a));
fir_decim fir_decimation_b (
.clk(adc_clk),
.clk_enable(adc_cic_valid_b),
.reset(adc_rst),
.filter_in(adc_cic_data_b),
.filter_out(adc_fir_data_b),
.ce_out(adc_fir_valid_b));
ad_iqcor #(.Q_OR_I_N (0),
.DISABLE(CORRECTION_DISABLE),
.SCALE_ONLY(1)
) i_scale_correction_a (
.clk (adc_clk),
.valid (adc_dec_valid_a_r),
.data_in (adc_dec_data_a_r),
.data_iq (16'h0),
.valid_out (adc_dec_valid_a),
.data_out (adc_dec_data_a),
.iqcor_enable (adc_correction_enable_a),
.iqcor_coeff_1 (adc_correction_coefficient_a),
.iqcor_coeff_2 (16'h0));
ad_iqcor #(.Q_OR_I_N (0),
.DISABLE(CORRECTION_DISABLE),
.SCALE_ONLY(1)
) i_scale_correction_b (
.clk (adc_clk),
.valid (adc_dec_valid_b_r),
.data_in (adc_dec_data_b_r),
.data_iq (16'h0),
.valid_out (adc_dec_valid_b),
.data_out (adc_dec_data_b),
.iqcor_enable (adc_correction_enable_b),
.iqcor_coeff_1 (adc_correction_coefficient_b),
.iqcor_coeff_2 (16'h0));
always @(posedge adc_clk) begin
case (filter_mask)
3'h1: filter_enable <= 5'b00001;
3'h2: filter_enable <= 5'b00011;
3'h3: filter_enable <= 5'b00111;
3'h6: filter_enable <= 5'b01111;
3'h7: filter_enable <= 5'b11111;
default: filter_enable <= 5'b00000;
endcase
end
always @(*) begin
case (filter_enable[0])
1'b0: adc_dec_data_a_r = {{4{adc_data_a[11]}},adc_data_a};
default: adc_dec_data_a_r = {adc_fir_data_a[25], adc_fir_data_a[25:11]};
endcase
case (filter_enable[0])
1'b0: adc_dec_valid_a_filter = adc_valid_a;
default: adc_dec_valid_a_filter = adc_fir_valid_a;
endcase
case (filter_enable[0])
1'b0: adc_dec_data_b_r = {{4{adc_data_b[11]}},adc_data_b};
default adc_dec_data_b_r = {adc_fir_data_b[25], adc_fir_data_b[25:11]};
endcase
case (filter_enable[0])
1'b0: adc_dec_valid_b_filter = adc_valid_b;
default: adc_dec_valid_b_filter = adc_fir_valid_b;
endcase
end
always @(posedge adc_clk) begin
if (adc_rst == 1'b1) begin
decimation_counter <= 32'b0;
adc_dec_valid_a_r <= 1'b0;
adc_dec_valid_b_r <= 1'b0;
end else begin
if (adc_dec_valid_a_filter == 1'b1) begin
if (decimation_counter < decimation_ratio) begin
decimation_counter <= decimation_counter + 1;
adc_dec_valid_a_r <= 1'b0;
adc_dec_valid_b_r <= 1'b0;
end else begin
decimation_counter <= 0;
adc_dec_valid_a_r <= 1'b1;
adc_dec_valid_b_r <= 1'b1;
end
end else begin
adc_dec_valid_a_r <= 1'b0;
adc_dec_valid_b_r <= 1'b0;
end
end
end
endmodule
adi_library/axi_adc_decimate/axi_adc_decimate_ip.tcl
+29
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# ip
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
adi_ip_create axi_adc_decimate
adi_ip_files axi_adc_decimate [list \
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
"$ad_hdl_dir/library/common/ad_iqcor.v" \
"$ad_hdl_dir/library/xilinx/common/ad_mul.v" \
"$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \
"fir_decim.v" \
"cic_decim.v" \
"axi_adc_decimate_filter.v" \
"axi_adc_decimate_reg.v" \
"axi_adc_decimate.v" ]
adi_ip_properties axi_adc_decimate
adi_ip_add_core_dependencies { \
analog.com:user:util_cic:1.0 \
}
ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface adc_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::save_core [ipx::current_core]
adi_library/axi_adc_decimate/axi_adc_decimate_reg.v
+156
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@@ -0,0 +1,156 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_adc_decimate_reg(
input clk,
output [31:0] adc_decimation_ratio,
output [ 2:0] adc_filter_mask,
output adc_correction_enable_a,
output adc_correction_enable_b,
output [15:0] adc_correction_coefficient_a,
output [15:0] adc_correction_coefficient_b,
// bus interface
input up_rstn,
input up_clk,
input up_wreq,
input [ 4:0] up_waddr,
input [31:0] up_wdata,
output reg up_wack,
input up_rreq,
input [ 4:0] up_raddr,
output reg [31:0] up_rdata,
output reg up_rack);
// internal registers
reg [31:0] up_version = 32'h00010000;
reg [31:0] up_scratch = 32'h0;
reg [31:0] up_decimation_ratio = 32'h0;
reg [ 2:0] up_filter_mask = 32'h0;
reg [ 1:0] up_config = 1'h0;
reg [15:0] up_correction_coefficient_a = 16'h0;
reg [15:0] up_correction_coefficient_b = 16'h0;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_wack <= 'd0;
up_scratch <= 'd0;
up_decimation_ratio <= 'd0;
up_filter_mask <= 'd0;
up_config <= 'd0;
up_correction_coefficient_a <= 'd0;
up_correction_coefficient_b <= 'd0;
end else begin
up_wack <= up_wreq;
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h1)) begin
up_scratch <= up_wdata;
end
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h10)) begin
up_decimation_ratio <= up_wdata;
end
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h11)) begin
up_filter_mask <= up_wdata[2:0];
end
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h12)) begin
up_config <= up_wdata[1:0];
end
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h13)) begin
up_correction_coefficient_a <= up_wdata[15:0];
end
if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h14)) begin
up_correction_coefficient_b <= up_wdata[15:0];
end
end
end
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rack <= 'd0;
up_rdata <= 'd0;
end else begin
up_rack <= up_rreq;
if (up_rreq == 1'b1) begin
case (up_raddr[4:0])
5'h0: up_rdata <= up_version;
5'h1: up_rdata <= up_scratch;
5'h10: up_rdata <= up_decimation_ratio;
5'h11: up_rdata <= { 29'h0, up_filter_mask };
5'h12: up_rdata <= { 30'h0, up_config };
5'h13: up_rdata <= { 16'h0, up_correction_coefficient_a };
5'h14: up_rdata <= { 16'h0, up_correction_coefficient_b };
default: up_rdata <= 0;
endcase
end else begin
up_rdata <= 32'd0;
end
end
end
up_xfer_cntrl #(.DATA_WIDTH(69)) i_xfer_cntrl (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_cntrl ({ up_config[1], // 1
up_config[0], // 1
up_correction_coefficient_b, // 16
up_correction_coefficient_a, // 16
up_decimation_ratio, // 32
up_filter_mask}), // 3
.up_xfer_done (),
.d_rst (1'b0),
.d_clk (clk),
.d_data_cntrl ({ adc_correction_enable_b, // 1
adc_correction_enable_a, // 1
adc_correction_coefficient_b, // 16
adc_correction_coefficient_a, // 16
adc_decimation_ratio, // 32
adc_filter_mask})); // 3
endmodule
// ***************************************************************************
// ***************************************************************************
adi_library/axi_adc_decimate/cic_decim.v
+162
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@@ -0,0 +1,162 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1 ns / 1 ns
module cic_decim (
input clk,
input clk_enable,
input [4:0] filter_enable,
input reset,
input [11:0] filter_in,
input [2:0] rate_sel,
output [11:0] filter_out,
output ce_out
);
localparam NUM_STAGES = 6;
localparam DATA_WIDTH = 106;
reg [11:0] filter_input_stage = 'h00;
wire signed [DATA_WIDTH-1:0] data_stage[0:NUM_STAGES*2];
wire signed [DATA_WIDTH-1:0] data_final_stage;
reg [16:0] counter = 'h00;
reg ce_comb = 1'b0;
reg ce_out_reg = 1'b0;
reg [11:0] data_out = 'h00;
reg [15:0] rate;
wire [4:0] enable = (clk_enable == 1'b1) ? filter_enable : 5'b0;
always @(*) begin
case (rate_sel)
3'h1: rate <= 16'd5 - 1;
3'h2: rate <= 16'd50 - 1;
3'h3: rate <= 16'd500 - 1;
3'h6: rate <= 16'd5000 - 1;
default: rate <= 16'd50000 - 1;
endcase
end
wire [15:0] counter_in = counter[16] == 1'b1 ? rate : counter[15:0];
always @(posedge clk) begin
if (reset == 1'b1) begin
counter <= {1'b1,16'h00};
end else if (clk_enable == 1'b1 && enable[0] == 1'b1) begin
counter <= counter_in - 1'b1;
end
end
always @(posedge clk) begin
if (reset == 1'b1) begin
ce_comb <= 1'b0;
end else begin
ce_comb <= enable[0] & counter[16];
end
end
always @(posedge clk) begin
if (enable[0] == 1'b1) begin
filter_input_stage <= filter_in;
end
end
assign data_stage[0] = $signed(filter_input_stage);
generate
genvar i;
for (i = 0; i < NUM_STAGES; i = i + 1) begin
cic_int #(
.DATA_WIDTH(DATA_WIDTH),
.NUM_STAGES(5),
.STAGE_WIDTH(20)
) i_int (
.clk(clk),
.ce(enable),
.data_in(data_stage[i]),
.data_out(data_stage[i+1])
);
end
endgenerate
cic_comb #(
.DATA_WIDTH(DATA_WIDTH),
.SEQ(5),
.NUM_STAGES(5),
.STAGE_WIDTH(20)
) i_comb0 (
.clk(clk),
.ce(ce_comb),
.enable(filter_enable),
.data_in(data_stage[6]),
.data_out(data_stage[11])
);
cic_comb #(
.DATA_WIDTH(DATA_WIDTH),
.SEQ(1),
.NUM_STAGES(5),
.STAGE_WIDTH(20)
) i_comb1 (
.clk(clk),
.ce(ce_comb),
.enable(filter_enable),
.data_in(data_stage[11]),
.data_out(data_stage[12])
);
assign data_final_stage = data_stage[2*NUM_STAGES];
always @(posedge clk) begin
if (ce_comb == 1'b1) begin
case (rate_sel)
'h1: data_out <= data_final_stage[25:14];
'h2: data_out <= data_final_stage[45:34];
'h3: data_out <= data_final_stage[65:54];
'h6: data_out <= data_final_stage[85:74];
default: data_out <= data_final_stage[105:94];
endcase
end
ce_out_reg <= ce_comb;
end
assign ce_out = ce_out_reg;
assign filter_out = data_out;
endmodule // cic_decim
adi_library/axi_adc_decimate/component.xml
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adi_library/axi_adc_decimate/fir_decim.v
+279
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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1 ns / 1 ns
module fir_decim #(
parameter USE_DSP48E = 1
) (
input clk,
input clk_enable,
input reset,
input signed [11:0] filter_in,
output reg signed [25:0] filter_out,
output reg ce_out
);
localparam signed [11:0] coeffphase1_1 = 12'b000011010101; //sfix12_En11
localparam signed [11:0] coeffphase1_2 = 12'b011011110010; //sfix12_En11
localparam signed [11:0] coeffphase1_3 = 12'b110000111110; //sfix12_En11
// We know that clk_enable is asserted at most every 5th clock cycle and the
// output is decimated by two. So we have 10 clock cycles to compute the
// result. That's plenty of time considering that there are only 6
// coefficients.
reg active = 1'b0;
reg active_d1 = 1'b0;
reg active_d2 = 1'b0;
reg [1:0] count = 2'b00;
reg phase = 1'b1;
reg ready = 1'b0;
reg [3:0] storage0[0:11];
reg [3:0] storage1[0:11];
reg signed [11:0] data0;
reg signed [11:0] data1;
reg signed [11:0] coeff;
wire signed [25:0] sum;
integer j;
initial begin
for (j = 0; j < 12; j = j + 1) begin
storage0[j] <= 'h00;
storage1[j] <= 'h00;
end
end
always @(posedge clk) begin
if (reset == 1'b1) begin
phase <= 1'b1;
end else begin
if (clk_enable == 1'b1) begin
phase <= phase + 1'b1;
end
end
end
always @(posedge clk) begin
if (clk_enable == 1'b1 && phase == 1'b1) begin
active <= 1'b1;
end else if (count == 'h2) begin
active <= 1'b0;
end
active_d1 <= active;
active_d2 <= active_d1;
end
always @(posedge clk) begin
if (active == 1'b1) begin
case (count)
'h2: count <= 'h0;
default: count <= count + 1'b1;
endcase
end
end
always @(posedge clk) begin
if (active_d1 == 1'b0 && active_d2 == 1'b1) begin
ready <= 1'b1;
end else begin
ready <= 1'b0;
end
end
generate
genvar i;
for (i = 0; i < 12; i = i + 1) begin
always @(posedge clk) begin
if (clk_enable == 1'b1) begin
if (phase == 1'b0) begin
storage0[i] <= {storage0[i][2:0],filter_in[i]};
end
if (phase == 1'b1) begin
storage1[i] <= {storage1[i][2:0],filter_in[i]};
end
end
end
always @(*) begin
data0[i] <= storage0[i][2-count];
data1[i] <= storage1[i][count];
end
end
endgenerate
always @(*) begin
case (count)
'h0: coeff <= coeffphase1_1;
'h1: coeff <= coeffphase1_2;
'h2: coeff <= coeffphase1_3;
default: coeff <= 'h00;
endcase
end
generate if (USE_DSP48E) begin
wire [47:0] _sum;
wire [6:0] opmode = {1'b0,active_d2,5'b00101};
// Can't exceed 26 bit.
assign sum = _sum[43:18];
// MAC with pre-adder
DSP48E1 #(
.ACASCREG (0),
.ADREG (1),
.ALUMODEREG (0),
.AREG (0),
.AUTORESET_PATDET ("NO_RESET"),
.A_INPUT ("DIRECT"),
.BCASCREG (1),
.BREG (1),
.B_INPUT ("DIRECT"),
.CARRYINREG (0),
.CARRYINSELREG (0),
.CREG (0),
.DREG (0),
.INMODEREG (0),
.MASK (48'h3fffffffffff),
.MREG (1),
.OPMODEREG (1),
.PATTERN (48'h000000000000),
.PREG (1),
.SEL_MASK ("MASK"),
.SEL_PATTERN ("PATTERN"),
.USE_DPORT ("TRUE"),
.USE_MULT ("MULTIPLY"),
.USE_PATTERN_DETECT ("NO_PATDET"),
.USE_SIMD ("ONE48"))
i_dsp_mac (
.CLK (clk),
.A ({5'h0,data0[11],data0,12'h0}), // MSB aligned to 24-bit, 25th bit signed extended
.B ({coeff,6'b0}),
.C (48'h00),
.D ({data1[11],data1,12'h0}),
.MULTSIGNIN (1'b0),
.CARRYIN (1'b0),
.CARRYCASCIN (1'b0),
.ACIN (30'h0),
.BCIN (18'h0),
.PCIN (48'h0),
.P (_sum),
.MULTSIGNOUT (),
.CARRYOUT (),
.CARRYCASCOUT (),
.ACOUT (),
.BCOUT (),
.PCOUT (),
.ALUMODE (4'b0000),
.CARRYINSEL (3'h0),
.INMODE (5'b00100),
.OPMODE (opmode),
.PATTERNBDETECT (),
.PATTERNDETECT (),
.OVERFLOW (),
.UNDERFLOW (),
.CEA1 (1'b0),
.CEA2 (1'b0),
.CEAD (active),
.CEALUMODE (1'b0),
.CEB1 (1'b0),
.CEB2 (active),
.CEC (1'b0),
.CECARRYIN (1'b0),
.CECTRL (active),
.CED (1'b0),
.CEINMODE (1'b0),
.CEM (active_d1),
.CEP (active_d2),
.RSTA (1'b0),
.RSTALLCARRYIN (1'b0),
.RSTALUMODE (1'b0),
.RSTB (1'b0),
.RSTC (1'b0),
.RSTCTRL (1'b0),
.RSTD (1'b0),
.RSTINMODE (1'b0),
.RSTM (1'b0),
.RSTP (1'b0)
);
end else begin
reg signed [25:0] _sum = 'h00;
reg signed [12:0] pre_adder;
reg signed [11:0] coeff_d1;
reg signed [23:0] product = 'h00;
assign sum = _sum;
always @(posedge clk) begin
if (active == 1'b1) begin
pre_adder <= data0 + data1;
coeff_d1 <= coeff;
end
if (active_d1 == 1'b1) begin
product <= coeff_d1 * pre_adder;
end
if (reset == 1'b1 || ready == 1'b1) begin
_sum <= 'h00;
end else if (active_d2 == 1'b1) begin
_sum <= _sum + product;
end
end
end
endgenerate
always @(posedge clk) begin
if (reset == 1'b1) begin
ce_out <= 1'b0;
end else begin
ce_out <= ready;
end
end
always @(posedge clk) begin
if (ready == 1'b1) begin
filter_out <= sum;
end
end
endmodule
adi_library/axi_adc_decimate/m2k_decim.m
+46
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clear all;
close all;
decim_rate = 50000;
h_cic = dsp.CICDecimator(decim_rate,1,6);
gainCIC = (h_cic.DecimationFactor*h_cic.DifferentialDelay)^h_cic.NumSections
[h1, w1] = h_cic.freqz();
fs = 1;
fPass = 0.20;
fStop = 0.50;
ast = 70;
CICCompDecim = dsp.CICCompensationDecimator(h_cic, ...
'DecimationFactor',2,'PassbandFrequency',fPass, ...
'StopbandFrequency',fStop,'SampleRate',fs, ...
'StopbandAttenuation',ast);
[h2, w2] = CICCompDecim.freqz();
CICCompDecim.coeffs()
FC = dsp.FilterCascade(h_cic,CICCompDecim);
[h3, w3] = FC.freqz();
subplot(311); hold on;
plot(w1/pi, 20*log10(abs(h1)/gainCIC));
plot(w2/pi, 20*log10(abs(h2)));
hold off; grid
subplot(312); plot(w3/pi, 20*log10(abs(h3)/gainCIC)); grid
% M = 8; % Decimation factor
% Fp = 40; % Passband-edge frequency
% Fst = 60; % Stopband-edge frequency
% Ap = 0.1; % Passband peak-to-peak ripple
% Ast = 80; % Minimum stopband attenuation
% Fs = 800; % Sampling frequency
% HfdDecim = fdesign.decimator(M,'lowpass',Fp,Fst,Ap,Ast,Fs);
% HNyqDecim = design(HfdDecim,'kaiserwin','SystemObject', true);
%
% [h4, w4] = freqz(HNyqDecim);
% subplot(313); plot(w4/pi, 20*log10(abs(h4))); grid
nt = numerictype(1,12,11);
fdhdltool(h_cic, nt);
fdhdltool(CICCompDecim, nt)
adi_library/axi_adc_decimate/xgui/axi_adc_decimate_v1_0.tcl
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# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
ipgui::add_param $IPINST -name "Component_Name"
#Adding Page
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
ipgui::add_param $IPINST -name "CORRECTION_DISABLE" -parent ${Page_0}
}
proc update_PARAM_VALUE.CORRECTION_DISABLE { PARAM_VALUE.CORRECTION_DISABLE } {
# Procedure called to update CORRECTION_DISABLE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.CORRECTION_DISABLE { PARAM_VALUE.CORRECTION_DISABLE } {
# Procedure called to validate CORRECTION_DISABLE
return true
}
proc update_MODELPARAM_VALUE.CORRECTION_DISABLE { MODELPARAM_VALUE.CORRECTION_DISABLE PARAM_VALUE.CORRECTION_DISABLE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.CORRECTION_DISABLE}] ${MODELPARAM_VALUE.CORRECTION_DISABLE}
}