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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_adc_decimate #(
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parameter CORRECTION_DISABLE = 1) (
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input adc_clk,
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input adc_rst,
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input [15:0] adc_data_a,
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input [15:0] adc_data_b,
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input adc_valid_a,
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input adc_valid_b,
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output [15:0] adc_dec_data_a,
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output [15:0] adc_dec_data_b,
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output adc_dec_valid_a,
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output adc_dec_valid_b,
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output [ 2:0] adc_data_rate,
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output adc_oversampling_en,
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// axi interface
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input s_axi_aclk,
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input s_axi_aresetn,
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input s_axi_awvalid,
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input [ 6:0] s_axi_awaddr,
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input [ 2:0] s_axi_awprot,
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output s_axi_awready,
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input s_axi_wvalid,
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input [31:0] s_axi_wdata,
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input [ 3:0] s_axi_wstrb,
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output s_axi_wready,
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output s_axi_bvalid,
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output [ 1:0] s_axi_bresp,
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input s_axi_bready,
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input s_axi_arvalid,
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input [ 6:0] s_axi_araddr,
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input [ 2:0] s_axi_arprot,
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output s_axi_arready,
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output s_axi_rvalid,
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output [31:0] s_axi_rdata,
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output [ 1:0] s_axi_rresp,
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input s_axi_rready);
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// internal signals
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wire up_clk;
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wire up_rstn;
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wire [ 4:0] up_waddr;
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wire [31:0] up_wdata;
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wire up_wack;
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wire up_wreq;
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wire up_rack;
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wire [31:0] up_rdata;
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wire up_rreq;
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wire [ 4:0] up_raddr;
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wire [31:0] decimation_ratio;
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wire [ 2:0] filter_mask;
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wire adc_correction_enable_a;
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wire adc_correction_enable_b;
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wire [15:0] adc_correction_coefficient_a;
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wire [15:0] adc_correction_coefficient_b;
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// signal name changes
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assign up_clk = s_axi_aclk;
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assign up_rstn = s_axi_aresetn;
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assign adc_data_rate = filter_mask;
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assign adc_oversampling_en = |decimation_ratio;
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axi_adc_decimate_filter #(
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.CORRECTION_DISABLE(CORRECTION_DISABLE)
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) axi_adc_decimate_filter (
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.adc_clk (adc_clk),
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.adc_rst (adc_rst),
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.decimation_ratio (decimation_ratio),
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.filter_mask (filter_mask),
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.adc_correction_enable_a(adc_correction_enable_a),
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.adc_correction_enable_b(adc_correction_enable_b),
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.adc_correction_coefficient_a(adc_correction_coefficient_a),
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.adc_correction_coefficient_b(adc_correction_coefficient_b),
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.adc_valid_a(adc_valid_a),
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.adc_valid_b(adc_valid_b),
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.adc_data_a(adc_data_a[11:0]),
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.adc_data_b(adc_data_b[11:0]),
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.adc_dec_data_a(adc_dec_data_a),
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.adc_dec_data_b(adc_dec_data_b),
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.adc_dec_valid_a(adc_dec_valid_a),
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.adc_dec_valid_b(adc_dec_valid_b));
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axi_adc_decimate_reg axi_adc_decimate_reg (
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.clk (adc_clk),
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.adc_decimation_ratio (decimation_ratio),
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.adc_filter_mask (filter_mask),
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.adc_correction_enable_a(adc_correction_enable_a),
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.adc_correction_enable_b(adc_correction_enable_b),
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.adc_correction_coefficient_a(adc_correction_coefficient_a),
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.adc_correction_coefficient_b(adc_correction_coefficient_b),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq),
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.up_waddr (up_waddr),
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.up_wdata (up_wdata),
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.up_wack (up_wack),
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.up_rreq (up_rreq),
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.up_raddr (up_raddr),
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.up_rdata (up_rdata),
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.up_rack (up_rack));
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up_axi #(
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.AXI_ADDRESS_WIDTH(7)
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) i_up_axi (
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_axi_awvalid (s_axi_awvalid),
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.up_axi_awaddr (s_axi_awaddr),
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.up_axi_awready (s_axi_awready),
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.up_axi_wvalid (s_axi_wvalid),
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.up_axi_wdata (s_axi_wdata),
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.up_axi_wstrb (s_axi_wstrb),
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.up_axi_wready (s_axi_wready),
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.up_axi_bvalid (s_axi_bvalid),
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.up_axi_bresp (s_axi_bresp),
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.up_axi_bready (s_axi_bready),
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.up_axi_arvalid (s_axi_arvalid),
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.up_axi_araddr (s_axi_araddr),
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.up_axi_arready (s_axi_arready),
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.up_axi_rvalid (s_axi_rvalid),
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.up_axi_rresp (s_axi_rresp),
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.up_axi_rdata (s_axi_rdata),
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.up_axi_rready (s_axi_rready),
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.up_wreq (up_wreq),
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.up_waddr (up_waddr),
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.up_wdata (up_wdata),
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.up_wack (up_wack),
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.up_rreq (up_rreq),
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.up_raddr (up_raddr),
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.up_rdata (up_rdata),
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.up_rack (up_rack));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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