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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_adc_decimate_reg(
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input clk,
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output [31:0] adc_decimation_ratio,
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output [ 2:0] adc_filter_mask,
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output adc_correction_enable_a,
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output adc_correction_enable_b,
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output [15:0] adc_correction_coefficient_a,
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output [15:0] adc_correction_coefficient_b,
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// bus interface
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input up_rstn,
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input up_clk,
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input up_wreq,
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input [ 4:0] up_waddr,
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input [31:0] up_wdata,
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output reg up_wack,
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input up_rreq,
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input [ 4:0] up_raddr,
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output reg [31:0] up_rdata,
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output reg up_rack);
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// internal registers
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reg [31:0] up_version = 32'h00010000;
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reg [31:0] up_scratch = 32'h0;
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reg [31:0] up_decimation_ratio = 32'h0;
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reg [ 2:0] up_filter_mask = 32'h0;
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reg [ 1:0] up_config = 1'h0;
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reg [15:0] up_correction_coefficient_a = 16'h0;
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reg [15:0] up_correction_coefficient_b = 16'h0;
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_wack <= 'd0;
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up_scratch <= 'd0;
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up_decimation_ratio <= 'd0;
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up_filter_mask <= 'd0;
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up_config <= 'd0;
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up_correction_coefficient_a <= 'd0;
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up_correction_coefficient_b <= 'd0;
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end else begin
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up_wack <= up_wreq;
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if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h1)) begin
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up_scratch <= up_wdata;
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end
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if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h10)) begin
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up_decimation_ratio <= up_wdata;
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end
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if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h11)) begin
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up_filter_mask <= up_wdata[2:0];
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end
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if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h12)) begin
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up_config <= up_wdata[1:0];
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end
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if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h13)) begin
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up_correction_coefficient_a <= up_wdata[15:0];
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end
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if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h14)) begin
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up_correction_coefficient_b <= up_wdata[15:0];
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end
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end
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end
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// processor read interface
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_rack <= 'd0;
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up_rdata <= 'd0;
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end else begin
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up_rack <= up_rreq;
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if (up_rreq == 1'b1) begin
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case (up_raddr[4:0])
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5'h0: up_rdata <= up_version;
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5'h1: up_rdata <= up_scratch;
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5'h10: up_rdata <= up_decimation_ratio;
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5'h11: up_rdata <= { 29'h0, up_filter_mask };
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5'h12: up_rdata <= { 30'h0, up_config };
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5'h13: up_rdata <= { 16'h0, up_correction_coefficient_a };
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5'h14: up_rdata <= { 16'h0, up_correction_coefficient_b };
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default: up_rdata <= 0;
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endcase
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end else begin
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up_rdata <= 32'd0;
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end
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end
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end
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up_xfer_cntrl #(.DATA_WIDTH(69)) i_xfer_cntrl (
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_data_cntrl ({ up_config[1], // 1
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up_config[0], // 1
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up_correction_coefficient_b, // 16
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up_correction_coefficient_a, // 16
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up_decimation_ratio, // 32
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up_filter_mask}), // 3
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.up_xfer_done (),
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.d_rst (1'b0),
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.d_clk (clk),
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.d_data_cntrl ({ adc_correction_enable_b, // 1
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adc_correction_enable_a, // 1
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adc_correction_coefficient_b, // 16
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adc_correction_coefficient_a, // 16
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adc_decimation_ratio, // 32
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adc_filter_mask})); // 3
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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