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first commit after restructuring
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2020 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module adrv9001_tx #(
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parameter CMOS_LVDS_N = 0,
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parameter NUM_LANES = 4,
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parameter FPGA_TECHNOLOGY = 0,
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parameter USE_RX_CLK_FOR_TX = 0
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) (
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input ref_clk,
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input up_clk,
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input mssi_sync,
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input tx_output_enable,
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// physical interface (transmit)
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output tx_dclk_out_n_NC,
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output tx_dclk_out_p_dclk_out,
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input tx_dclk_in_n_NC,
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input tx_dclk_in_p_dclk_in,
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output tx_idata_out_n_idata0,
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output tx_idata_out_p_idata1,
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output tx_qdata_out_n_qdata2,
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output tx_qdata_out_p_qdata3,
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output tx_strobe_out_n_NC,
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output tx_strobe_out_p_strobe_out,
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input rx_clk_div,
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input rx_clk,
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input rx_ssi_rst,
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// internal resets and clocks
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input dac_rst,
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output dac_clk_div,
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input [7:0] dac_data_0,
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input [7:0] dac_data_1,
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input [7:0] dac_data_2,
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input [7:0] dac_data_3,
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input [7:0] dac_data_strb,
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input [7:0] dac_data_clk,
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input dac_data_valid
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);
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localparam SEVEN_SERIES = 1;
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localparam ULTRASCALE = 2;
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localparam ULTRASCALE_PLUS = 3;
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// internal wire
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wire tx_dclk_in_s;
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wire dac_fast_clk;
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wire [NUM_LANES-1:0] serdes_out_p;
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wire [NUM_LANES-1:0] serdes_out_n;
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wire [NUM_LANES-1:0] data_s0;
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wire [NUM_LANES-1:0] data_s1;
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wire [NUM_LANES-1:0] data_s2;
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wire [NUM_LANES-1:0] data_s3;
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wire [NUM_LANES-1:0] data_s4;
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wire [NUM_LANES-1:0] data_s5;
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wire [NUM_LANES-1:0] data_s6;
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wire [NUM_LANES-1:0] data_s7;
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wire ssi_rst;
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ad_serdes_out #(
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.CMOS_LVDS_N (CMOS_LVDS_N),
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.DDR_OR_SDR_N(1),
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.DATA_WIDTH(NUM_LANES),
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.SERDES_FACTOR(8),
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.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY))
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i_serdes (
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.rst (dac_rst|ssi_rst),
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.clk (dac_fast_clk),
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.div_clk (dac_clk_div),
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.loaden (1'b0),
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.data_oe (tx_output_enable),
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.data_s0 (data_s0),
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.data_s1 (data_s1),
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.data_s2 (data_s2),
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.data_s3 (data_s3),
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.data_s4 (data_s4),
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.data_s5 (data_s5),
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.data_s6 (data_s6),
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.data_s7 (data_s7),
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.data_out_se (),
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.data_out_p (serdes_out_p),
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.data_out_n (serdes_out_n));
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generate
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if (CMOS_LVDS_N == 0) begin
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IBUFGDS i_dac_clk_in_ibuf (
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.I (tx_dclk_in_p_dclk_in),
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.IB (tx_dclk_in_n_NC),
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.O (tx_dclk_in_s));
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assign data_s0 = {dac_data_clk[7],dac_data_strb[7],dac_data_1[7],dac_data_0[7]};
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assign data_s1 = {dac_data_clk[6],dac_data_strb[6],dac_data_1[6],dac_data_0[6]};
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assign data_s2 = {dac_data_clk[5],dac_data_strb[5],dac_data_1[5],dac_data_0[5]};
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assign data_s3 = {dac_data_clk[4],dac_data_strb[4],dac_data_1[4],dac_data_0[4]};
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assign data_s4 = {dac_data_clk[3],dac_data_strb[3],dac_data_1[3],dac_data_0[3]};
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assign data_s5 = {dac_data_clk[2],dac_data_strb[2],dac_data_1[2],dac_data_0[2]};
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assign data_s6 = {dac_data_clk[1],dac_data_strb[1],dac_data_1[1],dac_data_0[1]};
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assign data_s7 = {dac_data_clk[0],dac_data_strb[0],dac_data_1[0],dac_data_0[0]};
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assign {tx_dclk_out_p_dclk_out,
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tx_strobe_out_p_strobe_out,
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tx_qdata_out_p_qdata3,
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tx_idata_out_p_idata1} = serdes_out_p;
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assign {tx_dclk_out_n_NC,
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tx_strobe_out_n_NC,
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tx_qdata_out_n_qdata2,
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tx_idata_out_n_idata0} = serdes_out_n;
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end else begin
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IBUF i_dac_clk_in_ibuf (
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.I (tx_dclk_in_p_dclk_in),
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.O (tx_dclk_in_s));
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assign data_s0 = {dac_data_clk[7],dac_data_strb[7],dac_data_3[7],dac_data_2[7],dac_data_1[7],dac_data_0[7]};
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assign data_s1 = {dac_data_clk[6],dac_data_strb[6],dac_data_3[6],dac_data_2[6],dac_data_1[6],dac_data_0[6]};
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assign data_s2 = {dac_data_clk[5],dac_data_strb[5],dac_data_3[5],dac_data_2[5],dac_data_1[5],dac_data_0[5]};
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assign data_s3 = {dac_data_clk[4],dac_data_strb[4],dac_data_3[4],dac_data_2[4],dac_data_1[4],dac_data_0[4]};
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assign data_s4 = {dac_data_clk[3],dac_data_strb[3],dac_data_3[3],dac_data_2[3],dac_data_1[3],dac_data_0[3]};
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assign data_s5 = {dac_data_clk[2],dac_data_strb[2],dac_data_3[2],dac_data_2[2],dac_data_1[2],dac_data_0[2]};
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assign data_s6 = {dac_data_clk[1],dac_data_strb[1],dac_data_3[1],dac_data_2[1],dac_data_1[1],dac_data_0[1]};
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assign data_s7 = {dac_data_clk[0],dac_data_strb[0],dac_data_3[0],dac_data_2[0],dac_data_1[0],dac_data_0[0]};
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assign {tx_dclk_out_p_dclk_out,
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tx_strobe_out_p_strobe_out,
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tx_qdata_out_p_qdata3,
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tx_qdata_out_n_qdata2,
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tx_idata_out_p_idata1,
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tx_idata_out_n_idata0} = serdes_out_p;
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assign {tx_dclk_out_n_NC,
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tx_strobe_out_n_NC} = 2'b0;
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end
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if (USE_RX_CLK_FOR_TX == 0) begin
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if (FPGA_TECHNOLOGY == SEVEN_SERIES) begin
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// SERDES fast clock
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BUFIO i_dac_clk_in_gbuf (
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.I (tx_dclk_in_s),
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.O (dac_fast_clk));
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// SERDES slow clock
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BUFR #(.BUFR_DIVIDE("4")) i_dac_div_clk_rbuf (
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.CLR (mssi_sync),
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.CE (1'b1),
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.I (tx_dclk_in_s),
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.O (dac_clk_div_s));
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BUFG I_bufg (
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.I (dac_clk_div_s),
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.O (dac_clk_div)
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);
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assign ssi_rst = mssi_sync;
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end else begin
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reg mssi_sync_d = 1'b0;
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reg mssi_sync_2d = 1'b0;
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always @(posedge dac_fast_clk) begin
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mssi_sync_d <= mssi_sync;
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mssi_sync_2d <= mssi_sync_d;
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end
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BUFGCE #(
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.CE_TYPE ("SYNC"),
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.IS_CE_INVERTED (1'b0),
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.IS_I_INVERTED (1'b0)
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) i_dac_clk_in_gbuf (
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.O (dac_fast_clk),
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.CE (1'b1),
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.I (tx_dclk_in_s)
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);
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BUFGCE_DIV #(
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.BUFGCE_DIVIDE (4),
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.IS_CE_INVERTED (1'b0),
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.IS_CLR_INVERTED (1'b0),
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.IS_I_INVERTED (1'b0)
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) i_dac_div_clk_rbuf (
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.O (dac_clk_div),
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.CE (1'b1),
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.CLR (mssi_sync_2d),
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.I (tx_dclk_in_s)
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);
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assign ssi_rst = mssi_sync_2d;
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end
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end else begin
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assign dac_fast_clk = rx_clk;
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assign dac_clk_div = rx_clk_div;
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assign ssi_rst = rx_ssi_rst;
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end
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endgenerate
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endmodule
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