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josh
2023-04-13 13:33:41 +08:00
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adi_library/axi_gpreg/Makefile
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####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
LIBRARY_NAME := axi_gpreg
GENERIC_DEPS += ../common/ad_rst.v
GENERIC_DEPS += ../common/up_axi.v
GENERIC_DEPS += ../common/up_clock_mon.v
GENERIC_DEPS += axi_gpreg.v
GENERIC_DEPS += axi_gpreg_clock_mon.v
GENERIC_DEPS += axi_gpreg_io.v
XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc
XILINX_DEPS += axi_gpreg_constr.ttcl
XILINX_DEPS += axi_gpreg_ip.tcl
include ../scripts/library.mk
adi_library/axi_gpreg/axi_gpreg.cache/wt/project.wpc
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version:1
6d6f64655f636f756e7465727c42617463684d6f6465:1
eof:
adi_library/axi_gpreg/axi_gpreg.hw/axi_gpreg.lpr
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<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
<labtools version="1" minor="0"/>
adi_library/axi_gpreg/axi_gpreg.v
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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_gpreg #(
parameter integer ID = 0,
parameter integer NUM_OF_IO = 8,
parameter integer NUM_OF_CLK_MONS = 8,
parameter integer BUF_ENABLE_0 = 1,
parameter integer BUF_ENABLE_1 = 1,
parameter integer BUF_ENABLE_2 = 1,
parameter integer BUF_ENABLE_3 = 1,
parameter integer BUF_ENABLE_4 = 1,
parameter integer BUF_ENABLE_5 = 1,
parameter integer BUF_ENABLE_6 = 1,
parameter integer BUF_ENABLE_7 = 1)
(
// io
output [ 31:0] up_gp_ioenb_0,
output [ 31:0] up_gp_out_0,
input [ 31:0] up_gp_in_0,
output [ 31:0] up_gp_ioenb_1,
output [ 31:0] up_gp_out_1,
input [ 31:0] up_gp_in_1,
output [ 31:0] up_gp_ioenb_2,
output [ 31:0] up_gp_out_2,
input [ 31:0] up_gp_in_2,
output [ 31:0] up_gp_ioenb_3,
output [ 31:0] up_gp_out_3,
input [ 31:0] up_gp_in_3,
output [ 31:0] up_gp_ioenb_4,
output [ 31:0] up_gp_out_4,
input [ 31:0] up_gp_in_4,
output [ 31:0] up_gp_ioenb_5,
output [ 31:0] up_gp_out_5,
input [ 31:0] up_gp_in_5,
output [ 31:0] up_gp_ioenb_6,
output [ 31:0] up_gp_out_6,
input [ 31:0] up_gp_in_6,
output [ 31:0] up_gp_ioenb_7,
output [ 31:0] up_gp_out_7,
input [ 31:0] up_gp_in_7,
// clock monitors
input d_clk_0,
input d_clk_1,
input d_clk_2,
input d_clk_3,
input d_clk_4,
input d_clk_5,
input d_clk_6,
input d_clk_7,
// axi interface
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [ 15:0] s_axi_awaddr,
output s_axi_awready,
input s_axi_wvalid,
input [ 31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [ 15:0] s_axi_araddr,
output s_axi_arready,
output s_axi_rvalid,
output [ 31:0] s_axi_rdata,
output [ 1:0] s_axi_rresp,
input s_axi_rready,
input [ 2:0] s_axi_awprot,
input [ 2:0] s_axi_arprot);
// version
localparam [31:0] PCORE_VERSION = 32'h00040063;
localparam integer BUF_ENABLE[7:0] = {BUF_ENABLE_7, BUF_ENABLE_6, BUF_ENABLE_5, BUF_ENABLE_4,
BUF_ENABLE_3, BUF_ENABLE_2, BUF_ENABLE_1, BUF_ENABLE_0};
// internal registers
reg up_wack_d = 'd0;
reg up_rack_d = 'd0;
reg [ 31:0] up_rdata_d = 'd0;
reg up_wack = 'd0;
reg [ 31:0] up_scratch = 'd0;
reg up_rack = 'd0;
reg [ 31:0] up_rdata = 'd0;
// internal signals
wire up_rstn;
wire up_clk;
wire up_wreq;
wire [ 13:0] up_waddr;
wire [ 31:0] up_wdata;
wire up_rreq;
wire [ 13:0] up_raddr;
wire up_wreq_s;
wire up_rreq_s;
wire [ 31:0] up_gp_ioenb_s[7:0];
wire [ 31:0] up_gp_out_s[7:0];
wire [ 31:0] up_gp_in_s[7:0];
wire [ 7:0] d_clk_s;
wire [ 16:0] up_wack_s;
wire [ 16:0] up_rack_s;
wire [ 31:0] up_rdata_s[16:0];
// signal name changes
assign up_rstn = s_axi_aresetn;
assign up_clk = s_axi_aclk;
// split-up interfaces
assign up_gp_ioenb_0 = up_gp_ioenb_s[0];
assign up_gp_out_0 = up_gp_out_s[0];
assign up_gp_in_s[0] = up_gp_in_0;
assign up_gp_ioenb_1 = up_gp_ioenb_s[1];
assign up_gp_out_1 = up_gp_out_s[1];
assign up_gp_in_s[1] = up_gp_in_1;
assign up_gp_ioenb_2 = up_gp_ioenb_s[2];
assign up_gp_out_2 = up_gp_out_s[2];
assign up_gp_in_s[2] = up_gp_in_2;
assign up_gp_ioenb_3 = up_gp_ioenb_s[3];
assign up_gp_out_3 = up_gp_out_s[3];
assign up_gp_in_s[3] = up_gp_in_3;
assign up_gp_ioenb_4 = up_gp_ioenb_s[4];
assign up_gp_out_4 = up_gp_out_s[4];
assign up_gp_in_s[4] = up_gp_in_4;
assign up_gp_ioenb_5 = up_gp_ioenb_s[5];
assign up_gp_out_5 = up_gp_out_s[5];
assign up_gp_in_s[5] = up_gp_in_5;
assign up_gp_ioenb_6 = up_gp_ioenb_s[6];
assign up_gp_out_6 = up_gp_out_s[6];
assign up_gp_in_s[6] = up_gp_in_6;
assign up_gp_ioenb_7 = up_gp_ioenb_s[7];
assign up_gp_out_7 = up_gp_out_s[7];
assign up_gp_in_s[7] = up_gp_in_7;
assign d_clk_s[0] = d_clk_0;
assign d_clk_s[1] = d_clk_1;
assign d_clk_s[2] = d_clk_2;
assign d_clk_s[3] = d_clk_3;
assign d_clk_s[4] = d_clk_4;
assign d_clk_s[5] = d_clk_5;
assign d_clk_s[6] = d_clk_6;
assign d_clk_s[7] = d_clk_7;
// up signals
always @(posedge up_clk or negedge up_rstn) begin
if (up_rstn == 1'b0) begin
up_wack_d <= 1'd0;
up_rack_d <= 1'd0;
up_rdata_d <= 32'd0;
end else begin
up_wack_d <= | up_wack_s;
up_rack_d <= | up_rack_s;
up_rdata_d <= up_rdata_s[ 0] | up_rdata_s[ 1] | up_rdata_s[ 2] |
up_rdata_s[ 3] | up_rdata_s[ 4] | up_rdata_s[ 5] | up_rdata_s[ 6] |
up_rdata_s[ 7] | up_rdata_s[ 8] | up_rdata_s[ 9] | up_rdata_s[10] |
up_rdata_s[11] | up_rdata_s[12] | up_rdata_s[13] | up_rdata_s[14] |
up_rdata_s[15] | up_rdata_s[16];
end
end
// generic register map
assign up_wack_s[16] = up_wack;
assign up_rack_s[16] = up_rack;
assign up_rdata_s[16] = up_rdata;
// decode block select
assign up_wreq_s = (up_waddr[13:8] == 6'h00) ? up_wreq : 1'b0;
assign up_rreq_s = (up_raddr[13:8] == 6'h00) ? up_rreq : 1'b0;
// processor write interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_wack <= 'd0;
up_scratch <= 'd0;
end else begin
up_wack <= up_wreq_s;
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin
up_scratch <= up_wdata;
end
end
end
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rack <= 'd0;
up_rdata <= 'd0;
end else begin
up_rack <= up_rreq_s;
if (up_rreq_s == 1'b1) begin
case (up_raddr[7:0])
8'h00: up_rdata <= PCORE_VERSION;
8'h01: up_rdata <= ID;
8'h02: up_rdata <= up_scratch;
default: up_rdata <= 0;
endcase
end else begin
up_rdata <= 32'd0;
end
end
end
// instantiations
genvar n;
generate
// gpio
if (NUM_OF_IO < 8) begin
for (n = NUM_OF_IO; n < 8; n = n + 1) begin: g_unused_io
assign up_gp_ioenb_s[n] = 32'd0;
assign up_gp_out_s[n] = 32'd0;
assign up_wack_s[n] = 1'd0;
assign up_rdata_s[n] = 32'd0;
assign up_rack_s[n] = 1'd0;
end
end
for (n = 0; n < NUM_OF_IO; n = n + 1) begin: g_io
axi_gpreg_io #(.ID (16+n)) i_gpreg_io (
.up_gp_ioenb (up_gp_ioenb_s[n]),
.up_gp_out (up_gp_out_s[n]),
.up_gp_in (up_gp_in_s[n]),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[n]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[n]),
.up_rack (up_rack_s[n]));
end
// clock monitors
if (NUM_OF_CLK_MONS < 8) begin
for (n = NUM_OF_CLK_MONS; n < 8; n = n + 1) begin: g_unused_clock_mon
assign up_wack_s[(8+n)] = 1'd0;
assign up_rdata_s[(8+n)] = 32'd0;
assign up_rack_s[(8+n)] = 1'd0;
end
end
for (n = 0; n < NUM_OF_CLK_MONS; n = n + 1) begin: g_clock_mon
axi_gpreg_clock_mon #(
.ID (32+n),
.BUF_ENABLE (BUF_ENABLE[n]))
i_gpreg_clock_mon (
.d_clk (d_clk_s[n]),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[(8+n)]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[(8+n)]),
.up_rack (up_rack_s[(8+n)]));
end
endgenerate
up_axi i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_d),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_d),
.up_rack (up_rack_d));
endmodule
// ***************************************************************************
// ***************************************************************************
adi_library/axi_gpreg/axi_gpreg.xpr
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<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
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<MsgAttr Name="RuleId" Val="1"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
<MsgAttr Name="StringsToMatch" Val="Evaluation"/>
<MsgAttr Name="StringsToMatch" Val="features"/>
<MsgAttr Name="StringsToMatch" Val="should"/>
<MsgAttr Name="StringsToMatch" Val="NOT"/>
<MsgAttr Name="StringsToMatch" Val="be"/>
<MsgAttr Name="StringsToMatch" Val="used"/>
<MsgAttr Name="StringsToMatch" Val="in"/>
<MsgAttr Name="StringsToMatch" Val="production"/>
<MsgAttr Name="StringsToMatch" Val="systems."/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val="Place 30-73"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="10"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
<MsgAttr Name="StringsToMatch" Val="axi_spi"/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val=""/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="11"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
<MsgAttr Name="StringsToMatch" Val="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY"/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val="BD 41-1343"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="2"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val="BD 41-1306"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="3"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="ERROR"/>
<MsgAttr Name="Id" Val="BD 41-1276"/>
<MsgAttr Name="Severity" Val="CRITICAL WARNING"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="4"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="IP_Flow 19-3656"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="5"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="IP_Flow 19-4623"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="6"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="IP_Flow 19-459"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="7"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="Synth 8-3331"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="8"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="Designutils 20-3303"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="9"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
<MsgAttr Name="StringsToMatch" Val="HDPYFinalizeIO"/>
</MsgRule>
<Board/>
<DashboardSummary Version="1" Minor="0">
<Dashboards>
<Dashboard Name="default_dashboard">
<Gadgets>
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
</Gadget>
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
</Gadget>
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
</Gadget>
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
</Gadget>
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
</Gadget>
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
</Gadget>
</Gadgets>
</Dashboard>
<CurrentDashboard>default_dashboard</CurrentDashboard>
</Dashboards>
</DashboardSummary>
<BootPmcSettings Version="1" Minor="0">
<Parameters>
<Parameter Name="PMC_CDO.ATTRS.LOADADDR" Value="" Type="string"/>
<Parameter Name="BOOT.PMC.QSPI_ENABLE" Value="0" Type="string"/>
<Parameter Name="BOOT.PMC.QSPI_FB_CLK" Value="0" Type="string"/>
<Parameter Name="BOOT.PMC.QSPI_FREQ" Value="300" Type="string"/>
<Parameter Name="BOOT.PMC.QSPI_BUS_WIDTH" Value="x1" Type="string"/>
<Parameter Name="BOOT.PMC.QSPI_DATA_MODE" Value="Single" Type="string"/>
<Parameter Name="BOOT.PMC.SD0_ENABLE" Value="0" Type="string"/>
<Parameter Name="BOOT.PMC.SD0_FREQ" Value="200" Type="string"/>
<Parameter Name="BOOT.PMC.SD0_SLOT_TYPE" Value="SD 2.0" Type="string"/>
<Parameter Name="BOOT.PMC.SD0_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
<Parameter Name="BOOT.PMC.SD1_ENABLE" Value="0" Type="string"/>
<Parameter Name="BOOT.PMC.SD1_FREQ" Value="200" Type="string"/>
<Parameter Name="BOOT.PMC.SD1_SLOT_TYPE" Value="SD 2.0" Type="string"/>
<Parameter Name="BOOT.PMC.SD1_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
<Parameter Name="BOOT.PMC.OSPI_ENABLE" Value="0" Type="string"/>
<Parameter Name="BOOT.PMC.OSPI_FREQ" Value="300" Type="string"/>
<Parameter Name="BOOT.USB_ENABLE" Value="0" Type="string"/>
<Parameter Name="BOOT.PMC.SMAP_ENABLE" Value="0" Type="string"/>
<Parameter Name="BOOT.PMC.SMAP_DATA_WIDTH" Value="32 Bit" Type="string"/>
<Parameter Name="BOOT.PMC.OSC_FREQ" Value="33.333" Type="string"/>
<Parameter Name="BOOT.SECONDARY.PCIE_ENABLE" Value="0" Type="string"/>
</Parameters>
</BootPmcSettings>
</Project>
adi_library/axi_gpreg/axi_gpreg_clock_mon.v
+143
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@@ -0,0 +1,143 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_gpreg_clock_mon #(
parameter ID = 0,
parameter BUF_ENABLE = 0) (
// clock
input d_clk,
// bus interface
input up_rstn,
input up_clk,
input up_wreq,
input [13:0] up_waddr,
input [31:0] up_wdata,
output reg up_wack,
input up_rreq,
input [13:0] up_raddr,
output reg [31:0] up_rdata,
output reg up_rack);
// internal registers
reg up_d_preset = 'd0;
reg up_d_resetn = 'd0;
// internal signals
wire up_wreq_s;
wire up_rreq_s;
wire [31:0] up_d_count_s;
wire d_rst;
wire d_clk_g;
// decode block select
assign up_wreq_s = (up_waddr[13:4] == ID) ? up_wreq : 1'b0;
assign up_rreq_s = (up_raddr[13:4] == ID) ? up_rreq : 1'b0;
// processor write interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_d_preset <= 1'd1;
up_wack <= 'd0;
up_d_resetn <= 'd0;
end else begin
up_d_preset <= ~up_d_resetn;
up_wack <= up_wreq_s;
if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h0)) begin
up_d_resetn <= up_wdata[0];
end
end
end
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rack <= 'd0;
up_rdata <= 'd0;
end else begin
up_rack <= up_rreq_s;
if (up_rreq_s == 1'b1) begin
case (up_raddr[3:0])
4'b0000: up_rdata <= {31'd0, up_d_resetn};
4'b0010: up_rdata <= up_d_count_s;
default: up_rdata <= 32'd0;
endcase
end else begin
up_rdata <= 32'd0;
end
end
end
// clock monitor
up_clock_mon i_clock_mon (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_d_count (up_d_count_s),
.d_rst (d_rst),
.d_clk (d_clk_g));
ad_rst i_d_rst_reg (
.rst_async (up_d_preset),
.clk (d_clk_g),
.rstn (),
.rst (d_rst));
generate
if (BUF_ENABLE == 1) begin
BUFG i_bufg (
.I (d_clk),
.O (d_clk_g));
end else begin
assign d_clk_g = d_clk;
end
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************
adi_library/axi_gpreg/axi_gpreg_constr.ttcl
+18
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@@ -0,0 +1,18 @@
<: set ComponentName [getComponentNameString] :>
<: setOutputDirectory "./" :>
<: setFileName [ttcl_add $ComponentName "_constr"] :>
<: setFileExtension ".xdc" :>
<: setFileProcessingOrder late :>
<: set num_of_clk_mons [getBooleanValue "NUM_OF_CLK_MONS"] :>
<: if { $num_of_clk_mons > 0 } { :>
set_property ASYNC_REG true [get_cells -hierarchical -filter {name =~ *up_count_running_m*}]
set_property ASYNC_REG true [get_cells -hierarchical -filter {name =~ *d_count_run_m*}]
set_property ASYNC_REG true [get_cells -hierarchical -filter {name =~ *up_d_count_reg*}]
set_false_path -from [get_cells -hierarchical -filter {name =~ *d_count_run_m3_reg* && IS_SEQUENTIAL}] -to [get_cells -hierarchical -filter {name =~ *up_count_running_m1_reg* && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hierarchical -filter {name =~ *up_count_run_reg* && IS_SEQUENTIAL}] -to [get_cells -hierarchical -filter {name =~ *d_count_run_m1_reg* && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hierarchical -filter {name =~ *d_count_reg* && IS_SEQUENTIAL}] -to [get_cells -hierarchical -filter {name =~ *up_d_count_reg* && IS_SEQUENTIAL}]
<: } :>
adi_library/axi_gpreg/axi_gpreg_io.v
+116
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@@ -0,0 +1,116 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_gpreg_io #(
parameter ID = 0) (
// gpio
output reg [31:0] up_gp_ioenb,
output reg [31:0] up_gp_out,
input [31:0] up_gp_in,
// bus interface
input up_rstn,
input up_clk,
input up_wreq,
input [13:0] up_waddr,
input [31:0] up_wdata,
output reg up_wack,
input up_rreq,
input [13:0] up_raddr,
output reg [31:0] up_rdata,
output reg up_rack);
// internal registers
// internal signals
wire up_wreq_s;
wire up_rreq_s;
// decode block select
assign up_wreq_s = (up_waddr[13:4] == ID) ? up_wreq : 1'b0;
assign up_rreq_s = (up_raddr[13:4] == ID) ? up_rreq : 1'b0;
// processor write interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_wack <= 'd0;
up_gp_ioenb <= {32{1'b1}};
up_gp_out <= 'd0;
end else begin
up_wack <= up_wreq_s;
if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h0)) begin
up_gp_ioenb <= up_wdata;
end
if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h1)) begin
up_gp_out <= up_wdata;
end
end
end
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rack <= 'd0;
up_rdata <= 'd0;
end else begin
up_rack <= up_rreq_s;
if (up_rreq_s == 1'b1) begin
case (up_raddr[3:0])
4'b0000: up_rdata <= up_gp_ioenb;
4'b0001: up_rdata <= up_gp_out;
4'b0010: up_rdata <= up_gp_in;
default: up_rdata <= 32'd0;
endcase
end else begin
up_rdata <= 32'd0;
end
end
end
endmodule
// ***************************************************************************
// ***************************************************************************
adi_library/axi_gpreg/axi_gpreg_ip.tcl
+57
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# ip
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
adi_ip_create axi_gpreg
adi_ip_files axi_gpreg [list \
"$ad_hdl_dir/library/common/ad_rst.v" \
"$ad_hdl_dir/library/common/up_clock_mon.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
"$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \
"axi_gpreg_io.v" \
"axi_gpreg_constr.ttcl" \
"axi_gpreg_clock_mon.v" \
"axi_gpreg.v" ]
adi_ip_properties axi_gpreg
adi_ip_ttcl axi_gpreg "axi_gpreg_constr.ttcl"
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_IO')) > 0} \
[ipx::get_ports up_gp_*_0 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_IO')) > 1} \
[ipx::get_ports up_gp_*_1 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_IO')) > 2} \
[ipx::get_ports up_gp_*_2 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_IO')) > 3} \
[ipx::get_ports up_gp_*_3 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_IO')) > 4} \
[ipx::get_ports up_gp_*_4 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_IO')) > 5} \
[ipx::get_ports up_gp_*_5 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_IO')) > 6} \
[ipx::get_ports up_gp_*_6 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_IO')) > 7} \
[ipx::get_ports up_gp_*_7 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLK_MONS')) > 0} \
[ipx::get_ports d_clk_0 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLK_MONS')) > 1} \
[ipx::get_ports d_clk_1 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLK_MONS')) > 2} \
[ipx::get_ports d_clk_2 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLK_MONS')) > 3} \
[ipx::get_ports d_clk_3 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLK_MONS')) > 4} \
[ipx::get_ports d_clk_4 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLK_MONS')) > 5} \
[ipx::get_ports d_clk_5 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLK_MONS')) > 6} \
[ipx::get_ports d_clk_6 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLK_MONS')) > 7} \
[ipx::get_ports d_clk_7 -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports -filter "direction==in" -of_objects [ipx::current_core]]
ipx::save_core [ipx::current_core]
adi_library/axi_gpreg/component.xml
+1667
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adi_library/axi_gpreg/xgui/axi_gpreg_v1_0.tcl
+175
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# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
ipgui::add_param $IPINST -name "Component_Name"
#Adding Page
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
ipgui::add_param $IPINST -name "BUF_ENABLE_0" -parent ${Page_0}
ipgui::add_param $IPINST -name "BUF_ENABLE_1" -parent ${Page_0}
ipgui::add_param $IPINST -name "BUF_ENABLE_2" -parent ${Page_0}
ipgui::add_param $IPINST -name "BUF_ENABLE_3" -parent ${Page_0}
ipgui::add_param $IPINST -name "BUF_ENABLE_4" -parent ${Page_0}
ipgui::add_param $IPINST -name "BUF_ENABLE_5" -parent ${Page_0}
ipgui::add_param $IPINST -name "BUF_ENABLE_6" -parent ${Page_0}
ipgui::add_param $IPINST -name "BUF_ENABLE_7" -parent ${Page_0}
ipgui::add_param $IPINST -name "ID" -parent ${Page_0}
ipgui::add_param $IPINST -name "NUM_OF_CLK_MONS" -parent ${Page_0}
ipgui::add_param $IPINST -name "NUM_OF_IO" -parent ${Page_0}
}
proc update_PARAM_VALUE.BUF_ENABLE_0 { PARAM_VALUE.BUF_ENABLE_0 } {
# Procedure called to update BUF_ENABLE_0 when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.BUF_ENABLE_0 { PARAM_VALUE.BUF_ENABLE_0 } {
# Procedure called to validate BUF_ENABLE_0
return true
}
proc update_PARAM_VALUE.BUF_ENABLE_1 { PARAM_VALUE.BUF_ENABLE_1 } {
# Procedure called to update BUF_ENABLE_1 when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.BUF_ENABLE_1 { PARAM_VALUE.BUF_ENABLE_1 } {
# Procedure called to validate BUF_ENABLE_1
return true
}
proc update_PARAM_VALUE.BUF_ENABLE_2 { PARAM_VALUE.BUF_ENABLE_2 } {
# Procedure called to update BUF_ENABLE_2 when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.BUF_ENABLE_2 { PARAM_VALUE.BUF_ENABLE_2 } {
# Procedure called to validate BUF_ENABLE_2
return true
}
proc update_PARAM_VALUE.BUF_ENABLE_3 { PARAM_VALUE.BUF_ENABLE_3 } {
# Procedure called to update BUF_ENABLE_3 when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.BUF_ENABLE_3 { PARAM_VALUE.BUF_ENABLE_3 } {
# Procedure called to validate BUF_ENABLE_3
return true
}
proc update_PARAM_VALUE.BUF_ENABLE_4 { PARAM_VALUE.BUF_ENABLE_4 } {
# Procedure called to update BUF_ENABLE_4 when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.BUF_ENABLE_4 { PARAM_VALUE.BUF_ENABLE_4 } {
# Procedure called to validate BUF_ENABLE_4
return true
}
proc update_PARAM_VALUE.BUF_ENABLE_5 { PARAM_VALUE.BUF_ENABLE_5 } {
# Procedure called to update BUF_ENABLE_5 when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.BUF_ENABLE_5 { PARAM_VALUE.BUF_ENABLE_5 } {
# Procedure called to validate BUF_ENABLE_5
return true
}
proc update_PARAM_VALUE.BUF_ENABLE_6 { PARAM_VALUE.BUF_ENABLE_6 } {
# Procedure called to update BUF_ENABLE_6 when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.BUF_ENABLE_6 { PARAM_VALUE.BUF_ENABLE_6 } {
# Procedure called to validate BUF_ENABLE_6
return true
}
proc update_PARAM_VALUE.BUF_ENABLE_7 { PARAM_VALUE.BUF_ENABLE_7 } {
# Procedure called to update BUF_ENABLE_7 when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.BUF_ENABLE_7 { PARAM_VALUE.BUF_ENABLE_7 } {
# Procedure called to validate BUF_ENABLE_7
return true
}
proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } {
# Procedure called to update ID when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } {
# Procedure called to validate ID
return true
}
proc update_PARAM_VALUE.NUM_OF_CLK_MONS { PARAM_VALUE.NUM_OF_CLK_MONS } {
# Procedure called to update NUM_OF_CLK_MONS when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.NUM_OF_CLK_MONS { PARAM_VALUE.NUM_OF_CLK_MONS } {
# Procedure called to validate NUM_OF_CLK_MONS
return true
}
proc update_PARAM_VALUE.NUM_OF_IO { PARAM_VALUE.NUM_OF_IO } {
# Procedure called to update NUM_OF_IO when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.NUM_OF_IO { PARAM_VALUE.NUM_OF_IO } {
# Procedure called to validate NUM_OF_IO
return true
}
proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID}
}
proc update_MODELPARAM_VALUE.NUM_OF_IO { MODELPARAM_VALUE.NUM_OF_IO PARAM_VALUE.NUM_OF_IO } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.NUM_OF_IO}] ${MODELPARAM_VALUE.NUM_OF_IO}
}
proc update_MODELPARAM_VALUE.NUM_OF_CLK_MONS { MODELPARAM_VALUE.NUM_OF_CLK_MONS PARAM_VALUE.NUM_OF_CLK_MONS } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.NUM_OF_CLK_MONS}] ${MODELPARAM_VALUE.NUM_OF_CLK_MONS}
}
proc update_MODELPARAM_VALUE.BUF_ENABLE_0 { MODELPARAM_VALUE.BUF_ENABLE_0 PARAM_VALUE.BUF_ENABLE_0 } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.BUF_ENABLE_0}] ${MODELPARAM_VALUE.BUF_ENABLE_0}
}
proc update_MODELPARAM_VALUE.BUF_ENABLE_1 { MODELPARAM_VALUE.BUF_ENABLE_1 PARAM_VALUE.BUF_ENABLE_1 } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.BUF_ENABLE_1}] ${MODELPARAM_VALUE.BUF_ENABLE_1}
}
proc update_MODELPARAM_VALUE.BUF_ENABLE_2 { MODELPARAM_VALUE.BUF_ENABLE_2 PARAM_VALUE.BUF_ENABLE_2 } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.BUF_ENABLE_2}] ${MODELPARAM_VALUE.BUF_ENABLE_2}
}
proc update_MODELPARAM_VALUE.BUF_ENABLE_3 { MODELPARAM_VALUE.BUF_ENABLE_3 PARAM_VALUE.BUF_ENABLE_3 } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.BUF_ENABLE_3}] ${MODELPARAM_VALUE.BUF_ENABLE_3}
}
proc update_MODELPARAM_VALUE.BUF_ENABLE_4 { MODELPARAM_VALUE.BUF_ENABLE_4 PARAM_VALUE.BUF_ENABLE_4 } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.BUF_ENABLE_4}] ${MODELPARAM_VALUE.BUF_ENABLE_4}
}
proc update_MODELPARAM_VALUE.BUF_ENABLE_5 { MODELPARAM_VALUE.BUF_ENABLE_5 PARAM_VALUE.BUF_ENABLE_5 } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.BUF_ENABLE_5}] ${MODELPARAM_VALUE.BUF_ENABLE_5}
}
proc update_MODELPARAM_VALUE.BUF_ENABLE_6 { MODELPARAM_VALUE.BUF_ENABLE_6 PARAM_VALUE.BUF_ENABLE_6 } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.BUF_ENABLE_6}] ${MODELPARAM_VALUE.BUF_ENABLE_6}
}
proc update_MODELPARAM_VALUE.BUF_ENABLE_7 { MODELPARAM_VALUE.BUF_ENABLE_7 PARAM_VALUE.BUF_ENABLE_7 } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.BUF_ENABLE_7}] ${MODELPARAM_VALUE.BUF_ENABLE_7}
}