Archived
first commit after restructuring
This commit is contained in:
@@ -0,0 +1,26 @@
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####################################################################################
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## Copyright 2018(c) Analog Devices, Inc.
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## Auto-generated, do not modify!
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||||
####################################################################################
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||||
LIBRARY_NAME := axi_i2s_adi
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||||
GENERIC_DEPS += ../common/axi_ctrlif.vhd
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GENERIC_DEPS += ../common/axi_streaming_dma_rx_fifo.vhd
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GENERIC_DEPS += ../common/axi_streaming_dma_tx_fifo.vhd
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GENERIC_DEPS += ../common/dma_fifo.vhd
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||||
GENERIC_DEPS += ../common/pl330_dma_fifo.vhd
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GENERIC_DEPS += axi_i2s_adi.vhd
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GENERIC_DEPS += fifo_synchronizer.vhd
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GENERIC_DEPS += i2s_clkgen.vhd
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GENERIC_DEPS += i2s_controller.vhd
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GENERIC_DEPS += i2s_rx.vhd
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GENERIC_DEPS += i2s_tx.vhd
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XILINX_DEPS += axi_i2s_adi_constr.xdc
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XILINX_DEPS += axi_i2s_adi_ip.tcl
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XILINX_DEPS += ../axi_i2s_adi/i2s.xml
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XILINX_DEPS += ../axi_i2s_adi/i2s_rtl.xml
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include ../scripts/library.mk
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@@ -0,0 +1,3 @@
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version:1
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6d6f64655f636f756e7465727c42617463684d6f6465:1
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eof:
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@@ -0,0 +1,6 @@
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<?xml version="1.0" encoding="UTF-8"?>
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||||
<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
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||||
<!-- -->
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||||
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
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||||
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<labtools version="1" minor="0"/>
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@@ -0,0 +1,482 @@
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-- ***************************************************************************
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||||
-- ***************************************************************************
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||||
-- Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- In this HDL repository, there are many different and unique modules, consisting
|
||||
-- of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
-- developed independently, and may be accompanied by separate and unique license
|
||||
-- terms.
|
||||
--
|
||||
-- The user should read each of these license terms, and understand the
|
||||
-- freedoms and responsibilities that he or she has by using this source/core.
|
||||
--
|
||||
-- This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
-- A PARTICULAR PURPOSE.
|
||||
--
|
||||
-- Redistribution and use of source or resulting binaries, with or without modification
|
||||
-- of this file, are permitted under one of the following two license terms:
|
||||
--
|
||||
-- 1. The GNU General Public License version 2 as published by the
|
||||
-- Free Software Foundation, which can be found in the top level directory
|
||||
-- of this repository (LICENSE_GPL2), and also online at:
|
||||
-- <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
--
|
||||
-- OR
|
||||
--
|
||||
-- 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
-- of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
-- https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
-- This will allow to generate bit files and not release the source code,
|
||||
-- as long as it attaches to an ADI device.
|
||||
--
|
||||
-- ***************************************************************************
|
||||
-- ***************************************************************************
|
||||
|
||||
library ieee;
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||||
use ieee.std_logic_1164.all;
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||||
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||||
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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library work;
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use work.i2s_controller;
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library work;
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use work.axi_streaming_dma_rx_fifo;
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use work.axi_streaming_dma_tx_fifo;
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use work.pl330_dma_fifo;
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use work.axi_ctrlif;
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entity axi_i2s_adi is
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generic
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(
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-- ADD USER GENERICS BELOW THIS LINE ---------------
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SLOT_WIDTH : integer := 24;
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||||
LRCLK_POL : integer := 0; -- LRCLK Polarity (0 - Falling edge, 1 - Rising edge)
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||||
BCLK_POL : integer := 0; -- BCLK Polarity (0 - Falling edge, 1 - Rising edge)
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||||
-- ADD USER GENERICS ABOVE THIS LINE ---------------
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-- DO NOT EDIT BELOW THIS LINE ---------------------
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-- Bus protocol parameters, do not add to or delete
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||||
S_AXI_DATA_WIDTH : integer := 32;
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||||
S_AXI_ADDRESS_WIDTH : integer := 32;
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||||
DEVICE_FAMILY : string := "virtex6";
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||||
-- DO NOT EDIT ABOVE THIS LINE ---------------------
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||||
DMA_TYPE : integer := 0;
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||||
NUM_OF_CHANNEL : integer := 1;
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HAS_TX : integer := 1;
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HAS_RX : integer := 1
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);
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port
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(
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-- Serial Data interface
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data_clk_i : in std_logic;
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bclk_o : out std_logic_vector(NUM_OF_CHANNEL - 1 downto 0);
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lrclk_o : out std_logic_vector(NUM_OF_CHANNEL - 1 downto 0);
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sdata_o : out std_logic_vector(NUM_OF_CHANNEL - 1 downto 0);
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sdata_i : in std_logic_vector(NUM_OF_CHANNEL - 1 downto 0);
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-- AXI Streaming DMA TX interface
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s_axis_aclk : in std_logic;
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s_axis_aresetn : in std_logic;
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s_axis_tready : out std_logic;
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s_axis_tdata : in std_logic_vector(31 downto 0);
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s_axis_tlast : in std_logic;
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s_axis_tvalid : in std_logic;
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-- AXI Streaming DMA RX interface
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m_axis_aclk : in std_logic;
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m_axis_tready : in std_logic;
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m_axis_tdata : out std_logic_vector(31 downto 0);
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m_axis_tlast : out std_logic;
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m_axis_tvalid : out std_logic;
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m_axis_tkeep : out std_logic_vector(3 downto 0);
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--PL330 DMA TX interface
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dma_req_tx_aclk : in std_logic;
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dma_req_tx_rstn : in std_logic;
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dma_req_tx_davalid : in std_logic;
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dma_req_tx_datype : in std_logic_vector(1 downto 0);
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dma_req_tx_daready : out std_logic;
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dma_req_tx_drvalid : out std_logic;
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dma_req_tx_drtype : out std_logic_vector(1 downto 0);
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dma_req_tx_drlast : out std_logic;
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dma_req_tx_drready : in std_logic;
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-- PL330 DMA RX interface
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dma_req_rx_aclk : in std_logic;
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dma_req_rx_rstn : in std_logic;
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dma_req_rx_davalid : in std_logic;
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dma_req_rx_datype : in std_logic_vector(1 downto 0);
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dma_req_rx_daready : out std_logic;
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dma_req_rx_drvalid : out std_logic;
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dma_req_rx_drtype : out std_logic_vector(1 downto 0);
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dma_req_rx_drlast : out std_logic;
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dma_req_rx_drready : in std_logic;
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-- AXI bus interface
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s_axi_aclk : in std_logic;
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s_axi_aresetn : in std_logic;
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s_axi_awaddr : in std_logic_vector(S_AXI_ADDRESS_WIDTH-1 downto 0);
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s_axi_awvalid : in std_logic;
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s_axi_wdata : in std_logic_vector(S_AXI_DATA_WIDTH-1 downto 0);
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s_axi_wstrb : in std_logic_vector((S_AXI_DATA_WIDTH/8)-1 downto 0);
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s_axi_wvalid : in std_logic;
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s_axi_bready : in std_logic;
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s_axi_araddr : in std_logic_vector(S_AXI_ADDRESS_WIDTH-1 downto 0);
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s_axi_arvalid : in std_logic;
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s_axi_rready : in std_logic;
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s_axi_arready : out std_logic;
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s_axi_rdata : out std_logic_vector(S_AXI_DATA_WIDTH-1 downto 0);
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s_axi_rresp : out std_logic_vector(1 downto 0);
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s_axi_rvalid : out std_logic;
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s_axi_wready : out std_logic;
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s_axi_bresp : out std_logic_vector(1 downto 0);
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s_axi_bvalid : out std_logic;
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s_axi_awready : out std_logic;
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s_axi_awprot : in std_logic_vector(2 downto 0);
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s_axi_arprot : in std_logic_vector(2 downto 0)
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);
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end entity axi_i2s_adi;
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architecture Behavioral of axi_i2s_adi is
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------------------------------------------
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-- Signals for user logic slave model s/w accessible register example
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------------------------------------------
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signal i2s_reset : std_logic;
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signal tx_fifo_reset : std_logic;
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signal tx_enable : Boolean;
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signal tx_data : std_logic_vector(SLOT_WIDTH - 1 downto 0);
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signal tx_ack : std_logic;
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signal tx_stb : std_logic;
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signal rx_enable : Boolean;
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signal rx_fifo_reset : std_logic;
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signal rx_data : std_logic_vector(SLOT_WIDTH - 1 downto 0);
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signal rx_ack : std_logic;
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signal rx_stb : std_logic;
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signal const_1 : std_logic;
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signal bclk_div_rate : natural range 0 to 255;
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signal lrclk_div_rate : natural range 0 to 255;
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signal period_len : integer range 0 to 65535;
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signal I2S_RESET_REG : std_logic_vector(31 downto 0);
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signal I2S_CONTROL_REG : std_logic_vector(31 downto 0);
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signal I2S_CLK_CONTROL_REG : std_logic_vector(31 downto 0);
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signal PERIOD_LEN_REG : std_logic_vector(31 downto 0);
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constant FIFO_AWIDTH : integer := integer(ceil(log2(real(NUM_OF_CHANNEL * 8))));
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-- Audio samples FIFO
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constant RAM_ADDR_WIDTH : integer := 7;
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type RAM_TYPE is array (0 to (2**RAM_ADDR_WIDTH - 1)) of std_logic_vector(31 downto 0);
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-- RX FIFO signals
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signal audio_fifo_rx : RAM_TYPE;
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signal audio_fifo_rx_wr_addr : integer range 0 to 2**RAM_ADDR_WIDTH-1;
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signal audio_fifo_rx_rd_addr : integer range 0 to 2**RAM_ADDR_WIDTH-1;
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signal tvalid : std_logic := '0';
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signal rx_tlast : std_logic;
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signal drain_tx_dma : std_logic;
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signal rx_sample : std_logic_vector(23 downto 0);
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signal wr_data : std_logic_vector(31 downto 0);
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signal rd_data : std_logic_vector(31 downto 0);
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signal wr_addr : integer range 0 to 11;
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signal rd_addr : integer range 0 to 11;
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signal wr_stb : std_logic;
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signal rd_ack : std_logic;
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signal tx_fifo_stb : std_logic;
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signal rx_fifo_ack : std_logic;
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signal cnt : integer range 0 to 2**16-1;
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begin
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const_1 <= '1';
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process (s_axi_aclk)
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begin
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if rising_edge(s_axi_aclk) then
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if s_axi_aresetn = '0' then
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cnt <= 0;
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else
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cnt <= (cnt + 1) mod 2**16;
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end if;
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end if;
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end process;
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streaming_dma_tx_gen: if DMA_TYPE = 0 and HAS_TX = 1 generate
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tx_fifo : entity axi_streaming_dma_tx_fifo
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generic map(
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RAM_ADDR_WIDTH => FIFO_AWIDTH,
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FIFO_DWIDTH => 24
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)
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port map(
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clk => s_axi_aclk,
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resetn => s_axi_aresetn,
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fifo_reset => tx_fifo_reset,
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enable => tx_enable,
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s_axis_aclk => s_axis_aclk,
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||||
s_axis_tready => s_axis_tready,
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s_axis_tdata => s_axis_tdata(31 downto 8),
|
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s_axis_tlast => s_axis_tlast,
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s_axis_tvalid => s_axis_tvalid,
|
||||
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||||
out_stb => tx_stb,
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out_ack => tx_ack,
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out_data => tx_data
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);
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end generate;
|
||||
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no_streaming_dma_tx_gen: if DMA_TYPE /= 0 or HAS_TX /= 1 generate
|
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s_axis_tready <= '0';
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end generate;
|
||||
|
||||
streaming_dma_rx_gen: if DMA_TYPE = 0 and HAS_RX = 1 generate
|
||||
rx_fifo : entity axi_streaming_dma_rx_fifo
|
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generic map(
|
||||
RAM_ADDR_WIDTH => FIFO_AWIDTH,
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FIFO_DWIDTH => 24
|
||||
)
|
||||
port map(
|
||||
clk => s_axi_aclk,
|
||||
resetn => s_axi_aresetn,
|
||||
fifo_reset => tx_fifo_reset,
|
||||
enable => tx_enable,
|
||||
|
||||
period_len => period_len,
|
||||
|
||||
in_stb => rx_stb,
|
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in_ack => rx_ack,
|
||||
in_data => rx_data,
|
||||
|
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m_axis_aclk => m_axis_aclk,
|
||||
m_axis_tready => m_axis_tready,
|
||||
m_axis_tdata => m_axis_tdata(31 downto 8),
|
||||
m_axis_tlast => m_axis_tlast,
|
||||
m_axis_tvalid => m_axis_tvalid,
|
||||
m_axis_tkeep => m_axis_tkeep
|
||||
);
|
||||
|
||||
m_axis_tdata(7 downto 0) <= (others => '0');
|
||||
end generate;
|
||||
|
||||
no_streaming_dma_rx_gen: if DMA_TYPE /= 0 or HAS_RX /= 1 generate
|
||||
m_axis_tdata <= (others => '0');
|
||||
m_axis_tlast <= '0';
|
||||
m_axis_tvalid <= '0';
|
||||
m_axis_tkeep <= (others => '0');
|
||||
end generate;
|
||||
|
||||
|
||||
|
||||
pl330_dma_tx_gen: if DMA_TYPE = 1 and HAS_TX = 1 generate
|
||||
tx_fifo_stb <= '1' when wr_addr = 11 and wr_stb = '1' else '0';
|
||||
|
||||
tx_fifo: entity pl330_dma_fifo
|
||||
generic map(
|
||||
RAM_ADDR_WIDTH => FIFO_AWIDTH,
|
||||
FIFO_DWIDTH => 24,
|
||||
FIFO_DIRECTION => 0
|
||||
)
|
||||
port map (
|
||||
clk => s_axi_aclk,
|
||||
resetn => s_axi_aresetn,
|
||||
fifo_reset => tx_fifo_reset,
|
||||
enable => tx_enable,
|
||||
|
||||
in_data => wr_data(31 downto 8),
|
||||
in_stb => tx_fifo_stb,
|
||||
|
||||
out_ack => tx_ack,
|
||||
out_stb => tx_stb,
|
||||
out_data => tx_data,
|
||||
|
||||
dclk => dma_req_tx_aclk,
|
||||
dresetn => dma_req_tx_rstn,
|
||||
davalid => dma_req_tx_davalid,
|
||||
daready => dma_req_tx_daready,
|
||||
datype => dma_req_tx_datype,
|
||||
drvalid => dma_req_tx_drvalid,
|
||||
drready => dma_req_tx_drready,
|
||||
drtype => dma_req_tx_drtype,
|
||||
drlast => dma_req_tx_drlast
|
||||
);
|
||||
end generate;
|
||||
|
||||
no_pl330_dma_tx_gen: if DMA_TYPE /= 1 or HAS_TX /= 1 generate
|
||||
dma_req_tx_daready <= '0';
|
||||
dma_req_tx_drvalid <= '0';
|
||||
dma_req_tx_drtype <= (others => '0');
|
||||
dma_req_tx_drlast <= '0';
|
||||
end generate;
|
||||
|
||||
pl330_dma_rx_gen: if DMA_TYPE = 1 and HAS_RX = 1 generate
|
||||
rx_fifo_ack <= '1' when rd_addr = 10 and rd_ack = '1' else '0';
|
||||
|
||||
rx_fifo: entity pl330_dma_fifo
|
||||
generic map(
|
||||
RAM_ADDR_WIDTH => FIFO_AWIDTH,
|
||||
FIFO_DWIDTH => 24,
|
||||
FIFO_DIRECTION => 1
|
||||
)
|
||||
port map (
|
||||
clk => s_axi_aclk,
|
||||
resetn => s_axi_aresetn,
|
||||
fifo_reset => rx_fifo_reset,
|
||||
enable => rx_enable,
|
||||
|
||||
in_ack => rx_ack,
|
||||
in_stb => rx_stb,
|
||||
in_data => rx_data,
|
||||
|
||||
out_data => rx_sample,
|
||||
out_ack => rx_fifo_ack,
|
||||
|
||||
dclk => dma_req_rx_aclk,
|
||||
dresetn => dma_req_rx_rstn,
|
||||
davalid => dma_req_rx_davalid,
|
||||
daready => dma_req_rx_daready,
|
||||
datype => dma_req_rx_datype,
|
||||
drvalid => dma_req_rx_drvalid,
|
||||
drready => dma_req_rx_drready,
|
||||
drtype => dma_req_rx_drtype,
|
||||
drlast => dma_req_rx_drlast
|
||||
);
|
||||
|
||||
end generate;
|
||||
|
||||
no_pl330_dma_rx_gen: if DMA_TYPE /= 1 or HAS_RX /= 1 generate
|
||||
dma_req_rx_daready <= '0';
|
||||
dma_req_rx_drvalid <= '0';
|
||||
dma_req_rx_drtype <= (others => '0');
|
||||
dma_req_rx_drlast <= '0';
|
||||
end generate;
|
||||
|
||||
ctrl : entity i2s_controller
|
||||
generic map (
|
||||
C_SLOT_WIDTH => SLOT_WIDTH,
|
||||
C_BCLK_POL => BCLK_POL,
|
||||
C_LRCLK_POL => LRCLK_POL,
|
||||
C_NUM_CH => NUM_OF_CHANNEL,
|
||||
C_HAS_TX => HAS_TX,
|
||||
C_HAS_RX => HAS_RX
|
||||
)
|
||||
port map (
|
||||
clk => s_axi_aclk,
|
||||
resetn => s_axi_aresetn,
|
||||
|
||||
data_clk => data_clk_i,
|
||||
bclk_o => bclk_o,
|
||||
lrclk_o => lrclk_o,
|
||||
sdata_o => sdata_o,
|
||||
sdata_i => sdata_i,
|
||||
|
||||
tx_enable => tx_enable,
|
||||
tx_ack => tx_ack,
|
||||
tx_stb => tx_stb,
|
||||
tx_data => tx_data,
|
||||
|
||||
rx_enable => rx_enable,
|
||||
rx_ack => rx_ack,
|
||||
rx_stb => rx_stb,
|
||||
rx_data => rx_data,
|
||||
|
||||
bclk_div_rate => bclk_div_rate,
|
||||
lrclk_div_rate => lrclk_div_rate
|
||||
);
|
||||
|
||||
i2s_reset <= I2S_RESET_REG(0);
|
||||
tx_fifo_reset <= I2S_RESET_REG(1);
|
||||
rx_fifo_reset <= I2S_RESET_REG(2);
|
||||
tx_enable <= I2S_CONTROL_REG(0) = '1';
|
||||
rx_enable <= I2S_CONTROL_REG(1) = '1';
|
||||
bclk_div_rate <= to_integer(unsigned(I2S_CLK_CONTROL_REG(7 downto 0)));
|
||||
lrclk_div_rate <= to_integer(unsigned(I2S_CLK_CONTROL_REG(23 downto 16)));
|
||||
period_len <= to_integer(unsigned(PERIOD_LEN_REG(15 downto 0)));
|
||||
|
||||
ctrlif: entity axi_ctrlif
|
||||
generic map (
|
||||
C_S_AXI_ADDR_WIDTH => S_AXI_ADDRESS_WIDTH,
|
||||
C_S_AXI_DATA_WIDTH => S_AXI_DATA_WIDTH,
|
||||
C_NUM_REG => 12
|
||||
)
|
||||
port map(
|
||||
s_axi_aclk => s_axi_aclk,
|
||||
s_axi_aresetn => s_axi_aresetn,
|
||||
s_axi_awaddr => s_axi_awaddr,
|
||||
s_axi_awvalid => s_axi_awvalid,
|
||||
s_axi_wdata => s_axi_wdata,
|
||||
s_axi_wstrb => s_axi_wstrb,
|
||||
s_axi_wvalid => s_axi_wvalid,
|
||||
s_axi_bready => s_axi_bready,
|
||||
s_axi_araddr => s_axi_araddr,
|
||||
s_axi_arvalid => s_axi_arvalid,
|
||||
s_axi_rready => s_axi_rready,
|
||||
s_axi_arready => s_axi_arready,
|
||||
s_axi_rdata => s_axi_rdata,
|
||||
s_axi_rresp => s_axi_rresp,
|
||||
s_axi_rvalid => s_axi_rvalid,
|
||||
s_axi_wready => s_axi_wready,
|
||||
s_axi_bresp => s_axi_bresp,
|
||||
s_axi_bvalid => s_axi_bvalid,
|
||||
s_axi_awready => s_axi_awready,
|
||||
|
||||
rd_addr => rd_addr,
|
||||
rd_data => rd_data,
|
||||
rd_ack => rd_ack,
|
||||
rd_stb => const_1,
|
||||
|
||||
wr_addr => wr_addr,
|
||||
wr_data => wr_data,
|
||||
wr_ack => const_1,
|
||||
wr_stb => wr_stb
|
||||
);
|
||||
|
||||
process(rd_addr, I2S_CONTROL_REG, I2S_CLK_CONTROL_REG, PERIOD_LEN_REG, rx_sample, cnt)
|
||||
begin
|
||||
case rd_addr is
|
||||
when 1 => rd_data <= I2S_CONTROL_REG and x"00000003";
|
||||
when 2 => rd_data <= I2S_CLK_CONTROL_REG and x"00ff00ff";
|
||||
when 6 => rd_data <= PERIOD_LEN_REG and x"0000ffff";
|
||||
when 10 => rd_data <= rx_sample & std_logic_vector(to_unsigned(cnt, 8));
|
||||
when others => rd_data <= (others => '0');
|
||||
end case;
|
||||
end process;
|
||||
|
||||
process(s_axi_aclk) is
|
||||
begin
|
||||
if rising_edge(s_axi_aclk) then
|
||||
if s_axi_aresetn = '0' then
|
||||
I2S_RESET_REG <= (others => '0');
|
||||
I2S_CONTROL_REG <= (others => '0');
|
||||
I2S_CLK_CONTROL_REG <= (others => '0');
|
||||
PERIOD_LEN_REG <= (others => '0');
|
||||
else
|
||||
-- Auto-clear the Reset Register bits
|
||||
I2S_RESET_REG(0) <= '0';
|
||||
I2S_RESET_REG(1) <= '0';
|
||||
I2S_RESET_REG(2) <= '0';
|
||||
if wr_stb = '1' then
|
||||
case wr_addr is
|
||||
when 0 => I2S_RESET_REG <= wr_data;
|
||||
when 1 => I2S_CONTROL_REG <= wr_data;
|
||||
when 2 => I2S_CLK_CONTROL_REG <= wr_data;
|
||||
when 6 => PERIOD_LEN_REG <= wr_data;
|
||||
when others => null;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end Behavioral;
|
||||
@@ -0,0 +1,441 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Version="7" Minor="40" Path="/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_i2s_adi/axi_i2s_adi.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="7c0c77ebf9144008a74a72ff4b02f3c8"/>
|
||||
<Option Name="Part" Val="xc7vx485tffg1157-1"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="BoardPart" Val=""/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../library"/>
|
||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../../ghdl/library"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="DSAVendor" Val="xilinx"/>
|
||||
<Option Name="DSANumComputeUnits" Val="60"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="0"/>
|
||||
<Option Name="WTModelSimExportSim" Val="0"/>
|
||||
<Option Name="WTQuestaExportSim" Val="0"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="0"/>
|
||||
<Option Name="WTRivieraExportSim" Val="0"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
<Option Name="SimTypes" Val="bfm"/>
|
||||
<Option Name="SimTypes" Val="tlm"/>
|
||||
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="31">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/../common/axi_ctrlif.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/fifo_synchronizer.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/i2s_clkgen.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/i2s_tx.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/i2s_rx.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/i2s_controller.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../common/dma_fifo.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../common/axi_streaming_dma_rx_fifo.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../common/axi_streaming_dma_tx_fifo.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../common/pl330_dma_fifo.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/axi_i2s_adi.vhd">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/component.xml">
|
||||
<FileInfo SFType="IPXACT"/>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="axi_i2s_adi"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<File Path="$PPRDIR/axi_i2s_adi_constr.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="IES">
|
||||
<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Xcelium">
|
||||
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="VCS">
|
||||
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="10">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Vivado 12-1790"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="1"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="Evaluation"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="features"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="should"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="NOT"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="be"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="used"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="in"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="production"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="systems."/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Place 30-73"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="10"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="axi_spi"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val=""/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="11"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1343"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="2"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1306"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="3"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="ERROR"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1276"/>
|
||||
<MsgAttr Name="Severity" Val="CRITICAL WARNING"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="4"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-3656"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="5"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-4623"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="6"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-459"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="7"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Synth 8-3331"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="8"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Designutils 20-3303"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="9"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="HDPYFinalizeIO"/>
|
||||
</MsgRule>
|
||||
<Board/>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
<BootPmcSettings Version="1" Minor="0">
|
||||
<Parameters>
|
||||
<Parameter Name="PMC_CDO.ATTRS.LOADADDR" Value="" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_FB_CLK" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_FREQ" Value="300" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_BUS_WIDTH" Value="x1" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_DATA_MODE" Value="Single" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_FREQ" Value="200" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_SLOT_TYPE" Value="SD 2.0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_FREQ" Value="200" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_SLOT_TYPE" Value="SD 2.0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSPI_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSPI_FREQ" Value="300" Type="string"/>
|
||||
<Parameter Name="BOOT.USB_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SMAP_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SMAP_DATA_WIDTH" Value="32 Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSC_FREQ" Value="33.333" Type="string"/>
|
||||
<Parameter Name="BOOT.SECONDARY.PCIE_ENABLE" Value="0" Type="string"/>
|
||||
</Parameters>
|
||||
</BootPmcSettings>
|
||||
</Project>
|
||||
@@ -0,0 +1,26 @@
|
||||
set ctrl_clk [get_clocks -of_objects [get_ports s_axi_aclk]]
|
||||
set data_clk [get_clocks -of_objects [get_ports data_clk_i]]
|
||||
|
||||
set_property ASYNC_REG TRUE \
|
||||
[get_cells -hier cdc_sync_stage1_*_reg] \
|
||||
[get_cells -hier cdc_sync_stage2_*_reg]
|
||||
|
||||
set_false_path \
|
||||
-from [get_cells -hier cdc_sync_stage0_*_reg -filter {IS_SEQUENTIAL}] \
|
||||
-to [get_cells -hier cdc_sync_stage1_*_reg -filter {IS_SEQUENTIAL}]
|
||||
|
||||
# TX FIFO
|
||||
set_max_delay \
|
||||
-from $ctrl_clk \
|
||||
-to [get_cells -hier out_data_reg* -filter {IS_SEQUENTIAL && NAME =~ *tx_sync*}] \
|
||||
[get_property PERIOD $data_clk] -datapath_only
|
||||
|
||||
# RX FIFO
|
||||
set_max_delay \
|
||||
-from $data_clk \
|
||||
-to [get_cells -hier out_data_reg* -filter {IS_SEQUENTIAL && NAME =~ *rx_sync*}] \
|
||||
[get_property PERIOD $ctrl_clk] -datapath_only
|
||||
|
||||
# Reset
|
||||
set_false_path \
|
||||
-to [get_pins -hier data_reset_vec_reg*/PRE]
|
||||
@@ -0,0 +1,239 @@
|
||||
# ip
|
||||
|
||||
source ../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
|
||||
adi_ip_create axi_i2s_adi
|
||||
adi_ip_files axi_i2s_adi [list \
|
||||
"$ad_hdl_dir/library/common/axi_ctrlif.vhd" \
|
||||
"$ad_hdl_dir/library/common/axi_streaming_dma_tx_fifo.vhd" \
|
||||
"$ad_hdl_dir/library/common/axi_streaming_dma_rx_fifo.vhd" \
|
||||
"$ad_hdl_dir/library/common/pl330_dma_fifo.vhd" \
|
||||
"$ad_hdl_dir/library/common/dma_fifo.vhd" \
|
||||
"i2s_controller.vhd" \
|
||||
"i2s_rx.vhd" \
|
||||
"i2s_tx.vhd" \
|
||||
"i2s_clkgen.vhd" \
|
||||
"fifo_synchronizer.vhd" \
|
||||
"axi_i2s_adi.vhd" \
|
||||
"axi_i2s_adi_constr.xdc" \
|
||||
]
|
||||
|
||||
adi_ip_properties axi_i2s_adi
|
||||
|
||||
set_property PROCESSING_ORDER LATE [ipx::get_files axi_i2s_adi_constr.xdc \
|
||||
-of_objects [ipx::get_file_groups -of_objects [ipx::current_core] \
|
||||
-filter {NAME =~ *synthesis*}]]
|
||||
|
||||
adi_ip_infer_streaming_interfaces axi_i2s_adi
|
||||
|
||||
set_property display_name "ADI AXI I2S Controller" [ipx::current_core]
|
||||
set_property description "ADI AXI I2S Controller" [ipx::current_core]
|
||||
|
||||
adi_add_bus "dma_ack_rx" "slave" \
|
||||
"xilinx.com:interface:axis_rtl:1.0" \
|
||||
"xilinx.com:interface:axis:1.0" \
|
||||
{ \
|
||||
{"dma_req_rx_davalid" "TVALID"} \
|
||||
{"dma_req_rx_daready" "TREADY"} \
|
||||
{"dma_req_rx_datype" "TUSER"} \
|
||||
}
|
||||
|
||||
adi_add_bus "dma_req_rx" "master" \
|
||||
"xilinx.com:interface:axis_rtl:1.0" \
|
||||
"xilinx.com:interface:axis:1.0" \
|
||||
{ \
|
||||
{"dma_req_rx_drvalid" "TVALID"} \
|
||||
{"dma_req_rx_drready" "TREADY"} \
|
||||
{"dma_req_rx_drtype" "TUSER"} \
|
||||
{"dma_req_rx_drlast" "TLAST"} \
|
||||
}
|
||||
# Clock and reset are for both dma_req and dma_ack
|
||||
adi_add_bus_clock "dma_req_rx_aclk" "dma_req_rx:dma_ack_rx" "dma_req_rx_rstn"
|
||||
|
||||
adi_add_bus "dma_ack_tx" "slave" \
|
||||
"xilinx.com:interface:axis_rtl:1.0" \
|
||||
"xilinx.com:interface:axis:1.0" \
|
||||
{ \
|
||||
{"dma_req_tx_davalid" "TVALID"} \
|
||||
{"dma_req_tx_daready" "TREADY"} \
|
||||
{"dma_req_tx_datype" "TUSER"} \
|
||||
}
|
||||
adi_add_bus "dma_req_tx" "master" \
|
||||
"xilinx.com:interface:axis_rtl:1.0" \
|
||||
"xilinx.com:interface:axis:1.0" \
|
||||
{ \
|
||||
{"dma_req_tx_drvalid" "TVALID"} \
|
||||
{"dma_req_tx_drready" "TREADY"} \
|
||||
{"dma_req_tx_drtype" "TUSER"} \
|
||||
{"dma_req_tx_drlast" "TLAST"} \
|
||||
}
|
||||
# Clock and reset are for both dma_req and dma_ack
|
||||
adi_add_bus_clock "dma_req_tx_aclk" "dma_req_tx:dma_ack_tx" "dma_req_tx_rstn"
|
||||
|
||||
adi_add_bus "i2s" "master" \
|
||||
"analog.com:interface:i2s_rtl:1.0" \
|
||||
"analog.com:interface:i2s:1.0" \
|
||||
{ \
|
||||
{"bclk_o" "BCLK"} \
|
||||
{"lrclk_o" "LRCLK"} \
|
||||
{"sdata_o" "SDATA_OUT"} \
|
||||
{"sdata_i" "SDATA_IN"} \
|
||||
}
|
||||
adi_add_bus_clock "data_clk_i" "i2s"
|
||||
|
||||
adi_set_bus_dependency "s_axis" "s_axis" \
|
||||
"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.HAS_TX')) = 1)"
|
||||
adi_set_bus_dependency "m_axis" "m_axis" \
|
||||
"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.HAS_RX')) = 1)"
|
||||
|
||||
adi_set_bus_dependency "dma_ack_tx" "dma_req_tx_da" \
|
||||
"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.HAS_TX')) = 1)"
|
||||
adi_set_bus_dependency "dma_req_tx" "dma_req_tx_dr" \
|
||||
"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.HAS_TX')) = 1)"
|
||||
adi_set_ports_dependency "dma_req_tx_aclk" \
|
||||
"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.HAS_TX')) = 1)"
|
||||
adi_set_ports_dependency "dma_req_tx_rstn" \
|
||||
"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.HAS_TX')) = 1)"
|
||||
adi_set_bus_dependency "dma_ack_rx" "dma_req_rx_da" \
|
||||
"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.HAS_RX')) = 1)"
|
||||
adi_set_bus_dependency "dma_req_rx" "dma_req_rx_dr" \
|
||||
"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.HAS_RX')) = 1)"
|
||||
adi_set_ports_dependency "dma_req_rx_aclk" \
|
||||
"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.HAS_RX')) = 1)"
|
||||
adi_set_ports_dependency "dma_req_rx_rstn" \
|
||||
"(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.HAS_RX')) = 1)"
|
||||
|
||||
# Tie-off optional inputs to 0
|
||||
set_property driver_value 0 [ipx::get_ports -filter "direction==in && enablement_dependency!={}" -of_objects [ipx::current_core]]
|
||||
|
||||
set cc [ipx::current_core]
|
||||
|
||||
set_property -dict [list \
|
||||
"value_validation_type" "list" \
|
||||
"value_validation_list" "16 20 24 32" \
|
||||
] \
|
||||
[ipx::get_user_parameters SLOT_WIDTH -of_objects $cc]
|
||||
|
||||
set_property -dict [list \
|
||||
"value_validation_type" "pairs" \
|
||||
"value_validation_pairs" { \
|
||||
"Falling Edge" "0" \
|
||||
"Rising Edge" "1" \
|
||||
} \
|
||||
] \
|
||||
[ipx::get_user_parameters LRCLK_POL -of_objects $cc]
|
||||
|
||||
set_property -dict [list \
|
||||
"value_validation_type" "pairs" \
|
||||
"value_validation_pairs" { \
|
||||
"Falling Edge" "0" \
|
||||
"Rising Edge" "1" \
|
||||
} \
|
||||
] \
|
||||
[ipx::get_user_parameters BCLK_POL -of_objects $cc]
|
||||
|
||||
set_property -dict [list \
|
||||
"value_validation_type" "pairs" \
|
||||
"value_validation_pairs" { \
|
||||
"AXI Stream" "0" \
|
||||
"PL330" "1" \
|
||||
} \
|
||||
] \
|
||||
[ipx::get_user_parameters DMA_TYPE -of_objects $cc]
|
||||
|
||||
set_property -dict [list \
|
||||
"value_validation_type" "range_long" \
|
||||
"value_validation_range_minimum" "0" \
|
||||
"value_validation_range_maximum" "1" \
|
||||
] \
|
||||
[ipx::get_user_parameters HAS_RX -of_objects $cc]
|
||||
|
||||
set_property -dict [list \
|
||||
"value_validation_type" "range_long" \
|
||||
"value_validation_range_minimum" "0" \
|
||||
"value_validation_range_maximum" "1" \
|
||||
] \
|
||||
[ipx::get_user_parameters HAS_TX -of_objects $cc]
|
||||
|
||||
set_property -dict [list \
|
||||
"value_validation_type" "range_long" \
|
||||
"value_validation_range_minimum" "1" \
|
||||
"value_validation_range_maximum" "32" \
|
||||
] \
|
||||
[ipx::get_user_parameters NUM_OF_CHANNEL -of_objects $cc]
|
||||
|
||||
set_property -dict [list \
|
||||
"value_validation_type" "range_long" \
|
||||
"value_validation_range_minimum" "1" \
|
||||
"value_validation_range_maximum" "32" \
|
||||
] \
|
||||
[ipx::get_user_parameters S_AXI_ADDRESS_WIDTH -of_objects $cc]
|
||||
|
||||
set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]
|
||||
|
||||
set i2s_group [ipgui::add_group -name "I2S Configuration" -component $cc \
|
||||
-parent $page0 -display_name "I2S Configuration"]
|
||||
|
||||
set p [ipgui::get_guiparamspec -name "SLOT_WIDTH" -component $cc]
|
||||
ipgui::move_param -component $cc -order 0 $p -parent $i2s_group
|
||||
set_property -dict [list \
|
||||
"widget" "comboBox" \
|
||||
"display_name" "Slot Width" \
|
||||
] $p
|
||||
|
||||
set p [ipgui::get_guiparamspec -name "LRCLK_POL" -component $cc]
|
||||
ipgui::move_param -component $cc -order 1 $p -parent $i2s_group
|
||||
set_property -dict [list \
|
||||
"widget" "comboBox" \
|
||||
"display_name" "Left-Right Clock Polarity" \
|
||||
] $p
|
||||
|
||||
set p [ipgui::get_guiparamspec -name "BCLK_POL" -component $cc]
|
||||
ipgui::move_param -component $cc -order 2 $p -parent $i2s_group
|
||||
set_property -dict [list \
|
||||
"widget" "comboBox" \
|
||||
"display_name" "Bit Clock Polarity" \
|
||||
] $p
|
||||
|
||||
set general_group [ipgui::add_group -name "General Configuration" -component $cc \
|
||||
-parent $page0 -display_name "General Configuration"]
|
||||
|
||||
set p [ipgui::get_guiparamspec -name "HAS_RX" -component $cc]
|
||||
ipgui::move_param -component $cc -order 0 $p -parent $general_group
|
||||
set_property -dict [list \
|
||||
"widget" "checkBox" \
|
||||
"display_name" "Enable I2S Receiver Support" \
|
||||
] $p
|
||||
|
||||
set p [ipgui::get_guiparamspec -name "HAS_TX" -component $cc]
|
||||
ipgui::move_param -component $cc -order 1 $p -parent $general_group
|
||||
set_property -dict [list \
|
||||
"widget" "checkBox" \
|
||||
"display_name" "Enable I2S Transmitter Support" \
|
||||
] $p
|
||||
|
||||
set p [ipgui::get_guiparamspec -name "DMA_TYPE" -component $cc]
|
||||
ipgui::move_param -component $cc -order 2 $p -parent $general_group
|
||||
set_property -dict [list \
|
||||
"widget" "comboBox" \
|
||||
"display_name" "DMA Interface Type" \
|
||||
] $p
|
||||
|
||||
set p [ipgui::get_guiparamspec -name "NUM_OF_CHANNEL" -component $cc]
|
||||
ipgui::move_param -component $cc -order 3 $p -parent $general_group
|
||||
set_property -dict [list \
|
||||
"display_name" "Number of Audio Channels" \
|
||||
] $p
|
||||
|
||||
set p [ipgui::get_guiparamspec -name "S_AXI_ADDRESS_WIDTH" -component $cc]
|
||||
ipgui::move_param -component $cc -order 4 $p -parent $general_group
|
||||
set_property -dict [list \
|
||||
"display_name" "AXI Address Width" \
|
||||
] $p
|
||||
|
||||
ipgui::remove_param -component $cc [ipgui::get_guiparamspec -name "S_AXI_DATA_WIDTH" -component $cc]
|
||||
ipgui::remove_param -component $cc [ipgui::get_guiparamspec -name "DEVICE_FAMILY" -component $cc]
|
||||
|
||||
ipx::create_xgui_files $cc
|
||||
ipx::save_core $cc
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,129 @@
|
||||
-- ***************************************************************************
|
||||
-- ***************************************************************************
|
||||
-- Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- In this HDL repository, there are many different and unique modules, consisting
|
||||
-- of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
-- developed independently, and may be accompanied by separate and unique license
|
||||
-- terms.
|
||||
--
|
||||
-- The user should read each of these license terms, and understand the
|
||||
-- freedoms and responsibilities that he or she has by using this source/core.
|
||||
--
|
||||
-- This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
-- A PARTICULAR PURPOSE.
|
||||
--
|
||||
-- Redistribution and use of source or resulting binaries, with or without modification
|
||||
-- of this file, are permitted under one of the following two license terms:
|
||||
--
|
||||
-- 1. The GNU General Public License version 2 as published by the
|
||||
-- Free Software Foundation, which can be found in the top level directory
|
||||
-- of this repository (LICENSE_GPL2), and also online at:
|
||||
-- <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
--
|
||||
-- OR
|
||||
--
|
||||
-- 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
-- of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
-- https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
-- This will allow to generate bit files and not release the source code,
|
||||
-- as long as it attaches to an ADI device.
|
||||
--
|
||||
-- ***************************************************************************
|
||||
-- ***************************************************************************
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
|
||||
entity fifo_synchronizer is
|
||||
generic (
|
||||
DEPTH : integer := 4;
|
||||
WIDTH : integer := 2
|
||||
);
|
||||
port (
|
||||
|
||||
in_clk : in std_logic;
|
||||
in_resetn : in std_logic;
|
||||
in_data : in std_logic_vector(WIDTH - 1 downto 0);
|
||||
in_tick : in std_logic;
|
||||
|
||||
out_clk : in std_logic;
|
||||
out_resetn : in std_logic;
|
||||
out_data : out std_logic_vector(WIDTH - 1 downto 0);
|
||||
out_tick : out std_logic
|
||||
);
|
||||
|
||||
end fifo_synchronizer;
|
||||
|
||||
architecture impl of fifo_synchronizer is
|
||||
type DATA_SYNC_FIFO_TYPE is array (0 to DEPTH - 1) of std_logic_vector(WIDTH - 1 downto 0);
|
||||
signal fifo: DATA_SYNC_FIFO_TYPE;
|
||||
|
||||
signal rd_addr : natural range 0 to DEPTH - 1;
|
||||
signal wr_addr : natural range 0 to DEPTH - 1;
|
||||
|
||||
signal cdc_sync_stage0_tick : std_logic;
|
||||
signal cdc_sync_stage1_tick : std_logic;
|
||||
signal cdc_sync_stage2_tick : std_logic;
|
||||
signal cdc_sync_stage3_tick : std_logic;
|
||||
signal tick : std_logic;
|
||||
begin
|
||||
|
||||
process (in_clk)
|
||||
begin
|
||||
if rising_edge(in_clk) then
|
||||
if in_tick = '1' then
|
||||
cdc_sync_stage0_tick <= not cdc_sync_stage0_tick;
|
||||
fifo(wr_addr) <= in_data;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (in_clk)
|
||||
begin
|
||||
if rising_edge(in_clk) then
|
||||
if in_resetn = '0' then
|
||||
wr_addr <= 0;
|
||||
else
|
||||
if in_tick = '1' then
|
||||
wr_addr <= (wr_addr + 1) mod DEPTH;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (out_clk)
|
||||
begin
|
||||
if rising_edge(out_clk) then
|
||||
cdc_sync_stage1_tick <= cdc_sync_stage0_tick;
|
||||
cdc_sync_stage2_tick <= cdc_sync_stage1_tick;
|
||||
cdc_sync_stage3_tick <= cdc_sync_stage2_tick;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
tick <= cdc_sync_stage2_tick xor cdc_sync_stage3_tick;
|
||||
out_tick <= tick;
|
||||
|
||||
process (out_clk)
|
||||
begin
|
||||
if rising_edge(out_clk) then
|
||||
if tick = '1' then
|
||||
out_data <= fifo(rd_addr);
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (out_clk)
|
||||
begin
|
||||
if rising_edge(out_clk) then
|
||||
if out_resetn = '0' then
|
||||
rd_addr <= 0;
|
||||
else
|
||||
if tick = '1' then
|
||||
rd_addr <= (rd_addr + 1) mod DEPTH;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
end;
|
||||
@@ -0,0 +1,13 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:busDefinition xmlns:xilinx="http://www.xilinx.com"
|
||||
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
|
||||
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>analog.com</spirit:vendor>
|
||||
<spirit:library>interface</spirit:library>
|
||||
<spirit:name>i2s</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:directConnection>false</spirit:directConnection>
|
||||
<spirit:isAddressable>false</spirit:isAddressable>
|
||||
<spirit:maxMasters>1</spirit:maxMasters>
|
||||
<spirit:maxSlaves>1</spirit:maxSlaves>
|
||||
</spirit:busDefinition>
|
||||
@@ -0,0 +1,130 @@
|
||||
-- ***************************************************************************
|
||||
-- ***************************************************************************
|
||||
-- Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- In this HDL repository, there are many different and unique modules, consisting
|
||||
-- of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
-- developed independently, and may be accompanied by separate and unique license
|
||||
-- terms.
|
||||
--
|
||||
-- The user should read each of these license terms, and understand the
|
||||
-- freedoms and responsibilities that he or she has by using this source/core.
|
||||
--
|
||||
-- This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
-- A PARTICULAR PURPOSE.
|
||||
--
|
||||
-- Redistribution and use of source or resulting binaries, with or without modification
|
||||
-- of this file, are permitted under one of the following two license terms:
|
||||
--
|
||||
-- 1. The GNU General Public License version 2 as published by the
|
||||
-- Free Software Foundation, which can be found in the top level directory
|
||||
-- of this repository (LICENSE_GPL2), and also online at:
|
||||
-- <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
--
|
||||
-- OR
|
||||
--
|
||||
-- 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
-- of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
-- https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
-- This will allow to generate bit files and not release the source code,
|
||||
-- as long as it attaches to an ADI device.
|
||||
--
|
||||
-- ***************************************************************************
|
||||
-- ***************************************************************************
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
|
||||
entity i2s_clkgen is
|
||||
port(
|
||||
clk : in std_logic; -- System clock
|
||||
resetn : in std_logic; -- System reset
|
||||
|
||||
enable : in Boolean ; -- Enable clockgen
|
||||
|
||||
tick : in std_logic;
|
||||
|
||||
bclk_div_rate : in natural range 0 to 255;
|
||||
lrclk_div_rate : in natural range 0 to 255;
|
||||
|
||||
bclk : out std_logic; -- Bit Clock
|
||||
lrclk : out std_logic; -- Frame Clock
|
||||
channel_sync : out std_logic;
|
||||
frame_sync : out std_logic
|
||||
);
|
||||
end i2s_clkgen;
|
||||
|
||||
architecture Behavioral of i2s_clkgen is
|
||||
signal reset_int : Boolean;
|
||||
|
||||
signal prev_bclk_div_rate : natural range 0 to 255;
|
||||
signal prev_lrclk_div_rate : natural range 0 to 255;
|
||||
|
||||
signal bclk_count : natural range 0 to 255;
|
||||
signal lrclk_count : natural range 0 to 255;
|
||||
|
||||
signal bclk_int : std_logic;
|
||||
signal lrclk_int : std_logic;
|
||||
|
||||
signal lrclk_tick : Boolean;
|
||||
begin
|
||||
|
||||
reset_int <= resetn = '0' or not enable;
|
||||
|
||||
bclk <= bclk_int;
|
||||
lrclk <= lrclk_int;
|
||||
|
||||
-----------------------------------------------------------------------------------
|
||||
-- Serial clock generation BCLK_O
|
||||
-----------------------------------------------------------------------------------
|
||||
bclk_gen: process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
prev_bclk_div_rate <= bclk_div_rate;
|
||||
if reset_int then -- or (bclk_div_rate /= prev_bclk_div_rate) then
|
||||
bclk_int <= '1';
|
||||
bclk_count <= bclk_div_rate;
|
||||
else
|
||||
if tick = '1' then
|
||||
if bclk_count = bclk_div_rate then
|
||||
bclk_count <= 0;
|
||||
bclk_int <= not bclk_int;
|
||||
else
|
||||
bclk_count <= bclk_count + 1;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process bclk_gen;
|
||||
|
||||
lrclk_tick <= tick = '1' and bclk_count = bclk_div_rate and bclk_int = '1';
|
||||
|
||||
channel_sync <= '1' when lrclk_count = 1 else '0';
|
||||
frame_sync <= '1' when lrclk_count = 1 and lrclk_int = '0' else '0';
|
||||
|
||||
-----------------------------------------------------------------------------------
|
||||
-- Frame clock generator LRCLK_O
|
||||
-----------------------------------------------------------------------------------
|
||||
lrclk_gen: process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
prev_lrclk_div_rate <= lrclk_div_rate;
|
||||
-- Reset
|
||||
if reset_int then -- or lrclk_div_rate /= prev_lrclk_div_rate then
|
||||
lrclk_int <= '1';
|
||||
lrclk_count <= lrclk_div_rate;
|
||||
else
|
||||
if lrclk_tick then
|
||||
if lrclk_count = lrclk_div_rate then
|
||||
lrclk_count <= 0;
|
||||
lrclk_int <= not lrclk_int;
|
||||
else
|
||||
lrclk_count <= lrclk_count + 1;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process lrclk_gen;
|
||||
|
||||
end Behavioral;
|
||||
@@ -0,0 +1,292 @@
|
||||
-- ***************************************************************************
|
||||
-- ***************************************************************************
|
||||
-- Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- In this HDL repository, there are many different and unique modules, consisting
|
||||
-- of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
-- developed independently, and may be accompanied by separate and unique license
|
||||
-- terms.
|
||||
--
|
||||
-- The user should read each of these license terms, and understand the
|
||||
-- freedoms and responsibilities that he or she has by using this source/core.
|
||||
--
|
||||
-- This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
-- A PARTICULAR PURPOSE.
|
||||
--
|
||||
-- Redistribution and use of source or resulting binaries, with or without modification
|
||||
-- of this file, are permitted under one of the following two license terms:
|
||||
--
|
||||
-- 1. The GNU General Public License version 2 as published by the
|
||||
-- Free Software Foundation, which can be found in the top level directory
|
||||
-- of this repository (LICENSE_GPL2), and also online at:
|
||||
-- <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
--
|
||||
-- OR
|
||||
--
|
||||
-- 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
-- of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
-- https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
-- This will allow to generate bit files and not release the source code,
|
||||
-- as long as it attaches to an ADI device.
|
||||
--
|
||||
-- ***************************************************************************
|
||||
-- ***************************************************************************
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
|
||||
library work;
|
||||
use work.fifo_synchronizer;
|
||||
use work.i2s_clkgen;
|
||||
use work.i2s_tx;
|
||||
use work.i2s_rx;
|
||||
|
||||
entity i2s_controller is
|
||||
generic(
|
||||
C_SLOT_WIDTH : integer := 24; -- Width of one Slot
|
||||
C_BCLK_POL : integer := 0; -- BCLK Polarity (0 - Falling edge, 1 - Rising edge)
|
||||
C_LRCLK_POL : integer := 0; -- LRCLK Polarity (0 - Falling edge, 1 - Rising edge)
|
||||
C_NUM_CH : integer := 1;
|
||||
C_HAS_TX : integer := 1;
|
||||
C_HAS_RX : integer := 1
|
||||
);
|
||||
port(
|
||||
clk : in std_logic; -- System clock
|
||||
resetn : in std_logic; -- System reset
|
||||
|
||||
data_clk : in std_logic; -- Data clock should be less than clk / 4
|
||||
bclk_o : out std_logic_vector(C_NUM_CH - 1 downto 0); -- Bit Clock
|
||||
lrclk_o : out std_logic_vector(C_NUM_CH - 1 downto 0); -- Frame Clock
|
||||
sdata_o : out std_logic_vector(C_NUM_CH - 1 downto 0); -- Serial Data Output
|
||||
sdata_i : in std_logic_vector(C_NUM_CH - 1 downto 0); -- Serial Data Input
|
||||
|
||||
tx_enable : in Boolean; -- Enable TX
|
||||
tx_ack : out std_logic; -- Request new Slot Data
|
||||
tx_stb : in std_logic; -- Request new Slot Data
|
||||
tx_data : in std_logic_vector(C_SLOT_WIDTH-1 downto 0); -- Slot Data in
|
||||
|
||||
rx_enable : in Boolean; -- Enable RX
|
||||
rx_ack : in std_logic;
|
||||
rx_stb : out std_logic; -- Valid Slot Data
|
||||
rx_data : out std_logic_vector(C_SLOT_WIDTH-1 downto 0); -- Slot Data out
|
||||
|
||||
-- Runtime parameter
|
||||
bclk_div_rate : in natural range 0 to 255;
|
||||
lrclk_div_rate : in natural range 0 to 255
|
||||
);
|
||||
end i2s_controller;
|
||||
|
||||
architecture Behavioral of i2s_controller is
|
||||
constant NUM_TX : integer := C_HAS_TX * C_NUM_CH;
|
||||
constant NUM_RX : integer := C_HAS_RX * C_NUM_CH;
|
||||
|
||||
signal enable : Boolean;
|
||||
|
||||
signal cdc_sync_stage0_tick : std_logic;
|
||||
signal cdc_sync_stage1_tick : std_logic;
|
||||
signal cdc_sync_stage2_tick : std_logic;
|
||||
signal cdc_sync_stage3_tick : std_logic;
|
||||
|
||||
signal BCLK_O_int : std_logic;
|
||||
signal LRCLK_O_int : std_logic;
|
||||
|
||||
signal tx_bclk : std_logic;
|
||||
signal tx_lrclk : std_logic;
|
||||
signal tx_sdata : std_logic_vector(C_NUM_CH - 1 downto 0);
|
||||
signal tx_tick : std_logic;
|
||||
signal tx_channel_sync : std_logic;
|
||||
signal tx_frame_sync : std_logic;
|
||||
|
||||
signal const_1 : std_logic;
|
||||
signal bclk_tick : std_logic;
|
||||
|
||||
signal rx_bclk : std_logic;
|
||||
signal rx_lrclk : std_logic;
|
||||
signal rx_sdata : std_logic_vector(NUM_RX - 1 downto 0);
|
||||
signal rx_channel_sync : std_logic;
|
||||
signal rx_frame_sync : std_logic;
|
||||
|
||||
signal tx_sync_fifo_out : std_logic_vector(3 + NUM_TX downto 0);
|
||||
signal tx_sync_fifo_in : std_logic_vector(3 + NUM_TX downto 0);
|
||||
signal rx_sync_fifo_out : std_logic_vector(3 + NUM_RX downto 0);
|
||||
signal rx_sync_fifo_in : std_logic_vector(3 + NUM_RX downto 0);
|
||||
|
||||
signal data_resetn : std_logic;
|
||||
signal data_reset_vec : std_logic_vector(2 downto 0);
|
||||
|
||||
begin
|
||||
enable <= rx_enable or tx_enable;
|
||||
|
||||
const_1 <= '1';
|
||||
process (data_clk, resetn)
|
||||
begin
|
||||
if resetn = '0' then
|
||||
data_reset_vec <= (others => '1');
|
||||
elsif rising_edge(data_clk) then
|
||||
data_reset_vec(2 downto 1) <= data_reset_vec(1 downto 0);
|
||||
data_reset_vec(0) <= '0';
|
||||
end if;
|
||||
end process;
|
||||
|
||||
data_resetn <= not data_reset_vec(2);
|
||||
|
||||
-- Generate tick signal in the DATA_CLK_I domain
|
||||
process (data_clk)
|
||||
begin
|
||||
if rising_edge(data_clk) then
|
||||
cdc_sync_stage0_tick <= not cdc_sync_stage0_tick;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
cdc_sync_stage1_tick <= cdc_sync_stage0_tick;
|
||||
cdc_sync_stage2_tick <= cdc_sync_stage1_tick;
|
||||
cdc_sync_stage3_tick <= cdc_sync_stage2_tick;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
tx_tick <= cdc_sync_stage2_tick xor cdc_sync_stage3_tick;
|
||||
|
||||
tx_sync_fifo_in(0) <= tx_channel_sync;
|
||||
tx_sync_fifo_in(1) <= tx_frame_sync;
|
||||
tx_sync_fifo_in(2) <= tx_bclk;
|
||||
tx_sync_fifo_in(3) <= tx_lrclk;
|
||||
tx_sync_fifo_in(3 + NUM_TX downto 4) <= tx_sdata;
|
||||
|
||||
|
||||
process (data_clk)
|
||||
begin
|
||||
if rising_edge(data_clk) then
|
||||
if data_resetn = '0' then
|
||||
bclk_o <= (others => '1');
|
||||
lrclk_o <= (others => '1');
|
||||
sdata_o <= (others => '0');
|
||||
else
|
||||
if C_BCLK_POL = 0 then
|
||||
bclk_o <= (others => tx_sync_fifo_out(2));
|
||||
else
|
||||
bclk_o <= (others => not tx_sync_fifo_out(2));
|
||||
end if;
|
||||
|
||||
if C_LRCLK_POL = 0 then
|
||||
lrclk_o <= (others => tx_sync_fifo_out(3));
|
||||
else
|
||||
lrclk_o <= (others => not tx_sync_fifo_out(3));
|
||||
end if;
|
||||
|
||||
if C_HAS_TX = 1 then
|
||||
sdata_o <= tx_sync_fifo_out(3 + NUM_TX downto 4);
|
||||
end if;
|
||||
|
||||
if C_HAS_RX = 1 then
|
||||
rx_sync_fifo_in(3 downto 0) <= tx_sync_fifo_out(3 downto 0);
|
||||
rx_sync_fifo_in(3 + NUM_RX downto 4) <= sdata_i;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
tx_sync: entity fifo_synchronizer
|
||||
generic map (
|
||||
DEPTH => 4,
|
||||
WIDTH => NUM_TX + 4
|
||||
)
|
||||
port map (
|
||||
in_resetn => resetn,
|
||||
in_clk => clk,
|
||||
in_data => tx_sync_fifo_in,
|
||||
in_tick => tx_tick,
|
||||
|
||||
out_resetn => data_resetn,
|
||||
out_clk => data_clk,
|
||||
out_data => tx_sync_fifo_out
|
||||
);
|
||||
|
||||
clkgen: entity i2s_clkgen
|
||||
port map(
|
||||
clk => clk,
|
||||
resetn => resetn,
|
||||
enable => enable,
|
||||
tick => tx_tick,
|
||||
|
||||
bclk_div_rate => bclk_div_rate,
|
||||
lrclk_div_rate => lrclk_div_rate,
|
||||
|
||||
channel_sync => tx_channel_sync,
|
||||
frame_sync => tx_frame_sync,
|
||||
|
||||
bclk => tx_bclk,
|
||||
lrclk => tx_lrclk
|
||||
);
|
||||
|
||||
tx_gen: if C_HAS_TX = 1 generate
|
||||
tx: entity i2s_tx
|
||||
generic map (
|
||||
C_SLOT_WIDTH => C_SLOT_WIDTH,
|
||||
C_NUM => NUM_TX
|
||||
)
|
||||
port map (
|
||||
clk => clk,
|
||||
resetn => resetn,
|
||||
enable => tx_enable,
|
||||
|
||||
channel_sync => tx_channel_sync,
|
||||
frame_sync => tx_frame_sync,
|
||||
bclk => tx_bclk,
|
||||
sdata => tx_sdata,
|
||||
|
||||
ack => tx_ack,
|
||||
stb => tx_stb,
|
||||
data => tx_data
|
||||
);
|
||||
end generate;
|
||||
|
||||
rx_gen: if C_HAS_RX = 1 generate
|
||||
rx: entity i2s_rx
|
||||
generic map (
|
||||
C_SLOT_WIDTH => C_SLOT_WIDTH,
|
||||
C_NUM => NUM_RX
|
||||
)
|
||||
port map (
|
||||
clk => clk,
|
||||
resetn => resetn,
|
||||
enable => rx_enable,
|
||||
|
||||
channel_sync => rx_channel_sync,
|
||||
frame_sync => rx_frame_sync,
|
||||
bclk => rx_bclk,
|
||||
sdata => rx_sdata,
|
||||
|
||||
ack => rx_ack,
|
||||
stb => rx_stb,
|
||||
data => rx_data
|
||||
);
|
||||
|
||||
rx_channel_sync <= rx_sync_fifo_out(0);
|
||||
rx_frame_sync <= rx_sync_fifo_out(1);
|
||||
rx_bclk <= rx_sync_fifo_out(2);
|
||||
rx_lrclk <= rx_sync_fifo_out(3);
|
||||
rx_sdata <= rx_sync_fifo_out(3 + NUM_RX downto 4);
|
||||
|
||||
rx_sync: entity fifo_synchronizer
|
||||
generic map (
|
||||
DEPTH => 4,
|
||||
WIDTH => NUM_RX + 4
|
||||
)
|
||||
port map (
|
||||
in_resetn => data_resetn,
|
||||
in_clk => data_clk,
|
||||
in_data => rx_sync_fifo_in,
|
||||
in_tick => const_1,
|
||||
|
||||
out_resetn => resetn,
|
||||
out_clk => clk,
|
||||
out_data => rx_sync_fifo_out
|
||||
);
|
||||
|
||||
end generate;
|
||||
|
||||
end Behavioral;
|
||||
@@ -0,0 +1,61 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:abstractionDefinition xmlns:xilinx="http://www.xilinx.com"
|
||||
xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
|
||||
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>analog.com</spirit:vendor>
|
||||
<spirit:library>interface</spirit:library>
|
||||
<spirit:name>i2s_rtl</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busType spirit:vendor="analog.com"
|
||||
spirit:library="interface"
|
||||
spirit:name="i2s"
|
||||
spirit:version="1.0"/>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>BCLK</spirit:logicalName>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>LRCLK</spirit:logicalName>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>SDATA_OUT</spirit:logicalName>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster/>
|
||||
<spirit:onSlave>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>SDATA_IN</spirit:logicalName>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave/>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
</spirit:abstractionDefinition>
|
||||
@@ -0,0 +1,177 @@
|
||||
-- ***************************************************************************
|
||||
-- ***************************************************************************
|
||||
-- Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- In this HDL repository, there are many different and unique modules, consisting
|
||||
-- of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
-- developed independently, and may be accompanied by separate and unique license
|
||||
-- terms.
|
||||
--
|
||||
-- The user should read each of these license terms, and understand the
|
||||
-- freedoms and responsibilities that he or she has by using this source/core.
|
||||
--
|
||||
-- This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
-- A PARTICULAR PURPOSE.
|
||||
--
|
||||
-- Redistribution and use of source or resulting binaries, with or without modification
|
||||
-- of this file, are permitted under one of the following two license terms:
|
||||
--
|
||||
-- 1. The GNU General Public License version 2 as published by the
|
||||
-- Free Software Foundation, which can be found in the top level directory
|
||||
-- of this repository (LICENSE_GPL2), and also online at:
|
||||
-- <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
--
|
||||
-- OR
|
||||
--
|
||||
-- 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
-- of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
-- https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
-- This will allow to generate bit files and not release the source code,
|
||||
-- as long as it attaches to an ADI device.
|
||||
--
|
||||
-- ***************************************************************************
|
||||
-- ***************************************************************************
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity i2s_rx is
|
||||
generic(
|
||||
C_SLOT_WIDTH : integer := 24; -- Width of one Slot
|
||||
C_NUM : integer := 1
|
||||
);
|
||||
port(
|
||||
clk : in std_logic; -- System clock
|
||||
resetn : in std_logic; -- System reset
|
||||
enable : in Boolean; -- Enable RX
|
||||
|
||||
bclk : in std_logic; -- Bit Clock
|
||||
channel_sync : in std_logic; -- Channel Sync
|
||||
frame_sync : in std_logic; -- Frame Sync
|
||||
sdata : in std_logic_vector(C_NUM - 1 downto 0); -- Serial Data Output
|
||||
|
||||
stb : out std_logic; -- Data available
|
||||
ack : in std_logic; -- Data has been consumed
|
||||
data : out std_logic_vector(C_SLOT_WIDTH-1 downto 0) -- Slot Data in
|
||||
);
|
||||
end i2s_rx;
|
||||
|
||||
architecture Behavioral of i2s_rx is
|
||||
type mem is array (0 to C_NUM - 1) of std_logic_vector(31 downto 0);
|
||||
type mem_latched is array (0 to C_NUM - 1) of std_logic_vector(C_SLOT_WIDTH - 1 downto 0);
|
||||
signal data_int : mem;
|
||||
signal data_latched : mem_latched;
|
||||
signal reset_int : Boolean;
|
||||
signal enable_int : Boolean;
|
||||
|
||||
signal bit_sync : std_logic;
|
||||
signal channel_sync_int : std_logic;
|
||||
signal frame_sync_int : std_logic;
|
||||
|
||||
signal bclk_d1 : std_logic;
|
||||
|
||||
type sequencer_state_type is (IDLE, ACTIVE);
|
||||
signal sequencer_state : sequencer_state_type;
|
||||
signal seq : natural range 0 to C_NUM - 1;
|
||||
|
||||
signal ovf_frame_cnt : natural range 0 to 1;
|
||||
begin
|
||||
|
||||
reset_int <= (resetn = '0') or not enable;
|
||||
|
||||
process (clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if resetn = '0' then
|
||||
bclk_d1 <= '0';
|
||||
else
|
||||
bclk_d1 <= bclk;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
bit_sync <= (bclk xor bclk_d1) and bclk;
|
||||
channel_sync_int <= channel_sync and bit_sync;
|
||||
frame_sync_int <= frame_sync and bit_sync;
|
||||
|
||||
stb <= '1' when sequencer_state = ACTIVE else '0';
|
||||
|
||||
sequencer: process (clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if reset_int or not enable_int then
|
||||
sequencer_state <= IDLE;
|
||||
ovf_frame_cnt <= 0;
|
||||
seq <= 0;
|
||||
else
|
||||
case sequencer_state is
|
||||
when IDLE =>
|
||||
if channel_sync_int = '1' then
|
||||
if ovf_frame_cnt = 0 then
|
||||
sequencer_state <= ACTIVE;
|
||||
else
|
||||
ovf_frame_cnt <= (ovf_frame_cnt + 1) mod 2;
|
||||
end if;
|
||||
end if;
|
||||
when ACTIVE =>
|
||||
-- The unlikely event the last ack came in in the same clock
|
||||
-- cyclce as the channel sync signal will still be treated
|
||||
-- as an overflow. This keeps the logic simple
|
||||
if ack = '1' then
|
||||
if seq = C_NUM - 1 then
|
||||
sequencer_state <= IDLE;
|
||||
seq <= 0;
|
||||
else
|
||||
seq <= seq + 1;
|
||||
end if;
|
||||
end if;
|
||||
if channel_sync_int = '1' then
|
||||
ovf_frame_cnt <= (ovf_frame_cnt + 1) mod 2;
|
||||
end if;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
data <= data_latched(seq);
|
||||
|
||||
gen: for i in 0 to C_NUM - 1 generate
|
||||
|
||||
unserialize_data: process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if reset_int then
|
||||
data_int(i) <= (others => '0');
|
||||
elsif bit_sync = '1' then
|
||||
if channel_sync = '1' then
|
||||
if sequencer_state = IDLE then
|
||||
data_latched(i) <= data_int(i)(31 downto 32 - C_SLOT_WIDTH);
|
||||
-- data_latched(i) <= data_int(i)(31 downto 32 -
|
||||
-- C_SLOT_WIDTH + 8) &
|
||||
-- std_logic_vector(to_unsigned(i+1,8));
|
||||
end if;
|
||||
end if;
|
||||
data_int(i) <= data_int(i)(30 downto 0) & sdata(i);
|
||||
end if;
|
||||
end if;
|
||||
end process unserialize_data;
|
||||
end generate;
|
||||
|
||||
enable_sync: process (clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if reset_int then
|
||||
enable_int <= False;
|
||||
else
|
||||
if enable and frame_sync_int = '1' then
|
||||
enable_int <= True;
|
||||
elsif not enable then
|
||||
enable_int <= False;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process enable_sync;
|
||||
|
||||
end Behavioral;
|
||||
@@ -0,0 +1,131 @@
|
||||
-- ***************************************************************************
|
||||
-- ***************************************************************************
|
||||
-- Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
--
|
||||
-- In this HDL repository, there are many different and unique modules, consisting
|
||||
-- of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
-- developed independently, and may be accompanied by separate and unique license
|
||||
-- terms.
|
||||
--
|
||||
-- The user should read each of these license terms, and understand the
|
||||
-- freedoms and responsibilities that he or she has by using this source/core.
|
||||
--
|
||||
-- This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
-- A PARTICULAR PURPOSE.
|
||||
--
|
||||
-- Redistribution and use of source or resulting binaries, with or without modification
|
||||
-- of this file, are permitted under one of the following two license terms:
|
||||
--
|
||||
-- 1. The GNU General Public License version 2 as published by the
|
||||
-- Free Software Foundation, which can be found in the top level directory
|
||||
-- of this repository (LICENSE_GPL2), and also online at:
|
||||
-- <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
--
|
||||
-- OR
|
||||
--
|
||||
-- 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
-- of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
-- https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
-- This will allow to generate bit files and not release the source code,
|
||||
-- as long as it attaches to an ADI device.
|
||||
--
|
||||
-- ***************************************************************************
|
||||
-- ***************************************************************************
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
|
||||
entity i2s_tx is
|
||||
generic(
|
||||
C_SLOT_WIDTH : integer := 24; -- Width of one Slot
|
||||
C_NUM : integer := 1
|
||||
);
|
||||
port(
|
||||
clk : in std_logic; -- System clock
|
||||
resetn : in std_logic; -- System reset
|
||||
enable : in Boolean; -- Enable TX
|
||||
|
||||
bclk : in std_logic; -- Bit Clock
|
||||
channel_sync : in std_logic; -- Channel Sync
|
||||
frame_sync : in std_logic; -- Frame Sync
|
||||
sdata : out std_logic_vector(C_NUM - 1 downto 0); -- Serial Data Output
|
||||
|
||||
ack : out std_logic; -- Request new Slot Data
|
||||
stb : in std_logic; -- Request new Slot Data
|
||||
data : in std_logic_vector(C_SLOT_WIDTH-1 downto 0) -- Slot Data in
|
||||
);
|
||||
end i2s_tx;
|
||||
|
||||
architecture Behavioral of i2s_tx is
|
||||
type mem is array (0 to C_NUM - 1) of std_logic_vector(31 downto 0);
|
||||
signal data_int : mem;
|
||||
signal reset_int : Boolean;
|
||||
signal enable_int : Boolean;
|
||||
|
||||
signal bit_sync : std_logic;
|
||||
signal channel_sync_int : std_logic;
|
||||
signal frame_sync_int : std_logic;
|
||||
signal channel_sync_int_d1 : std_logic;
|
||||
|
||||
signal bclk_d1 : std_logic;
|
||||
begin
|
||||
|
||||
reset_int <= resetn = '0' or not enable;
|
||||
|
||||
process (clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if resetn = '0' then
|
||||
bclk_d1 <= '0';
|
||||
channel_sync_int_d1 <= '0';
|
||||
else
|
||||
bclk_d1 <= bclk;
|
||||
channel_sync_int_d1 <= channel_sync_int;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
bit_sync <= (bclk xor bclk_d1) and not bclk;
|
||||
channel_sync_int <= channel_sync and bit_sync;
|
||||
frame_sync_int <= frame_sync and bit_sync;
|
||||
|
||||
ack <= '1' when channel_sync_int_d1 = '1' and enable_int else '0';
|
||||
|
||||
gen: for i in 0 to C_NUM - 1 generate
|
||||
|
||||
serialize_data: process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if reset_int then
|
||||
data_int(i)(31 downto 0) <= (others => '0');
|
||||
elsif bit_sync = '1' then
|
||||
if channel_sync_int = '1' then
|
||||
data_int(i)(31 downto 32-C_SLOT_WIDTH) <= data;
|
||||
data_int(i)(31-C_SLOT_WIDTH downto 0) <= (others => '0');
|
||||
else
|
||||
data_int(i) <= data_int(i)(30 downto 0) & '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process serialize_data;
|
||||
sdata(i) <= data_int(i)(31) when enable_int else '0';
|
||||
|
||||
end generate;
|
||||
|
||||
enable_sync: process (clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if reset_int then
|
||||
enable_int <= False;
|
||||
else
|
||||
if enable and frame_sync_int = '1' and stb = '1' then
|
||||
enable_int <= True;
|
||||
elsif not enable then
|
||||
enable_int <= False;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end Behavioral;
|
||||
@@ -0,0 +1,164 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||
#Adding Group
|
||||
set I2S_Configuration [ipgui::add_group $IPINST -name "I2S Configuration" -parent ${Page_0}]
|
||||
ipgui::add_param $IPINST -name "SLOT_WIDTH" -parent ${I2S_Configuration} -widget comboBox
|
||||
ipgui::add_param $IPINST -name "LRCLK_POL" -parent ${I2S_Configuration} -widget comboBox
|
||||
ipgui::add_param $IPINST -name "BCLK_POL" -parent ${I2S_Configuration} -widget comboBox
|
||||
|
||||
#Adding Group
|
||||
set General_Configuration [ipgui::add_group $IPINST -name "General Configuration" -parent ${Page_0}]
|
||||
ipgui::add_param $IPINST -name "HAS_RX" -parent ${General_Configuration} -widget checkBox
|
||||
ipgui::add_param $IPINST -name "HAS_TX" -parent ${General_Configuration} -widget checkBox
|
||||
ipgui::add_param $IPINST -name "DMA_TYPE" -parent ${General_Configuration} -widget comboBox
|
||||
ipgui::add_param $IPINST -name "NUM_OF_CHANNEL" -parent ${General_Configuration}
|
||||
ipgui::add_param $IPINST -name "S_AXI_ADDRESS_WIDTH" -parent ${General_Configuration}
|
||||
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.BCLK_POL { PARAM_VALUE.BCLK_POL } {
|
||||
# Procedure called to update BCLK_POL when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.BCLK_POL { PARAM_VALUE.BCLK_POL } {
|
||||
# Procedure called to validate BCLK_POL
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DEVICE_FAMILY { PARAM_VALUE.DEVICE_FAMILY } {
|
||||
# Procedure called to update DEVICE_FAMILY when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DEVICE_FAMILY { PARAM_VALUE.DEVICE_FAMILY } {
|
||||
# Procedure called to validate DEVICE_FAMILY
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DMA_TYPE { PARAM_VALUE.DMA_TYPE } {
|
||||
# Procedure called to update DMA_TYPE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DMA_TYPE { PARAM_VALUE.DMA_TYPE } {
|
||||
# Procedure called to validate DMA_TYPE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.HAS_RX { PARAM_VALUE.HAS_RX } {
|
||||
# Procedure called to update HAS_RX when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.HAS_RX { PARAM_VALUE.HAS_RX } {
|
||||
# Procedure called to validate HAS_RX
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.HAS_TX { PARAM_VALUE.HAS_TX } {
|
||||
# Procedure called to update HAS_TX when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.HAS_TX { PARAM_VALUE.HAS_TX } {
|
||||
# Procedure called to validate HAS_TX
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.LRCLK_POL { PARAM_VALUE.LRCLK_POL } {
|
||||
# Procedure called to update LRCLK_POL when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.LRCLK_POL { PARAM_VALUE.LRCLK_POL } {
|
||||
# Procedure called to validate LRCLK_POL
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.NUM_OF_CHANNEL { PARAM_VALUE.NUM_OF_CHANNEL } {
|
||||
# Procedure called to update NUM_OF_CHANNEL when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.NUM_OF_CHANNEL { PARAM_VALUE.NUM_OF_CHANNEL } {
|
||||
# Procedure called to validate NUM_OF_CHANNEL
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.SLOT_WIDTH { PARAM_VALUE.SLOT_WIDTH } {
|
||||
# Procedure called to update SLOT_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.SLOT_WIDTH { PARAM_VALUE.SLOT_WIDTH } {
|
||||
# Procedure called to validate SLOT_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.S_AXI_ADDRESS_WIDTH { PARAM_VALUE.S_AXI_ADDRESS_WIDTH } {
|
||||
# Procedure called to update S_AXI_ADDRESS_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.S_AXI_ADDRESS_WIDTH { PARAM_VALUE.S_AXI_ADDRESS_WIDTH } {
|
||||
# Procedure called to validate S_AXI_ADDRESS_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.S_AXI_DATA_WIDTH { PARAM_VALUE.S_AXI_DATA_WIDTH } {
|
||||
# Procedure called to update S_AXI_DATA_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.S_AXI_DATA_WIDTH { PARAM_VALUE.S_AXI_DATA_WIDTH } {
|
||||
# Procedure called to validate S_AXI_DATA_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.SLOT_WIDTH { MODELPARAM_VALUE.SLOT_WIDTH PARAM_VALUE.SLOT_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.SLOT_WIDTH}] ${MODELPARAM_VALUE.SLOT_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.LRCLK_POL { MODELPARAM_VALUE.LRCLK_POL PARAM_VALUE.LRCLK_POL } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.LRCLK_POL}] ${MODELPARAM_VALUE.LRCLK_POL}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.BCLK_POL { MODELPARAM_VALUE.BCLK_POL PARAM_VALUE.BCLK_POL } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.BCLK_POL}] ${MODELPARAM_VALUE.BCLK_POL}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.S_AXI_DATA_WIDTH { MODELPARAM_VALUE.S_AXI_DATA_WIDTH PARAM_VALUE.S_AXI_DATA_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.S_AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.S_AXI_DATA_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.S_AXI_ADDRESS_WIDTH { MODELPARAM_VALUE.S_AXI_ADDRESS_WIDTH PARAM_VALUE.S_AXI_ADDRESS_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.S_AXI_ADDRESS_WIDTH}] ${MODELPARAM_VALUE.S_AXI_ADDRESS_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DEVICE_FAMILY { MODELPARAM_VALUE.DEVICE_FAMILY PARAM_VALUE.DEVICE_FAMILY } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DEVICE_FAMILY}] ${MODELPARAM_VALUE.DEVICE_FAMILY}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DMA_TYPE { MODELPARAM_VALUE.DMA_TYPE PARAM_VALUE.DMA_TYPE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DMA_TYPE}] ${MODELPARAM_VALUE.DMA_TYPE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.NUM_OF_CHANNEL { MODELPARAM_VALUE.NUM_OF_CHANNEL PARAM_VALUE.NUM_OF_CHANNEL } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.NUM_OF_CHANNEL}] ${MODELPARAM_VALUE.NUM_OF_CHANNEL}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.HAS_TX { MODELPARAM_VALUE.HAS_TX PARAM_VALUE.HAS_TX } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.HAS_TX}] ${MODELPARAM_VALUE.HAS_TX}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.HAS_RX { MODELPARAM_VALUE.HAS_RX PARAM_VALUE.HAS_RX } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.HAS_RX}] ${MODELPARAM_VALUE.HAS_RX}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user