Archived
first commit after restructuring
This commit is contained in:
@@ -0,0 +1,29 @@
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####################################################################################
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||||
## Copyright 2018(c) Analog Devices, Inc.
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||||
## Auto-generated, do not modify!
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||||
####################################################################################
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||||
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||||
LIBRARY_NAME := axi_laser_driver
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||||
|
||||
GENERIC_DEPS += ../common/up_clock_mon.v
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GENERIC_DEPS += axi_laser_driver.v
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GENERIC_DEPS += axi_laser_driver_regmap.v
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||||
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||||
XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc
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||||
XILINX_DEPS += axi_laser_driver_constr.xdc
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XILINX_DEPS += axi_laser_driver_ip.tcl
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XILINX_LIB_DEPS += axi_pulse_gen
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XILINX_LIB_DEPS += util_cdc
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INTEL_DEPS += ../axi_pulse_gen/axi_pulse_gen_constr.sdc
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||||
INTEL_DEPS += ../axi_pulse_gen/axi_pulse_gen_regmap.v
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INTEL_DEPS += ../common/ad_rst.v
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INTEL_DEPS += ../common/up_axi.v
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||||
INTEL_DEPS += ../common/util_pulse_gen.v
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||||
INTEL_DEPS += ../util_cdc/sync_bits.v
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INTEL_DEPS += ../util_cdc/sync_event.v
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INTEL_DEPS += axi_laser_driver_constr.sdc
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INTEL_DEPS += axi_laser_driver_hw.tcl
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include ../scripts/library.mk
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@@ -0,0 +1,3 @@
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version:1
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6d6f64655f636f756e7465727c42617463684d6f6465:1
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eof:
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@@ -0,0 +1,6 @@
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||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<labtools version="1" minor="0"/>
|
||||
@@ -0,0 +1,301 @@
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||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2019 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
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||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
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||||
`timescale 1ns/100ps
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||||
module axi_laser_driver #(
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||||
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parameter ID = 0,
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parameter [0:0] ASYNC_CLK_EN = 1,
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parameter PULSE_WIDTH = 7,
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parameter PULSE_PERIOD = 10 )(
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// axi interface
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input s_axi_aclk,
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input s_axi_aresetn,
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input s_axi_awvalid,
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input [15:0] s_axi_awaddr,
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||||
input [ 2:0] s_axi_awprot,
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||||
output s_axi_awready,
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||||
input s_axi_wvalid,
|
||||
input [31:0] s_axi_wdata,
|
||||
input [ 3:0] s_axi_wstrb,
|
||||
output s_axi_wready,
|
||||
output s_axi_bvalid,
|
||||
output [ 1:0] s_axi_bresp,
|
||||
input s_axi_bready,
|
||||
input s_axi_arvalid,
|
||||
input [15:0] s_axi_araddr,
|
||||
input [ 2:0] s_axi_arprot,
|
||||
output s_axi_arready,
|
||||
output s_axi_rvalid,
|
||||
output [ 1:0] s_axi_rresp,
|
||||
output [31:0] s_axi_rdata,
|
||||
input s_axi_rready,
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||||
|
||||
// external clock and control/status signals
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||||
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||||
input ext_clk,
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||||
output driver_en_n,
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output driver_pulse,
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||||
input driver_otw_n,
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output driver_dp_reset,
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output reg [ 7:0] tia_chsel,
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||||
|
||||
// interrupt
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||||
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||||
output irq);
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||||
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// internal signals
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||||
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||||
reg up_wack = 1'b0;
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reg up_rack = 1'b0;
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reg [31:0] up_rdata = 32'b0;
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reg driver_pulse_int_d = 1'b0;
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reg [ 1:0] sequence_counter = 2'b00;
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||||
// internal signals
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wire clk;
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wire up_clk;
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wire up_rstn;
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wire up_rreq_s;
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wire up_rack_ld_s;
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wire up_rack_pwm_s;
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wire [13:0] up_raddr_s;
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wire [31:0] up_rdata_ld_s;
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wire [31:0] up_rdata_pwm_s;
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wire up_wreq_s;
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wire up_wack_ld_s;
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wire up_wack_pwm_s;
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wire [13:0] up_waddr_s;
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wire [31:0] up_wdata_s;
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wire [31:0] pulse_width_s;
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wire [31:0] pulse_period_s;
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wire load_config_s;
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wire pulse_gen_resetn;
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wire [31:0] pulse_counter_s;
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wire driver_pulse_int_s;
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wire [31:0] up_ext_clk_count_s;
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||||
wire sequence_en_s;
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||||
wire auto_sequence_s;
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||||
wire [31:0] sequence_offset_s;
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wire [ 1:0] auto_seq0_s;
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wire [ 1:0] auto_seq1_s;
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||||
wire [ 1:0] auto_seq2_s;
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||||
wire [ 1:0] auto_seq3_s;
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wire [ 7:0] manual_select_s;
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||||
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||||
// local parameters
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||||
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||||
localparam [31:0] CORE_VERSION = {16'h0001, /* MAJOR */
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8'h00, /* MINOR */
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8'h61}; /* PATCH */ // 1.00.a
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||||
localparam [31:0] CORE_MAGIC = 32'h4C534452; // LSDR
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||||
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||||
assign up_clk = s_axi_aclk;
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assign up_rstn = s_axi_aresetn;
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||||
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||||
// register maps
|
||||
|
||||
axi_pulse_gen_regmap #(
|
||||
.ID (ID),
|
||||
.CORE_MAGIC (CORE_MAGIC),
|
||||
.CORE_VERSION (CORE_VERSION),
|
||||
.ASYNC_CLK_EN (ASYNC_CLK_EN),
|
||||
.PULSE_WIDTH (PULSE_WIDTH),
|
||||
.PULSE_PERIOD (PULSE_PERIOD))
|
||||
i_pwm_regmap (
|
||||
.ext_clk (ext_clk),
|
||||
.clk_out (clk),
|
||||
.pulse_gen_resetn (pulse_gen_resetn),
|
||||
.pulse_width (pulse_width_s),
|
||||
.pulse_period (pulse_period_s),
|
||||
.load_config (load_config_s),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq_s),
|
||||
.up_waddr (up_waddr_s),
|
||||
.up_wdata (up_wdata_s),
|
||||
.up_wack (up_wack_pwm_s),
|
||||
.up_rreq (up_rreq_s),
|
||||
.up_raddr (up_raddr_s),
|
||||
.up_rdata (up_rdata_pwm_s),
|
||||
.up_rack (up_rack_pwm_s));
|
||||
|
||||
axi_laser_driver_regmap #(
|
||||
.ID (ID),
|
||||
.LASER_DRIVER_ID (1))
|
||||
i_laser_driver_regmap (
|
||||
.clk (clk),
|
||||
.driver_en_n (driver_en_n),
|
||||
.driver_otw_n (driver_otw_n),
|
||||
.pulse (driver_pulse_int_s),
|
||||
.up_ext_clk_count (up_ext_clk_count_s),
|
||||
.irq (irq),
|
||||
.sequence_en (sequence_en_s),
|
||||
.auto_sequence (auto_sequence_s),
|
||||
.sequence_offset (sequence_offset_s),
|
||||
.auto_seq0 (auto_seq0_s),
|
||||
.auto_seq1 (auto_seq1_s),
|
||||
.auto_seq2 (auto_seq2_s),
|
||||
.auto_seq3 (auto_seq3_s),
|
||||
.manual_select (manual_select_s),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq_s),
|
||||
.up_waddr (up_waddr_s),
|
||||
.up_wdata (up_wdata_s),
|
||||
.up_wack (up_wack_ld_s),
|
||||
.up_rreq (up_rreq_s),
|
||||
.up_raddr (up_raddr_s),
|
||||
.up_rdata (up_rdata_ld_s),
|
||||
.up_rack (up_rack_ld_s));
|
||||
|
||||
// read interface merge
|
||||
|
||||
always @(posedge up_clk) begin
|
||||
if (up_rstn == 0) begin
|
||||
up_wack <= 'd0;
|
||||
up_rack <= 'd0;
|
||||
up_rdata <= 'd0;
|
||||
end else begin
|
||||
up_wack <= up_wack_ld_s | up_wack_pwm_s;
|
||||
up_rack <= up_rack_ld_s | up_rack_pwm_s;
|
||||
up_rdata <= up_rdata_ld_s | up_rdata_pwm_s;
|
||||
end
|
||||
end
|
||||
|
||||
// generic PWM generator's
|
||||
|
||||
util_pulse_gen #(
|
||||
.PULSE_WIDTH(PULSE_WIDTH),
|
||||
.PULSE_PERIOD(PULSE_PERIOD))
|
||||
i_laser_driver_pulse (
|
||||
.clk (clk),
|
||||
.rstn (pulse_gen_resetn),
|
||||
.pulse_width (pulse_width_s),
|
||||
.pulse_period (pulse_period_s),
|
||||
.load_config (load_config_s),
|
||||
.pulse (driver_pulse_int_s),
|
||||
.pulse_counter (pulse_counter_s));
|
||||
|
||||
// data path reset generation
|
||||
// this logic will generate a reset signal right before the generated pulse
|
||||
// in order to use it for resetting the cpack module, to synchronize it to
|
||||
// the driver pulse
|
||||
always @(posedge clk) begin
|
||||
driver_pulse_int_d <= driver_pulse_int_s;
|
||||
end
|
||||
assign driver_dp_reset = driver_pulse_int_s & ~driver_pulse_int_d;
|
||||
assign driver_pulse = driver_pulse_int_d;
|
||||
|
||||
// clock monitor for the external clock
|
||||
|
||||
up_clock_mon i_clock_mon (
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_d_count (up_ext_clk_count_s),
|
||||
.d_rst (~pulse_gen_resetn),
|
||||
.d_clk (ext_clk));
|
||||
|
||||
// TIA sequencer
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (sequence_en_s == 1'b0) begin
|
||||
sequence_counter <= 2'b00;
|
||||
end else begin
|
||||
if (pulse_counter_s == sequence_offset_s) begin
|
||||
if (auto_sequence_s) begin
|
||||
sequence_counter <= sequence_counter + 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (sequence_en_s == 1'b0) begin
|
||||
tia_chsel <= 8'h00;
|
||||
end else begin
|
||||
if (pulse_counter_s == sequence_offset_s) begin
|
||||
if (auto_sequence_s) begin
|
||||
case (sequence_counter)
|
||||
2'b00 : tia_chsel <= {auto_seq0_s, auto_seq0_s, auto_seq0_s, auto_seq0_s};
|
||||
2'b01 : tia_chsel <= {auto_seq1_s, auto_seq1_s, auto_seq1_s, auto_seq1_s};
|
||||
2'b10 : tia_chsel <= {auto_seq2_s, auto_seq2_s, auto_seq2_s, auto_seq2_s};
|
||||
2'b11 : tia_chsel <= {auto_seq3_s, auto_seq3_s, auto_seq3_s, auto_seq3_s};
|
||||
default : tia_chsel <= 8'h00;
|
||||
endcase
|
||||
end else begin
|
||||
tia_chsel <= manual_select_s;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// AXI Memory Mapped Wrapper
|
||||
|
||||
up_axi #(
|
||||
.AXI_ADDRESS_WIDTH(16))
|
||||
i_up_axi (
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_axi_awvalid (s_axi_awvalid),
|
||||
.up_axi_awaddr (s_axi_awaddr),
|
||||
.up_axi_awready (s_axi_awready),
|
||||
.up_axi_wvalid (s_axi_wvalid),
|
||||
.up_axi_wdata (s_axi_wdata),
|
||||
.up_axi_wstrb (s_axi_wstrb),
|
||||
.up_axi_wready (s_axi_wready),
|
||||
.up_axi_bvalid (s_axi_bvalid),
|
||||
.up_axi_bresp (s_axi_bresp),
|
||||
.up_axi_bready (s_axi_bready),
|
||||
.up_axi_arvalid (s_axi_arvalid),
|
||||
.up_axi_araddr (s_axi_araddr),
|
||||
.up_axi_arready (s_axi_arready),
|
||||
.up_axi_rvalid (s_axi_rvalid),
|
||||
.up_axi_rresp (s_axi_rresp),
|
||||
.up_axi_rdata (s_axi_rdata),
|
||||
.up_axi_rready (s_axi_rready),
|
||||
.up_wreq (up_wreq_s),
|
||||
.up_waddr (up_waddr_s),
|
||||
.up_wdata (up_wdata_s),
|
||||
.up_wack (up_wack),
|
||||
.up_rreq (up_rreq_s),
|
||||
.up_raddr (up_raddr_s),
|
||||
.up_rdata (up_rdata),
|
||||
.up_rack (up_rack));
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,402 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Version="7" Minor="40" Path="/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_laser_driver/axi_laser_driver.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="b9a39497d6af452dbde72fd439f0a5c9"/>
|
||||
<Option Name="Part" Val="xc7vx485tffg1157-1"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="BoardPart" Val=""/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../library"/>
|
||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../../ghdl/library"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="DSAVendor" Val="xilinx"/>
|
||||
<Option Name="DSANumComputeUnits" Val="60"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="0"/>
|
||||
<Option Name="WTModelSimExportSim" Val="0"/>
|
||||
<Option Name="WTQuestaExportSim" Val="0"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="0"/>
|
||||
<Option Name="WTRivieraExportSim" Val="0"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
<Option Name="SimTypes" Val="bfm"/>
|
||||
<Option Name="SimTypes" Val="tlm"/>
|
||||
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="31">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/axi_laser_driver_regmap.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../common/up_clock_mon.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/axi_laser_driver.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/component.xml">
|
||||
<FileInfo SFType="IPXACT"/>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="axi_laser_driver"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<File Path="$PPRDIR/../xilinx/common/up_clock_mon_constr.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/axi_laser_driver_constr.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="IES">
|
||||
<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Xcelium">
|
||||
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="VCS">
|
||||
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="10">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Vivado 12-1790"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="1"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="Evaluation"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="features"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="should"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="NOT"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="be"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="used"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="in"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="production"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="systems."/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Place 30-73"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="10"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="axi_spi"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val=""/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="11"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1343"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="2"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1306"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="3"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="ERROR"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1276"/>
|
||||
<MsgAttr Name="Severity" Val="CRITICAL WARNING"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="4"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-3656"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="5"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-4623"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="6"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-459"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="7"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Synth 8-3331"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="8"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Designutils 20-3303"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="9"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="HDPYFinalizeIO"/>
|
||||
</MsgRule>
|
||||
<Board/>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
<BootPmcSettings Version="1" Minor="0">
|
||||
<Parameters>
|
||||
<Parameter Name="PMC_CDO.ATTRS.LOADADDR" Value="" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_FB_CLK" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_FREQ" Value="300" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_BUS_WIDTH" Value="x1" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_DATA_MODE" Value="Single" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_FREQ" Value="200" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_SLOT_TYPE" Value="SD 2.0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_FREQ" Value="200" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_SLOT_TYPE" Value="SD 2.0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSPI_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSPI_FREQ" Value="300" Type="string"/>
|
||||
<Parameter Name="BOOT.USB_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SMAP_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SMAP_DATA_WIDTH" Value="32 Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSC_FREQ" Value="33.333" Type="string"/>
|
||||
<Parameter Name="BOOT.SECONDARY.PCIE_ENABLE" Value="0" Type="string"/>
|
||||
</Parameters>
|
||||
</BootPmcSettings>
|
||||
</Project>
|
||||
@@ -0,0 +1,16 @@
|
||||
|
||||
set_false_path \
|
||||
-to [get_registers *i_driver_otw_sync|cdc_sync_stage1*]
|
||||
|
||||
set_false_path \
|
||||
-to [get_registers *i_pulse_sync|cdc_sync_stage1*]
|
||||
|
||||
set_false_path \
|
||||
-to [get_registers *i_sequencer_sync|cdc_sync_stage1[*]]
|
||||
|
||||
set_false_path \
|
||||
-to [get_registers *i_sequence_offset_sync|cdc_sync_stage1[*]]
|
||||
|
||||
set_false_path \
|
||||
-to [get_registers *i_sequence_control_sync|cdc_sync_stage1[*]]
|
||||
|
||||
@@ -0,0 +1,20 @@
|
||||
|
||||
set_property ASYNC_REG TRUE \
|
||||
[get_cells -hier {*cdc_sync_stage1_reg*}] \
|
||||
[get_cells -hier {*cdc_sync_stage2_reg*}]
|
||||
|
||||
set_false_path \
|
||||
-to [get_pins -hierarchical * -filter {NAME=~*i_driver_otw_sync/cdc_sync_stage1_reg[0]/D}]
|
||||
|
||||
set_false_path \
|
||||
-to [get_pins -hierarchical * -filter {NAME=~*i_pulse_sync/cdc_sync_stage1_reg[0]/D}]
|
||||
|
||||
set_false_path \
|
||||
-to [get_pins -hierarchical * -filter {NAME=~*i_sequencer_sync/cdc_sync_stage1_reg[*]/D}]
|
||||
|
||||
set_false_path \
|
||||
-to [get_pins -hierarchical * -filter {NAME=~*i_sequence_offset_sync/cdc_sync_stage1_reg[*]/D}]
|
||||
|
||||
set_false_path \
|
||||
-to [get_pins -hierarchical * -filter {NAME=~*i_sequence_control_sync/cdc_sync_stage1_reg[*]/D}]
|
||||
|
||||
@@ -0,0 +1,81 @@
|
||||
|
||||
package require qsys
|
||||
source ../scripts/adi_env.tcl
|
||||
source ../scripts/adi_ip_intel.tcl
|
||||
|
||||
set_module_property NAME axi_laser_driver
|
||||
set_module_property DESCRIPTION "AXI Laser Driver IP for Lidar prototyping platform "
|
||||
set_module_property VERSION 1.0
|
||||
set_module_property GROUP "Analog Devices"
|
||||
set_module_property DISPLAY_NAME axi_laser_driver
|
||||
|
||||
# source files
|
||||
|
||||
ad_ip_files axi_laser_driver [list \
|
||||
"$ad_hdl_dir/library/util_cdc/sync_bits.v" \
|
||||
"$ad_hdl_dir/library/util_cdc/sync_event.v" \
|
||||
"$ad_hdl_dir/library/common/ad_rst.v" \
|
||||
"$ad_hdl_dir/library/common/up_axi.v" \
|
||||
"$ad_hdl_dir/library/common/up_clock_mon.v" \
|
||||
"$ad_hdl_dir/library/common/util_pulse_gen.v" \
|
||||
"$ad_hdl_dir/library/axi_pulse_gen/axi_pulse_gen_regmap.v" \
|
||||
"$ad_hdl_dir/library/axi_pulse_gen/axi_pulse_gen_constr.sdc" \
|
||||
"axi_laser_driver_constr.sdc" \
|
||||
"axi_laser_driver_regmap.v" \
|
||||
"axi_laser_driver.v"]
|
||||
|
||||
# IP parameters
|
||||
|
||||
add_parameter ID INTEGER 0
|
||||
set_parameter_property ID DEFAULT_VALUE 0
|
||||
set_parameter_property ID DISPLAY_NAME "Core ID"
|
||||
set_parameter_property ID UNITS None
|
||||
set_parameter_property ID HDL_PARAMETER true
|
||||
|
||||
add_parameter ASYNC_CLK_EN INTEGER 0
|
||||
set_parameter_property ASYNC_CLK_EN DEFAULT_VALUE 0
|
||||
set_parameter_property ASYNC_CLK_EN DISPLAY_NAME "Asynchronous Clocks"
|
||||
set_parameter_property ASYNC_CLK_EN DISPLAY_HINT boolean
|
||||
set_parameter_property ASYNC_CLK_EN ALLOWED_RANGES { "0:Disabled" "1:Enabled"}
|
||||
set_parameter_property ASYNC_CLK_EN HDL_PARAMETER true
|
||||
|
||||
add_parameter PULSE_WIDTH INTEGER 0
|
||||
set_parameter_property PULSE_WIDTH DEFAULT_VALUE 0
|
||||
set_parameter_property PULSE_WIDTH DISPLAY_NAME "PWM pulse width"
|
||||
set_parameter_property PULSE_WIDTH UNITS None
|
||||
set_parameter_property PULSE_WIDTH HDL_PARAMETER true
|
||||
|
||||
add_parameter PULSE_PERIOD INTEGER 0
|
||||
set_parameter_property PULSE_PERIOD DEFAULT_VALUE 0
|
||||
set_parameter_property PULSE_PERIOD DISPLAY_NAME "PWM period"
|
||||
set_parameter_property PULSE_PERIOD UNITS None
|
||||
set_parameter_property PULSE_PERIOD HDL_PARAMETER true
|
||||
|
||||
# AXI4 Memory Mapped Interface
|
||||
|
||||
ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn 15
|
||||
|
||||
# Interrupt interface
|
||||
|
||||
add_interface interrupt_sender interrupt end
|
||||
set_interface_property interrupt_sender associatedAddressablePoint s_axi
|
||||
set_interface_property interrupt_sender associatedClock s_axi_clock
|
||||
set_interface_property interrupt_sender associatedReset s_axi_reset
|
||||
set_interface_property interrupt_sender ENABLED true
|
||||
set_interface_property interrupt_sender EXPORT_OF ""
|
||||
set_interface_property interrupt_sender PORT_NAME_MAP ""
|
||||
set_interface_property interrupt_sender CMSIS_SVD_VARIABLES ""
|
||||
set_interface_property interrupt_sender SVD_ADDRESS_GROUP ""
|
||||
|
||||
add_interface_port interrupt_sender irq irq Output 1
|
||||
|
||||
# external clock and control/status ports
|
||||
|
||||
ad_interface clock ext_clk input 1
|
||||
|
||||
ad_interface signal driver_en_n output 1
|
||||
ad_interface signal driver_pulse output 1
|
||||
ad_interface signal driver_otw_n input 1
|
||||
ad_interface reset driver_dp_reset output 1 if_ext_clk
|
||||
ad_interface signal tia_chsel output 8
|
||||
|
||||
@@ -0,0 +1,97 @@
|
||||
# ip
|
||||
|
||||
source ../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
|
||||
adi_ip_create axi_laser_driver
|
||||
adi_ip_files axi_laser_driver [list \
|
||||
"$ad_hdl_dir/library/common/up_clock_mon.v" \
|
||||
"$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \
|
||||
"axi_laser_driver_constr.xdc" \
|
||||
"axi_laser_driver_regmap.v" \
|
||||
"axi_laser_driver.v"]
|
||||
|
||||
adi_ip_properties axi_laser_driver
|
||||
adi_ip_ttcl axi_laser_driver "../axi_pulse_gen/axi_pulse_gen_constr.ttcl"
|
||||
|
||||
adi_ip_add_core_dependencies { \
|
||||
analog.com:user:util_cdc:1.0 \
|
||||
analog.com:user:axi_pulse_gen:1.0 \
|
||||
}
|
||||
|
||||
set cc [ipx::current_core]
|
||||
|
||||
set_property display_name "ADI AXI Laser Driver" $cc
|
||||
set_property description "ADI AXI Laser Driver" $cc
|
||||
|
||||
## define ext_clk port as a clock interface
|
||||
adi_add_bus ext_clk slave \
|
||||
"xilinx.com:signal:clock_rtl:1.0" \
|
||||
"xilinx.com:signal:clock:1.0" \
|
||||
[list {"ext_clk" "CLK"} ]
|
||||
|
||||
adi_set_ports_dependency "ext_clk" \
|
||||
"(spirit:decode(id('MODELPARAM_VALUE.ASYNC_CLK_EN')) = 1)" 0
|
||||
|
||||
## Parameter validation
|
||||
|
||||
set_property -dict [list \
|
||||
"value_format" "bool" \
|
||||
"value" "true" \
|
||||
] \
|
||||
[ipx::get_user_parameters ASYNC_CLK_EN -of_objects $cc]
|
||||
|
||||
set_property -dict [list \
|
||||
"value_format" "bool" \
|
||||
"value" "true" \
|
||||
] \
|
||||
[ipx::get_hdl_parameters ASYNC_CLK_EN -of_objects $cc]
|
||||
|
||||
set_property -dict [list \
|
||||
"value_validation_type" "range_long" \
|
||||
"value_validation_range_minimum" "0" \
|
||||
"value_validation_range_maximum" "2147483647" \
|
||||
] \
|
||||
[ipx::get_user_parameters PULSE_WIDTH -of_objects $cc]
|
||||
|
||||
set_property -dict [list \
|
||||
"value_validation_type" "range_long" \
|
||||
"value_validation_range_minimum" "0" \
|
||||
"value_validation_range_maximum" "2147483647" \
|
||||
] \
|
||||
[ipx::get_user_parameters PULSE_PERIOD -of_objects $cc]
|
||||
|
||||
## Customize XGUI layout
|
||||
|
||||
## Remove the automatically generated GUI page
|
||||
ipgui::remove_page -component $cc [ipgui::get_pagespec -name "Page 0" -component $cc]
|
||||
ipx::save_core $cc
|
||||
|
||||
## Create a new GUI page
|
||||
|
||||
ipgui::add_page -name {AXI Pulse Generator} -component $cc -display_name {AXI Pulse Generator}
|
||||
set page0 [ipgui::get_pagespec -name "AXI Pulse Generator" -component $cc]
|
||||
|
||||
ipgui::add_param -name "ASYNC_CLK_EN" -component $cc -parent $page0
|
||||
set_property -dict [list \
|
||||
"display_name" "ASYNC_CLK_EN" \
|
||||
"tooltip" "External clock for the counter" \
|
||||
"widget" "checkBox" \
|
||||
] [ipgui::get_guiparamspec -name "ASYNC_CLK_EN" -component $cc]
|
||||
|
||||
ipgui::add_param -name "PULSE_WIDTH" -component $cc -parent $page0
|
||||
set_property -dict [list \
|
||||
"display_name" "Pulse width" \
|
||||
"tooltip" "Pulse width of the generated signal. The unit interval is the system or external clock period." \
|
||||
] [ipgui::get_guiparamspec -name "PULSE_WIDTH" -component $cc]
|
||||
|
||||
ipgui::add_param -name "PULSE_PERIOD" -component $cc -parent $page0
|
||||
set_property -dict [list \
|
||||
"display_name" "Pulse period" \
|
||||
"tooltip" "Period of the generated signal. The unit interval is the system or external clock period." \
|
||||
] [ipgui::get_guiparamspec -name "PULSE_PERIOD" -component $cc]
|
||||
|
||||
## Save the modifications
|
||||
|
||||
ipx::create_xgui_files $cc
|
||||
ipx::save_core $cc
|
||||
@@ -0,0 +1,280 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2019 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module axi_laser_driver_regmap #(
|
||||
|
||||
parameter ID = 0,
|
||||
parameter LASER_DRIVER_ID = 1 )(
|
||||
|
||||
// control and status signals
|
||||
|
||||
input clk,
|
||||
output driver_en_n,
|
||||
input driver_otw_n,
|
||||
|
||||
input pulse,
|
||||
output reg irq,
|
||||
|
||||
input [31:0] up_ext_clk_count,
|
||||
|
||||
// TIA sequencer
|
||||
|
||||
output sequence_en,
|
||||
output auto_sequence,
|
||||
output [31:0] sequence_offset,
|
||||
|
||||
output [ 1:0] auto_seq0,
|
||||
output [ 1:0] auto_seq1,
|
||||
output [ 1:0] auto_seq2,
|
||||
output [ 1:0] auto_seq3,
|
||||
|
||||
output [ 7:0] manual_select,
|
||||
|
||||
// processor interface
|
||||
|
||||
input up_rstn,
|
||||
input up_clk,
|
||||
input up_wreq,
|
||||
input [13:0] up_waddr,
|
||||
input [31:0] up_wdata,
|
||||
output reg up_wack,
|
||||
input up_rreq,
|
||||
input [13:0] up_raddr,
|
||||
output reg [31:0] up_rdata,
|
||||
output reg up_rack
|
||||
);
|
||||
|
||||
// internal registers
|
||||
|
||||
reg up_driver_en_n = 1'b0;
|
||||
reg [2:0] up_irq_mask = 3'b111;
|
||||
reg [2:0] up_irq_source = 3'b000;
|
||||
reg up_driver_otw_n_int = 1'b1;
|
||||
|
||||
reg up_sequence_en = 1'b0;
|
||||
reg up_auto_sequence = 1'b1;
|
||||
reg [31:0] up_sequence_offset = 32'b0;
|
||||
reg [ 1:0] up_auto_seq0 = 2'b00;
|
||||
reg [ 1:0] up_auto_seq1 = 2'b01;
|
||||
reg [ 1:0] up_auto_seq2 = 2'b10;
|
||||
reg [ 1:0] up_auto_seq3 = 2'b11;
|
||||
reg [ 7:0] up_manual_select = 8'h00;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire up_wreq_int_s;
|
||||
wire up_rreq_int_s;
|
||||
wire up_driver_otw_n_s;
|
||||
wire [2:0] up_irq_pending_s;
|
||||
wire [2:0] up_irq_trigger_s;
|
||||
wire [2:0] up_irq_source_clear_s;
|
||||
wire up_pulse_s;
|
||||
|
||||
wire up_driver_otw_n_enter_s;
|
||||
wire up_driver_otw_n_exit_s;
|
||||
|
||||
// map the laser driver registers into the address space
|
||||
|
||||
assign up_wreq_int_s = (up_waddr[13:5] == LASER_DRIVER_ID) ? up_wreq : 1'b0;
|
||||
assign up_rreq_int_s = (up_raddr[13:5] == LASER_DRIVER_ID) ? up_rreq : 1'b0;
|
||||
|
||||
always @(posedge up_clk) begin
|
||||
if (up_rstn == 0) begin
|
||||
up_wack <= 1'b0;
|
||||
up_driver_en_n <= 1'b1; // by default laser is disabled
|
||||
up_irq_mask <= 3'b111;
|
||||
up_sequence_en <= 1'b0;
|
||||
up_auto_sequence <= 1'b1;
|
||||
up_sequence_offset <= 32'h19; // 25*4ns is the default offset for TIA selection
|
||||
up_auto_seq0 <= 2'b00;
|
||||
up_auto_seq1 <= 2'b01;
|
||||
up_auto_seq2 <= 2'b10;
|
||||
up_auto_seq3 <= 2'b11;
|
||||
up_manual_select <= 8'h00;
|
||||
end else begin
|
||||
up_wack <= up_wreq_int_s;
|
||||
if ((up_wreq_int_s == 1'b1) && (up_waddr[3:0] == 4'h0)) begin
|
||||
up_driver_en_n <= up_wdata[0];
|
||||
end
|
||||
if ((up_wreq_int_s == 1'b1) && (up_waddr[3:0] == 4'h8)) begin
|
||||
up_irq_mask <= up_wdata[2:0];
|
||||
end
|
||||
if ((up_wreq_int_s == 1'b1) && (up_waddr[3:0] == 4'hB)) begin
|
||||
up_sequence_en <= up_wdata[0];
|
||||
up_auto_sequence <= up_wdata[1];
|
||||
end
|
||||
if ((up_wreq_int_s == 1'b1) && (up_waddr[3:0] == 4'hC)) begin
|
||||
up_sequence_offset <= up_wdata;
|
||||
end
|
||||
if ((up_wreq_int_s == 1'b1) && (up_waddr[3:0] == 4'hD)) begin
|
||||
up_auto_seq0 <= up_wdata[1:0];
|
||||
up_auto_seq1 <= up_wdata[5:4];
|
||||
up_auto_seq2 <= up_wdata[9:8];
|
||||
up_auto_seq3 <= up_wdata[13:12];
|
||||
end
|
||||
if ((up_wreq_int_s == 1'b1) && (up_waddr[3:0] == 4'hE)) begin
|
||||
up_manual_select <= {up_wdata[13:12],
|
||||
up_wdata[9:8],
|
||||
up_wdata[5:4],
|
||||
up_wdata[1:0]};
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge up_clk) begin
|
||||
if (up_rstn == 0) begin
|
||||
up_rack <= 1'b0;
|
||||
up_rdata <= 32'b0;
|
||||
end else begin
|
||||
up_rack <= up_rreq_int_s;
|
||||
if (up_rreq_int_s == 1'b1) begin
|
||||
case (up_raddr[4:0])
|
||||
5'h00: up_rdata <= {31'h0, up_driver_en_n};
|
||||
5'h01: up_rdata <= {31'h0, up_driver_otw_n_s};
|
||||
5'h02: up_rdata <= up_ext_clk_count;
|
||||
5'h08: up_rdata <= {29'h0, up_irq_mask};
|
||||
5'h09: up_rdata <= {29'h0, up_irq_source};
|
||||
5'h0A: up_rdata <= {29'h0, up_irq_pending_s};
|
||||
5'h0B: up_rdata <= {30'h0, up_auto_sequence, up_sequence_en};
|
||||
5'h0C: up_rdata <= up_sequence_offset;
|
||||
5'h0D: up_rdata <= {18'h0, up_auto_seq3,
|
||||
2'h0, up_auto_seq2,
|
||||
2'h0, up_auto_seq1,
|
||||
2'h0, up_auto_seq0};
|
||||
5'h0E: up_rdata <= {18'h0, up_manual_select[7:6],
|
||||
2'h0, up_manual_select[5:4],
|
||||
2'h0, up_manual_select[3:2],
|
||||
2'h0, up_manual_select[1:0]};
|
||||
|
||||
default: up_rdata <= 0;
|
||||
endcase
|
||||
end else begin
|
||||
up_rdata <= 32'd0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign driver_en_n = up_driver_en_n;
|
||||
|
||||
always @(posedge up_clk) begin
|
||||
up_driver_otw_n_int <= up_driver_otw_n_s;
|
||||
end
|
||||
// negative edge of otw_n - system enters into an over temperature state
|
||||
assign up_driver_otw_n_enter_s = ~up_driver_otw_n_s & up_driver_otw_n_int;
|
||||
// positive edge of otw_n - system exits from an over temperature state
|
||||
assign up_driver_otw_n_exit_s = up_driver_otw_n_s & ~up_driver_otw_n_int;
|
||||
|
||||
// Interrupt handling - it can be generated by a generated pulse or an over
|
||||
// temperature warning signal
|
||||
|
||||
assign up_irq_pending_s = ~up_irq_mask & up_irq_source;
|
||||
assign up_irq_trigger_s = {up_driver_otw_n_exit_s, up_driver_otw_n_enter_s, up_pulse_s};
|
||||
assign up_irq_source_clear_s = (up_wreq_int_s == 1'b1 && up_waddr[3:0] == 4'hA) ? up_wdata[2:0] : 3'b000;
|
||||
|
||||
always @(posedge up_clk) begin
|
||||
if (up_rstn == 1'b0) begin
|
||||
irq <= 1'b0;
|
||||
end else begin
|
||||
irq <= |up_irq_pending_s;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge up_clk) begin
|
||||
if (up_rstn == 1'b0) begin
|
||||
up_irq_source <= 3'b000;
|
||||
end else begin
|
||||
up_irq_source <= up_irq_trigger_s | (up_irq_source & ~up_irq_source_clear_s);
|
||||
end
|
||||
end
|
||||
|
||||
// CDC logic
|
||||
|
||||
sync_bits #(
|
||||
.NUM_OF_BITS (1),
|
||||
.ASYNC_CLK (1))
|
||||
i_driver_otw_sync (
|
||||
.in_bits (driver_otw_n),
|
||||
.out_clk (up_clk),
|
||||
.out_resetn (1'b1),
|
||||
.out_bits (up_driver_otw_n_s));
|
||||
|
||||
sync_bits #(
|
||||
.NUM_OF_BITS (1),
|
||||
.ASYNC_CLK (1))
|
||||
i_pulse_sync (
|
||||
.in_bits (pulse),
|
||||
.out_clk (up_clk),
|
||||
.out_resetn (1'b1),
|
||||
.out_bits (up_pulse_s));
|
||||
|
||||
sync_bits #(
|
||||
.NUM_OF_BITS (2),
|
||||
.ASYNC_CLK (1))
|
||||
i_sequence_control_sync (
|
||||
.in_bits ({up_auto_sequence, up_sequence_en}),
|
||||
.out_clk (clk),
|
||||
.out_resetn (1'b1),
|
||||
.out_bits ({auto_sequence, sequence_en}));
|
||||
|
||||
sync_bits #(
|
||||
.NUM_OF_BITS (16),
|
||||
.ASYNC_CLK (1))
|
||||
i_sequencer_sync (
|
||||
.in_bits ({up_auto_seq3,
|
||||
up_auto_seq2,
|
||||
up_auto_seq1,
|
||||
up_auto_seq0,
|
||||
up_manual_select
|
||||
}),
|
||||
.out_clk (clk),
|
||||
.out_resetn (1'b1),
|
||||
.out_bits ({auto_seq3,
|
||||
auto_seq2,
|
||||
auto_seq1,
|
||||
auto_seq0,
|
||||
manual_select
|
||||
}));
|
||||
|
||||
sync_bits #(
|
||||
.NUM_OF_BITS (32),
|
||||
.ASYNC_CLK (1))
|
||||
i_sequence_offset_sync (
|
||||
.in_bits (up_sequence_offset),
|
||||
.out_clk (clk),
|
||||
.out_resetn (1'b1),
|
||||
.out_bits (sequence_offset));
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,982 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>analog.com</spirit:vendor>
|
||||
<spirit:library>user</spirit:library>
|
||||
<spirit:name>axi_laser_driver</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>s_axi</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave>
|
||||
<spirit:memoryMapRef spirit:memoryMapRef="s_axi"/>
|
||||
</spirit:slave>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>AWADDR</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axi_awaddr</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>AWPROT</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axi_awprot</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>AWVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axi_awvalid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>AWREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axi_awready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>WDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axi_wdata</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>WSTRB</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axi_wstrb</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>WVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axi_wvalid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>WREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axi_wready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>BRESP</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axi_bresp</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>BVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axi_bvalid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>BREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axi_bready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>ARADDR</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axi_araddr</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>ARPROT</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axi_arprot</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>ARVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axi_arvalid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>ARREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axi_arready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RDATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axi_rdata</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RRESP</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axi_rresp</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RVALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axi_rvalid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RREADY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axi_rready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>s_axi_aclk</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axi_aclk</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_ACLK.ASSOCIATED_BUSIF">s_axi</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_ACLK.ASSOCIATED_RESET">s_axi_aresetn</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>s_axi_aresetn</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>s_axi_aresetn</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_ARESETN.POLARITY" spirit:choiceRef="choice_list_74b5137e">ACTIVE_LOW</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>ext_clk</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>ext_clk</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
|
||||
</spirit:busInterfaces>
|
||||
<spirit:memoryMaps>
|
||||
<spirit:memoryMap>
|
||||
<spirit:name>s_axi</spirit:name>
|
||||
<spirit:addressBlock>
|
||||
<spirit:name>axi_lite</spirit:name>
|
||||
<spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
|
||||
<spirit:range spirit:format="long">65536</spirit:range>
|
||||
<spirit:width spirit:format="long">0</spirit:width>
|
||||
</spirit:addressBlock>
|
||||
</spirit:memoryMap>
|
||||
</spirit:memoryMaps>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
|
||||
<spirit:displayName>Synthesis</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
|
||||
<spirit:language>Verilog</spirit:language>
|
||||
<spirit:modelName>axi_laser_driver</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagesynthesis_analog_com_user_axi_pulse_gen_1_0__ref_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>74ccffd2</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:language>Verilog</spirit:language>
|
||||
<spirit:modelName>axi_laser_driver</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_analog_com_user_axi_pulse_gen_1_0__ref_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>028e72ab</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_xpgui</spirit:name>
|
||||
<spirit:displayName>UI Layout</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_xpgui_analog_com_user_axi_pulse_gen_1_0__ref_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>ce5d3fb0</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>s_axi_aclk</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>s_axi_aresetn</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>s_axi_awvalid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>s_axi_awaddr</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">15</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>s_axi_awprot</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">2</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
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|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
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|
||||
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|
||||
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|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
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|
||||
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|
||||
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|
||||
<spirit:port>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
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|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
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|
||||
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|
||||
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|
||||
<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
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|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<spirit:port>
|
||||
<spirit:name>s_axi_bvalid</spirit:name>
|
||||
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|
||||
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|
||||
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|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
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|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<spirit:port>
|
||||
<spirit:name>s_axi_bresp</spirit:name>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
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|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
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|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<spirit:port>
|
||||
<spirit:name>s_axi_arvalid</spirit:name>
|
||||
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|
||||
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|
||||
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|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
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|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
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|
||||
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|
||||
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|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
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|
||||
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|
||||
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|
||||
<spirit:port>
|
||||
<spirit:name>s_axi_araddr</spirit:name>
|
||||
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|
||||
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|
||||
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|
||||
<spirit:left spirit:format="long">15</spirit:left>
|
||||
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|
||||
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|
||||
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|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
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|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
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|
||||
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|
||||
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|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
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|
||||
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|
||||
<spirit:port>
|
||||
<spirit:name>s_axi_arprot</spirit:name>
|
||||
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|
||||
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|
||||
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|
||||
<spirit:left spirit:format="long">2</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
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|
||||
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|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
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|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
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|
||||
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|
||||
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|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
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|
||||
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|
||||
<spirit:port>
|
||||
<spirit:name>s_axi_arready</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
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|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
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|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<spirit:port>
|
||||
<spirit:name>s_axi_rvalid</spirit:name>
|
||||
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|
||||
<spirit:direction>out</spirit:direction>
|
||||
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|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
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|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<spirit:port>
|
||||
<spirit:name>s_axi_rresp</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
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|
||||
<spirit:left spirit:format="long">1</spirit:left>
|
||||
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|
||||
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|
||||
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|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
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|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
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|
||||
</spirit:wireTypeDefs>
|
||||
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|
||||
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|
||||
<spirit:port>
|
||||
<spirit:name>s_axi_rdata</spirit:name>
|
||||
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|
||||
<spirit:direction>out</spirit:direction>
|
||||
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|
||||
<spirit:left spirit:format="long">31</spirit:left>
|
||||
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|
||||
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|
||||
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|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
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|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<spirit:port>
|
||||
<spirit:name>s_axi_rready</spirit:name>
|
||||
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|
||||
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|
||||
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|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
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|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
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|
||||
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|
||||
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|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
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|
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|
||||
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|
||||
<spirit:port>
|
||||
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|
||||
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|
||||
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|
||||
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|
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<spirit:wireTypeDef>
|
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<spirit:typeName>std_logic</spirit:typeName>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
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|
||||
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|
||||
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|
||||
<xilinx:portInfo>
|
||||
<xilinx:enablement>
|
||||
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PORT_ENABLEMENT.ext_clk" xilinx:dependency="(spirit:decode(id('MODELPARAM_VALUE.ASYNC_CLK_EN')) = 1)">true</xilinx:isEnabled>
|
||||
</xilinx:enablement>
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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<spirit:wireTypeDef>
|
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<spirit:typeName>std_logic</spirit:typeName>
|
||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
||||
<spirit:port>
|
||||
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|
||||
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|
||||
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|
||||
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|
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<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
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|
||||
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|
||||
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|
||||
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|
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|
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|
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|
||||
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|
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|
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|
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|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
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|
||||
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|
||||
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||||
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|
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|
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|
||||
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|
||||
<spirit:name>driver_dp_reset</spirit:name>
|
||||
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|
||||
<spirit:direction>out</spirit:direction>
|
||||
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|
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<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
<spirit:port>
|
||||
<spirit:name>tia_chsel</spirit:name>
|
||||
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|
||||
<spirit:direction>out</spirit:direction>
|
||||
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|
||||
<spirit:left spirit:format="long">7</spirit:left>
|
||||
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||||
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|
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|
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<spirit:wireTypeDef>
|
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<spirit:typeName>reg</spirit:typeName>
|
||||
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|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
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|
||||
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|
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||||
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|
||||
<spirit:port>
|
||||
<spirit:name>irq</spirit:name>
|
||||
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|
||||
<spirit:direction>out</spirit:direction>
|
||||
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|
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<spirit:wireTypeDef>
|
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<spirit:typeName>std_logic</spirit:typeName>
|
||||
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|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
<spirit:name>ID</spirit:name>
|
||||
<spirit:displayName>Id</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.ID">0</spirit:value>
|
||||
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|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>ASYNC_CLK_EN</spirit:name>
|
||||
<spirit:displayName>Async Clk En</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.ASYNC_CLK_EN">true</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>PULSE_WIDTH</spirit:name>
|
||||
<spirit:displayName>Pulse Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PULSE_WIDTH">7</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>PULSE_PERIOD</spirit:name>
|
||||
<spirit:displayName>Pulse Period</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PULSE_PERIOD">10</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
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|
||||
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|
||||
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|
||||
<spirit:choice>
|
||||
<spirit:name>choice_list_74b5137e</spirit:name>
|
||||
<spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
|
||||
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
|
||||
</spirit:choice>
|
||||
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|
||||
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|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>../axi_pulse_gen/axi_pulse_gen_constr.ttcl</spirit:name>
|
||||
<spirit:userFileType>ttcl</spirit:userFileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../xilinx/common/up_clock_mon_constr.xdc</spirit:name>
|
||||
<spirit:userFileType>xdc</spirit:userFileType>
|
||||
</spirit:file>
|
||||
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<spirit:parameter>
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<spirit:name>ID</spirit:name>
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<spirit:displayName>Id</spirit:displayName>
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<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.ID">0</spirit:value>
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<spirit:name>ASYNC_CLK_EN</spirit:name>
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<spirit:displayName>ASYNC_CLK_EN</spirit:displayName>
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<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ASYNC_CLK_EN">true</spirit:value>
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<spirit:displayName>Pulse width</spirit:displayName>
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<spirit:name>PULSE_PERIOD</spirit:name>
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<spirit:displayName>Pulse period</spirit:displayName>
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<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PULSE_PERIOD" spirit:minimum="0" spirit:maximum="2147483647" spirit:rangeType="long">10</spirit:value>
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<spirit:parameter>
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<spirit:name>Component_Name</spirit:name>
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<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">axi_laser_driver_v1_0</spirit:value>
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</spirit:parameter>
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@@ -0,0 +1,72 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set AXI_Pulse_Generator [ipgui::add_page $IPINST -name "AXI Pulse Generator"]
|
||||
set ASYNC_CLK_EN [ipgui::add_param $IPINST -name "ASYNC_CLK_EN" -parent ${AXI_Pulse_Generator}]
|
||||
set_property tooltip {External clock for the counter} ${ASYNC_CLK_EN}
|
||||
set PULSE_WIDTH [ipgui::add_param $IPINST -name "PULSE_WIDTH" -parent ${AXI_Pulse_Generator}]
|
||||
set_property tooltip {Pulse width of the generated signal. The unit interval is the system or external clock period.} ${PULSE_WIDTH}
|
||||
set PULSE_PERIOD [ipgui::add_param $IPINST -name "PULSE_PERIOD" -parent ${AXI_Pulse_Generator}]
|
||||
set_property tooltip {Period of the generated signal. The unit interval is the system or external clock period.} ${PULSE_PERIOD}
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ASYNC_CLK_EN { PARAM_VALUE.ASYNC_CLK_EN } {
|
||||
# Procedure called to update ASYNC_CLK_EN when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ASYNC_CLK_EN { PARAM_VALUE.ASYNC_CLK_EN } {
|
||||
# Procedure called to validate ASYNC_CLK_EN
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } {
|
||||
# Procedure called to update ID when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } {
|
||||
# Procedure called to validate ID
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.PULSE_PERIOD { PARAM_VALUE.PULSE_PERIOD } {
|
||||
# Procedure called to update PULSE_PERIOD when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.PULSE_PERIOD { PARAM_VALUE.PULSE_PERIOD } {
|
||||
# Procedure called to validate PULSE_PERIOD
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.PULSE_WIDTH { PARAM_VALUE.PULSE_WIDTH } {
|
||||
# Procedure called to update PULSE_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.PULSE_WIDTH { PARAM_VALUE.PULSE_WIDTH } {
|
||||
# Procedure called to validate PULSE_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.ASYNC_CLK_EN { MODELPARAM_VALUE.ASYNC_CLK_EN PARAM_VALUE.ASYNC_CLK_EN } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ASYNC_CLK_EN}] ${MODELPARAM_VALUE.ASYNC_CLK_EN}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.PULSE_WIDTH { MODELPARAM_VALUE.PULSE_WIDTH PARAM_VALUE.PULSE_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.PULSE_WIDTH}] ${MODELPARAM_VALUE.PULSE_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.PULSE_PERIOD { MODELPARAM_VALUE.PULSE_PERIOD PARAM_VALUE.PULSE_PERIOD } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.PULSE_PERIOD}] ${MODELPARAM_VALUE.PULSE_PERIOD}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user