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first commit after restructuring

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josh
2023-04-13 13:33:41 +08:00
commit 3c2cd0ba29
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adi_library/axi_logic_analyzer/axi_logic_analyzer_ip.tcl
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# ip
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
adi_ip_create axi_logic_analyzer
adi_ip_files axi_logic_analyzer [list \
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
"$ad_hdl_dir/library/common/up_xfer_status.v" \
"$ad_hdl_dir/library/common/ad_rst.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
"$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \
"axi_logic_analyzer_constr.xdc" \
"axi_logic_analyzer_reg.v" \
"axi_logic_analyzer_trigger.v" \
"axi_logic_analyzer.v" ]
adi_ip_properties axi_logic_analyzer
ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface clk_out xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::save_core [ipx::current_core]