Archived
first commit after restructuring
This commit is contained in:
@@ -0,0 +1,22 @@
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####################################################################################
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## Copyright 2018(c) Analog Devices, Inc.
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## Auto-generated, do not modify!
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####################################################################################
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LIBRARY_NAME := axi_mc_current_monitor
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GENERIC_DEPS += ../common/ad_rst.v
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GENERIC_DEPS += ../common/up_adc_channel.v
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GENERIC_DEPS += ../common/up_adc_common.v
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GENERIC_DEPS += ../common/up_axi.v
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GENERIC_DEPS += ../common/up_clock_mon.v
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GENERIC_DEPS += ../common/up_xfer_cntrl.v
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GENERIC_DEPS += ../common/up_xfer_status.v
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GENERIC_DEPS += ad7401.v
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GENERIC_DEPS += axi_mc_current_monitor.v
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GENERIC_DEPS += dec256sinc24b.v
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XILINX_DEPS += axi_mc_current_monitor_constr.xdc
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XILINX_DEPS += axi_mc_current_monitor_ip.tcl
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include ../scripts/library.mk
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@@ -0,0 +1,170 @@
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// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
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||||
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||||
`timescale 1 ns / 100 ps //Use a timescale that is best for simulation.
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//------------------------------------------------------------------------------
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//----------- Module Declaration -----------------------------------------------
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//------------------------------------------------------------------------------
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module ad7401
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//----------- Ports Declarations -----------------------------------------------
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(
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//clock and reset signals
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input fpga_clk_i, // system clock
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input adc_clk_i, // up to 20 MHZ clock
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input reset_i, // active high reset signal
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//IP control and data interface
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output reg [15:0] data_o, // data read from the ADC
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output reg data_rd_ready_o, // when set to high the data read from the ADC is available on the data_o bus
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output reg adc_status_o,
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//AD7401 control and data interface
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input adc_mdata_i // AD7401 MDAT pin
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);
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//------------------------------------------------------------------------------
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//----------- Wire Declarations ------------------------------------------------
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//------------------------------------------------------------------------------
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wire data_rdy_s;
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wire [15:0] data_s ;
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//------------------------------------------------------------------------------
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//----------- Registers Declarations -------------------------------------------
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//------------------------------------------------------------------------------
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//State machine
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reg [3:0] present_state;
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reg [3:0] next_state;
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reg data_rdy_s_d1;
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reg data_rdy_s_d2;
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//------------------------------------------------------------------------------
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//----------- Local Parameters -------------------------------------------------
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//------------------------------------------------------------------------------
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//States
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localparam WAIT_DATA_RDY_HIGH_STATE = 4'b0001;
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localparam ACQUIRE_DATA_STATE = 4'b0010;
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localparam TRANSFER_DATA_STATE = 4'b0100;
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localparam WAIT_DATA_RDY_LOW_STATE = 4'b1000;
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//------------------------------------------------------------------------------
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//----------- Assign/Always Blocks ---------------------------------------------
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//------------------------------------------------------------------------------
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// synchronize data on fpga_clki
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always @(posedge fpga_clk_i)
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begin
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data_rdy_s_d1 <= data_rdy_s;
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data_rdy_s_d2 <= data_rdy_s_d1;
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end
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always @(posedge fpga_clk_i)
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begin
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if(reset_i == 1'b1)
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begin
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present_state <= WAIT_DATA_RDY_HIGH_STATE;
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adc_status_o <= 1'b0;
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end
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else
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begin
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present_state <= next_state;
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case (present_state)
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WAIT_DATA_RDY_HIGH_STATE:
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begin
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data_rd_ready_o <= 1'b0;
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end
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ACQUIRE_DATA_STATE: // Acquire data from the filter
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begin
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data_o <= data_s;
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data_rd_ready_o <= 1'b0;
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adc_status_o <= 1'b1;
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end
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TRANSFER_DATA_STATE: // Transfer data to the upper module to write in memory
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begin
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data_rd_ready_o <= 1'b1;
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end
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WAIT_DATA_RDY_LOW_STATE:
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begin
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data_rd_ready_o <= 1'b0;
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end
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endcase
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end
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end
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always @(present_state, data_rdy_s_d2)
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begin
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next_state <= present_state;
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case (present_state)
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WAIT_DATA_RDY_HIGH_STATE:
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begin
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if(data_rdy_s_d2 == 1'b1)
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begin
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next_state <= ACQUIRE_DATA_STATE;
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end
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end
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ACQUIRE_DATA_STATE:
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begin
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next_state <= TRANSFER_DATA_STATE;
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end
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TRANSFER_DATA_STATE:
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begin
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next_state <= WAIT_DATA_RDY_LOW_STATE;
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end
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WAIT_DATA_RDY_LOW_STATE:
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begin
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if(data_rdy_s_d2 == 1'b0)
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begin
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next_state <= WAIT_DATA_RDY_HIGH_STATE;
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end
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end
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default:
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begin
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next_state <= WAIT_DATA_RDY_HIGH_STATE;
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end
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endcase
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end
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dec256sinc24b filter(
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.mclkout_i(adc_clk_i),
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.reset_i(reset_i),
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.mdata_i(adc_mdata_i),
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.data_rdy_o(data_rdy_s),
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.data_o(data_s));
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endmodule
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@@ -0,0 +1,3 @@
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version:1
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6d6f64655f636f756e7465727c42617463684d6f6465:1
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||||
eof:
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+6
@@ -0,0 +1,6 @@
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<?xml version="1.0" encoding="UTF-8"?>
|
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<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<labtools version="1" minor="0"/>
|
||||
@@ -0,0 +1,418 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
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module axi_mc_current_monitor (
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// physical interface
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input adc_ia_dat_i,
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output adc_enable_ia,
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input adc_ib_dat_i,
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output adc_enable_ib,
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input adc_vbus_dat_i,
|
||||
output adc_enable_vbus,
|
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output adc_clk_o,
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|
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input ref_clk,
|
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input adc_clk_i,
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||||
|
||||
output [15:0] ia_o,
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output [15:0] ib_o,
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output [15:0] vbus_o,
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output i_ready_o,
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|
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// axi interface
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input s_axi_aclk,
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input s_axi_aresetn,
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input s_axi_awvalid,
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||||
input [15:0] s_axi_awaddr,
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||||
output s_axi_awready,
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||||
input s_axi_wvalid,
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||||
input [31:0] s_axi_wdata,
|
||||
input [3:0] s_axi_wstrb,
|
||||
output s_axi_wready,
|
||||
output s_axi_bvalid,
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||||
output [1:0] s_axi_bresp,
|
||||
input s_axi_bready,
|
||||
input s_axi_arvalid,
|
||||
input [15:0] s_axi_araddr,
|
||||
output s_axi_arready,
|
||||
output s_axi_rvalid,
|
||||
output [1:0] s_axi_rresp,
|
||||
output [31:0] s_axi_rdata,
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||||
input s_axi_rready,
|
||||
input [ 2:0] s_axi_awprot,
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||||
input [ 2:0] s_axi_arprot
|
||||
|
||||
);
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||||
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||||
//------------------------------------------------------------------------------
|
||||
//----------- Registers Declarations -------------------------------------------
|
||||
//------------------------------------------------------------------------------
|
||||
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||||
reg [31:0] up_rdata = 'd0;
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reg up_wack = 'd0;
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||||
reg up_rack = 'd0;
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||||
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||||
//------------------------------------------------------------------------------
|
||||
//----------- Wires Declarations -----------------------------------------------
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
// internal clocks & resets
|
||||
|
||||
wire adc_rst;
|
||||
wire up_rstn;
|
||||
wire up_clk;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire up_rreq_s;
|
||||
wire up_wreq_s;
|
||||
wire [13:0] up_waddr_s;
|
||||
wire [13:0] up_raddr_s;
|
||||
wire [31:0] up_wdata_s;
|
||||
wire [31:0] up_adc_common_rdata_s;
|
||||
wire up_adc_common_ack_s;
|
||||
wire [31:0] up_rdata_0_s;
|
||||
wire [31:0] up_rdata_1_s;
|
||||
wire [31:0] up_rdata_2_s;
|
||||
wire up_rack_0_s;
|
||||
wire up_rack_1_s;
|
||||
wire up_rack_2_s;
|
||||
wire up_wack_0_s;
|
||||
wire up_wack_1_s;
|
||||
wire up_wack_2_s;
|
||||
|
||||
wire adc_status_a_s;
|
||||
wire [15:0] adc_data_ia_s ;
|
||||
wire data_rd_ready_ia_s;
|
||||
wire adc_status_b_s;
|
||||
wire [15:0] adc_data_ib_s;
|
||||
wire adc_status_vbus_s;
|
||||
wire [15:0] adc_data_vbus_s;
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
//----------- Assign/Always Blocks ---------------------------------------------
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
// signal name changes
|
||||
|
||||
assign up_clk = s_axi_aclk;
|
||||
assign up_rstn = s_axi_aresetn;
|
||||
|
||||
// current outputs
|
||||
|
||||
assign i_ready_o = data_rd_ready_ia_s;
|
||||
|
||||
assign ia_o = adc_data_ia_s ;
|
||||
assign ib_o = adc_data_ib_s ;
|
||||
assign vbus_o = adc_data_vbus_s;
|
||||
|
||||
// adc clock
|
||||
|
||||
assign adc_clk_o = adc_clk_i;
|
||||
|
||||
// processor read interface
|
||||
|
||||
always @(negedge up_rstn or posedge up_clk)
|
||||
begin
|
||||
if(up_rstn == 0)
|
||||
begin
|
||||
up_rdata <= 'd0;
|
||||
up_rack <= 'd0;
|
||||
up_wack <= 'd0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
up_rdata <= up_adc_common_rdata_s | up_rdata_0_s | up_rdata_1_s | up_rdata_2_s ;
|
||||
up_rack <= up_adc_common_rack_s | up_rack_0_s | up_rack_1_s | up_rack_2_s ;
|
||||
up_wack <= up_adc_common_wack_s | up_wack_0_s | up_wack_1_s | up_wack_2_s ;
|
||||
end
|
||||
end
|
||||
|
||||
// adc interfaces
|
||||
|
||||
ad7401 ia_if(
|
||||
.fpga_clk_i(ref_clk),
|
||||
.adc_clk_i(adc_clk_o),
|
||||
.reset_i(adc_rst),
|
||||
.adc_status_o(adc_status_a_s),
|
||||
.data_o(adc_data_ia_s),
|
||||
.data_rd_ready_o(data_rd_ready_ia_s),
|
||||
.adc_mdata_i(adc_ia_dat_i));
|
||||
|
||||
ad7401 ib_if(
|
||||
.fpga_clk_i(ref_clk),
|
||||
.adc_clk_i(adc_clk_o),
|
||||
.reset_i(adc_rst),
|
||||
.adc_status_o(adc_status_b_s),
|
||||
.data_o(adc_data_ib_s),
|
||||
.data_rd_ready_o(),
|
||||
.adc_mdata_i(adc_ib_dat_i));
|
||||
|
||||
ad7401 vbus_if(
|
||||
.fpga_clk_i(ref_clk),
|
||||
.adc_clk_i(adc_clk_o),
|
||||
.reset_i(adc_rst),
|
||||
.adc_status_o(adc_status_vbus_s),
|
||||
.data_o(adc_data_vbus_s),
|
||||
.data_rd_ready_o(),
|
||||
.adc_mdata_i(adc_vbus_dat_i));
|
||||
|
||||
up_adc_channel #(.CHANNEL_ID(0)) i_up_adc_channel_ia(
|
||||
.adc_clk(adc_clk_o),
|
||||
.adc_rst(adc_rst),
|
||||
.adc_enable(adc_enable_ia),
|
||||
.adc_iqcor_enb(),
|
||||
.adc_dcfilt_enb(),
|
||||
.adc_dfmt_se(),
|
||||
.adc_dfmt_type(),
|
||||
.adc_dfmt_enable(),
|
||||
.adc_dcfilt_offset(),
|
||||
.adc_dcfilt_coeff(),
|
||||
.adc_iqcor_coeff_1(),
|
||||
.adc_iqcor_coeff_2(),
|
||||
.adc_pnseq_sel(),
|
||||
.adc_data_sel(),
|
||||
.adc_pn_err(1'b0),
|
||||
.adc_pn_oos(1'b0),
|
||||
.adc_or(1'b0),
|
||||
.up_adc_pn_err(),
|
||||
.up_adc_pn_oos(),
|
||||
.up_adc_or(),
|
||||
.up_usr_datatype_be(),
|
||||
.up_usr_datatype_signed(),
|
||||
.up_usr_datatype_shift(),
|
||||
.up_usr_datatype_total_bits(),
|
||||
.up_usr_datatype_bits(),
|
||||
.up_usr_decimation_m(),
|
||||
.up_usr_decimation_n(),
|
||||
.adc_usr_datatype_be(1'b0),
|
||||
.adc_usr_datatype_signed(1'b1),
|
||||
.adc_usr_datatype_shift(8'd0),
|
||||
.adc_usr_datatype_total_bits(8'd16),
|
||||
.adc_usr_datatype_bits(8'd16),
|
||||
.adc_usr_decimation_m(16'd1),
|
||||
.adc_usr_decimation_n(16'd1),
|
||||
.up_rstn(up_rstn),
|
||||
.up_clk(up_clk),
|
||||
.up_wreq (up_wreq_s),
|
||||
.up_waddr (up_waddr_s),
|
||||
.up_wdata (up_wdata_s),
|
||||
.up_wack (up_wack_0_s),
|
||||
.up_rreq (up_rreq_s),
|
||||
.up_raddr (up_raddr_s),
|
||||
.up_rdata (up_rdata_0_s),
|
||||
.up_rack (up_rack_0_s));
|
||||
|
||||
up_adc_channel #(.CHANNEL_ID(1)) i_up_adc_channel_ib(
|
||||
.adc_clk(adc_clk_o),
|
||||
.adc_rst(adc_rst),
|
||||
.adc_enable(adc_enable_ib),
|
||||
.adc_iqcor_enb(),
|
||||
.adc_dcfilt_enb(),
|
||||
.adc_dfmt_se(),
|
||||
.adc_dfmt_type(),
|
||||
.adc_dfmt_enable(),
|
||||
.adc_dcfilt_offset(),
|
||||
.adc_dcfilt_coeff(),
|
||||
.adc_iqcor_coeff_1(),
|
||||
.adc_iqcor_coeff_2(),
|
||||
.adc_pnseq_sel(),
|
||||
.adc_data_sel(),
|
||||
.adc_pn_err(1'b0),
|
||||
.adc_pn_oos(1'b0),
|
||||
.adc_or(1'b0),
|
||||
.up_adc_pn_err(),
|
||||
.up_adc_pn_oos(),
|
||||
.up_adc_or(),
|
||||
.up_usr_datatype_be(),
|
||||
.up_usr_datatype_signed(),
|
||||
.up_usr_datatype_shift(),
|
||||
.up_usr_datatype_total_bits(),
|
||||
.up_usr_datatype_bits(),
|
||||
.up_usr_decimation_m(),
|
||||
.up_usr_decimation_n(),
|
||||
.adc_usr_datatype_be(1'b0),
|
||||
.adc_usr_datatype_signed(1'b1),
|
||||
.adc_usr_datatype_shift(8'd0),
|
||||
.adc_usr_datatype_total_bits(8'd16),
|
||||
.adc_usr_datatype_bits(8'd16),
|
||||
.adc_usr_decimation_m(16'd1),
|
||||
.adc_usr_decimation_n(16'd1),
|
||||
.up_rstn(up_rstn),
|
||||
.up_clk(up_clk),
|
||||
.up_wreq (up_wreq_s),
|
||||
.up_waddr (up_waddr_s),
|
||||
.up_wdata (up_wdata_s),
|
||||
.up_wack (up_wack_1_s),
|
||||
.up_rreq (up_rreq_s),
|
||||
.up_raddr (up_raddr_s),
|
||||
.up_rdata (up_rdata_1_s),
|
||||
.up_rack (up_rack_1_s));
|
||||
|
||||
up_adc_channel #(.CHANNEL_ID(2)) i_up_adc_channel_vbus(
|
||||
.adc_clk(adc_clk_o),
|
||||
.adc_rst(adc_rst),
|
||||
.adc_enable(adc_enable_vbus),
|
||||
.adc_iqcor_enb(),
|
||||
.adc_dcfilt_enb(),
|
||||
.adc_dfmt_se(),
|
||||
.adc_dfmt_type(),
|
||||
.adc_dfmt_enable(),
|
||||
.adc_dcfilt_offset(),
|
||||
.adc_dcfilt_coeff(),
|
||||
.adc_iqcor_coeff_1(),
|
||||
.adc_iqcor_coeff_2(),
|
||||
.adc_pnseq_sel(),
|
||||
.adc_data_sel(),
|
||||
.adc_pn_err(1'b0),
|
||||
.adc_pn_oos(1'b0),
|
||||
.adc_or(1'b0),
|
||||
.up_adc_pn_err(),
|
||||
.up_adc_pn_oos(),
|
||||
.up_adc_or(),
|
||||
.up_usr_datatype_be(),
|
||||
.up_usr_datatype_signed(),
|
||||
.up_usr_datatype_shift(),
|
||||
.up_usr_datatype_total_bits(),
|
||||
.up_usr_datatype_bits(),
|
||||
.up_usr_decimation_m(),
|
||||
.up_usr_decimation_n(),
|
||||
.adc_usr_datatype_be(1'b0),
|
||||
.adc_usr_datatype_signed(1'b1),
|
||||
.adc_usr_datatype_shift(8'd0),
|
||||
.adc_usr_datatype_total_bits(8'd16),
|
||||
.adc_usr_datatype_bits(8'd16),
|
||||
.adc_usr_decimation_m(16'd1),
|
||||
.adc_usr_decimation_n(16'd1),
|
||||
.up_rstn(up_rstn),
|
||||
.up_clk(up_clk),
|
||||
.up_wreq (up_wreq_s),
|
||||
.up_waddr (up_waddr_s),
|
||||
.up_wdata (up_wdata_s),
|
||||
.up_wack (up_wack_2_s),
|
||||
.up_rreq (up_rreq_s),
|
||||
.up_raddr (up_raddr_s),
|
||||
.up_rdata (up_rdata_2_s),
|
||||
.up_rack (up_rack_2_s));
|
||||
|
||||
// common processor control
|
||||
|
||||
up_adc_common i_up_adc_common(
|
||||
.mmcm_rst(),
|
||||
.adc_clk(adc_clk_o),
|
||||
.adc_rst(adc_rst),
|
||||
.adc_r1_mode(),
|
||||
.adc_ddr_edgesel(),
|
||||
.adc_pin_mode(),
|
||||
.adc_status(1'b1),
|
||||
.adc_sync_status(1'b1),
|
||||
.adc_status_ovf(1'b0),
|
||||
.adc_clk_ratio(32'd1),
|
||||
.adc_start_code(),
|
||||
.adc_sref_sync(),
|
||||
.adc_sync(),
|
||||
|
||||
.up_pps_rcounter (32'b0),
|
||||
.up_pps_status (1'b0),
|
||||
|
||||
.up_adc_ce(),
|
||||
.up_status_pn_err(1'b0),
|
||||
.up_status_pn_oos(1'b0),
|
||||
.up_status_or(1'b0),
|
||||
|
||||
.up_drp_sel(),
|
||||
.up_drp_wr(),
|
||||
.up_drp_addr(),
|
||||
.up_drp_wdata(),
|
||||
.up_drp_rdata(16'd0),
|
||||
.up_drp_ready(1'b0),
|
||||
.up_drp_locked(1'b0),
|
||||
|
||||
.up_usr_chanmax_out(),
|
||||
.up_usr_chanmax_in(8'd3),
|
||||
.up_adc_gpio_in(32'h0),
|
||||
.up_adc_gpio_out(),
|
||||
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq_s),
|
||||
.up_waddr (up_waddr_s),
|
||||
.up_wdata (up_wdata_s),
|
||||
.up_wack (up_adc_common_wack_s),
|
||||
.up_rreq (up_rreq_s),
|
||||
.up_raddr (up_raddr_s),
|
||||
.up_rdata (up_adc_common_rdata_s),
|
||||
.up_rack (up_adc_common_rack_s));
|
||||
|
||||
// up bus interface
|
||||
|
||||
up_axi i_up_axi(
|
||||
.up_rstn(up_rstn),
|
||||
.up_clk(up_clk),
|
||||
.up_axi_awvalid(s_axi_awvalid),
|
||||
.up_axi_awaddr(s_axi_awaddr),
|
||||
.up_axi_awready(s_axi_awready),
|
||||
.up_axi_wvalid(s_axi_wvalid),
|
||||
.up_axi_wdata(s_axi_wdata),
|
||||
.up_axi_wstrb(s_axi_wstrb),
|
||||
.up_axi_wready(s_axi_wready),
|
||||
.up_axi_bvalid(s_axi_bvalid),
|
||||
.up_axi_bresp(s_axi_bresp),
|
||||
.up_axi_bready(s_axi_bready),
|
||||
.up_axi_arvalid(s_axi_arvalid),
|
||||
.up_axi_araddr(s_axi_araddr),
|
||||
.up_axi_arready(s_axi_arready),
|
||||
.up_axi_rvalid(s_axi_rvalid),
|
||||
.up_axi_rresp(s_axi_rresp),
|
||||
.up_axi_rdata(s_axi_rdata),
|
||||
.up_axi_rready(s_axi_rready),
|
||||
.up_wreq (up_wreq_s),
|
||||
.up_waddr (up_waddr_s),
|
||||
.up_wdata (up_wdata_s),
|
||||
.up_wack (up_wack),
|
||||
.up_rreq (up_rreq_s),
|
||||
.up_raddr (up_raddr_s),
|
||||
.up_rdata (up_rdata),
|
||||
.up_rack (up_rack));
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
@@ -0,0 +1,445 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Version="7" Minor="40" Path="/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_mc_current_monitor/axi_mc_current_monitor.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="e78dd1e9209b4dff819cf5223b2a1030"/>
|
||||
<Option Name="Part" Val="xc7vx485tffg1157-1"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="BoardPart" Val=""/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../library"/>
|
||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../../ghdl/library"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="DSAVendor" Val="xilinx"/>
|
||||
<Option Name="DSANumComputeUnits" Val="60"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="0"/>
|
||||
<Option Name="WTModelSimExportSim" Val="0"/>
|
||||
<Option Name="WTQuestaExportSim" Val="0"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="0"/>
|
||||
<Option Name="WTRivieraExportSim" Val="0"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
<Option Name="SimTypes" Val="bfm"/>
|
||||
<Option Name="SimTypes" Val="tlm"/>
|
||||
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="31">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/ad7401.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../common/ad_rst.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/dec256sinc24b.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../common/up_adc_channel.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../common/up_adc_common.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../common/up_axi.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../common/up_clock_mon.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../common/up_xfer_cntrl.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../common/up_xfer_status.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/axi_mc_current_monitor.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/component.xml">
|
||||
<FileInfo SFType="IPXACT"/>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="axi_mc_current_monitor"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<File Path="$PPRDIR/axi_mc_current_monitor_constr.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="IES">
|
||||
<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Xcelium">
|
||||
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="VCS">
|
||||
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="10">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Vivado 12-1790"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="1"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="Evaluation"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="features"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="should"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="NOT"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="be"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="used"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="in"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="production"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="systems."/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Place 30-73"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="10"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="axi_spi"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val=""/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="11"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1343"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="2"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1306"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="3"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="ERROR"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1276"/>
|
||||
<MsgAttr Name="Severity" Val="CRITICAL WARNING"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="4"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-3656"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="5"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-4623"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="6"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-459"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="7"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Synth 8-3331"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="8"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Designutils 20-3303"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="9"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="HDPYFinalizeIO"/>
|
||||
</MsgRule>
|
||||
<Board/>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
<BootPmcSettings Version="1" Minor="0">
|
||||
<Parameters>
|
||||
<Parameter Name="PMC_CDO.ATTRS.LOADADDR" Value="" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_FB_CLK" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_FREQ" Value="300" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_BUS_WIDTH" Value="x1" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_DATA_MODE" Value="Single" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_FREQ" Value="200" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_SLOT_TYPE" Value="SD 2.0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_FREQ" Value="200" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_SLOT_TYPE" Value="SD 2.0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSPI_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSPI_FREQ" Value="300" Type="string"/>
|
||||
<Parameter Name="BOOT.USB_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SMAP_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SMAP_DATA_WIDTH" Value="32 Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSC_FREQ" Value="33.333" Type="string"/>
|
||||
<Parameter Name="BOOT.SECONDARY.PCIE_ENABLE" Value="0" Type="string"/>
|
||||
</Parameters>
|
||||
</BootPmcSettings>
|
||||
</Project>
|
||||
@@ -0,0 +1,7 @@
|
||||
create_generated_clock -name [current_instance]/ia_clk -source [get_ports adc_clk_i] \
|
||||
-divide_by 256 [get_pins ia_if/filter/word_count_reg[7]/Q]
|
||||
create_generated_clock -name [current_instance]/ib_clk -source [get_ports adc_clk_i] \
|
||||
-divide_by 256 [get_pins ib_if/filter/word_count_reg[7]/Q]
|
||||
create_generated_clock -name [current_instance]/vbus_clk -source [get_ports adc_clk_i] \
|
||||
-divide_by 256 [get_pins vbus_if/filter/word_count_reg[7]/Q]
|
||||
|
||||
@@ -0,0 +1,28 @@
|
||||
# ip
|
||||
|
||||
source ../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
|
||||
adi_ip_create axi_mc_current_monitor
|
||||
adi_ip_files axi_mc_current_monitor [list \
|
||||
"$ad_hdl_dir/library/common/ad_rst.v" \
|
||||
"$ad_hdl_dir/library/common/up_axi.v" \
|
||||
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
|
||||
"$ad_hdl_dir/library/common/up_xfer_status.v" \
|
||||
"$ad_hdl_dir/library/common/up_clock_mon.v" \
|
||||
"$ad_hdl_dir/library/common/up_adc_common.v" \
|
||||
"$ad_hdl_dir/library/common/up_adc_channel.v" \
|
||||
"dec256sinc24b.v" \
|
||||
"ad7401.v" \
|
||||
"axi_mc_current_monitor_constr.xdc" \
|
||||
"axi_mc_current_monitor.v" ]
|
||||
|
||||
adi_ip_properties axi_mc_current_monitor
|
||||
|
||||
ipx::infer_bus_interface ref_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
ipx::infer_bus_interface adc_clk_i xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
ipx::infer_bus_interface adc_clk_o xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
|
||||
ipx::save_core [ipx::current_core]
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,175 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1 ns / 100 ps //Use a timescale that is best for simulation.
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
//----------- Module Declaration -----------------------------------------------
|
||||
//------------------------------------------------------------------------------
|
||||
module dec256sinc24b
|
||||
(
|
||||
input reset_i,
|
||||
input mclkout_i,
|
||||
input mdata_i,
|
||||
|
||||
output data_rdy_o, // signals when new data is available
|
||||
output reg [15:0] data_o // outputs filtered data
|
||||
);
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
//----------- Registers Declarations -------------------------------------------
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
reg [23:0] ip_data1;
|
||||
reg [23:0] acc1;
|
||||
reg [23:0] acc2;
|
||||
reg [23:0] acc3;
|
||||
reg [23:0] acc3_d1;
|
||||
reg [23:0] acc3_d2;
|
||||
reg [23:0] diff1;
|
||||
reg [23:0] diff2;
|
||||
reg [23:0] diff3;
|
||||
reg [23:0] diff1_d;
|
||||
reg [23:0] diff2_d;
|
||||
reg [7:0] word_count;
|
||||
reg word_clk;
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
//----------- Assign/Always Blocks ---------------------------------------------
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
assign data_rdy_o = word_clk;
|
||||
|
||||
/* Perform the Sinc ACTION */
|
||||
always @(mdata_i)
|
||||
begin
|
||||
if(mdata_i == 0)
|
||||
begin
|
||||
ip_data1 <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
ip_data1 <= 1;
|
||||
end
|
||||
end
|
||||
|
||||
/*ACCUMULATOR (INTEGRATOR)
|
||||
* Perform the accumulation (IIR) at the speed of the modulator.
|
||||
* mclkout_i = modulators conversion bit rate */
|
||||
always @(negedge mclkout_i or posedge reset_i)
|
||||
begin
|
||||
if( reset_i == 1'b1 )
|
||||
begin
|
||||
/*initialize acc registers on reset*/
|
||||
acc1 <= 0;
|
||||
acc2 <= 0;
|
||||
acc3 <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
/*perform accumulation process*/
|
||||
acc1 <= acc1 + ip_data1;
|
||||
acc2 <= acc2 + acc1;
|
||||
acc3 <= acc3 + acc2;
|
||||
end
|
||||
end
|
||||
|
||||
/*DECIMATION STAGE (MCLKOUT_I/ WORD_CLK) */
|
||||
always@(posedge mclkout_i or posedge reset_i )
|
||||
begin
|
||||
if(reset_i == 1'b1)
|
||||
begin
|
||||
word_count <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
word_count <= word_count + 1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(word_count)
|
||||
begin
|
||||
word_clk <= word_count[7];
|
||||
end
|
||||
|
||||
/*DIFFERENTIATOR (including decimation stage)
|
||||
* Perform the differentiation stage (FIR) at a lower speed.
|
||||
WORD_CLK = output word rate */
|
||||
always @(posedge word_clk or posedge reset_i)
|
||||
begin
|
||||
if(reset_i == 1'b1)
|
||||
begin
|
||||
acc3_d2 <= 0;
|
||||
diff1_d <= 0;
|
||||
diff2_d <= 0;
|
||||
diff1 <= 0;
|
||||
diff2 <= 0;
|
||||
diff3 <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
diff1 <= acc3 - acc3_d2;
|
||||
diff2 <= diff1 - diff1_d;
|
||||
diff3 <= diff2 - diff2_d;
|
||||
acc3_d2 <= acc3;
|
||||
diff1_d <= diff1;
|
||||
diff2_d <= diff2;
|
||||
end
|
||||
end
|
||||
|
||||
/* Clock the Sinc output into an output register
|
||||
Clocking Sinc Output into an Output Register
|
||||
WORD_CLK = output word rate */
|
||||
always @(posedge word_clk)
|
||||
begin
|
||||
data_o[15] <= diff3[23];
|
||||
data_o[14] <= diff3[22];
|
||||
data_o[13] <= diff3[21];
|
||||
data_o[12] <= diff3[20];
|
||||
data_o[11] <= diff3[19];
|
||||
data_o[10] <= diff3[18];
|
||||
data_o[9] <= diff3[17];
|
||||
data_o[8] <= diff3[16];
|
||||
data_o[7] <= diff3[15];
|
||||
data_o[6] <= diff3[14];
|
||||
data_o[5] <= diff3[13];
|
||||
data_o[4] <= diff3[12];
|
||||
data_o[3] <= diff3[11];
|
||||
data_o[2] <= diff3[10];
|
||||
data_o[1] <= diff3[9];
|
||||
data_o[0] <= diff3[8];
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,10 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
ipgui::add_page $IPINST -name "Page 0"
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user