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first commit after restructuring

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josh
2023-04-13 13:33:41 +08:00
commit 3c2cd0ba29
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adi_library/jesd204/ad_ip_jesd204_tpl_dac/.timestamp_intel
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adi_library/jesd204/ad_ip_jesd204_tpl_dac/AD9135.qprs
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<?xml version="1.0" encoding="UTF-8"?>
<ip><presets version="17.1">
<preset name="AD9135 Mode 08" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9135">
<parameter name="PART" value="AD9135" />
<parameter name="NUM_CHANNELS" value="1" />
<parameter name="NUM_LANES" value="4" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="2" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9135 Mode 09" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9135">
<parameter name="PART" value="AD9135" />
<parameter name="NUM_CHANNELS" value="1" />
<parameter name="NUM_LANES" value="2" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9135 Mode 10" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9135">
<parameter name="PART" value="AD9135" />
<parameter name="NUM_CHANNELS" value="1" />
<parameter name="NUM_LANES" value="1" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9135 Mode 11" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9135">
<parameter name="PART" value="AD9135" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="8" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="2" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9135 Mode 12" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9135">
<parameter name="PART" value="AD9135" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="4" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9135 Mode 13" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9135">
<parameter name="PART" value="AD9135" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="2" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
</presets></ip>
adi_library/jesd204/ad_ip_jesd204_tpl_dac/AD9136.qprs
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<?xml version="1.0" encoding="UTF-8"?>
<ip><presets version="17.1">
<preset name="AD9136 Mode 08" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9136">
<parameter name="PART" value="AD9136" />
<parameter name="NUM_CHANNELS" value="1" />
<parameter name="NUM_LANES" value="4" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="2" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9136 Mode 09" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9136">
<parameter name="PART" value="AD9136" />
<parameter name="NUM_CHANNELS" value="1" />
<parameter name="NUM_LANES" value="2" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9136 Mode 10" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9136">
<parameter name="PART" value="AD9136" />
<parameter name="NUM_CHANNELS" value="1" />
<parameter name="NUM_LANES" value="1" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9136 Mode 11" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9136">
<parameter name="PART" value="AD9136" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="8" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="2" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9136 Mode 12" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9136">
<parameter name="PART" value="AD9136" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="4" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9136 Mode 13" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9136">
<parameter name="PART" value="AD9136" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="2" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
</presets></ip>
adi_library/jesd204/ad_ip_jesd204_tpl_dac/AD9144.qprs
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<?xml version="1.0" encoding="UTF-8"?>
<ip><presets version="17.1">
<preset name="AD9144 Mode 00" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9144">
<parameter name="PART" value="AD9144" />
<parameter name="NUM_CHANNELS" value="4" />
<parameter name="NUM_LANES" value="8" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9144 Mode 01" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9144">
<parameter name="PART" value="AD9144" />
<parameter name="NUM_CHANNELS" value="4" />
<parameter name="NUM_LANES" value="8" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="2" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9144 Mode 02" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9144">
<parameter name="PART" value="AD9144" />
<parameter name="NUM_CHANNELS" value="4" />
<parameter name="NUM_LANES" value="4" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9144 Mode 03" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9144">
<parameter name="PART" value="AD9144" />
<parameter name="NUM_CHANNELS" value="4" />
<parameter name="NUM_LANES" value="2" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9144 Mode 04" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9144">
<parameter name="PART" value="AD9144" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="4" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9144 Mode 05" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9144">
<parameter name="PART" value="AD9144" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="4" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="2" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9144 Mode 06" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9144">
<parameter name="PART" value="AD9144" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="2" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9144 Mode 07" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9144">
<parameter name="PART" value="AD9144" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="1" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9144 Mode 09" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9144">
<parameter name="PART" value="AD9144" />
<parameter name="NUM_CHANNELS" value="1" />
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<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9144 Mode 10" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9144">
<parameter name="PART" value="AD9144" />
<parameter name="NUM_CHANNELS" value="1" />
<parameter name="NUM_LANES" value="1" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
</presets></ip>
adi_library/jesd204/ad_ip_jesd204_tpl_dac/AD9152.qprs
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<?xml version="1.0" encoding="UTF-8"?>
<ip><presets version="17.1">
<preset name="AD9152 Mode 04" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9152">
<parameter name="PART" value="AD9152" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="4" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9152 Mode 05" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9152">
<parameter name="PART" value="AD9152" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="4" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="2" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9152 Mode 06" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9152">
<parameter name="PART" value="AD9152" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="2" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9152 Mode 07" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9152">
<parameter name="PART" value="AD9152" />
<parameter name="NUM_CHANNELS" value="2" />
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<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
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<preset name="AD9152 Mode 09" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9152">
<parameter name="PART" value="AD9152" />
<parameter name="NUM_CHANNELS" value="1" />
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<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
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<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
</presets></ip>
adi_library/jesd204/ad_ip_jesd204_tpl_dac/AD9154.qprs
+93
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<?xml version="1.0" encoding="UTF-8"?>
<ip><presets version="17.1">
<preset name="AD9154 Mode 00" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9154">
<parameter name="PART" value="AD9154" />
<parameter name="NUM_CHANNELS" value="4" />
<parameter name="NUM_LANES" value="8" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9154 Mode 01" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9154">
<parameter name="PART" value="AD9154" />
<parameter name="NUM_CHANNELS" value="4" />
<parameter name="NUM_LANES" value="8" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="2" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9154 Mode 02" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9154">
<parameter name="PART" value="AD9154" />
<parameter name="NUM_CHANNELS" value="4" />
<parameter name="NUM_LANES" value="4" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9154 Mode 03" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9154">
<parameter name="PART" value="AD9154" />
<parameter name="NUM_CHANNELS" value="4" />
<parameter name="NUM_LANES" value="2" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9154 Mode 04" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9154">
<parameter name="PART" value="AD9154" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="4" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
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<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="2" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9154 Mode 06" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9154">
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<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="2" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9154 Mode 07" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9154">
<parameter name="PART" value="AD9154" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="1" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9154 Mode 09" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9154">
<parameter name="PART" value="AD9154" />
<parameter name="NUM_CHANNELS" value="1" />
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<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9154 Mode 10" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9154">
<parameter name="PART" value="AD9154" />
<parameter name="NUM_CHANNELS" value="1" />
<parameter name="NUM_LANES" value="1" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
</presets></ip>
adi_library/jesd204/ad_ip_jesd204_tpl_dac/AD9171.qprs
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<?xml version="1.0" encoding="UTF-8"?>
<ip><presets version="17.1">
<preset name="AD9171 Mode 00" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9171">
<parameter name="PART" value="AD9171" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="1" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9171 Mode 03" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9171">
<parameter name="PART" value="AD9171" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="2" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9171 Mode 05" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9171">
<parameter name="PART" value="AD9171" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="1" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="12" />
<parameter name="BITS_PER_SAMPLE" value="12" />
</preset>
</presets></ip>
adi_library/jesd204/ad_ip_jesd204_tpl_dac/AD9172.qprs
+156
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<?xml version="1.0" encoding="UTF-8"?>
<ip><presets version="17.1">
<preset name="AD9172 Mode 00" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9172">
<parameter name="PART" value="AD9172" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="1" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9172 Mode 01" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9172">
<parameter name="PART" value="AD9172" />
<parameter name="NUM_CHANNELS" value="4" />
<parameter name="NUM_LANES" value="2" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9172 Mode 02" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9172">
<parameter name="PART" value="AD9172" />
<parameter name="NUM_CHANNELS" value="6" />
<parameter name="NUM_LANES" value="3" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9172 Mode 03" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9172">
<parameter name="PART" value="AD9172" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="2" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9172 Mode 04" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9172">
<parameter name="PART" value="AD9172" />
<parameter name="NUM_CHANNELS" value="4" />
<parameter name="NUM_LANES" value="4" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9172 Mode 05" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9172">
<parameter name="PART" value="AD9172" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="1" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="12" />
<parameter name="BITS_PER_SAMPLE" value="12" />
</preset>
<preset name="AD9172 Mode 06" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9172">
<parameter name="PART" value="AD9172" />
<parameter name="NUM_CHANNELS" value="4" />
<parameter name="NUM_LANES" value="2" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="12" />
<parameter name="BITS_PER_SAMPLE" value="12" />
</preset>
<preset name="AD9172 Mode 07" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9172">
<parameter name="PART" value="AD9172" />
<parameter name="NUM_CHANNELS" value="4" />
<parameter name="NUM_LANES" value="1" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9172 Mode 08" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9172">
<parameter name="PART" value="AD9172" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="4" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9172 Mode 09" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9172">
<parameter name="PART" value="AD9172" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="4" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="2" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9172 Mode 10" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9172">
<parameter name="PART" value="AD9172" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="8" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="2" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9172 Mode 11" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9172">
<parameter name="PART" value="AD9172" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="8" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="4" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9172 Mode 12" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9172">
<parameter name="PART" value="AD9172" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="8" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="8" />
<parameter name="CONVERTER_RESOLUTION" value="12" />
<parameter name="BITS_PER_SAMPLE" value="12" />
</preset>
<preset name="AD9172 Mode 18" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9172">
<parameter name="PART" value="AD9172" />
<parameter name="NUM_CHANNELS" value="1" />
<parameter name="NUM_LANES" value="4" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="2" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9172 Mode 19" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9172">
<parameter name="PART" value="AD9172" />
<parameter name="NUM_CHANNELS" value="1" />
<parameter name="NUM_LANES" value="4" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="4" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9172 Mode 20" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9172">
<parameter name="PART" value="AD9172" />
<parameter name="NUM_CHANNELS" value="1" />
<parameter name="NUM_LANES" value="8" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="4" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9172 Mode 21" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9172">
<parameter name="PART" value="AD9172" />
<parameter name="NUM_CHANNELS" value="1" />
<parameter name="NUM_LANES" value="8" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="8" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
</presets></ip>
adi_library/jesd204/ad_ip_jesd204_tpl_dac/AD9173.qprs
+138
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<?xml version="1.0" encoding="UTF-8"?>
<ip><presets version="17.1">
<preset name="AD9173 Mode 00" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9173">
<parameter name="PART" value="AD9173" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="1" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9173 Mode 01" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9173">
<parameter name="PART" value="AD9173" />
<parameter name="NUM_CHANNELS" value="4" />
<parameter name="NUM_LANES" value="2" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9173 Mode 02" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9173">
<parameter name="PART" value="AD9173" />
<parameter name="NUM_CHANNELS" value="6" />
<parameter name="NUM_LANES" value="3" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9173 Mode 03" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9173">
<parameter name="PART" value="AD9173" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="2" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9173 Mode 04" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9173">
<parameter name="PART" value="AD9173" />
<parameter name="NUM_CHANNELS" value="4" />
<parameter name="NUM_LANES" value="4" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9173 Mode 05" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9173">
<parameter name="PART" value="AD9173" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="1" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="12" />
<parameter name="BITS_PER_SAMPLE" value="12" />
</preset>
<preset name="AD9173 Mode 06" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9173">
<parameter name="PART" value="AD9173" />
<parameter name="NUM_CHANNELS" value="4" />
<parameter name="NUM_LANES" value="2" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="12" />
<parameter name="BITS_PER_SAMPLE" value="12" />
</preset>
<preset name="AD9173 Mode 07" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9173">
<parameter name="PART" value="AD9173" />
<parameter name="NUM_CHANNELS" value="4" />
<parameter name="NUM_LANES" value="1" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9173 Mode 08" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9173">
<parameter name="PART" value="AD9173" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="4" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9173 Mode 09" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9173">
<parameter name="PART" value="AD9173" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="4" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="2" />
<parameter name="CONVERTER_RESOLUTION" value="16" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9173 Mode 13" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9173">
<parameter name="PART" value="AD9173" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="4" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="CONVERTER_RESOLUTION" value="11" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9173 Mode 14" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9173">
<parameter name="PART" value="AD9173" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="4" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="2" />
<parameter name="CONVERTER_RESOLUTION" value="11" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9173 Mode 15" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9173">
<parameter name="PART" value="AD9173" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="8" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="2" />
<parameter name="CONVERTER_RESOLUTION" value="11" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9173 Mode 16" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9173">
<parameter name="PART" value="AD9173" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="8" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="1" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="4" />
<parameter name="CONVERTER_RESOLUTION" value="11" />
<parameter name="BITS_PER_SAMPLE" value="16" />
</preset>
<preset name="AD9173 Mode 17" kind="ad_ip_jesd204_tpl_dac" version="All" description="AD9173">
<parameter name="PART" value="AD9173" />
<parameter name="NUM_CHANNELS" value="2" />
<parameter name="NUM_LANES" value="8" />
<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />
<parameter name="SAMPLES_PER_FRAME_MANUAL" value="8" />
<parameter name="CONVERTER_RESOLUTION" value="11" />
<parameter name="BITS_PER_SAMPLE" value="12" />
</preset>
</presets></ip>
adi_library/jesd204/ad_ip_jesd204_tpl_dac/Makefile
+45
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####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
LIBRARY_NAME := ad_ip_jesd204_tpl_dac
GENERIC_DEPS += ../../common/ad_dds.v
GENERIC_DEPS += ../../common/ad_dds_1.v
GENERIC_DEPS += ../../common/ad_dds_2.v
GENERIC_DEPS += ../../common/ad_dds_cordic_pipe.v
GENERIC_DEPS += ../../common/ad_dds_sine.v
GENERIC_DEPS += ../../common/ad_dds_sine_cordic.v
GENERIC_DEPS += ../../common/ad_iqcor.v
GENERIC_DEPS += ../../common/ad_perfect_shuffle.v
GENERIC_DEPS += ../../common/ad_rst.v
GENERIC_DEPS += ../../common/up_axi.v
GENERIC_DEPS += ../../common/up_clock_mon.v
GENERIC_DEPS += ../../common/up_dac_channel.v
GENERIC_DEPS += ../../common/up_dac_common.v
GENERIC_DEPS += ../../common/up_xfer_cntrl.v
GENERIC_DEPS += ../../common/up_xfer_status.v
GENERIC_DEPS += ../ad_ip_jesd204_tpl_common/up_tpl_common.v
GENERIC_DEPS += ad_ip_jesd204_tpl_dac.v
GENERIC_DEPS += ad_ip_jesd204_tpl_dac_channel.v
GENERIC_DEPS += ad_ip_jesd204_tpl_dac_core.v
GENERIC_DEPS += ad_ip_jesd204_tpl_dac_framer.v
GENERIC_DEPS += ad_ip_jesd204_tpl_dac_pn.v
GENERIC_DEPS += ad_ip_jesd204_tpl_dac_regmap.v
XILINX_DEPS += ../../xilinx/common/ad_mul.v
XILINX_DEPS += ../../xilinx/common/ad_rst_constr.xdc
XILINX_DEPS += ../../xilinx/common/up_clock_mon_constr.xdc
XILINX_DEPS += ../../xilinx/common/up_xfer_cntrl_constr.xdc
XILINX_DEPS += ../../xilinx/common/up_xfer_status_constr.xdc
XILINX_DEPS += ad_ip_jesd204_tpl_dac_ip.tcl
INTEL_DEPS += ../../intel/common/ad_mul.v
INTEL_DEPS += ../../intel/common/up_clock_mon_constr.sdc
INTEL_DEPS += ../../intel/common/up_rst_constr.sdc
INTEL_DEPS += ../../intel/common/up_xfer_cntrl_constr.sdc
INTEL_DEPS += ../../intel/common/up_xfer_status_constr.sdc
INTEL_DEPS += ad_ip_jesd204_tpl_dac_hw.tcl
include ../../scripts/library.mk
adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac.cache/wt/project.wpc
+3
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@@ -0,0 +1,3 @@
version:1
6d6f64655f636f756e7465727c42617463684d6f6465:1
eof:
adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac.hw/ad_ip_jesd204_tpl_dac.lpr
+6
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@@ -0,0 +1,6 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
<labtools version="1" minor="0"/>
adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac.v
+238
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@@ -0,0 +1,238 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2018 (c) Analog Devices, Inc. All rights reserved.
//
// Each core or library found in this collection may have its own licensing terms.
// The user should keep this in in mind while exploring these cores.
//
// Redistribution and use in source and binary forms,
// with or without modification of this file, are permitted under the terms of either
// (at the option of the user):
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory, or at:
// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
//
// OR
//
// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_ip_jesd204_tpl_dac #(
parameter ID = 0,
parameter FPGA_TECHNOLOGY = 0,
parameter FPGA_FAMILY = 0,
parameter SPEED_GRADE = 0,
parameter DEV_PACKAGE = 0,
parameter NUM_LANES = 4,
parameter NUM_CHANNELS = 2,
parameter SAMPLES_PER_FRAME = 1,
parameter CONVERTER_RESOLUTION = 16,
parameter BITS_PER_SAMPLE = 16,
parameter OCTETS_PER_BEAT = 4,
parameter DDS_TYPE = 1,
parameter DDS_CORDIC_DW = 16,
parameter DDS_CORDIC_PHASE_DW = 16,
parameter DATAPATH_DISABLE = 0,
parameter IQCORRECTION_DISABLE = 1,
parameter EXT_SYNC = 0
) (
// jesd interface
// link_clk is (line-rate/40)
input link_clk,
output link_valid,
input link_ready,
output [NUM_LANES*8*OCTETS_PER_BEAT-1:0] link_data,
// dma interface
output [NUM_CHANNELS-1:0] enable,
output [NUM_CHANNELS-1:0] dac_valid,
input [NUM_LANES*8*OCTETS_PER_BEAT-1:0] dac_ddata,
input dac_dunf,
// external sync, should be on the link_clk clock domain
input dac_sync_in,
// axi interface
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
output s_axi_awready,
input [12:0] s_axi_awaddr,
input [2:0] s_axi_awprot,
input s_axi_wvalid,
output s_axi_wready,
input [31:0] s_axi_wdata,
input [3:0] s_axi_wstrb,
output s_axi_bvalid,
input s_axi_bready,
output [1:0] s_axi_bresp,
input s_axi_arvalid,
output s_axi_arready,
input [12:0] s_axi_araddr,
input [2:0] s_axi_arprot,
output s_axi_rvalid,
input s_axi_rready,
output [31:0] s_axi_rdata,
output [1:0] s_axi_rresp
);
localparam DATA_PATH_WIDTH = OCTETS_PER_BEAT * 8 * NUM_LANES / NUM_CHANNELS / BITS_PER_SAMPLE;
localparam LINK_DATA_WIDTH = NUM_LANES * OCTETS_PER_BEAT * 8;
localparam DMA_DATA_WIDTH = BITS_PER_SAMPLE * DATA_PATH_WIDTH * NUM_CHANNELS;
localparam BYTES_PER_FRAME = (NUM_CHANNELS * BITS_PER_SAMPLE * SAMPLES_PER_FRAME) / ( 8 * NUM_LANES);
// internal signals
wire dac_sync;
wire dac_sync_in_status;
wire dac_dds_format;
wire [NUM_CHANNELS*16-1:0] dac_dds_scale_0_s;
wire [NUM_CHANNELS*16-1:0] dac_dds_init_0_s;
wire [NUM_CHANNELS*16-1:0] dac_dds_incr_0_s;
wire [NUM_CHANNELS*16-1:0] dac_dds_scale_1_s;
wire [NUM_CHANNELS*16-1:0] dac_dds_init_1_s;
wire [NUM_CHANNELS*16-1:0] dac_dds_incr_1_s;
wire [NUM_CHANNELS*16-1:0] dac_pat_data_0_s;
wire [NUM_CHANNELS*16-1:0] dac_pat_data_1_s;
wire [NUM_CHANNELS*4-1:0] dac_data_sel_s;
wire [NUM_CHANNELS-1:0] dac_iqcor_enb;
wire [NUM_CHANNELS*16-1:0] dac_iqcor_coeff_1;
wire [NUM_CHANNELS*16-1:0] dac_iqcor_coeff_2;
// regmap
ad_ip_jesd204_tpl_dac_regmap #(
.ID (ID),
.DATAPATH_DISABLE (DATAPATH_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),
.DEV_PACKAGE (DEV_PACKAGE),
.NUM_CHANNELS (NUM_CHANNELS),
.DATA_PATH_WIDTH (DATA_PATH_WIDTH),
.NUM_PROFILES(1)
) i_regmap (
.s_axi_aclk (s_axi_aclk),
.s_axi_aresetn (s_axi_aresetn),
.s_axi_awvalid (s_axi_awvalid),
.s_axi_awready (s_axi_awready),
.s_axi_awaddr (s_axi_awaddr),
.s_axi_awprot (s_axi_awprot),
.s_axi_wvalid (s_axi_wvalid),
.s_axi_wready (s_axi_wready),
.s_axi_wdata (s_axi_wdata),
.s_axi_wstrb (s_axi_wstrb),
.s_axi_bvalid (s_axi_bvalid),
.s_axi_bready (s_axi_bready),
.s_axi_bresp (s_axi_bresp),
.s_axi_arvalid (s_axi_arvalid),
.s_axi_arready (s_axi_arready),
.s_axi_araddr (s_axi_araddr),
.s_axi_arprot (s_axi_arprot),
.s_axi_rvalid (s_axi_rvalid),
.s_axi_rresp (s_axi_rresp),
.s_axi_rdata (s_axi_rdata),
.s_axi_rready (s_axi_rready),
.link_clk (link_clk),
.dac_dunf (dac_dunf),
.dac_sync (dac_sync),
.dac_sync_in_status (dac_sync_in_status),
.dac_dds_format (dac_dds_format),
.dac_dds_scale_0 (dac_dds_scale_0_s),
.dac_dds_init_0 (dac_dds_init_0_s),
.dac_dds_incr_0 (dac_dds_incr_0_s),
.dac_dds_scale_1 (dac_dds_scale_1_s),
.dac_dds_init_1 (dac_dds_init_1_s),
.dac_dds_incr_1 (dac_dds_incr_1_s),
.dac_pat_data_0 (dac_pat_data_0_s),
.dac_pat_data_1 (dac_pat_data_1_s),
.dac_data_sel (dac_data_sel_s),
.dac_iqcor_enb (dac_iqcor_enb),
.dac_iqcor_coeff_1 (dac_iqcor_coeff_1),
.dac_iqcor_coeff_2 (dac_iqcor_coeff_2),
.jesd_m (NUM_CHANNELS),
.jesd_l (NUM_LANES),
.jesd_s (SAMPLES_PER_FRAME),
.jesd_f (BYTES_PER_FRAME),
.jesd_n (CONVERTER_RESOLUTION),
.jesd_np (BITS_PER_SAMPLE),
.up_profile_sel ()
);
// core
ad_ip_jesd204_tpl_dac_core #(
.DATAPATH_DISABLE (DATAPATH_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE),
.NUM_LANES (NUM_LANES),
.NUM_CHANNELS (NUM_CHANNELS),
.BITS_PER_SAMPLE (BITS_PER_SAMPLE),
.CONVERTER_RESOLUTION (CONVERTER_RESOLUTION),
.SAMPLES_PER_FRAME (SAMPLES_PER_FRAME),
.OCTETS_PER_BEAT (OCTETS_PER_BEAT),
.DATA_PATH_WIDTH (DATA_PATH_WIDTH),
.LINK_DATA_WIDTH (LINK_DATA_WIDTH),
.DMA_DATA_WIDTH (DMA_DATA_WIDTH),
.DDS_TYPE (DDS_TYPE),
.DDS_CORDIC_DW (DDS_CORDIC_DW),
.DDS_CORDIC_PHASE_DW (DDS_CORDIC_PHASE_DW),
.EXT_SYNC (EXT_SYNC)
) i_core (
.clk (link_clk),
.link_valid (link_valid),
.link_ready (link_ready),
.link_data (link_data),
.enable (enable),
.dac_valid (dac_valid),
.dac_ddata (dac_ddata),
.dac_sync (dac_sync),
.dac_sync_in_status (dac_sync_in_status),
.dac_sync_in (dac_sync_in),
.dac_dds_format (dac_dds_format),
.dac_dds_scale_0 (dac_dds_scale_0_s),
.dac_dds_init_0 (dac_dds_init_0_s),
.dac_dds_incr_0 (dac_dds_incr_0_s),
.dac_dds_scale_1 (dac_dds_scale_1_s),
.dac_dds_init_1 (dac_dds_init_1_s),
.dac_dds_incr_1 (dac_dds_incr_1_s),
.dac_pat_data_0 (dac_pat_data_0_s),
.dac_pat_data_1 (dac_pat_data_1_s),
.dac_data_sel (dac_data_sel_s),
.dac_iqcor_enb (dac_iqcor_enb),
.dac_iqcor_coeff_1 (dac_iqcor_coeff_1),
.dac_iqcor_coeff_2 (dac_iqcor_coeff_2)
);
endmodule
adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac.xpr
+561
View File
@@ -0,0 +1,561 @@
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<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
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<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="IP_Flow 19-459"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="7"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="Synth 8-3331"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="8"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="Designutils 20-3303"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="9"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
<MsgAttr Name="StringsToMatch" Val="HDPYFinalizeIO"/>
</MsgRule>
<Board/>
<DashboardSummary Version="1" Minor="0">
<Dashboards>
<Dashboard Name="default_dashboard">
<Gadgets>
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
</Gadget>
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
</Gadget>
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
</Gadget>
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
</Gadget>
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
</Gadget>
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
</Gadget>
</Gadgets>
</Dashboard>
<CurrentDashboard>default_dashboard</CurrentDashboard>
</Dashboards>
</DashboardSummary>
<BootPmcSettings Version="1" Minor="0">
<Parameters>
<Parameter Name="PMC_CDO.ATTRS.LOADADDR" Value="" Type="string"/>
<Parameter Name="BOOT.PMC.QSPI_ENABLE" Value="0" Type="string"/>
<Parameter Name="BOOT.PMC.QSPI_FB_CLK" Value="0" Type="string"/>
<Parameter Name="BOOT.PMC.QSPI_FREQ" Value="300" Type="string"/>
<Parameter Name="BOOT.PMC.QSPI_BUS_WIDTH" Value="x1" Type="string"/>
<Parameter Name="BOOT.PMC.QSPI_DATA_MODE" Value="Single" Type="string"/>
<Parameter Name="BOOT.PMC.SD0_ENABLE" Value="0" Type="string"/>
<Parameter Name="BOOT.PMC.SD0_FREQ" Value="200" Type="string"/>
<Parameter Name="BOOT.PMC.SD0_SLOT_TYPE" Value="SD 2.0" Type="string"/>
<Parameter Name="BOOT.PMC.SD0_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
<Parameter Name="BOOT.PMC.SD1_ENABLE" Value="0" Type="string"/>
<Parameter Name="BOOT.PMC.SD1_FREQ" Value="200" Type="string"/>
<Parameter Name="BOOT.PMC.SD1_SLOT_TYPE" Value="SD 2.0" Type="string"/>
<Parameter Name="BOOT.PMC.SD1_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
<Parameter Name="BOOT.PMC.OSPI_ENABLE" Value="0" Type="string"/>
<Parameter Name="BOOT.PMC.OSPI_FREQ" Value="300" Type="string"/>
<Parameter Name="BOOT.USB_ENABLE" Value="0" Type="string"/>
<Parameter Name="BOOT.PMC.SMAP_ENABLE" Value="0" Type="string"/>
<Parameter Name="BOOT.PMC.SMAP_DATA_WIDTH" Value="32 Bit" Type="string"/>
<Parameter Name="BOOT.PMC.OSC_FREQ" Value="33.333" Type="string"/>
<Parameter Name="BOOT.SECONDARY.PCIE_ENABLE" Value="0" Type="string"/>
</Parameters>
</BootPmcSettings>
</Project>
adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_channel.v
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// ***************************************************************************
// ***************************************************************************
// Copyright 2018 (c) Analog Devices, Inc. All rights reserved.
//
// Each core or library found in this collection may have its own licensing terms.
// The user should keep this in in mind while exploring these cores.
//
// Redistribution and use in source and binary forms,
// with or without modification of this file, are permitted under the terms of either
// (at the option of the user):
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory, or at:
// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
//
// OR
//
// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_ip_jesd204_tpl_dac_channel #(
parameter DATAPATH_DISABLE = 0,
parameter IQCORRECTION_DISABLE = 1,
parameter DATA_PATH_WIDTH = 4,
parameter CONVERTER_RESOLUTION = 16,
parameter BITS_PER_SAMPLE = 16,
parameter DDS_TYPE = 1,
parameter DDS_CORDIC_DW = 16,
parameter DDS_CORDIC_PHASE_DW = 16,
parameter Q_OR_I_N = 0
) (
// dac interface
input clk,
input [DATA_PATH_WIDTH*BITS_PER_SAMPLE-1:0] dma_data,
output reg [DATA_PATH_WIDTH*CONVERTER_RESOLUTION-1:0] dac_data = 'h00,
// PN data
input [DATA_PATH_WIDTH*CONVERTER_RESOLUTION-1:0] pn7_data,
input [DATA_PATH_WIDTH*CONVERTER_RESOLUTION-1:0] pn15_data,
// Configuration
input dac_data_sync,
input dac_dds_format,
input [3:0] dac_data_sel,
input [15:0] dac_dds_scale_0,
input [15:0] dac_dds_init_0,
input [15:0] dac_dds_incr_0,
input [15:0] dac_dds_scale_1,
input [15:0] dac_dds_init_1,
input [15:0] dac_dds_incr_1,
input [15:0] dac_pat_data_0,
input [15:0] dac_pat_data_1,
input dac_iqcor_enb,
input [15:0] dac_iqcor_coeff_1,
input [15:0] dac_iqcor_coeff_2,
input [DATA_PATH_WIDTH*BITS_PER_SAMPLE-1:0] dac_iqcor_data_in,
output reg dac_enable = 1'b0
);
localparam CR = CONVERTER_RESOLUTION;
localparam CHANNEL_DATA_WIDTH = DATA_PATH_WIDTH * CR;
// internal signals
wire [CHANNEL_DATA_WIDTH-1:0] dac_dds_data_s;
wire [CHANNEL_DATA_WIDTH-1:0] dac_dma_data_s;
wire [CHANNEL_DATA_WIDTH-1:0] dac_pat_data_s;
wire [CHANNEL_DATA_WIDTH-1:0] dac_iqcor_data_s;
generate
if (DATA_PATH_WIDTH > 1) begin
assign dac_pat_data_s = {DATA_PATH_WIDTH/2{dac_pat_data_1[0+:CR],dac_pat_data_0[0+:CR]}};
end else begin
reg dac_pat_data_sel = 1'b0;
always @(posedge clk) begin
if (dac_data_sync == 1'b1) begin
dac_pat_data_sel <= 1'b0;
end else begin
dac_pat_data_sel <= ~dac_pat_data_sel;
end
end
assign dac_pat_data_s = dac_pat_data_sel == 1'b0 ?
dac_pat_data_0[0+:CR] : dac_pat_data_1[0+:CR];
end
genvar i;
/* Data is expected to be LSB aligned, drop unused MSBs */
for (i = 0; i < DATA_PATH_WIDTH; i = i + 1) begin: g_dac_dma_data
assign dac_dma_data_s[CR*i+:CR] = dma_data[BITS_PER_SAMPLE*i+:CR];
end
endgenerate
ad_iqcor #(
.Q_OR_I_N (Q_OR_I_N),
.DISABLE (IQCORRECTION_DISABLE),
.CR (CR),
.DPW (DATA_PATH_WIDTH)
) i_ad_iqcor (
.clk (clk),
.valid (1'b1),
.data_in (dac_dma_data_s),
.data_iq (dac_iqcor_data_in),
.valid_out (),
.data_out (dac_iqcor_data_s),
.iqcor_enable (dac_iqcor_enb),
.iqcor_coeff_1 (dac_iqcor_coeff_1),
.iqcor_coeff_2 (dac_iqcor_coeff_2));
// dac data select
always @(posedge clk) begin
dac_enable <= (dac_data_sel == 4'h2) ? 1'b1 : 1'b0;
case (dac_data_sel)
4'h7: dac_data <= pn15_data;
4'h6: dac_data <= pn7_data;
4'h5: dac_data <= ~pn15_data;
4'h4: dac_data <= ~pn7_data;
4'h3: dac_data <= 'h00;
4'h2: dac_data <= dac_iqcor_data_s;
4'h1: dac_data <= dac_pat_data_s;
default: dac_data <= dac_dds_data_s;
endcase
end
// dds
ad_dds #(
.DISABLE (DATAPATH_DISABLE),
.DDS_DW (CONVERTER_RESOLUTION),
.PHASE_DW (16),
.DDS_TYPE (DDS_TYPE),
.CORDIC_DW (DDS_CORDIC_DW),
.CORDIC_PHASE_DW (DDS_CORDIC_PHASE_DW),
.CLK_RATIO (DATA_PATH_WIDTH))
i_dds (
.clk (clk),
.dac_dds_format (dac_dds_format),
.dac_data_sync (dac_data_sync),
.dac_valid (1'b1),
.tone_1_scale (dac_dds_scale_0),
.tone_2_scale (dac_dds_scale_1),
.tone_1_init_offset (dac_dds_init_0),
.tone_2_init_offset (dac_dds_init_1),
.tone_1_freq_word (dac_dds_incr_0),
.tone_2_freq_word (dac_dds_incr_1),
.dac_dds_data (dac_dds_data_s));
endmodule
adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_core.v
+199
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// ***************************************************************************
// ***************************************************************************
// Copyright 2018 (c) Analog Devices, Inc. All rights reserved.
//
// Each core or library found in this collection may have its own licensing terms.
// The user should keep this in in mind while exploring these cores.
//
// Redistribution and use in source and binary forms,
// with or without modification of this file, are permitted under the terms of either
// (at the option of the user):
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory, or at:
// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
//
// OR
//
// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_ip_jesd204_tpl_dac_core #(
parameter DATAPATH_DISABLE = 0,
parameter IQCORRECTION_DISABLE = 1,
parameter NUM_LANES = 1,
parameter NUM_CHANNELS = 1,
parameter BITS_PER_SAMPLE = 16,
parameter CONVERTER_RESOLUTION = 16,
parameter SAMPLES_PER_FRAME = 1,
parameter OCTETS_PER_BEAT = 4,
parameter DATA_PATH_WIDTH = 4,
parameter LINK_DATA_WIDTH = NUM_LANES * OCTETS_PER_BEAT * 8,
parameter DMA_DATA_WIDTH = DATA_PATH_WIDTH * BITS_PER_SAMPLE * NUM_CHANNELS,
parameter DDS_TYPE = 1,
parameter DDS_CORDIC_DW = 16,
parameter DDS_CORDIC_PHASE_DW = 16,
parameter EXT_SYNC = 0
) (
// dac interface
input clk,
output link_valid,
input link_ready,
output [LINK_DATA_WIDTH-1:0] link_data,
// dma interface
output [NUM_CHANNELS-1:0] dac_valid,
input [DMA_DATA_WIDTH-1:0] dac_ddata,
// Configuration interface
input dac_sync,
input dac_sync_in,
output dac_sync_in_status,
input dac_dds_format,
input [NUM_CHANNELS*4-1:0] dac_data_sel,
input [NUM_CHANNELS*16-1:0] dac_dds_scale_0,
input [NUM_CHANNELS*16-1:0] dac_dds_init_0,
input [NUM_CHANNELS*16-1:0] dac_dds_incr_0,
input [NUM_CHANNELS*16-1:0] dac_dds_scale_1,
input [NUM_CHANNELS*16-1:0] dac_dds_init_1,
input [NUM_CHANNELS*16-1:0] dac_dds_incr_1,
input [NUM_CHANNELS*16-1:0] dac_pat_data_0,
input [NUM_CHANNELS*16-1:0] dac_pat_data_1,
input [NUM_CHANNELS-1:0] dac_iqcor_enb,
input [NUM_CHANNELS*16-1:0] dac_iqcor_coeff_1,
input [NUM_CHANNELS*16-1:0] dac_iqcor_coeff_2,
output [NUM_CHANNELS-1:0] enable
);
localparam DAC_CDW = CONVERTER_RESOLUTION * DATA_PATH_WIDTH;
localparam DAC_DATA_WIDTH = DAC_CDW * NUM_CHANNELS;
localparam DMA_CDW = DATA_PATH_WIDTH * BITS_PER_SAMPLE;
wire [DAC_DATA_WIDTH-1:0] dac_data_s;
wire [DAC_CDW-1:0] pn7_data;
wire [DAC_CDW-1:0] pn15_data;
reg dac_sync_in_d1 ='d0;
reg dac_sync_in_d2 ='d0;
reg dac_sync_in_arm ='d0;
reg dac_sync_d1 = 'd0;
assign link_valid = 1'b1;
assign dac_sync_in_status = dac_sync_in_arm;
always @(posedge clk) begin
dac_sync_d1 <= dac_sync;
dac_sync_in_d1 <= dac_sync_in;
dac_sync_in_d2 <= dac_sync_in_d1;
if ((~dac_sync_d1&dac_sync) == 1'b1) begin
dac_sync_in_arm <= ~dac_sync_in_arm;
end else if ((~dac_sync_in_d2&dac_sync_in_d1) == 1'b1) begin
dac_sync_in_arm <= 1'b0;
end else if (EXT_SYNC == 1'b0) begin
dac_sync_in_arm <= 1'b0;
end
end
// device interface
ad_ip_jesd204_tpl_dac_framer #(
.NUM_LANES (NUM_LANES),
.NUM_CHANNELS (NUM_CHANNELS),
.BITS_PER_SAMPLE (BITS_PER_SAMPLE),
.CONVERTER_RESOLUTION (CONVERTER_RESOLUTION),
.SAMPLES_PER_FRAME (SAMPLES_PER_FRAME),
.OCTETS_PER_BEAT (OCTETS_PER_BEAT),
.LINK_DATA_WIDTH (LINK_DATA_WIDTH),
.DAC_DATA_WIDTH (DAC_DATA_WIDTH)
) i_framer (
.link_data (link_data),
.dac_data (dac_data_s)
);
// PN generator
ad_ip_jesd204_tpl_dac_pn #(
.DATA_PATH_WIDTH (DATA_PATH_WIDTH),
.CONVERTER_RESOLUTION (CONVERTER_RESOLUTION)
) i_pn_gen (
.clk (clk),
.reset (dac_sync_in_arm),
.pn7_data (pn7_data),
.pn15_data (pn15_data)
);
// dac valid
assign dac_valid = {NUM_CHANNELS{~dac_sync_in_arm}};
generate
genvar i;
for (i = 0; i < NUM_CHANNELS; i = i + 1) begin: g_channel
// Find the pair of the current channel for I/Q channels
// Assuming even channels are I, odd channels are Q
// Assuming channel count is even other case do not pair channels
localparam IQ_PAIR_CH_INDEX = (NUM_CHANNELS%2) ? i :
(i%2) ? i-1 : i+1;
ad_ip_jesd204_tpl_dac_channel #(
.DATA_PATH_WIDTH (DATA_PATH_WIDTH),
.CONVERTER_RESOLUTION (CONVERTER_RESOLUTION),
.DATAPATH_DISABLE (DATAPATH_DISABLE),
.BITS_PER_SAMPLE (BITS_PER_SAMPLE),
.DDS_TYPE (DDS_TYPE),
.DDS_CORDIC_DW (DDS_CORDIC_DW),
.DDS_CORDIC_PHASE_DW (DDS_CORDIC_PHASE_DW),
.IQCORRECTION_DISABLE(IQCORRECTION_DISABLE),
.Q_OR_I_N(i%2)
) i_channel (
.clk (clk),
.dac_enable (enable[i]),
.dac_data (dac_data_s[DAC_CDW*i+:DAC_CDW]),
.dma_data (dac_ddata[DMA_CDW*i+:DMA_CDW]),
.pn7_data (pn7_data),
.pn15_data (pn15_data),
.dac_data_sync (dac_sync_in_arm),
.dac_dds_format (dac_dds_format),
.dac_data_sel (dac_data_sel[4*i+:4]),
.dac_dds_scale_0 (dac_dds_scale_0[16*i+:16]),
.dac_dds_init_0 (dac_dds_init_0[16*i+:16]),
.dac_dds_incr_0 (dac_dds_incr_0[16*i+:16]),
.dac_dds_scale_1 (dac_dds_scale_1[16*i+:16]),
.dac_dds_init_1 (dac_dds_init_1[16*i+:16]),
.dac_dds_incr_1 (dac_dds_incr_1[16*i+:16]),
.dac_pat_data_0 (dac_pat_data_0[16*i+:16]),
.dac_pat_data_1 (dac_pat_data_1[16*i+:16]),
.dac_iqcor_enb (dac_iqcor_enb[i]),
.dac_iqcor_coeff_1 (dac_iqcor_coeff_1[16*i+:16]),
.dac_iqcor_coeff_2 (dac_iqcor_coeff_2[16*i+:16]),
.dac_iqcor_data_in (dac_ddata[DMA_CDW*IQ_PAIR_CH_INDEX+:DMA_CDW])
);
end
endgenerate
endmodule
adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_framer.v
+145
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// ***************************************************************************
// ***************************************************************************
// Copyright 2018 (c) Analog Devices, Inc. All rights reserved.
//
// Each core or library found in this collection may have its own licensing terms.
// The user should keep this in in mind while exploring these cores.
//
// Redistribution and use in source and binary forms,
// with or without modification of this file, are permitted under the terms of either
// (at the option of the user):
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory, or at:
// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
//
// OR
//
// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_ip_jesd204_tpl_dac_framer #(
parameter NUM_LANES = 8,
parameter NUM_CHANNELS = 4,
parameter BITS_PER_SAMPLE = 16,
parameter CONVERTER_RESOLUTION = 16,
parameter SAMPLES_PER_FRAME = 2,
parameter OCTETS_PER_BEAT = 4,
parameter LINK_DATA_WIDTH = OCTETS_PER_BEAT * 8 * NUM_LANES,
parameter DAC_DATA_WIDTH = LINK_DATA_WIDTH * CONVERTER_RESOLUTION / BITS_PER_SAMPLE
) (
// jesd interface
output [LINK_DATA_WIDTH-1:0] link_data,
// dac interface
input [DAC_DATA_WIDTH-1:0] dac_data
);
/*
* The framer module takes sample data and maps it onto the format that the
* JESD204 link expects for the specified framer configuration.
*
* The input sample data in dac_data is expected to be grouped by converter.
* The first sample is in the LSBs. Each sample has CONVERTER_RESOLUTION bits.
*
* Or in other words the data in dac_data is expected to have the following
* layout.
*
* MSB LSB
* [ MmSn, ..., MmS1, MnS0, ..., M1Sn, ... M1S1, M1S0, M0Sn, ... M0S1, M0S0 ]
*
* Where MjSi refers to the i-th sample of the j-th converter. With m being
* the number of converters and n the number of samples per converter per
* beat.
*
* In the default configuration the framer module processes 4 octets per beat.
* This means it can support settings with either 1, 2 or 4 octets per frame
* (F). Depending on the octets per frame the frames per beat will either be
* 4, 2 or 1 respectively. For other settings of OCTETS_PER_BEAT similar
* reasoning applies.
*
* The number of samples per frame (S) and the number of frames processed per
* beat gives the number of samples per converter per beat. This is either
* S * 4 (for F=1), S * 2 (for F=2) or S (for F=1).
*
* The framer module does not have a parameter for the octets per frame (F)
* since it can be derived from all other parameters given the following
* relationship: F = (M * N' * S) / (L * 8)
*
*
* Mapping in performed in two steps. First samples are grouped into frames,
* as there might be more than one frame pert beat. In the second step the
* frames are distributed onto the lanes.
*
* In the JESD204 standard samples and octets are ordered MSB first, this
* means earlier data is in the MSBs. This core on the other hand expects
* samples and octets to be LSB first ordered. This means earlier data is in
* the LSBs. To accommodate this two additional steps are required to order
* data from LSB to MSB before the framing process and back from MSB to LSB
* after it.
*
* The data itself that is contained within the samples and octets is LSB
* ordered in either case. That means lower bits are in the LSBs.
*/
localparam BITS_PER_CHANNEL_PER_FRAME = BITS_PER_SAMPLE * SAMPLES_PER_FRAME;
localparam BITS_PER_LANE_PER_FRAME = BITS_PER_CHANNEL_PER_FRAME *
NUM_CHANNELS / NUM_LANES;
localparam FRAMES_PER_BEAT = OCTETS_PER_BEAT * 8 / BITS_PER_LANE_PER_FRAME;
localparam SAMPLES_PER_BEAT = DAC_DATA_WIDTH / CONVERTER_RESOLUTION;
localparam TAIL_BITS = BITS_PER_SAMPLE - CONVERTER_RESOLUTION;
wire [LINK_DATA_WIDTH-1:0] link_data_msb_s;
wire [LINK_DATA_WIDTH-1:0] frame_data_s;
wire [LINK_DATA_WIDTH-1:0] dac_data_msb;
generate
genvar i;
genvar j;
/* Reorder samples MSB first and insert tail bits */
for (i = 0; i < SAMPLES_PER_BEAT; i = i + 1) begin: g_dac_data_msb
localparam src_w = CONVERTER_RESOLUTION;
localparam dst_w = BITS_PER_SAMPLE;
localparam src_lsb = i * src_w;
localparam dst_msb = LINK_DATA_WIDTH - 1 - i * dst_w;
assign dac_data_msb[dst_msb-:src_w] = dac_data[src_lsb+:src_w];
if (TAIL_BITS > 0) begin
assign dac_data_msb[dst_msb-src_w-:TAIL_BITS] = {TAIL_BITS{1'b0}};
end
end
/* Slice channel and pack it into frames */
ad_perfect_shuffle #(
.NUM_GROUPS (NUM_CHANNELS),
.WORDS_PER_GROUP (FRAMES_PER_BEAT),
.WORD_WIDTH (BITS_PER_CHANNEL_PER_FRAME)
) i_channels_to_frames (
.data_in (dac_data_msb),
.data_out (frame_data_s)
);
/* Slice frame and pack it into lanes */
ad_perfect_shuffle #(
.NUM_GROUPS (FRAMES_PER_BEAT),
.WORDS_PER_GROUP (NUM_LANES),
.WORD_WIDTH (BITS_PER_LANE_PER_FRAME)
) i_frames_to_lanes (
.data_in (frame_data_s),
.data_out (link_data_msb_s)
);
/* Reorder octets LSB first */
for (i = 0; i < LINK_DATA_WIDTH; i = i + 8) begin: g_link_data
assign link_data[i+:8] = link_data_msb_s[LINK_DATA_WIDTH-1-i-:8];
end
endgenerate
endmodule
adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_hw.tcl
+509
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@@ -0,0 +1,509 @@
# ***************************************************************************
# ***************************************************************************
# Copyright 2018 (c) Analog Devices, Inc. All rights reserved.
#
# Each core or library found in this collection may have its own licensing terms.
# The user should keep this in in mind while exploring these cores.
#
# Redistribution and use in source and binary forms,
# with or without modification of this file, are permitted under the terms of either
# (at the option of the user):
#
# 1. The GNU General Public License version 2 as published by the
# Free Software Foundation, which can be found in the top level directory, or at:
# https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
#
# OR
#
# 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
# https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
#
# ***************************************************************************
# ***************************************************************************
package require qsys
source ../../scripts/adi_env.tcl
source ../../scripts/adi_ip_intel.tcl
ad_ip_create ad_ip_jesd204_tpl_dac "JESD204 Transport Layer for DACs" p_ad_ip_jesd204_tpl_dac_elab
set_module_property VALIDATION_CALLBACK p_ad_ip_jesd204_tpl_dac_validate
ad_ip_files ad_ip_jesd204_tpl_dac [list \
$ad_hdl_dir/library/intel/common/ad_mul.v \
$ad_hdl_dir/library/common/ad_dds_sine.v \
$ad_hdl_dir/library/common/ad_dds_cordic_pipe.v \
$ad_hdl_dir/library/common/ad_dds_sine_cordic.v \
$ad_hdl_dir/library/common/ad_dds_2.v \
$ad_hdl_dir/library/common/ad_dds_1.v \
$ad_hdl_dir/library/common/ad_dds.v \
$ad_hdl_dir/library/common/ad_iqcor.v \
$ad_hdl_dir/library/common/ad_perfect_shuffle.v \
$ad_hdl_dir/library/common/ad_rst.v \
$ad_hdl_dir/library/common/up_axi.v \
$ad_hdl_dir/library/common/up_xfer_cntrl.v \
$ad_hdl_dir/library/common/up_xfer_status.v \
$ad_hdl_dir/library/common/up_clock_mon.v \
$ad_hdl_dir/library/common/up_dac_common.v \
$ad_hdl_dir/library/common/up_dac_channel.v \
\
$ad_hdl_dir/library/intel/common/up_xfer_cntrl_constr.sdc \
$ad_hdl_dir/library/intel/common/up_xfer_status_constr.sdc \
$ad_hdl_dir/library/intel/common/up_clock_mon_constr.sdc \
$ad_hdl_dir/library/intel/common/up_rst_constr.sdc \
\
ad_ip_jesd204_tpl_dac.v \
ad_ip_jesd204_tpl_dac_channel.v \
ad_ip_jesd204_tpl_dac_core.v \
ad_ip_jesd204_tpl_dac_framer.v \
ad_ip_jesd204_tpl_dac_pn.v \
ad_ip_jesd204_tpl_dac_regmap.v \
../ad_ip_jesd204_tpl_common/up_tpl_common.v \
]
# parameters
set group "General Configuration"
ad_ip_parameter ID INTEGER 0 true [list \
DISPLAY_NAME "Core ID" \
GROUP $group \
]
set group "JESD204 Framer Configuration"
ad_ip_parameter PART STRING "Generic" false [list \
DISPLAY_NAME "Part" \
ALLOWED_RANGES { \
"Generic" \
"AD9135" \
"AD9136" \
"AD9144" \
"AD9152" \
"AD9154" \
"AD9161" \
"AD9162" \
"AD9163" \
"AD9164" \
"AD9171" \
"AD9172" \
"AD9173" \
} \
GROUP $group \
]
ad_ip_parameter NUM_LANES INTEGER 1 true [list \
DISPLAY_NAME "Number of Lanes (L)" \
DISPLAY_UNITS "lanes" \
ALLOWED_RANGES {1 2 3 4 8 16} \
GROUP $group \
]
ad_ip_parameter NUM_CHANNELS INTEGER 1 true [list \
DISPLAY_NAME "Number of Converters (M)" \
DISPLAY_UNITS "converters" \
ALLOWED_RANGES {1 2 4 6 8 16 32 64} \
GROUP $group \
]
ad_ip_parameter BITS_PER_SAMPLE INTEGER 16 false [list \
DISPLAY_NAME "Bits per Sample (N')" \
ALLOWED_RANGES {8 12 16} \
UNITS bits \
GROUP $group \
]
ad_ip_parameter CONVERTER_RESOLUTION INTEGER 16 true [list \
DISPLAY_NAME "Converter Resolution (N)" \
ALLOWED_RANGES {8 11 12 16} \
UNITS bits \
GROUP $group \
]
ad_ip_parameter ENABLE_SAMPLES_PER_FRAME_MANUAL BOOLEAN 0 false [list \
DISPLAY_NAME "Manual Samples per Frame" \
GROUP $group \
]
ad_ip_parameter SAMPLES_PER_FRAME INTEGER 1 true [list \
DISPLAY_NAME "Samples per Frame (S)" \
DISPLAY_UNITS "samples" \
ALLOWED_RANGES {1 2 3 4 6 8 12 16} \
DERIVED true \
GROUP $group \
]
ad_ip_parameter SAMPLES_PER_FRAME_MANUAL INTEGER 1 false [list \
DISPLAY_NAME "Samples per Frame (S)" \
DISPLAY_UNITS "samples" \
ALLOWED_RANGES {1 2 3 4 6 8 12 16} \
VISIBLE false \
GROUP $group \
]
ad_ip_parameter OCTETS_PER_FRAME INTEGER 1 false [list \
DISPLAY_NAME "Octets per Frame (F)" \
DISPLAY_UNITS "octets" \
ALLOWED_RANGES {1 2 4 8} \
DERIVED true \
GROUP $group \
]
set group "Framer Input Information"
# Parameters in this group are informative only and can be read back after the
# core has been configured to find out the expected layout of the input data.
# E.g.
# set NUM_OF_CHANNELS [get_instance_parameter_value jesd204_transport NUM_CHANNELS]
# set CHANNEL_DATA_WIDTH [get_instance_parameter_value jesd204_transport CHANNEL_DATA_WIDTH]
#
# add_instance util_dac_upack util_upack
# set_instance_parameter_values util_dac_upack [list \
# CHANNEL_DATA_WIDTH $CHANNEL_DATA_WIDTH \
# NUM_OF_CHANNELS $NUM_OF_CHANNELS \
# ]
ad_ip_parameter SAMPLES_PER_CHANNEL INTEGER 1 false [list \
DISPLAY_NAME "Samples per Channel per Beat" \
DERIVED true \
GROUP $group \
]
ad_ip_parameter CHANNEL_DATA_WIDTH INTEGER 1 false [list \
DISPLAY_NAME "Channel Data Width" \
UNITS bits \
DERIVED true \
GROUP $group \
]
set group "Datapath Configuration"
ad_ip_parameter DATAPATH_DISABLE boolean 0 true [list \
DISPLAY_NAME "Disable Datapath" \
GROUP $group \
]
ad_ip_parameter DDS_TYPE INTEGER 1 true [list \
DISPLAY_NAME "DDS Type" \
ALLOWED_RANGES {"0:Polynominal" "1:CORDIC"} \
GROUP $group \
]
ad_ip_parameter DDS_CORDIC_DW INTEGER 16 true [list \
DISPLAY_NAME "CORDIC DDS Data Width" \
ALLOWED_RANGES {8:20} \
UNITS bits \
GROUP $group \
]
ad_ip_parameter DDS_CORDIC_PHASE_DW INTEGER 16 true [list \
DISPLAY_NAME "CORDIC DDS Phase Width" \
ALLOWED_RANGES {8:20} \
UNITS bits \
GROUP $group \
]
# axi4 slave
ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn 12
# core clock and start of frame
add_interface link_clk clock end
add_interface_port link_clk link_clk clk Input 1
# We don't expect too large values for a and b, trivial implementation will do
proc gcd {a b} {
if {$a == $b} {
return $b
} elseif {$a > $b} {
return [gcd [expr $a - $b] $b]
} else {
return [gcd $a [expr $b - $a]]
}
}
# M L S F N NP
set ad9136_modes { \
{1 4 2 1 16 16} \
{1 2 1 1 16 16} \
{1 1 1 2 16 16} \
{2 8 2 1 16 16} \
{2 4 1 1 16 16} \
{2 2 1 2 16 16} \
}
set ad9144_modes { \
{4 8 1 1 16 16} \
{4 8 2 2 16 16} \
{4 4 1 2 16 16} \
{4 2 1 4 16 16} \
{2 4 1 1 16 16} \
{2 4 2 2 16 16} \
{2 2 1 2 16 16} \
{2 1 1 4 16 16} \
{1 2 1 1 16 16} \
{1 1 1 2 16 16} \
}
set ad9152_modes { \
{2 4 1 1 16 16} \
{2 4 2 2 16 16} \
{2 2 1 2 16 16} \
{2 1 1 4 16 16} \
{1 2 1 1 16 16} \
{1 1 1 2 16 16} \
}
set ad9161_modes { \
{2 1 1 4 16 16} \
{2 2 1 2 16 16} \
{2 3 3 4 16 16} \
{2 4 1 1 16 16} \
{2 6 3 2 16 16} \
{1 8 4 1 16 16} \
{2 8 2 1 16 16} \
}
set ad9163_modes { \
{2 1 1 4 16 16} \
{2 2 1 2 16 16} \
{2 3 3 4 16 16} \
{2 4 1 1 16 16} \
{2 6 3 2 16 16} \
{2 8 2 1 16 16} \
}
set ad9171_modes { \
{2 1 1 4 16 16} \
{2 2 1 2 16 16} \
{2 1 1 3 12 12} \
}
set ad9172_modes { \
{2 1 1 4 16 16} \
{4 2 1 4 16 16} \
{6 3 1 4 16 16} \
{2 2 1 2 16 16} \
{4 4 1 2 16 16} \
{2 1 1 3 12 12} \
{4 2 1 3 12 12} \
{4 1 1 8 16 16} \
{2 4 1 1 16 16} \
{2 4 2 2 16 16} \
{2 8 2 1 16 16} \
{2 8 4 2 16 16} \
{2 8 8 3 12 12} \
{1 4 2 1 16 16} \
{1 4 4 2 16 16} \
{1 8 4 1 16 16} \
{1 8 8 2 16 16} \
}
set ad9173_modes { \
{2 1 1 4 16 16} \
{4 2 1 4 16 16} \
{6 3 1 4 16 16} \
{2 2 1 2 16 16} \
{4 4 1 2 16 16} \
{2 1 1 3 12 12} \
{4 2 1 3 12 12} \
{4 1 1 8 16 16} \
{2 4 1 1 16 16} \
{2 4 2 2 16 16} \
{2 4 1 1 11 16} \
{2 4 2 2 11 16} \
{2 8 2 1 11 16} \
{2 8 4 2 11 16} \
{2 8 8 3 11 12} \
}
# validate
proc p_ad_ip_jesd204_tpl_dac_validate {} {
set L [get_parameter_value "NUM_LANES"]
set M [get_parameter_value "NUM_CHANNELS"]
set NP [get_parameter_value "BITS_PER_SAMPLE"]
set N [get_parameter_value "CONVERTER_RESOLUTION"]
set S_manual [get_parameter_value "SAMPLES_PER_FRAME_MANUAL"]
set enable_S_manual [get_parameter_value "ENABLE_SAMPLES_PER_FRAME_MANUAL"]
# With fixed values for M, L and N' all valid values for S and F have a
# constant ratio of S / F. Choose a ratio so that S and F are co-prime.
# Choosing values for F and S that have a common factor has higher latency
# and no added benefits.
#
# Since converters often support those higher latency modes still allow a
# manual override of the S parameter in case somebody wants to use those modes
# anyway.
#
# To be able to set samples per frame manually ENABLE_SAMPLES_PER_FRAME_MANUAL
# needs to be set to true and SAMPLES_PER_FRAME_MANUAL to the desired value.
#
# When manual sample per frame selection is enabled still verify that the
# selected value is valid.
set S_min [expr $L * 8]
set F_min [expr $M * $NP]
set common_factor [gcd $S_min $F_min]
set S_min [expr $S_min / $common_factor]
set F_min [expr $F_min / $common_factor]
if {$enable_S_manual} {
if {$S_manual % $S_min != 0} {
send_message ERROR "For framer configuration (L=$L, M=$M, NP=$NP) samples per frame (S) must be an integer multiple of $S_min"
set S $S_min
set F $F_min
} else {
set S $S_manual
set F [expr $S_manual * $M * $NP / $L / 8]
}
} else {
set S $S_min
set F $F_min
}
set_parameter_value OCTETS_PER_FRAME $F
set_parameter_value SAMPLES_PER_FRAME $S
set_parameter_property SAMPLES_PER_FRAME VISIBLE [expr !$enable_S_manual]
set_parameter_property SAMPLES_PER_FRAME_MANUAL VISIBLE $enable_S_manual
set_parameter_value SAMPLES_PER_CHANNEL [expr 4 * $S / $F]
set_parameter_value CHANNEL_DATA_WIDTH [expr 16 * (4 * $S / $F)]
set data_path_enabled [expr ![get_parameter_value DATAPATH_DISABLE]]
set cordic_enabled [expr $data_path_enabled && [get_parameter_value DDS_TYPE] == 1]
set_parameter_property DDS_TYPE ENABLED $data_path_enabled
set_parameter_property DDS_CORDIC_DW ENABLED $cordic_enabled
set_parameter_property DDS_CORDIC_PHASE_DW ENABLED $cordic_enabled
set part [get_parameter_value "PART"]
if {$part == "AD9135" || $part == "AD9136"} {
global ad9136_modes
set modes $ad9136_modes
} elseif {$part == "AD9144" || $part == "AD9154"} {
global ad9144_modes
set modes $ad9144_modes
} elseif {$part == "AD9152"} {
global ad9152_modes
set modes $ad9152_modes
} elseif {$part == "AD9161" || $part == "AD9162" || $part == "AD9164"} {
global ad9161_modes
set modes $ad9161_modes
} elseif {$part == "AD9163"} {
global ad9163_modes
set modes $ad9163_modes
} elseif {$part == "AD9171"} {
global ad9171_modes
set modes $ad9171_modes
} elseif {$part == "AD9172"} {
global ad9172_modes
set modes $ad9172_modes
} elseif {$part == "AD9173"} {
global ad9173_modes
set modes $ad9173_modes
} else {
set modes {}
}
if {$modes != {}} {
set allowed_channels {}
set allowed_lanes {}
set allowed_samples_per_frame {}
set allowed_resolution {}
set allowed_bits_per_sample {}
set valid_mode false
foreach m $modes {
if {$m == [list $M $L $S $F $N $NP]} {
set valid_mode true
}
lappend allowed_channels [lindex $m 0]
lappend allowed_lanes [lindex $m 1]
lappend allowed_samples_per_frame [lindex $m 2]
lappend allowed_resolution [lindex $m 4]
lappend allowed_bits_per_sample [lindex $m 5]
}
set allowed_channels [lsort -unique -integer $allowed_channels]
set allowed_lanes [lsort -unique -integer $allowed_lanes]
set allowed_samples_per_frame [lsort -unique -integer $allowed_samples_per_frame]
set allowed_resolution [lsort -unique -integer $allowed_resolution]
set allowed_bits_per_sample [lsort -unique -integer $allowed_bits_per_sample]
if {!$valid_mode} {
send_message ERROR "Framer configuration (L=$L, M=$M, N=$N, NP=$NP, S=$S, F=$F) not supported by $part"
}
} else {
set allowed_channels {1 2 4 6 8 16 32 64}
set allowed_lanes {1 2 3 4 8 16}
set allowed_samples_per_frame {1 2 3 4 6 8 12 16}
set allowed_resolution {8 11 12 16}
set allowed_bits_per_sample {8 12 16}
}
set_parameter_property "NUM_CHANNELS" "ALLOWED_RANGES" $allowed_channels
set_parameter_property "NUM_LANES" "ALLOWED_RANGES" $allowed_lanes
set_parameter_property "SAMPLES_PER_FRAME" "ALLOWED_RANGES" $allowed_samples_per_frame
set_parameter_property "CONVERTER_RESOLUTION" "ALLOWED_RANGES" $allowed_resolution
set_parameter_property "BITS_PER_SAMPLE" "ALLOWED_RANGES" $allowed_bits_per_sample
if {$enable_S_manual} {
set allowed_S {}
foreach i {1 2 4} {
if {$F_min * $i <= 4 && $S_min * $i <= 16} {
set new_S [expr $S_min * $i]
if {[lsearch -integer $allowed_samples_per_frame $new_S] != -1} {
lappend allowed_S $new_S
}
}
}
set_parameter_property SAMPLES_PER_FRAME_MANUAL ALLOWED_RANGES $allowed_S
} else {
set_parameter_property SAMPLES_PER_FRAME_MANUAL ALLOWED_RANGES {1 2 3 4 6 8 12 16}
}
}
# elaborate
proc p_ad_ip_jesd204_tpl_dac_elab {} {
# read core parameters
set L [get_parameter_value "NUM_LANES"]
set M [get_parameter_value "NUM_CHANNELS"]
set NP [get_parameter_value "BITS_PER_SAMPLE"]
# The DMA interface is always 16-bits per sample, regardless of NP
# In case of an invalid configuration the expression can be 0, but we still
# want to be able to generate an interface without generating an extra error,
# so set the minimum width to 1.
set channel_bus_width [expr max(1, 16 * (32 * $L / ($M * $NP)))]
# link layer interface
add_interface link_data avalon_streaming source
add_interface_port link_data link_data data output [expr 32 * $L]
add_interface_port link_data link_valid valid output 1
add_interface_port link_data link_ready ready input 1
set_interface_property link_data associatedClock link_clk
set_interface_property link_data dataBitsPerSymbol [expr 32 * $L]
# dma interface
for {set i 0} {$i < $M} {incr i} {
add_interface dac_ch_$i conduit end
add_interface_port dac_ch_$i dac_enable_$i enable output 1
set_port_property dac_enable_$i fragment_list [format "enable(%d:%d)" $i $i]
add_interface_port dac_ch_$i dac_valid_$i valid output 1
set_port_property dac_valid_$i fragment_list [format "dac_valid(%d:%d)" $i $i]
add_interface_port dac_ch_$i dac_data_$i data input $channel_bus_width
set_port_property dac_data_$i fragment_list \
[format "dac_ddata(%d:%d)" [expr $channel_bus_width*$i+$channel_bus_width-1] [expr $channel_bus_width*$i]]
set_interface_property dac_ch_$i associatedClock link_clk
}
ad_interface signal dac_dunf input 1 unf
}
adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_ip.tcl
+166
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@@ -0,0 +1,166 @@
# ***************************************************************************
# ***************************************************************************
# Copyright 2018 (c) Analog Devices, Inc. All rights reserved.
#
# Each core or library found in this collection may have its own licensing terms.
# The user should keep this in in mind while exploring these cores.
#
# Redistribution and use in source and binary forms,
# with or without modification of this file, are permitted under the terms of either
# (at the option of the user):
#
# 1. The GNU General Public License version 2 as published by the
# Free Software Foundation, which can be found in the top level directory, or at:
# https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
#
# OR
#
# 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
# https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
#
# ***************************************************************************
# ***************************************************************************
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
adi_ip_create ad_ip_jesd204_tpl_dac
adi_ip_files ad_ip_jesd204_tpl_dac [list \
"$ad_hdl_dir/library/xilinx/common/ad_mul.v" \
"$ad_hdl_dir/library/common/ad_dds_sine.v" \
"$ad_hdl_dir/library/common/ad_dds_cordic_pipe.v" \
"$ad_hdl_dir/library/common/ad_dds_sine_cordic.v" \
"$ad_hdl_dir/library/common/ad_dds_2.v" \
"$ad_hdl_dir/library/common/ad_dds_1.v" \
"$ad_hdl_dir/library/common/ad_dds.v" \
"$ad_hdl_dir/library/common/ad_iqcor.v" \
"$ad_hdl_dir/library/common/ad_perfect_shuffle.v" \
"$ad_hdl_dir/library/common/ad_rst.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
"$ad_hdl_dir/library/common/up_xfer_status.v" \
"$ad_hdl_dir/library/common/up_clock_mon.v" \
"$ad_hdl_dir/library/common/up_dac_common.v" \
"$ad_hdl_dir/library/common/up_dac_channel.v" \
"$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \
"../ad_ip_jesd204_tpl_common/up_tpl_common.v" \
"ad_ip_jesd204_tpl_dac_channel.v" \
"ad_ip_jesd204_tpl_dac_core.v" \
"ad_ip_jesd204_tpl_dac_framer.v" \
"ad_ip_jesd204_tpl_dac_regmap.v" \
"ad_ip_jesd204_tpl_dac_pn.v" \
"ad_ip_jesd204_tpl_dac.v" ]
adi_ip_properties ad_ip_jesd204_tpl_dac
adi_init_bd_tcl
adi_ip_bd ad_ip_jesd204_tpl_dac "bd/bd.tcl"
set cc [ipx::current_core]
set_property display_name "JESD204 Transport Layer for DACs" $cc
set_property description "JESD204 Transport Layer for DACs" $cc
# ADD missing stuff #######################################################
adi_add_bus "link" "master" \
"xilinx.com:interface:axis_rtl:1.0" \
"xilinx.com:interface:axis:1.0" \
[list \
{"link_ready" "TREADY"} \
{"link_valid" "TVALID"} \
{"link_data" "TDATA"} \
]
adi_add_bus_clock "link_clk" "link"
set_property -dict [list \
"value_validation_type" "pairs" \
"value_validation_pairs" {"Polynominal" "0" "CORDIC" "1"} \
"enablement_tcl_expr" "\$DATAPATH_DISABLE == 0" \
] [ipx::get_user_parameters DDS_TYPE -of_objects $cc]
foreach p {DDS_CORDIC_DW DDS_CORDIC_PHASE_DW} {
set_property -dict [list \
"value_validation_type" "range_long" \
"value_validation_range_minimum" 8 \
"value_validation_range_maximum" 20 \
"enablement_tcl_expr" "\$DATAPATH_DISABLE == 0 && \$DDS_TYPE == 1" \
] [ipx::get_user_parameters $p -of_objects $cc]
}
foreach {p v} {
"NUM_LANES" "1 2 3 4 8 16" \
"NUM_CHANNELS" "1 2 4 6 8 16 32 64" \
"BITS_PER_SAMPLE" "8 12 16" \
"CONVERTER_RESOLUTION" "8 11 12 16" \
"SAMPLES_PER_FRAME" "1 2 3 4 6 8 12 16" \
"OCTETS_PER_BEAT" "4 8" \
} { \
set_property -dict [list \
"value_validation_type" "list" \
"value_validation_list" $v \
] [ipx::get_user_parameters $p -of_objects $cc]
}
set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]
set general_group [ipgui::add_group -name "General Configuration" -component $cc \
-parent $page0 -display_name "General Configuration"]
set p [ipgui::get_guiparamspec -name "ID" -component $cc]
ipgui::move_param -component $cc -order 0 $p -parent $general_group
set_property -dict [list \
"display_name" "Core ID" \
] $p
set framer_group [ipgui::add_group -name "JESD204 Framer Configuration" -component $cc \
-parent $page0 -display_name "JESD204 Framer Cofiguration"]
set i 0
foreach {k v} { \
"NUM_LANES" "Number of Lanes (L)" \
"NUM_CHANNELS" "Number of Conveters (M)" \
"BITS_PER_SAMPLE" "Bits per Sample (N')" \
"CONVERTER_RESOLUTION" "Converter Resolution (N)" \
"SAMPLES_PER_FRAME" "Samples per Frame (S)" \
"OCTETS_PER_BEAT" "Octets per Beat" \
} { \
set p [ipgui::get_guiparamspec -name $k -component $cc]
ipgui::move_param -component $cc -order $i $p -parent $framer_group
set_property -dict [list \
WIDGET "comboBox" \
DISPLAY_NAME $v \
] $p
incr i
}
set datapath_group [ipgui::add_group -name "Datapath Configuration" -component $cc \
-parent $page0 -display_name "Datapath Cofiguration"]
set i 0
foreach {k v w} {
"DATAPATH_DISABLE" "Disable Datapath" "checkBox" \
"EXT_SYNC" "Enable external SYNC" "checkBox" \
"IQCORRECTION_DISABLE" "Disable IQ Correction" "checkBox" \
"DDS_TYPE" "DDS Type" "comboBox" \
"DDS_CORDIC_DW" "CORDIC DDS Data Width" "text" \
"DDS_CORDIC_PHASE_DW" "CORDIC DDS Phase Width" "text" \
} { \
set p [ipgui::get_guiparamspec -name $k -component $cc]
ipgui::move_param -component $cc -order $i $p -parent $datapath_group
set_property -dict [list \
WIDGET $w \
DISPLAY_NAME $v \
] $p
incr i
}
adi_add_auto_fpga_spec_params
ipx::create_xgui_files [ipx::current_core]
ipx::save_core [ipx::current_core]
adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_pn.v
+99
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// ***************************************************************************
// ***************************************************************************
// Copyright 2018 (c) Analog Devices, Inc. All rights reserved.
//
// Each core or library found in this collection may have its own licensing terms.
// The user should keep this in in mind while exploring these cores.
//
// Redistribution and use in source and binary forms,
// with or without modification of this file, are permitted under the terms of either
// (at the option of the user):
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory, or at:
// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
//
// OR
//
// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_ip_jesd204_tpl_dac_pn #(
parameter DATA_PATH_WIDTH = 4,
parameter CONVERTER_RESOLUTION = 16
) (
input clk,
input reset,
output [DATA_PATH_WIDTH*CONVERTER_RESOLUTION-1:0] pn7_data,
output [DATA_PATH_WIDTH*CONVERTER_RESOLUTION-1:0] pn15_data
);
localparam CR = CONVERTER_RESOLUTION;
localparam DW = DATA_PATH_WIDTH * CR - 1;
/* We need at least enough bits to store the PN state */
localparam PN7_W = DW > 6 ? DW : 6;
localparam PN15_W = DW > 14 ? DW : 14;
reg [PN7_W:0] pn7_state = {PN7_W+1{1'b1}};
reg [PN15_W:0] pn15_state = {PN15_W+1{1'b1}};
wire [DW:0] pn7;
wire [DW+7:0] pn7_full_state;
wire [PN7_W:0] pn7_reset;
wire [DW:0] pn15;
wire [DW+15:0] pn15_full_state;
wire [PN15_W:0] pn15_reset;
/* PN7 x^7 + x^6 + 1 */
assign pn7 = pn7_full_state[7+:DW+1] ^ pn7_full_state[6+:DW+1];
assign pn7_full_state = {pn7_state[6:0],pn7};
/* PN15 x^15 + x^14 + 1 */
assign pn15 = pn15_full_state[15+:DW+1] ^ pn15_full_state[14+:DW+1];
assign pn15_full_state = {pn15_state[14:0],pn15};
assign pn7_reset[PN7_W-:7] = {7{1'b1}};
assign pn15_reset[PN15_W-:15] = {15{1'b1}};
generate
if (PN7_W >= 7) begin
assign pn7_reset[PN7_W-7:0] = pn7_reset[PN7_W:7] ^ pn7_reset[PN7_W-1:6];
end
if (PN15_W >= 15) begin
assign pn15_reset[PN15_W-15:0] = pn15_reset[PN15_W:15] ^ pn15_reset[PN15_W-1:14];
end
endgenerate
always @(posedge clk) begin
if (reset == 1'b1) begin
pn7_state <= pn7_reset;
pn15_state <= pn15_reset;
end else begin
pn7_state <= pn7_full_state[PN7_W:0];
pn15_state <= pn15_full_state[PN15_W:0];
end
end
generate
/*
* The first sample contains the first MSB of the PN sequence, but the first
* sample is also in the LSB of the output data. So extract data at the MSB
* sample of the PN state and put it into the LSB sample of the output data.
*/
genvar i;
for (i = 0; i <= DW; i = i + CR) begin: g_pn_swizzle
assign pn7_data[i+:CR] = pn7_state[PN7_W-i-:CR];
assign pn15_data[i+:CR] = pn15_state[PN15_W-i-:CR];
end
endgenerate
endmodule
adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_regmap.v
+324
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// ***************************************************************************
// ***************************************************************************
// Copyright 2018 (c) Analog Devices, Inc. All rights reserved.
//
// Each core or library found in this collection may have its own licensing terms.
// The user should keep this in in mind while exploring these cores.
//
// Redistribution and use in source and binary forms,
// with or without modification of this file, are permitted under the terms of either
// (at the option of the user):
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory, or at:
// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
//
// OR
//
// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_ip_jesd204_tpl_dac_regmap #(
parameter ID = 0,
parameter DATAPATH_DISABLE = 0,
parameter IQCORRECTION_DISABLE = 1,
parameter FPGA_TECHNOLOGY = 0,
parameter FPGA_FAMILY = 0,
parameter SPEED_GRADE = 0,
parameter DEV_PACKAGE = 0,
parameter NUM_CHANNELS = 2,
parameter DATA_PATH_WIDTH = 16,
parameter NUM_PROFILES = 1 // Number of supported JESD profiles
) (
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
output s_axi_awready,
input [12:0] s_axi_awaddr,
input [2:0] s_axi_awprot,
input s_axi_wvalid,
output s_axi_wready,
input [31:0] s_axi_wdata,
input [3:0] s_axi_wstrb,
input s_axi_arvalid,
output s_axi_arready,
input [12:0] s_axi_araddr,
input [2:0] s_axi_arprot,
output s_axi_rvalid,
input s_axi_rready,
output [31:0] s_axi_rdata,
output [1:0] s_axi_rresp,
output s_axi_bvalid,
input s_axi_bready,
output [1:0] s_axi_bresp,
input link_clk,
input dac_dunf,
output dac_sync,
input dac_sync_in_status,
output [NUM_CHANNELS*4-1:0] dac_data_sel,
output dac_dds_format,
output [NUM_CHANNELS*16-1:0] dac_dds_scale_0,
output [NUM_CHANNELS*16-1:0] dac_dds_init_0,
output [NUM_CHANNELS*16-1:0] dac_dds_incr_0,
output [NUM_CHANNELS*16-1:0] dac_dds_scale_1,
output [NUM_CHANNELS*16-1:0] dac_dds_init_1,
output [NUM_CHANNELS*16-1:0] dac_dds_incr_1,
output [NUM_CHANNELS*16-1:0] dac_pat_data_0,
output [NUM_CHANNELS*16-1:0] dac_pat_data_1,
output [NUM_CHANNELS-1:0] dac_iqcor_enb,
output [NUM_CHANNELS*16-1:0] dac_iqcor_coeff_1,
output [NUM_CHANNELS*16-1:0] dac_iqcor_coeff_2,
// Framer interface
input [NUM_PROFILES*8-1: 0] jesd_m,
input [NUM_PROFILES*8-1: 0] jesd_l,
input [NUM_PROFILES*8-1: 0] jesd_s,
input [NUM_PROFILES*8-1: 0] jesd_f,
input [NUM_PROFILES*8-1: 0] jesd_n,
input [NUM_PROFILES*8-1: 0] jesd_np,
output [$clog2(NUM_PROFILES):0] up_profile_sel
);
// internal registers
reg up_wack = 1'b0;
reg up_rack = 1'b0;
reg [31:0] up_rdata = 32'h00;
reg [31:0] up_rdata_all;
wire up_wreq_s;
wire [10:0] up_waddr_s;
wire [31:0] up_wdata_s;
wire [NUM_CHANNELS+1:0] up_wack_s;
wire up_rreq_s;
wire [10:0] up_raddr_s;
wire [31:0] up_rdata_s[0:NUM_CHANNELS+1];
wire [NUM_CHANNELS+1:0] up_rack_s;
// internal clocks and resets
wire up_clk;
wire up_rstn;
wire dac_rst;
// signal name changes
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
// up bus interface
up_axi #(
.AXI_ADDRESS_WIDTH (13)
) i_up_axi (
.up_clk (up_clk),
.up_rstn (up_rstn),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata),
.up_rack (up_rack)
);
integer n;
always @(*) begin
up_rdata_all = 'h00;
for (n = 0; n < NUM_CHANNELS + 2; n = n + 1) begin
up_rdata_all = up_rdata_all | up_rdata_s[n];
end
end
always @(posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_rdata <= 'd0;
up_rack <= 'd0;
up_wack <= 'd0;
end else begin
up_rdata <= up_rdata_all;
up_rack <= |up_rack_s;
up_wack <= |up_wack_s;
end
end
// dac common processor interface
up_dac_common #(
.COMMON_ID(6'h0),
.ID (ID),
.CONFIG((DATAPATH_DISABLE << 6) | (IQCORRECTION_DISABLE << 0)),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),
.DEV_PACKAGE (DEV_PACKAGE),
.DRP_DISABLE (1),
.USERPORTS_DISABLE (1),
.GPIO_DISABLE (1)
) i_up_dac_common (
.mmcm_rst (),
.dac_clk (link_clk),
.dac_rst (dac_rst),
.dac_sync (dac_sync),
.dac_sync_in_status (dac_sync_in_status),
.dac_frame (),
.dac_clksel (),
.dac_par_type (),
.dac_par_enb (),
.dac_r1_mode (),
.dac_datafmt (dac_dds_format),
.dac_datarate (),
.dac_status (1'b1),
.dac_status_unf (dac_dunf),
.dac_clk_ratio (DATA_PATH_WIDTH),
.up_drp_sel (),
.up_drp_wr (),
.up_drp_addr (),
.up_drp_wdata (),
.up_drp_rdata (32'd0),
.up_drp_ready (1'd0),
.up_drp_locked (1'd1),
.up_usr_chanmax (),
.dac_usr_chanmax (NUM_CHANNELS),
.up_dac_gpio_in (32'd0),
.up_dac_gpio_out (),
.up_dac_ce (),
.up_pps_rcounter ('h00),
.up_pps_status (1'b0),
.up_pps_irq_mask (),
.up_clk (up_clk),
.up_rstn (up_rstn),
.up_wreq (up_wreq_s),
.up_waddr ({3'b0,up_waddr_s}),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[0]),
.up_rreq (up_rreq_s),
.up_raddr ({3'b0,up_raddr_s}),
.up_rdata (up_rdata_s[0]),
.up_rack (up_rack_s[0])
);
generate
genvar i;
for (i = 0; i < NUM_CHANNELS; i = i + 1) begin: g_channel
up_dac_channel #(
.COMMON_ID(6'h1 + i/16),
.CHANNEL_ID (i % 16),
.USERPORTS_DISABLE (1),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE)
) i_up_dac_channel (
.dac_clk (link_clk),
.dac_rst (dac_rst),
.dac_dds_scale_1 (dac_dds_scale_0[16*i+:16]),
.dac_dds_init_1 (dac_dds_init_0[16*i+:16]),
.dac_dds_incr_1 (dac_dds_incr_0[16*i+:16]),
.dac_dds_scale_2 (dac_dds_scale_1[16*i+:16]),
.dac_dds_init_2 (dac_dds_init_1[16*i+:16]),
.dac_dds_incr_2 (dac_dds_incr_1[16*i+:16]),
.dac_pat_data_1 (dac_pat_data_0[16*i+:16]),
.dac_pat_data_2 (dac_pat_data_1[16*i+:16]),
.dac_data_sel (dac_data_sel[4*i+:4]),
.dac_iq_mode (),
.dac_iqcor_enb (dac_iqcor_enb[i]),
.dac_iqcor_coeff_1 (dac_iqcor_coeff_1[16*i+:16]),
.dac_iqcor_coeff_2 (dac_iqcor_coeff_2[16*i+:16]),
.up_usr_datatype_be (),
.up_usr_datatype_signed (),
.up_usr_datatype_shift (),
.up_usr_datatype_total_bits (),
.up_usr_datatype_bits (),
.up_usr_interpolation_m (),
.up_usr_interpolation_n (),
.dac_usr_datatype_be (1'b0),
.dac_usr_datatype_signed (1'b1),
.dac_usr_datatype_shift (8'd0),
.dac_usr_datatype_total_bits (8'd16),
.dac_usr_datatype_bits (8'd16),
.dac_usr_interpolation_m (16'd1),
.dac_usr_interpolation_n (16'd1),
.up_clk (up_clk),
.up_rstn (up_rstn),
.up_wreq (up_wreq_s),
.up_waddr ({3'b0,up_waddr_s}),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[i+1]),
.up_rreq (up_rreq_s),
.up_raddr ({3'b0,up_raddr_s}),
.up_rdata (up_rdata_s[i+1]),
.up_rack (up_rack_s[i+1])
);
end
endgenerate
up_tpl_common #(
.COMMON_ID(2'h0), // Offset of regmap
.NUM_PROFILES(NUM_PROFILES) // Number of JESD profiles
) i_up_tpl_dac (
.jesd_m (jesd_m),
.jesd_l (jesd_l),
.jesd_s (jesd_s),
.jesd_f (jesd_f),
.jesd_n (jesd_n),
.jesd_np (jesd_np),
.up_profile_sel (up_profile_sel),
// bus interface
.up_clk (up_clk),
.up_rstn (up_rstn),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[NUM_CHANNELS+1]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[NUM_CHANNELS+1]),
.up_rack (up_rack_s[NUM_CHANNELS+1])
);
endmodule
adi_library/jesd204/ad_ip_jesd204_tpl_dac/bd/bd.tcl
+47
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# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!
proc init {cellpath otherInfo} {
set ip [get_bd_cells $cellpath]
bd::mark_propagate_only $ip " \
DEV_PACKAGE \
SPEED_GRADE \
FPGA_FAMILY \
FPGA_TECHNOLOGY"
adi_auto_assign_device_spec $cellpath
}
# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)
proc adi_auto_assign_device_spec {cellpath} {
set ip [get_bd_cells $cellpath]
set ip_param_list [list_property $ip]
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
set parent_dir "../"
for {set x 1} {$x<=4} {incr x} {
set linkname ${ip_path}${parent_dir}scripts/adi_xilinx_device_info_enc.tcl
if { [file exists $linkname] } {
source ${ip_path}${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl
break
}
append parent_dir "../"
}
# Find predefindes auto assignable parameters
foreach i $auto_set_param_list {
if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
set val [adi_device_spec $cellpath $i]
set_property CONFIG.$i $val $ip
}
}
# Find predefindes auto assignable/overwritable parameters
foreach i $auto_set_param_list_overwritable {
if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
set val [adi_device_spec $cellpath $i]
set_property CONFIG.$i $val $ip
}
}
}
adi_library/jesd204/ad_ip_jesd204_tpl_dac/component.xml
+1428
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adi_library/jesd204/ad_ip_jesd204_tpl_dac/gui/ad_ip_jesd204_tpl_dac_v1_0.gtcl
+4
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@@ -0,0 +1,4 @@
# This file is automatically written. Do not modify.
proc gen_USERPARAMETER_DDS_TYPE_ENABLEMENT {DATAPATH_DISABLE } {expr $DATAPATH_DISABLE == 0}
proc gen_USERPARAMETER_DDS_CORDIC_DW_ENABLEMENT {DATAPATH_DISABLE DDS_TYPE } {expr $DATAPATH_DISABLE == 0 && $DDS_TYPE == 1}
proc gen_USERPARAMETER_DDS_CORDIC_PHASE_DW_ENABLEMENT {DATAPATH_DISABLE DDS_TYPE } {expr $DATAPATH_DISABLE == 0 && $DDS_TYPE == 1}
adi_library/jesd204/ad_ip_jesd204_tpl_dac/scripts/generate_presets.py
+48
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@@ -0,0 +1,48 @@
#!/usr/bin/env python3
import math
import os
import sys
path = os.path.dirname(sys.argv[0])
f = open(os.path.join(path, 'modes.txt'))
conv = {}
for l in f:
if l[0] == "#":
continue
x = l.split()
if len(x) == 0:
continue
if len(x) == 1:
name = x[0]
modes = []
conv[name] = modes
continue
modes.append(list(map(int, x)))
f.close()
for name, modes in conv.items():
f = open(os.path.join(path, '..', '{}.qprs'.format(name)), 'w')
f.write('<?xml version="1.0" encoding="UTF-8"?>\n<ip><presets version="17.1">\n')
for m in modes:
f.write('\t<preset name="{} Mode {:02d}" kind="ad_ip_jesd204_tpl_dac" version="All" description="{}">\n'.format(name, m[0], name))
f.write('\t\t<parameter name="PART" value="{}" />\n'.format(name))
f.write('\t\t<parameter name="NUM_CHANNELS" value="{}" />\n'.format(m[1]))
f.write('\t\t<parameter name="NUM_LANES" value="{}" />\n'.format(m[2]))
if math.gcd(m[4], m[3]) != 1:
f.write('\t\t<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="1" />\n')
else:
f.write('\t\t<parameter name="ENABLE_SAMPLES_PER_FRAME_MANUAL" value="0" />\n')
f.write('\t\t<parameter name="SAMPLES_PER_FRAME_MANUAL" value="{}" />\n'.format(m[3]))
f.write('\t\t<parameter name="CONVERTER_RESOLUTION" value="{}" />\n'.format(m[6]))
f.write('\t\t<parameter name="BITS_PER_SAMPLE" value="{}" />\n'.format(m[7]))
f.write('\t</preset>\n')
f.write('</presets></ip>\n')
f.close()
adi_library/jesd204/ad_ip_jesd204_tpl_dac/scripts/modes.txt
+89
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# Mode M L S F HD N NP
AD9135
8 1 4 2 1 1 16 16
9 1 2 1 1 1 16 16
10 1 1 1 2 0 16 16
11 2 8 2 1 1 16 16
12 2 4 1 1 1 16 16
13 2 2 1 2 0 16 16
AD9136
8 1 4 2 1 1 16 16
9 1 2 1 1 1 16 16
10 1 1 1 2 0 16 16
11 2 8 2 1 1 16 16
12 2 4 1 1 1 16 16
13 2 2 1 2 0 16 16
AD9144
0 4 8 1 1 1 16 16
1 4 8 2 2 0 16 16
2 4 4 1 2 0 16 16
3 4 2 1 4 0 16 16
4 2 4 1 1 1 16 16
5 2 4 2 2 0 16 16
6 2 2 1 2 0 16 16
7 2 1 1 4 0 16 16
9 1 2 1 1 1 16 16
10 1 1 1 2 0 16 16
AD9152
4 2 4 1 1 1 16 16
5 2 4 2 2 0 16 16
6 2 2 1 2 0 16 16
7 2 1 1 4 0 16 16
9 1 2 1 1 1 16 16
10 1 1 1 2 0 16 16
AD9154
0 4 8 1 1 1 16 16
1 4 8 2 2 0 16 16
2 4 4 1 2 0 16 16
3 4 2 1 4 0 16 16
4 2 4 1 1 1 16 16
5 2 4 2 2 0 16 16
6 2 2 1 2 0 16 16
7 2 1 1 4 0 16 16
9 1 2 1 1 1 16 16
10 1 1 1 2 0 16 16
AD9171
0 2 1 1 4 1 16 16
3 2 2 1 2 1 16 16
5 2 1 1 3 1 12 12
AD9172
0 2 1 1 4 1 16 16
1 4 2 1 4 1 16 16
2 6 3 1 4 1 16 16
3 2 2 1 2 1 16 16
4 4 4 1 2 1 16 16
5 2 1 1 3 1 12 12
6 4 2 1 3 1 12 12
7 4 1 1 8 1 16 16
8 2 4 1 1 1 16 16
9 2 4 2 2 1 16 16
10 2 8 2 1 1 16 16
11 2 8 4 2 1 16 16
12 2 8 8 3 1 12 12
18 1 4 2 1 1 16 16
19 1 4 4 2 1 16 16
20 1 8 4 1 1 16 16
21 1 8 8 2 1 16 16
AD9173
0 2 1 1 4 1 16 16
1 4 2 1 4 1 16 16
2 6 3 1 4 1 16 16
3 2 2 1 2 1 16 16
4 4 4 1 2 1 16 16
5 2 1 1 3 1 12 12
6 4 2 1 3 1 12 12
7 4 1 1 8 1 16 16
8 2 4 1 1 1 16 16
9 2 4 2 2 1 16 16
13 2 4 1 1 1 11 16
14 2 4 2 2 1 11 16
15 2 8 2 1 1 11 16
16 2 8 4 2 1 11 16
17 2 8 8 3 1 11 12
adi_library/jesd204/ad_ip_jesd204_tpl_dac/temporary_case_dependencies.mk
+2
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CLEAN_TARGET += bd
CLEAN_TARGET += temporary_case_dependencies.mk
adi_library/jesd204/ad_ip_jesd204_tpl_dac/xgui/ad_ip_jesd204_tpl_dac_v1_0.tcl
+312
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# Loading additional proc with user specified bodies to compute parameter values.
source [file join [file dirname [file dirname [info script]]] gui/ad_ip_jesd204_tpl_dac_v1_0.gtcl]
# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
ipgui::add_param $IPINST -name "Component_Name"
#Adding Page
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
#Adding Group
set General_Configuration [ipgui::add_group $IPINST -name "General Configuration" -parent ${Page_0}]
ipgui::add_param $IPINST -name "ID" -parent ${General_Configuration}
#Adding Group
set JESD204_Framer_Configuration [ipgui::add_group $IPINST -name "JESD204 Framer Configuration" -parent ${Page_0} -display_name {JESD204 Framer Cofiguration}]
ipgui::add_param $IPINST -name "NUM_LANES" -parent ${JESD204_Framer_Configuration} -widget comboBox
ipgui::add_param $IPINST -name "NUM_CHANNELS" -parent ${JESD204_Framer_Configuration} -widget comboBox
ipgui::add_param $IPINST -name "BITS_PER_SAMPLE" -parent ${JESD204_Framer_Configuration} -widget comboBox
ipgui::add_param $IPINST -name "CONVERTER_RESOLUTION" -parent ${JESD204_Framer_Configuration} -widget comboBox
ipgui::add_param $IPINST -name "SAMPLES_PER_FRAME" -parent ${JESD204_Framer_Configuration} -widget comboBox
ipgui::add_param $IPINST -name "OCTETS_PER_BEAT" -parent ${JESD204_Framer_Configuration} -widget comboBox
#Adding Group
set Datapath_Configuration [ipgui::add_group $IPINST -name "Datapath Configuration" -parent ${Page_0} -display_name {Datapath Cofiguration}]
ipgui::add_param $IPINST -name "DATAPATH_DISABLE" -parent ${Datapath_Configuration} -widget checkBox
ipgui::add_param $IPINST -name "EXT_SYNC" -parent ${Datapath_Configuration} -widget checkBox
ipgui::add_param $IPINST -name "IQCORRECTION_DISABLE" -parent ${Datapath_Configuration} -widget checkBox
ipgui::add_param $IPINST -name "DDS_TYPE" -parent ${Datapath_Configuration} -widget comboBox
ipgui::add_param $IPINST -name "DDS_CORDIC_DW" -parent ${Datapath_Configuration}
ipgui::add_param $IPINST -name "DDS_CORDIC_PHASE_DW" -parent ${Datapath_Configuration}
#Adding Group
set FPGA_info [ipgui::add_group $IPINST -name "FPGA info" -parent ${Page_0}]
ipgui::add_param $IPINST -name "FPGA_TECHNOLOGY" -parent ${FPGA_info} -widget comboBox
ipgui::add_param $IPINST -name "FPGA_FAMILY" -parent ${FPGA_info} -widget comboBox
ipgui::add_param $IPINST -name "SPEED_GRADE" -parent ${FPGA_info} -widget comboBox
ipgui::add_param $IPINST -name "DEV_PACKAGE" -parent ${FPGA_info} -widget comboBox
}
proc update_PARAM_VALUE.DDS_CORDIC_DW { PARAM_VALUE.DDS_CORDIC_DW PARAM_VALUE.DATAPATH_DISABLE PARAM_VALUE.DDS_TYPE } {
# Procedure called to update DDS_CORDIC_DW when any of the dependent parameters in the arguments change
set DDS_CORDIC_DW ${PARAM_VALUE.DDS_CORDIC_DW}
set DATAPATH_DISABLE ${PARAM_VALUE.DATAPATH_DISABLE}
set DDS_TYPE ${PARAM_VALUE.DDS_TYPE}
set values(DATAPATH_DISABLE) [get_property value $DATAPATH_DISABLE]
set values(DDS_TYPE) [get_property value $DDS_TYPE]
if { [gen_USERPARAMETER_DDS_CORDIC_DW_ENABLEMENT $values(DATAPATH_DISABLE) $values(DDS_TYPE)] } {
set_property enabled true $DDS_CORDIC_DW
} else {
set_property enabled false $DDS_CORDIC_DW
}
}
proc validate_PARAM_VALUE.DDS_CORDIC_DW { PARAM_VALUE.DDS_CORDIC_DW } {
# Procedure called to validate DDS_CORDIC_DW
return true
}
proc update_PARAM_VALUE.DDS_CORDIC_PHASE_DW { PARAM_VALUE.DDS_CORDIC_PHASE_DW PARAM_VALUE.DATAPATH_DISABLE PARAM_VALUE.DDS_TYPE } {
# Procedure called to update DDS_CORDIC_PHASE_DW when any of the dependent parameters in the arguments change
set DDS_CORDIC_PHASE_DW ${PARAM_VALUE.DDS_CORDIC_PHASE_DW}
set DATAPATH_DISABLE ${PARAM_VALUE.DATAPATH_DISABLE}
set DDS_TYPE ${PARAM_VALUE.DDS_TYPE}
set values(DATAPATH_DISABLE) [get_property value $DATAPATH_DISABLE]
set values(DDS_TYPE) [get_property value $DDS_TYPE]
if { [gen_USERPARAMETER_DDS_CORDIC_PHASE_DW_ENABLEMENT $values(DATAPATH_DISABLE) $values(DDS_TYPE)] } {
set_property enabled true $DDS_CORDIC_PHASE_DW
} else {
set_property enabled false $DDS_CORDIC_PHASE_DW
}
}
proc validate_PARAM_VALUE.DDS_CORDIC_PHASE_DW { PARAM_VALUE.DDS_CORDIC_PHASE_DW } {
# Procedure called to validate DDS_CORDIC_PHASE_DW
return true
}
proc update_PARAM_VALUE.DDS_TYPE { PARAM_VALUE.DDS_TYPE PARAM_VALUE.DATAPATH_DISABLE } {
# Procedure called to update DDS_TYPE when any of the dependent parameters in the arguments change
set DDS_TYPE ${PARAM_VALUE.DDS_TYPE}
set DATAPATH_DISABLE ${PARAM_VALUE.DATAPATH_DISABLE}
set values(DATAPATH_DISABLE) [get_property value $DATAPATH_DISABLE]
if { [gen_USERPARAMETER_DDS_TYPE_ENABLEMENT $values(DATAPATH_DISABLE)] } {
set_property enabled true $DDS_TYPE
} else {
set_property enabled false $DDS_TYPE
}
}
proc validate_PARAM_VALUE.DDS_TYPE { PARAM_VALUE.DDS_TYPE } {
# Procedure called to validate DDS_TYPE
return true
}
proc update_PARAM_VALUE.BITS_PER_SAMPLE { PARAM_VALUE.BITS_PER_SAMPLE } {
# Procedure called to update BITS_PER_SAMPLE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.BITS_PER_SAMPLE { PARAM_VALUE.BITS_PER_SAMPLE } {
# Procedure called to validate BITS_PER_SAMPLE
return true
}
proc update_PARAM_VALUE.CONVERTER_RESOLUTION { PARAM_VALUE.CONVERTER_RESOLUTION } {
# Procedure called to update CONVERTER_RESOLUTION when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.CONVERTER_RESOLUTION { PARAM_VALUE.CONVERTER_RESOLUTION } {
# Procedure called to validate CONVERTER_RESOLUTION
return true
}
proc update_PARAM_VALUE.DATAPATH_DISABLE { PARAM_VALUE.DATAPATH_DISABLE } {
# Procedure called to update DATAPATH_DISABLE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.DATAPATH_DISABLE { PARAM_VALUE.DATAPATH_DISABLE } {
# Procedure called to validate DATAPATH_DISABLE
return true
}
proc update_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } {
# Procedure called to update DEV_PACKAGE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } {
# Procedure called to validate DEV_PACKAGE
return true
}
proc update_PARAM_VALUE.EXT_SYNC { PARAM_VALUE.EXT_SYNC } {
# Procedure called to update EXT_SYNC when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.EXT_SYNC { PARAM_VALUE.EXT_SYNC } {
# Procedure called to validate EXT_SYNC
return true
}
proc update_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } {
# Procedure called to update FPGA_FAMILY when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } {
# Procedure called to validate FPGA_FAMILY
return true
}
proc update_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } {
# Procedure called to update FPGA_TECHNOLOGY when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } {
# Procedure called to validate FPGA_TECHNOLOGY
return true
}
proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } {
# Procedure called to update ID when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } {
# Procedure called to validate ID
return true
}
proc update_PARAM_VALUE.IQCORRECTION_DISABLE { PARAM_VALUE.IQCORRECTION_DISABLE } {
# Procedure called to update IQCORRECTION_DISABLE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.IQCORRECTION_DISABLE { PARAM_VALUE.IQCORRECTION_DISABLE } {
# Procedure called to validate IQCORRECTION_DISABLE
return true
}
proc update_PARAM_VALUE.NUM_CHANNELS { PARAM_VALUE.NUM_CHANNELS } {
# Procedure called to update NUM_CHANNELS when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.NUM_CHANNELS { PARAM_VALUE.NUM_CHANNELS } {
# Procedure called to validate NUM_CHANNELS
return true
}
proc update_PARAM_VALUE.NUM_LANES { PARAM_VALUE.NUM_LANES } {
# Procedure called to update NUM_LANES when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.NUM_LANES { PARAM_VALUE.NUM_LANES } {
# Procedure called to validate NUM_LANES
return true
}
proc update_PARAM_VALUE.OCTETS_PER_BEAT { PARAM_VALUE.OCTETS_PER_BEAT } {
# Procedure called to update OCTETS_PER_BEAT when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.OCTETS_PER_BEAT { PARAM_VALUE.OCTETS_PER_BEAT } {
# Procedure called to validate OCTETS_PER_BEAT
return true
}
proc update_PARAM_VALUE.SAMPLES_PER_FRAME { PARAM_VALUE.SAMPLES_PER_FRAME } {
# Procedure called to update SAMPLES_PER_FRAME when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.SAMPLES_PER_FRAME { PARAM_VALUE.SAMPLES_PER_FRAME } {
# Procedure called to validate SAMPLES_PER_FRAME
return true
}
proc update_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } {
# Procedure called to update SPEED_GRADE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } {
# Procedure called to validate SPEED_GRADE
return true
}
proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID}
}
proc update_MODELPARAM_VALUE.FPGA_TECHNOLOGY { MODELPARAM_VALUE.FPGA_TECHNOLOGY PARAM_VALUE.FPGA_TECHNOLOGY } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.FPGA_TECHNOLOGY}] ${MODELPARAM_VALUE.FPGA_TECHNOLOGY}
}
proc update_MODELPARAM_VALUE.FPGA_FAMILY { MODELPARAM_VALUE.FPGA_FAMILY PARAM_VALUE.FPGA_FAMILY } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.FPGA_FAMILY}] ${MODELPARAM_VALUE.FPGA_FAMILY}
}
proc update_MODELPARAM_VALUE.SPEED_GRADE { MODELPARAM_VALUE.SPEED_GRADE PARAM_VALUE.SPEED_GRADE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.SPEED_GRADE}] ${MODELPARAM_VALUE.SPEED_GRADE}
}
proc update_MODELPARAM_VALUE.DEV_PACKAGE { MODELPARAM_VALUE.DEV_PACKAGE PARAM_VALUE.DEV_PACKAGE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.DEV_PACKAGE}] ${MODELPARAM_VALUE.DEV_PACKAGE}
}
proc update_MODELPARAM_VALUE.NUM_LANES { MODELPARAM_VALUE.NUM_LANES PARAM_VALUE.NUM_LANES } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.NUM_LANES}] ${MODELPARAM_VALUE.NUM_LANES}
}
proc update_MODELPARAM_VALUE.NUM_CHANNELS { MODELPARAM_VALUE.NUM_CHANNELS PARAM_VALUE.NUM_CHANNELS } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.NUM_CHANNELS}] ${MODELPARAM_VALUE.NUM_CHANNELS}
}
proc update_MODELPARAM_VALUE.SAMPLES_PER_FRAME { MODELPARAM_VALUE.SAMPLES_PER_FRAME PARAM_VALUE.SAMPLES_PER_FRAME } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.SAMPLES_PER_FRAME}] ${MODELPARAM_VALUE.SAMPLES_PER_FRAME}
}
proc update_MODELPARAM_VALUE.CONVERTER_RESOLUTION { MODELPARAM_VALUE.CONVERTER_RESOLUTION PARAM_VALUE.CONVERTER_RESOLUTION } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.CONVERTER_RESOLUTION}] ${MODELPARAM_VALUE.CONVERTER_RESOLUTION}
}
proc update_MODELPARAM_VALUE.BITS_PER_SAMPLE { MODELPARAM_VALUE.BITS_PER_SAMPLE PARAM_VALUE.BITS_PER_SAMPLE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.BITS_PER_SAMPLE}] ${MODELPARAM_VALUE.BITS_PER_SAMPLE}
}
proc update_MODELPARAM_VALUE.OCTETS_PER_BEAT { MODELPARAM_VALUE.OCTETS_PER_BEAT PARAM_VALUE.OCTETS_PER_BEAT } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.OCTETS_PER_BEAT}] ${MODELPARAM_VALUE.OCTETS_PER_BEAT}
}
proc update_MODELPARAM_VALUE.DDS_TYPE { MODELPARAM_VALUE.DDS_TYPE PARAM_VALUE.DDS_TYPE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.DDS_TYPE}] ${MODELPARAM_VALUE.DDS_TYPE}
}
proc update_MODELPARAM_VALUE.DDS_CORDIC_DW { MODELPARAM_VALUE.DDS_CORDIC_DW PARAM_VALUE.DDS_CORDIC_DW } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.DDS_CORDIC_DW}] ${MODELPARAM_VALUE.DDS_CORDIC_DW}
}
proc update_MODELPARAM_VALUE.DDS_CORDIC_PHASE_DW { MODELPARAM_VALUE.DDS_CORDIC_PHASE_DW PARAM_VALUE.DDS_CORDIC_PHASE_DW } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.DDS_CORDIC_PHASE_DW}] ${MODELPARAM_VALUE.DDS_CORDIC_PHASE_DW}
}
proc update_MODELPARAM_VALUE.DATAPATH_DISABLE { MODELPARAM_VALUE.DATAPATH_DISABLE PARAM_VALUE.DATAPATH_DISABLE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.DATAPATH_DISABLE}] ${MODELPARAM_VALUE.DATAPATH_DISABLE}
}
proc update_MODELPARAM_VALUE.IQCORRECTION_DISABLE { MODELPARAM_VALUE.IQCORRECTION_DISABLE PARAM_VALUE.IQCORRECTION_DISABLE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.IQCORRECTION_DISABLE}] ${MODELPARAM_VALUE.IQCORRECTION_DISABLE}
}
proc update_MODELPARAM_VALUE.EXT_SYNC { MODELPARAM_VALUE.EXT_SYNC PARAM_VALUE.EXT_SYNC } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.EXT_SYNC}] ${MODELPARAM_VALUE.EXT_SYNC}
}