Archived
first commit after restructuring
This commit is contained in:
@@ -0,0 +1,41 @@
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####################################################################################
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## Copyright 2018(c) Analog Devices, Inc.
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## Auto-generated, do not modify!
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####################################################################################
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LIBRARY_NAME := axi_jesd204_rx
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GENERIC_DEPS += ../../common/up_axi.v
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GENERIC_DEPS += axi_jesd204_rx.v
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GENERIC_DEPS += jesd204_up_ilas_mem.v
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GENERIC_DEPS += jesd204_up_rx.v
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GENERIC_DEPS += jesd204_up_rx_lane.v
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XILINX_DEPS += axi_jesd204_rx_constr.xdc
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XILINX_DEPS += axi_jesd204_rx_ip.tcl
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XILINX_DEPS += axi_jesd204_rx_ooc.ttcl
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XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_cfg.xml
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XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_cfg_rtl.xml
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XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_event.xml
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XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_event_rtl.xml
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XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_ilas_config.xml
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XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_ilas_config_rtl.xml
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XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_status.xml
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XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_status_rtl.xml
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XILINX_LIB_DEPS += jesd204/axi_jesd204_common
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XILINX_INTERFACE_DEPS += jesd204/interfaces
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INTEL_DEPS += ../../common/up_clock_mon.v
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INTEL_DEPS += ../../intel/common/up_clock_mon_constr.sdc
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INTEL_DEPS += ../../util_cdc/sync_bits.v
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INTEL_DEPS += ../../util_cdc/sync_data.v
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INTEL_DEPS += ../../util_cdc/sync_event.v
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INTEL_DEPS += ../axi_jesd204_common/jesd204_up_common.v
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INTEL_DEPS += ../axi_jesd204_common/jesd204_up_sysref.v
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INTEL_DEPS += axi_jesd204_rx_constr.sdc
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INTEL_DEPS += axi_jesd204_rx_hw.tcl
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include ../../scripts/library.mk
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@@ -0,0 +1,3 @@
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version:1
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6d6f64655f636f756e7465727c42617463684d6f6465:1
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eof:
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@@ -0,0 +1,6 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
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<!-- -->
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<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
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<labtools version="1" minor="0"/>
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@@ -0,0 +1,335 @@
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//
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// The ADI JESD204 Core is released under the following license, which is
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// different than all other HDL cores in this repository.
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//
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||||
// Please read this, and understand the freedoms and responsibilities you have
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// by using this source code/core.
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||||
//
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||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
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//
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||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
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||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact [email protected] for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
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||||
//
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||||
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`timescale 1ns/100ps
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module axi_jesd204_rx #(
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parameter ID = 0,
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parameter NUM_LANES = 1,
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parameter NUM_LINKS = 1,
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parameter LINK_MODE = 1, // 2 - 64B/66B; 1 - 8B/10B
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parameter ENABLE_LINK_STATS = 0
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) (
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input s_axi_aclk,
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input s_axi_aresetn,
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input s_axi_awvalid,
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input [13:0] s_axi_awaddr,
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output s_axi_awready,
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input [2:0] s_axi_awprot,
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input s_axi_wvalid,
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input [31:0] s_axi_wdata,
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input [3:0] s_axi_wstrb,
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output s_axi_wready,
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output s_axi_bvalid,
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output [1:0] s_axi_bresp,
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input s_axi_bready,
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input s_axi_arvalid,
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input [13:0] s_axi_araddr,
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output s_axi_arready,
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input [2:0] s_axi_arprot,
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output s_axi_rvalid,
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input s_axi_rready,
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output [ 1:0] s_axi_rresp,
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output [31:0] s_axi_rdata,
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output irq,
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input core_clk,
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input core_reset_ext,
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output core_reset,
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output [NUM_LANES-1:0] core_cfg_lanes_disable,
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output [NUM_LINKS-1:0] core_cfg_links_disable,
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output [7:0] core_cfg_beats_per_multiframe,
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output [7:0] core_cfg_octets_per_frame,
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output core_cfg_disable_scrambler,
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output core_cfg_disable_char_replacement,
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output [7:0] core_cfg_lmfc_offset,
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output core_cfg_sysref_oneshot,
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output core_cfg_sysref_disable,
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output core_cfg_buffer_early_release,
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output [7:0] core_cfg_buffer_delay,
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output [7:0] core_cfg_frame_align_err_threshold,
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||||
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input [NUM_LANES-1:0] core_ilas_config_valid,
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input [2*NUM_LANES-1:0] core_ilas_config_addr,
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input [32*NUM_LANES-1:0] core_ilas_config_data,
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input core_event_sysref_alignment_error,
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input core_event_sysref_edge,
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input core_event_frame_alignment_error,
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input core_event_unexpected_lane_state_error,
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output [6:0] core_ctrl_err_statistics_mask,
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output core_ctrl_err_statistics_reset,
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||||
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input [32*NUM_LANES-1:0] core_status_err_statistics_cnt,
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input [1:0] core_status_ctrl_state,
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input [2*NUM_LANES-1:0] core_status_lane_cgs_state,
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input [3*NUM_LANES-1:0] core_status_lane_emb_state,
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input [NUM_LANES-1:0] core_status_lane_ifs_ready,
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||||
input [14*NUM_LANES-1:0] core_status_lane_latency,
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input [8*NUM_LANES-1:0] core_status_lane_frame_align_err_cnt
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);
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localparam PCORE_VERSION = 32'h00010461; // 1.04.a
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localparam PCORE_MAGIC = 32'h32303452; // 204R
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localparam DATA_PATH_WIDTH = LINK_MODE == 2 ? 3 : 2;
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/* Register interface signals */
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reg [31:0] up_rdata = 'h0;
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reg up_wack = 1'b0;
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reg up_rack = 1'b0;
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reg up_rreq_d1 = 1'b0;
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wire up_wreq;
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wire up_rreq;
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wire [31:0] up_wdata;
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wire [11:0] up_waddr;
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wire [11:0] up_raddr;
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wire [31:0] up_rdata_common;
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wire [31:0] up_rdata_sysref;
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wire [31:0] up_rdata_rx;
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wire [4:0] up_irq_trigger;
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wire up_cfg_is_writeable;
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wire up_cfg_sysref_oneshot;
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wire up_cfg_sysref_disable;
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wire up_cfg_buffer_early_release;
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wire [7:0] up_cfg_buffer_delay;
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wire [7:0] up_cfg_lmfc_offset;
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wire [7:0] up_cfg_frame_align_err_threshold;
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wire up_reset;
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wire up_reset_synchronizer;
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wire up_event_frame_alignment_error;
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wire up_event_unexpected_lane_state_error;
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sync_event #(
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.NUM_OF_EVENTS (2)
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) i_sync_frame_align_err (
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.in_clk(core_clk),
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.in_event({core_event_unexpected_lane_state_error,
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core_event_frame_alignment_error}),
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.out_clk(s_axi_aclk),
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.out_event({up_event_unexpected_lane_state_error,
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up_event_frame_alignment_error})
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);
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assign up_irq_trigger = {3'b0,
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up_event_unexpected_lane_state_error,
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up_event_frame_alignment_error} &
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{5{~up_cfg_is_writeable}};
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up_axi #(
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.AXI_ADDRESS_WIDTH (14)
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) i_up_axi (
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.up_rstn(~up_reset),
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.up_clk(s_axi_aclk),
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.up_axi_awvalid(s_axi_awvalid),
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.up_axi_awaddr(s_axi_awaddr),
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.up_axi_awready(s_axi_awready),
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.up_axi_wvalid(s_axi_wvalid),
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.up_axi_wdata(s_axi_wdata),
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.up_axi_wstrb(s_axi_wstrb),
|
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.up_axi_wready(s_axi_wready),
|
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.up_axi_bvalid(s_axi_bvalid),
|
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.up_axi_bresp(s_axi_bresp),
|
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.up_axi_bready(s_axi_bready),
|
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.up_axi_arvalid(s_axi_arvalid),
|
||||
.up_axi_araddr(s_axi_araddr),
|
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.up_axi_arready(s_axi_arready),
|
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.up_axi_rvalid(s_axi_rvalid),
|
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.up_axi_rresp(s_axi_rresp),
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.up_axi_rdata(s_axi_rdata),
|
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.up_axi_rready(s_axi_rready),
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.up_wreq(up_wreq),
|
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.up_waddr(up_waddr),
|
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.up_wdata(up_wdata),
|
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.up_wack(up_wack),
|
||||
.up_rreq(up_rreq),
|
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.up_raddr(up_raddr),
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||||
.up_rdata(up_rdata),
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.up_rack(up_rack)
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||||
);
|
||||
|
||||
jesd204_up_common #(
|
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.PCORE_VERSION(PCORE_VERSION),
|
||||
.PCORE_MAGIC(PCORE_MAGIC),
|
||||
.ID(ID),
|
||||
.NUM_LANES(NUM_LANES),
|
||||
.NUM_LINKS(NUM_LINKS),
|
||||
.DATA_PATH_WIDTH(DATA_PATH_WIDTH),
|
||||
.NUM_IRQS(5),
|
||||
.EXTRA_CFG_WIDTH(27),
|
||||
.LINK_MODE(LINK_MODE),
|
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.ENABLE_LINK_STATS(ENABLE_LINK_STATS)
|
||||
) i_up_common (
|
||||
.up_clk(s_axi_aclk),
|
||||
.ext_resetn(s_axi_aresetn),
|
||||
|
||||
.up_reset(up_reset),
|
||||
.up_reset_synchronizer(up_reset_synchronizer),
|
||||
|
||||
.core_clk(core_clk),
|
||||
.core_reset_ext(core_reset_ext),
|
||||
.core_reset(core_reset),
|
||||
|
||||
.up_raddr(up_raddr),
|
||||
.up_rdata(up_rdata_common),
|
||||
.up_wreq(up_wreq),
|
||||
.up_waddr(up_waddr),
|
||||
.up_wdata(up_wdata),
|
||||
|
||||
.up_cfg_is_writeable(up_cfg_is_writeable),
|
||||
|
||||
.up_irq_trigger(up_irq_trigger),
|
||||
.irq(irq),
|
||||
|
||||
.core_cfg_beats_per_multiframe(core_cfg_beats_per_multiframe),
|
||||
.core_cfg_octets_per_frame(core_cfg_octets_per_frame),
|
||||
.core_cfg_lanes_disable(core_cfg_lanes_disable),
|
||||
.core_cfg_links_disable(core_cfg_links_disable),
|
||||
.core_cfg_disable_scrambler(core_cfg_disable_scrambler),
|
||||
.core_cfg_disable_char_replacement(core_cfg_disable_char_replacement),
|
||||
|
||||
.up_extra_cfg({
|
||||
/* 19-26 */ up_cfg_frame_align_err_threshold,
|
||||
/* 18 */ up_cfg_sysref_disable,
|
||||
/* 17 */ up_cfg_sysref_oneshot,
|
||||
/* 16 */ up_cfg_buffer_early_release,
|
||||
/* 08-15 */ up_cfg_buffer_delay,
|
||||
/* 00-07 */ up_cfg_lmfc_offset
|
||||
}),
|
||||
.core_extra_cfg({
|
||||
/* 19-26 */ core_cfg_frame_align_err_threshold,
|
||||
/* 18 */ core_cfg_sysref_disable,
|
||||
/* 17 */ core_cfg_sysref_oneshot,
|
||||
/* 16 */ core_cfg_buffer_early_release,
|
||||
/* 08-15 */ core_cfg_buffer_delay,
|
||||
/* 00-07 */ core_cfg_lmfc_offset
|
||||
})
|
||||
);
|
||||
|
||||
jesd204_up_sysref #(
|
||||
.DATA_PATH_WIDTH(DATA_PATH_WIDTH)
|
||||
) i_up_sysref (
|
||||
.up_clk(s_axi_aclk),
|
||||
.up_reset(up_reset),
|
||||
|
||||
.core_clk(core_clk),
|
||||
.core_event_sysref_edge(core_event_sysref_edge),
|
||||
.core_event_sysref_alignment_error(core_event_sysref_alignment_error),
|
||||
|
||||
.up_raddr(up_raddr),
|
||||
.up_rdata(up_rdata_sysref),
|
||||
.up_wreq(up_wreq),
|
||||
.up_waddr(up_waddr),
|
||||
.up_wdata(up_wdata),
|
||||
|
||||
.up_cfg_is_writeable(up_cfg_is_writeable),
|
||||
|
||||
.up_cfg_lmfc_offset(up_cfg_lmfc_offset),
|
||||
.up_cfg_sysref_oneshot(up_cfg_sysref_oneshot),
|
||||
.up_cfg_sysref_disable(up_cfg_sysref_disable)
|
||||
);
|
||||
|
||||
jesd204_up_rx #(
|
||||
.NUM_LANES(NUM_LANES),
|
||||
.DATA_PATH_WIDTH(DATA_PATH_WIDTH)
|
||||
) i_up_rx (
|
||||
.up_clk(s_axi_aclk),
|
||||
.up_reset(up_reset),
|
||||
.up_reset_synchronizer(up_reset_synchronizer),
|
||||
|
||||
.core_clk(core_clk),
|
||||
.core_reset(core_reset),
|
||||
|
||||
.up_rreq(up_rreq),
|
||||
.up_raddr(up_raddr),
|
||||
.up_rdata(up_rdata_rx),
|
||||
.up_wreq(up_wreq),
|
||||
.up_waddr(up_waddr),
|
||||
.up_wdata(up_wdata),
|
||||
|
||||
.up_cfg_is_writeable(up_cfg_is_writeable),
|
||||
|
||||
.up_cfg_buffer_early_release(up_cfg_buffer_early_release),
|
||||
.up_cfg_buffer_delay(up_cfg_buffer_delay),
|
||||
|
||||
.up_cfg_frame_align_err_threshold(up_cfg_frame_align_err_threshold),
|
||||
|
||||
.core_ctrl_err_statistics_reset(core_ctrl_err_statistics_reset),
|
||||
.core_ctrl_err_statistics_mask(core_ctrl_err_statistics_mask),
|
||||
|
||||
.core_status_ctrl_state(core_status_ctrl_state),
|
||||
.core_status_lane_cgs_state(core_status_lane_cgs_state),
|
||||
.core_status_lane_emb_state(core_status_lane_emb_state),
|
||||
.core_status_lane_ifs_ready(core_status_lane_ifs_ready),
|
||||
.core_status_lane_latency(core_status_lane_latency),
|
||||
.core_status_lane_frame_align_err_cnt(core_status_lane_frame_align_err_cnt),
|
||||
|
||||
.core_status_err_statistics_cnt(core_status_err_statistics_cnt),
|
||||
|
||||
.core_ilas_config_valid(core_ilas_config_valid),
|
||||
.core_ilas_config_addr(core_ilas_config_addr),
|
||||
.core_ilas_config_data(core_ilas_config_data)
|
||||
);
|
||||
|
||||
always @(posedge s_axi_aclk) begin
|
||||
up_wack <= up_wreq;
|
||||
|
||||
// ILAS memory takes one clock cycle before the data is ready, hence the extra
|
||||
// delay.
|
||||
up_rreq_d1 <= up_rreq;
|
||||
up_rack <= up_rreq_d1;
|
||||
if (up_rreq_d1 == 1'b1) begin
|
||||
up_rdata <= up_rdata_common | up_rdata_sysref | up_rdata_rx;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,411 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Version="7" Minor="40" Path="/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/axi_jesd204_rx/axi_jesd204_rx.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="1e23432a3fd14206ab7694702b9effd9"/>
|
||||
<Option Name="Part" Val="xc7vx485tffg1157-1"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="BoardPart" Val=""/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../../library"/>
|
||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../../../ghdl/library"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="DSAVendor" Val="xilinx"/>
|
||||
<Option Name="DSANumComputeUnits" Val="60"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="0"/>
|
||||
<Option Name="WTModelSimExportSim" Val="0"/>
|
||||
<Option Name="WTQuestaExportSim" Val="0"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="0"/>
|
||||
<Option Name="WTRivieraExportSim" Val="0"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
<Option Name="SimTypes" Val="bfm"/>
|
||||
<Option Name="SimTypes" Val="tlm"/>
|
||||
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="31">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/jesd204_up_ilas_mem.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/jesd204_up_rx.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/jesd204_up_rx_lane.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../common/up_axi.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/axi_jesd204_rx.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/axi_jesd204_rx_ooc.ttcl"/>
|
||||
<File Path="$PPRDIR/component.xml">
|
||||
<FileInfo SFType="IPXACT"/>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="axi_jesd204_rx"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<File Path="$PPRDIR/axi_jesd204_rx_constr.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="IES">
|
||||
<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Xcelium">
|
||||
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="VCS">
|
||||
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="10">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Vivado 12-1790"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="1"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="Evaluation"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="features"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="should"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="NOT"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="be"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="used"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="in"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="production"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="systems."/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Place 30-73"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="10"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="axi_spi"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val=""/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="11"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1343"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="2"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1306"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="3"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="ERROR"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1276"/>
|
||||
<MsgAttr Name="Severity" Val="CRITICAL WARNING"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="4"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-3656"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="5"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-4623"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="6"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-459"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="7"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Synth 8-3331"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="8"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Designutils 20-3303"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="9"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="HDPYFinalizeIO"/>
|
||||
</MsgRule>
|
||||
<Board/>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
<BootPmcSettings Version="1" Minor="0">
|
||||
<Parameters>
|
||||
<Parameter Name="PMC_CDO.ATTRS.LOADADDR" Value="" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_FB_CLK" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_FREQ" Value="300" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_BUS_WIDTH" Value="x1" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_DATA_MODE" Value="Single" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_FREQ" Value="200" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_SLOT_TYPE" Value="SD 2.0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_FREQ" Value="200" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_SLOT_TYPE" Value="SD 2.0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSPI_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSPI_FREQ" Value="300" Type="string"/>
|
||||
<Parameter Name="BOOT.USB_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SMAP_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SMAP_DATA_WIDTH" Value="32 Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSC_FREQ" Value="33.333" Type="string"/>
|
||||
<Parameter Name="BOOT.SECONDARY.PCIE_ENABLE" Value="0" Type="string"/>
|
||||
</Parameters>
|
||||
</BootPmcSettings>
|
||||
</Project>
|
||||
@@ -0,0 +1,81 @@
|
||||
#
|
||||
# The ADI JESD204 Core is released under the following license, which is
|
||||
# different than all other HDL cores in this repository.
|
||||
#
|
||||
# Please read this, and understand the freedoms and responsibilities you have
|
||||
# by using this source code/core.
|
||||
#
|
||||
# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
#
|
||||
# This core is free software, you can use run, copy, study, change, ask
|
||||
# questions about and improve this core. Distribution of source, or resulting
|
||||
# binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
# source of the entire project (excluding the system libraries provide by the
|
||||
# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
# License version 2 as published by the Free Software Foundation.
|
||||
#
|
||||
# This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License version 2
|
||||
# along with this source code, and binary. If not, see
|
||||
# <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
# available under terms different than the General Public License. (e.g. they
|
||||
# do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
# core with any corresponding source code.) For these alternate terms you must
|
||||
# purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
# interested in such a license should contact [email protected] for
|
||||
# more information. This commercial license is sub-licensable (if you purchase
|
||||
# chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
# purchase a JESD204 license, end users of your product will also have a
|
||||
# license to use this core in a commercial setting without releasing their
|
||||
# source code).
|
||||
#
|
||||
# In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
# or publication in which you use this JESD204 HDL core. (You are not required
|
||||
# to do so; it is up to your common sense to decide whether you want to comply
|
||||
# with this request or not.) For general publications, we suggest referencing :
|
||||
# “The design and implementation of the JESD204 HDL Core used in this project
|
||||
# is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
#
|
||||
|
||||
set script_dir [file dirname [info script]]
|
||||
|
||||
source "$script_dir/util_cdc_constr.tcl"
|
||||
|
||||
util_cdc_sync_data_constr {*|jesd204_up_rx:i_up_rx|sync_data:i_cdc_status}
|
||||
util_cdc_sync_data_constr {*|jesd204_up_rx:i_up_rx|sync_data:i_cdc_cfg}
|
||||
util_cdc_sync_event_constr {*|jesd204_up_sysref:i_up_sysref|sync_event:i_cdc_sysref_event}
|
||||
util_cdc_sync_bits_constr {*|jesd204_up_rx:i_up_rx|jesd204_up_rx_lane:gen_lane[*].i_up_rx_lane|sync_bits:i_cdc_status_ready}
|
||||
|
||||
# set_max_skew?
|
||||
set_false_path \
|
||||
-to [get_registers {*|jesd204_up_rx:i_up_rx|jesd204_up_rx_lane:gen_lane[*].i_up_rx_lane|up_status_latency[*]}]
|
||||
|
||||
util_cdc_sync_bits_constr {*|jesd204_up_rx:i_up_rx|jesd204_up_rx_lane:gen_lane[*].i_up_rx_lane|jesd204_up_ilas_mem:i_ilas_mem|sync_bits:i_cdc_ilas_ready}
|
||||
|
||||
set_false_path \
|
||||
-from [get_registers {*|jesd204_up_common:i_up_common|up_reset_core}] \
|
||||
-to [get_registers {*|jesd204_up_common:i_up_common|core_reset_vector[*]}]
|
||||
|
||||
set_false_path \
|
||||
-from [get_registers {*|jesd204_up_common:i_up_common|core_reset_vector[0]}] \
|
||||
-to [get_registers {*|jesd204_up_common:i_up_common|up_reset_synchronizer_vector[*]}]
|
||||
|
||||
set_false_path \
|
||||
-to [get_pins -compatibility_mode {*|jesd204_up_common:i_up_common|up_core_reset_ext_synchronizer_vector[*]|clrn}]
|
||||
|
||||
set_false_path \
|
||||
-from [get_registers {*|jesd204_up_common:i_up_common|up_cfg_*}] \
|
||||
-to [get_registers {*|jesd204_up_common:i_up_common|core_cfg_*}]
|
||||
|
||||
set_false_path \
|
||||
-from [get_registers {*|jesd204_up_rx:i_up_rx|up_cfg_*}] \
|
||||
-to [get_registers {*|jesd204_up_common:i_up_common|core_extra_cfg[*]}]
|
||||
|
||||
set_false_path \
|
||||
-from [get_registers {*|jesd204_up_sysref:i_up_sysref|up_cfg_*}] \
|
||||
-to [get_registers {*|jesd204_up_common:i_up_common|core_extra_cfg[*]}]
|
||||
@@ -0,0 +1,153 @@
|
||||
#
|
||||
# The ADI JESD204 Core is released under the following license, which is
|
||||
# different than all other HDL cores in this repository.
|
||||
#
|
||||
# Please read this, and understand the freedoms and responsibilities you have
|
||||
# by using this source code/core.
|
||||
#
|
||||
# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
#
|
||||
# This core is free software, you can use run, copy, study, change, ask
|
||||
# questions about and improve this core. Distribution of source, or resulting
|
||||
# binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
# source of the entire project (excluding the system libraries provide by the
|
||||
# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
# License version 2 as published by the Free Software Foundation.
|
||||
#
|
||||
# This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License version 2
|
||||
# along with this source code, and binary. If not, see
|
||||
# <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
# available under terms different than the General Public License. (e.g. they
|
||||
# do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
# core with any corresponding source code.) For these alternate terms you must
|
||||
# purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
# interested in such a license should contact [email protected] for
|
||||
# more information. This commercial license is sub-licensable (if you purchase
|
||||
# chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
# purchase a JESD204 license, end users of your product will also have a
|
||||
# license to use this core in a commercial setting without releasing their
|
||||
# source code).
|
||||
#
|
||||
# In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
# or publication in which you use this JESD204 HDL core. (You are not required
|
||||
# to do so; it is up to your common sense to decide whether you want to comply
|
||||
# with this request or not.) For general publications, we suggest referencing :
|
||||
# “The design and implementation of the JESD204 HDL Core used in this project
|
||||
# is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
#
|
||||
|
||||
set axi_clk [get_clocks -of_objects [get_ports s_axi_aclk]]
|
||||
set core_clk [get_clocks -of_objects [get_ports core_clk]]
|
||||
|
||||
set_property ASYNC_REG TRUE \
|
||||
[get_cells -hier {*cdc_sync_stage1_reg*}] \
|
||||
[get_cells -hier {*cdc_sync_stage2_reg*}]
|
||||
|
||||
# Used for synchronizing resets with asynchronous de-assert
|
||||
set_property ASYNC_REG TRUE \
|
||||
[get_cells -hier {up_reset_vector_reg*}] \
|
||||
[get_cells -hier {core_reset_vector_reg*}] \
|
||||
[get_cells -hier {up_reset_synchronizer_vector_reg*}] \
|
||||
[get_cells -hier {up_core_reset_ext_synchronizer_vector_reg*}]
|
||||
|
||||
set_false_path \
|
||||
-from [get_pins {i_up_rx/i_cdc_status/in_toggle_d1_reg/C}] \
|
||||
-to [get_pins {i_up_rx/i_cdc_status/i_sync_out/cdc_sync_stage1_reg[0]/D}]
|
||||
|
||||
set_false_path \
|
||||
-from [get_pins {i_up_rx/i_cdc_status/out_toggle_d1_reg/C}] \
|
||||
-to [get_pins {i_up_rx/i_cdc_status/i_sync_in/cdc_sync_stage1_reg[0]/D}]
|
||||
|
||||
set_false_path \
|
||||
-from [get_pins {i_up_rx/i_cdc_cfg/in_toggle_d1_reg/C}] \
|
||||
-to [get_pins {i_up_rx/i_cdc_cfg/i_sync_out/cdc_sync_stage1_reg[0]/D}]
|
||||
|
||||
set_false_path \
|
||||
-from [get_pins {i_up_rx/i_cdc_cfg/out_toggle_d1_reg/C}] \
|
||||
-to [get_pins {i_up_rx/i_cdc_cfg/i_sync_in/cdc_sync_stage1_reg[0]/D}]
|
||||
|
||||
set_false_path \
|
||||
-from [get_pins {i_up_sysref/i_cdc_sysref_event/in_toggle_d1_reg/C}] \
|
||||
-to [get_pins {i_up_sysref/i_cdc_sysref_event/i_sync_out/cdc_sync_stage1_reg[0]/D}]
|
||||
|
||||
set_false_path \
|
||||
-from [get_pins {i_up_sysref/i_cdc_sysref_event/out_toggle_d1_reg/C}] \
|
||||
-to [get_pins {i_up_sysref/i_cdc_sysref_event/i_sync_in/cdc_sync_stage1_reg[0]/D}]
|
||||
|
||||
set_false_path \
|
||||
-from [get_pins {i_up_sysref/i_cdc_sysref_event/cdc_hold_reg*/C}] \
|
||||
-to [get_pins {i_up_sysref/i_cdc_sysref_event/out_event_reg*/D}]
|
||||
|
||||
set_false_path \
|
||||
-from [get_pins {i_sync_frame_align_err/in_toggle_d1_reg/C}] \
|
||||
-to [get_pins {i_sync_frame_align_err/i_sync_out/cdc_sync_stage1_reg[0]/D}]
|
||||
|
||||
set_false_path \
|
||||
-from [get_pins {i_sync_frame_align_err/out_toggle_d1_reg/C}] \
|
||||
-to [get_pins {i_sync_frame_align_err/i_sync_in/cdc_sync_stage1_reg[0]/D}]
|
||||
|
||||
set_false_path \
|
||||
-from [get_pins {i_sync_frame_align_err/cdc_hold_reg*/C}] \
|
||||
-to [get_pins {i_sync_frame_align_err/out_event_reg*/D}]
|
||||
|
||||
# Don't place them too far appart
|
||||
set_max_delay -datapath_only \
|
||||
-from [get_pins {i_up_rx/i_cdc_status/cdc_hold_reg[*]/C}] \
|
||||
-to [get_pins {i_up_rx/i_cdc_status/out_data_reg[*]/D}] \
|
||||
[get_property -min PERIOD $axi_clk]
|
||||
|
||||
set_false_path \
|
||||
-from $core_clk \
|
||||
-to [get_pins {i_up_rx/*i_up_rx_lane/i_cdc_status_ready/cdc_sync_stage1_reg*/D}]
|
||||
|
||||
set_max_delay -datapath_only \
|
||||
-from [get_pins {i_up_rx/i_cdc_cfg/cdc_hold_reg[*]/C}] \
|
||||
-to [get_pins {i_up_rx/i_cdc_cfg/out_data_reg[*]/D}] \
|
||||
[get_property -min PERIOD $core_clk]
|
||||
|
||||
set_max_delay -datapath_only \
|
||||
-from $core_clk \
|
||||
-to [get_pins {i_up_rx/*i_up_rx_lane/up_status_latency_reg[*]/D}] \
|
||||
[get_property -min PERIOD $axi_clk]
|
||||
|
||||
set_false_path \
|
||||
-from $core_clk \
|
||||
-to [get_pins {i_up_rx/*i_up_rx_lane/i_ilas_mem/i_cdc_ilas_ready/cdc_sync_stage1_reg[0]/D}]
|
||||
|
||||
# Use -quiet here since the ILAS mem is missing in non 8b10b configuration
|
||||
set_max_delay -quiet -datapath_only \
|
||||
-from [get_pins {i_up_rx/gen_lane[*].i_up_rx_lane/i_ilas_mem/mem_reg_*/*/CLK}] \
|
||||
-to [get_pins {i_up_rx/gen_lane[*].i_up_rx_lane/i_ilas_mem/up_rdata_reg[*]/D}] \
|
||||
[get_property -min PERIOD $axi_clk]
|
||||
|
||||
set_false_path \
|
||||
-from [get_pins {i_up_common/up_reset_core_reg/C}] \
|
||||
-to [get_pins {i_up_common/core_reset_vector_reg[*]/PRE}]
|
||||
|
||||
set_false_path \
|
||||
-from [get_pins {i_up_common/core_reset_vector_reg[0]/C}] \
|
||||
-to [get_pins {i_up_common/up_reset_synchronizer_vector_reg[*]/PRE}]
|
||||
|
||||
set_false_path \
|
||||
-to [get_pins {i_up_common/up_core_reset_ext_synchronizer_vector_reg[*]/PRE}]
|
||||
|
||||
set_max_delay -datapath_only \
|
||||
-from [get_pins {i_up_common/up_cfg_*_reg*/C}] \
|
||||
-to [get_pins {i_up_common/core_cfg_*_reg*/D}] \
|
||||
[get_property -min PERIOD $core_clk]
|
||||
|
||||
set_max_delay -datapath_only \
|
||||
-from [get_pins {i_up_rx/up_cfg_*_reg*/C}] \
|
||||
-to [get_pins {i_up_common/core_extra_cfg_reg[*]/D}] \
|
||||
[get_property -min PERIOD $core_clk]
|
||||
|
||||
set_max_delay -datapath_only \
|
||||
-from [get_pins {i_up_sysref/up_cfg_*_reg*/C}] \
|
||||
-to [get_pins {i_up_common/core_extra_cfg_reg[*]/D}] \
|
||||
[get_property -min PERIOD $core_clk]
|
||||
@@ -0,0 +1,170 @@
|
||||
#
|
||||
# The ADI JESD204 Core is released under the following license, which is
|
||||
# different than all other HDL cores in this repository.
|
||||
#
|
||||
# Please read this, and understand the freedoms and responsibilities you have
|
||||
# by using this source code/core.
|
||||
#
|
||||
# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
#
|
||||
# This core is free software, you can use run, copy, study, change, ask
|
||||
# questions about and improve this core. Distribution of source, or resulting
|
||||
# binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
# source of the entire project (excluding the system libraries provide by the
|
||||
# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
# License version 2 as published by the Free Software Foundation.
|
||||
#
|
||||
# This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License version 2
|
||||
# along with this source code, and binary. If not, see
|
||||
# <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
# available under terms different than the General Public License. (e.g. they
|
||||
# do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
# core with any corresponding source code.) For these alternate terms you must
|
||||
# purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
# interested in such a license should contact [email protected] for
|
||||
# more information. This commercial license is sub-licensable (if you purchase
|
||||
# chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
# purchase a JESD204 license, end users of your product will also have a
|
||||
# license to use this core in a commercial setting without releasing their
|
||||
# source code).
|
||||
#
|
||||
# In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
# or publication in which you use this JESD204 HDL core. (You are not required
|
||||
# to do so; it is up to your common sense to decide whether you want to comply
|
||||
# with this request or not.) For general publications, we suggest referencing :
|
||||
# “The design and implementation of the JESD204 HDL Core used in this project
|
||||
# is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
#
|
||||
|
||||
package require qsys
|
||||
|
||||
source ../../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_intel.tcl
|
||||
|
||||
ad_ip_create axi_jesd204_rx "ADI JESD204 Receive AXI Interface"
|
||||
|
||||
set_module_property INTERNAL true
|
||||
|
||||
# files
|
||||
|
||||
ad_ip_files axi_jesd204_rx [list \
|
||||
axi_jesd204_rx.v \
|
||||
axi_jesd204_rx_constr.sdc \
|
||||
jesd204_up_rx.v \
|
||||
jesd204_up_rx_lane.v \
|
||||
jesd204_up_ilas_mem.v \
|
||||
../axi_jesd204_common/jesd204_up_common.v \
|
||||
../axi_jesd204_common/jesd204_up_sysref.v \
|
||||
$ad_hdl_dir/library/common/up_axi.v \
|
||||
$ad_hdl_dir/library/common/up_clock_mon.v \
|
||||
$ad_hdl_dir/library/util_cdc/sync_bits.v \
|
||||
$ad_hdl_dir/library/util_cdc/sync_data.v \
|
||||
$ad_hdl_dir/library/util_cdc/sync_event.v \
|
||||
$ad_hdl_dir/library/util_cdc/util_cdc_constr.tcl \
|
||||
$ad_hdl_dir/library/intel/common/up_clock_mon_constr.sdc \
|
||||
]
|
||||
|
||||
# parameters
|
||||
|
||||
add_parameter ID NATURAL 0
|
||||
set_parameter_property ID DISPLAY_NAME "Peripheral ID"
|
||||
set_parameter_property ID HDL_PARAMETER true
|
||||
|
||||
add_parameter NUM_LANES INTEGER 1
|
||||
set_parameter_property NUM_LANES DISPLAY_NAME "Number of Lanes"
|
||||
set_parameter_property NUM_LANES ALLOWED_RANGES 1:8
|
||||
set_parameter_property NUM_LANES HDL_PARAMETER true
|
||||
|
||||
add_parameter NUM_LINKS INTEGER 1
|
||||
set_parameter_property NUM_LINKS DISPLAY_NAME "Number of Links"
|
||||
set_parameter_property NUM_LINKS ALLOWED_RANGES 1:8
|
||||
set_parameter_property NUM_LINKS HDL_PARAMETER true
|
||||
|
||||
# axi4 slave interface
|
||||
|
||||
ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn 14
|
||||
|
||||
# interrupt
|
||||
|
||||
add_interface interrupt interrupt end
|
||||
set_interface_property interrupt associatedClock s_axi_clock
|
||||
set_interface_property interrupt associatedReset s_axi_reset
|
||||
#set_interface_property interrupt associatedAddressablePoint s_axi
|
||||
add_interface_port interrupt irq irq Output 1
|
||||
|
||||
# core clock
|
||||
|
||||
add_interface core_clock clock end
|
||||
add_interface_port core_clock core_clk clk Input 1
|
||||
|
||||
# core reset ext
|
||||
|
||||
add_interface core_reset_ext reset end
|
||||
set_interface_property core_reset_ext associatedClock core_clock
|
||||
add_interface_port core_reset_ext core_reset_ext reset Input 1
|
||||
|
||||
# core reset
|
||||
|
||||
add_interface core_reset reset start
|
||||
set_interface_property core_reset associatedClock core_clock
|
||||
set_interface_property core_reset associatedResetSinks core_reset_ext
|
||||
add_interface_port core_reset core_reset reset Output 1
|
||||
|
||||
# config interface
|
||||
|
||||
add_interface config conduit end
|
||||
set_interface_property config associatedClock core_clock
|
||||
set_interface_property config associatedReset core_reset
|
||||
|
||||
add_interface_port config core_cfg_beats_per_multiframe beats_per_multiframe Output 8
|
||||
add_interface_port config core_cfg_buffer_delay buffer_delay Output 8
|
||||
add_interface_port config core_cfg_buffer_early_release buffer_early_release Output 1
|
||||
add_interface_port config core_cfg_disable_char_replacement disable_char_replacement Output 1
|
||||
add_interface_port config core_cfg_disable_scrambler disable_scrambler Output 1
|
||||
add_interface_port config core_cfg_lanes_disable lanes_disable Output NUM_LANES
|
||||
add_interface_port config core_cfg_links_disable links_disable Output NUM_LINKS
|
||||
add_interface_port config core_cfg_lmfc_offset lmfc_offset Output 8
|
||||
add_interface_port config core_cfg_octets_per_frame octets_per_frame Output 8
|
||||
add_interface_port config core_cfg_sysref_disable sysref_disable Output 1
|
||||
add_interface_port config core_cfg_sysref_oneshot sysref_oneshot Output 1
|
||||
add_interface_port config core_cfg_frame_align_err_threshold frame_align_err_threshold Output 8
|
||||
add_interface_port config core_ctrl_err_statistics_reset err_statistics_reset Output 1
|
||||
add_interface_port config core_ctrl_err_statistics_mask err_statistics_mask Output 3
|
||||
|
||||
# status interface
|
||||
|
||||
add_interface status conduit end
|
||||
set_interface_property status associatedClock core_clock
|
||||
set_interface_property status associatedReset core_reset
|
||||
|
||||
add_interface_port status core_status_ctrl_state ctrl_state Input 2
|
||||
add_interface_port status core_status_lane_cgs_state lane_cgs_state Input 2*NUM_LANES
|
||||
add_interface_port status core_status_lane_ifs_ready lane_ifs_ready Input NUM_LANES
|
||||
add_interface_port status core_status_lane_latency lane_latency Input 14*NUM_LANES
|
||||
add_interface_port status core_status_lane_frame_align_err_cnt lane_frame_align_err_cnt Input 8*NUM_LANES
|
||||
add_interface_port status core_status_err_statistics_cnt err_statistics_cnt Input 32*NUM_LANES
|
||||
|
||||
# event interface
|
||||
|
||||
add_interface event conduit end
|
||||
set_interface_property event associatedClock core_clock
|
||||
set_interface_property event associatedReset core_reset
|
||||
|
||||
add_interface_port event core_event_sysref_alignment_error sysref_alignment_error Input 1
|
||||
add_interface_port event core_event_sysref_edge sysref_edge Input 1
|
||||
|
||||
# ilas_config
|
||||
|
||||
add_interface ilas_config conduit end
|
||||
set_interface_property ilas_config associatedClock core_clock
|
||||
set_interface_property ilas_config associatedReset core_reset
|
||||
|
||||
add_interface_port ilas_config core_ilas_config_addr addr Input 2*NUM_LANES
|
||||
add_interface_port ilas_config core_ilas_config_data data Input 32*NUM_LANES
|
||||
add_interface_port ilas_config core_ilas_config_valid valid Input NUM_LANES
|
||||
@@ -0,0 +1,153 @@
|
||||
#
|
||||
# The ADI JESD204 Core is released under the following license, which is
|
||||
# different than all other HDL cores in this repository.
|
||||
#
|
||||
# Please read this, and understand the freedoms and responsibilities you have
|
||||
# by using this source code/core.
|
||||
#
|
||||
# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
#
|
||||
# This core is free software, you can use run, copy, study, change, ask
|
||||
# questions about and improve this core. Distribution of source, or resulting
|
||||
# binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
# source of the entire project (excluding the system libraries provide by the
|
||||
# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
# License version 2 as published by the Free Software Foundation.
|
||||
#
|
||||
# This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License version 2
|
||||
# along with this source code, and binary. If not, see
|
||||
# <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
# available under terms different than the General Public License. (e.g. they
|
||||
# do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
# core with any corresponding source code.) For these alternate terms you must
|
||||
# purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
# interested in such a license should contact [email protected] for
|
||||
# more information. This commercial license is sub-licensable (if you purchase
|
||||
# chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
# purchase a JESD204 license, end users of your product will also have a
|
||||
# license to use this core in a commercial setting without releasing their
|
||||
# source code).
|
||||
#
|
||||
# In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
# or publication in which you use this JESD204 HDL core. (You are not required
|
||||
# to do so; it is up to your common sense to decide whether you want to comply
|
||||
# with this request or not.) For general publications, we suggest referencing :
|
||||
# “The design and implementation of the JESD204 HDL Core used in this project
|
||||
# is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
#
|
||||
|
||||
source ../../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
|
||||
adi_ip_create axi_jesd204_rx
|
||||
adi_ip_files axi_jesd204_rx [list \
|
||||
"../../common/up_axi.v" \
|
||||
"jesd204_up_rx.v" \
|
||||
"jesd204_up_rx_lane.v" \
|
||||
"jesd204_up_ilas_mem.v" \
|
||||
"axi_jesd204_rx_constr.xdc" \
|
||||
"axi_jesd204_rx_ooc.ttcl" \
|
||||
"axi_jesd204_rx.v" \
|
||||
]
|
||||
|
||||
adi_ip_properties axi_jesd204_rx
|
||||
|
||||
adi_ip_ttcl axi_jesd204_rx "axi_jesd204_rx_ooc.ttcl"
|
||||
|
||||
set_property PROCESSING_ORDER LATE [ipx::get_files axi_jesd204_rx_constr.xdc \
|
||||
-of_objects [ipx::get_file_groups -of_objects [ipx::current_core] \
|
||||
-filter {NAME =~ *synthesis*}]]
|
||||
|
||||
adi_ip_add_core_dependencies { \
|
||||
analog.com:user:axi_jesd204_common:1.0 \
|
||||
}
|
||||
|
||||
set_property display_name "ADI JESD204C Receive AXI Interface" [ipx::current_core]
|
||||
set_property description "ADI JESD204C Receive AXI Interface" [ipx::current_core]
|
||||
|
||||
adi_add_bus "rx_cfg" "master" \
|
||||
"analog.com:interface:jesd204_rx_cfg_rtl:1.0" \
|
||||
"analog.com:interface:jesd204_rx_cfg:1.0" \
|
||||
{ \
|
||||
{ "core_cfg_lanes_disable" "lanes_disable" } \
|
||||
{ "core_cfg_links_disable" "links_disable" } \
|
||||
{ "core_cfg_beats_per_multiframe" "beats_per_multiframe" } \
|
||||
{ "core_cfg_octets_per_frame" "octets_per_frame" } \
|
||||
{ "core_cfg_lmfc_offset" "lmfc_offset" } \
|
||||
{ "core_cfg_sysref_oneshot" "sysref_oneshot" } \
|
||||
{ "core_cfg_sysref_disable" "sysref_disable" } \
|
||||
{ "core_ctrl_err_statistics_reset" "err_statistics_reset" } \
|
||||
{ "core_ctrl_err_statistics_mask" "err_statistics_mask" } \
|
||||
{ "core_cfg_buffer_early_release" "buffer_early_release" } \
|
||||
{ "core_cfg_buffer_delay" "buffer_delay" } \
|
||||
{ "core_cfg_disable_char_replacement" "disable_char_replacement" } \
|
||||
{ "core_cfg_disable_scrambler" "disable_scrambler" } \
|
||||
{ "core_cfg_frame_align_err_threshold" "frame_align_err_threshold" } \
|
||||
}
|
||||
|
||||
adi_add_bus "rx_ilas_config" "slave" \
|
||||
"analog.com:interface:jesd204_rx_ilas_config_rtl:1.0" \
|
||||
"analog.com:interface:jesd204_rx_ilas_config:1.0" \
|
||||
{ \
|
||||
{ "core_ilas_config_valid" "valid" } \
|
||||
{ "core_ilas_config_addr" "addr" } \
|
||||
{ "core_ilas_config_data" "data" } \
|
||||
}
|
||||
|
||||
adi_add_bus "rx_event" "slave" \
|
||||
"analog.com:interface:jesd204_rx_event_rtl:1.0" \
|
||||
"analog.com:interface:jesd204_rx_event:1.0" \
|
||||
{ \
|
||||
{ "core_event_sysref_alignment_error" "sysref_alignment_error" } \
|
||||
{ "core_event_sysref_edge" "sysref_edge" } \
|
||||
{ "core_event_frame_alignment_error" "frame_alignment_error" } \
|
||||
{ "core_event_unexpected_lane_state_error" "unexpected_lane_state_error" } \
|
||||
}
|
||||
|
||||
adi_add_bus "rx_status" "slave" \
|
||||
"analog.com:interface:jesd204_rx_status_rtl:1.0" \
|
||||
"analog.com:interface:jesd204_rx_status:1.0" \
|
||||
{ \
|
||||
{ "core_status_ctrl_state" "ctrl_state" } \
|
||||
{ "core_status_lane_cgs_state" "lane_cgs_state" } \
|
||||
{ "core_status_lane_emb_state" "lane_emb_state" } \
|
||||
{ "core_status_lane_ifs_ready" "lane_ifs_ready" } \
|
||||
{ "core_status_lane_latency" "lane_latency" } \
|
||||
{ "core_status_lane_frame_align_err_cnt" "lane_frame_align_err_cnt" } \
|
||||
{ "core_status_err_statistics_cnt" "err_statistics_cnt" } \
|
||||
}
|
||||
|
||||
ipx::infer_bus_interface irq xilinx.com:signal:interrupt_rtl:1.0 [ipx::current_core]
|
||||
|
||||
adi_add_bus_clock "core_clk" "rx_status:rx_event:rx_ilas_config:rx_cfg" \
|
||||
"core_reset" "master"
|
||||
|
||||
set_property DRIVER_VALUE "0" [ipx::get_ports "core_reset_ext"]
|
||||
|
||||
adi_set_bus_dependency "rx_ilas_config" "rx_ilas_config" \
|
||||
"(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 1)"
|
||||
set cc [ipx::current_core]
|
||||
set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]
|
||||
|
||||
# Link layer mode
|
||||
set p [ipgui::get_guiparamspec -name "LINK_MODE" -component $cc]
|
||||
ipgui::move_param -component $cc -order 0 $p -parent $page0
|
||||
set_property -dict [list \
|
||||
"display_name" "Link Layer mode" \
|
||||
"tooltip" "Link Layer mode" \
|
||||
"widget" "comboBox" \
|
||||
] $p
|
||||
|
||||
set_property -dict [list \
|
||||
value_validation_type pairs \
|
||||
value_validation_pairs {64B66B 2 8B10B 1} \
|
||||
] [ipx::get_user_parameters $p -of_objects $cc]
|
||||
|
||||
ipx::create_xgui_files [ipx::current_core]
|
||||
ipx::save_core [ipx::current_core]
|
||||
@@ -0,0 +1,61 @@
|
||||
#
|
||||
# The ADI JESD204 Core is released under the following license, which is
|
||||
# different than all other HDL cores in this repository.
|
||||
#
|
||||
# Please read this, and understand the freedoms and responsibilities you have
|
||||
# by using this source code/core.
|
||||
#
|
||||
# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
#
|
||||
# This core is free software, you can use run, copy, study, change, ask
|
||||
# questions about and improve this core. Distribution of source, or resulting
|
||||
# binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
# source of the entire project (excluding the system libraries provide by the
|
||||
# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
# License version 2 as published by the Free Software Foundation.
|
||||
#
|
||||
# This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License version 2
|
||||
# along with this source code, and binary. If not, see
|
||||
# <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
# available under terms different than the General Public License. (e.g. they
|
||||
# do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
# core with any corresponding source code.) For these alternate terms you must
|
||||
# purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
# interested in such a license should contact [email protected] for
|
||||
# more information. This commercial license is sub-licensable (if you purchase
|
||||
# chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
# purchase a JESD204 license, end users of your product will also have a
|
||||
# license to use this core in a commercial setting without releasing their
|
||||
# source code).
|
||||
#
|
||||
# In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
# or publication in which you use this JESD204 HDL core. (You are not required
|
||||
# to do so; it is up to your common sense to decide whether you want to comply
|
||||
# with this request or not.) For general publications, we suggest referencing :
|
||||
# “The design and implementation of the JESD204 HDL Core used in this project
|
||||
# is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
#
|
||||
|
||||
<: setFileUsedIn { out_of_context synthesis implementation } :>
|
||||
<: ;#Component and file information :>
|
||||
<: set ComponentName [getComponentNameString] :>
|
||||
<: setOutputDirectory "./" :>
|
||||
<: setFileName $ComponentName :>
|
||||
<: setFileExtension "_ooc.xdc" :>
|
||||
|
||||
# This XDC is used only for OOC mode of synthesis, implementation.
|
||||
# These are default values for timing driven synthesis during OOC flow.
|
||||
# These values will be overwritten during implementation with information
|
||||
# from top level.
|
||||
|
||||
create_clock -name s_axi_aclk -period 10 [get_ports s_axi_aclk]
|
||||
create_clock -name core_clk -period 2.5 [get_ports core_clk]
|
||||
|
||||
################################################################################
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,122 @@
|
||||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact [email protected] for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module jesd204_up_ilas_mem (
|
||||
input up_clk,
|
||||
|
||||
input up_rreq,
|
||||
input [1:0] up_raddr,
|
||||
output reg [31:0] up_rdata,
|
||||
|
||||
input core_clk,
|
||||
input core_reset,
|
||||
|
||||
input core_ilas_config_valid,
|
||||
input [1:0] core_ilas_config_addr,
|
||||
input [31:0] core_ilas_config_data,
|
||||
|
||||
output up_ilas_ready
|
||||
);
|
||||
|
||||
reg [31:0] mem[0:3];
|
||||
reg core_ilas_captured = 1'b0;
|
||||
|
||||
sync_bits i_cdc_ilas_ready (
|
||||
.in_bits(core_ilas_captured),
|
||||
.out_resetn(1'b1),
|
||||
.out_clk(up_clk),
|
||||
.out_bits(up_ilas_ready)
|
||||
);
|
||||
|
||||
always @(posedge core_clk) begin
|
||||
if (core_reset == 1'b1) begin
|
||||
core_ilas_captured <= 1'b0;
|
||||
end else begin
|
||||
if (core_ilas_config_valid == 1'b1 && core_ilas_config_addr == 'h3) begin
|
||||
core_ilas_captured <= 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge up_clk) begin
|
||||
if (up_rreq == 1'b1) begin
|
||||
up_rdata <= mem[up_raddr];
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge core_clk) begin
|
||||
if (core_ilas_config_valid == 1'b1) begin
|
||||
mem[core_ilas_config_addr] <= core_ilas_config_data;
|
||||
end
|
||||
end
|
||||
|
||||
/*
|
||||
* Shift register with variable tap for accessing the stored data.
|
||||
*
|
||||
* This has slightly better utilization on Xilinx based platforms than the dual
|
||||
* port RAM approach, but there is no equivalent primitive on Intel resulting
|
||||
* in increased utilization since it needs to be implemented used registers and
|
||||
* muxes.
|
||||
*
|
||||
* We might make this a device dependent configuration option at some point.
|
||||
|
||||
reg [3:0] mem[0:31];
|
||||
|
||||
generate
|
||||
genvar i;
|
||||
for (i = 0; i < 32; i = i + 1) begin: gen_ilas_mem
|
||||
assign up_rdata[i] = mem[i][~up_raddr];
|
||||
|
||||
always @(posedge core_clk) begin
|
||||
if (core_ilas_config_valid == 1'b1) begin
|
||||
mem[i] <= {mem[i][2:0],core_ilas_config_data[i]};
|
||||
end
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
*/
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,237 @@
|
||||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact [email protected] for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module jesd204_up_rx # (
|
||||
parameter NUM_LANES = 1,
|
||||
parameter DATA_PATH_WIDTH = 2
|
||||
) (
|
||||
input up_clk,
|
||||
input up_reset,
|
||||
input up_reset_synchronizer,
|
||||
|
||||
input up_rreq,
|
||||
input [11:0] up_raddr,
|
||||
output reg [31:0] up_rdata,
|
||||
input up_wreq,
|
||||
input [11:0] up_waddr,
|
||||
input [31:0] up_wdata,
|
||||
|
||||
input core_clk,
|
||||
input core_reset,
|
||||
|
||||
input [NUM_LANES-1:0] core_ilas_config_valid,
|
||||
input [2*NUM_LANES-1:0] core_ilas_config_addr,
|
||||
input [32*NUM_LANES-1:0] core_ilas_config_data,
|
||||
|
||||
input [1:0] core_status_ctrl_state,
|
||||
input [2*NUM_LANES-1:0] core_status_lane_cgs_state,
|
||||
input [3*NUM_LANES-1:0] core_status_lane_emb_state,
|
||||
input [NUM_LANES-1:0] core_status_lane_ifs_ready,
|
||||
input [14*NUM_LANES-1:0] core_status_lane_latency,
|
||||
input [8*NUM_LANES-1:0] core_status_lane_frame_align_err_cnt,
|
||||
|
||||
input [32*NUM_LANES-1:0] core_status_err_statistics_cnt,
|
||||
output [6:0] core_ctrl_err_statistics_mask,
|
||||
output core_ctrl_err_statistics_reset,
|
||||
|
||||
input up_cfg_is_writeable,
|
||||
output reg up_cfg_buffer_early_release,
|
||||
output reg [7:0] up_cfg_buffer_delay,
|
||||
|
||||
output reg [7:0] up_cfg_frame_align_err_threshold
|
||||
);
|
||||
|
||||
localparam ELASTIC_BUFFER_SIZE = 256;
|
||||
|
||||
wire [1:0] up_status_ctrl_state;
|
||||
wire [2*NUM_LANES-1:0] up_status_lane_cgs_state;
|
||||
wire [8*NUM_LANES-1:0] up_status_lane_frame_align_err_cnt;
|
||||
wire [3*NUM_LANES-1:0] up_status_lane_emb_state;
|
||||
wire [31:0] up_lane_rdata[0:NUM_LANES-1];
|
||||
wire [32*NUM_LANES-1:0] up_status_err_statistics_cnt;
|
||||
|
||||
reg up_ctrl_err_statistics_reset = 0;
|
||||
reg [6:0] up_ctrl_err_statistics_mask = 7'h0;
|
||||
|
||||
sync_data #(
|
||||
.NUM_OF_BITS(2+NUM_LANES*(3+2+32+8))
|
||||
) i_cdc_status (
|
||||
.in_clk(core_clk),
|
||||
.in_data({
|
||||
core_status_err_statistics_cnt,
|
||||
core_status_ctrl_state,
|
||||
core_status_lane_cgs_state,
|
||||
core_status_lane_emb_state,
|
||||
core_status_lane_frame_align_err_cnt
|
||||
}),
|
||||
.out_clk(up_clk),
|
||||
.out_data({
|
||||
up_status_err_statistics_cnt,
|
||||
up_status_ctrl_state,
|
||||
up_status_lane_cgs_state,
|
||||
up_status_lane_emb_state,
|
||||
up_status_lane_frame_align_err_cnt
|
||||
})
|
||||
);
|
||||
|
||||
sync_data #(
|
||||
.NUM_OF_BITS(8)
|
||||
) i_cdc_cfg (
|
||||
.in_clk(up_clk),
|
||||
.in_data({
|
||||
up_ctrl_err_statistics_mask,
|
||||
up_ctrl_err_statistics_reset
|
||||
}),
|
||||
.out_clk(core_clk),
|
||||
.out_data({
|
||||
core_ctrl_err_statistics_mask,
|
||||
core_ctrl_err_statistics_reset
|
||||
})
|
||||
);
|
||||
|
||||
localparam LANE_BASE_ADDR = 'h300 / 32;
|
||||
|
||||
always @(*) begin
|
||||
case (up_raddr)
|
||||
/* Core configuration */
|
||||
12'h010: up_rdata = ELASTIC_BUFFER_SIZE; /* Elastic buffer size in octets */
|
||||
|
||||
/* JESD RX configuraton */
|
||||
12'h090: up_rdata = {
|
||||
/* 17-31 */ 15'h00, /* Reserved for future additions */
|
||||
/* 16 */ up_cfg_buffer_early_release, /* Release buffer as soon as all lanes are ready. */
|
||||
/* 10-15 */ 6'b0000, /* Reserved for future extensions of buffer_delay */
|
||||
/* 02-09 */ up_cfg_buffer_delay, /* Buffer release delay */
|
||||
/* 00-01 */ 2'b00 /* Data path width alignment */
|
||||
};
|
||||
12'h91: up_rdata = {
|
||||
/* 15-31 */ 17'h00, /* Reserved for future additions */
|
||||
/* 08-14 */ up_ctrl_err_statistics_mask,
|
||||
/* 01-07 */ 7'h0,
|
||||
/* 00 */ up_ctrl_err_statistics_reset
|
||||
};
|
||||
12'h92: up_rdata = {
|
||||
/* 08-31 */ 24'h0,
|
||||
/* 00-07 */ up_cfg_frame_align_err_threshold
|
||||
};
|
||||
|
||||
/* 0x93-0x9f reserved for future use */
|
||||
|
||||
/* JESD RX status */
|
||||
12'ha0: up_rdata = {
|
||||
/* 04-31 */ 28'h00, /* Reserved for future additions */
|
||||
/* 02-03 */ 2'b00, /* Reserved for future extensions of ctrl_state */
|
||||
/* 00-01 */ up_status_ctrl_state /* State of the internal state machine */
|
||||
};
|
||||
default: begin
|
||||
if (up_raddr[11:3] >= LANE_BASE_ADDR &&
|
||||
up_raddr[11:3] < LANE_BASE_ADDR + NUM_LANES) begin
|
||||
up_rdata = up_lane_rdata[up_raddr[11:3] - LANE_BASE_ADDR];
|
||||
end else begin
|
||||
up_rdata = 'h00;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
always @(posedge up_clk) begin
|
||||
if (up_reset == 1'b1) begin
|
||||
up_cfg_buffer_early_release <= 1'b0;
|
||||
up_cfg_buffer_delay <= 'h00;
|
||||
up_ctrl_err_statistics_mask <= 7'h0;
|
||||
up_ctrl_err_statistics_reset <= 1'b0;
|
||||
up_cfg_frame_align_err_threshold <= 8'd4;
|
||||
end else if (up_wreq == 1'b1 && up_cfg_is_writeable == 1'b1) begin
|
||||
case (up_waddr)
|
||||
/* JESD RX configuraton */
|
||||
12'h090: begin
|
||||
up_cfg_buffer_early_release <= up_wdata[16];
|
||||
up_cfg_buffer_delay <= up_wdata[9:DATA_PATH_WIDTH];
|
||||
end
|
||||
endcase
|
||||
end else if (up_wreq == 1'b1) begin
|
||||
case (up_waddr)
|
||||
12'h91: begin
|
||||
up_ctrl_err_statistics_mask <= up_wdata[14:8];
|
||||
up_ctrl_err_statistics_reset <= up_wdata[0];
|
||||
end
|
||||
12'h92: begin
|
||||
up_cfg_frame_align_err_threshold <= up_wdata[7:0];
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
genvar i;
|
||||
generate for (i = 0; i < NUM_LANES; i = i + 1) begin: gen_lane
|
||||
jesd204_up_rx_lane i_up_rx_lane (
|
||||
.up_clk(up_clk),
|
||||
.up_reset_synchronizer(up_reset_synchronizer),
|
||||
|
||||
.up_rreq(up_rreq),
|
||||
.up_raddr(up_raddr[2:0]),
|
||||
.up_rdata(up_lane_rdata[i]),
|
||||
|
||||
.up_status_cgs_state(up_status_lane_cgs_state[2*i+1:2*i]),
|
||||
.up_status_err_statistics_cnt(up_status_err_statistics_cnt[32*i+31:32*i]),
|
||||
.up_status_emb_state(up_status_lane_emb_state[3*i+2:3*i]),
|
||||
.up_status_lane_frame_align_err_cnt(up_status_lane_frame_align_err_cnt[8*i+7:8*i]),
|
||||
|
||||
.core_clk(core_clk),
|
||||
.core_reset(core_reset),
|
||||
|
||||
.core_ilas_config_valid(core_ilas_config_valid[i]),
|
||||
.core_ilas_config_addr(core_ilas_config_addr[2*i+1:2*i]),
|
||||
.core_ilas_config_data(core_ilas_config_data[32*i+31:32*i]),
|
||||
|
||||
.core_status_ifs_ready(core_status_lane_ifs_ready[i]),
|
||||
.core_status_latency(core_status_lane_latency[14*i+13:14*i])
|
||||
);
|
||||
end
|
||||
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,152 @@
|
||||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact [email protected] for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module jesd204_up_rx_lane (
|
||||
input up_clk,
|
||||
input up_reset_synchronizer,
|
||||
|
||||
input up_rreq,
|
||||
input [2:0] up_raddr,
|
||||
output reg [31:0] up_rdata,
|
||||
|
||||
input [1:0] up_status_cgs_state,
|
||||
input [31:0] up_status_err_statistics_cnt,
|
||||
input [2:0] up_status_emb_state,
|
||||
input [7:0] up_status_lane_frame_align_err_cnt,
|
||||
|
||||
input core_clk,
|
||||
input core_reset,
|
||||
|
||||
input core_ilas_config_valid,
|
||||
input [1:0] core_ilas_config_addr,
|
||||
input [31:0] core_ilas_config_data,
|
||||
|
||||
input core_status_ifs_ready,
|
||||
input [13:0] core_status_latency
|
||||
);
|
||||
|
||||
wire [1:0] up_status_ctrl_state;
|
||||
|
||||
wire up_status_ifs_ready;
|
||||
reg [13:0] up_status_latency = 'h00;
|
||||
|
||||
wire [31:0] up_ilas_rdata;
|
||||
wire up_ilas_ready;
|
||||
|
||||
sync_bits #(
|
||||
.NUM_OF_BITS(1)
|
||||
) i_cdc_status_ready (
|
||||
.in_bits({
|
||||
core_status_ifs_ready
|
||||
}),
|
||||
.out_clk(up_clk),
|
||||
.out_resetn(1'b1),
|
||||
.out_bits({
|
||||
up_status_ifs_ready
|
||||
})
|
||||
);
|
||||
|
||||
always @(posedge up_clk) begin
|
||||
if (up_reset_synchronizer == 1'b1) begin
|
||||
up_status_latency <= 'h00;
|
||||
end else begin
|
||||
if (up_status_ifs_ready == 1'b1) begin
|
||||
up_status_latency <= core_status_latency;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(*) begin
|
||||
if (up_raddr[2] == 1'b1) begin
|
||||
if (up_ilas_ready == 1'b1) begin
|
||||
up_rdata = up_ilas_rdata;
|
||||
end else begin
|
||||
up_rdata = 'h00;
|
||||
end
|
||||
end else begin
|
||||
case (up_raddr[1:0])
|
||||
2'b00: up_rdata = {
|
||||
/* 11-31 */ 21'h0, /* Reserved for future use */
|
||||
/* 08-10 */ up_status_emb_state,
|
||||
/* 06-07 */ 2'h00,
|
||||
/* 05 */ up_ilas_ready,
|
||||
/* 04 */ up_status_ifs_ready,
|
||||
/* 02-03 */ 2'b00, /* Reserved for future extensions of cgs_state */
|
||||
/* 00-01 */ up_status_cgs_state
|
||||
};
|
||||
2'b01: up_rdata = {
|
||||
/* 14-31 */ 18'h00, /* Reserved for future use */
|
||||
/* 00-13 */ up_status_latency
|
||||
};
|
||||
2'b10: up_rdata = {
|
||||
/* 00-31 */ up_status_err_statistics_cnt
|
||||
};
|
||||
2'b11: up_rdata = {
|
||||
/* 08-31 */ 24'h0, /* Reserved for future use */
|
||||
/* 00-07 */ up_status_lane_frame_align_err_cnt
|
||||
};
|
||||
default: up_rdata = 'h00;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
jesd204_up_ilas_mem i_ilas_mem (
|
||||
.up_clk(up_clk),
|
||||
|
||||
.up_rreq(up_rreq),
|
||||
.up_raddr(up_raddr[1:0]),
|
||||
.up_rdata(up_ilas_rdata),
|
||||
.up_ilas_ready(up_ilas_ready),
|
||||
|
||||
.core_clk(core_clk),
|
||||
.core_reset(core_reset),
|
||||
|
||||
.core_ilas_config_valid(core_ilas_config_valid),
|
||||
.core_ilas_config_addr(core_ilas_config_addr),
|
||||
.core_ilas_config_data(core_ilas_config_data)
|
||||
);
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,85 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||
ipgui::add_param $IPINST -name "LINK_MODE" -parent ${Page_0} -widget comboBox
|
||||
ipgui::add_param $IPINST -name "ENABLE_LINK_STATS" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "ID" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "NUM_LANES" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "NUM_LINKS" -parent ${Page_0}
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ENABLE_LINK_STATS { PARAM_VALUE.ENABLE_LINK_STATS } {
|
||||
# Procedure called to update ENABLE_LINK_STATS when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ENABLE_LINK_STATS { PARAM_VALUE.ENABLE_LINK_STATS } {
|
||||
# Procedure called to validate ENABLE_LINK_STATS
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } {
|
||||
# Procedure called to update ID when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } {
|
||||
# Procedure called to validate ID
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.LINK_MODE { PARAM_VALUE.LINK_MODE } {
|
||||
# Procedure called to update LINK_MODE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.LINK_MODE { PARAM_VALUE.LINK_MODE } {
|
||||
# Procedure called to validate LINK_MODE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.NUM_LANES { PARAM_VALUE.NUM_LANES } {
|
||||
# Procedure called to update NUM_LANES when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.NUM_LANES { PARAM_VALUE.NUM_LANES } {
|
||||
# Procedure called to validate NUM_LANES
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.NUM_LINKS { PARAM_VALUE.NUM_LINKS } {
|
||||
# Procedure called to update NUM_LINKS when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.NUM_LINKS { PARAM_VALUE.NUM_LINKS } {
|
||||
# Procedure called to validate NUM_LINKS
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.NUM_LANES { MODELPARAM_VALUE.NUM_LANES PARAM_VALUE.NUM_LANES } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.NUM_LANES}] ${MODELPARAM_VALUE.NUM_LANES}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.NUM_LINKS { MODELPARAM_VALUE.NUM_LINKS PARAM_VALUE.NUM_LINKS } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.NUM_LINKS}] ${MODELPARAM_VALUE.NUM_LINKS}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.LINK_MODE { MODELPARAM_VALUE.LINK_MODE PARAM_VALUE.LINK_MODE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.LINK_MODE}] ${MODELPARAM_VALUE.LINK_MODE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.ENABLE_LINK_STATS { MODELPARAM_VALUE.ENABLE_LINK_STATS PARAM_VALUE.ENABLE_LINK_STATS } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ENABLE_LINK_STATS}] ${MODELPARAM_VALUE.ENABLE_LINK_STATS}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user