first commit after restructuring

adi_library/jesd204/axi_jesd204_rx/Makefile

@@ -0,0 +1,41 @@
+####################################################################################
+## Copyright 2018(c) Analog Devices, Inc.
+## Auto-generated, do not modify!
+####################################################################################
+
+LIBRARY_NAME := axi_jesd204_rx
+
+GENERIC_DEPS += ../../common/up_axi.v
+GENERIC_DEPS += axi_jesd204_rx.v
+GENERIC_DEPS += jesd204_up_ilas_mem.v
+GENERIC_DEPS += jesd204_up_rx.v
+GENERIC_DEPS += jesd204_up_rx_lane.v
+
+XILINX_DEPS += axi_jesd204_rx_constr.xdc
+XILINX_DEPS += axi_jesd204_rx_ip.tcl
+XILINX_DEPS += axi_jesd204_rx_ooc.ttcl
+
+XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_cfg.xml
+XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_cfg_rtl.xml
+XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_event.xml
+XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_event_rtl.xml
+XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_ilas_config.xml
+XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_ilas_config_rtl.xml
+XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_status.xml
+XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_status_rtl.xml
+
+XILINX_LIB_DEPS += jesd204/axi_jesd204_common
+
+XILINX_INTERFACE_DEPS += jesd204/interfaces
+
+INTEL_DEPS += ../../common/up_clock_mon.v
+INTEL_DEPS += ../../intel/common/up_clock_mon_constr.sdc
+INTEL_DEPS += ../../util_cdc/sync_bits.v
+INTEL_DEPS += ../../util_cdc/sync_data.v
+INTEL_DEPS += ../../util_cdc/sync_event.v
+INTEL_DEPS += ../axi_jesd204_common/jesd204_up_common.v
+INTEL_DEPS += ../axi_jesd204_common/jesd204_up_sysref.v
+INTEL_DEPS += axi_jesd204_rx_constr.sdc
+INTEL_DEPS += axi_jesd204_rx_hw.tcl
+
+include ../../scripts/library.mk