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//
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// The ADI JESD204 Core is released under the following license, which is
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// different than all other HDL cores in this repository.
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//
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// Please read this, and understand the freedoms and responsibilities you have
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// by using this source code/core.
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//
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// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
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//
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// This core is free software, you can use run, copy, study, change, ask
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// questions about and improve this core. Distribution of source, or resulting
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// binaries (including those inside an FPGA or ASIC) require you to release the
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// source of the entire project (excluding the system libraries provide by the
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// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License version 2
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// along with this source code, and binary. If not, see
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// <http://www.gnu.org/licenses/>.
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//
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// Commercial licenses (with commercial support) of this JESD204 core are also
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// available under terms different than the General Public License. (e.g. they
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// do not require you to accompany any image (FPGA or ASIC) using the JESD204
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// core with any corresponding source code.) For these alternate terms you must
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// purchase a license from Analog Devices Technology Licensing Office. Users
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// interested in such a license should contact [email protected] for
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// more information. This commercial license is sub-licensable (if you purchase
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// chips from Analog Devices, incorporate them into your PCB level product, and
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// purchase a JESD204 license, end users of your product will also have a
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// license to use this core in a commercial setting without releasing their
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// source code).
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//
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// In addition, we kindly ask you to acknowledge ADI in any program, application
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// or publication in which you use this JESD204 HDL core. (You are not required
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// to do so; it is up to your common sense to decide whether you want to comply
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// with this request or not.) For general publications, we suggest referencing :
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// “The design and implementation of the JESD204 HDL Core used in this project
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// is copyright © 2016-2017, Analog Devices, Inc.”
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//
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`timescale 1ns/100ps
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module jesd204_lmfc (
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input clk,
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input reset,
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input sysref,
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input [7:0] cfg_beats_per_multiframe,
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input [7:0] cfg_lmfc_offset,
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input cfg_sysref_oneshot,
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input cfg_sysref_disable,
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output reg lmfc_edge,
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output reg lmfc_clk,
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output reg [7:0] lmfc_counter,
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// Local MultiBlock clock edge
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output reg lmc_edge,
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output reg lmc_quarter_edge,
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// End of Extended MultiBlock
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output reg eoemb,
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output reg sysref_edge,
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output reg sysref_alignment_error
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);
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reg sysref_r = 1'b0;
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reg sysref_d1 = 1'b0;
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reg sysref_d2 = 1'b0;
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reg sysref_d3 = 1'b0;
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reg sysref_captured;
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/* lmfc_octet_counter = lmfc_counter * (char_clock_rate / device_clock_rate) */
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reg [7:0] lmfc_counter_next = 'h00;
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reg lmfc_clk_p1 = 1'b1;
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reg lmfc_active = 1'b0;
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always @(posedge clk) begin
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sysref_r <= sysref;
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end
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/*
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* Unfortunately setup and hold are often ignored on the sysref signal relative
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* to the device clock. The device will often still work fine, just not
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* deterministic. Reduce the probability that the meta-stability creeps into the
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* reset of the system and causes non-reproducible issues.
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*/
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always @(posedge clk) begin
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sysref_d1 <= sysref_r;
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sysref_d2 <= sysref_d1;
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sysref_d3 <= sysref_d2;
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end
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always @(posedge clk) begin
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if (sysref_d3 == 1'b0 && sysref_d2 == 1'b1 && cfg_sysref_disable == 1'b0) begin
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sysref_edge <= 1'b1;
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end else begin
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sysref_edge <= 1'b0;
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end
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end
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always @(posedge clk) begin
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if (reset == 1'b1) begin
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sysref_captured <= 1'b0;
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end else if (sysref_edge == 1'b1) begin
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sysref_captured <= 1'b1;
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end
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end
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/*
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* The configuration must be static when the core is out of reset. Otherwise
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* undefined behaviour might occur.
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* E.g. lmfc_counter > beats_per_multiframe
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*
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* To change the configuration first assert reset, then update the configuration
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* setting, finally deassert reset.
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*/
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always @(*) begin
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if (lmfc_counter == cfg_beats_per_multiframe) begin
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lmfc_counter_next = 'h00;
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end else begin
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lmfc_counter_next = lmfc_counter + 1'b1;
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end
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end
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always @(posedge clk) begin
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if (reset == 1'b1) begin
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lmfc_counter <= 'h01;
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lmfc_active <= cfg_sysref_disable;
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end else begin
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/*
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* In oneshot mode only the first occurence of the
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* SYSREF signal is used for alignment.
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*/
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if (sysref_edge == 1'b1 &&
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(cfg_sysref_oneshot == 1'b0 || sysref_captured == 1'b0)) begin
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lmfc_counter <= cfg_lmfc_offset;
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lmfc_active <= 1'b1;
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end else begin
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lmfc_counter <= lmfc_counter_next;
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end
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end
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end
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always @(posedge clk) begin
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if (reset == 1'b1) begin
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sysref_alignment_error <= 1'b0;
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end else begin
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/*
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* Alignement error is reported regardless of oneshot mode
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* setting.
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*/
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sysref_alignment_error <= 1'b0;
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if (sysref_edge == 1'b1 && lmfc_active == 1'b1 &&
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lmfc_counter_next != cfg_lmfc_offset) begin
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sysref_alignment_error <= 1'b1;
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end
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end
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end
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always @(posedge clk) begin
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if (lmfc_counter == 'h00 && lmfc_active == 1'b1) begin
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lmfc_edge <= 1'b1;
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end else begin
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lmfc_edge <= 1'b0;
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end
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end
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// 1 MultiBlock = 32 blocks
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always @(posedge clk) begin
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if (lmfc_counter[4:0] == 'h00 && lmfc_active == 1'b1) begin
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lmc_edge <= 1'b1;
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end else begin
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lmc_edge <= 1'b0;
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end
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end
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always @(posedge clk) begin
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if (lmfc_counter[2:0] == 'h00 && lmfc_active == 1'b1) begin
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lmc_quarter_edge <= 1'b1;
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end else begin
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lmc_quarter_edge <= 1'b0;
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end
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end
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// End of Extended MultiBlock
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always @(posedge clk) begin
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if (lmfc_active == 1'b1) begin
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eoemb <= lmfc_counter[7:5] == cfg_beats_per_multiframe[7:5];
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end else begin
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eoemb <= 1'b0;
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end
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end
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always @(posedge clk) begin
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if (reset == 1'b1) begin
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lmfc_clk_p1 <= 1'b0;
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end else if (lmfc_active == 1'b1) begin
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if (lmfc_counter == cfg_beats_per_multiframe) begin
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lmfc_clk_p1 <= 1'b1;
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end else if (lmfc_counter == cfg_beats_per_multiframe[7:1]) begin
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lmfc_clk_p1 <= 1'b0;
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end
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end
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lmfc_clk <= lmfc_clk_p1;
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end
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endmodule
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