Archived
first commit after restructuring
This commit is contained in:
@@ -0,0 +1,14 @@
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||||
####################################################################################
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||||
## Copyright 2018(c) Analog Devices, Inc.
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||||
## Auto-generated, do not modify!
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||||
####################################################################################
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||||
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||||
LIBRARY_NAME := jesd204_soft_pcs_rx
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||||
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||||
GENERIC_DEPS += jesd204_8b10b_decoder.v
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||||
GENERIC_DEPS += jesd204_pattern_align.v
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GENERIC_DEPS += jesd204_soft_pcs_rx.v
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||||
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||||
INTEL_DEPS += jesd204_soft_pcs_rx_hw.tcl
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||||
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||||
include ../../scripts/library.mk
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||||
@@ -0,0 +1,416 @@
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||||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact [email protected] for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
|
||||
`timescale 1ns/100ps
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||||
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||||
module jesd204_8b10b_decoder (
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||||
input in_disparity,
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input [9:0] in_char,
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output [7:0] out_char,
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output out_charisk,
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output out_notintable,
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output reg out_disperr,
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output reg out_disparity
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);
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||||
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||||
/*
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* Only supports the subset of 8b10b that is used by JESD204.
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||||
* If non-supported control characters are supplied the output is undefined.
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||||
*/
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||||
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||||
reg [4:0] data5b;
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reg notintable5b;
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reg [1:0] disparity5b;
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reg ignore5b;
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reg [2:0] data3b;
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reg notintable3b;
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reg [1:0] disparity3b;
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reg ignore3b;
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reg [1:0] total_disparity;
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||||
reg notintable_disparity;
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// Only detect K28.X
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wire charisk = in_char[5:0] == 6'b000011 || in_char[5:0] == 6'b111100;
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always @(*) begin
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notintable5b = 1'b0;
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disparity5b = 2'b00;
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ignore5b = 1'b0;
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||||
case (in_char[5:0])
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6'b000011: begin
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data5b = 5'd28;
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disparity5b = 2'b11;
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end
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||||
6'b111100: begin
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data5b = 5'd28;
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disparity5b = 2'b01;
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end
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||||
6'b000110: begin
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data5b = 5'd00;
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disparity5b = 2'b11;
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||||
end
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||||
6'b111001: begin
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||||
data5b = 5'd00;
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disparity5b = 2'b01;
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||||
end
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||||
6'b010001: begin
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||||
data5b = 5'd01;
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disparity5b = 2'b11;
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||||
end
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||||
6'b101110: begin
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data5b = 5'd01;
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disparity5b = 2'b01;
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||||
end
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||||
6'b010010: begin
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data5b = 5'd02;
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disparity5b = 2'b11;
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end
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||||
6'b101101: begin
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data5b = 5'd02;
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disparity5b = 2'b01;
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end
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||||
6'b100011: begin
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data5b = 5'd03;
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end
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6'b010100: begin
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data5b = 5'd04;
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disparity5b = 2'b11;
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end
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6'b101011: begin
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data5b = 5'd04;
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disparity5b = 2'b01;
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end
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||||
6'b100101: begin
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data5b = 5'd05;
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end
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6'b100110: begin
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data5b = 5'd06;
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end
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||||
6'b000111: begin
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data5b = 5'd7;
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disparity5b = 2'b11;
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ignore5b = 1'b1;
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end
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6'b111000: begin
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data5b = 5'd7;
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disparity5b = 2'b01;
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ignore5b = 1'b1;
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end
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||||
6'b011000: begin
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data5b = 5'd8;
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disparity5b = 2'b11;
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end
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6'b100111: begin
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data5b = 5'd8;
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disparity5b = 2'b01;
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||||
end
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||||
6'b101001: begin
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data5b = 5'd9;
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end
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||||
6'b101010: begin
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data5b = 5'd10;
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end
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||||
6'b001011: begin
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data5b = 5'd11;
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end
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||||
6'b101100: begin
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data5b = 5'd12;
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end
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||||
6'b001101: begin
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data5b = 5'd13;
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end
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||||
6'b001110: begin
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data5b = 5'd14;
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end
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||||
6'b000101: begin
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data5b = 5'd15;
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disparity5b = 2'b11;
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end
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||||
6'b111010: begin
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data5b = 5'd15;
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disparity5b = 2'b01;
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||||
end
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||||
6'b001001: begin
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||||
data5b = 5'd16;
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disparity5b = 2'b11;
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end
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||||
6'b110110: begin
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data5b = 5'd16;
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disparity5b = 2'b01;
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end
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6'b110001: begin
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data5b = 5'd17;
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end
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||||
6'b110010: begin
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data5b = 5'd18;
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end
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||||
6'b010011: begin
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||||
data5b = 5'd19;
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end
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6'b110100: begin
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||||
data5b = 5'd20;
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end
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6'b010101: begin
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data5b = 5'd21;
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end
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6'b010110: begin
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data5b = 5'd22;
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end
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6'b101000: begin
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||||
data5b = 5'd23;
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disparity5b = 2'b11;
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end
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||||
6'b010111: begin
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||||
data5b = 5'd23;
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disparity5b = 2'b01;
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end
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||||
6'b001100: begin
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data5b = 5'd24;
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disparity5b = 2'b11;
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||||
end
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||||
6'b110011: begin
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data5b = 5'd24;
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disparity5b = 2'b01;
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end
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||||
6'b011001: begin
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data5b = 5'd25;
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end
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6'b011010: begin
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data5b = 5'd26;
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end
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||||
6'b100100: begin
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||||
data5b = 5'd27;
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||||
disparity5b = 2'b11;
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||||
end
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||||
6'b011011: begin
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||||
data5b = 5'd27;
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||||
disparity5b = 2'b01;
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||||
end
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||||
6'b011100: begin
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||||
data5b = 5'd28;
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||||
end
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||||
6'b100010: begin
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||||
data5b = 5'd29;
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||||
disparity5b = 2'b11;
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||||
end
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||||
6'b011101: begin
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||||
data5b = 5'd29;
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||||
disparity5b = 2'b01;
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||||
end
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||||
6'b100001: begin
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||||
data5b = 5'd30;
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||||
disparity5b = 2'b11;
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||||
end
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||||
6'b011110: begin
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||||
data5b = 5'd30;
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||||
disparity5b = 2'b01;
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||||
end
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||||
6'b001010: begin
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||||
data5b = 5'd31;
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||||
disparity5b = 2'b11;
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||||
end
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||||
6'b110101: begin
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||||
data5b = 5'd31;
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||||
disparity5b = 2'b01;
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||||
end
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||||
default: begin
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||||
data5b = 5'd00;
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||||
notintable5b = 1'b1;
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||||
end
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||||
endcase
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||||
end
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||||
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||||
always @(*) begin
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||||
ignore3b = 1'b0;
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||||
case (in_char[9:6])
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4'b0010: begin
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||||
disparity3b = 2'b11;
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||||
end
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||||
4'b1101: begin
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||||
disparity3b = 2'b01;
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||||
end
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||||
4'b1100: begin
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||||
disparity3b = 2'b11;
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||||
ignore3b = 1'b1;
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||||
end
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||||
4'b0011: begin
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||||
disparity3b = 2'b01;
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||||
ignore3b = 1'b1;
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||||
end
|
||||
4'b0100: begin
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||||
disparity3b = 2'b11;
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||||
end
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||||
4'b1011: begin
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||||
disparity3b = 2'b01;
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||||
end
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||||
4'b1000: begin
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||||
disparity3b = 2'b11;
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||||
end
|
||||
4'b0111: begin
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||||
disparity3b = 2'b01;
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||||
end
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||||
4'b0001: begin
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||||
disparity3b = 2'b11;
|
||||
end
|
||||
4'b1110: begin
|
||||
disparity3b = 2'b01;
|
||||
end
|
||||
default: begin
|
||||
disparity3b = 2'b00;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
always @(*) begin
|
||||
notintable3b = 1'b0;
|
||||
|
||||
if (charisk == 1'b1) begin
|
||||
case (in_char[9:6] ^ {4{in_char[5]}})
|
||||
4'b1101: begin
|
||||
data3b = 3'd0;
|
||||
end
|
||||
4'b0011: begin
|
||||
data3b = 3'd3;
|
||||
end
|
||||
4'b1011: begin
|
||||
data3b = 3'd4;
|
||||
end
|
||||
4'b1010: begin
|
||||
data3b = 3'd5;
|
||||
end
|
||||
4'b1110: begin
|
||||
data3b = 3'd7;
|
||||
end
|
||||
default: begin
|
||||
data3b = 3'd0;
|
||||
notintable3b = 1'b1;
|
||||
end
|
||||
endcase
|
||||
end else begin
|
||||
case (in_char[9:6])
|
||||
4'b0010: begin
|
||||
data3b = 3'd0;
|
||||
end
|
||||
4'b1101: begin
|
||||
data3b = 3'd0;
|
||||
end
|
||||
4'b1001: begin
|
||||
data3b = 3'd1;
|
||||
end
|
||||
4'b1010: begin
|
||||
data3b = 3'd2;
|
||||
end
|
||||
4'b1100: begin
|
||||
data3b = 3'd3;
|
||||
end
|
||||
4'b0011: begin
|
||||
data3b = 3'd3;
|
||||
end
|
||||
4'b0100: begin
|
||||
data3b = 3'd4;
|
||||
end
|
||||
4'b1011: begin
|
||||
data3b = 3'd4;
|
||||
end
|
||||
4'b0101: begin
|
||||
data3b = 3'd5;
|
||||
end
|
||||
4'b0110: begin
|
||||
data3b = 3'd6;
|
||||
end
|
||||
4'b1000: begin
|
||||
data3b = 3'd7;
|
||||
notintable3b = in_char[5:4] == 2'b00;
|
||||
end
|
||||
4'b0111: begin
|
||||
data3b = 3'd7;
|
||||
notintable3b = in_char[5:4] == 2'b11;
|
||||
end
|
||||
4'b0001: begin
|
||||
data3b = 3'd7;
|
||||
notintable3b = in_char[5:4] != 2'b00;
|
||||
end
|
||||
4'b1110: begin
|
||||
data3b = 3'd7;
|
||||
notintable3b = in_char[5:4] != 2'b11;
|
||||
end
|
||||
default: begin
|
||||
data3b = 3'd0;
|
||||
notintable3b = 1'b1;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
always @(*) begin
|
||||
if (disparity3b == disparity5b && disparity3b != 2'b00) begin
|
||||
notintable_disparity = 1'b1;
|
||||
end else begin
|
||||
notintable_disparity = 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(*) begin
|
||||
total_disparity = (ignore3b ? 2'b00 : disparity3b) ^ (ignore5b ? 2'b00 : disparity5b);
|
||||
|
||||
if (total_disparity[0] == 1'b0 || out_notintable == 1'b1) begin
|
||||
out_disparity = in_disparity;
|
||||
out_disperr = 1'b0;
|
||||
end else if (total_disparity[1] == 1'b1) begin
|
||||
out_disparity = 1'b0;
|
||||
out_disperr = ~in_disparity;
|
||||
end else begin
|
||||
out_disparity = 1'b1;
|
||||
out_disperr = in_disparity;
|
||||
end
|
||||
end
|
||||
|
||||
assign out_char = {data3b,data5b};
|
||||
assign out_charisk = charisk;
|
||||
assign out_notintable = notintable5b | notintable3b | notintable_disparity;
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,155 @@
|
||||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact [email protected] for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module jesd204_pattern_align #(
|
||||
parameter DATA_PATH_WIDTH = 4
|
||||
) (
|
||||
input clk,
|
||||
input reset,
|
||||
|
||||
input patternalign_en,
|
||||
|
||||
input [DATA_PATH_WIDTH*10-1:0] in_data,
|
||||
output [DATA_PATH_WIDTH*10-1:0] out_data
|
||||
);
|
||||
|
||||
localparam [9:0] PATTERN_P = 10'b1010000011;
|
||||
localparam [9:0] PATTERN_N = 10'b0101111100;
|
||||
|
||||
reg [1:0] match_counter = 2'h0;
|
||||
reg pattern_sync = 1'b0;
|
||||
reg pattern_match = 1'b0;
|
||||
|
||||
reg [3:0] align = 4'h0;
|
||||
reg [1:0] cooldown = 2'h3;
|
||||
|
||||
reg [8:0] data_d1 = 9'h00;
|
||||
reg [DATA_PATH_WIDTH*10+2:0] aligned_data_stage1;
|
||||
reg [DATA_PATH_WIDTH*10-1:0] aligned_data_stage2;
|
||||
wire [(DATA_PATH_WIDTH+1)*10-2:0] full_data;
|
||||
|
||||
assign full_data = {in_data,data_d1};
|
||||
assign out_data = aligned_data_stage2;
|
||||
|
||||
/* 2-stage cascade of 3:1 and 4:1 muxes */
|
||||
|
||||
integer i;
|
||||
|
||||
always @(*) begin
|
||||
for (i = 0; i < DATA_PATH_WIDTH*10+3; i = i + 1) begin
|
||||
if (i < DATA_PATH_WIDTH*10+1) begin
|
||||
case (align[3:2])
|
||||
2'b00: aligned_data_stage1[i] = full_data[i];
|
||||
2'b01: aligned_data_stage1[i] = full_data[i+4];
|
||||
2'b10: aligned_data_stage1[i] = full_data[i+8];
|
||||
default: aligned_data_stage1[i] = 1'b0;
|
||||
endcase
|
||||
end else begin
|
||||
case (align[2])
|
||||
1'b0: aligned_data_stage1[i] = full_data[i];
|
||||
default: aligned_data_stage1[i] = full_data[i+4];
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
aligned_data_stage2 = aligned_data_stage1[align[1:0]+:DATA_PATH_WIDTH*10];
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
data_d1 <= in_data[DATA_PATH_WIDTH*10-9+:9];
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (out_data[9:0] == PATTERN_P || out_data[9:0] == PATTERN_N) begin
|
||||
pattern_match <= 1'b1;
|
||||
end else begin
|
||||
pattern_match <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (reset == 1'b1) begin
|
||||
cooldown <= 2'h3;
|
||||
align <= 4'h0;
|
||||
end else begin
|
||||
if (cooldown != 2'h0) begin
|
||||
cooldown <= cooldown - 1'b1;
|
||||
end else if (patternalign_en == 1'b1 && pattern_sync == 1'b0 &&
|
||||
pattern_match == 1'b0) begin
|
||||
cooldown <= 2'h3;
|
||||
if (align == 'h9) begin
|
||||
align <= 4'h0;
|
||||
end else begin
|
||||
align <= align + 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (reset == 1'b1) begin
|
||||
pattern_sync <= 1'b0;
|
||||
match_counter <= 2'h0;
|
||||
end else begin
|
||||
if (match_counter == 2'h0) begin
|
||||
pattern_sync <= 1'b0;
|
||||
end else if (match_counter == 2'h3) begin
|
||||
pattern_sync <= 1'b1;
|
||||
end
|
||||
|
||||
if (pattern_match == 1'b1) begin
|
||||
if (match_counter != 2'h3) begin
|
||||
match_counter <= match_counter + 1'b1;
|
||||
end
|
||||
end else begin
|
||||
if (match_counter != 2'h0) begin
|
||||
match_counter <= match_counter - 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,157 @@
|
||||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact [email protected] for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module jesd204_soft_pcs_rx #(
|
||||
parameter NUM_LANES = 1,
|
||||
parameter DATA_PATH_WIDTH = 4,
|
||||
parameter REGISTER_INPUTS = 0,
|
||||
parameter INVERT_INPUTS = 0
|
||||
) (
|
||||
input clk,
|
||||
input reset,
|
||||
|
||||
input patternalign_en,
|
||||
|
||||
input [NUM_LANES*DATA_PATH_WIDTH*10-1:0] data,
|
||||
|
||||
output reg [NUM_LANES*DATA_PATH_WIDTH*8-1:0] char,
|
||||
output reg [NUM_LANES*DATA_PATH_WIDTH-1:0] charisk,
|
||||
output reg [NUM_LANES*DATA_PATH_WIDTH-1:0] notintable,
|
||||
output reg [NUM_LANES*DATA_PATH_WIDTH-1:0] disperr
|
||||
);
|
||||
|
||||
localparam LANE_DATA_WIDTH = DATA_PATH_WIDTH * 10;
|
||||
|
||||
wire [NUM_LANES*LANE_DATA_WIDTH-1:0] data_aligned;
|
||||
|
||||
wire [NUM_LANES*DATA_PATH_WIDTH*8-1:0] char_s;
|
||||
wire [NUM_LANES*DATA_PATH_WIDTH-1:0] charisk_s;
|
||||
wire [NUM_LANES*DATA_PATH_WIDTH-1:0] notintable_s;
|
||||
wire [NUM_LANES*DATA_PATH_WIDTH-1:0] disperr_s;
|
||||
|
||||
reg [NUM_LANES-1:0] disparity = {NUM_LANES{1'b0}};
|
||||
wire [DATA_PATH_WIDTH:0] disparity_chain[0:NUM_LANES-1];
|
||||
|
||||
wire [NUM_LANES*DATA_PATH_WIDTH*10-1:0] data_s;
|
||||
wire patternalign_en_s;
|
||||
|
||||
always @(posedge clk) begin
|
||||
char <= char_s;
|
||||
charisk <= charisk_s;
|
||||
notintable <= notintable_s;
|
||||
disperr <= disperr_s;
|
||||
end
|
||||
|
||||
generate
|
||||
genvar lane;
|
||||
genvar i;
|
||||
if (REGISTER_INPUTS > 0) begin
|
||||
reg patternalign_en_r;
|
||||
reg [NUM_LANES*DATA_PATH_WIDTH*10-1:0] data_r;
|
||||
always @(posedge clk) begin
|
||||
patternalign_en_r <= patternalign_en;
|
||||
data_r <= data;
|
||||
end
|
||||
assign patternalign_en_s = patternalign_en_r;
|
||||
assign data_s = data_r;
|
||||
end else begin
|
||||
assign patternalign_en_s = patternalign_en;
|
||||
assign data_s = data;
|
||||
end
|
||||
|
||||
for (lane = 0; lane < NUM_LANES; lane = lane + 1) begin: gen_lane
|
||||
|
||||
jesd204_pattern_align #(
|
||||
.DATA_PATH_WIDTH(DATA_PATH_WIDTH)
|
||||
) i_pattern_align (
|
||||
.clk(clk),
|
||||
.reset(reset),
|
||||
|
||||
.patternalign_en(patternalign_en_s),
|
||||
.in_data(data_s[LANE_DATA_WIDTH*lane+:LANE_DATA_WIDTH]),
|
||||
.out_data(data_aligned[LANE_DATA_WIDTH*lane+:LANE_DATA_WIDTH])
|
||||
);
|
||||
|
||||
assign disparity_chain[lane][0] = disparity[lane];
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (reset == 1'b1) begin
|
||||
disparity[lane] <= 1'b0;
|
||||
end else begin
|
||||
disparity[lane] <= disparity_chain[lane][DATA_PATH_WIDTH];
|
||||
end
|
||||
end
|
||||
|
||||
for (i = 0; i < DATA_PATH_WIDTH; i = i + 1) begin: gen_dpw
|
||||
localparam j = DATA_PATH_WIDTH * lane + i;
|
||||
wire [9:0] in_char;
|
||||
if (REGISTER_INPUTS > 1) begin
|
||||
reg [9:0] in_char_r = 10'b0;
|
||||
always @(posedge clk) begin
|
||||
in_char_r <= INVERT_INPUTS ? ~data_aligned[j*10+:10] :
|
||||
data_aligned[j*10+:10];
|
||||
end
|
||||
assign in_char = in_char_r;
|
||||
end else begin
|
||||
assign in_char = INVERT_INPUTS ? ~data_aligned[j*10+:10] :
|
||||
data_aligned[j*10+:10];
|
||||
end
|
||||
|
||||
jesd204_8b10b_decoder i_dec (
|
||||
.in_char(in_char),
|
||||
.out_char(char_s[j*8+:8]),
|
||||
.out_charisk(charisk_s[j]),
|
||||
.out_notintable(notintable_s[j]),
|
||||
.out_disperr(disperr_s[j]),
|
||||
|
||||
.in_disparity(disparity_chain[lane][i]),
|
||||
.out_disparity(disparity_chain[lane][i+1])
|
||||
);
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,92 @@
|
||||
#
|
||||
# The ADI JESD204 Core is released under the following license, which is
|
||||
# different than all other HDL cores in this repository.
|
||||
#
|
||||
# Please read this, and understand the freedoms and responsibilities you have
|
||||
# by using this source code/core.
|
||||
#
|
||||
# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
#
|
||||
# This core is free software, you can use run, copy, study, change, ask
|
||||
# questions about and improve this core. Distribution of source, or resulting
|
||||
# binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
# source of the entire project (excluding the system libraries provide by the
|
||||
# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
# License version 2 as published by the Free Software Foundation.
|
||||
#
|
||||
# This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License version 2
|
||||
# along with this source code, and binary. If not, see
|
||||
# <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
# available under terms different than the General Public License. (e.g. they
|
||||
# do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
# core with any corresponding source code.) For these alternate terms you must
|
||||
# purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
# interested in such a license should contact [email protected] for
|
||||
# more information. This commercial license is sub-licensable (if you purchase
|
||||
# chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
# purchase a JESD204 license, end users of your product will also have a
|
||||
# license to use this core in a commercial setting without releasing their
|
||||
# source code).
|
||||
#
|
||||
# In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
# or publication in which you use this JESD204 HDL core. (You are not required
|
||||
# to do so; it is up to your common sense to decide whether you want to comply
|
||||
# with this request or not.) For general publications, we suggest referencing :
|
||||
# “The design and implementation of the JESD204 HDL Core used in this project
|
||||
# is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
#
|
||||
|
||||
package require qsys
|
||||
|
||||
source ../../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_intel.tcl
|
||||
|
||||
ad_ip_create jesd204_soft_pcs_rx "ADI JESD204 Transmit Soft PCS"
|
||||
|
||||
ad_ip_parameter REGISTER_INPUTS INTEGER 0
|
||||
ad_ip_parameter INVERT_INPUTS INTEGER 0
|
||||
|
||||
set_module_property INTERNAL true
|
||||
|
||||
# files
|
||||
|
||||
ad_ip_files jesd204_soft_pcs_rx [list \
|
||||
jesd204_soft_pcs_rx.v \
|
||||
jesd204_pattern_align.v \
|
||||
jesd204_8b10b_decoder.v \
|
||||
]
|
||||
|
||||
# clock
|
||||
|
||||
add_interface clock clock end
|
||||
add_interface_port clock clk clk Input 1
|
||||
|
||||
# reset
|
||||
|
||||
add_interface reset reset end
|
||||
set_interface_property reset associatedClock clock
|
||||
set_interface_property reset synchronousEdges DEASSERT
|
||||
|
||||
add_interface_port reset reset reset Input 1
|
||||
|
||||
# interfaces
|
||||
|
||||
add_interface rx_phy conduit start
|
||||
#set_interface_property rx_phy associatedClock clock
|
||||
#set_interface_property rx_phy associatedReset reset
|
||||
add_interface_port rx_phy char char Output 32
|
||||
add_interface_port rx_phy charisk charisk Output 4
|
||||
add_interface_port rx_phy disperr disperr Output 4
|
||||
add_interface_port rx_phy notintable notintable Output 4
|
||||
add_interface_port rx_phy patternalign_en patternalign_en Input 1
|
||||
|
||||
add_interface rx_raw_data conduit end
|
||||
#set_interface_property rx_raw_data associatedClock clock
|
||||
#set_interface_property rx_raw_data associatedReset reset
|
||||
add_interface_port rx_raw_data data raw_data Input 40
|
||||
Reference in New Issue
Block a user