Archived
first commit after restructuring
This commit is contained in:
@@ -0,0 +1,41 @@
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####################################################################################
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## Copyright 2018(c) Analog Devices, Inc.
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## Auto-generated, do not modify!
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####################################################################################
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LIBRARY_NAME := jesd204_tx
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GENERIC_DEPS += jesd204_tx.v
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GENERIC_DEPS += jesd204_tx_ctrl.v
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GENERIC_DEPS += jesd204_tx_lane.v
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XILINX_DEPS += jesd204_tx_constr.ttcl
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XILINX_DEPS += jesd204_tx_header.v
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XILINX_DEPS += jesd204_tx_ip.tcl
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XILINX_DEPS += jesd204_tx_lane_64b.v
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XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_cfg.xml
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XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_cfg_rtl.xml
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XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_ctrl.xml
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XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_ctrl_rtl.xml
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XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_event.xml
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XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_event_rtl.xml
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XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_ilas_config.xml
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XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_ilas_config_rtl.xml
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XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_status.xml
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XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_status_rtl.xml
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XILINX_LIB_DEPS += jesd204/jesd204_common
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XILINX_LIB_DEPS += util_cdc
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XILINX_INTERFACE_DEPS += jesd204/interfaces
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INTEL_DEPS += ../../util_cdc/sync_bits.v
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INTEL_DEPS += ../jesd204_common/jesd204_eof_generator.v
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INTEL_DEPS += ../jesd204_common/jesd204_lmfc.v
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INTEL_DEPS += ../jesd204_common/jesd204_scrambler.v
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INTEL_DEPS += ../jesd204_common/pipeline_stage.v
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INTEL_DEPS += jesd204_tx_constr.sdc
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INTEL_DEPS += jesd204_tx_hw.tcl
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include ../../scripts/library.mk
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,2 @@
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# This file is automatically written. Do not modify.
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proc gen_USERPARAMETER_DATA_PATH_WIDTH_VALUE {LINK_MODE } {expr $LINK_MODE*4}
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@@ -0,0 +1,3 @@
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version:1
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6d6f64655f636f756e7465727c42617463684d6f6465:1
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eof:
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@@ -0,0 +1,6 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
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||||
<!-- -->
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||||
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
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||||
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||||
<labtools version="1" minor="0"/>
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@@ -0,0 +1,323 @@
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//
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||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
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||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact [email protected] for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
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||||
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||||
`timescale 1ns/100ps
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module jesd204_tx #(
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parameter NUM_LANES = 1,
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parameter NUM_LINKS = 1,
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parameter NUM_OUTPUT_PIPELINE = 0,
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parameter LINK_MODE = 1, // 2 - 64B/66B; 1 - 8B/10B
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/* Only 4 is supported at the moment for 8b/10b and 8 for 64b */
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parameter DATA_PATH_WIDTH = LINK_MODE[1] ? 8 : 4
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) (
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input clk,
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input reset,
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output [DATA_PATH_WIDTH*8*NUM_LANES-1:0] phy_data,
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output [DATA_PATH_WIDTH*NUM_LANES-1:0] phy_charisk,
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output [2*NUM_LANES-1:0] phy_header,
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input sysref,
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output lmfc_edge,
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output lmfc_clk,
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input [NUM_LINKS-1:0] sync,
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input [DATA_PATH_WIDTH*8*NUM_LANES-1:0] tx_data,
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output tx_ready,
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input tx_valid,
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input [NUM_LANES-1:0] cfg_lanes_disable,
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input [NUM_LINKS-1:0] cfg_links_disable,
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input [7:0] cfg_beats_per_multiframe,
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input [7:0] cfg_octets_per_frame,
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input [7:0] cfg_lmfc_offset,
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input cfg_sysref_oneshot,
|
||||
input cfg_sysref_disable,
|
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input cfg_continuous_cgs,
|
||||
input cfg_continuous_ilas,
|
||||
input cfg_skip_ilas,
|
||||
input [7:0] cfg_mframes_per_ilas,
|
||||
input cfg_disable_char_replacement,
|
||||
input cfg_disable_scrambler,
|
||||
|
||||
output ilas_config_rd,
|
||||
output [1:0] ilas_config_addr,
|
||||
input [32*NUM_LANES-1:0] ilas_config_data,
|
||||
|
||||
input ctrl_manual_sync_request,
|
||||
|
||||
output event_sysref_edge,
|
||||
output event_sysref_alignment_error,
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||||
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||||
output [NUM_LINKS-1:0] status_sync,
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||||
output [1:0] status_state
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||||
);
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||||
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||||
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||||
localparam MAX_OCTETS_PER_FRAME = 8;
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localparam MAX_OCTETS_PER_MULTIFRAME =
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(MAX_OCTETS_PER_FRAME * 32) > 1024 ? 1024 : (MAX_OCTETS_PER_FRAME * 32);
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localparam MAX_BEATS_PER_MULTIFRAME = MAX_OCTETS_PER_MULTIFRAME / DATA_PATH_WIDTH;
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||||
localparam LMFC_COUNTER_WIDTH = MAX_BEATS_PER_MULTIFRAME > 256 ? 9 :
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MAX_BEATS_PER_MULTIFRAME > 128 ? 8 :
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||||
MAX_BEATS_PER_MULTIFRAME > 64 ? 7 :
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||||
MAX_BEATS_PER_MULTIFRAME > 32 ? 6 :
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||||
MAX_BEATS_PER_MULTIFRAME > 16 ? 5 :
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||||
MAX_BEATS_PER_MULTIFRAME > 8 ? 4 :
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MAX_BEATS_PER_MULTIFRAME > 4 ? 3 :
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MAX_BEATS_PER_MULTIFRAME > 2 ? 2 : 1;
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localparam DW = DATA_PATH_WIDTH * 8 * NUM_LANES;
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localparam CW = DATA_PATH_WIDTH * NUM_LANES;
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localparam HW = 2 * NUM_LANES;
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||||
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||||
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wire [DW-1:0] phy_data_r;
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wire [CW-1:0] phy_charisk_r;
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wire [HW-1:0] phy_header_r;
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wire lmc_edge;
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wire lmc_quarter_edge;
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wire eoemb;
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jesd204_lmfc i_lmfc (
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.clk(clk),
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.reset(reset),
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.cfg_beats_per_multiframe(cfg_beats_per_multiframe),
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||||
.cfg_lmfc_offset(cfg_lmfc_offset),
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.cfg_sysref_oneshot(cfg_sysref_oneshot),
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.cfg_sysref_disable(cfg_sysref_disable),
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.sysref(sysref),
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.sysref_edge(event_sysref_edge),
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.sysref_alignment_error(event_sysref_alignment_error),
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.lmfc_edge(lmfc_edge),
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||||
.lmfc_clk(lmfc_clk),
|
||||
.lmfc_counter(),
|
||||
.lmc_edge(lmc_edge),
|
||||
.lmc_quarter_edge(lmc_quarter_edge),
|
||||
.eoemb(eoemb)
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||||
);
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generate
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genvar i;
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if (LINK_MODE[0] == 1) begin : mode_8b10b
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wire eof_gen_reset;
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wire [DATA_PATH_WIDTH-1:0] eof;
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wire eomf;
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wire [NUM_LANES-1:0] lane_cgs_enable;
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wire [DW-1:0] ilas_data;
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wire [DATA_PATH_WIDTH-1:0] ilas_charisk;
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wire cfg_generate_eomf = 1'b1;
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||||
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||||
jesd204_tx_ctrl #(
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.NUM_LANES(NUM_LANES),
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.NUM_LINKS(NUM_LINKS),
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.DATA_PATH_WIDTH(DATA_PATH_WIDTH)
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) i_tx_ctrl (
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||||
.clk(clk),
|
||||
.reset(reset),
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||||
|
||||
.sync(sync),
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||||
.lmfc_edge(lmfc_edge),
|
||||
|
||||
.lane_cgs_enable(lane_cgs_enable),
|
||||
.eof_reset(eof_gen_reset),
|
||||
|
||||
.tx_ready(tx_ready),
|
||||
|
||||
.ilas_data(ilas_data),
|
||||
.ilas_charisk(ilas_charisk),
|
||||
|
||||
.ilas_config_addr(ilas_config_addr),
|
||||
.ilas_config_rd(ilas_config_rd),
|
||||
.ilas_config_data(ilas_config_data),
|
||||
|
||||
.cfg_lanes_disable(cfg_lanes_disable),
|
||||
.cfg_links_disable(cfg_links_disable),
|
||||
.cfg_continuous_cgs(cfg_continuous_cgs),
|
||||
.cfg_continuous_ilas(cfg_continuous_ilas),
|
||||
.cfg_skip_ilas(cfg_skip_ilas),
|
||||
.cfg_mframes_per_ilas(cfg_mframes_per_ilas),
|
||||
.cfg_disable_char_replacement(cfg_disable_char_replacement),
|
||||
|
||||
.ctrl_manual_sync_request(ctrl_manual_sync_request),
|
||||
|
||||
.status_sync(status_sync),
|
||||
.status_state(status_state)
|
||||
);
|
||||
|
||||
jesd204_eof_generator #(
|
||||
.DATA_PATH_WIDTH(DATA_PATH_WIDTH),
|
||||
.MAX_OCTETS_PER_FRAME(MAX_OCTETS_PER_FRAME)
|
||||
) i_eof_gen (
|
||||
.clk(clk),
|
||||
.reset(eof_gen_reset),
|
||||
|
||||
.cfg_octets_per_frame(cfg_octets_per_frame),
|
||||
.cfg_generate_eomf(cfg_generate_eomf),
|
||||
|
||||
.lmfc_edge(lmfc_edge),
|
||||
.sof(),
|
||||
.eof(eof),
|
||||
.eomf(eomf)
|
||||
);
|
||||
|
||||
|
||||
|
||||
for (i = 0; i < NUM_LANES; i = i + 1) begin: gen_lane
|
||||
|
||||
localparam D_START = i * DATA_PATH_WIDTH*8;
|
||||
localparam D_STOP = D_START + DATA_PATH_WIDTH*8-1;
|
||||
localparam C_START = i * DATA_PATH_WIDTH;
|
||||
localparam C_STOP = C_START + DATA_PATH_WIDTH-1;
|
||||
|
||||
jesd204_tx_lane #(
|
||||
.DATA_PATH_WIDTH(DATA_PATH_WIDTH)
|
||||
) i_lane (
|
||||
.clk(clk),
|
||||
|
||||
.eof(eof),
|
||||
.eomf(eomf),
|
||||
|
||||
.cgs_enable(lane_cgs_enable[i]),
|
||||
|
||||
.ilas_data(ilas_data[D_STOP:D_START]),
|
||||
.ilas_charisk(ilas_charisk),
|
||||
|
||||
.tx_data(tx_data[D_STOP:D_START]),
|
||||
.tx_ready(tx_ready),
|
||||
|
||||
.phy_data(phy_data_r[D_STOP:D_START]),
|
||||
.phy_charisk(phy_charisk_r[C_STOP:C_START]),
|
||||
|
||||
.cfg_disable_scrambler(cfg_disable_scrambler)
|
||||
);
|
||||
end
|
||||
|
||||
assign phy_header_r = 'h0;
|
||||
|
||||
end
|
||||
|
||||
if (LINK_MODE[1] == 1) begin : mode_64b66b
|
||||
reg tx_ready_loc;
|
||||
|
||||
for (i = 0; i < NUM_LANES; i = i + 1) begin: gen_lane
|
||||
localparam D_START = i * DATA_PATH_WIDTH*8;
|
||||
localparam D_STOP = D_START + DATA_PATH_WIDTH*8-1;
|
||||
localparam H_START = i * 2;
|
||||
localparam H_STOP = H_START + 2 -1;
|
||||
jesd204_tx_lane_64b i_lane(
|
||||
.clk(clk),
|
||||
.reset(reset),
|
||||
|
||||
.tx_data(tx_data[D_STOP:D_START]),
|
||||
.tx_ready(tx_ready_loc),
|
||||
|
||||
.phy_data(phy_data_r[D_STOP:D_START]),
|
||||
.phy_header(phy_header_r[H_STOP:H_START]),
|
||||
|
||||
.lmc_edge(lmc_edge),
|
||||
.lmc_quarter_edge(lmc_quarter_edge),
|
||||
.eoemb(eoemb),
|
||||
|
||||
.cfg_disable_scrambler(cfg_disable_scrambler),
|
||||
.cfg_header_mode(2'b0),
|
||||
.cfg_lane_disable(cfg_lanes_disable[i])
|
||||
);
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (reset) begin
|
||||
tx_ready_loc <= 1'b0;
|
||||
end else if (lmfc_edge) begin
|
||||
tx_ready_loc <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
assign tx_ready = tx_ready_loc;
|
||||
// Link considered in DATA phase when SYSREF received and LEMC clock started
|
||||
// running
|
||||
assign status_state = {2{tx_ready_loc}};
|
||||
|
||||
|
||||
assign phy_charisk_r = 'h0;
|
||||
assign ilas_config_rd = 'h0;
|
||||
assign ilas_config_addr = 'h0;
|
||||
assign status_sync = 'h0;
|
||||
|
||||
end
|
||||
|
||||
endgenerate
|
||||
|
||||
pipeline_stage #(
|
||||
.WIDTH(CW + DW + HW),
|
||||
.REGISTERED(NUM_OUTPUT_PIPELINE)
|
||||
) i_output_pipeline_stage (
|
||||
.clk(clk),
|
||||
.in({
|
||||
phy_data_r,
|
||||
phy_charisk_r,
|
||||
phy_header_r
|
||||
}),
|
||||
.out({
|
||||
phy_data,
|
||||
phy_charisk,
|
||||
phy_header
|
||||
})
|
||||
);
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,405 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Version="7" Minor="40" Path="/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/jesd204/jesd204_tx/jesd204_tx.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="a17c8f805f934b9eb28ce4265b03b7aa"/>
|
||||
<Option Name="Part" Val="xc7vx485tffg1157-1"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="BoardPart" Val=""/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../../library"/>
|
||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../../../ghdl/library"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="DSAVendor" Val="xilinx"/>
|
||||
<Option Name="DSANumComputeUnits" Val="60"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="0"/>
|
||||
<Option Name="WTModelSimExportSim" Val="0"/>
|
||||
<Option Name="WTQuestaExportSim" Val="0"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="0"/>
|
||||
<Option Name="WTRivieraExportSim" Val="0"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
<Option Name="SimTypes" Val="bfm"/>
|
||||
<Option Name="SimTypes" Val="tlm"/>
|
||||
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="31">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/jesd204_tx_ctrl.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/jesd204_tx_header.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/jesd204_tx_lane.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/jesd204_tx_lane_64b.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/jesd204_tx.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/jesd204_tx_constr.ttcl"/>
|
||||
<File Path="$PPRDIR/component.xml">
|
||||
<FileInfo SFType="IPXACT"/>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="jesd204_tx"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="IES">
|
||||
<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Xcelium">
|
||||
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="VCS">
|
||||
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="10">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Vivado 12-1790"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="1"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="Evaluation"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="features"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="should"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="NOT"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="be"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="used"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="in"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="production"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="systems."/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Place 30-73"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="10"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="axi_spi"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val=""/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="11"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1343"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="2"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1306"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="3"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="ERROR"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1276"/>
|
||||
<MsgAttr Name="Severity" Val="CRITICAL WARNING"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="4"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-3656"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="5"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-4623"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="6"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-459"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="7"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Synth 8-3331"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="8"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Designutils 20-3303"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="9"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="HDPYFinalizeIO"/>
|
||||
</MsgRule>
|
||||
<Board/>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
<BootPmcSettings Version="1" Minor="0">
|
||||
<Parameters>
|
||||
<Parameter Name="PMC_CDO.ATTRS.LOADADDR" Value="" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_FB_CLK" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_FREQ" Value="300" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_BUS_WIDTH" Value="x1" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_DATA_MODE" Value="Single" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_FREQ" Value="200" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_SLOT_TYPE" Value="SD 2.0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_FREQ" Value="200" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_SLOT_TYPE" Value="SD 2.0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSPI_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSPI_FREQ" Value="300" Type="string"/>
|
||||
<Parameter Name="BOOT.USB_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SMAP_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SMAP_DATA_WIDTH" Value="32 Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSC_FREQ" Value="33.333" Type="string"/>
|
||||
<Parameter Name="BOOT.SECONDARY.PCIE_ENABLE" Value="0" Type="string"/>
|
||||
</Parameters>
|
||||
</BootPmcSettings>
|
||||
</Project>
|
||||
@@ -0,0 +1,50 @@
|
||||
#
|
||||
# The ADI JESD204 Core is released under the following license, which is
|
||||
# different than all other HDL cores in this repository.
|
||||
#
|
||||
# Please read this, and understand the freedoms and responsibilities you have
|
||||
# by using this source code/core.
|
||||
#
|
||||
# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
#
|
||||
# This core is free software, you can use run, copy, study, change, ask
|
||||
# questions about and improve this core. Distribution of source, or resulting
|
||||
# binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
# source of the entire project (excluding the system libraries provide by the
|
||||
# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
# License version 2 as published by the Free Software Foundation.
|
||||
#
|
||||
# This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License version 2
|
||||
# along with this source code, and binary. If not, see
|
||||
# <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
# available under terms different than the General Public License. (e.g. they
|
||||
# do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
# core with any corresponding source code.) For these alternate terms you must
|
||||
# purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
# interested in such a license should contact [email protected] for
|
||||
# more information. This commercial license is sub-licensable (if you purchase
|
||||
# chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
# purchase a JESD204 license, end users of your product will also have a
|
||||
# license to use this core in a commercial setting without releasing their
|
||||
# source code).
|
||||
#
|
||||
# In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
# or publication in which you use this JESD204 HDL core. (You are not required
|
||||
# to do so; it is up to your common sense to decide whether you want to comply
|
||||
# with this request or not.) For general publications, we suggest referencing :
|
||||
# “The design and implementation of the JESD204 HDL Core used in this project
|
||||
# is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
#
|
||||
|
||||
set script_dir [file dirname [info script]]
|
||||
|
||||
source "$script_dir/util_cdc_constr.tcl"
|
||||
|
||||
# SYNC~ is a asynchronous interface
|
||||
util_cdc_sync_bits_constr {*|jesd204_tx_ctrl:i_tx_ctrl|sync_bits:i_cdc_sync}
|
||||
@@ -0,0 +1,58 @@
|
||||
#
|
||||
# The ADI JESD204 Core is released under the following license, which is
|
||||
# different than all other HDL cores in this repository.
|
||||
#
|
||||
# Please read this, and understand the freedoms and responsibilities you have
|
||||
# by using this source code/core.
|
||||
#
|
||||
# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
#
|
||||
# This core is free software, you can use run, copy, study, change, ask
|
||||
# questions about and improve this core. Distribution of source, or resulting
|
||||
# binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
# source of the entire project (excluding the system libraries provide by the
|
||||
# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
# License version 2 as published by the Free Software Foundation.
|
||||
#
|
||||
# This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License version 2
|
||||
# along with this source code, and binary. If not, see
|
||||
# <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
# available under terms different than the General Public License. (e.g. they
|
||||
# do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
# core with any corresponding source code.) For these alternate terms you must
|
||||
# purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
# interested in such a license should contact [email protected] for
|
||||
# more information. This commercial license is sub-licensable (if you purchase
|
||||
# chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
# purchase a JESD204 license, end users of your product will also have a
|
||||
# license to use this core in a commercial setting without releasing their
|
||||
# source code).
|
||||
#
|
||||
# In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
# or publication in which you use this JESD204 HDL core. (You are not required
|
||||
# to do so; it is up to your common sense to decide whether you want to comply
|
||||
# with this request or not.) For general publications, we suggest referencing :
|
||||
# “The design and implementation of the JESD204 HDL Core used in this project
|
||||
# is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
#
|
||||
<: set ComponentName [getComponentNameString] :>
|
||||
<: setOutputDirectory "./" :>
|
||||
<: setFileName [ttcl_add $ComponentName "_constr"] :>
|
||||
<: setFileExtension ".xdc" :>
|
||||
<: setFileProcessingOrder late :>
|
||||
<: set sysref_iob [get_property PARAM_VALUE.SYSREF_IOB] :>
|
||||
|
||||
set_property ASYNC_REG TRUE \
|
||||
[get_cells {i_lmfc/sysref_d1_reg}] \
|
||||
[get_cells {i_lmfc/sysref_d2_reg}]
|
||||
|
||||
# Make sure that the device clock to sysref skew is at least somewhat
|
||||
# predictable
|
||||
set_property IOB <=: $sysref_iob :> \
|
||||
[get_cells {i_lmfc/sysref_r_reg}]
|
||||
@@ -0,0 +1,279 @@
|
||||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact [email protected] for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module jesd204_tx_ctrl #(
|
||||
parameter NUM_LANES = 1,
|
||||
parameter NUM_LINKS = 1,
|
||||
parameter DATA_PATH_WIDTH = 4
|
||||
) (
|
||||
input clk,
|
||||
input reset,
|
||||
|
||||
input [NUM_LINKS-1:0] sync,
|
||||
input lmfc_edge,
|
||||
|
||||
output reg [NUM_LANES-1:0] lane_cgs_enable,
|
||||
output reg eof_reset,
|
||||
|
||||
output reg tx_ready,
|
||||
|
||||
output reg [DATA_PATH_WIDTH*8*NUM_LANES-1:0] ilas_data,
|
||||
output reg [DATA_PATH_WIDTH-1:0] ilas_charisk,
|
||||
|
||||
output reg [1:0] ilas_config_addr,
|
||||
output reg ilas_config_rd,
|
||||
input [DATA_PATH_WIDTH*8*NUM_LANES-1:0] ilas_config_data,
|
||||
|
||||
input [NUM_LANES-1:0] cfg_lanes_disable,
|
||||
input [NUM_LINKS-1:0] cfg_links_disable,
|
||||
input cfg_continuous_cgs,
|
||||
input cfg_continuous_ilas,
|
||||
input cfg_skip_ilas,
|
||||
input [7:0] cfg_mframes_per_ilas,
|
||||
input cfg_disable_char_replacement,
|
||||
|
||||
input ctrl_manual_sync_request,
|
||||
|
||||
output [NUM_LINKS-1:0] status_sync,
|
||||
output reg [1:0] status_state
|
||||
);
|
||||
|
||||
reg lmfc_edge_d1 = 1'b0;
|
||||
reg lmfc_edge_d2 = 1'b0;
|
||||
reg ilas_reset = 1'b1;
|
||||
reg ilas_data_reset = 1'b1;
|
||||
reg sync_request = 1'b0;
|
||||
reg sync_request_received = 1'b0;
|
||||
reg [7:0] mframe_counter = 'h00;
|
||||
reg [5:0] ilas_counter = 'h00;
|
||||
reg ilas_config_rd_d1 = 1'b1;
|
||||
reg last_ilas_mframe = 1'b0;
|
||||
reg cgs_enable = 1'b1;
|
||||
|
||||
wire [NUM_LINKS-1:0] status_sync_masked;
|
||||
|
||||
sync_bits #(
|
||||
.NUM_OF_BITS (NUM_LINKS))
|
||||
i_cdc_sync (
|
||||
.in_bits(sync),
|
||||
.out_clk(clk),
|
||||
.out_resetn(1'b1),
|
||||
.out_bits(status_sync)
|
||||
);
|
||||
assign status_sync_masked = status_sync | cfg_links_disable;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (reset == 1'b1) begin
|
||||
sync_request <= {NUM_LINKS{1'b0}};
|
||||
end else begin
|
||||
/* TODO: SYNC must be asserted at least 4 frames before interpreted as a
|
||||
* sync request and the /K28.5/ symbol generation has lasted for at
|
||||
* least 1 frame + 9 octets */
|
||||
if (cfg_continuous_cgs == 1'b1) begin
|
||||
sync_request <= 1'b1;
|
||||
end else begin
|
||||
sync_request <= ~(&status_sync_masked) | ctrl_manual_sync_request;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (sync_request == 1'b0 && sync_request_received == 1'b1) begin
|
||||
lmfc_edge_d1 <= lmfc_edge;
|
||||
lmfc_edge_d2 <= lmfc_edge_d1;
|
||||
end else begin
|
||||
lmfc_edge_d1 <= 1'b0;
|
||||
lmfc_edge_d2 <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (reset == 1'b1) begin
|
||||
sync_request_received <= 1'b0;
|
||||
end else if (sync_request == 1'b1) begin
|
||||
sync_request_received <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (cfg_skip_ilas == 1'b1 ||
|
||||
mframe_counter == cfg_mframes_per_ilas) begin
|
||||
last_ilas_mframe <= 1'b1;
|
||||
end else begin
|
||||
last_ilas_mframe <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
localparam STATE_WAIT = 2'b00;
|
||||
localparam STATE_CGS = 2'b01;
|
||||
localparam STATE_ILAS = 2'b10;
|
||||
localparam STATE_DATA = 2'b11;
|
||||
|
||||
/* Timeline
|
||||
*
|
||||
* #1 lmfc_edge == 1, ilas_reset update
|
||||
* #2 eof_reset update
|
||||
* #3 {lane_,}cgs_enable, tx_ready update
|
||||
*
|
||||
* One multi-frame should at least be 3 clock cycles (TBD 64-bit data path)
|
||||
*/
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (sync_request == 1'b1 || reset == 1'b1) begin
|
||||
cgs_enable <= 1'b1;
|
||||
lane_cgs_enable <= {NUM_LANES{1'b1}};
|
||||
tx_ready <= 1'b0;
|
||||
eof_reset <= 1'b1;
|
||||
ilas_reset <= 1'b1;
|
||||
ilas_data_reset <= 1'b1;
|
||||
|
||||
if (sync_request_received == 1'b0) begin
|
||||
status_state <= STATE_WAIT;
|
||||
end else begin
|
||||
status_state <= STATE_CGS;
|
||||
end
|
||||
end else if (sync_request_received == 1'b1) begin
|
||||
if (lmfc_edge == 1'b1 && last_ilas_mframe == 1'b1) begin
|
||||
ilas_reset <= 1'b1;
|
||||
status_state <= STATE_DATA;
|
||||
end else if (lmfc_edge_d1 == 1'b1 && (cfg_continuous_ilas == 1'b1 ||
|
||||
cgs_enable == 1'b1)) begin
|
||||
ilas_reset <= 1'b0;
|
||||
status_state <= STATE_ILAS;
|
||||
end
|
||||
|
||||
if (lmfc_edge_d1 == 1'b1) begin
|
||||
if (last_ilas_mframe == 1'b1 && cfg_continuous_ilas == 1'b0) begin
|
||||
eof_reset <= cfg_disable_char_replacement;
|
||||
ilas_data_reset <= 1'b1;
|
||||
end else if (cgs_enable == 1'b1) begin
|
||||
ilas_data_reset <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
if (lmfc_edge_d2 == 1'b1) begin
|
||||
lane_cgs_enable <= cfg_lanes_disable;
|
||||
cgs_enable <= 1'b0;
|
||||
if (last_ilas_mframe == 1'b1 && cfg_continuous_ilas == 1'b0) begin
|
||||
tx_ready <= 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (ilas_reset == 1'b1) begin
|
||||
mframe_counter <= 'h00;
|
||||
end else if (lmfc_edge_d1 == 1'b1) begin
|
||||
mframe_counter <= mframe_counter + 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (ilas_reset == 1'b1) begin
|
||||
ilas_config_rd <= 1'b0;
|
||||
end else if (mframe_counter == 'h00 && lmfc_edge == 1'b1) begin
|
||||
ilas_config_rd <= 1'b1;
|
||||
end else if (ilas_config_addr == 'h3) begin
|
||||
ilas_config_rd <= 1'b0;
|
||||
end
|
||||
ilas_config_rd_d1 <= ilas_config_rd;
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (ilas_config_rd == 1'b0) begin
|
||||
ilas_config_addr <= 'h00;
|
||||
end else begin
|
||||
ilas_config_addr <= ilas_config_addr + 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (ilas_reset == 1'b1) begin
|
||||
ilas_counter <= 'h00;
|
||||
end else begin
|
||||
ilas_counter <= ilas_counter + 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
wire [31:0] ilas_default_data = {
|
||||
ilas_counter,2'h3,
|
||||
ilas_counter,2'h2,
|
||||
ilas_counter,2'h1,
|
||||
ilas_counter,2'h0
|
||||
};
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (ilas_data_reset == 1'b1) begin
|
||||
ilas_data <= {NUM_LANES{32'h00}};
|
||||
ilas_charisk <= 4'b0000;
|
||||
end else begin
|
||||
if (ilas_config_rd_d1 == 1'b1) begin
|
||||
case (ilas_config_addr)
|
||||
2'h1: begin
|
||||
ilas_data <= (ilas_config_data & {NUM_LANES{32'hffff0000}}) |
|
||||
{NUM_LANES{16'h00,8'h9c,8'h1c}}; // /Q/ /R/
|
||||
ilas_charisk <= 4'b0011;
|
||||
end
|
||||
default: begin
|
||||
ilas_data <= ilas_config_data;
|
||||
ilas_charisk <= 4'b0000;
|
||||
end
|
||||
endcase
|
||||
end else if (lmfc_edge_d2 == 1'b1) begin
|
||||
ilas_data <= {NUM_LANES{ilas_default_data[31:8],8'h1c}}; // /R/
|
||||
ilas_charisk <= 4'b0001;
|
||||
end else if (lmfc_edge_d1 == 1'b1) begin
|
||||
ilas_data <= {NUM_LANES{8'h7c,ilas_default_data[23:0]}}; // /A/
|
||||
ilas_charisk <= 4'b1000;
|
||||
end else begin
|
||||
ilas_data <= {NUM_LANES{ilas_default_data}};
|
||||
ilas_charisk <= 4'b0000;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,108 @@
|
||||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact [email protected] for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module jesd204_tx_header (
|
||||
input clk,
|
||||
input reset,
|
||||
|
||||
input [1:0] cfg_header_mode,
|
||||
|
||||
input lmc_edge,
|
||||
input lmc_quarter_edge,
|
||||
|
||||
// Header content to be sent must be valid during lmc_edge
|
||||
input eoemb,
|
||||
input [2:0] crc3,
|
||||
input [11:0] crc12,
|
||||
input [25:0] fec,
|
||||
input [18:0] cmd,
|
||||
|
||||
output [1:0] header
|
||||
|
||||
);
|
||||
|
||||
reg header_bit;
|
||||
reg [31:0] sync_word = 'h0;
|
||||
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (reset) begin
|
||||
sync_word <= 'h0;
|
||||
end else if (lmc_edge) begin
|
||||
case (cfg_header_mode)
|
||||
// CRC-12
|
||||
2'b00 : sync_word <= {crc12[11:9],1'b1,crc12[8:6],1'b1,
|
||||
crc12[5:3],1'b1,crc12[2:0],1'b1,
|
||||
cmd[6:4],1'b1,cmd[3],1'b1,eoemb,1'b1,
|
||||
cmd[2:0],5'b00001};
|
||||
// CRC-3
|
||||
2'b01 : sync_word <= { crc3[2:0],1'b1,cmd[6:4],1'b1,
|
||||
3'b000,1'b1,cmd[3:1],1'b1,
|
||||
3'b000,1'b1,cmd[0],1'b1,eoemb,1'b1,
|
||||
3'b000,5'b00001};
|
||||
// FEC
|
||||
2'b10 : sync_word <= { fec[25:18],
|
||||
fec[17:10],
|
||||
fec[9:4],eoemb,fec[3],
|
||||
fec[2:0],5'b00001};
|
||||
// Stand alone command
|
||||
2'b11 : sync_word <= { cmd[18:16],1'b1,cmd[15:13],1'b1,
|
||||
cmd[12:10],1'b1,cmd[9:7],1'b1,
|
||||
cmd[6:4],1'b1,cmd[3],1'b1,eoemb,1'b1,
|
||||
cmd[2:0],5'b00001};
|
||||
endcase
|
||||
end else begin
|
||||
if (lmc_quarter_edge && cfg_header_mode == 2'b01) begin
|
||||
sync_word <= {crc3[2],crc3[1],crc3[0],sync_word[27:0],1'b0};
|
||||
end else begin
|
||||
sync_word <= {sync_word[30:0],1'b0};
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign header = {~sync_word[31],sync_word[31]};
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,210 @@
|
||||
#
|
||||
# The ADI JESD204 Core is released under the following license, which is
|
||||
# different than all other HDL cores in this repository.
|
||||
#
|
||||
# Please read this, and understand the freedoms and responsibilities you have
|
||||
# by using this source code/core.
|
||||
#
|
||||
# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
#
|
||||
# This core is free software, you can use run, copy, study, change, ask
|
||||
# questions about and improve this core. Distribution of source, or resulting
|
||||
# binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
# source of the entire project (excluding the system libraries provide by the
|
||||
# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
# License version 2 as published by the Free Software Foundation.
|
||||
#
|
||||
# This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License version 2
|
||||
# along with this source code, and binary. If not, see
|
||||
# <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
# available under terms different than the General Public License. (e.g. they
|
||||
# do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
# core with any corresponding source code.) For these alternate terms you must
|
||||
# purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
# interested in such a license should contact [email protected] for
|
||||
# more information. This commercial license is sub-licensable (if you purchase
|
||||
# chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
# purchase a JESD204 license, end users of your product will also have a
|
||||
# license to use this core in a commercial setting without releasing their
|
||||
# source code).
|
||||
#
|
||||
# In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
# or publication in which you use this JESD204 HDL core. (You are not required
|
||||
# to do so; it is up to your common sense to decide whether you want to comply
|
||||
# with this request or not.) For general publications, we suggest referencing :
|
||||
# “The design and implementation of the JESD204 HDL Core used in this project
|
||||
# is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
#
|
||||
|
||||
package require qsys
|
||||
|
||||
source ../../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_intel.tcl
|
||||
|
||||
ad_ip_create jesd204_tx "ADI JESD204 Transmit" jesd204_tx_elaboration_callback
|
||||
|
||||
set_module_property INTERNAL true
|
||||
|
||||
# files
|
||||
|
||||
ad_ip_files jesd204_tx [list \
|
||||
jesd204_tx.v \
|
||||
jesd204_tx_ctrl.v \
|
||||
jesd204_tx_lane.v \
|
||||
jesd204_tx_constr.sdc \
|
||||
../jesd204_common/jesd204_eof_generator.v \
|
||||
../jesd204_common/jesd204_lmfc.v \
|
||||
../jesd204_common/jesd204_scrambler.v \
|
||||
../jesd204_common/pipeline_stage.v \
|
||||
$ad_hdl_dir/library/util_cdc/sync_bits.v \
|
||||
$ad_hdl_dir/library/util_cdc/util_cdc_constr.tcl \
|
||||
]
|
||||
|
||||
# parameters
|
||||
|
||||
add_parameter NUM_LANES INTEGER 1
|
||||
set_parameter_property NUM_LANES DISPLAY_NAME "Number of Lanes"
|
||||
set_parameter_property NUM_LANES ALLOWED_RANGES 1:8
|
||||
set_parameter_property NUM_LANES HDL_PARAMETER true
|
||||
|
||||
add_parameter NUM_LINKS INTEGER 1
|
||||
set_parameter_property NUM_LINKS DISPLAY_NAME "Number of Links"
|
||||
set_parameter_property NUM_LINKS ALLOWED_RANGES 1:8
|
||||
set_parameter_property NUM_LINKS HDL_PARAMETER true
|
||||
|
||||
add_parameter NUM_OUTPUT_PIPELINE INTEGER 0
|
||||
set_parameter_property NUM_OUTPUT_PIPELINE DISPLAY_NAME "Number of output pipeline stages"
|
||||
set_parameter_property NUM_OUTPUT_PIPELINE ALLOWED_RANGES 0:3
|
||||
set_parameter_property NUM_OUTPUT_PIPELINE HDL_PARAMETER true
|
||||
|
||||
# clock
|
||||
|
||||
add_interface clock clock end
|
||||
add_interface_port clock clk clk Input 1
|
||||
|
||||
# reset
|
||||
|
||||
add_interface reset reset end
|
||||
set_interface_property reset associatedClock clock
|
||||
set_interface_property reset synchronousEdges DEASSERT
|
||||
add_interface_port reset reset reset Input 1
|
||||
|
||||
# SYSREF~ interface
|
||||
|
||||
add_interface sysref conduit end
|
||||
set_interface_property sysref associatedClock clock
|
||||
set_interface_property sysref associatedReset reset
|
||||
add_interface_port sysref sysref export Input 1
|
||||
|
||||
# SYNC interface
|
||||
|
||||
add_interface sync conduit end
|
||||
set_interface_property sync associatedClock clock
|
||||
set_interface_property sync associatedReset reset
|
||||
add_interface_port sync sync export Input 1
|
||||
|
||||
# ilas_config interface
|
||||
|
||||
add_interface ilas_config conduit end
|
||||
set_interface_property ilas_config associatedClock clock
|
||||
set_interface_property ilas_config associatedReset reset
|
||||
|
||||
add_interface_port ilas_config ilas_config_addr addr Output 2
|
||||
add_interface_port ilas_config ilas_config_data data Input 32*NUM_LANES
|
||||
add_interface_port ilas_config ilas_config_rd rd Output 1
|
||||
|
||||
# event interface
|
||||
|
||||
add_interface event conduit end
|
||||
set_interface_property event associatedClock clock
|
||||
set_interface_property event associatedReset reset
|
||||
|
||||
add_interface_port event event_sysref_alignment_error sysref_alignment_error Output 1
|
||||
add_interface_port event event_sysref_edge sysref_edge Output 1
|
||||
|
||||
# control interface
|
||||
|
||||
add_interface control conduit end
|
||||
set_interface_property control associatedClock clock
|
||||
set_interface_property control associatedReset reset
|
||||
|
||||
add_interface_port control ctrl_manual_sync_request manual_sync_request Input 1
|
||||
|
||||
# config interface
|
||||
|
||||
add_interface config conduit end
|
||||
set_interface_property config associatedClock clock
|
||||
set_interface_property config associatedReset reset
|
||||
|
||||
add_interface_port config cfg_beats_per_multiframe beats_per_multiframe Input 8
|
||||
add_interface_port config cfg_continuous_cgs continuous_cgs Input 1
|
||||
add_interface_port config cfg_continuous_ilas continuous_ilas Input 1
|
||||
add_interface_port config cfg_disable_char_replacement disable_char_replacement Input 1
|
||||
add_interface_port config cfg_disable_scrambler disable_scrambler Input 1
|
||||
add_interface_port config cfg_lanes_disable lanes_disable Input NUM_LANES
|
||||
add_interface_port config cfg_links_disable links_disable Input NUM_LINKS
|
||||
add_interface_port config cfg_lmfc_offset lmfc_offset Input 8
|
||||
add_interface_port config cfg_mframes_per_ilas mframes_per_ilas Input 8
|
||||
add_interface_port config cfg_octets_per_frame octets_per_frame Input 8
|
||||
add_interface_port config cfg_skip_ilas skip_ilas Input 1
|
||||
add_interface_port config cfg_sysref_disable sysref_disable Input 1
|
||||
add_interface_port config cfg_sysref_oneshot sysref_oneshot Input 1
|
||||
|
||||
# status interface
|
||||
|
||||
add_interface status conduit end
|
||||
set_interface_property status associatedClock clock
|
||||
set_interface_property status associatedReset reset
|
||||
|
||||
add_interface_port status status_state state Output 2
|
||||
add_interface_port status status_sync sync Output 1
|
||||
|
||||
# lmfc_clk interface
|
||||
|
||||
add_interface lmfc_clk conduit end
|
||||
#set_interface_property lmfc_clk associatedClock clock
|
||||
#set_interface_property lmfc_clk associatedReset reset
|
||||
add_interface_port lmfc_clk lmfc_clk export Output 1
|
||||
set_port_property lmfc_clk TERMINATION TRUE
|
||||
|
||||
# lmfc_edge interface
|
||||
|
||||
add_interface lmfc_edge conduit end
|
||||
#set_interface_property lmfc_edge associatedClock clock
|
||||
#set_interface_property lmfc_edge associatedReset reset
|
||||
add_interface_port lmfc_edge lmfc_edge export Output 1
|
||||
set_port_property lmfc_edge TERMINATION TRUE
|
||||
|
||||
proc jesd204_tx_elaboration_callback {} {
|
||||
set num_lanes [get_parameter_value "NUM_LANES"]
|
||||
|
||||
# tx_data interface
|
||||
|
||||
add_interface tx_data avalon_streaming sink
|
||||
set_interface_property tx_data associatedClock clock
|
||||
|
||||
add_interface_port tx_data tx_data data input [expr 32*$num_lanes]
|
||||
add_interface_port tx_data tx_ready ready output 1
|
||||
add_interface_port tx_data tx_valid valid input 1
|
||||
set_interface_property tx_data dataBitsPerSymbol [expr 32*$num_lanes]
|
||||
|
||||
# phy interfaces
|
||||
|
||||
for {set i 0 } {$i < $num_lanes} {incr i} {
|
||||
add_interface tx_phy${i} conduit start
|
||||
# set_interface_property tx_phy${i} associatedClock clock
|
||||
# set_interface_property tx_phy${i} associatedReset reset
|
||||
add_interface_port tx_phy${i} tx_phy${i}_data char Output 32
|
||||
set_port_property tx_phy${i}_data fragment_list \
|
||||
[format "phy_data(%d:%d)" [expr 32*$i+31] [expr 32*$i]]
|
||||
add_interface_port tx_phy${i} tx_phy${i}_charisk charisk Output 4
|
||||
set_port_property tx_phy${i}_charisk fragment_list \
|
||||
[format "phy_charisk(%d:%d)" [expr 4*$i+3] [expr 4*$i]]
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,190 @@
|
||||
#
|
||||
# The ADI JESD204 Core is released under the following license, which is
|
||||
# different than all other HDL cores in this repository.
|
||||
#
|
||||
# Please read this, and understand the freedoms and responsibilities you have
|
||||
# by using this source code/core.
|
||||
#
|
||||
# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
#
|
||||
# This core is free software, you can use run, copy, study, change, ask
|
||||
# questions about and improve this core. Distribution of source, or resulting
|
||||
# binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
# source of the entire project (excluding the system libraries provide by the
|
||||
# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
# License version 2 as published by the Free Software Foundation.
|
||||
#
|
||||
# This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License version 2
|
||||
# along with this source code, and binary. If not, see
|
||||
# <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
# available under terms different than the General Public License. (e.g. they
|
||||
# do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
# core with any corresponding source code.) For these alternate terms you must
|
||||
# purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
# interested in such a license should contact [email protected] for
|
||||
# more information. This commercial license is sub-licensable (if you purchase
|
||||
# chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
# purchase a JESD204 license, end users of your product will also have a
|
||||
# license to use this core in a commercial setting without releasing their
|
||||
# source code).
|
||||
#
|
||||
# In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
# or publication in which you use this JESD204 HDL core. (You are not required
|
||||
# to do so; it is up to your common sense to decide whether you want to comply
|
||||
# with this request or not.) For general publications, we suggest referencing :
|
||||
# “The design and implementation of the JESD204 HDL Core used in this project
|
||||
# is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
#
|
||||
|
||||
source ../../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
|
||||
adi_ip_create jesd204_tx
|
||||
adi_ip_files jesd204_tx [list \
|
||||
"jesd204_tx_lane.v" \
|
||||
"jesd204_tx_lane_64b.v" \
|
||||
"jesd204_tx_header.v" \
|
||||
"jesd204_tx_ctrl.v" \
|
||||
"jesd204_tx_constr.ttcl" \
|
||||
"jesd204_tx.v"
|
||||
]
|
||||
|
||||
adi_ip_properties_lite jesd204_tx
|
||||
adi_ip_ttcl jesd204_tx "jesd204_tx_constr.ttcl"
|
||||
|
||||
adi_ip_add_core_dependencies { \
|
||||
analog.com:user:jesd204_common:1.0 \
|
||||
analog.com:user:util_cdc:1.0 \
|
||||
}
|
||||
|
||||
set_property display_name "ADI JESD204 Transmit" [ipx::current_core]
|
||||
set_property description "ADI JESD204 Transmit" [ipx::current_core]
|
||||
|
||||
adi_add_bus "tx_data" "slave" \
|
||||
"xilinx.com:interface:axis_rtl:1.0" \
|
||||
"xilinx.com:interface:axis:1.0" \
|
||||
{ \
|
||||
{ "tx_valid" "TVALID" } \
|
||||
{ "tx_ready" "TREADY" } \
|
||||
{ "tx_data" "TDATA" } \
|
||||
}
|
||||
|
||||
adi_add_multi_bus 16 "tx_phy" "master" \
|
||||
"xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0" \
|
||||
"xilinx.com:display_jesd204:jesd204_tx_bus:1.0" \
|
||||
[list \
|
||||
{ "phy_data" "txdata" 32 "(spirit:decode(id('MODELPARAM_VALUE.DATA_PATH_WIDTH')) * 8)"} \
|
||||
{ "phy_charisk" "txcharisk" 4 "(spirit:decode(id('MODELPARAM_VALUE.DATA_PATH_WIDTH')))"} \
|
||||
{ "phy_header" "txheader" 2} \
|
||||
] \
|
||||
"(spirit:decode(id('MODELPARAM_VALUE.NUM_LANES')) > {i})"
|
||||
|
||||
adi_add_bus "tx_cfg" "slave" \
|
||||
"analog.com:interface:jesd204_tx_cfg_rtl:1.0" \
|
||||
"analog.com:interface:jesd204_tx_cfg:1.0" \
|
||||
{ \
|
||||
{ "cfg_lanes_disable" "lanes_disable" } \
|
||||
{ "cfg_links_disable" "links_disable" } \
|
||||
{ "cfg_beats_per_multiframe" "beats_per_multiframe" } \
|
||||
{ "cfg_octets_per_frame" "octets_per_frame" } \
|
||||
{ "cfg_lmfc_offset" "lmfc_offset" } \
|
||||
{ "cfg_sysref_oneshot" "sysref_oneshot" } \
|
||||
{ "cfg_sysref_disable" "sysref_disable" } \
|
||||
{ "cfg_continuous_cgs" "continuous_cgs" } \
|
||||
{ "cfg_continuous_ilas" "continuous_ilas" } \
|
||||
{ "cfg_skip_ilas" "skip_ilas" } \
|
||||
{ "cfg_mframes_per_ilas" "mframes_per_ilas" } \
|
||||
{ "cfg_disable_char_replacement" "disable_char_replacement" } \
|
||||
{ "cfg_disable_scrambler" "disable_scrambler" } \
|
||||
}
|
||||
|
||||
adi_add_bus "tx_ilas_config" "master" \
|
||||
"analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" \
|
||||
"analog.com:interface:jesd204_tx_ilas_config:1.0" \
|
||||
{ \
|
||||
{ "ilas_config_rd" "rd" } \
|
||||
{ "ilas_config_addr" "addr" } \
|
||||
{ "ilas_config_data" "data" } \
|
||||
}
|
||||
|
||||
adi_add_bus "tx_event" "master" \
|
||||
"analog.com:interface:jesd204_tx_event_rtl:1.0" \
|
||||
"analog.com:interface:jesd204_tx_event:1.0" \
|
||||
{ \
|
||||
{ "event_sysref_alignment_error" "sysref_alignment_error" } \
|
||||
{ "event_sysref_edge" "sysref_edge" } \
|
||||
}
|
||||
|
||||
adi_add_bus "tx_status" "master" \
|
||||
"analog.com:interface:jesd204_tx_status_rtl:1.0" \
|
||||
"analog.com:interface:jesd204_tx_status:1.0" \
|
||||
{ \
|
||||
{ "status_state" "state" } \
|
||||
{ "status_sync" "sync" } \
|
||||
}
|
||||
|
||||
adi_add_bus "tx_ctrl" "slave" \
|
||||
"analog.com:interface:jesd204_tx_ctrl_rtl:1.0" \
|
||||
"analog.com:interface:jesd204_tx_ctrl:1.0" \
|
||||
{ \
|
||||
{ "ctrl_manual_sync_request" "manual_sync_request" } \
|
||||
}
|
||||
|
||||
adi_add_bus_clock "clk" "tx_data:tx_cfg:tx_ilas_config:tx_event:tx_status:tx_ctrl" \
|
||||
"reset"
|
||||
|
||||
adi_set_bus_dependency "tx_ilas_config" "tx_ilas_config" \
|
||||
"(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 1)"
|
||||
|
||||
adi_set_bus_dependency "tx_ctrl" "tx_ctrl" \
|
||||
"(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 1)"
|
||||
|
||||
adi_set_ports_dependency "sync" \
|
||||
"(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 1)"
|
||||
|
||||
|
||||
set cc [ipx::current_core]
|
||||
set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]
|
||||
|
||||
# Link layer mode
|
||||
set p [ipgui::get_guiparamspec -name "LINK_MODE" -component $cc]
|
||||
ipgui::move_param -component $cc -order 0 $p -parent $page0
|
||||
set_property -dict [list \
|
||||
"display_name" "Link Layer mode" \
|
||||
"tooltip" "Link Layer mode" \
|
||||
"widget" "comboBox" \
|
||||
] $p
|
||||
|
||||
set_property -dict [list \
|
||||
value_validation_type pairs \
|
||||
value_validation_pairs {64B66B 2 8B10B 1} \
|
||||
] [ipx::get_user_parameters $p -of_objects $cc]
|
||||
|
||||
|
||||
# Data width selection
|
||||
set param [ipx::get_user_parameters DATA_PATH_WIDTH -of_objects $cc]
|
||||
set_property -dict [list \
|
||||
enablement_value false \
|
||||
value_tcl_expr {expr $LINK_MODE*4} \
|
||||
] $param
|
||||
|
||||
|
||||
# SYSREF IOB placement
|
||||
set param [ipx::add_user_parameter SYSREF_IOB $cc]
|
||||
set_property -dict {value_resolve_type user value_format bool value true} $param
|
||||
|
||||
set param [ipgui::add_param -name {SYSREF_IOB} -component $cc -parent $page0]
|
||||
set_property -dict [list \
|
||||
display_name {Place SYSREF in IOB} \
|
||||
widget {checkBox} \
|
||||
show_label true \
|
||||
] $param
|
||||
|
||||
ipx::create_xgui_files [ipx::current_core]
|
||||
ipx::save_core [ipx::current_core]
|
||||
@@ -0,0 +1,119 @@
|
||||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact [email protected] for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module jesd204_tx_lane #(
|
||||
parameter DATA_PATH_WIDTH = 4
|
||||
) (
|
||||
input clk,
|
||||
|
||||
input [DATA_PATH_WIDTH-1:0] eof,
|
||||
input eomf,
|
||||
|
||||
input cgs_enable,
|
||||
|
||||
input [DATA_PATH_WIDTH*8-1:0] ilas_data,
|
||||
input [DATA_PATH_WIDTH-1:0] ilas_charisk,
|
||||
|
||||
input [DATA_PATH_WIDTH*8-1:0] tx_data,
|
||||
input tx_ready,
|
||||
|
||||
output reg [DATA_PATH_WIDTH*8-1:0] phy_data,
|
||||
output reg [DATA_PATH_WIDTH-1:0] phy_charisk,
|
||||
|
||||
input cfg_disable_scrambler
|
||||
);
|
||||
|
||||
wire [DATA_PATH_WIDTH*8-1:0] scrambled_data;
|
||||
wire [7:0] scrambled_char[0:DATA_PATH_WIDTH-1];
|
||||
reg [7:0] char_align[0:DATA_PATH_WIDTH-1];
|
||||
|
||||
jesd204_scrambler #(
|
||||
.WIDTH(DATA_PATH_WIDTH*8),
|
||||
.DESCRAMBLE(0)
|
||||
) i_scrambler (
|
||||
.clk(clk),
|
||||
.reset(~tx_ready),
|
||||
.enable(~cfg_disable_scrambler),
|
||||
.data_in(tx_data),
|
||||
.data_out(scrambled_data)
|
||||
);
|
||||
|
||||
generate
|
||||
genvar i;
|
||||
|
||||
for (i = 0; i < DATA_PATH_WIDTH; i = i + 1) begin: gen_char
|
||||
assign scrambled_char[i] = scrambled_data[i*8+7:i*8];
|
||||
|
||||
always @(*) begin
|
||||
if (i == DATA_PATH_WIDTH-1 && eomf == 1'b1) begin
|
||||
char_align[i] = 8'h7c; // /A/
|
||||
end else begin
|
||||
char_align[i] = 8'hfc; // /F/
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (cgs_enable == 1'b1) begin
|
||||
phy_charisk[i] <= 1'b1;
|
||||
end else if (eof[i] == 1'b1 && scrambled_char[i] == char_align[i]) begin
|
||||
phy_charisk[i] <= 1'b1;
|
||||
end else begin
|
||||
phy_charisk[i] <= ilas_charisk[i];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endgenerate
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (cgs_enable == 1'b1) begin
|
||||
phy_data <= {DATA_PATH_WIDTH{8'hbc}};
|
||||
end else begin
|
||||
phy_data <= (tx_ready) ? scrambled_data : ilas_data;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,143 @@
|
||||
//
|
||||
// The ADI JESD204 Core is released under the following license, which is
|
||||
// different than all other HDL cores in this repository.
|
||||
//
|
||||
// Please read this, and understand the freedoms and responsibilities you have
|
||||
// by using this source code/core.
|
||||
//
|
||||
// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
|
||||
//
|
||||
// This core is free software, you can use run, copy, study, change, ask
|
||||
// questions about and improve this core. Distribution of source, or resulting
|
||||
// binaries (including those inside an FPGA or ASIC) require you to release the
|
||||
// source of the entire project (excluding the system libraries provide by the
|
||||
// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
|
||||
// License version 2 as published by the Free Software Foundation.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License version 2
|
||||
// along with this source code, and binary. If not, see
|
||||
// <http://www.gnu.org/licenses/>.
|
||||
//
|
||||
// Commercial licenses (with commercial support) of this JESD204 core are also
|
||||
// available under terms different than the General Public License. (e.g. they
|
||||
// do not require you to accompany any image (FPGA or ASIC) using the JESD204
|
||||
// core with any corresponding source code.) For these alternate terms you must
|
||||
// purchase a license from Analog Devices Technology Licensing Office. Users
|
||||
// interested in such a license should contact [email protected] for
|
||||
// more information. This commercial license is sub-licensable (if you purchase
|
||||
// chips from Analog Devices, incorporate them into your PCB level product, and
|
||||
// purchase a JESD204 license, end users of your product will also have a
|
||||
// license to use this core in a commercial setting without releasing their
|
||||
// source code).
|
||||
//
|
||||
// In addition, we kindly ask you to acknowledge ADI in any program, application
|
||||
// or publication in which you use this JESD204 HDL core. (You are not required
|
||||
// to do so; it is up to your common sense to decide whether you want to comply
|
||||
// with this request or not.) For general publications, we suggest referencing :
|
||||
// “The design and implementation of the JESD204 HDL Core used in this project
|
||||
// is copyright © 2016-2017, Analog Devices, Inc.”
|
||||
//
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module jesd204_tx_lane_64b (
|
||||
input clk,
|
||||
input reset,
|
||||
|
||||
input [63:0] tx_data,
|
||||
input tx_ready,
|
||||
|
||||
output reg [63:0] phy_data,
|
||||
output [1:0] phy_header,
|
||||
|
||||
input lmc_edge,
|
||||
input lmc_quarter_edge,
|
||||
input eoemb,
|
||||
|
||||
// Scrambling mandatory in 64bxxb, keep this for debugging purposes
|
||||
input cfg_disable_scrambler,
|
||||
input [1:0] cfg_header_mode,
|
||||
input cfg_lane_disable
|
||||
|
||||
);
|
||||
|
||||
reg [63:0] scrambled_data;
|
||||
reg lmc_edge_d1 = 'b0;
|
||||
reg lmc_edge_d2 = 'b0;
|
||||
reg lmc_quarter_edge_d1 = 'b0;
|
||||
reg lmc_quarter_edge_d2 = 'b0;
|
||||
reg tx_ready_d1 = 'b0;
|
||||
|
||||
wire [63:0] tx_data_msb_s;
|
||||
wire [63:0] scrambled_data_r;
|
||||
wire [11:0] crc12;
|
||||
|
||||
/* Reorder octets MSB first */
|
||||
genvar i;
|
||||
generate
|
||||
for (i = 0; i < 64; i = i + 8) begin: g_link_data
|
||||
assign tx_data_msb_s[i+:8] = tx_data[64-1-i-:8];
|
||||
end
|
||||
endgenerate
|
||||
|
||||
jesd204_scrambler_64b #(
|
||||
.WIDTH(64),
|
||||
.DESCRAMBLE(0)
|
||||
) i_scrambler (
|
||||
.clk(clk),
|
||||
.reset(reset),
|
||||
.enable(~cfg_disable_scrambler),
|
||||
.data_in(tx_data_msb_s),
|
||||
.data_out(scrambled_data_r)
|
||||
);
|
||||
|
||||
always @(posedge clk) begin
|
||||
lmc_edge_d1 <= lmc_edge;
|
||||
lmc_edge_d2 <= lmc_edge_d1;
|
||||
lmc_quarter_edge_d1 <= lmc_quarter_edge;
|
||||
lmc_quarter_edge_d2 <= lmc_quarter_edge_d1;
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
scrambled_data <= scrambled_data_r;
|
||||
phy_data <= scrambled_data;
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
tx_ready_d1 <= tx_ready;
|
||||
end
|
||||
|
||||
jesd204_crc12 i_crc12 (
|
||||
.clk(clk),
|
||||
.reset(~tx_ready_d1),
|
||||
.init(lmc_edge_d2),
|
||||
.data_in(scrambled_data),
|
||||
.crc12(crc12)
|
||||
);
|
||||
|
||||
jesd204_tx_header i_header_gen (
|
||||
.clk(clk),
|
||||
.reset(~tx_ready | cfg_lane_disable),
|
||||
|
||||
.cfg_header_mode(cfg_header_mode),
|
||||
|
||||
.lmc_edge(lmc_edge_d2),
|
||||
.lmc_quarter_edge(lmc_quarter_edge_d2),
|
||||
|
||||
// Header content to be sent must be valid during lmc_edge
|
||||
.eoemb(eoemb),
|
||||
.crc3(3'b0),
|
||||
.crc12(crc12),
|
||||
.fec(26'b0),
|
||||
.cmd(19'b0),
|
||||
|
||||
.header(phy_header)
|
||||
|
||||
);
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,104 @@
|
||||
|
||||
# Loading additional proc with user specified bodies to compute parameter values.
|
||||
source [file join [file dirname [file dirname [info script]]] gui/jesd204_tx_v1_0.gtcl]
|
||||
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||
ipgui::add_param $IPINST -name "LINK_MODE" -parent ${Page_0} -widget comboBox
|
||||
ipgui::add_param $IPINST -name "DATA_PATH_WIDTH" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "NUM_LANES" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "NUM_LINKS" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "NUM_OUTPUT_PIPELINE" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "SYSREF_IOB" -parent ${Page_0}
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DATA_PATH_WIDTH { PARAM_VALUE.DATA_PATH_WIDTH PARAM_VALUE.LINK_MODE } {
|
||||
# Procedure called to update DATA_PATH_WIDTH when any of the dependent parameters in the arguments change
|
||||
|
||||
set DATA_PATH_WIDTH ${PARAM_VALUE.DATA_PATH_WIDTH}
|
||||
set LINK_MODE ${PARAM_VALUE.LINK_MODE}
|
||||
set values(LINK_MODE) [get_property value $LINK_MODE]
|
||||
set_property value [gen_USERPARAMETER_DATA_PATH_WIDTH_VALUE $values(LINK_MODE)] $DATA_PATH_WIDTH
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DATA_PATH_WIDTH { PARAM_VALUE.DATA_PATH_WIDTH } {
|
||||
# Procedure called to validate DATA_PATH_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.LINK_MODE { PARAM_VALUE.LINK_MODE } {
|
||||
# Procedure called to update LINK_MODE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.LINK_MODE { PARAM_VALUE.LINK_MODE } {
|
||||
# Procedure called to validate LINK_MODE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.NUM_LANES { PARAM_VALUE.NUM_LANES } {
|
||||
# Procedure called to update NUM_LANES when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.NUM_LANES { PARAM_VALUE.NUM_LANES } {
|
||||
# Procedure called to validate NUM_LANES
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.NUM_LINKS { PARAM_VALUE.NUM_LINKS } {
|
||||
# Procedure called to update NUM_LINKS when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.NUM_LINKS { PARAM_VALUE.NUM_LINKS } {
|
||||
# Procedure called to validate NUM_LINKS
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.NUM_OUTPUT_PIPELINE { PARAM_VALUE.NUM_OUTPUT_PIPELINE } {
|
||||
# Procedure called to update NUM_OUTPUT_PIPELINE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.NUM_OUTPUT_PIPELINE { PARAM_VALUE.NUM_OUTPUT_PIPELINE } {
|
||||
# Procedure called to validate NUM_OUTPUT_PIPELINE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.SYSREF_IOB { PARAM_VALUE.SYSREF_IOB } {
|
||||
# Procedure called to update SYSREF_IOB when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.SYSREF_IOB { PARAM_VALUE.SYSREF_IOB } {
|
||||
# Procedure called to validate SYSREF_IOB
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.NUM_LANES { MODELPARAM_VALUE.NUM_LANES PARAM_VALUE.NUM_LANES } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.NUM_LANES}] ${MODELPARAM_VALUE.NUM_LANES}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.NUM_LINKS { MODELPARAM_VALUE.NUM_LINKS PARAM_VALUE.NUM_LINKS } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.NUM_LINKS}] ${MODELPARAM_VALUE.NUM_LINKS}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.NUM_OUTPUT_PIPELINE { MODELPARAM_VALUE.NUM_OUTPUT_PIPELINE PARAM_VALUE.NUM_OUTPUT_PIPELINE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.NUM_OUTPUT_PIPELINE}] ${MODELPARAM_VALUE.NUM_OUTPUT_PIPELINE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.LINK_MODE { MODELPARAM_VALUE.LINK_MODE PARAM_VALUE.LINK_MODE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.LINK_MODE}] ${MODELPARAM_VALUE.LINK_MODE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DATA_PATH_WIDTH { MODELPARAM_VALUE.DATA_PATH_WIDTH PARAM_VALUE.DATA_PATH_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DATA_PATH_WIDTH}] ${MODELPARAM_VALUE.DATA_PATH_WIDTH}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user