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//
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// The ADI JESD204 Core is released under the following license, which is
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// different than all other HDL cores in this repository.
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//
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// Please read this, and understand the freedoms and responsibilities you have
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// by using this source code/core.
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//
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// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
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//
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// This core is free software, you can use run, copy, study, change, ask
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// questions about and improve this core. Distribution of source, or resulting
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// binaries (including those inside an FPGA or ASIC) require you to release the
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// source of the entire project (excluding the system libraries provide by the
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// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License version 2
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// along with this source code, and binary. If not, see
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// <http://www.gnu.org/licenses/>.
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//
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// Commercial licenses (with commercial support) of this JESD204 core are also
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// available under terms different than the General Public License. (e.g. they
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// do not require you to accompany any image (FPGA or ASIC) using the JESD204
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// core with any corresponding source code.) For these alternate terms you must
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// purchase a license from Analog Devices Technology Licensing Office. Users
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// interested in such a license should contact [email protected] for
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// more information. This commercial license is sub-licensable (if you purchase
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// chips from Analog Devices, incorporate them into your PCB level product, and
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// purchase a JESD204 license, end users of your product will also have a
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// license to use this core in a commercial setting without releasing their
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// source code).
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//
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// In addition, we kindly ask you to acknowledge ADI in any program, application
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// or publication in which you use this JESD204 HDL core. (You are not required
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// to do so; it is up to your common sense to decide whether you want to comply
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// with this request or not.) For general publications, we suggest referencing :
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// “The design and implementation of the JESD204 HDL Core used in this project
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// is copyright © 2016-2017, Analog Devices, Inc.”
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//
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`timescale 1ns/100ps
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module jesd204_tx_lane_64b (
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input clk,
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input reset,
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input [63:0] tx_data,
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input tx_ready,
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output reg [63:0] phy_data,
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output [1:0] phy_header,
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input lmc_edge,
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input lmc_quarter_edge,
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input eoemb,
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// Scrambling mandatory in 64bxxb, keep this for debugging purposes
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input cfg_disable_scrambler,
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input [1:0] cfg_header_mode,
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input cfg_lane_disable
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);
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reg [63:0] scrambled_data;
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reg lmc_edge_d1 = 'b0;
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reg lmc_edge_d2 = 'b0;
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reg lmc_quarter_edge_d1 = 'b0;
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reg lmc_quarter_edge_d2 = 'b0;
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reg tx_ready_d1 = 'b0;
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wire [63:0] tx_data_msb_s;
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wire [63:0] scrambled_data_r;
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wire [11:0] crc12;
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/* Reorder octets MSB first */
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genvar i;
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generate
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for (i = 0; i < 64; i = i + 8) begin: g_link_data
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assign tx_data_msb_s[i+:8] = tx_data[64-1-i-:8];
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end
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endgenerate
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jesd204_scrambler_64b #(
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.WIDTH(64),
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.DESCRAMBLE(0)
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) i_scrambler (
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.clk(clk),
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.reset(reset),
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.enable(~cfg_disable_scrambler),
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.data_in(tx_data_msb_s),
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.data_out(scrambled_data_r)
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);
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always @(posedge clk) begin
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lmc_edge_d1 <= lmc_edge;
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lmc_edge_d2 <= lmc_edge_d1;
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lmc_quarter_edge_d1 <= lmc_quarter_edge;
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lmc_quarter_edge_d2 <= lmc_quarter_edge_d1;
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end
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always @(posedge clk) begin
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scrambled_data <= scrambled_data_r;
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phy_data <= scrambled_data;
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end
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always @(posedge clk) begin
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tx_ready_d1 <= tx_ready;
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end
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jesd204_crc12 i_crc12 (
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.clk(clk),
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.reset(~tx_ready_d1),
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.init(lmc_edge_d2),
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.data_in(scrambled_data),
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.crc12(crc12)
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);
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jesd204_tx_header i_header_gen (
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.clk(clk),
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.reset(~tx_ready | cfg_lane_disable),
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.cfg_header_mode(cfg_header_mode),
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.lmc_edge(lmc_edge_d2),
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.lmc_quarter_edge(lmc_quarter_edge_d2),
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// Header content to be sent must be valid during lmc_edge
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.eoemb(eoemb),
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.crc3(3'b0),
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.crc12(crc12),
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.fec(26'b0),
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.cmd(19'b0),
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.header(phy_header)
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);
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endmodule
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