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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module util_adcfifo #(
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parameter FPGA_TECHNOLOGY = 0,
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parameter ADC_DATA_WIDTH = 256,
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parameter DMA_DATA_WIDTH = 64,
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parameter DMA_READY_ENABLE = 1,
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parameter DMA_ADDRESS_WIDTH = 10) (
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// fifo interface
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input adc_rst,
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input adc_clk,
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input adc_wr,
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input [ADC_DATA_WIDTH-1:0] adc_wdata,
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output adc_wovf,
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// dma interface
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input dma_clk,
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output dma_wr,
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output [DMA_DATA_WIDTH-1:0] dma_wdata,
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input dma_wready,
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input dma_xfer_req,
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output [ 3:0] dma_xfer_status);
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localparam DMA_MEM_RATIO = ADC_DATA_WIDTH/DMA_DATA_WIDTH;
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localparam ADDRESS_PADDING_WIDTH = (DMA_MEM_RATIO == 1) ? 0 :
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(DMA_MEM_RATIO == 2) ? 1 :
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(DMA_MEM_RATIO == 4) ? 2 : 3;
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localparam ADC_ADDRESS_WIDTH = DMA_ADDRESS_WIDTH - ADDRESS_PADDING_WIDTH;
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localparam ADC_ADDR_LIMIT = (2**ADC_ADDRESS_WIDTH)-1;
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localparam DMA_ADDR_LIMIT = (2**DMA_ADDRESS_WIDTH)-1;
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// internal registers
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reg [ 2:0] adc_xfer_req_m = 'd0;
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reg adc_xfer_init = 'd0;
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reg adc_xfer_enable = 'd0;
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reg adc_wr_int = 'd0;
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reg [ADC_DATA_WIDTH-1:0] adc_wdata_int = 'd0;
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reg [ADC_ADDRESS_WIDTH-1:0] adc_waddr_int = 'd0;
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reg adc_capture_arm = 1'b0;
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reg dma_rd = 'd0;
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reg dma_rd_d = 'd0;
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reg [DMA_DATA_WIDTH-1:0] dma_rdata_d = 'd0;
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reg [DMA_ADDRESS_WIDTH:0] dma_raddr = 'd0;
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reg [DMA_ADDRESS_WIDTH-1:0] dma_waddr_int = 'd0;
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reg dma_endof_read = 'd0;
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// internal signals
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wire adc_rst_s;
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wire dma_wready_s;
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wire [DMA_DATA_WIDTH-1:0] dma_rdata_s;
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wire dma_read_rst_s;
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wire dma_wr_int_s;
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wire [ADC_ADDRESS_WIDTH-1:0] dma_waddr_int_s;
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wire adc_end_of_capture_s;
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wire [ADC_ADDRESS_WIDTH-1:0] adc_waddr_int_s;
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// write interface
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assign adc_wovf = 1'd0;
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// synchronize the adc_rst to the adc_clk clock domain
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ad_rst i_adc_rst_sync (
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.rst_async (adc_rst),
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.clk (adc_clk),
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.rstn (),
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.rst (adc_rst_s));
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// optional capture synchronization
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always @(posedge adc_clk) begin
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if (adc_rst_s == 1'b1) begin
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adc_xfer_req_m <= 'd0;
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end else begin
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adc_xfer_req_m <= {adc_xfer_req_m[1:0], dma_xfer_req};
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end
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end
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always @(posedge adc_clk) begin
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if (adc_rst_s == 1'b1) begin
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adc_xfer_init <= 'd0;
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end else begin
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adc_xfer_init <= adc_xfer_req_m[1] & ~adc_xfer_req_m[2];
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end
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end
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// a de-asserted xfer_req will reset the FIFO
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assign dma_wr = dma_wr_int_s & dma_xfer_req;
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assign adc_end_of_capture_s = ((adc_waddr_int_s == ADC_ADDR_LIMIT) || (adc_xfer_req_m[2] == 1'b0)) &&
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(adc_wr_int == 1'b1);
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always @(posedge adc_clk) begin
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if (adc_rst_s == 1'b1) begin
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adc_xfer_enable <= 'd0;
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end else begin
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if (adc_xfer_init == 1'b1) begin
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adc_xfer_enable <= 1'b1;
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end else if (adc_end_of_capture_s == 1'b1) begin
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adc_xfer_enable <= 1'b0;
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end
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end
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end
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assign adc_waddr_int_s = (adc_waddr_int == ADC_ADDR_LIMIT) ? adc_waddr_int : adc_waddr_int + 1'b1;
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always @(posedge adc_clk) begin
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if (adc_xfer_req_m[2] == 1'b0) begin
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adc_wr_int <= 'd0;
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adc_wdata_int <= 'd0;
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adc_waddr_int <= 'd0;
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end else begin
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adc_wr_int <= adc_wr & adc_xfer_enable;
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adc_wdata_int <= adc_wdata;
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if (adc_wr_int == 1'b1) begin
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adc_waddr_int <= adc_waddr_int_s;
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end
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end
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end
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// read interface
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assign dma_xfer_status = 4'd0;
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// write address synchronization
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sync_gray #(
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.DATA_WIDTH (ADC_ADDRESS_WIDTH),
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.ASYNC_CLK (1))
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i_dma_waddr_sync (
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.in_clk (adc_clk),
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.in_resetn (1'b1),
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.in_count (adc_waddr_int),
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.out_resetn (1'b1),
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.out_clk (dma_clk),
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.out_count (dma_waddr_int_s));
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always @(posedge dma_clk) begin
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if (dma_read_rst_s == 1'b1) begin
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dma_waddr_int <= 'd0;
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end else begin
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dma_waddr_int <= {dma_waddr_int_s,{ADDRESS_PADDING_WIDTH{1'b0}}};
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end
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end
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assign dma_read_rst_s = ~dma_xfer_req;
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assign dma_wready_s = (DMA_READY_ENABLE == 0) ? 1'b1 : dma_wready;
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assign dma_rd_s = ((dma_raddr < {1'b0, dma_waddr_int}) || &dma_waddr_int) & dma_wready_s;
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always @(posedge dma_clk) begin
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if (dma_read_rst_s == 1'b1) begin
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dma_rd <= 'd0;
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dma_rd_d <= 'd0;
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dma_rdata_d <= 'd0;
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dma_raddr <= 'd0;
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dma_endof_read <= 'd0;
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end else begin
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if (dma_waddr_int != 'd0) begin
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dma_rd <= dma_rd_s;
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if (dma_rd_s == 1'b1) begin
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dma_raddr <= dma_raddr + 1'b1;
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end
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end
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dma_rd_d <= dma_rd;
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dma_rdata_d <= dma_rdata_s;
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end
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end
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// instantiations
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generate
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if (FPGA_TECHNOLOGY == 1) begin
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mem_asym i_mem_asym (
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.mem_i_wrclock_clk (adc_clk),
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.mem_i_wren_wren (adc_wr_int),
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.mem_i_wraddress_wraddress (adc_waddr_int),
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.mem_i_datain_datain (adc_wdata_int),
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.mem_i_rdclock_clk (dma_clk),
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.mem_i_rdaddress_rdaddress (dma_raddr[DMA_ADDRESS_WIDTH-1:0]),
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.mem_o_dataout_dataout (dma_rdata_s));
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end else begin
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ad_mem_asym #(
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.A_ADDRESS_WIDTH (ADC_ADDRESS_WIDTH),
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.A_DATA_WIDTH (ADC_DATA_WIDTH),
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.B_ADDRESS_WIDTH (DMA_ADDRESS_WIDTH),
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.B_DATA_WIDTH (DMA_DATA_WIDTH))
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i_mem_asym (
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.clka (adc_clk),
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.wea (adc_wr_int),
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.addra (adc_waddr_int),
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.dina (adc_wdata_int),
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.clkb (dma_clk),
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.reb (1'b1),
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.addrb (dma_raddr[DMA_ADDRESS_WIDTH-1:0]),
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.doutb (dma_rdata_s));
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end
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endgenerate
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ad_axis_inf_rx #(.DATA_WIDTH(DMA_DATA_WIDTH)) i_axis_inf (
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.clk (dma_clk),
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.rst (dma_read_rst_s),
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.valid (dma_rd_d),
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.last (1'd0),
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.data (dma_rdata_d),
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.inf_valid (dma_wr_int_s),
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.inf_last (),
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.inf_data (dma_wdata),
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.inf_ready (dma_wready));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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