Archived
first commit after restructuring
This commit is contained in:
@@ -0,0 +1,18 @@
|
||||
####################################################################################
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||||
## Copyright 2018(c) Analog Devices, Inc.
|
||||
## Auto-generated, do not modify!
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||||
####################################################################################
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||||
|
||||
LIBRARY_NAME := util_axis_fifo
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||||
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||||
GENERIC_DEPS += ../common/ad_mem.v
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||||
GENERIC_DEPS += address_gray.v
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||||
GENERIC_DEPS += address_gray_pipelined.v
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||||
GENERIC_DEPS += address_sync.v
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||||
GENERIC_DEPS += util_axis_fifo.v
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||||
|
||||
XILINX_DEPS += util_axis_fifo_ip.tcl
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||||
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||||
XILINX_LIB_DEPS += util_cdc
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||||
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||||
include ../scripts/library.mk
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@@ -0,0 +1,155 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
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||||
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||||
module fifo_address_gray #(
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||||
parameter ADDRESS_WIDTH = 4
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||||
) (
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||||
input m_axis_aclk,
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||||
input m_axis_aresetn,
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||||
input m_axis_ready,
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||||
output reg m_axis_valid,
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||||
output reg [ADDRESS_WIDTH:0] m_axis_level,
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||||
|
||||
input s_axis_aclk,
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input s_axis_aresetn,
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||||
output reg s_axis_ready,
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||||
input s_axis_valid,
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||||
output reg s_axis_empty,
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||||
output [ADDRESS_WIDTH-1:0] s_axis_waddr,
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||||
output reg [ADDRESS_WIDTH:0] s_axis_room
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||||
);
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||||
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reg [ADDRESS_WIDTH:0] _s_axis_waddr = 'h00;
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reg [ADDRESS_WIDTH:0] _s_axis_waddr_next;
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||||
|
||||
reg [ADDRESS_WIDTH:0] _m_axis_raddr = 'h00;
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||||
reg [ADDRESS_WIDTH:0] _m_axis_raddr_next;
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||||
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||||
reg [ADDRESS_WIDTH:0] s_axis_waddr_gray = 'h00;
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||||
wire [ADDRESS_WIDTH:0] s_axis_waddr_gray_next;
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||||
wire [ADDRESS_WIDTH:0] s_axis_raddr_gray;
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||||
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||||
reg [ADDRESS_WIDTH:0] m_axis_raddr_gray = 'h00;
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wire [ADDRESS_WIDTH:0] m_axis_raddr_gray_next;
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wire [ADDRESS_WIDTH:0] m_axis_waddr_gray;
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||||
assign s_axis_waddr = _s_axis_waddr[ADDRESS_WIDTH-1:0];
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||||
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||||
always @(*)
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||||
begin
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||||
if (s_axis_ready && s_axis_valid)
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||||
_s_axis_waddr_next <= _s_axis_waddr + 1;
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||||
else
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||||
_s_axis_waddr_next <= _s_axis_waddr;
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||||
end
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||||
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||||
assign s_axis_waddr_gray_next = _s_axis_waddr_next ^ _s_axis_waddr_next[ADDRESS_WIDTH:1];
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||||
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||||
always @(posedge s_axis_aclk)
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||||
begin
|
||||
if (s_axis_aresetn == 1'b0) begin
|
||||
_s_axis_waddr <= 'h00;
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||||
s_axis_waddr_gray <= 'h00;
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||||
end else begin
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||||
_s_axis_waddr <= _s_axis_waddr_next;
|
||||
s_axis_waddr_gray <= s_axis_waddr_gray_next;
|
||||
end
|
||||
end
|
||||
|
||||
always @(*)
|
||||
begin
|
||||
if (m_axis_ready && m_axis_valid)
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||||
_m_axis_raddr_next <= _m_axis_raddr + 1;
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||||
else
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||||
_m_axis_raddr_next <= _m_axis_raddr;
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||||
end
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||||
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||||
assign m_axis_raddr_gray_next = _m_axis_raddr_next ^ _m_axis_raddr_next[ADDRESS_WIDTH:1];
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||||
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||||
always @(posedge m_axis_aclk)
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||||
begin
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||||
if (m_axis_aresetn == 1'b0) begin
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||||
_m_axis_raddr <= 'h00;
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||||
m_axis_raddr_gray <= 'h00;
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||||
end else begin
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||||
_m_axis_raddr <= _m_axis_raddr_next;
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m_axis_raddr_gray <= m_axis_raddr_gray_next;
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||||
end
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||||
end
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||||
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sync_bits #(
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||||
.NUM_OF_BITS(ADDRESS_WIDTH + 1)
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) i_waddr_sync (
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.out_clk(m_axis_aclk),
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.out_resetn(m_axis_aresetn),
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||||
.in_bits(s_axis_waddr_gray),
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||||
.out_bits(m_axis_waddr_gray)
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||||
);
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||||
|
||||
sync_bits #(
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||||
.NUM_OF_BITS(ADDRESS_WIDTH + 1)
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||||
) i_raddr_sync (
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.out_clk(s_axis_aclk),
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||||
.out_resetn(s_axis_aresetn),
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||||
.in_bits(m_axis_raddr_gray),
|
||||
.out_bits(s_axis_raddr_gray)
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||||
);
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||||
always @(posedge s_axis_aclk)
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||||
begin
|
||||
if (s_axis_aresetn == 1'b0) begin
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s_axis_ready <= 1'b1;
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s_axis_empty <= 1'b1;
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end else begin
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||||
s_axis_ready <= (s_axis_raddr_gray[ADDRESS_WIDTH] == s_axis_waddr_gray_next[ADDRESS_WIDTH] ||
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||||
s_axis_raddr_gray[ADDRESS_WIDTH-1] == s_axis_waddr_gray_next[ADDRESS_WIDTH-1] ||
|
||||
s_axis_raddr_gray[ADDRESS_WIDTH-2:0] != s_axis_waddr_gray_next[ADDRESS_WIDTH-2:0]);
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||||
s_axis_empty <= s_axis_raddr_gray == s_axis_waddr_gray_next;
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||||
end
|
||||
end
|
||||
|
||||
always @(posedge m_axis_aclk)
|
||||
begin
|
||||
if (s_axis_aresetn == 1'b0)
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||||
m_axis_valid <= 1'b0;
|
||||
else begin
|
||||
m_axis_valid <= m_axis_waddr_gray != m_axis_raddr_gray_next;
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||||
end
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||||
end
|
||||
|
||||
endmodule
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||||
|
||||
@@ -0,0 +1,152 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module fifo_address_gray_pipelined #(
|
||||
parameter ADDRESS_WIDTH = 4
|
||||
) (
|
||||
input m_axis_aclk,
|
||||
input m_axis_aresetn,
|
||||
input m_axis_ready,
|
||||
output reg m_axis_valid,
|
||||
output [ADDRESS_WIDTH-1:0] m_axis_raddr,
|
||||
output reg [ADDRESS_WIDTH:0] m_axis_level,
|
||||
|
||||
input s_axis_aclk,
|
||||
input s_axis_aresetn,
|
||||
output reg s_axis_ready,
|
||||
input s_axis_valid,
|
||||
output reg s_axis_empty,
|
||||
output [ADDRESS_WIDTH-1:0] s_axis_waddr,
|
||||
output reg [ADDRESS_WIDTH:0] s_axis_room
|
||||
);
|
||||
|
||||
localparam MAX_ROOM = {1'b1,{ADDRESS_WIDTH{1'b0}}};
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||||
|
||||
reg [ADDRESS_WIDTH:0] _s_axis_waddr = 'h00;
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||||
reg [ADDRESS_WIDTH:0] _s_axis_waddr_next;
|
||||
wire [ADDRESS_WIDTH:0] _s_axis_raddr;
|
||||
|
||||
reg [ADDRESS_WIDTH:0] _m_axis_raddr = 'h00;
|
||||
reg [ADDRESS_WIDTH:0] _m_axis_raddr_next;
|
||||
wire [ADDRESS_WIDTH:0] _m_axis_waddr;
|
||||
|
||||
assign s_axis_waddr = _s_axis_waddr[ADDRESS_WIDTH-1:0];
|
||||
assign m_axis_raddr = _m_axis_raddr[ADDRESS_WIDTH-1:0];
|
||||
|
||||
always @(*)
|
||||
begin
|
||||
if (s_axis_ready && s_axis_valid)
|
||||
_s_axis_waddr_next <= _s_axis_waddr + 1'b1;
|
||||
else
|
||||
_s_axis_waddr_next <= _s_axis_waddr;
|
||||
end
|
||||
|
||||
always @(posedge s_axis_aclk)
|
||||
begin
|
||||
if (s_axis_aresetn == 1'b0) begin
|
||||
_s_axis_waddr <= 'h00;
|
||||
end else begin
|
||||
_s_axis_waddr <= _s_axis_waddr_next;
|
||||
end
|
||||
end
|
||||
|
||||
always @(*)
|
||||
begin
|
||||
if (m_axis_ready && m_axis_valid)
|
||||
_m_axis_raddr_next <= _m_axis_raddr + 1'b1;
|
||||
else
|
||||
_m_axis_raddr_next <= _m_axis_raddr;
|
||||
end
|
||||
|
||||
always @(posedge m_axis_aclk)
|
||||
begin
|
||||
if (m_axis_aresetn == 1'b0) begin
|
||||
_m_axis_raddr <= 'h00;
|
||||
end else begin
|
||||
_m_axis_raddr <= _m_axis_raddr_next;
|
||||
end
|
||||
end
|
||||
|
||||
sync_gray #(
|
||||
.DATA_WIDTH(ADDRESS_WIDTH + 1)
|
||||
) i_waddr_sync (
|
||||
.in_clk(s_axis_aclk),
|
||||
.in_resetn(s_axis_aresetn),
|
||||
.out_clk(m_axis_aclk),
|
||||
.out_resetn(m_axis_aresetn),
|
||||
.in_count(_s_axis_waddr),
|
||||
.out_count(_m_axis_waddr)
|
||||
);
|
||||
|
||||
sync_gray #(
|
||||
.DATA_WIDTH(ADDRESS_WIDTH + 1)
|
||||
) i_raddr_sync (
|
||||
.in_clk(m_axis_aclk),
|
||||
.in_resetn(m_axis_aresetn),
|
||||
.out_clk(s_axis_aclk),
|
||||
.out_resetn(s_axis_aresetn),
|
||||
.in_count(_m_axis_raddr),
|
||||
.out_count(_s_axis_raddr)
|
||||
);
|
||||
|
||||
always @(posedge s_axis_aclk)
|
||||
begin
|
||||
if (s_axis_aresetn == 1'b0) begin
|
||||
s_axis_ready <= 1'b1;
|
||||
s_axis_empty <= 1'b1;
|
||||
s_axis_room <= MAX_ROOM;
|
||||
end else begin
|
||||
s_axis_ready <= (_s_axis_raddr[ADDRESS_WIDTH] == _s_axis_waddr_next[ADDRESS_WIDTH] ||
|
||||
_s_axis_raddr[ADDRESS_WIDTH-1:0] != _s_axis_waddr_next[ADDRESS_WIDTH-1:0]);
|
||||
s_axis_empty <= _s_axis_raddr == _s_axis_waddr_next;
|
||||
s_axis_room <= _s_axis_raddr - _s_axis_waddr_next + MAX_ROOM;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge m_axis_aclk)
|
||||
begin
|
||||
if (m_axis_aresetn == 1'b0) begin
|
||||
m_axis_valid <= 1'b0;
|
||||
m_axis_level <= 'h00;
|
||||
end else begin
|
||||
m_axis_valid <= _m_axis_waddr != _m_axis_raddr_next;
|
||||
m_axis_level <= _m_axis_waddr - _m_axis_raddr_next;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
@@ -0,0 +1,109 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module fifo_address_sync #(
|
||||
parameter ADDRESS_WIDTH = 4
|
||||
) (
|
||||
input clk,
|
||||
input resetn,
|
||||
|
||||
input m_axis_ready,
|
||||
output reg m_axis_valid,
|
||||
output reg [ADDRESS_WIDTH-1:0] m_axis_raddr,
|
||||
output [ADDRESS_WIDTH:0] m_axis_level,
|
||||
|
||||
output reg s_axis_ready,
|
||||
input s_axis_valid,
|
||||
output reg s_axis_empty,
|
||||
output reg [ADDRESS_WIDTH-1:0] s_axis_waddr,
|
||||
output [ADDRESS_WIDTH:0] s_axis_room
|
||||
);
|
||||
|
||||
localparam MAX_ROOM = {1'b1,{ADDRESS_WIDTH{1'b0}}};
|
||||
|
||||
reg [ADDRESS_WIDTH:0] room = MAX_ROOM;
|
||||
reg [ADDRESS_WIDTH:0] level = 'h00;
|
||||
reg [ADDRESS_WIDTH:0] level_next;
|
||||
|
||||
assign s_axis_room = room;
|
||||
assign m_axis_level = level;
|
||||
|
||||
wire read = m_axis_ready & m_axis_valid;
|
||||
wire write = s_axis_ready & s_axis_valid;
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if (resetn == 1'b0) begin
|
||||
s_axis_waddr <= 'h00;
|
||||
m_axis_raddr <= 'h00;
|
||||
end else begin
|
||||
if (write)
|
||||
s_axis_waddr <= s_axis_waddr + 1'b1;
|
||||
if (read)
|
||||
m_axis_raddr <= m_axis_raddr + 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(*)
|
||||
begin
|
||||
if (read & ~write)
|
||||
level_next <= level - 1'b1;
|
||||
else if (~read & write)
|
||||
level_next <= level + 1'b1;
|
||||
else
|
||||
level_next <= level;
|
||||
end
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if (resetn == 1'b0) begin
|
||||
m_axis_valid <= 1'b0;
|
||||
s_axis_ready <= 1'b0;
|
||||
level <= 'h00;
|
||||
room <= MAX_ROOM;
|
||||
s_axis_empty <= 'h00;
|
||||
end else begin
|
||||
level <= level_next;
|
||||
room <= MAX_ROOM - level_next;
|
||||
m_axis_valid <= level_next != 0;
|
||||
s_axis_ready <= level_next != MAX_ROOM;
|
||||
s_axis_empty <= level_next == 0;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
@@ -0,0 +1,602 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>analog.com</spirit:vendor>
|
||||
<spirit:library>user</spirit:library>
|
||||
<spirit:name>util_axis_fifo</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>s_axis</spirit:name>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
|
||||
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version:1
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6d6f64655f636f756e7465727c42617463684d6f6465:1
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eof:
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<?xml version="1.0" encoding="UTF-8"?>
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<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
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<!-- -->
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<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
|
||||
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<labtools version="1" minor="0"/>
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@@ -0,0 +1,248 @@
|
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// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
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// terms.
|
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//
|
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|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module util_axis_fifo #(
|
||||
parameter DATA_WIDTH = 64,
|
||||
parameter ASYNC_CLK = 1,
|
||||
parameter ADDRESS_WIDTH = 4,
|
||||
parameter S_AXIS_REGISTERED = 1
|
||||
) (
|
||||
input m_axis_aclk,
|
||||
input m_axis_aresetn,
|
||||
input m_axis_ready,
|
||||
output m_axis_valid,
|
||||
output [DATA_WIDTH-1:0] m_axis_data,
|
||||
output [ADDRESS_WIDTH:0] m_axis_level,
|
||||
|
||||
input s_axis_aclk,
|
||||
input s_axis_aresetn,
|
||||
output s_axis_ready,
|
||||
input s_axis_valid,
|
||||
input [DATA_WIDTH-1:0] s_axis_data,
|
||||
output s_axis_empty,
|
||||
output [ADDRESS_WIDTH:0] s_axis_room
|
||||
);
|
||||
|
||||
generate if (ADDRESS_WIDTH == 0) begin
|
||||
|
||||
reg [DATA_WIDTH-1:0] cdc_sync_fifo_ram;
|
||||
reg s_axis_waddr = 1'b0;
|
||||
reg m_axis_raddr = 1'b0;
|
||||
|
||||
wire m_axis_waddr;
|
||||
wire s_axis_raddr;
|
||||
|
||||
sync_bits #(
|
||||
.NUM_OF_BITS(1),
|
||||
.ASYNC_CLK(ASYNC_CLK)
|
||||
) i_waddr_sync (
|
||||
.out_clk(m_axis_aclk),
|
||||
.out_resetn(m_axis_aresetn),
|
||||
.in_bits(s_axis_waddr),
|
||||
.out_bits(m_axis_waddr)
|
||||
);
|
||||
|
||||
sync_bits #(
|
||||
.NUM_OF_BITS(1),
|
||||
.ASYNC_CLK(ASYNC_CLK)
|
||||
) i_raddr_sync (
|
||||
.out_clk(s_axis_aclk),
|
||||
.out_resetn(s_axis_aresetn),
|
||||
.in_bits(m_axis_raddr),
|
||||
.out_bits(s_axis_raddr)
|
||||
);
|
||||
|
||||
assign m_axis_valid = m_axis_raddr != m_axis_waddr;
|
||||
assign m_axis_level = m_axis_valid;
|
||||
assign s_axis_ready = s_axis_raddr == s_axis_waddr;
|
||||
assign s_axis_empty = s_axis_ready;
|
||||
assign s_axis_room = s_axis_ready;
|
||||
|
||||
always @(posedge s_axis_aclk) begin
|
||||
if (s_axis_ready == 1'b1 && s_axis_valid == 1'b1)
|
||||
cdc_sync_fifo_ram <= s_axis_data;
|
||||
end
|
||||
|
||||
always @(posedge s_axis_aclk) begin
|
||||
if (s_axis_aresetn == 1'b0) begin
|
||||
s_axis_waddr <= 1'b0;
|
||||
end else begin
|
||||
if (s_axis_ready & s_axis_valid) begin
|
||||
s_axis_waddr <= s_axis_waddr + 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge m_axis_aclk) begin
|
||||
if (m_axis_aresetn == 1'b0) begin
|
||||
m_axis_raddr <= 1'b0;
|
||||
end else begin
|
||||
if (m_axis_valid & m_axis_ready)
|
||||
m_axis_raddr <= m_axis_raddr + 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
assign m_axis_data = cdc_sync_fifo_ram;
|
||||
|
||||
end else begin
|
||||
|
||||
reg [DATA_WIDTH-1:0] ram[0:2**ADDRESS_WIDTH-1];
|
||||
|
||||
wire [ADDRESS_WIDTH-1:0] s_axis_waddr;
|
||||
wire [ADDRESS_WIDTH-1:0] m_axis_raddr;
|
||||
wire _m_axis_ready;
|
||||
wire _m_axis_valid;
|
||||
wire [ADDRESS_WIDTH:0] _m_axis_level;
|
||||
|
||||
wire s_mem_write;
|
||||
wire m_mem_read;
|
||||
|
||||
reg valid;
|
||||
|
||||
always @(posedge m_axis_aclk) begin
|
||||
if (m_axis_aresetn == 1'b0) begin
|
||||
valid <= 1'b0;
|
||||
end else begin
|
||||
if (_m_axis_valid)
|
||||
valid <= 1'b1;
|
||||
else if (m_axis_ready)
|
||||
valid <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
assign s_mem_write = s_axis_ready & s_axis_valid;
|
||||
assign m_mem_read = (~valid || m_axis_ready) && _m_axis_valid;
|
||||
|
||||
if (ASYNC_CLK == 1) begin
|
||||
|
||||
// The assumption is that in this mode the S_AXIS_REGISTERED is 1
|
||||
|
||||
fifo_address_gray_pipelined #(
|
||||
.ADDRESS_WIDTH(ADDRESS_WIDTH)
|
||||
) i_address_gray (
|
||||
.m_axis_aclk(m_axis_aclk),
|
||||
.m_axis_aresetn(m_axis_aresetn),
|
||||
.m_axis_ready(_m_axis_ready),
|
||||
.m_axis_valid(_m_axis_valid),
|
||||
.m_axis_raddr(m_axis_raddr),
|
||||
.m_axis_level(_m_axis_level),
|
||||
|
||||
.s_axis_aclk(s_axis_aclk),
|
||||
.s_axis_aresetn(s_axis_aresetn),
|
||||
.s_axis_ready(s_axis_ready),
|
||||
.s_axis_valid(s_axis_valid),
|
||||
.s_axis_empty(s_axis_empty),
|
||||
.s_axis_waddr(s_axis_waddr),
|
||||
.s_axis_room(s_axis_room)
|
||||
);
|
||||
|
||||
// When the clocks are asynchronous instantiate a block RAM
|
||||
// regardless of the requested size to make sure we threat the
|
||||
// clock crossing correctly
|
||||
ad_mem #(
|
||||
.DATA_WIDTH (DATA_WIDTH),
|
||||
.ADDRESS_WIDTH (ADDRESS_WIDTH))
|
||||
i_mem (
|
||||
.clka(s_axis_aclk),
|
||||
.wea(s_mem_write),
|
||||
.addra(s_axis_waddr),
|
||||
.dina(s_axis_data),
|
||||
.clkb(m_axis_aclk),
|
||||
.reb(m_mem_read),
|
||||
.addrb(m_axis_raddr),
|
||||
.doutb(m_axis_data)
|
||||
);
|
||||
|
||||
assign _m_axis_ready = ~valid || m_axis_ready;
|
||||
assign m_axis_valid = valid;
|
||||
// the util_axis_fifo is functioning in 'first write fall through' mode,
|
||||
// which means that we need to assure that the value of the level reflects
|
||||
// the actual FIFO level plus the available data, which sits on the bus
|
||||
assign m_axis_level = (m_axis_valid) ? _m_axis_level + 1'b1 : _m_axis_level;
|
||||
|
||||
end else begin
|
||||
|
||||
fifo_address_sync #(
|
||||
.ADDRESS_WIDTH(ADDRESS_WIDTH)
|
||||
) i_address_sync (
|
||||
.clk(m_axis_aclk),
|
||||
.resetn(m_axis_aresetn),
|
||||
.m_axis_ready(_m_axis_ready),
|
||||
.m_axis_valid(_m_axis_valid),
|
||||
.m_axis_raddr(m_axis_raddr),
|
||||
.m_axis_level(m_axis_level),
|
||||
|
||||
.s_axis_ready(s_axis_ready),
|
||||
.s_axis_valid(s_axis_valid),
|
||||
.s_axis_empty(s_axis_empty),
|
||||
.s_axis_waddr(s_axis_waddr),
|
||||
.s_axis_room(s_axis_room)
|
||||
);
|
||||
|
||||
// When the clocks are synchronous use behavioral modeling for the SDP RAM
|
||||
// Let the synthesizer decide what to infer (distributed or block RAM)
|
||||
always @(posedge s_axis_aclk) begin
|
||||
if (s_mem_write)
|
||||
ram[s_axis_waddr] <= s_axis_data;
|
||||
end
|
||||
|
||||
if (S_AXIS_REGISTERED == 1) begin
|
||||
|
||||
reg [DATA_WIDTH-1:0] data;
|
||||
|
||||
always @(posedge m_axis_aclk) begin
|
||||
if (m_mem_read)
|
||||
data <= ram[m_axis_raddr];
|
||||
end
|
||||
|
||||
assign _m_axis_ready = ~valid || m_axis_ready;
|
||||
assign m_axis_data = data;
|
||||
assign m_axis_valid = valid;
|
||||
|
||||
end else begin
|
||||
|
||||
assign _m_axis_ready = m_axis_ready;
|
||||
assign m_axis_valid = _m_axis_valid;
|
||||
assign m_axis_data = ram[m_axis_raddr];
|
||||
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
end endgenerate
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,405 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Version="7" Minor="40" Path="/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_axis_fifo/util_axis_fifo.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="25d68f17b8ff467a9c4f67a247b8e579"/>
|
||||
<Option Name="Part" Val="xc7vx485tffg1157-1"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="BoardPart" Val=""/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../library"/>
|
||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../../ghdl/library"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="DSAVendor" Val="xilinx"/>
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||||
<Option Name="DSANumComputeUnits" Val="60"/>
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<Option Name="WTXSimLaunchSim" Val="0"/>
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||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="0"/>
|
||||
<Option Name="WTModelSimExportSim" Val="0"/>
|
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<Option Name="WTQuestaExportSim" Val="0"/>
|
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<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="0"/>
|
||||
<Option Name="WTRivieraExportSim" Val="0"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
<Option Name="SimTypes" Val="bfm"/>
|
||||
<Option Name="SimTypes" Val="tlm"/>
|
||||
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="31">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/../common/ad_mem.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/address_gray_pipelined.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/address_sync.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/util_axis_fifo.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/address_gray.v">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
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</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/component.xml">
|
||||
<FileInfo SFType="IPXACT"/>
|
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</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="util_axis_fifo"/>
|
||||
</Config>
|
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</FileSet>
|
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<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
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<Filter Type="Constrs"/>
|
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<Config>
|
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<Option Name="ConstrsType" Val="XDC"/>
|
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</Config>
|
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</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
|
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<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
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<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
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<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
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<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
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<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
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</Simulator>
|
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<Simulator Name="Questa">
|
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<Option Name="Description" Val="Questa Advanced Simulator"/>
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</Simulator>
|
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<Simulator Name="IES">
|
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<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
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</Simulator>
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<Simulator Name="Xcelium">
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<Option Name="Description" Val="Xcelium Parallel Simulator"/>
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</Simulator>
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<Simulator Name="VCS">
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<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
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</Simulator>
|
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<Simulator Name="Riviera">
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<Option Name="Description" Val="Riviera-PRO Simulator"/>
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</Simulator>
|
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</Simulators>
|
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<Runs Version="1" Minor="10">
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<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
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</Run>
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<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
|
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<Strategy Version="1" Minor="2">
|
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<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
|
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<Desc>Default settings for Implementation.</Desc>
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</StratHandle>
|
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<Step Id="init_design"/>
|
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<Step Id="opt_design"/>
|
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<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
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<Step Id="post_place_power_opt_design"/>
|
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<Step Id="phys_opt_design"/>
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<Step Id="route_design"/>
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<Step Id="post_route_phys_opt_design"/>
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<Step Id="write_bitstream"/>
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</Strategy>
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<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
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|
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</MsgRule>
|
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<MsgRule>
|
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<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
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<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
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<MsgAttr Name="Id" Val="Place 30-73"/>
|
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<MsgAttr Name="Severity" Val="ANY"/>
|
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<MsgAttr Name="ShowRule" Val="1"/>
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<MsgAttr Name="NewSeverity" Val="WARNING"/>
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|
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<MsgAttr Name="StringsToMatch" Val="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY"/>
|
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|
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|
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<MsgAttr Name="Limit" Val="-1"/>
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<MsgAttr Name="Severity" Val="ANY"/>
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<MsgAttr Name="ShowRule" Val="1"/>
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<MsgAttr Name="RuleSource" Val="2"/>
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<MsgAttr Name="StringIsRegExp" Val="0"/>
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<MsgAttr Name="RuleId" Val="2"/>
|
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<MsgAttr Name="Note" Val=""/>
|
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<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
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</MsgRule>
|
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<MsgRule>
|
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<MsgAttr Name="RuleType" Val="1"/>
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||||
<MsgAttr Name="Limit" Val="-1"/>
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<MsgAttr Name="NewSeverity" Val="WARNING"/>
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<MsgAttr Name="Id" Val="BD 41-1306"/>
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<MsgAttr Name="RuleId" Val="3"/>
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<MsgAttr Name="Note" Val=""/>
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<MsgAttr Name="CreatedTimestamp" Val=""/>
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<MsgRule>
|
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<MsgAttr Name="RuleType" Val="1"/>
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<MsgAttr Name="Limit" Val="-1"/>
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<MsgAttr Name="Note" Val=""/>
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||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-3656"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
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<MsgAttr Name="RuleSource" Val="2"/>
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<MsgAttr Name="StringIsRegExp" Val="0"/>
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<MsgAttr Name="RuleId" Val="5"/>
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<MsgAttr Name="Note" Val=""/>
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<MsgAttr Name="CreatedTimestamp" Val=""/>
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</MsgRule>
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<MsgRule>
|
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<MsgAttr Name="RuleType" Val="1"/>
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<MsgAttr Name="Limit" Val="-1"/>
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<MsgAttr Name="NewSeverity" Val="INFO"/>
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<MsgAttr Name="Id" Val="IP_Flow 19-4623"/>
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<MsgAttr Name="Severity" Val="ANY"/>
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<MsgAttr Name="RuleType" Val="1"/>
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|
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</MsgRule>
|
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<MsgRule>
|
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<MsgAttr Name="RuleType" Val="1"/>
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|
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<MsgAttr Name="RuleId" Val="8"/>
|
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<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Designutils 20-3303"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="9"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="HDPYFinalizeIO"/>
|
||||
</MsgRule>
|
||||
<Board/>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
<BootPmcSettings Version="1" Minor="0">
|
||||
<Parameters>
|
||||
<Parameter Name="PMC_CDO.ATTRS.LOADADDR" Value="" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_FB_CLK" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_FREQ" Value="300" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_BUS_WIDTH" Value="x1" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_DATA_MODE" Value="Single" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_FREQ" Value="200" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_SLOT_TYPE" Value="SD 2.0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_FREQ" Value="200" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_SLOT_TYPE" Value="SD 2.0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSPI_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSPI_FREQ" Value="300" Type="string"/>
|
||||
<Parameter Name="BOOT.USB_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SMAP_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SMAP_DATA_WIDTH" Value="32 Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSC_FREQ" Value="33.333" Type="string"/>
|
||||
<Parameter Name="BOOT.SECONDARY.PCIE_ENABLE" Value="0" Type="string"/>
|
||||
</Parameters>
|
||||
</BootPmcSettings>
|
||||
</Project>
|
||||
@@ -0,0 +1,41 @@
|
||||
|
||||
source ../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
|
||||
adi_ip_create util_axis_fifo
|
||||
adi_ip_files util_axis_fifo [list \
|
||||
"address_gray.v" \
|
||||
"address_gray_pipelined.v" \
|
||||
"address_sync.v" \
|
||||
"../common/ad_mem.v" \
|
||||
"util_axis_fifo.v" \
|
||||
]
|
||||
|
||||
adi_ip_properties_lite util_axis_fifo
|
||||
|
||||
adi_ip_add_core_dependencies { \
|
||||
analog.com:user:util_cdc:1.0 \
|
||||
}
|
||||
|
||||
adi_add_bus "s_axis" "slave" \
|
||||
"xilinx.com:interface:axis_rtl:1.0" \
|
||||
"xilinx.com:interface:axis:1.0" \
|
||||
{
|
||||
{"s_axis_valid" "TVALID"} \
|
||||
{"s_axis_ready" "TREADY"} \
|
||||
{"s_axis_data" "TDATA"} \
|
||||
}
|
||||
|
||||
adi_add_bus "m_axis" "master" \
|
||||
"xilinx.com:interface:axis_rtl:1.0" \
|
||||
"xilinx.com:interface:axis:1.0" \
|
||||
{
|
||||
{"m_axis_valid" "TVALID"} \
|
||||
{"m_axis_ready" "TREADY"} \
|
||||
{"m_axis_data" "TDATA"} \
|
||||
}
|
||||
|
||||
adi_add_bus_clock "m_axis_aclk" "m_axis" "m_axis_aresetn"
|
||||
adi_add_bus_clock "s_axis_aclk" "s_axis" "m_axis_aresetn"
|
||||
|
||||
ipx::save_core [ipx::current_core]
|
||||
@@ -0,0 +1,70 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||
ipgui::add_param $IPINST -name "ADDRESS_WIDTH" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "ASYNC_CLK" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "DATA_WIDTH" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "S_AXIS_REGISTERED" -parent ${Page_0}
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ADDRESS_WIDTH { PARAM_VALUE.ADDRESS_WIDTH } {
|
||||
# Procedure called to update ADDRESS_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ADDRESS_WIDTH { PARAM_VALUE.ADDRESS_WIDTH } {
|
||||
# Procedure called to validate ADDRESS_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ASYNC_CLK { PARAM_VALUE.ASYNC_CLK } {
|
||||
# Procedure called to update ASYNC_CLK when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ASYNC_CLK { PARAM_VALUE.ASYNC_CLK } {
|
||||
# Procedure called to validate ASYNC_CLK
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } {
|
||||
# Procedure called to update DATA_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } {
|
||||
# Procedure called to validate DATA_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.S_AXIS_REGISTERED { PARAM_VALUE.S_AXIS_REGISTERED } {
|
||||
# Procedure called to update S_AXIS_REGISTERED when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.S_AXIS_REGISTERED { PARAM_VALUE.S_AXIS_REGISTERED } {
|
||||
# Procedure called to validate S_AXIS_REGISTERED
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.DATA_WIDTH { MODELPARAM_VALUE.DATA_WIDTH PARAM_VALUE.DATA_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DATA_WIDTH}] ${MODELPARAM_VALUE.DATA_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.ASYNC_CLK { MODELPARAM_VALUE.ASYNC_CLK PARAM_VALUE.ASYNC_CLK } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ASYNC_CLK}] ${MODELPARAM_VALUE.ASYNC_CLK}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.ADDRESS_WIDTH { MODELPARAM_VALUE.ADDRESS_WIDTH PARAM_VALUE.ADDRESS_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ADDRESS_WIDTH}] ${MODELPARAM_VALUE.ADDRESS_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.S_AXIS_REGISTERED { MODELPARAM_VALUE.S_AXIS_REGISTERED PARAM_VALUE.S_AXIS_REGISTERED } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.S_AXIS_REGISTERED}] ${MODELPARAM_VALUE.S_AXIS_REGISTERED}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user