Archived
first commit after restructuring
This commit is contained in:
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####################################################################################
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## Copyright 2018(c) Analog Devices, Inc.
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## Auto-generated, do not modify!
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####################################################################################
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LIBRARY_NAME := util_rfifo
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GENERIC_DEPS += ../common/ad_mem.v
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GENERIC_DEPS += util_rfifo.v
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XILINX_DEPS += util_rfifo_constr.xdc
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XILINX_DEPS += util_rfifo_ip.tcl
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INTEL_DEPS += util_rfifo_constr.sdc
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INTEL_DEPS += util_rfifo_hw.tcl
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include ../scripts/library.mk
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File diff suppressed because it is too large
Load Diff
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version:1
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6d6f64655f636f756e7465727c42617463684d6f6465:1
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eof:
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@@ -0,0 +1,6 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
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<!-- -->
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<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
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<labtools version="1" minor="0"/>
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@@ -0,0 +1,405 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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||||
// of various HDL (Verilog or VHDL) components. The individual modules are
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||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
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||||
//
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||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
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||||
//
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||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
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||||
//
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||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
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||||
// of this repository (LICENSE_GPL2), and also online at:
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||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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||||
//
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||||
// OR
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||||
//
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||||
// 2. An ADI specific BSD license, which can be found in the top level directory
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||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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||||
// This will allow to generate bit files and not release the source code,
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||||
// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module util_rfifo #(
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parameter NUM_OF_CHANNELS = 4,
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parameter DIN_DATA_WIDTH = 32,
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parameter DOUT_DATA_WIDTH = 64,
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parameter DIN_ADDRESS_WIDTH = 8) (
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// d-in interface
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input din_rstn,
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input din_clk,
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output din_enable_0,
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output din_valid_0,
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input din_valid_in_0,
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input [DIN_DATA_WIDTH-1:0] din_data_0,
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output din_enable_1,
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output din_valid_1,
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input din_valid_in_1,
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input [DIN_DATA_WIDTH-1:0] din_data_1,
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output din_enable_2,
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output din_valid_2,
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input din_valid_in_2,
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input [DIN_DATA_WIDTH-1:0] din_data_2,
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output din_enable_3,
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output din_valid_3,
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input din_valid_in_3,
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input [DIN_DATA_WIDTH-1:0] din_data_3,
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output din_enable_4,
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output din_valid_4,
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input din_valid_in_4,
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input [DIN_DATA_WIDTH-1:0] din_data_4,
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output din_enable_5,
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output din_valid_5,
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input din_valid_in_5,
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input [DIN_DATA_WIDTH-1:0] din_data_5,
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output din_enable_6,
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output din_valid_6,
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input din_valid_in_6,
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input [DIN_DATA_WIDTH-1:0] din_data_6,
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output din_enable_7,
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output din_valid_7,
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input din_valid_in_7,
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input [DIN_DATA_WIDTH-1:0] din_data_7,
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input din_unf,
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// d-out interface
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input dout_rst,
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input dout_clk,
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input dout_enable_0,
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input dout_valid_0,
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output dout_valid_out_0,
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output [DOUT_DATA_WIDTH-1:0] dout_data_0,
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input dout_enable_1,
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input dout_valid_1,
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output dout_valid_out_1,
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output [DOUT_DATA_WIDTH-1:0] dout_data_1,
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input dout_enable_2,
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input dout_valid_2,
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output dout_valid_out_2,
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output [DOUT_DATA_WIDTH-1:0] dout_data_2,
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input dout_enable_3,
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input dout_valid_3,
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output dout_valid_out_3,
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output [DOUT_DATA_WIDTH-1:0] dout_data_3,
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input dout_enable_4,
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input dout_valid_4,
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output dout_valid_out_4,
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output [DOUT_DATA_WIDTH-1:0] dout_data_4,
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input dout_enable_5,
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input dout_valid_5,
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output dout_valid_out_5,
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output [DOUT_DATA_WIDTH-1:0] dout_data_5,
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input dout_enable_6,
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input dout_valid_6,
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output dout_valid_out_6,
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output [DOUT_DATA_WIDTH-1:0] dout_data_6,
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input dout_enable_7,
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input dout_valid_7,
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output dout_valid_out_7,
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output [DOUT_DATA_WIDTH-1:0] dout_data_7,
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output reg dout_unf);
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localparam M_MEM_RATIO = DOUT_DATA_WIDTH/DIN_DATA_WIDTH;
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localparam ADDRESS_WIDTH = (DIN_ADDRESS_WIDTH > 5) ? DIN_ADDRESS_WIDTH : 5;
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localparam DATA_WIDTH = DOUT_DATA_WIDTH * NUM_OF_CHANNELS;
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localparam T_DIN_DATA_WIDTH = DIN_DATA_WIDTH * 8;
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localparam T_DOUT_DATA_WIDTH = DOUT_DATA_WIDTH * 8;
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// internal registers
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reg [(DATA_WIDTH-1):0] din_wdata = 'd0;
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reg [(ADDRESS_WIDTH-1):0] din_waddr = 'hc;
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reg din_wr = 'd0;
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reg din_valid = 'd0;
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reg [ 6:0] din_req_cnt = 'd0;
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reg [ 7:0] din_enable_m1 = 'd0;
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reg [ 7:0] din_enable = 'd0;
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reg din_req_t_m1 = 'd0;
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reg din_req_t_m2 = 'd0;
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reg din_req_t_m3 = 'd0;
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reg din_req = 'd0;
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reg din_init = 'd0;
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reg din_unf_d = 'd0;
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reg [ 7:0] dout_valid = 'd0;
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reg [(T_DOUT_DATA_WIDTH+1):0] dout_data = 'd0;
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reg [(DATA_WIDTH-1):0] dout_rdata = 'd0;
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reg [ 7:0] dout_enable = 'd0;
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reg dout_req_t = 'd0;
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reg dout_init = 'd0;
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reg [(ADDRESS_WIDTH-1):0] dout_raddr = 'd0;
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reg dout_unf_m1 = 'd0;
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// internal signals
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wire [(T_DIN_DATA_WIDTH-1):0] din_data_s;
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wire din_req_s;
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wire [ 7:0] dout_enable_s;
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wire [ 7:0] dout_valid_s;
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wire [(T_DOUT_DATA_WIDTH+1):0] dout_data_s;
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wire dout_init_s;
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wire [(DATA_WIDTH-1):0] dout_rdata_s;
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wire [ 2:0] din_wcnt_s;
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// variables
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// enables & valids
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assign din_enable_7 = din_enable[7];
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assign din_enable_6 = din_enable[6];
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assign din_enable_5 = din_enable[5];
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assign din_enable_4 = din_enable[4];
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assign din_enable_3 = din_enable[3];
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assign din_enable_2 = din_enable[2];
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assign din_enable_1 = din_enable[1];
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assign din_enable_0 = din_enable[0];
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assign din_valid_7 = din_valid;
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assign din_valid_6 = din_valid;
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assign din_valid_5 = din_valid;
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assign din_valid_4 = din_valid;
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assign din_valid_3 = din_valid;
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assign din_valid_2 = din_valid;
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assign din_valid_1 = din_valid;
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assign din_valid_0 = din_valid;
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assign din_data_s = {din_data_7, din_data_6, din_data_5, din_data_4,
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din_data_3, din_data_2, din_data_1, din_data_0};
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// simple data transfer-- no ovf/unf handling- read-bw > write-bw
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// dout_width >= din_width only
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genvar n;
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generate
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for (n = 0; n < NUM_OF_CHANNELS; n = n + 1) begin: g_in
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if (M_MEM_RATIO == 1) begin
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always @(posedge din_clk) begin
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if (din_valid_in_0 == 1'b1) begin
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din_wdata[((DOUT_DATA_WIDTH*(n+1))-1):(DOUT_DATA_WIDTH*n)] <=
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din_data_s[((DIN_DATA_WIDTH*(n+1))-1):(DIN_DATA_WIDTH*n)];
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end
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end
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end else begin
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always @(posedge din_clk) begin
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if (din_valid_in_0 == 1'b1) begin
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din_wdata[((DOUT_DATA_WIDTH*(n+1))-1):(DOUT_DATA_WIDTH*n)] <=
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{din_data_s[((DIN_DATA_WIDTH*(n+1))-1):(DIN_DATA_WIDTH*n)],
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din_wdata[((DOUT_DATA_WIDTH*(n+1))-1):(DIN_DATA_WIDTH+(DOUT_DATA_WIDTH*n))]};
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end
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end
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end
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end
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endgenerate
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generate
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if (M_MEM_RATIO == 1) begin
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assign din_wcnt_s = 'b0;
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end else begin
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reg [ 2:0] din_wcnt = 'd0;
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always @(posedge din_clk or negedge din_rstn)
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if (din_rstn == 1'b0) begin
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din_wcnt <= 'd0;
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end else begin
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if (din_valid_in_0 == 1'b1) begin
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din_wcnt <= din_wcnt + 1'b1;
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end
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end
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assign din_wcnt_s = din_wcnt;
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end
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endgenerate
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always @(posedge din_clk or negedge din_rstn) begin
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if (din_rstn == 1'b0) begin
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din_waddr <= 'hc;
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din_wr <= 1'd0;
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end else begin
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if ((din_req == 1'b1) && (din_init == 1'b1)) begin
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din_waddr <= 'h18;
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end else if (din_wr == 1'b1) begin
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din_waddr <= din_waddr + 1'b1;
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end
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case (M_MEM_RATIO)
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8: din_wr <= din_valid_in_0 & din_wcnt_s[2] & din_wcnt_s[1] & din_wcnt_s[0];
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4: din_wr <= din_valid_in_0 & din_wcnt_s[1] & din_wcnt_s[0];
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2: din_wr <= din_valid_in_0 & din_wcnt_s[0];
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default: din_wr <= din_valid_in_0;
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endcase
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||||
end
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||||
end
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always @(posedge din_clk or negedge din_rstn) begin
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||||
if (din_rstn == 1'b0) begin
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din_valid <= 'd0;
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||||
din_req_cnt <= 'd0;
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end else begin
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||||
din_valid <= din_req_cnt[6];
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||||
if (din_req_s == 1'b1) begin
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||||
case (M_MEM_RATIO)
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8: din_req_cnt <= 7'h40;
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4: din_req_cnt <= 7'h60;
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2: din_req_cnt <= 7'h70;
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||||
default: din_req_cnt <= 7'h78;
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||||
endcase
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||||
end else if (din_req_cnt[6] == 1'b1) begin
|
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din_req_cnt <= din_req_cnt + 1'b1;
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||||
end
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||||
end
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||||
end
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||||
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assign din_req_s = din_req_t_m3 ^ din_req_t_m2;
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||||
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||||
always @(posedge din_clk or negedge din_rstn) begin
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if (din_rstn == 1'b0) begin
|
||||
din_enable_m1 <= 'd0;
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din_enable <= 'd0;
|
||||
din_req_t_m1 <= 'd0;
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||||
din_req_t_m2 <= 'd0;
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||||
din_req_t_m3 <= 'd0;
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||||
din_req <= 'd0;
|
||||
din_init <= 'd0;
|
||||
din_unf_d <= 'd0;
|
||||
end else begin
|
||||
din_enable_m1 <= dout_enable;
|
||||
din_enable <= din_enable_m1;
|
||||
din_req_t_m1 <= dout_req_t;
|
||||
din_req_t_m2 <= din_req_t_m1;
|
||||
din_req_t_m3 <= din_req_t_m2;
|
||||
din_req <= din_req_s;
|
||||
if (din_req_s == 1'b1) begin
|
||||
din_init <= dout_init;
|
||||
end
|
||||
din_unf_d <= din_unf;
|
||||
end
|
||||
end
|
||||
|
||||
// read interface (bus expansion and/or clock conversion)
|
||||
|
||||
assign dout_enable_s = {dout_enable_7, dout_enable_6, dout_enable_5, dout_enable_4,
|
||||
dout_enable_3, dout_enable_2, dout_enable_1, dout_enable_0};
|
||||
assign dout_valid_s = {dout_valid_7, dout_valid_6, dout_valid_5, dout_valid_4,
|
||||
dout_valid_3, dout_valid_2, dout_valid_1, dout_valid_0};
|
||||
|
||||
generate
|
||||
if (NUM_OF_CHANNELS >= 8) begin
|
||||
assign dout_data_s = dout_rdata;
|
||||
end else begin
|
||||
assign dout_data_s[(T_DOUT_DATA_WIDTH+1):DATA_WIDTH] = 'd0;
|
||||
assign dout_data_s[(DATA_WIDTH-1):0] = dout_rdata;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
assign dout_valid_out_7 = dout_valid[7];
|
||||
assign dout_valid_out_6 = dout_valid[6];
|
||||
assign dout_valid_out_5 = dout_valid[5];
|
||||
assign dout_valid_out_4 = dout_valid[4];
|
||||
assign dout_valid_out_3 = dout_valid[3];
|
||||
assign dout_valid_out_2 = dout_valid[2];
|
||||
assign dout_valid_out_1 = dout_valid[1];
|
||||
assign dout_valid_out_0 = dout_valid[0];
|
||||
|
||||
assign dout_data_7 = dout_data[((DOUT_DATA_WIDTH*8)-1):(DOUT_DATA_WIDTH*7)];
|
||||
assign dout_data_6 = dout_data[((DOUT_DATA_WIDTH*7)-1):(DOUT_DATA_WIDTH*6)];
|
||||
assign dout_data_5 = dout_data[((DOUT_DATA_WIDTH*6)-1):(DOUT_DATA_WIDTH*5)];
|
||||
assign dout_data_4 = dout_data[((DOUT_DATA_WIDTH*5)-1):(DOUT_DATA_WIDTH*4)];
|
||||
assign dout_data_3 = dout_data[((DOUT_DATA_WIDTH*4)-1):(DOUT_DATA_WIDTH*3)];
|
||||
assign dout_data_2 = dout_data[((DOUT_DATA_WIDTH*3)-1):(DOUT_DATA_WIDTH*2)];
|
||||
assign dout_data_1 = dout_data[((DOUT_DATA_WIDTH*2)-1):(DOUT_DATA_WIDTH*1)];
|
||||
assign dout_data_0 = dout_data[((DOUT_DATA_WIDTH*1)-1):(DOUT_DATA_WIDTH*0)];
|
||||
|
||||
always @(posedge dout_clk) begin
|
||||
if (dout_rst == 1'b1) begin
|
||||
dout_valid <= 8'd0;
|
||||
end else begin
|
||||
dout_valid <= dout_valid_s;
|
||||
end
|
||||
end
|
||||
|
||||
generate
|
||||
for (n = 0; n < NUM_OF_CHANNELS; n = n + 1) begin: g_out
|
||||
always @(posedge dout_clk) begin
|
||||
if (dout_rst == 1'b1) begin
|
||||
dout_data[((DOUT_DATA_WIDTH*(n+1))-1):(DOUT_DATA_WIDTH*n)] <= 'd0;
|
||||
end else if (dout_valid_s[n] == 1'b1) begin
|
||||
dout_data[((DOUT_DATA_WIDTH*(n+1))-1):(DOUT_DATA_WIDTH*n)] <=
|
||||
dout_data_s[((DOUT_DATA_WIDTH*(n+1))-1):(DOUT_DATA_WIDTH*n)];
|
||||
end
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
always @(posedge dout_clk) begin
|
||||
dout_rdata <= dout_rdata_s;
|
||||
end
|
||||
|
||||
assign dout_init_s = (dout_enable == dout_enable_s) ? 1'b0 : 1'b1;
|
||||
|
||||
always @(posedge dout_clk) begin
|
||||
if (dout_rst == 1'b1) begin
|
||||
dout_enable <= 'd0;
|
||||
dout_req_t <= 'd0;
|
||||
dout_init <= 'd0;
|
||||
dout_raddr <= 'd0;
|
||||
end else begin
|
||||
dout_enable <= dout_enable_s;
|
||||
if (dout_init_s == 1'b1) begin
|
||||
dout_req_t <= ~dout_req_t;
|
||||
dout_init <= 1'd1;
|
||||
dout_raddr <= 'd0;
|
||||
end else if (dout_valid_s[0] == 1'b1) begin
|
||||
if (dout_raddr[2:0] == 3'd7) begin
|
||||
dout_req_t <= ~dout_req_t;
|
||||
dout_init <= 1'd0;
|
||||
end
|
||||
dout_raddr <= dout_raddr + 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge dout_clk) begin
|
||||
if (dout_rst == 1'b1) begin
|
||||
dout_unf_m1 <= 'd0;
|
||||
dout_unf <= 'd0;
|
||||
end else begin
|
||||
dout_unf_m1 <= din_unf_d;
|
||||
dout_unf <= dout_unf_m1;
|
||||
end
|
||||
end
|
||||
|
||||
// instantiations
|
||||
|
||||
ad_mem #(.ADDRESS_WIDTH(ADDRESS_WIDTH), .DATA_WIDTH(DATA_WIDTH)) i_mem (
|
||||
.clka (din_clk),
|
||||
.wea (din_wr),
|
||||
.addra (din_waddr),
|
||||
.dina (din_wdata),
|
||||
.clkb (dout_clk),
|
||||
.reb (1'b1),
|
||||
.addrb (dout_raddr),
|
||||
.doutb (dout_rdata_s));
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
@@ -0,0 +1,389 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Version="7" Minor="40" Path="/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/util_rfifo/util_rfifo.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="78982d25bc624452b933f59bbd6b46c6"/>
|
||||
<Option Name="Part" Val="xc7vx485tffg1157-1"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="BoardPart" Val=""/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../library"/>
|
||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../../ghdl/library"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="DSAVendor" Val="xilinx"/>
|
||||
<Option Name="DSANumComputeUnits" Val="60"/>
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||||
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|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="0"/>
|
||||
<Option Name="WTModelSimExportSim" Val="0"/>
|
||||
<Option Name="WTQuestaExportSim" Val="0"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="0"/>
|
||||
<Option Name="WTRivieraExportSim" Val="0"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
<Option Name="SimTypes" Val="bfm"/>
|
||||
<Option Name="SimTypes" Val="tlm"/>
|
||||
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="31">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/../common/ad_mem.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/util_rfifo.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/component.xml">
|
||||
<FileInfo SFType="IPXACT"/>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="util_rfifo"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<File Path="$PPRDIR/util_rfifo_constr.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
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||||
<Config>
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||||
<Option Name="DesignMode" Val="RTL"/>
|
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<Option Name="TopAutoSet" Val="TRUE"/>
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<Option Name="TransportPathDelay" Val="0"/>
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<Option Name="TransportIntDelay" Val="0"/>
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<Option Name="SrcSet" Val="sources_1"/>
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||||
</Config>
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</FileSet>
|
||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
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||||
</Config>
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</FileSet>
|
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</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
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<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
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<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="IES">
|
||||
<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Xcelium">
|
||||
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="VCS">
|
||||
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="10">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
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</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
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<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
|
||||
<Strategy Version="1" Minor="2">
|
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<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
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<MsgAttr Name="Limit" Val="-1"/>
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||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
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<MsgAttr Name="Id" Val="Vivado 12-1790"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
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<MsgAttr Name="ShowRule" Val="1"/>
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<MsgAttr Name="RuleSource" Val="2"/>
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<MsgAttr Name="RuleId" Val="1"/>
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||||
<MsgAttr Name="Author" Val=""/>
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<MsgAttr Name="CreatedTimestamp" Val=""/>
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<MsgAttr Name="StringsToMatch" Val="Evaluation"/>
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<MsgAttr Name="StringsToMatch" Val="features"/>
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||||
<MsgAttr Name="StringsToMatch" Val="should"/>
|
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<MsgAttr Name="StringsToMatch" Val="NOT"/>
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||||
<MsgAttr Name="StringsToMatch" Val="be"/>
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<MsgAttr Name="StringsToMatch" Val="used"/>
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<MsgAttr Name="StringsToMatch" Val="in"/>
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<MsgAttr Name="StringsToMatch" Val="production"/>
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<MsgAttr Name="StringsToMatch" Val="systems."/>
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|
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<MsgRule>
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||||
<MsgAttr Name="RuleType" Val="1"/>
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<MsgAttr Name="Limit" Val="-1"/>
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<MsgAttr Name="NewSeverity" Val="WARNING"/>
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<MsgAttr Name="Id" Val="Place 30-73"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="10"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="axi_spi"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val=""/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
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<MsgAttr Name="RuleId" Val="11"/>
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|
||||
<MsgAttr Name="StringsToMatch" Val="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY"/>
|
||||
</MsgRule>
|
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<MsgRule>
|
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<MsgAttr Name="RuleType" Val="1"/>
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||||
<MsgAttr Name="Limit" Val="-1"/>
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<MsgAttr Name="Id" Val="BD 41-1343"/>
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<MsgAttr Name="Severity" Val="ANY"/>
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<MsgAttr Name="RuleSource" Val="2"/>
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<MsgAttr Name="Note" Val=""/>
|
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<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
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<MsgAttr Name="Limit" Val="-1"/>
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<MsgAttr Name="NewSeverity" Val="WARNING"/>
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<MsgAttr Name="Id" Val="BD 41-1306"/>
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||||
<MsgAttr Name="RuleSource" Val="2"/>
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<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="3"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="ERROR"/>
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||||
<MsgAttr Name="Id" Val="BD 41-1276"/>
|
||||
<MsgAttr Name="Severity" Val="CRITICAL WARNING"/>
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||||
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||||
<MsgAttr Name="RuleSource" Val="2"/>
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||||
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|
||||
<MsgAttr Name="RuleId" Val="4"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-3656"/>
|
||||
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|
||||
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||||
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|
||||
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|
||||
<MsgAttr Name="RuleId" Val="5"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-4623"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="6"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-459"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="7"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Synth 8-3331"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="8"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Designutils 20-3303"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="9"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="HDPYFinalizeIO"/>
|
||||
</MsgRule>
|
||||
<Board/>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
<BootPmcSettings Version="1" Minor="0">
|
||||
<Parameters>
|
||||
<Parameter Name="PMC_CDO.ATTRS.LOADADDR" Value="" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_FB_CLK" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_FREQ" Value="300" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_BUS_WIDTH" Value="x1" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_DATA_MODE" Value="Single" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_FREQ" Value="200" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_SLOT_TYPE" Value="SD 2.0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_FREQ" Value="200" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_SLOT_TYPE" Value="SD 2.0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSPI_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSPI_FREQ" Value="300" Type="string"/>
|
||||
<Parameter Name="BOOT.USB_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SMAP_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SMAP_DATA_WIDTH" Value="32 Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSC_FREQ" Value="33.333" Type="string"/>
|
||||
<Parameter Name="BOOT.SECONDARY.PCIE_ENABLE" Value="0" Type="string"/>
|
||||
</Parameters>
|
||||
</BootPmcSettings>
|
||||
</Project>
|
||||
@@ -0,0 +1,6 @@
|
||||
|
||||
set_false_path -from [get_registers *dout_enable*] -to [get_registers *din_enable_m1*]
|
||||
set_false_path -from [get_registers *dout_req_t*] -to [get_registers *din_req_t_m1*]
|
||||
set_false_path -from [get_registers *dout_init*] -to [get_registers *din_init*]
|
||||
set_false_path -from [get_registers *din_unf_d*] -to [get_registers *dout_unf_m1*]
|
||||
|
||||
@@ -0,0 +1,10 @@
|
||||
|
||||
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *din_enable_m*}]
|
||||
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *din_req_t_m*}]
|
||||
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *dout_unf_m*}]
|
||||
|
||||
set_false_path -from [get_cells -hier -filter {name =~ *dout_enable* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *din_enable_m1* && IS_SEQUENTIAL}]
|
||||
set_false_path -from [get_cells -hier -filter {name =~ *dout_req_t* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *din_req_t_m1* && IS_SEQUENTIAL}]
|
||||
set_false_path -from [get_cells -hier -filter {name =~ *dout_init* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *din_init* && IS_SEQUENTIAL}]
|
||||
set_false_path -from [get_cells -hier -filter {name =~ *din_unf* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *dout_unf_m1* && IS_SEQUENTIAL}]
|
||||
|
||||
@@ -0,0 +1,68 @@
|
||||
|
||||
|
||||
package require qsys
|
||||
source ../scripts/adi_env.tcl
|
||||
source ../scripts/adi_ip_intel.tcl
|
||||
|
||||
ad_ip_create util_rfifo {Utils Read FIFO} util_rfifo_elab
|
||||
ad_ip_files util_rfifo [list\
|
||||
$ad_hdl_dir/library/common/ad_mem.v \
|
||||
util_rfifo.v \
|
||||
util_rfifo_constr.sdc]
|
||||
|
||||
# parameters
|
||||
|
||||
ad_ip_parameter NUM_OF_CHANNELS INTEGER 4
|
||||
ad_ip_parameter DIN_DATA_WIDTH INTEGER 32
|
||||
ad_ip_parameter DOUT_DATA_WIDTH INTEGER 64
|
||||
ad_ip_parameter DIN_ADDRESS_WIDTH INTEGER 8
|
||||
|
||||
# defaults
|
||||
|
||||
ad_interface clock din_clk input 1
|
||||
ad_interface reset-n din_rstn input 1 if_din_clk
|
||||
ad_interface clock dout_clk input 1
|
||||
ad_interface reset dout_rst input 1 if_dout_clk
|
||||
|
||||
add_interface din_0 conduit end
|
||||
add_interface_port din_0 din_enable_0 enable Output 1
|
||||
add_interface_port din_0 din_valid_0 valid Output 1
|
||||
add_interface_port din_0 din_valid_in_0 data_valid Input 1
|
||||
add_interface_port din_0 din_data_0 data Input DIN_DATA_WIDTH
|
||||
set_interface_property din_0 associatedClock if_din_clk
|
||||
set_interface_property din_0 associatedReset none
|
||||
|
||||
add_interface dout_0 conduit end
|
||||
add_interface_port dout_0 dout_enable_0 enable Input 1
|
||||
add_interface_port dout_0 dout_valid_0 valid Input 1
|
||||
add_interface_port dout_0 dout_valid_out_0 data_valid Output 1
|
||||
add_interface_port dout_0 dout_data_0 data Output DOUT_DATA_WIDTH
|
||||
set_interface_property dout_0 associatedClock if_dout_clk
|
||||
set_interface_property dout_0 associatedReset none
|
||||
|
||||
ad_interface signal din_unf input 1 unf
|
||||
ad_interface signal dout_unf output 1 unf
|
||||
|
||||
proc util_rfifo_elab {} {
|
||||
|
||||
for {set n 1} {$n < 8} {incr n} {
|
||||
if {[get_parameter_value NUM_OF_CHANNELS] > $n} {
|
||||
add_interface din_${n} conduit end
|
||||
add_interface_port din_${n} din_enable_${n} enable Output 1
|
||||
add_interface_port din_${n} din_valid_${n} valid Output 1
|
||||
add_interface_port din_${n} din_valid_in_${n} data_valid Input 1
|
||||
add_interface_port din_${n} din_data_${n} data Input DIN_DATA_WIDTH
|
||||
set_interface_property din_${n} associatedClock if_din_clk
|
||||
set_interface_property din_${n} associatedReset none
|
||||
|
||||
add_interface dout_${n} conduit end
|
||||
add_interface_port dout_${n} dout_enable_${n} enable Input 1
|
||||
add_interface_port dout_${n} dout_valid_${n} valid Input 1
|
||||
add_interface_port dout_${n} dout_valid_out_${n} data_valid Output 1
|
||||
add_interface_port dout_${n} dout_data_${n} data Output DOUT_DATA_WIDTH
|
||||
set_interface_property dout_${n} associatedClock if_dout_clk
|
||||
set_interface_property dout_${n} associatedReset none
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@@ -0,0 +1,42 @@
|
||||
# ip
|
||||
|
||||
source ../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
|
||||
adi_ip_create util_rfifo
|
||||
adi_ip_files util_rfifo [list \
|
||||
"$ad_hdl_dir/library/common/ad_mem.v" \
|
||||
"util_rfifo_constr.xdc" \
|
||||
"util_rfifo.v" ]
|
||||
|
||||
adi_ip_properties_lite util_rfifo
|
||||
|
||||
ipx::remove_all_bus_interface [ipx::current_core]
|
||||
set_property driver_value 0 [ipx::get_ports *dout_enable* -of_objects [ipx::current_core]]
|
||||
set_property driver_value 0 [ipx::get_ports *dout_valid* -of_objects [ipx::current_core]]
|
||||
set_property driver_value 0 [ipx::get_ports *din_valid_in* -of_objects [ipx::current_core]]
|
||||
set_property driver_value 0 [ipx::get_ports *din_data* -of_objects [ipx::current_core]]
|
||||
set_property driver_value 0 [ipx::get_ports *din_unf* -of_objects [ipx::current_core]]
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 1} \
|
||||
[ipx::get_ports *_1* -of_objects [ipx::current_core]]
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 2} \
|
||||
[ipx::get_ports *_2* -of_objects [ipx::current_core]]
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 3} \
|
||||
[ipx::get_ports *_3* -of_objects [ipx::current_core]]
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 4} \
|
||||
[ipx::get_ports *_4* -of_objects [ipx::current_core]]
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 5} \
|
||||
[ipx::get_ports *_5* -of_objects [ipx::current_core]]
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 6} \
|
||||
[ipx::get_ports *_6* -of_objects [ipx::current_core]]
|
||||
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 7} \
|
||||
[ipx::get_ports *_7* -of_objects [ipx::current_core]]
|
||||
|
||||
ipx::infer_bus_interface din_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
ipx::infer_bus_interface dout_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
ipx::infer_bus_interface din_rstn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
|
||||
ipx::infer_bus_interface dout_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
|
||||
|
||||
ipx::save_core [ipx::current_core]
|
||||
|
||||
|
||||
@@ -0,0 +1,70 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||
ipgui::add_param $IPINST -name "DIN_ADDRESS_WIDTH" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "DIN_DATA_WIDTH" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "DOUT_DATA_WIDTH" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "NUM_OF_CHANNELS" -parent ${Page_0}
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DIN_ADDRESS_WIDTH { PARAM_VALUE.DIN_ADDRESS_WIDTH } {
|
||||
# Procedure called to update DIN_ADDRESS_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DIN_ADDRESS_WIDTH { PARAM_VALUE.DIN_ADDRESS_WIDTH } {
|
||||
# Procedure called to validate DIN_ADDRESS_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DIN_DATA_WIDTH { PARAM_VALUE.DIN_DATA_WIDTH } {
|
||||
# Procedure called to update DIN_DATA_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DIN_DATA_WIDTH { PARAM_VALUE.DIN_DATA_WIDTH } {
|
||||
# Procedure called to validate DIN_DATA_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DOUT_DATA_WIDTH { PARAM_VALUE.DOUT_DATA_WIDTH } {
|
||||
# Procedure called to update DOUT_DATA_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DOUT_DATA_WIDTH { PARAM_VALUE.DOUT_DATA_WIDTH } {
|
||||
# Procedure called to validate DOUT_DATA_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.NUM_OF_CHANNELS { PARAM_VALUE.NUM_OF_CHANNELS } {
|
||||
# Procedure called to update NUM_OF_CHANNELS when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.NUM_OF_CHANNELS { PARAM_VALUE.NUM_OF_CHANNELS } {
|
||||
# Procedure called to validate NUM_OF_CHANNELS
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.NUM_OF_CHANNELS { MODELPARAM_VALUE.NUM_OF_CHANNELS PARAM_VALUE.NUM_OF_CHANNELS } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.NUM_OF_CHANNELS}] ${MODELPARAM_VALUE.NUM_OF_CHANNELS}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DIN_DATA_WIDTH { MODELPARAM_VALUE.DIN_DATA_WIDTH PARAM_VALUE.DIN_DATA_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DIN_DATA_WIDTH}] ${MODELPARAM_VALUE.DIN_DATA_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DOUT_DATA_WIDTH { MODELPARAM_VALUE.DOUT_DATA_WIDTH PARAM_VALUE.DOUT_DATA_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DOUT_DATA_WIDTH}] ${MODELPARAM_VALUE.DOUT_DATA_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DIN_ADDRESS_WIDTH { MODELPARAM_VALUE.DIN_ADDRESS_WIDTH PARAM_VALUE.DIN_ADDRESS_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DIN_ADDRESS_WIDTH}] ${MODELPARAM_VALUE.DIN_ADDRESS_WIDTH}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user