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josh
2023-04-13 13:33:41 +08:00
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adi_library/util_wfifo/.timestamp_intel
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adi_library/util_wfifo/Makefile
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####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
LIBRARY_NAME := util_wfifo
GENERIC_DEPS += ../common/ad_mem.v
GENERIC_DEPS += util_wfifo.v
XILINX_DEPS += util_wfifo_constr.xdc
XILINX_DEPS += util_wfifo_ip.tcl
INTEL_DEPS += util_wfifo_constr.sdc
INTEL_DEPS += util_wfifo_hw.tcl
include ../scripts/library.mk
adi_library/util_wfifo/component.xml
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adi_library/util_wfifo/util_wfifo.cache/wt/project.wpc
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version:1
6d6f64655f636f756e7465727c42617463684d6f6465:1
eof:
adi_library/util_wfifo/util_wfifo.hw/util_wfifo.lpr
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<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
<labtools version="1" minor="0"/>
adi_library/util_wfifo/util_wfifo.v
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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module util_wfifo #(
parameter NUM_OF_CHANNELS = 4,
parameter DIN_DATA_WIDTH = 32,
parameter DOUT_DATA_WIDTH = 64,
parameter DIN_ADDRESS_WIDTH = 8) (
// d-in interface
input din_rst,
input din_clk,
input din_enable_0,
input din_valid_0,
input [DIN_DATA_WIDTH-1:0] din_data_0,
input din_enable_1,
input din_valid_1,
input [DIN_DATA_WIDTH-1:0] din_data_1,
input din_enable_2,
input din_valid_2,
input [DIN_DATA_WIDTH-1:0] din_data_2,
input din_enable_3,
input din_valid_3,
input [DIN_DATA_WIDTH-1:0] din_data_3,
input din_enable_4,
input din_valid_4,
input [DIN_DATA_WIDTH-1:0] din_data_4,
input din_enable_5,
input din_valid_5,
input [DIN_DATA_WIDTH-1:0] din_data_5,
input din_enable_6,
input din_valid_6,
input [DIN_DATA_WIDTH-1:0] din_data_6,
input din_enable_7,
input din_valid_7,
input [DIN_DATA_WIDTH-1:0] din_data_7,
output reg din_ovf,
// d-out interface
input dout_rstn,
input dout_clk,
output dout_enable_0,
output dout_valid_0,
output [DOUT_DATA_WIDTH-1:0] dout_data_0,
output dout_enable_1,
output dout_valid_1,
output [DOUT_DATA_WIDTH-1:0] dout_data_1,
output dout_enable_2,
output dout_valid_2,
output [DOUT_DATA_WIDTH-1:0] dout_data_2,
output dout_enable_3,
output dout_valid_3,
output [DOUT_DATA_WIDTH-1:0] dout_data_3,
output dout_enable_4,
output dout_valid_4,
output [DOUT_DATA_WIDTH-1:0] dout_data_4,
output dout_enable_5,
output dout_valid_5,
output [DOUT_DATA_WIDTH-1:0] dout_data_5,
output dout_enable_6,
output dout_valid_6,
output [DOUT_DATA_WIDTH-1:0] dout_data_6,
output dout_enable_7,
output dout_valid_7,
output [DOUT_DATA_WIDTH-1:0] dout_data_7,
input dout_ovf);
localparam M_MEM_RATIO = DOUT_DATA_WIDTH/DIN_DATA_WIDTH;
localparam ADDRESS_WIDTH = (DIN_ADDRESS_WIDTH > 4) ? DIN_ADDRESS_WIDTH : 4;
localparam DATA_WIDTH = DOUT_DATA_WIDTH * NUM_OF_CHANNELS;
localparam T_DIN_DATA_WIDTH = DIN_DATA_WIDTH * 8;
localparam T_DOUT_DATA_WIDTH = DOUT_DATA_WIDTH * 8;
// internal registers
reg [(DATA_WIDTH-1):0] din_wdata = 'd0;
reg [ 7:0] din_enable = 'd0;
reg din_wr = 'd0;
reg [(ADDRESS_WIDTH-1):0] din_waddr = 'd0;
reg din_req_t = 'd0;
reg [(ADDRESS_WIDTH-4):0] din_rinit = 'd0;
reg din_ovf_m1 = 'd0;
reg dout_req_t_m1 = 'd0;
reg dout_req_t_m2 = 'd0;
reg dout_req_t_m3 = 'd0;
reg dout_req_t = 'd0;
reg [(ADDRESS_WIDTH-4):0] dout_rinit = 'd0;
reg dout_ovf_d = 'd0;
reg [ 3:0] dout_req_cnt = 'd0;
reg [(ADDRESS_WIDTH-1):0] dout_raddr = 'd8;
reg dout_rd_d = 'd0;
reg dout_valid = 'd0;
reg [ 7:0] dout_enable_m1 = 'd0;
reg [ 7:0] dout_enable = 'd0;
reg [(DATA_WIDTH-1):0] dout_rdata = 'd0;
// internal signals
wire [ 7:0] din_enable_s;
wire [ 7:0] din_valid_s;
wire [(T_DIN_DATA_WIDTH-1):0] din_data_s;
wire dout_req_t_s;
wire [(DATA_WIDTH-1):0] dout_rdata_s;
wire [(T_DOUT_DATA_WIDTH+1):0] dout_data_s;
wire [ 2:0] din_dcnt_s;
// variables
genvar n;
// concat signals, valid_0 must always be active
assign din_enable_s = { din_enable_7, din_enable_6, din_enable_5, din_enable_4,
din_enable_3, din_enable_2, din_enable_1, din_enable_0};
assign din_valid_s = { din_valid_7, din_valid_6, din_valid_5, din_valid_4,
din_valid_3, din_valid_2, din_valid_1, din_valid_0};
assign din_data_s = { din_data_7, din_data_6, din_data_5, din_data_4,
din_data_3, din_data_2, din_data_1, din_data_0};
// simple data transfer-- no ovf/unf handling- read-bw > write-bw (equal will NOT work)
// dout_width >= din_width only-
generate
for (n = 0; n < NUM_OF_CHANNELS; n = n + 1) begin: g_in
if (M_MEM_RATIO == 1) begin
always @(posedge din_clk) begin
if (din_valid_s[n] == 1'b1) begin
din_wdata[((DOUT_DATA_WIDTH*(n+1))-1):(DOUT_DATA_WIDTH*n)] <=
din_data_s[((DIN_DATA_WIDTH*(n+1))-1):(DIN_DATA_WIDTH*n)];
end
end
end else begin
always @(posedge din_clk) begin
if (din_valid_s[n] == 1'b1) begin
din_wdata[((DOUT_DATA_WIDTH*(n+1))-1):(DOUT_DATA_WIDTH*n)] <=
{din_data_s[((DIN_DATA_WIDTH*(n+1))-1):(DIN_DATA_WIDTH*n)],
din_wdata[((DOUT_DATA_WIDTH*(n+1))-1):(DIN_DATA_WIDTH+(DOUT_DATA_WIDTH*n))]};
end
end
end
end
endgenerate
generate
if (M_MEM_RATIO == 1) begin
assign din_dcnt_s = 'b0;
end else begin
reg [ 2:0] din_dcnt = 'd0;
always @(posedge din_clk)
if (din_rst == 1'b1) begin
din_dcnt <= 'd0;
end else begin
if (din_valid_s[0] == 1'b1) begin
din_dcnt <= din_dcnt + 1'b1;
end
end
assign din_dcnt_s = din_dcnt;
end
endgenerate
always @(posedge din_clk) begin
if (din_rst == 1'b1) begin
din_enable <= 8'd0;
din_wr <= 1'd0;
din_waddr <= 'd0;
din_req_t <= 1'd0;
din_rinit <= 'd0;
din_ovf_m1 <= 'd0;
din_ovf <= 'd0;
end else begin
din_enable <= din_enable_s;
case (M_MEM_RATIO)
8: din_wr <= din_valid_s[0] & din_dcnt_s[0] & din_dcnt_s[1] & din_dcnt_s[2];
4: din_wr <= din_valid_s[0] & din_dcnt_s[0] & din_dcnt_s[1];
2: din_wr <= din_valid_s[0] & din_dcnt_s[0];
default: din_wr <= din_valid_s[0];
endcase
if (din_wr == 1'b1) begin
din_waddr <= din_waddr + 1'b1;
end
if ((din_wr == 1'b1) && (din_waddr[2:0] == 3'd7)) begin
din_req_t <= ~din_req_t;
din_rinit <= din_waddr[(ADDRESS_WIDTH-1):3];
end
din_ovf_m1 <= dout_ovf_d;
din_ovf <= din_ovf_m1;
end
end
// read interface (bus expansion and/or clock conversion)
assign dout_req_t_s = dout_req_t_m3 ^ dout_req_t_m2;
always @(posedge dout_clk or negedge dout_rstn) begin
if (dout_rstn == 1'b0) begin
dout_req_t_m1 <= 'd0;
dout_req_t_m2 <= 'd0;
dout_req_t_m3 <= 'd0;
dout_req_t <= 'd0;
dout_rinit <= 'd0;
dout_ovf_d <= 'd0;
end else begin
dout_req_t_m1 <= din_req_t;
dout_req_t_m2 <= dout_req_t_m1;
dout_req_t_m3 <= dout_req_t_m2;
dout_req_t <= dout_req_t_s;
if (dout_req_t_s == 1'b1) begin
dout_rinit <= din_rinit;
end
dout_ovf_d <= dout_ovf;
end
end
always @(posedge dout_clk or negedge dout_rstn) begin
if (dout_rstn == 1'b0) begin
dout_req_cnt <= 'd0;
dout_raddr <= 'd8;
dout_rd_d <= 'd0;
dout_valid <= 'd0;
end else begin
if (dout_req_t == 1'b1) begin
dout_req_cnt <= 4'h8;
dout_raddr <= {dout_rinit, 3'd0};
end else if (dout_req_cnt[3] == 1'b1) begin
dout_req_cnt <= dout_req_cnt + 1'b1;
dout_raddr <= dout_raddr + 1'b1;
end
dout_rd_d <= dout_req_cnt[3];
dout_valid <= dout_rd_d;
end
end
always @(posedge dout_clk or negedge dout_rstn) begin
if (dout_rstn == 1'b0) begin
dout_enable_m1 <= 'd0;
dout_enable <= 'd0;
end else begin
dout_enable_m1 <= din_enable;
dout_enable <= dout_enable_m1;
end
end
always @(posedge dout_clk) begin
dout_rdata <= dout_rdata_s;
end
generate
if (NUM_OF_CHANNELS >= 8) begin
assign dout_data_s = dout_rdata;
end else begin
assign dout_data_s[(T_DOUT_DATA_WIDTH+1):DATA_WIDTH] = 'd0;
assign dout_data_s[(DATA_WIDTH-1):0] = dout_rdata;
end
endgenerate
assign dout_enable_7 = dout_enable[7];
assign dout_valid_7 = dout_valid;
assign dout_data_7 = dout_data_s[((DOUT_DATA_WIDTH*8)-1):(DOUT_DATA_WIDTH*7)];
assign dout_enable_6 = dout_enable[6];
assign dout_valid_6 = dout_valid;
assign dout_data_6 = dout_data_s[((DOUT_DATA_WIDTH*7)-1):(DOUT_DATA_WIDTH*6)];
assign dout_enable_5 = dout_enable[5];
assign dout_valid_5 = dout_valid;
assign dout_data_5 = dout_data_s[((DOUT_DATA_WIDTH*6)-1):(DOUT_DATA_WIDTH*5)];
assign dout_enable_4 = dout_enable[4];
assign dout_valid_4 = dout_valid;
assign dout_data_4 = dout_data_s[((DOUT_DATA_WIDTH*5)-1):(DOUT_DATA_WIDTH*4)];
assign dout_enable_3 = dout_enable[3];
assign dout_valid_3 = dout_valid;
assign dout_data_3 = dout_data_s[((DOUT_DATA_WIDTH*4)-1):(DOUT_DATA_WIDTH*3)];
assign dout_enable_2 = dout_enable[2];
assign dout_valid_2 = dout_valid;
assign dout_data_2 = dout_data_s[((DOUT_DATA_WIDTH*3)-1):(DOUT_DATA_WIDTH*2)];
assign dout_enable_1 = dout_enable[1];
assign dout_valid_1 = dout_valid;
assign dout_data_1 = dout_data_s[((DOUT_DATA_WIDTH*2)-1):(DOUT_DATA_WIDTH*1)];
assign dout_enable_0 = dout_enable[0];
assign dout_valid_0 = dout_valid;
assign dout_data_0 = dout_data_s[((DOUT_DATA_WIDTH*1)-1):(DOUT_DATA_WIDTH*0)];
// instantiations
ad_mem #(.ADDRESS_WIDTH(ADDRESS_WIDTH), .DATA_WIDTH(DATA_WIDTH)) i_mem (
.clka (din_clk),
.wea (din_wr),
.addra (din_waddr),
.dina (din_wdata),
.clkb (dout_clk),
.reb (1'b1),
.addrb (dout_raddr),
.doutb (dout_rdata_s));
endmodule
// ***************************************************************************
// ***************************************************************************
adi_library/util_wfifo/util_wfifo.xpr
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<!-- -->
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
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<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="11"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
<MsgAttr Name="StringsToMatch" Val="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY"/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val="BD 41-1343"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="2"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val="BD 41-1306"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="3"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="ERROR"/>
<MsgAttr Name="Id" Val="BD 41-1276"/>
<MsgAttr Name="Severity" Val="CRITICAL WARNING"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="4"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="IP_Flow 19-3656"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="5"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="IP_Flow 19-4623"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="6"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="IP_Flow 19-459"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="7"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="Synth 8-3331"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="8"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="Designutils 20-3303"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="9"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
<MsgAttr Name="StringsToMatch" Val="HDPYFinalizeIO"/>
</MsgRule>
<Board/>
<DashboardSummary Version="1" Minor="0">
<Dashboards>
<Dashboard Name="default_dashboard">
<Gadgets>
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
</Gadget>
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
</Gadget>
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
</Gadget>
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
</Gadget>
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
</Gadget>
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
</Gadget>
</Gadgets>
</Dashboard>
<CurrentDashboard>default_dashboard</CurrentDashboard>
</Dashboards>
</DashboardSummary>
<BootPmcSettings Version="1" Minor="0">
<Parameters>
<Parameter Name="PMC_CDO.ATTRS.LOADADDR" Value="" Type="string"/>
<Parameter Name="BOOT.PMC.QSPI_ENABLE" Value="0" Type="string"/>
<Parameter Name="BOOT.PMC.QSPI_FB_CLK" Value="0" Type="string"/>
<Parameter Name="BOOT.PMC.QSPI_FREQ" Value="300" Type="string"/>
<Parameter Name="BOOT.PMC.QSPI_BUS_WIDTH" Value="x1" Type="string"/>
<Parameter Name="BOOT.PMC.QSPI_DATA_MODE" Value="Single" Type="string"/>
<Parameter Name="BOOT.PMC.SD0_ENABLE" Value="0" Type="string"/>
<Parameter Name="BOOT.PMC.SD0_FREQ" Value="200" Type="string"/>
<Parameter Name="BOOT.PMC.SD0_SLOT_TYPE" Value="SD 2.0" Type="string"/>
<Parameter Name="BOOT.PMC.SD0_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
<Parameter Name="BOOT.PMC.SD1_ENABLE" Value="0" Type="string"/>
<Parameter Name="BOOT.PMC.SD1_FREQ" Value="200" Type="string"/>
<Parameter Name="BOOT.PMC.SD1_SLOT_TYPE" Value="SD 2.0" Type="string"/>
<Parameter Name="BOOT.PMC.SD1_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
<Parameter Name="BOOT.PMC.OSPI_ENABLE" Value="0" Type="string"/>
<Parameter Name="BOOT.PMC.OSPI_FREQ" Value="300" Type="string"/>
<Parameter Name="BOOT.USB_ENABLE" Value="0" Type="string"/>
<Parameter Name="BOOT.PMC.SMAP_ENABLE" Value="0" Type="string"/>
<Parameter Name="BOOT.PMC.SMAP_DATA_WIDTH" Value="32 Bit" Type="string"/>
<Parameter Name="BOOT.PMC.OSC_FREQ" Value="33.333" Type="string"/>
<Parameter Name="BOOT.SECONDARY.PCIE_ENABLE" Value="0" Type="string"/>
</Parameters>
</BootPmcSettings>
</Project>
adi_library/util_wfifo/util_wfifo_constr.sdc
+6
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set_false_path -from [get_registers *din_enable*] -to [get_registers *dout_enable_m1*]
set_false_path -from [get_registers *din_req_t*] -to [get_registers *dout_req_t_m1*]
set_false_path -from [get_registers *din_rinit*] -to [get_registers *dout_rinit*]
set_false_path -from [get_registers *dout_ovf_d*] -to [get_registers *din_ovf_m1*]
adi_library/util_wfifo/util_wfifo_constr.xdc
+10
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set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *dout_enable_m*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *dout_req_t_m*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *din_ovf_m*}]
set_false_path -from [get_cells -hier -filter {name =~ *din_enable* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *dout_enable_m1* && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *din_req_t* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *dout_req_t_m1* && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *din_rinit* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *dout_rinit* && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *dout_ovf* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *din_ovf_m1* && IS_SEQUENTIAL}]
adi_library/util_wfifo/util_wfifo_hw.tcl
+211
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package require qsys
source ../scripts/adi_env.tcl
source ../scripts/adi_ip_intel.tcl
set_module_property NAME util_wfifo
set_module_property DESCRIPTION "Utils Write FIFO"
set_module_property VERSION 1.0
set_module_property GROUP "Analog Devices"
set_module_property DISPLAY_NAME util_wfifo
set_module_property ELABORATION_CALLBACK p_util_wfifo
# files
add_fileset quartus_synth QUARTUS_SYNTH "" ""
set_fileset_property quartus_synth TOP_LEVEL util_wfifo
add_fileset_file ad_mem.v VERILOG PATH $ad_hdl_dir/library/common/ad_mem.v
add_fileset_file util_wfifo.v VERILOG PATH util_wfifo.v TOP_LEVEL_FILE
add_fileset_file util_wfifo_constr.sdc SDC PATH util_wfifo_constr.sdc
# parameters
add_parameter NUM_OF_CHANNELS INTEGER 0
set_parameter_property NUM_OF_CHANNELS DEFAULT_VALUE 4
set_parameter_property NUM_OF_CHANNELS DISPLAY_NAME NUM_OF_CHANNELS
set_parameter_property NUM_OF_CHANNELS UNITS None
set_parameter_property NUM_OF_CHANNELS HDL_PARAMETER true
add_parameter DIN_DATA_WIDTH INTEGER 0
set_parameter_property DIN_DATA_WIDTH DEFAULT_VALUE 32
set_parameter_property DIN_DATA_WIDTH DISPLAY_NAME DIN_DATA_WIDTH
set_parameter_property DIN_DATA_WIDTH UNITS None
set_parameter_property DIN_DATA_WIDTH HDL_PARAMETER true
add_parameter DOUT_DATA_WIDTH INTEGER 0
set_parameter_property DOUT_DATA_WIDTH DEFAULT_VALUE 64
set_parameter_property DOUT_DATA_WIDTH DISPLAY_NAME DOUT_DATA_WIDTH
set_parameter_property DOUT_DATA_WIDTH UNITS None
set_parameter_property DOUT_DATA_WIDTH HDL_PARAMETER true
add_parameter DIN_ADDRESS_WIDTH INTEGER 0
set_parameter_property DIN_ADDRESS_WIDTH DEFAULT_VALUE 8
set_parameter_property DIN_ADDRESS_WIDTH DISPLAY_NAME DIN_ADDRESS_WIDTH
set_parameter_property DIN_ADDRESS_WIDTH UNITS None
set_parameter_property DIN_ADDRESS_WIDTH HDL_PARAMETER true
# defaults
ad_interface clock din_clk input 1
ad_interface reset din_rst input 1 if_din_clk
ad_interface clock dout_clk input 1
ad_interface reset-n dout_rstn input 1 if_dout_clk
add_interface din_0 conduit end
add_interface_port din_0 din_enable_0 enable Input 1
add_interface_port din_0 din_valid_0 valid Input 1
add_interface_port din_0 din_data_0 data Input DIN_DATA_WIDTH
set_interface_property din_0 associatedClock if_din_clk
set_interface_property din_0 associatedReset none
add_interface dout_0 conduit end
add_interface_port dout_0 dout_enable_0 enable Output 1
add_interface_port dout_0 dout_valid_0 valid Output 1
add_interface_port dout_0 dout_data_0 data Output DOUT_DATA_WIDTH
set_interface_property dout_0 associatedClock if_dout_clk
set_interface_property dout_0 associatedReset none
ad_interface signal din_ovf output 1 ovf
ad_interface signal dout_ovf input 1 ovf
proc p_util_wfifo {} {
if {[get_parameter_value NUM_OF_CHANNELS] > 1} {
add_interface din_1 conduit end
add_interface_port din_1 din_enable_1 enable Input 1
add_interface_port din_1 din_valid_1 valid Input 1
add_interface_port din_1 din_data_1 data Input DIN_DATA_WIDTH
set_interface_property din_1 associatedClock if_din_clk
set_interface_property din_1 associatedReset none
add_interface dout_1 conduit end
add_interface_port dout_1 dout_enable_1 enable Output 1
add_interface_port dout_1 dout_valid_1 valid Output 1
add_interface_port dout_1 dout_data_1 data Output DOUT_DATA_WIDTH
set_interface_property dout_1 associatedClock if_dout_clk
set_interface_property dout_1 associatedReset none
}
if {[get_parameter_value NUM_OF_CHANNELS] > 2} {
add_interface din_2 conduit end
add_interface_port din_2 din_enable_2 enable Input 1
add_interface_port din_2 din_valid_2 valid Input 1
add_interface_port din_2 din_data_2 data Input DIN_DATA_WIDTH
set_interface_property din_2 associatedClock if_din_clk
set_interface_property din_2 associatedReset none
add_interface dout_2 conduit end
add_interface_port dout_2 dout_enable_2 enable Output 1
add_interface_port dout_2 dout_valid_2 valid Output 1
add_interface_port dout_2 dout_data_2 data Output DOUT_DATA_WIDTH
set_interface_property dout_2 associatedClock if_dout_clk
set_interface_property dout_2 associatedReset none
}
if {[get_parameter_value NUM_OF_CHANNELS] > 3} {
add_interface din_3 conduit end
add_interface_port din_3 din_enable_3 enable Input 1
add_interface_port din_3 din_valid_3 valid Input 1
add_interface_port din_3 din_data_3 data Input DIN_DATA_WIDTH
set_interface_property din_3 associatedClock if_din_clk
set_interface_property din_3 associatedReset none
add_interface dout_3 conduit end
add_interface_port dout_3 dout_enable_3 enable Output 1
add_interface_port dout_3 dout_valid_3 valid Output 1
add_interface_port dout_3 dout_data_3 data Output DOUT_DATA_WIDTH
set_interface_property dout_3 associatedClock if_dout_clk
set_interface_property dout_3 associatedReset none
}
if {[get_parameter_value NUM_OF_CHANNELS] > 4} {
add_interface din_4 conduit end
add_interface_port din_4 din_enable_4 enable Input 1
add_interface_port din_4 din_valid_4 valid Input 1
add_interface_port din_4 din_data_4 data Input DIN_DATA_WIDTH
set_interface_property din_4 associatedClock if_din_clk
set_interface_property din_4 associatedReset none
add_interface dout_4 conduit end
add_interface_port dout_4 dout_enable_4 enable Output 1
add_interface_port dout_4 dout_valid_4 valid Output 1
add_interface_port dout_4 dout_data_4 data Output DOUT_DATA_WIDTH
set_interface_property dout_4 associatedClock if_dout_clk
set_interface_property dout_4 associatedReset none
}
if {[get_parameter_value NUM_OF_CHANNELS] > 5} {
add_interface din_5 conduit end
add_interface_port din_5 din_enable_5 enable Input 1
add_interface_port din_5 din_valid_5 valid Input 1
add_interface_port din_5 din_data_5 data Input DIN_DATA_WIDTH
set_interface_property din_5 associatedClock if_din_clk
set_interface_property din_5 associatedReset none
add_interface dout_5 conduit end
add_interface_port dout_5 dout_enable_5 enable Output 1
add_interface_port dout_5 dout_valid_5 valid Output 1
add_interface_port dout_5 dout_data_5 data Output DOUT_DATA_WIDTH
set_interface_property dout_5 associatedClock if_dout_clk
set_interface_property dout_5 associatedReset none
}
if {[get_parameter_value NUM_OF_CHANNELS] > 6} {
add_interface din_6 conduit end
add_interface_port din_6 din_enable_6 enable Input 1
add_interface_port din_6 din_valid_6 valid Input 1
add_interface_port din_6 din_data_6 data Input DIN_DATA_WIDTH
set_interface_property din_6 associatedClock if_din_clk
set_interface_property din_6 associatedReset none
add_interface dout_6 conduit end
add_interface_port dout_6 dout_enable_6 enable Output 1
add_interface_port dout_6 dout_valid_6 valid Output 1
add_interface_port dout_6 dout_data_6 data Output DOUT_DATA_WIDTH
set_interface_property dout_6 associatedClock if_dout_clk
set_interface_property dout_6 associatedReset none
}
if {[get_parameter_value NUM_OF_CHANNELS] > 7} {
add_interface din_7 conduit end
add_interface_port din_7 din_enable_7 enable Input 1
add_interface_port din_7 din_valid_7 valid Input 1
add_interface_port din_7 din_data_7 data Input DIN_DATA_WIDTH
set_interface_property din_7 associatedClock if_din_clk
set_interface_property din_7 associatedReset none
add_interface dout_7 conduit end
add_interface_port dout_7 dout_enable_7 enable Output 1
add_interface_port dout_7 dout_valid_7 valid Output 1
add_interface_port dout_7 dout_data_7 data Output DOUT_DATA_WIDTH
set_interface_property dout_7 associatedClock if_dout_clk
set_interface_property dout_7 associatedReset none
}
}
adi_library/util_wfifo/util_wfifo_ip.tcl
+41
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# ip
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
adi_ip_create util_wfifo
adi_ip_files util_wfifo [list \
"$ad_hdl_dir/library/common/ad_mem.v" \
"util_wfifo_constr.xdc" \
"util_wfifo.v" ]
adi_ip_properties_lite util_wfifo
ipx::remove_all_bus_interface [ipx::current_core]
set_property driver_value 0 [ipx::get_ports *din_enable* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *din_valid* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *din_data* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dout_ovf* -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 1} \
[ipx::get_ports *_1* -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 2} \
[ipx::get_ports *_2* -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 3} \
[ipx::get_ports *_3* -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 4} \
[ipx::get_ports *_4* -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 5} \
[ipx::get_ports *_5* -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 6} \
[ipx::get_ports *_6* -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 7} \
[ipx::get_ports *_7* -of_objects [ipx::current_core]]
ipx::infer_bus_interface din_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface din_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface dout_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface dout_rstn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::save_core [ipx::current_core]
adi_library/util_wfifo/xgui/util_wfifo_v1_0.tcl
+70
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# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
ipgui::add_param $IPINST -name "Component_Name"
#Adding Page
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
ipgui::add_param $IPINST -name "DIN_ADDRESS_WIDTH" -parent ${Page_0}
ipgui::add_param $IPINST -name "DIN_DATA_WIDTH" -parent ${Page_0}
ipgui::add_param $IPINST -name "DOUT_DATA_WIDTH" -parent ${Page_0}
ipgui::add_param $IPINST -name "NUM_OF_CHANNELS" -parent ${Page_0}
}
proc update_PARAM_VALUE.DIN_ADDRESS_WIDTH { PARAM_VALUE.DIN_ADDRESS_WIDTH } {
# Procedure called to update DIN_ADDRESS_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.DIN_ADDRESS_WIDTH { PARAM_VALUE.DIN_ADDRESS_WIDTH } {
# Procedure called to validate DIN_ADDRESS_WIDTH
return true
}
proc update_PARAM_VALUE.DIN_DATA_WIDTH { PARAM_VALUE.DIN_DATA_WIDTH } {
# Procedure called to update DIN_DATA_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.DIN_DATA_WIDTH { PARAM_VALUE.DIN_DATA_WIDTH } {
# Procedure called to validate DIN_DATA_WIDTH
return true
}
proc update_PARAM_VALUE.DOUT_DATA_WIDTH { PARAM_VALUE.DOUT_DATA_WIDTH } {
# Procedure called to update DOUT_DATA_WIDTH when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.DOUT_DATA_WIDTH { PARAM_VALUE.DOUT_DATA_WIDTH } {
# Procedure called to validate DOUT_DATA_WIDTH
return true
}
proc update_PARAM_VALUE.NUM_OF_CHANNELS { PARAM_VALUE.NUM_OF_CHANNELS } {
# Procedure called to update NUM_OF_CHANNELS when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.NUM_OF_CHANNELS { PARAM_VALUE.NUM_OF_CHANNELS } {
# Procedure called to validate NUM_OF_CHANNELS
return true
}
proc update_MODELPARAM_VALUE.NUM_OF_CHANNELS { MODELPARAM_VALUE.NUM_OF_CHANNELS PARAM_VALUE.NUM_OF_CHANNELS } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.NUM_OF_CHANNELS}] ${MODELPARAM_VALUE.NUM_OF_CHANNELS}
}
proc update_MODELPARAM_VALUE.DIN_DATA_WIDTH { MODELPARAM_VALUE.DIN_DATA_WIDTH PARAM_VALUE.DIN_DATA_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.DIN_DATA_WIDTH}] ${MODELPARAM_VALUE.DIN_DATA_WIDTH}
}
proc update_MODELPARAM_VALUE.DOUT_DATA_WIDTH { MODELPARAM_VALUE.DOUT_DATA_WIDTH PARAM_VALUE.DOUT_DATA_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.DOUT_DATA_WIDTH}] ${MODELPARAM_VALUE.DOUT_DATA_WIDTH}
}
proc update_MODELPARAM_VALUE.DIN_ADDRESS_WIDTH { MODELPARAM_VALUE.DIN_ADDRESS_WIDTH PARAM_VALUE.DIN_ADDRESS_WIDTH } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.DIN_ADDRESS_WIDTH}] ${MODELPARAM_VALUE.DIN_ADDRESS_WIDTH}
}