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first commit after restructuring

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josh
2023-04-13 13:33:41 +08:00
commit 3c2cd0ba29
15090 changed files with 6794217 additions and 0 deletions
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adi_library/xilinx/util_adxcvr/Makefile
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####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
LIBRARY_NAME := util_adxcvr
XILINX_DEPS += bd/bd.tcl
XILINX_DEPS += util_adxcvr.v
XILINX_DEPS += util_adxcvr_constr.xdc
XILINX_DEPS += util_adxcvr_ip.tcl
XILINX_DEPS += util_adxcvr_xch.v
XILINX_DEPS += util_adxcvr_xcm.v
XILINX_DEPS += ../../interfaces/if_xcvr_ch.xml
XILINX_DEPS += ../../interfaces/if_xcvr_ch_rtl.xml
XILINX_DEPS += ../../interfaces/if_xcvr_cm.xml
XILINX_DEPS += ../../interfaces/if_xcvr_cm_rtl.xml
XILINX_INTERFACE_DEPS += interfaces
include ../../scripts/library.mk
adi_library/xilinx/util_adxcvr/bd/bd.tcl
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proc init {cellpath otherInfo} {
set ip [get_bd_cells $cellpath]
bd::mark_propagate_override $ip " \
XCVR_TYPE CH_HSPMUX PPF0_CFG RXPI_CFG0 RXPI_CFG1 RTX_BUF_CML_CTRL \
QPLL_LPF RXCDR_CFG3_GEN2 RXCDR_CFG3_GEN3 RXCDR_CFG3_GEN4 TX_PI_BIASSET"
adi_auto_assign_device_spec $cellpath
}
# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)
proc adi_auto_assign_device_spec {cellpath} {
set ip [get_bd_cells $cellpath]
set ip_param_list [list_property $ip]
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
set parent_dir "../"
for {set x 1} {$x<=4} {incr x} {
set linkname ${ip_path}${parent_dir}scripts/adi_xilinx_device_info_enc.tcl
if { [file exists $linkname] } {
source ${ip_path}${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl
break
}
append parent_dir "../"
}
# Find predefindes auto assignable parameters
foreach i $auto_set_param_list {
if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
set val [adi_device_spec $cellpath $i]
set_property CONFIG.$i $val $ip
}
}
# Find predefindes auto assignable/overwritable parameters
foreach i $auto_set_param_list_overwritable {
if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
set val [adi_device_spec $cellpath $i]
set_property CONFIG.$i $val $ip
}
}
}
adi_library/xilinx/util_adxcvr/component.xml
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adi_library/xilinx/util_adxcvr/gui/util_adxcvr_v1_0.gtcl
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# This file is automatically written. Do not modify.
proc gen_USERPARAMETER_PPF0_CFG_VALUE {XCVR_TYPE } {expr [format "0x%x" [expr {$XCVR_TYPE == 9} ? 0x800 : 0x600]]}
proc gen_USERPARAMETER_QPLL_LPF_VALUE {XCVR_TYPE } {expr [format "0x%x" [expr {$XCVR_TYPE == 9} ? 0x37f : 0x137]]}
proc gen_USERPARAMETER_CH_HSPMUX_VALUE {XCVR_TYPE } {expr [format "0x%x" [expr {$XCVR_TYPE == 8} ? 0x2424 : {$XCVR_TYPE == 9} ? 0x2020 : 0x0]]}
proc gen_USERPARAMETER_RXPI_CFG0_VALUE {XCVR_TYPE } {expr [format "0x%x" [expr {$XCVR_TYPE == 8} ? 0x2 : {$XCVR_TYPE == 9} ? 0x100 : 0x0]]}
proc gen_USERPARAMETER_RXPI_CFG1_VALUE {XCVR_TYPE } {expr [format "0x%x" [expr {$XCVR_TYPE == 8} ? 0x15 : 0x0]]}
proc gen_USERPARAMETER_RTX_BUF_CML_CTRL_VALUE {XCVR_TYPE } {expr [format "0x%x" [expr {$XCVR_TYPE == 9} ? 0x3 : 0x0]]}
proc gen_USERPARAMETER_TX_PI_BIASSET_VALUE {XCVR_TYPE } {expr {$XCVR_TYPE == 9} ? 0 : 1}
proc gen_USERPARAMETER_RXCDR_CFG3_GEN2_VALUE {XCVR_TYPE } {expr [format "0x%x" [expr {$XCVR_TYPE == 9} ? 0x12 : 0x1a ]]}
proc gen_USERPARAMETER_RXCDR_CFG3_GEN4_VALUE {XCVR_TYPE } {expr [format "0x%x" [expr {$XCVR_TYPE == 9} ? 0x12 : 0x24 ]]}
adi_library/xilinx/util_adxcvr/util_adxcvr.cache/wt/project.wpc
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version:1
6d6f64655f636f756e7465727c42617463684d6f6465:1
eof:
adi_library/xilinx/util_adxcvr/util_adxcvr.hw/util_adxcvr.lpr
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<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
<labtools version="1" minor="0"/>
adi_library/xilinx/util_adxcvr/util_adxcvr.v
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adi_library/xilinx/util_adxcvr/util_adxcvr.xpr
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<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="40" Path="/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/xilinx/util_adxcvr/util_adxcvr.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="8300a5efc297470d8fab49fdec746631"/>
<Option Name="Part" Val="xc7vx485tffg1157-1"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="CompiledLibDirXSim" Val=""/>
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
<Option Name="BoardPart" Val=""/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="ProjectType" Val="Default"/>
<Option Name="IPRepoPath" Val="$PPRDIR/../../../library"/>
<Option Name="IPRepoPath" Val="$PPRDIR/../../../../ghdl/library"/>
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
<Option Name="IPCachePermission" Val="read"/>
<Option Name="IPCachePermission" Val="write"/>
<Option Name="EnableCoreContainer" Val="FALSE"/>
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSAVendor" Val="xilinx"/>
<Option Name="DSANumComputeUnits" Val="60"/>
<Option Name="WTXSimLaunchSim" Val="0"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="0"/>
<Option Name="WTModelSimExportSim" Val="0"/>
<Option Name="WTQuestaExportSim" Val="0"/>
<Option Name="WTIesExportSim" Val="0"/>
<Option Name="WTVcsExportSim" Val="0"/>
<Option Name="WTRivieraExportSim" Val="0"/>
<Option Name="WTActivehdlExportSim" Val="0"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
<Option Name="XSimTraceLimit" Val="65536"/>
<Option Name="SimTypes" Val="rtl"/>
<Option Name="SimTypes" Val="bfm"/>
<Option Name="SimTypes" Val="tlm"/>
<Option Name="SimTypes" Val="tlm_dpi"/>
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
</Configuration>
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/util_adxcvr_xch.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/util_adxcvr_xcm.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/util_adxcvr.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../scripts/adi_xilinx_device_info_enc.tcl">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/bd/bd.tcl">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/component.xml">
<FileInfo SFType="IPXACT"/>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="util_adxcvr"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
<Filter Type="Constrs"/>
<File Path="$PPRDIR/util_adxcvr_constr.xdc">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>
<Option Name="SrcSet" Val="sources_1"/>
</Config>
</FileSet>
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
<Filter Type="Utils"/>
<Config>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">
<Option Name="Description" Val="Vivado Simulator"/>
<Option Name="CompiledLib" Val="0"/>
</Simulator>
<Simulator Name="ModelSim">
<Option Name="Description" Val="ModelSim Simulator"/>
</Simulator>
<Simulator Name="Questa">
<Option Name="Description" Val="Questa Advanced Simulator"/>
</Simulator>
<Simulator Name="IES">
<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
</Simulator>
<Simulator Name="Xcelium">
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
</Simulator>
<Simulator Name="VCS">
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
</Simulator>
<Simulator Name="Riviera">
<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="10">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
</Runs>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val="Vivado 12-1790"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="1"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
<MsgAttr Name="StringsToMatch" Val="Evaluation"/>
<MsgAttr Name="StringsToMatch" Val="features"/>
<MsgAttr Name="StringsToMatch" Val="should"/>
<MsgAttr Name="StringsToMatch" Val="NOT"/>
<MsgAttr Name="StringsToMatch" Val="be"/>
<MsgAttr Name="StringsToMatch" Val="used"/>
<MsgAttr Name="StringsToMatch" Val="in"/>
<MsgAttr Name="StringsToMatch" Val="production"/>
<MsgAttr Name="StringsToMatch" Val="systems."/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val="Place 30-73"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="10"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
<MsgAttr Name="StringsToMatch" Val="axi_spi"/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val=""/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="11"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
<MsgAttr Name="StringsToMatch" Val="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY"/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val="BD 41-1343"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="2"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="WARNING"/>
<MsgAttr Name="Id" Val="BD 41-1306"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="3"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="ERROR"/>
<MsgAttr Name="Id" Val="BD 41-1276"/>
<MsgAttr Name="Severity" Val="CRITICAL WARNING"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="4"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="IP_Flow 19-3656"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="5"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="IP_Flow 19-4623"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="6"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="IP_Flow 19-459"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="7"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="Synth 8-3331"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="8"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
</MsgRule>
<MsgRule>
<MsgAttr Name="RuleType" Val="1"/>
<MsgAttr Name="Limit" Val="-1"/>
<MsgAttr Name="NewSeverity" Val="INFO"/>
<MsgAttr Name="Id" Val="Designutils 20-3303"/>
<MsgAttr Name="Severity" Val="ANY"/>
<MsgAttr Name="ShowRule" Val="1"/>
<MsgAttr Name="RuleSource" Val="2"/>
<MsgAttr Name="StringIsRegExp" Val="0"/>
<MsgAttr Name="RuleId" Val="9"/>
<MsgAttr Name="Note" Val=""/>
<MsgAttr Name="Author" Val=""/>
<MsgAttr Name="CreatedTimestamp" Val=""/>
<MsgAttr Name="StringsToMatch" Val="HDPYFinalizeIO"/>
</MsgRule>
<Board/>
<DashboardSummary Version="1" Minor="0">
<Dashboards>
<Dashboard Name="default_dashboard">
<Gadgets>
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
</Gadget>
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
</Gadget>
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
</Gadget>
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
</Gadget>
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
</Gadget>
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
</Gadget>
</Gadgets>
</Dashboard>
<CurrentDashboard>default_dashboard</CurrentDashboard>
</Dashboards>
</DashboardSummary>
<BootPmcSettings Version="1" Minor="0">
<Parameters>
<Parameter Name="PMC_CDO.ATTRS.LOADADDR" Value="" Type="string"/>
<Parameter Name="BOOT.PMC.QSPI_ENABLE" Value="0" Type="string"/>
<Parameter Name="BOOT.PMC.QSPI_FB_CLK" Value="0" Type="string"/>
<Parameter Name="BOOT.PMC.QSPI_FREQ" Value="300" Type="string"/>
<Parameter Name="BOOT.PMC.QSPI_BUS_WIDTH" Value="x1" Type="string"/>
<Parameter Name="BOOT.PMC.QSPI_DATA_MODE" Value="Single" Type="string"/>
<Parameter Name="BOOT.PMC.SD0_ENABLE" Value="0" Type="string"/>
<Parameter Name="BOOT.PMC.SD0_FREQ" Value="200" Type="string"/>
<Parameter Name="BOOT.PMC.SD0_SLOT_TYPE" Value="SD 2.0" Type="string"/>
<Parameter Name="BOOT.PMC.SD0_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
<Parameter Name="BOOT.PMC.SD1_ENABLE" Value="0" Type="string"/>
<Parameter Name="BOOT.PMC.SD1_FREQ" Value="200" Type="string"/>
<Parameter Name="BOOT.PMC.SD1_SLOT_TYPE" Value="SD 2.0" Type="string"/>
<Parameter Name="BOOT.PMC.SD1_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
<Parameter Name="BOOT.PMC.OSPI_ENABLE" Value="0" Type="string"/>
<Parameter Name="BOOT.PMC.OSPI_FREQ" Value="300" Type="string"/>
<Parameter Name="BOOT.USB_ENABLE" Value="0" Type="string"/>
<Parameter Name="BOOT.PMC.SMAP_ENABLE" Value="0" Type="string"/>
<Parameter Name="BOOT.PMC.SMAP_DATA_WIDTH" Value="32 Bit" Type="string"/>
<Parameter Name="BOOT.PMC.OSC_FREQ" Value="33.333" Type="string"/>
<Parameter Name="BOOT.SECONDARY.PCIE_ENABLE" Value="0" Type="string"/>
</Parameters>
</BootPmcSettings>
</Project>
adi_library/xilinx/util_adxcvr/util_adxcvr_constr.xdc
+11
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@@ -0,0 +1,11 @@
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_rx_rst_done*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_tx_rst_done*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *rx_rate*}]
set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *tx_rate*}]
set_false_path -to [get_cells -hier -filter {name =~ *up_rx_rst_done_m1_reg && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *up_tx_rst_done_m1_reg && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *rx_rate_m1_reg* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *tx_rate_m1_reg* && IS_SEQUENTIAL}]
adi_library/xilinx/util_adxcvr/util_adxcvr_ip.tcl
+865
View File
@@ -0,0 +1,865 @@
## AUTO GENERATED BY util_adxcvr.pl, DO NOT MODIFY!
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
adi_ip_create util_adxcvr
adi_ip_files util_adxcvr [list \
"$ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl" \
"util_adxcvr_constr.xdc" \
"util_adxcvr_xcm.v" \
"util_adxcvr_xch.v" \
"util_adxcvr.v" \
"bd/bd.tcl" ]
adi_ip_properties_lite util_adxcvr
adi_ip_bd util_adxcvr "bd/bd.tcl"
ipx::remove_all_bus_interface [ipx::current_core]
ipx::infer_bus_interface up_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface cpll_ref_clk_0 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface cpll_ref_clk_1 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface cpll_ref_clk_2 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface cpll_ref_clk_3 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface cpll_ref_clk_4 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface cpll_ref_clk_5 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface cpll_ref_clk_6 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface cpll_ref_clk_7 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface cpll_ref_clk_8 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface cpll_ref_clk_9 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface cpll_ref_clk_10 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface cpll_ref_clk_11 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface cpll_ref_clk_12 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface cpll_ref_clk_13 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface cpll_ref_clk_14 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface cpll_ref_clk_15 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface qpll_ref_clk_0 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface qpll_ref_clk_4 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface qpll_ref_clk_8 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface qpll_ref_clk_12 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface rx_out_clk_0 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface rx_out_clk_1 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface rx_out_clk_2 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface rx_out_clk_3 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface rx_out_clk_4 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface rx_out_clk_5 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface rx_out_clk_6 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface rx_out_clk_7 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface rx_out_clk_8 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface rx_out_clk_9 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface rx_out_clk_10 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface rx_out_clk_11 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface rx_out_clk_12 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface rx_out_clk_13 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface rx_out_clk_14 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface rx_out_clk_15 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface tx_out_clk_0 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface tx_out_clk_1 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface tx_out_clk_2 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface tx_out_clk_3 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface tx_out_clk_4 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface tx_out_clk_5 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface tx_out_clk_6 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface tx_out_clk_7 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface tx_out_clk_8 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface tx_out_clk_9 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface tx_out_clk_10 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface tx_out_clk_11 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface tx_out_clk_12 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface tx_out_clk_13 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface tx_out_clk_14 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface tx_out_clk_15 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface rx_clk_0 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface rx_clk_1 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface rx_clk_2 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface rx_clk_3 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface rx_clk_4 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface rx_clk_5 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface rx_clk_6 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface rx_clk_7 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface rx_clk_8 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface rx_clk_9 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface rx_clk_10 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface rx_clk_11 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface rx_clk_12 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface rx_clk_13 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface rx_clk_14 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface rx_clk_15 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface tx_clk_0 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface tx_clk_1 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface tx_clk_2 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface tx_clk_3 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface tx_clk_4 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface tx_clk_5 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface tx_clk_6 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface tx_clk_7 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface tx_clk_8 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface tx_clk_9 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface tx_clk_10 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface tx_clk_11 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface tx_clk_12 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface tx_clk_13 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface tx_clk_14 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface tx_clk_15 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface up_rstn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface up_rx_rst_0 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface up_rx_rst_1 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface up_rx_rst_2 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface up_rx_rst_3 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface up_rx_rst_4 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface up_rx_rst_5 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface up_rx_rst_6 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface up_rx_rst_7 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface up_rx_rst_8 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface up_rx_rst_9 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface up_rx_rst_10 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface up_rx_rst_11 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface up_rx_rst_12 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface up_rx_rst_13 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface up_rx_rst_14 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface up_rx_rst_15 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface up_tx_rst_0 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface up_tx_rst_1 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface up_tx_rst_2 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface up_tx_rst_3 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface up_tx_rst_4 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface up_tx_rst_5 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface up_tx_rst_6 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface up_tx_rst_7 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface up_tx_rst_8 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface up_tx_rst_9 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface up_tx_rst_10 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface up_tx_rst_11 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface up_tx_rst_12 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface up_tx_rst_13 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface up_tx_rst_14 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface up_tx_rst_15 xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
set_property driver_value 0 [ipx::get_ports -filter "direction==in" -of_objects [ipx::current_core]]
for {set n 0} {$n < 16} {incr n} {
if {($n%4) == 0} {
adi_if_infer_bus analog.com:interface:if_xcvr_cm slave up_cm_${n} [list \
"enb up_cm_enb_${n} "\
"addr up_cm_addr_${n} "\
"wr up_cm_wr_${n} "\
"wdata up_cm_wdata_${n} "\
"rdata up_cm_rdata_${n} "\
"ready up_cm_ready_${n} "]
}
adi_if_infer_bus analog.com:interface:if_xcvr_cm slave up_es_${n} [list \
"enb up_es_enb_${n} "\
"addr up_es_addr_${n} "\
"wr up_es_wr_${n} "\
"wdata up_es_wdata_${n} "\
"rdata up_es_rdata_${n} "\
"reset up_es_reset_${n} "\
"ready up_es_ready_${n} "]
adi_if_infer_bus analog.com:interface:if_xcvr_ch slave up_rx_${n} [list \
"pll_locked up_rx_pll_locked_${n} "\
"rst up_rx_rst_${n} "\
"user_ready up_rx_user_ready_${n} "\
"rst_done up_rx_rst_done_${n} "\
"lpm_dfe_n up_rx_lpm_dfe_n_${n} "\
"rate up_rx_rate_${n} "\
"sys_clk_sel up_rx_sys_clk_sel_${n} "\
"out_clk_sel up_rx_out_clk_sel_${n} "\
"enb up_rx_enb_${n} "\
"addr up_rx_addr_${n} "\
"wr up_rx_wr_${n} "\
"wdata up_rx_wdata_${n} "\
"rdata up_rx_rdata_${n} "\
"ready up_rx_ready_${n} "]
adi_if_infer_bus analog.com:interface:if_xcvr_ch slave up_tx_${n} [list \
"pll_locked up_tx_pll_locked_${n} "\
"rst up_tx_rst_${n} "\
"user_ready up_tx_user_ready_${n} "\
"rst_done up_tx_rst_done_${n} "\
"lpm_dfe_n up_tx_lpm_dfe_n_${n} "\
"rate up_tx_rate_${n} "\
"sys_clk_sel up_tx_sys_clk_sel_${n} "\
"out_clk_sel up_tx_out_clk_sel_${n} "\
"tx_diffctrl up_tx_diffctrl_${n} "\
"tx_postcursor up_tx_postcursor_${n} "\
"tx_precursor up_tx_precursor_${n} "\
"enb up_tx_enb_${n} "\
"addr up_tx_addr_${n} "\
"wr up_tx_wr_${n} "\
"wdata up_tx_wdata_${n} "\
"rdata up_tx_rdata_${n} "\
"ready up_tx_ready_${n} "]
ipx::add_bus_interface rx_${n} [ipx::current_core]
set_property abstraction_type_vlnv xilinx.com:display_jesd204:jesd204_rx_bus_rtl:1.0 \
[ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]
set_property bus_type_vlnv xilinx.com:display_jesd204:jesd204_rx_bus:1.0 \
[ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]
set_property interface_mode master [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]
ipx::add_port_map rxcharisk [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]
set_property physical_name rx_charisk_${n} [ipx::get_port_maps rxcharisk -of_objects \
[ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]]
ipx::add_port_map rxnotintable [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]
set_property physical_name rx_notintable_${n} [ipx::get_port_maps rxnotintable -of_objects \
[ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]]
ipx::add_port_map rxdisperr [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]
set_property physical_name rx_disperr_${n} [ipx::get_port_maps rxdisperr -of_objects \
[ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]]
ipx::add_port_map rxdata [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]
set_property physical_name rx_data_${n} [ipx::get_port_maps rxdata -of_objects \
[ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]]
ipx::add_bus_interface tx_${n} [ipx::current_core]
set_property abstraction_type_vlnv xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0 \
[ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]]
set_property bus_type_vlnv xilinx.com:display_jesd204:jesd204_tx_bus:1.0 \
[ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]]
set_property interface_mode slave [ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]]
ipx::add_port_map txcharisk [ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]]
set_property physical_name tx_charisk_${n} [ipx::get_port_maps txcharisk -of_objects \
[ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]]]
ipx::add_port_map txdata [ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]]
set_property physical_name tx_data_${n} [ipx::get_port_maps txdata -of_objects \
[ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]]]
}
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0} \
[ipx::get_bus_interfaces up_es_0 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0} \
[ipx::get_bus_interfaces up_rx_0 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0} \
[ipx::get_bus_interfaces rx_0 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0} \
[ipx::get_ports rx_*0* -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0} \
[ipx::get_ports up_rx_rst_0 -of_objects [ipx::current_core]] \
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0} \
[ipx::get_bus_interfaces up_tx_0 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0} \
[ipx::get_bus_interfaces tx_0 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0} \
[ipx::get_ports tx_*0* -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0} \
[ipx::get_ports up_tx_rst_0 -of_objects [ipx::current_core]] \
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0) or \
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0)} \
[ipx::get_ports cpll_ref_clk_0 -of_objects [ipx::current_core]] \
[ipx::get_ports up_cpll_rst_0 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0) or \
(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0)} \
[ipx::get_ports qpll_ref_clk_0 -of_objects [ipx::current_core]] \
[ipx::get_ports up_qpll_rst_0 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0) or \
(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0)} \
[ipx::get_bus_interfaces up_cm_0 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1} \
[ipx::get_bus_interfaces up_es_1 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1} \
[ipx::get_bus_interfaces up_rx_1 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1} \
[ipx::get_bus_interfaces rx_1 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1} \
[ipx::get_ports rx_*1* -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1} \
[ipx::get_ports up_rx_rst_1 -of_objects [ipx::current_core]] \
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 1} \
[ipx::get_bus_interfaces up_tx_1 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 1} \
[ipx::get_bus_interfaces tx_1 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 1} \
[ipx::get_ports tx_*1* -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 1} \
[ipx::get_ports up_tx_rst_1 -of_objects [ipx::current_core]] \
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 1) or \
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1)} \
[ipx::get_ports cpll_ref_clk_1 -of_objects [ipx::current_core]] \
[ipx::get_ports up_cpll_rst_1 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2} \
[ipx::get_bus_interfaces up_es_2 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2} \
[ipx::get_bus_interfaces up_rx_2 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2} \
[ipx::get_bus_interfaces rx_2 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2} \
[ipx::get_ports rx_*2* -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2} \
[ipx::get_ports up_rx_rst_2 -of_objects [ipx::current_core]] \
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 2} \
[ipx::get_bus_interfaces up_tx_2 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 2} \
[ipx::get_bus_interfaces tx_2 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 2} \
[ipx::get_ports tx_*2* -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 2} \
[ipx::get_ports up_tx_rst_2 -of_objects [ipx::current_core]] \
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 2) or \
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2)} \
[ipx::get_ports cpll_ref_clk_2 -of_objects [ipx::current_core]] \
[ipx::get_ports up_cpll_rst_2 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3} \
[ipx::get_bus_interfaces up_es_3 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3} \
[ipx::get_bus_interfaces up_rx_3 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3} \
[ipx::get_bus_interfaces rx_3 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3} \
[ipx::get_ports rx_*3* -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3} \
[ipx::get_ports up_rx_rst_3 -of_objects [ipx::current_core]] \
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 3} \
[ipx::get_bus_interfaces up_tx_3 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 3} \
[ipx::get_bus_interfaces tx_3 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 3} \
[ipx::get_ports tx_*3* -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 3} \
[ipx::get_ports up_tx_rst_3 -of_objects [ipx::current_core]] \
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 3) or \
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3)} \
[ipx::get_ports cpll_ref_clk_3 -of_objects [ipx::current_core]] \
[ipx::get_ports up_cpll_rst_3 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4} \
[ipx::get_bus_interfaces up_es_4 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4} \
[ipx::get_bus_interfaces up_rx_4 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4} \
[ipx::get_bus_interfaces rx_4 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4} \
[ipx::get_ports rx_*4* -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4} \
[ipx::get_ports up_rx_rst_4 -of_objects [ipx::current_core]] \
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4} \
[ipx::get_bus_interfaces up_tx_4 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4} \
[ipx::get_bus_interfaces tx_4 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4} \
[ipx::get_ports tx_*4* -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4} \
[ipx::get_ports up_tx_rst_4 -of_objects [ipx::current_core]] \
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4) or \
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4)} \
[ipx::get_ports cpll_ref_clk_4 -of_objects [ipx::current_core]] \
[ipx::get_ports up_cpll_rst_4 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4) or \
(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4)} \
[ipx::get_ports qpll_ref_clk_4 -of_objects [ipx::current_core]] \
[ipx::get_ports up_qpll_rst_4 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4) or \
(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4)} \
[ipx::get_bus_interfaces up_cm_4 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5} \
[ipx::get_bus_interfaces up_es_5 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5} \
[ipx::get_bus_interfaces up_rx_5 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5} \
[ipx::get_bus_interfaces rx_5 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5} \
[ipx::get_ports rx_*5* -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5} \
[ipx::get_ports up_rx_rst_5 -of_objects [ipx::current_core]] \
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 5} \
[ipx::get_bus_interfaces up_tx_5 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 5} \
[ipx::get_bus_interfaces tx_5 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 5} \
[ipx::get_ports tx_*5* -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 5} \
[ipx::get_ports up_tx_rst_5 -of_objects [ipx::current_core]] \
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 5) or \
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5)} \
[ipx::get_ports cpll_ref_clk_5 -of_objects [ipx::current_core]] \
[ipx::get_ports up_cpll_rst_5 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6} \
[ipx::get_bus_interfaces up_es_6 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6} \
[ipx::get_bus_interfaces up_rx_6 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6} \
[ipx::get_bus_interfaces rx_6 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6} \
[ipx::get_ports rx_*6* -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6} \
[ipx::get_ports up_rx_rst_6 -of_objects [ipx::current_core]] \
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 6} \
[ipx::get_bus_interfaces up_tx_6 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 6} \
[ipx::get_bus_interfaces tx_6 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 6} \
[ipx::get_ports tx_*6* -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 6} \
[ipx::get_ports up_tx_rst_6 -of_objects [ipx::current_core]] \
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 6) or \
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6)} \
[ipx::get_ports cpll_ref_clk_6 -of_objects [ipx::current_core]] \
[ipx::get_ports up_cpll_rst_6 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7} \
[ipx::get_bus_interfaces up_es_7 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7} \
[ipx::get_bus_interfaces up_rx_7 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7} \
[ipx::get_bus_interfaces rx_7 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7} \
[ipx::get_ports rx_*7* -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7} \
[ipx::get_ports up_rx_rst_7 -of_objects [ipx::current_core]] \
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 7} \
[ipx::get_bus_interfaces up_tx_7 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 7} \
[ipx::get_bus_interfaces tx_7 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 7} \
[ipx::get_ports tx_*7* -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 7} \
[ipx::get_ports up_tx_rst_7 -of_objects [ipx::current_core]] \
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 7) or \
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7)} \
[ipx::get_ports cpll_ref_clk_7 -of_objects [ipx::current_core]] \
[ipx::get_ports up_cpll_rst_7 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8} \
[ipx::get_bus_interfaces up_es_8 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8} \
[ipx::get_bus_interfaces up_rx_8 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8} \
[ipx::get_bus_interfaces rx_8 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8} \
[ipx::get_ports rx_*8* -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8} \
[ipx::get_ports up_rx_rst_8 -of_objects [ipx::current_core]] \
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8} \
[ipx::get_bus_interfaces up_tx_8 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8} \
[ipx::get_bus_interfaces tx_8 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8} \
[ipx::get_ports tx_*8* -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8} \
[ipx::get_ports up_tx_rst_8 -of_objects [ipx::current_core]] \
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8) or \
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8)} \
[ipx::get_ports cpll_ref_clk_8 -of_objects [ipx::current_core]] \
[ipx::get_ports up_cpll_rst_8 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8) or \
(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8)} \
[ipx::get_ports qpll_ref_clk_8 -of_objects [ipx::current_core]] \
[ipx::get_ports up_qpll_rst_8 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8) or \
(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8)} \
[ipx::get_bus_interfaces up_cm_8 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9} \
[ipx::get_bus_interfaces up_es_9 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9} \
[ipx::get_bus_interfaces up_rx_9 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9} \
[ipx::get_bus_interfaces rx_9 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9} \
[ipx::get_ports rx_*9* -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9} \
[ipx::get_ports up_rx_rst_9 -of_objects [ipx::current_core]] \
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 9} \
[ipx::get_bus_interfaces up_tx_9 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 9} \
[ipx::get_bus_interfaces tx_9 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 9} \
[ipx::get_ports tx_*9* -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 9} \
[ipx::get_ports up_tx_rst_9 -of_objects [ipx::current_core]] \
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 9) or \
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9)} \
[ipx::get_ports cpll_ref_clk_9 -of_objects [ipx::current_core]] \
[ipx::get_ports up_cpll_rst_9 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10} \
[ipx::get_bus_interfaces up_es_10 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10} \
[ipx::get_bus_interfaces up_rx_10 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10} \
[ipx::get_bus_interfaces rx_10 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10} \
[ipx::get_ports rx_*10* -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10} \
[ipx::get_ports up_rx_rst_10 -of_objects [ipx::current_core]] \
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 10} \
[ipx::get_bus_interfaces up_tx_10 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 10} \
[ipx::get_bus_interfaces tx_10 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 10} \
[ipx::get_ports tx_*10* -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 10} \
[ipx::get_ports up_tx_rst_10 -of_objects [ipx::current_core]] \
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 10) or \
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10)} \
[ipx::get_ports cpll_ref_clk_10 -of_objects [ipx::current_core]] \
[ipx::get_ports up_cpll_rst_10 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11} \
[ipx::get_bus_interfaces up_es_11 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11} \
[ipx::get_bus_interfaces up_rx_11 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11} \
[ipx::get_bus_interfaces rx_11 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11} \
[ipx::get_ports rx_*11* -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11} \
[ipx::get_ports up_rx_rst_11 -of_objects [ipx::current_core]] \
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 11} \
[ipx::get_bus_interfaces up_tx_11 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 11} \
[ipx::get_bus_interfaces tx_11 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 11} \
[ipx::get_ports tx_*11* -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 11} \
[ipx::get_ports up_tx_rst_11 -of_objects [ipx::current_core]] \
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 11) or \
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11)} \
[ipx::get_ports cpll_ref_clk_11 -of_objects [ipx::current_core]] \
[ipx::get_ports up_cpll_rst_11 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12} \
[ipx::get_bus_interfaces up_es_12 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12} \
[ipx::get_bus_interfaces up_rx_12 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12} \
[ipx::get_bus_interfaces rx_12 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12} \
[ipx::get_ports rx_*12* -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12} \
[ipx::get_ports up_rx_rst_12 -of_objects [ipx::current_core]] \
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12} \
[ipx::get_bus_interfaces up_tx_12 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12} \
[ipx::get_bus_interfaces tx_12 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12} \
[ipx::get_ports tx_*12* -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12} \
[ipx::get_ports up_tx_rst_12 -of_objects [ipx::current_core]] \
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12) or \
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12)} \
[ipx::get_ports cpll_ref_clk_12 -of_objects [ipx::current_core]] \
[ipx::get_ports up_cpll_rst_12 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12) or \
(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12)} \
[ipx::get_ports qpll_ref_clk_12 -of_objects [ipx::current_core]] \
[ipx::get_ports up_qpll_rst_12 -of_objects [ipx::current_core]]
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12) or \
(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12)} \
[ipx::get_bus_interfaces up_cm_12 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13} \
[ipx::get_bus_interfaces up_es_13 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13} \
[ipx::get_bus_interfaces up_rx_13 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13} \
[ipx::get_bus_interfaces rx_13 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13} \
[ipx::get_ports rx_*13* -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13} \
[ipx::get_ports up_rx_rst_13 -of_objects [ipx::current_core]] \
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 13} \
[ipx::get_bus_interfaces up_tx_13 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 13} \
[ipx::get_bus_interfaces tx_13 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 13} \
[ipx::get_ports tx_*13* -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 13} \
[ipx::get_ports up_tx_rst_13 -of_objects [ipx::current_core]] \
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 13) or \
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13)} \
[ipx::get_ports cpll_ref_clk_13 -of_objects [ipx::current_core]] \
[ipx::get_ports up_cpll_rst_13 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14} \
[ipx::get_bus_interfaces up_es_14 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14} \
[ipx::get_bus_interfaces up_rx_14 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14} \
[ipx::get_bus_interfaces rx_14 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14} \
[ipx::get_ports rx_*14* -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14} \
[ipx::get_ports up_rx_rst_14 -of_objects [ipx::current_core]] \
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 14} \
[ipx::get_bus_interfaces up_tx_14 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 14} \
[ipx::get_bus_interfaces tx_14 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 14} \
[ipx::get_ports tx_*14* -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 14} \
[ipx::get_ports up_tx_rst_14 -of_objects [ipx::current_core]] \
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 14) or \
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14)} \
[ipx::get_ports cpll_ref_clk_14 -of_objects [ipx::current_core]] \
[ipx::get_ports up_cpll_rst_14 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15} \
[ipx::get_bus_interfaces up_es_15 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15} \
[ipx::get_bus_interfaces up_rx_15 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15} \
[ipx::get_bus_interfaces rx_15 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15} \
[ipx::get_ports rx_*15* -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15} \
[ipx::get_ports up_rx_rst_15 -of_objects [ipx::current_core]] \
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 15} \
[ipx::get_bus_interfaces up_tx_15 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 15} \
[ipx::get_bus_interfaces tx_15 -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 15} \
[ipx::get_ports tx_*15* -of_objects [ipx::current_core]]
set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 15} \
[ipx::get_ports up_tx_rst_15 -of_objects [ipx::current_core]] \
set_property enablement_dependency \
{(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 15) or \
(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15)} \
[ipx::get_ports cpll_ref_clk_15 -of_objects [ipx::current_core]] \
[ipx::get_ports up_cpll_rst_15 -of_objects [ipx::current_core]]
adi_add_auto_fpga_spec_params
set cc [ipx::current_core]
set param [ipx::get_user_parameters CH_HSPMUX -of_objects $cc]
set_property -dict [list \
value_tcl_expr {[format "0x%x" [expr {$XCVR_TYPE == 8} ? 0x2424 : \
{$XCVR_TYPE == 9} ? 0x2020 : 0x0]]} \
] $param
set param [ipx::get_user_parameters PPF0_CFG -of_objects $cc]
set_property -dict [list \
value_tcl_expr {[format "0x%x" [expr {$XCVR_TYPE == 9} ? 0x800 : 0x600]]} \
] $param
set param [ipx::get_user_parameters RXPI_CFG0 -of_objects $cc]
set_property -dict [list \
value_tcl_expr {[format "0x%x" [expr {$XCVR_TYPE == 8} ? 0x2 : \
{$XCVR_TYPE == 9} ? 0x100 : 0x0]]} \
] $param
set param [ipx::get_user_parameters RXPI_CFG1 -of_objects $cc]
set_property -dict [list \
value_tcl_expr {[format "0x%x" [expr {$XCVR_TYPE == 8} ? 0x15 : 0x0]]} \
] $param
set param [ipx::get_user_parameters RTX_BUF_CML_CTRL -of_objects $cc]
set_property -dict [list \
value_tcl_expr {[format "0x%x" [expr {$XCVR_TYPE == 9} ? 0x3 : 0x0]]} \
] $param
set param [ipx::get_user_parameters QPLL_LPF -of_objects $cc]
set_property -dict [list \
value_tcl_expr {[format "0x%x" [expr {$XCVR_TYPE == 9} ? 0x37f : 0x137]]} \
] $param
set param [ipx::get_user_parameters RXCDR_CFG3_GEN2 -of_objects $cc]
set_property -dict [list \
value_tcl_expr {[format "0x%x" [expr {$XCVR_TYPE == 9} ? 0x12 : 0x1a ]]} \
] $param
set param [ipx::get_user_parameters RXCDR_CFG3_GEN4 -of_objects $cc]
set_property -dict [list \
value_tcl_expr {[format "0x%x" [expr {$XCVR_TYPE == 9} ? 0x12 : 0x24 ]]} \
] $param
set param [ipx::get_user_parameters TX_PI_BIASSET -of_objects $cc]
set_property -dict [list \
value_tcl_expr {expr {$XCVR_TYPE == 9} ? 0 : 1} \
] $param
ipx::create_xgui_files [ipx::current_core]
ipx::save_core [ipx::current_core]
adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v
+3287
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adi_library/xilinx/util_adxcvr/util_adxcvr_xcm.v
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@@ -0,0 +1,743 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ps
module util_adxcvr_xcm #(
// parameters
parameter integer XCVR_TYPE = 0,
parameter integer QPLL_REFCLK_DIV = 1,
parameter integer QPLL_FBDIV_RATIO = 1,
parameter [15:0] POR_CFG = 16'b0000000000000110,
parameter [15:0] PPF0_CFG = 16'b0000011000000000,
parameter [26:0] QPLL_CFG = 27'h0680181,
parameter [ 9:0] QPLL_FBDIV = 10'b0000110000,
parameter [15:0] QPLL_CFG0 = 16'b0011001100011100,
parameter [15:0] QPLL_CFG1 = 16'b1101000000111000,
parameter [15:0] QPLL_CFG1_G3 = 16'b1101000000111000,
parameter [15:0] QPLL_CFG2 = 16'b0000111111000000,
parameter [15:0] QPLL_CFG2_G3 = 16'b0000111111000000,
parameter [15:0] QPLL_CFG3 = 16'b0000000100100000,
parameter [15:0] QPLL_CFG4 = 16'b0000000000000011,
parameter [15:0] QPLL_CP_G3 = 10'b0000011111,
parameter [15:0] QPLL_LPF = 10'b0100110111,
parameter [15:0] QPLL_CP = 10'b0001111111
) (
// reset and clocks
input qpll_ref_clk,
input qpll_sel,
output qpll2ch_clk,
output qpll2ch_ref_clk,
output qpll2ch_locked,
output qpll1_clk,
output qpll1_ref_clk,
output qpll1_locked,
// drp interface
input up_rstn,
input up_clk,
input up_qpll_rst,
input up_cm_enb,
input [11:0] up_cm_addr,
input up_cm_wr,
input [15:0] up_cm_wdata,
output [15:0] up_cm_rdata,
output up_cm_ready);
localparam GTXE2_TRANSCEIVERS = 2;
localparam GTHE3_TRANSCEIVERS = 5;
localparam GTHE4_TRANSCEIVERS = 8;
localparam GTYE4_TRANSCEIVERS = 9;
// internal registers
reg up_enb_int = 'd0;
reg [11:0] up_addr_int = 'd0;
reg up_wr_int = 'd0;
reg [15:0] up_wdata_int = 'd0;
reg [15:0] up_rdata_int = 'd0;
reg up_ready_int = 'd0;
reg up_sel_int = 'd0;
// internal signals
wire [15:0] up_rdata_s;
wire up_ready_s;
// drp access
assign up_cm_rdata = up_rdata_int;
assign up_cm_ready = up_ready_int;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_enb_int <= 1'd0;
up_addr_int <= 12'd0;
up_wr_int <= 1'd0;
up_wdata_int <= 16'd0;
up_rdata_int <= 16'd0;
up_ready_int <= 1'd0;
up_sel_int <= 1'b0;
end else begin
if (up_cm_enb == 1'b1) begin
up_enb_int <= up_cm_enb;
up_addr_int <= up_cm_addr;
up_wr_int <= up_cm_wr;
up_wdata_int <= up_cm_wdata;
end else begin
up_enb_int <= 1'd0;
up_addr_int <= 12'd0;
up_wr_int <= 1'd0;
up_wdata_int <= 16'd0;
end
if (up_cm_enb == 1'b1) begin
up_sel_int <= 1'b1;
end else if (up_ready_s == 1'b1) begin
up_sel_int <= 1'b0;
end
if (up_sel_int == 1'b1) begin
up_ready_int <= up_ready_s;
up_rdata_int <= up_rdata_s;
end else begin
up_ready_int <= 1'b0;
up_rdata_int <= 'h00;
end
end
end
// instantiations
generate
if (XCVR_TYPE == GTXE2_TRANSCEIVERS) begin
assign qpll1_locked = 1'b0;
assign qpll1_clk = 1'b0;
assign qpll1_ref_clk = 1'b0;
GTXE2_COMMON #(
.BIAS_CFG (64'h0000040000001000),
.COMMON_CFG (32'h00000000),
.IS_DRPCLK_INVERTED (1'b0),
.IS_GTGREFCLK_INVERTED (1'b0),
.IS_QPLLLOCKDETCLK_INVERTED (1'b0),
.QPLL_CFG (QPLL_CFG),
.QPLL_CLKOUT_CFG (4'b0000),
.QPLL_COARSE_FREQ_OVRD (6'b010000),
.QPLL_COARSE_FREQ_OVRD_EN (1'b0),
.QPLL_CP (10'b0000011111),
.QPLL_CP_MONITOR_EN (1'b0),
.QPLL_DMONITOR_SEL (1'b0),
.QPLL_FBDIV (QPLL_FBDIV),
.QPLL_FBDIV_MONITOR_EN (1'b0),
.QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO),
.QPLL_INIT_CFG (24'h000006),
.QPLL_LOCK_CFG (16'h21E8),
.QPLL_LPF (4'b1111),
.QPLL_REFCLK_DIV (QPLL_REFCLK_DIV),
.SIM_QPLLREFCLK_SEL (3'b001),
.SIM_RESET_SPEEDUP ("TRUE"),
.SIM_VERSION ("4.0"))
i_gtxe2_common (
.QPLLDMONITOR (),
.QPLLFBCLKLOST (),
.REFCLKOUTMONITOR (),
.BGBYPASSB (1'h1),
.BGMONITORENB (1'h1),
.BGPDB (1'h1),
.BGRCALOVRD (5'h1f),
.DRPADDR (up_addr_int[7:0]),
.DRPCLK (up_clk),
.DRPDI (up_wdata_int),
.DRPDO (up_rdata_s),
.DRPEN (up_enb_int),
.DRPRDY (up_ready_s),
.DRPWE (up_wr_int),
.GTGREFCLK (1'h0),
.GTNORTHREFCLK0 (1'h0),
.GTNORTHREFCLK1 (1'h0),
.GTREFCLK0 (qpll_ref_clk),
.GTREFCLK1 (1'h0),
.GTSOUTHREFCLK0 (1'h0),
.GTSOUTHREFCLK1 (1'h0),
.PMARSVD (8'h0),
.QPLLLOCK (qpll2ch_locked),
.QPLLLOCKDETCLK (up_clk),
.QPLLLOCKEN (1'h1),
.QPLLOUTCLK (qpll2ch_clk),
.QPLLOUTREFCLK (qpll2ch_ref_clk),
.QPLLOUTRESET (1'h0),
.QPLLPD (1'h0),
.QPLLREFCLKLOST (),
.QPLLREFCLKSEL (3'h1),
.QPLLRESET (up_qpll_rst),
.QPLLRSVD1 (16'h0),
.QPLLRSVD2 (5'h1f),
.RCALENB (1'h1));
end
endgenerate
generate
if (XCVR_TYPE == GTHE3_TRANSCEIVERS) begin
GTHE3_COMMON #(
.BIAS_CFG0 (16'h0000),
.BIAS_CFG1 (16'h0000),
.BIAS_CFG2 (16'h0000),
.BIAS_CFG3 (16'h0040),
.BIAS_CFG4 (16'h0000),
.BIAS_CFG_RSVD (10'b0000000000),
.COMMON_CFG0 (16'h0000),
.COMMON_CFG1 (16'h0000),
.POR_CFG (16'h0004),
.QPLL0_CFG0 (16'h321c),
.QPLL0_CFG1 (16'h1018),
.QPLL0_CFG1_G3 (16'h1018),
.QPLL0_CFG2 (16'h0048),
.QPLL0_CFG2_G3 (16'h0048),
.QPLL0_CFG3 (16'h0120),
.QPLL0_CFG4 (16'h0000),
.QPLL0_CP (10'b0000011111),
.QPLL0_CP_G3 (10'b1111111111),
.QPLL0_FBDIV (QPLL_FBDIV),
.QPLL0_FBDIV_G3 (80),
.QPLL0_INIT_CFG0 (16'h02b2),
.QPLL0_INIT_CFG1 (8'h00),
.QPLL0_LOCK_CFG (16'h21e8),
.QPLL0_LOCK_CFG_G3 (16'h21e8),
.QPLL0_LPF (10'b1111111111),
.QPLL0_LPF_G3 (10'b0000010101),
.QPLL0_REFCLK_DIV (QPLL_REFCLK_DIV),
.QPLL0_SDM_CFG0 (16'b0000000000000000),
.QPLL0_SDM_CFG1 (16'b0000000000000000),
.QPLL0_SDM_CFG2 (16'b0000000000000000),
.QPLL1_CFG0 (16'h321c),
.QPLL1_CFG1 (16'h1018),
.QPLL1_CFG1_G3 (16'h1018),
.QPLL1_CFG2 (16'h0040),
.QPLL1_CFG2_G3 (16'h0040),
.QPLL1_CFG3 (16'h0120),
.QPLL1_CFG4 (16'h0000),
.QPLL1_CP (10'b0000011111),
.QPLL1_CP_G3 (10'b1111111111),
.QPLL1_FBDIV (QPLL_FBDIV),
.QPLL1_FBDIV_G3 (80),
.QPLL1_INIT_CFG0 (16'h02b2),
.QPLL1_INIT_CFG1 (8'h00),
.QPLL1_LOCK_CFG (16'h21e8),
.QPLL1_LOCK_CFG_G3 (16'h21e8),
.QPLL1_LPF (10'b1111111111),
.QPLL1_LPF_G3 (10'b0000010101),
.QPLL1_REFCLK_DIV (QPLL_REFCLK_DIV),
.QPLL1_SDM_CFG0 (16'b0000000000000000),
.QPLL1_SDM_CFG1 (16'b0000000000000000),
.QPLL1_SDM_CFG2 (16'b0000000000000000),
.RSVD_ATTR0 (16'h0000),
.RSVD_ATTR1 (16'h0000),
.RSVD_ATTR2 (16'h0000),
.RSVD_ATTR3 (16'h0000),
.RXRECCLKOUT0_SEL (2'b00),
.RXRECCLKOUT1_SEL (2'b00),
.SARC_EN (1'b1),
.SARC_SEL (1'b0),
.SDM0DATA1_0 (16'b0000000000000000),
.SDM0DATA1_1 (9'b000000000),
.SDM0INITSEED0_0 (16'b0000000000000000),
.SDM0INITSEED0_1 (9'b000000000),
.SDM0_DATA_PIN_SEL (1'b0),
.SDM0_WIDTH_PIN_SEL (1'b0),
.SDM1DATA1_0 (16'b0000000000000000),
.SDM1DATA1_1 (9'b000000000),
.SDM1INITSEED0_0 (16'b0000000000000000),
.SDM1INITSEED0_1 (9'b000000000),
.SDM1_DATA_PIN_SEL (1'b0),
.SDM1_WIDTH_PIN_SEL (1'b0),
.SIM_MODE ("FAST"),
.SIM_RESET_SPEEDUP ("TRUE"),
.SIM_VERSION (2))
i_gthe3_common (
.BGBYPASSB (1'h1),
.BGMONITORENB (1'h1),
.BGPDB (1'h1),
.BGRCALOVRD (5'h1f),
.BGRCALOVRDENB (1'h1),
.DRPADDR (up_addr_int[8:0]),
.DRPCLK (up_clk),
.DRPDI (up_wdata_int),
.DRPDO (up_rdata_s),
.DRPEN (up_enb_int),
.DRPRDY (up_ready_s),
.DRPWE (up_wr_int),
.GTGREFCLK0 (1'h0),
.GTGREFCLK1 (1'h0),
.GTNORTHREFCLK00 (1'h0),
.GTNORTHREFCLK01 (1'h0),
.GTNORTHREFCLK10 (1'h0),
.GTNORTHREFCLK11 (1'h0),
.GTREFCLK00 (qpll_ref_clk),
.GTREFCLK01 (1'h0),
.GTREFCLK10 (1'h0),
.GTREFCLK11 (1'h0),
.GTSOUTHREFCLK00 (1'h0),
.GTSOUTHREFCLK01 (1'h0),
.GTSOUTHREFCLK10 (1'h0),
.GTSOUTHREFCLK11 (1'h0),
.PMARSVD0 (8'h0),
.PMARSVD1 (8'h0),
.PMARSVDOUT0 (),
.PMARSVDOUT1 (),
.QPLL0CLKRSVD0 (1'h0),
.QPLL0CLKRSVD1 (1'h0),
.QPLL0FBCLKLOST (),
.QPLL0LOCK (qpll2ch_locked),
.QPLL0LOCKDETCLK (up_clk),
.QPLL0LOCKEN (1'h1),
.QPLL0OUTCLK (qpll2ch_clk),
.QPLL0OUTREFCLK (qpll2ch_ref_clk),
.QPLL0PD (1'h0),
.QPLL0REFCLKLOST (),
.QPLL0REFCLKSEL (3'h1),
.QPLL0RESET (up_qpll_rst),
.QPLL1CLKRSVD0 (1'h0),
.QPLL1CLKRSVD1 (1'h0),
.QPLL1FBCLKLOST (),
.QPLL1LOCK (qpll1_locked),
.QPLL1LOCKDETCLK (up_clk),
.QPLL1LOCKEN (1'h1),
.QPLL1OUTCLK (qpll1_clk),
.QPLL1OUTREFCLK (qpll1_ref_clk),
.QPLL1PD (~qpll_sel),
.QPLL1REFCLKLOST (),
.QPLL1REFCLKSEL (3'h1),
.QPLL1RESET (up_qpll_rst),
.QPLLDMONITOR0 (),
.QPLLDMONITOR1 (),
.QPLLRSVD1 (8'h0),
.QPLLRSVD2 (5'h0),
.QPLLRSVD3 (5'h0),
.QPLLRSVD4 (8'h0),
.RCALENB (1'h1),
.REFCLKOUTMONITOR0 (),
.REFCLKOUTMONITOR1 (),
.RXRECCLK0_SEL (),
.RXRECCLK1_SEL ());
end
endgenerate
generate
if (XCVR_TYPE == GTHE4_TRANSCEIVERS) begin
GTHE4_COMMON #(
.AEN_QPLL0_FBDIV (1'b1),
.AEN_QPLL1_FBDIV (1'b1),
.AEN_SDM0TOGGLE (1'b0),
.AEN_SDM1TOGGLE (1'b0),
.A_SDM0TOGGLE (1'b0),
.A_SDM1DATA_HIGH (9'b000000000),
.A_SDM1DATA_LOW (16'b0000000000000000),
.A_SDM1TOGGLE (1'b0),
.BIAS_CFG0 (16'b0000000000000000),
.BIAS_CFG1 (16'b0000000000000000),
.BIAS_CFG2 (16'b0000000100100100),
.BIAS_CFG3 (16'b0000000001000001),
.BIAS_CFG4 (16'b0000000000010000),
.BIAS_CFG_RSVD (16'b0000000000000000),
.COMMON_CFG0 (16'b0000000000000000),
.COMMON_CFG1 (16'b0000000000000000),
.POR_CFG (POR_CFG),
.PPF0_CFG (PPF0_CFG),
.PPF1_CFG (16'b0000011000000000),
.QPLL0CLKOUT_RATE ("HALF"),
.QPLL0_CFG0 (QPLL_CFG0),
.QPLL0_CFG1 (QPLL_CFG1),
.QPLL0_CFG1_G3 (QPLL_CFG1_G3),
.QPLL0_CFG2 (QPLL_CFG2),
.QPLL0_CFG2_G3 (QPLL_CFG2_G3),
.QPLL0_CFG3 (QPLL_CFG3),
.QPLL0_CFG4 (QPLL_CFG4),
.QPLL0_CP (QPLL_CP),
.QPLL0_CP_G3 (QPLL_CP_G3),
.QPLL0_FBDIV (QPLL_FBDIV),
.QPLL0_FBDIV_G3 (160),
.QPLL0_INIT_CFG0 (16'b0000001010110010),
.QPLL0_INIT_CFG1 (8'b00000000),
.QPLL0_LOCK_CFG (16'b0010010111101000),
.QPLL0_LOCK_CFG_G3 (16'b0010010111101000),
.QPLL0_LPF (QPLL_LPF),
.QPLL0_LPF_G3 (10'b0111010101),
.QPLL0_PCI_EN (1'b0),
.QPLL0_RATE_SW_USE_DRP (1'b1),
.QPLL0_REFCLK_DIV (QPLL_REFCLK_DIV),
.QPLL0_SDM_CFG0 (16'b0000000010000000),
.QPLL0_SDM_CFG1 (16'b0000000000000000),
.QPLL0_SDM_CFG2 (16'b0000000000000000),
.QPLL1CLKOUT_RATE ("HALF"),
.QPLL1_CFG0 (QPLL_CFG0),
.QPLL1_CFG1 (QPLL_CFG1),
.QPLL1_CFG1_G3 (QPLL_CFG1_G3),
.QPLL1_CFG2 (QPLL_CFG2),
.QPLL1_CFG2_G3 (QPLL_CFG2_G3),
.QPLL1_CFG3 (QPLL_CFG3),
.QPLL1_CFG4 (QPLL_CFG4),
.QPLL1_CP (10'b1111111111),
.QPLL1_CP_G3 (10'b0011111111),
.QPLL1_FBDIV (QPLL_FBDIV),
.QPLL1_FBDIV_G3 (80),
.QPLL1_INIT_CFG0 (16'b0000001010110010),
.QPLL1_INIT_CFG1 (8'b00000000),
.QPLL1_LOCK_CFG (16'b0010010111101000),
.QPLL1_LOCK_CFG_G3 (16'b0010010111101000),
.QPLL1_LPF (10'b0100110101),
.QPLL1_LPF_G3 (10'b0111010100),
.QPLL1_PCI_EN (1'b0),
.QPLL1_RATE_SW_USE_DRP (1'b1),
.QPLL1_REFCLK_DIV (QPLL_REFCLK_DIV),
.QPLL1_SDM_CFG0 (16'b0000000010000000),
.QPLL1_SDM_CFG1 (16'b0000000000000000),
.QPLL1_SDM_CFG2 (16'b0000000000000000),
.RSVD_ATTR0 (16'b0000000000000000),
.RSVD_ATTR1 (16'b0000000000000000),
.RSVD_ATTR2 (16'b0000000000000000),
.RSVD_ATTR3 (16'b0000000000000000),
.RXRECCLKOUT0_SEL (2'b00),
.RXRECCLKOUT1_SEL (2'b00),
.SARC_ENB (1'b0),
.SARC_SEL (1'b0),
.SDM0INITSEED0_0 (16'b0000000100010001),
.SDM0INITSEED0_1 (9'b000010001),
.SDM1INITSEED0_0 (16'b0000000100010001),
.SDM1INITSEED0_1 (9'b000010001),
.SIM_MODE ("FAST"),
.SIM_RESET_SPEEDUP ("TRUE"))
i_gthe4_common (
.BGBYPASSB (1'd1),
.BGMONITORENB (1'd1),
.BGPDB (1'd1),
.BGRCALOVRD (5'b11111),
.BGRCALOVRDENB (1'd1),
.DRPADDR ({4'd0, up_addr_int}),
.DRPCLK (up_clk),
.DRPDI (up_wdata_int),
.DRPDO (up_rdata_s),
.DRPEN (up_enb_int),
.DRPRDY (up_ready_s),
.DRPWE (up_wr_int),
.GTGREFCLK0 (1'd0),
.GTGREFCLK1 (1'd0),
.GTNORTHREFCLK00 (1'd0),
.GTNORTHREFCLK01 (1'd0),
.GTNORTHREFCLK10 (1'd0),
.GTNORTHREFCLK11 (1'd0),
.GTREFCLK00 (qpll_ref_clk),
.GTREFCLK01 (qpll_ref_clk),
.GTREFCLK10 (1'd0),
.GTREFCLK11 (1'd0),
.GTSOUTHREFCLK00 (1'd0),
.GTSOUTHREFCLK01 (1'd0),
.GTSOUTHREFCLK10 (1'd0),
.GTSOUTHREFCLK11 (1'd0),
.PCIERATEQPLL0 (3'd0),
.PCIERATEQPLL1 (3'd0),
.PMARSVD0 (8'd0),
.PMARSVD1 (8'd0),
.PMARSVDOUT0 (),
.PMARSVDOUT1 (),
.QPLL0CLKRSVD0 (1'd0),
.QPLL0CLKRSVD1 (1'd0),
.QPLL0FBCLKLOST (),
.QPLL0FBDIV (8'd0),
.QPLL0LOCK (qpll2ch_locked),
.QPLL0LOCKDETCLK (up_clk),
.QPLL0LOCKEN (1'd1),
.QPLL0OUTCLK (qpll2ch_clk),
.QPLL0OUTREFCLK (qpll2ch_ref_clk),
.QPLL0PD (qpll_sel),
.QPLL0REFCLKLOST (),
.QPLL0REFCLKSEL (3'b001),
.QPLL0RESET (up_qpll_rst),
.QPLL1CLKRSVD0 (1'd0),
.QPLL1CLKRSVD1 (1'd0),
.QPLL1FBCLKLOST (),
.QPLL1FBDIV (8'd0),
.QPLL1LOCK (qpll1_locked),
.QPLL1LOCKDETCLK (up_clk),
.QPLL1LOCKEN (1'd1),
.QPLL1OUTCLK (qpll1_clk),
.QPLL1OUTREFCLK (qpll1_ref_clk),
.QPLL1PD (~qpll_sel),
.QPLL1REFCLKLOST (),
.QPLL1REFCLKSEL (3'b001),
.QPLL1RESET (up_qpll_rst),
.QPLLDMONITOR0 (),
.QPLLDMONITOR1 (),
.QPLLRSVD1 (8'd0),
.QPLLRSVD2 (5'd0),
.QPLLRSVD3 (5'd0),
.QPLLRSVD4 (8'd0),
.RCALENB (1'd1),
.REFCLKOUTMONITOR0 (),
.REFCLKOUTMONITOR1 (),
.RXRECCLK0SEL (),
.RXRECCLK1SEL (),
.SDM0DATA (25'd0),
.SDM0FINALOUT (),
.SDM0RESET (1'd0),
.SDM0TESTDATA (),
.SDM0TOGGLE (1'd0),
.SDM0WIDTH (2'd0),
.SDM1DATA (25'd0),
.SDM1FINALOUT (),
.SDM1RESET (1'd0),
.SDM1TESTDATA (),
.SDM1TOGGLE (1'd0),
.SDM1WIDTH (2'd0),
.TCONGPI (10'd0),
.TCONGPO (),
.TCONPOWERUP (1'd0),
.TCONRESET (2'd0),
.TCONRSVDIN1 (2'd0),
.TCONRSVDOUT0 ());
end
endgenerate
generate
if (XCVR_TYPE == GTYE4_TRANSCEIVERS) begin
GTYE4_COMMON #(
.AEN_QPLL0_FBDIV (1'b1),
.AEN_QPLL1_FBDIV (1'b1),
.AEN_SDM0TOGGLE (1'b0),
.AEN_SDM1TOGGLE (1'b0),
.A_SDM0TOGGLE (1'b0),
.A_SDM1DATA_HIGH (9'b000000000),
.A_SDM1DATA_LOW (16'b0000000000000000),
.A_SDM1TOGGLE (1'b0),
.BIAS_CFG0 (16'b0000000000000000),
.BIAS_CFG1 (16'b0000000000000000),
.BIAS_CFG2 (16'b0000000100100100),
.BIAS_CFG3 (16'b0000000001000001),
.BIAS_CFG4 (16'b0000000000010000),
.BIAS_CFG_RSVD (16'b0000000000000000),
.COMMON_CFG0 (16'b0000000000000000),
.COMMON_CFG1 (16'b0000000000000000),
.POR_CFG (16'b0000000000000000),
.PPF0_CFG (PPF0_CFG),
.PPF1_CFG (16'b0000011000000000),
.QPLL0CLKOUT_RATE ("HALF"),
.QPLL0_CFG0 (QPLL_CFG0),
.QPLL0_CFG1 (QPLL_CFG1),
.QPLL0_CFG1_G3 (QPLL_CFG1_G3),
.QPLL0_CFG2 (QPLL_CFG2),
.QPLL0_CFG2_G3 (QPLL_CFG2_G3),
.QPLL0_CFG3 (QPLL_CFG3),
.QPLL0_CFG4 (QPLL_CFG4),
.QPLL0_CP (10'b0011111111),
.QPLL0_CP_G3 (10'b0000001111),
.QPLL0_FBDIV (QPLL_FBDIV),
.QPLL0_FBDIV_G3 (160),
.QPLL0_INIT_CFG0 (16'b0000001010110010),
.QPLL0_INIT_CFG1 (8'b00000000),
.QPLL0_LOCK_CFG (16'b0010010111101000),
.QPLL0_LOCK_CFG_G3 (16'b0010010111101000),
.QPLL0_LPF (QPLL_LPF),
.QPLL0_LPF_G3 (10'b0111010101),
.QPLL0_PCI_EN (1'b0),
.QPLL0_RATE_SW_USE_DRP (1'b1),
.QPLL0_REFCLK_DIV (QPLL_REFCLK_DIV),
.QPLL0_SDM_CFG0 (16'b0000000010000000),
.QPLL0_SDM_CFG1 (16'b0000000000000000),
.QPLL0_SDM_CFG2 (16'b0000000000000000),
.QPLL1CLKOUT_RATE ("HALF"),
.QPLL1_CFG0 (QPLL_CFG0),
.QPLL1_CFG1 (QPLL_CFG1),
.QPLL1_CFG1_G3 (QPLL_CFG1_G3),
.QPLL1_CFG2 (QPLL_CFG2),
.QPLL1_CFG2_G3 (QPLL_CFG2_G3),
.QPLL1_CFG3 (QPLL_CFG3),
.QPLL1_CFG4 (QPLL_CFG4),
.QPLL1_CP (10'b0011111111),
.QPLL1_CP_G3 (10'b0001111111),
.QPLL1_FBDIV (QPLL_FBDIV),
.QPLL1_FBDIV_G3 (80),
.QPLL1_INIT_CFG0 (16'b0000001010110010),
.QPLL1_INIT_CFG1 (8'b00000000),
.QPLL1_LOCK_CFG (16'b0010010111101000),
.QPLL1_LOCK_CFG_G3 (16'b0010010111101000),
.QPLL1_LPF (10'b1000011111),
.QPLL1_LPF_G3 (10'b0111010100),
.QPLL1_PCI_EN (1'b0),
.QPLL1_RATE_SW_USE_DRP (1'b1),
.QPLL1_REFCLK_DIV (QPLL_REFCLK_DIV),
.QPLL1_SDM_CFG0 (16'b0000000010000000),
.QPLL1_SDM_CFG1 (16'b0000000000000000),
.QPLL1_SDM_CFG2 (16'b0000000000000000),
.RSVD_ATTR0 (16'b0000000000000000),
.RSVD_ATTR1 (16'b0000000000000000),
.RSVD_ATTR2 (16'b0000000000000000),
.RSVD_ATTR3 (16'b0000000000000000),
.RXRECCLKOUT0_SEL (2'b00),
.RXRECCLKOUT1_SEL (2'b00),
.SARC_ENB (1'b0),
.SARC_SEL (1'b0),
.SDM0INITSEED0_0 (16'b0000000100010001),
.SDM0INITSEED0_1 (9'b000010001),
.SDM1INITSEED0_0 (16'b0000000100010001),
.SDM1INITSEED0_1 (9'b000010001),
.SIM_MODE ("FAST"),
.SIM_RESET_SPEEDUP ("TRUE"),
.SIM_DEVICE ("ULTRASCALE_PLUS"),
.UB_CFG0 (16'b0000000000000000),
.UB_CFG1 (16'b0000000000000000),
.UB_CFG2 (16'b0000000000000000),
.UB_CFG3 (16'b0000000000000000),
.UB_CFG4 (16'b0000000000000000),
.UB_CFG5 (16'b0000010000000000),
.UB_CFG6 (16'b0000000000000000))
i_gtye4_common (
.BGBYPASSB (1'b1),
.BGMONITORENB (1'b1),
.BGPDB (1'b1),
.BGRCALOVRD (5'b11111),
.BGRCALOVRDENB (1'b1),
.DRPADDR ({4'd0, up_addr_int}),
.DRPCLK (up_clk),
.DRPDI (up_wdata_int),
.DRPEN (up_enb_int),
.DRPWE (up_wr_int),
.GTGREFCLK0 (1'b0),
.GTGREFCLK1 (1'b0),
.GTNORTHREFCLK00 (1'b0),
.GTNORTHREFCLK01 (1'b0),
.GTNORTHREFCLK10 (1'b0),
.GTNORTHREFCLK11 (1'b0),
.GTREFCLK00 (qpll_ref_clk),
.GTREFCLK01 (qpll_ref_clk),
.GTREFCLK10 (1'b0),
.GTREFCLK11 (1'b0),
.GTSOUTHREFCLK00 (1'b0),
.GTSOUTHREFCLK01 (1'b0),
.GTSOUTHREFCLK10 (1'b0),
.GTSOUTHREFCLK11 (1'b0),
.PCIERATEQPLL0 (3'b0),
.PCIERATEQPLL1 (3'b0),
.PMARSVD0 (8'b0),
.PMARSVD1 (8'b0),
.QPLL0CLKRSVD0 (1'b0),
.QPLL0CLKRSVD1 (1'b0),
.QPLL0FBDIV (8'b0),
.QPLL0LOCKDETCLK (up_clk),
.QPLL0LOCKEN (1'b1),
.QPLL0PD (qpll_sel),
.QPLL0REFCLKSEL (3'b1),
.QPLL0RESET (up_qpll_rst),
.QPLL1CLKRSVD0 (1'b0),
.QPLL1CLKRSVD1 (1'b0),
.QPLL1FBDIV (8'b0),
.QPLL1LOCKDETCLK (up_clk),
.QPLL1LOCKEN (1'b1),
.QPLL1PD (~qpll_sel),
.QPLL1REFCLKSEL (3'b1),
.QPLL1RESET (up_qpll_rst),
.QPLLRSVD1 (8'b0),
.QPLLRSVD2 (5'b0),
.QPLLRSVD3 (5'b0),
.QPLLRSVD4 (8'b0),
.RCALENB (1'b1),
.SDM0DATA (25'b0),
.SDM0RESET (1'b0),
.SDM0TOGGLE (1'b0),
.SDM0WIDTH (2'b0),
.SDM1DATA (25'b0),
.SDM1RESET (1'b0),
.SDM1TOGGLE (1'b0),
.SDM1WIDTH (2'b0),
.UBCFGSTREAMEN (1'b0),
.UBDO (16'b0),
.UBDRDY (1'b0),
.UBENABLE (1'b0),
.UBGPI (2'b0),
.UBINTR (2'b0),
.UBIOLMBRST (1'b0),
.UBMBRST (1'b0),
.UBMDMCAPTURE (1'b0),
.UBMDMDBGRST (1'b0),
.UBMDMDBGUPDATE (1'b0),
.UBMDMREGEN (4'b0),
.UBMDMSHIFT (1'b0),
.UBMDMSYSRST (1'b0),
.UBMDMTCK (1'b0),
.UBMDMTDI (1'b0),
.DRPDO ( up_rdata_s),
.DRPRDY ( up_ready_s),
.PMARSVDOUT0 (),
.PMARSVDOUT1 (),
.QPLL0FBCLKLOST (),
.QPLL0LOCK ( qpll2ch_locked),
.QPLL0OUTCLK ( qpll2ch_clk),
.QPLL0OUTREFCLK ( qpll2ch_ref_clk),
.QPLL0REFCLKLOST (),
.QPLL1FBCLKLOST (),
.QPLL1LOCK ( qpll1_locked),
.QPLL1OUTCLK ( qpll1_clk),
.QPLL1OUTREFCLK ( qpll1_ref_clk),
.QPLL1REFCLKLOST (),
.QPLLDMONITOR0 (),
.QPLLDMONITOR1 (),
.REFCLKOUTMONITOR0 (),
.REFCLKOUTMONITOR1 (),
.RXRECCLK0SEL (),
.RXRECCLK1SEL (),
.SDM0FINALOUT (),
.SDM0TESTDATA (),
.SDM1FINALOUT (),
.SDM1TESTDATA (),
.UBDADDR (),
.UBDEN (),
.UBDI (),
.UBDWE (),
.UBMDMTDO (),
.UBRSVDOUT (),
.UBTXUART ());
end
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************
adi_library/xilinx/util_adxcvr/xgui/util_adxcvr_v1_0.tcl
+932
View File
@@ -0,0 +1,932 @@
# Loading additional proc with user specified bodies to compute parameter values.
source [file join [file dirname [file dirname [info script]]] gui/util_adxcvr_v1_0.gtcl]
# Definitional proc to organize widgets for parameters.
proc init_gui { IPINST } {
ipgui::add_param $IPINST -name "Component_Name"
#Adding Page
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
ipgui::add_param $IPINST -name "A_TXDIFFCTRL" -parent ${Page_0}
ipgui::add_param $IPINST -name "CH_HSPMUX" -parent ${Page_0}
ipgui::add_param $IPINST -name "CPLL_CFG0" -parent ${Page_0}
ipgui::add_param $IPINST -name "CPLL_CFG1" -parent ${Page_0}
ipgui::add_param $IPINST -name "CPLL_CFG2" -parent ${Page_0}
ipgui::add_param $IPINST -name "CPLL_CFG3" -parent ${Page_0}
ipgui::add_param $IPINST -name "CPLL_FBDIV" -parent ${Page_0}
ipgui::add_param $IPINST -name "CPLL_FBDIV_4_5" -parent ${Page_0}
ipgui::add_param $IPINST -name "POR_CFG" -parent ${Page_0}
ipgui::add_param $IPINST -name "PPF0_CFG" -parent ${Page_0}
ipgui::add_param $IPINST -name "PREIQ_FREQ_BST" -parent ${Page_0}
ipgui::add_param $IPINST -name "QPLL_CFG" -parent ${Page_0}
ipgui::add_param $IPINST -name "QPLL_CFG0" -parent ${Page_0}
ipgui::add_param $IPINST -name "QPLL_CFG1" -parent ${Page_0}
ipgui::add_param $IPINST -name "QPLL_CFG1_G3" -parent ${Page_0}
ipgui::add_param $IPINST -name "QPLL_CFG2" -parent ${Page_0}
ipgui::add_param $IPINST -name "QPLL_CFG2_G3" -parent ${Page_0}
ipgui::add_param $IPINST -name "QPLL_CFG3" -parent ${Page_0}
ipgui::add_param $IPINST -name "QPLL_CFG4" -parent ${Page_0}
ipgui::add_param $IPINST -name "QPLL_CP" -parent ${Page_0}
ipgui::add_param $IPINST -name "QPLL_CP_G3" -parent ${Page_0}
ipgui::add_param $IPINST -name "QPLL_FBDIV" -parent ${Page_0}
ipgui::add_param $IPINST -name "QPLL_FBDIV_RATIO" -parent ${Page_0}
ipgui::add_param $IPINST -name "QPLL_LPF" -parent ${Page_0}
ipgui::add_param $IPINST -name "QPLL_REFCLK_DIV" -parent ${Page_0}
ipgui::add_param $IPINST -name "RTX_BUF_CML_CTRL" -parent ${Page_0}
ipgui::add_param $IPINST -name "RXCDR_CFG0" -parent ${Page_0}
ipgui::add_param $IPINST -name "RXCDR_CFG2" -parent ${Page_0}
ipgui::add_param $IPINST -name "RXCDR_CFG2_GEN2" -parent ${Page_0}
ipgui::add_param $IPINST -name "RXCDR_CFG2_GEN4" -parent ${Page_0}
ipgui::add_param $IPINST -name "RXCDR_CFG3" -parent ${Page_0}
ipgui::add_param $IPINST -name "RXCDR_CFG3_GEN2" -parent ${Page_0}
ipgui::add_param $IPINST -name "RXCDR_CFG3_GEN3" -parent ${Page_0}
ipgui::add_param $IPINST -name "RXCDR_CFG3_GEN4" -parent ${Page_0}
ipgui::add_param $IPINST -name "RXPI_CFG0" -parent ${Page_0}
ipgui::add_param $IPINST -name "RXPI_CFG1" -parent ${Page_0}
ipgui::add_param $IPINST -name "RX_CDR_CFG" -parent ${Page_0}
ipgui::add_param $IPINST -name "RX_CLK25_DIV" -parent ${Page_0}
ipgui::add_param $IPINST -name "RX_DFE_LPM_CFG" -parent ${Page_0}
ipgui::add_param $IPINST -name "RX_LANE_INVERT" -parent ${Page_0}
ipgui::add_param $IPINST -name "RX_NUM_OF_LANES" -parent ${Page_0}
ipgui::add_param $IPINST -name "RX_OUT_DIV" -parent ${Page_0}
ipgui::add_param $IPINST -name "RX_PMA_CFG" -parent ${Page_0}
ipgui::add_param $IPINST -name "RX_WIDEMODE_CDR" -parent ${Page_0}
ipgui::add_param $IPINST -name "RX_XMODE_SEL" -parent ${Page_0}
ipgui::add_param $IPINST -name "TXDRV_FREQBAND" -parent ${Page_0}
ipgui::add_param $IPINST -name "TXFE_CFG1" -parent ${Page_0}
ipgui::add_param $IPINST -name "TXFE_CFG2" -parent ${Page_0}
ipgui::add_param $IPINST -name "TXFE_CFG3" -parent ${Page_0}
ipgui::add_param $IPINST -name "TXPI_CFG" -parent ${Page_0}
ipgui::add_param $IPINST -name "TXPI_CFG0" -parent ${Page_0}
ipgui::add_param $IPINST -name "TXPI_CFG1" -parent ${Page_0}
ipgui::add_param $IPINST -name "TX_CLK25_DIV" -parent ${Page_0}
ipgui::add_param $IPINST -name "TX_LANE_INVERT" -parent ${Page_0}
ipgui::add_param $IPINST -name "TX_NUM_OF_LANES" -parent ${Page_0}
ipgui::add_param $IPINST -name "TX_OUT_DIV" -parent ${Page_0}
ipgui::add_param $IPINST -name "TX_PI_BIASSET" -parent ${Page_0}
#Adding Group
set FPGA_info [ipgui::add_group $IPINST -name "FPGA info" -parent ${Page_0}]
ipgui::add_param $IPINST -name "XCVR_TYPE" -parent ${FPGA_info} -widget comboBox
}
proc update_PARAM_VALUE.CH_HSPMUX { PARAM_VALUE.CH_HSPMUX PARAM_VALUE.XCVR_TYPE } {
# Procedure called to update CH_HSPMUX when any of the dependent parameters in the arguments change
set CH_HSPMUX ${PARAM_VALUE.CH_HSPMUX}
set XCVR_TYPE ${PARAM_VALUE.XCVR_TYPE}
set values(XCVR_TYPE) [get_property value $XCVR_TYPE]
set_property value [gen_USERPARAMETER_CH_HSPMUX_VALUE $values(XCVR_TYPE)] $CH_HSPMUX
}
proc validate_PARAM_VALUE.CH_HSPMUX { PARAM_VALUE.CH_HSPMUX } {
# Procedure called to validate CH_HSPMUX
return true
}
proc update_PARAM_VALUE.PPF0_CFG { PARAM_VALUE.PPF0_CFG PARAM_VALUE.XCVR_TYPE } {
# Procedure called to update PPF0_CFG when any of the dependent parameters in the arguments change
set PPF0_CFG ${PARAM_VALUE.PPF0_CFG}
set XCVR_TYPE ${PARAM_VALUE.XCVR_TYPE}
set values(XCVR_TYPE) [get_property value $XCVR_TYPE]
set_property value [gen_USERPARAMETER_PPF0_CFG_VALUE $values(XCVR_TYPE)] $PPF0_CFG
}
proc validate_PARAM_VALUE.PPF0_CFG { PARAM_VALUE.PPF0_CFG } {
# Procedure called to validate PPF0_CFG
return true
}
proc update_PARAM_VALUE.QPLL_LPF { PARAM_VALUE.QPLL_LPF PARAM_VALUE.XCVR_TYPE } {
# Procedure called to update QPLL_LPF when any of the dependent parameters in the arguments change
set QPLL_LPF ${PARAM_VALUE.QPLL_LPF}
set XCVR_TYPE ${PARAM_VALUE.XCVR_TYPE}
set values(XCVR_TYPE) [get_property value $XCVR_TYPE]
set_property value [gen_USERPARAMETER_QPLL_LPF_VALUE $values(XCVR_TYPE)] $QPLL_LPF
}
proc validate_PARAM_VALUE.QPLL_LPF { PARAM_VALUE.QPLL_LPF } {
# Procedure called to validate QPLL_LPF
return true
}
proc update_PARAM_VALUE.RTX_BUF_CML_CTRL { PARAM_VALUE.RTX_BUF_CML_CTRL PARAM_VALUE.XCVR_TYPE } {
# Procedure called to update RTX_BUF_CML_CTRL when any of the dependent parameters in the arguments change
set RTX_BUF_CML_CTRL ${PARAM_VALUE.RTX_BUF_CML_CTRL}
set XCVR_TYPE ${PARAM_VALUE.XCVR_TYPE}
set values(XCVR_TYPE) [get_property value $XCVR_TYPE]
set_property value [gen_USERPARAMETER_RTX_BUF_CML_CTRL_VALUE $values(XCVR_TYPE)] $RTX_BUF_CML_CTRL
}
proc validate_PARAM_VALUE.RTX_BUF_CML_CTRL { PARAM_VALUE.RTX_BUF_CML_CTRL } {
# Procedure called to validate RTX_BUF_CML_CTRL
return true
}
proc update_PARAM_VALUE.RXCDR_CFG3_GEN2 { PARAM_VALUE.RXCDR_CFG3_GEN2 PARAM_VALUE.XCVR_TYPE } {
# Procedure called to update RXCDR_CFG3_GEN2 when any of the dependent parameters in the arguments change
set RXCDR_CFG3_GEN2 ${PARAM_VALUE.RXCDR_CFG3_GEN2}
set XCVR_TYPE ${PARAM_VALUE.XCVR_TYPE}
set values(XCVR_TYPE) [get_property value $XCVR_TYPE]
set_property value [gen_USERPARAMETER_RXCDR_CFG3_GEN2_VALUE $values(XCVR_TYPE)] $RXCDR_CFG3_GEN2
}
proc validate_PARAM_VALUE.RXCDR_CFG3_GEN2 { PARAM_VALUE.RXCDR_CFG3_GEN2 } {
# Procedure called to validate RXCDR_CFG3_GEN2
return true
}
proc update_PARAM_VALUE.RXCDR_CFG3_GEN4 { PARAM_VALUE.RXCDR_CFG3_GEN4 PARAM_VALUE.XCVR_TYPE } {
# Procedure called to update RXCDR_CFG3_GEN4 when any of the dependent parameters in the arguments change
set RXCDR_CFG3_GEN4 ${PARAM_VALUE.RXCDR_CFG3_GEN4}
set XCVR_TYPE ${PARAM_VALUE.XCVR_TYPE}
set values(XCVR_TYPE) [get_property value $XCVR_TYPE]
set_property value [gen_USERPARAMETER_RXCDR_CFG3_GEN4_VALUE $values(XCVR_TYPE)] $RXCDR_CFG3_GEN4
}
proc validate_PARAM_VALUE.RXCDR_CFG3_GEN4 { PARAM_VALUE.RXCDR_CFG3_GEN4 } {
# Procedure called to validate RXCDR_CFG3_GEN4
return true
}
proc update_PARAM_VALUE.RXPI_CFG0 { PARAM_VALUE.RXPI_CFG0 PARAM_VALUE.XCVR_TYPE } {
# Procedure called to update RXPI_CFG0 when any of the dependent parameters in the arguments change
set RXPI_CFG0 ${PARAM_VALUE.RXPI_CFG0}
set XCVR_TYPE ${PARAM_VALUE.XCVR_TYPE}
set values(XCVR_TYPE) [get_property value $XCVR_TYPE]
set_property value [gen_USERPARAMETER_RXPI_CFG0_VALUE $values(XCVR_TYPE)] $RXPI_CFG0
}
proc validate_PARAM_VALUE.RXPI_CFG0 { PARAM_VALUE.RXPI_CFG0 } {
# Procedure called to validate RXPI_CFG0
return true
}
proc update_PARAM_VALUE.RXPI_CFG1 { PARAM_VALUE.RXPI_CFG1 PARAM_VALUE.XCVR_TYPE } {
# Procedure called to update RXPI_CFG1 when any of the dependent parameters in the arguments change
set RXPI_CFG1 ${PARAM_VALUE.RXPI_CFG1}
set XCVR_TYPE ${PARAM_VALUE.XCVR_TYPE}
set values(XCVR_TYPE) [get_property value $XCVR_TYPE]
set_property value [gen_USERPARAMETER_RXPI_CFG1_VALUE $values(XCVR_TYPE)] $RXPI_CFG1
}
proc validate_PARAM_VALUE.RXPI_CFG1 { PARAM_VALUE.RXPI_CFG1 } {
# Procedure called to validate RXPI_CFG1
return true
}
proc update_PARAM_VALUE.TX_PI_BIASSET { PARAM_VALUE.TX_PI_BIASSET PARAM_VALUE.XCVR_TYPE } {
# Procedure called to update TX_PI_BIASSET when any of the dependent parameters in the arguments change
set TX_PI_BIASSET ${PARAM_VALUE.TX_PI_BIASSET}
set XCVR_TYPE ${PARAM_VALUE.XCVR_TYPE}
set values(XCVR_TYPE) [get_property value $XCVR_TYPE]
set_property value [gen_USERPARAMETER_TX_PI_BIASSET_VALUE $values(XCVR_TYPE)] $TX_PI_BIASSET
}
proc validate_PARAM_VALUE.TX_PI_BIASSET { PARAM_VALUE.TX_PI_BIASSET } {
# Procedure called to validate TX_PI_BIASSET
return true
}
proc update_PARAM_VALUE.A_TXDIFFCTRL { PARAM_VALUE.A_TXDIFFCTRL } {
# Procedure called to update A_TXDIFFCTRL when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.A_TXDIFFCTRL { PARAM_VALUE.A_TXDIFFCTRL } {
# Procedure called to validate A_TXDIFFCTRL
return true
}
proc update_PARAM_VALUE.CPLL_CFG0 { PARAM_VALUE.CPLL_CFG0 } {
# Procedure called to update CPLL_CFG0 when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.CPLL_CFG0 { PARAM_VALUE.CPLL_CFG0 } {
# Procedure called to validate CPLL_CFG0
return true
}
proc update_PARAM_VALUE.CPLL_CFG1 { PARAM_VALUE.CPLL_CFG1 } {
# Procedure called to update CPLL_CFG1 when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.CPLL_CFG1 { PARAM_VALUE.CPLL_CFG1 } {
# Procedure called to validate CPLL_CFG1
return true
}
proc update_PARAM_VALUE.CPLL_CFG2 { PARAM_VALUE.CPLL_CFG2 } {
# Procedure called to update CPLL_CFG2 when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.CPLL_CFG2 { PARAM_VALUE.CPLL_CFG2 } {
# Procedure called to validate CPLL_CFG2
return true
}
proc update_PARAM_VALUE.CPLL_CFG3 { PARAM_VALUE.CPLL_CFG3 } {
# Procedure called to update CPLL_CFG3 when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.CPLL_CFG3 { PARAM_VALUE.CPLL_CFG3 } {
# Procedure called to validate CPLL_CFG3
return true
}
proc update_PARAM_VALUE.CPLL_FBDIV { PARAM_VALUE.CPLL_FBDIV } {
# Procedure called to update CPLL_FBDIV when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.CPLL_FBDIV { PARAM_VALUE.CPLL_FBDIV } {
# Procedure called to validate CPLL_FBDIV
return true
}
proc update_PARAM_VALUE.CPLL_FBDIV_4_5 { PARAM_VALUE.CPLL_FBDIV_4_5 } {
# Procedure called to update CPLL_FBDIV_4_5 when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.CPLL_FBDIV_4_5 { PARAM_VALUE.CPLL_FBDIV_4_5 } {
# Procedure called to validate CPLL_FBDIV_4_5
return true
}
proc update_PARAM_VALUE.POR_CFG { PARAM_VALUE.POR_CFG } {
# Procedure called to update POR_CFG when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.POR_CFG { PARAM_VALUE.POR_CFG } {
# Procedure called to validate POR_CFG
return true
}
proc update_PARAM_VALUE.PREIQ_FREQ_BST { PARAM_VALUE.PREIQ_FREQ_BST } {
# Procedure called to update PREIQ_FREQ_BST when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.PREIQ_FREQ_BST { PARAM_VALUE.PREIQ_FREQ_BST } {
# Procedure called to validate PREIQ_FREQ_BST
return true
}
proc update_PARAM_VALUE.QPLL_CFG { PARAM_VALUE.QPLL_CFG } {
# Procedure called to update QPLL_CFG when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.QPLL_CFG { PARAM_VALUE.QPLL_CFG } {
# Procedure called to validate QPLL_CFG
return true
}
proc update_PARAM_VALUE.QPLL_CFG0 { PARAM_VALUE.QPLL_CFG0 } {
# Procedure called to update QPLL_CFG0 when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.QPLL_CFG0 { PARAM_VALUE.QPLL_CFG0 } {
# Procedure called to validate QPLL_CFG0
return true
}
proc update_PARAM_VALUE.QPLL_CFG1 { PARAM_VALUE.QPLL_CFG1 } {
# Procedure called to update QPLL_CFG1 when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.QPLL_CFG1 { PARAM_VALUE.QPLL_CFG1 } {
# Procedure called to validate QPLL_CFG1
return true
}
proc update_PARAM_VALUE.QPLL_CFG1_G3 { PARAM_VALUE.QPLL_CFG1_G3 } {
# Procedure called to update QPLL_CFG1_G3 when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.QPLL_CFG1_G3 { PARAM_VALUE.QPLL_CFG1_G3 } {
# Procedure called to validate QPLL_CFG1_G3
return true
}
proc update_PARAM_VALUE.QPLL_CFG2 { PARAM_VALUE.QPLL_CFG2 } {
# Procedure called to update QPLL_CFG2 when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.QPLL_CFG2 { PARAM_VALUE.QPLL_CFG2 } {
# Procedure called to validate QPLL_CFG2
return true
}
proc update_PARAM_VALUE.QPLL_CFG2_G3 { PARAM_VALUE.QPLL_CFG2_G3 } {
# Procedure called to update QPLL_CFG2_G3 when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.QPLL_CFG2_G3 { PARAM_VALUE.QPLL_CFG2_G3 } {
# Procedure called to validate QPLL_CFG2_G3
return true
}
proc update_PARAM_VALUE.QPLL_CFG3 { PARAM_VALUE.QPLL_CFG3 } {
# Procedure called to update QPLL_CFG3 when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.QPLL_CFG3 { PARAM_VALUE.QPLL_CFG3 } {
# Procedure called to validate QPLL_CFG3
return true
}
proc update_PARAM_VALUE.QPLL_CFG4 { PARAM_VALUE.QPLL_CFG4 } {
# Procedure called to update QPLL_CFG4 when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.QPLL_CFG4 { PARAM_VALUE.QPLL_CFG4 } {
# Procedure called to validate QPLL_CFG4
return true
}
proc update_PARAM_VALUE.QPLL_CP { PARAM_VALUE.QPLL_CP } {
# Procedure called to update QPLL_CP when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.QPLL_CP { PARAM_VALUE.QPLL_CP } {
# Procedure called to validate QPLL_CP
return true
}
proc update_PARAM_VALUE.QPLL_CP_G3 { PARAM_VALUE.QPLL_CP_G3 } {
# Procedure called to update QPLL_CP_G3 when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.QPLL_CP_G3 { PARAM_VALUE.QPLL_CP_G3 } {
# Procedure called to validate QPLL_CP_G3
return true
}
proc update_PARAM_VALUE.QPLL_FBDIV { PARAM_VALUE.QPLL_FBDIV } {
# Procedure called to update QPLL_FBDIV when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.QPLL_FBDIV { PARAM_VALUE.QPLL_FBDIV } {
# Procedure called to validate QPLL_FBDIV
return true
}
proc update_PARAM_VALUE.QPLL_FBDIV_RATIO { PARAM_VALUE.QPLL_FBDIV_RATIO } {
# Procedure called to update QPLL_FBDIV_RATIO when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.QPLL_FBDIV_RATIO { PARAM_VALUE.QPLL_FBDIV_RATIO } {
# Procedure called to validate QPLL_FBDIV_RATIO
return true
}
proc update_PARAM_VALUE.QPLL_REFCLK_DIV { PARAM_VALUE.QPLL_REFCLK_DIV } {
# Procedure called to update QPLL_REFCLK_DIV when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.QPLL_REFCLK_DIV { PARAM_VALUE.QPLL_REFCLK_DIV } {
# Procedure called to validate QPLL_REFCLK_DIV
return true
}
proc update_PARAM_VALUE.RXCDR_CFG0 { PARAM_VALUE.RXCDR_CFG0 } {
# Procedure called to update RXCDR_CFG0 when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.RXCDR_CFG0 { PARAM_VALUE.RXCDR_CFG0 } {
# Procedure called to validate RXCDR_CFG0
return true
}
proc update_PARAM_VALUE.RXCDR_CFG2 { PARAM_VALUE.RXCDR_CFG2 } {
# Procedure called to update RXCDR_CFG2 when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.RXCDR_CFG2 { PARAM_VALUE.RXCDR_CFG2 } {
# Procedure called to validate RXCDR_CFG2
return true
}
proc update_PARAM_VALUE.RXCDR_CFG2_GEN2 { PARAM_VALUE.RXCDR_CFG2_GEN2 } {
# Procedure called to update RXCDR_CFG2_GEN2 when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.RXCDR_CFG2_GEN2 { PARAM_VALUE.RXCDR_CFG2_GEN2 } {
# Procedure called to validate RXCDR_CFG2_GEN2
return true
}
proc update_PARAM_VALUE.RXCDR_CFG2_GEN4 { PARAM_VALUE.RXCDR_CFG2_GEN4 } {
# Procedure called to update RXCDR_CFG2_GEN4 when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.RXCDR_CFG2_GEN4 { PARAM_VALUE.RXCDR_CFG2_GEN4 } {
# Procedure called to validate RXCDR_CFG2_GEN4
return true
}
proc update_PARAM_VALUE.RXCDR_CFG3 { PARAM_VALUE.RXCDR_CFG3 } {
# Procedure called to update RXCDR_CFG3 when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.RXCDR_CFG3 { PARAM_VALUE.RXCDR_CFG3 } {
# Procedure called to validate RXCDR_CFG3
return true
}
proc update_PARAM_VALUE.RXCDR_CFG3_GEN3 { PARAM_VALUE.RXCDR_CFG3_GEN3 } {
# Procedure called to update RXCDR_CFG3_GEN3 when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.RXCDR_CFG3_GEN3 { PARAM_VALUE.RXCDR_CFG3_GEN3 } {
# Procedure called to validate RXCDR_CFG3_GEN3
return true
}
proc update_PARAM_VALUE.RX_CDR_CFG { PARAM_VALUE.RX_CDR_CFG } {
# Procedure called to update RX_CDR_CFG when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.RX_CDR_CFG { PARAM_VALUE.RX_CDR_CFG } {
# Procedure called to validate RX_CDR_CFG
return true
}
proc update_PARAM_VALUE.RX_CLK25_DIV { PARAM_VALUE.RX_CLK25_DIV } {
# Procedure called to update RX_CLK25_DIV when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.RX_CLK25_DIV { PARAM_VALUE.RX_CLK25_DIV } {
# Procedure called to validate RX_CLK25_DIV
return true
}
proc update_PARAM_VALUE.RX_DFE_LPM_CFG { PARAM_VALUE.RX_DFE_LPM_CFG } {
# Procedure called to update RX_DFE_LPM_CFG when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.RX_DFE_LPM_CFG { PARAM_VALUE.RX_DFE_LPM_CFG } {
# Procedure called to validate RX_DFE_LPM_CFG
return true
}
proc update_PARAM_VALUE.RX_LANE_INVERT { PARAM_VALUE.RX_LANE_INVERT } {
# Procedure called to update RX_LANE_INVERT when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.RX_LANE_INVERT { PARAM_VALUE.RX_LANE_INVERT } {
# Procedure called to validate RX_LANE_INVERT
return true
}
proc update_PARAM_VALUE.RX_NUM_OF_LANES { PARAM_VALUE.RX_NUM_OF_LANES } {
# Procedure called to update RX_NUM_OF_LANES when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.RX_NUM_OF_LANES { PARAM_VALUE.RX_NUM_OF_LANES } {
# Procedure called to validate RX_NUM_OF_LANES
return true
}
proc update_PARAM_VALUE.RX_OUT_DIV { PARAM_VALUE.RX_OUT_DIV } {
# Procedure called to update RX_OUT_DIV when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.RX_OUT_DIV { PARAM_VALUE.RX_OUT_DIV } {
# Procedure called to validate RX_OUT_DIV
return true
}
proc update_PARAM_VALUE.RX_PMA_CFG { PARAM_VALUE.RX_PMA_CFG } {
# Procedure called to update RX_PMA_CFG when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.RX_PMA_CFG { PARAM_VALUE.RX_PMA_CFG } {
# Procedure called to validate RX_PMA_CFG
return true
}
proc update_PARAM_VALUE.RX_WIDEMODE_CDR { PARAM_VALUE.RX_WIDEMODE_CDR } {
# Procedure called to update RX_WIDEMODE_CDR when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.RX_WIDEMODE_CDR { PARAM_VALUE.RX_WIDEMODE_CDR } {
# Procedure called to validate RX_WIDEMODE_CDR
return true
}
proc update_PARAM_VALUE.RX_XMODE_SEL { PARAM_VALUE.RX_XMODE_SEL } {
# Procedure called to update RX_XMODE_SEL when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.RX_XMODE_SEL { PARAM_VALUE.RX_XMODE_SEL } {
# Procedure called to validate RX_XMODE_SEL
return true
}
proc update_PARAM_VALUE.TXDRV_FREQBAND { PARAM_VALUE.TXDRV_FREQBAND } {
# Procedure called to update TXDRV_FREQBAND when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.TXDRV_FREQBAND { PARAM_VALUE.TXDRV_FREQBAND } {
# Procedure called to validate TXDRV_FREQBAND
return true
}
proc update_PARAM_VALUE.TXFE_CFG1 { PARAM_VALUE.TXFE_CFG1 } {
# Procedure called to update TXFE_CFG1 when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.TXFE_CFG1 { PARAM_VALUE.TXFE_CFG1 } {
# Procedure called to validate TXFE_CFG1
return true
}
proc update_PARAM_VALUE.TXFE_CFG2 { PARAM_VALUE.TXFE_CFG2 } {
# Procedure called to update TXFE_CFG2 when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.TXFE_CFG2 { PARAM_VALUE.TXFE_CFG2 } {
# Procedure called to validate TXFE_CFG2
return true
}
proc update_PARAM_VALUE.TXFE_CFG3 { PARAM_VALUE.TXFE_CFG3 } {
# Procedure called to update TXFE_CFG3 when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.TXFE_CFG3 { PARAM_VALUE.TXFE_CFG3 } {
# Procedure called to validate TXFE_CFG3
return true
}
proc update_PARAM_VALUE.TXPI_CFG { PARAM_VALUE.TXPI_CFG } {
# Procedure called to update TXPI_CFG when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.TXPI_CFG { PARAM_VALUE.TXPI_CFG } {
# Procedure called to validate TXPI_CFG
return true
}
proc update_PARAM_VALUE.TXPI_CFG0 { PARAM_VALUE.TXPI_CFG0 } {
# Procedure called to update TXPI_CFG0 when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.TXPI_CFG0 { PARAM_VALUE.TXPI_CFG0 } {
# Procedure called to validate TXPI_CFG0
return true
}
proc update_PARAM_VALUE.TXPI_CFG1 { PARAM_VALUE.TXPI_CFG1 } {
# Procedure called to update TXPI_CFG1 when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.TXPI_CFG1 { PARAM_VALUE.TXPI_CFG1 } {
# Procedure called to validate TXPI_CFG1
return true
}
proc update_PARAM_VALUE.TX_CLK25_DIV { PARAM_VALUE.TX_CLK25_DIV } {
# Procedure called to update TX_CLK25_DIV when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.TX_CLK25_DIV { PARAM_VALUE.TX_CLK25_DIV } {
# Procedure called to validate TX_CLK25_DIV
return true
}
proc update_PARAM_VALUE.TX_LANE_INVERT { PARAM_VALUE.TX_LANE_INVERT } {
# Procedure called to update TX_LANE_INVERT when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.TX_LANE_INVERT { PARAM_VALUE.TX_LANE_INVERT } {
# Procedure called to validate TX_LANE_INVERT
return true
}
proc update_PARAM_VALUE.TX_NUM_OF_LANES { PARAM_VALUE.TX_NUM_OF_LANES } {
# Procedure called to update TX_NUM_OF_LANES when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.TX_NUM_OF_LANES { PARAM_VALUE.TX_NUM_OF_LANES } {
# Procedure called to validate TX_NUM_OF_LANES
return true
}
proc update_PARAM_VALUE.TX_OUT_DIV { PARAM_VALUE.TX_OUT_DIV } {
# Procedure called to update TX_OUT_DIV when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.TX_OUT_DIV { PARAM_VALUE.TX_OUT_DIV } {
# Procedure called to validate TX_OUT_DIV
return true
}
proc update_PARAM_VALUE.XCVR_TYPE { PARAM_VALUE.XCVR_TYPE } {
# Procedure called to update XCVR_TYPE when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.XCVR_TYPE { PARAM_VALUE.XCVR_TYPE } {
# Procedure called to validate XCVR_TYPE
return true
}
proc update_MODELPARAM_VALUE.XCVR_TYPE { MODELPARAM_VALUE.XCVR_TYPE PARAM_VALUE.XCVR_TYPE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.XCVR_TYPE}] ${MODELPARAM_VALUE.XCVR_TYPE}
}
proc update_MODELPARAM_VALUE.QPLL_REFCLK_DIV { MODELPARAM_VALUE.QPLL_REFCLK_DIV PARAM_VALUE.QPLL_REFCLK_DIV } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.QPLL_REFCLK_DIV}] ${MODELPARAM_VALUE.QPLL_REFCLK_DIV}
}
proc update_MODELPARAM_VALUE.QPLL_FBDIV_RATIO { MODELPARAM_VALUE.QPLL_FBDIV_RATIO PARAM_VALUE.QPLL_FBDIV_RATIO } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.QPLL_FBDIV_RATIO}] ${MODELPARAM_VALUE.QPLL_FBDIV_RATIO}
}
proc update_MODELPARAM_VALUE.POR_CFG { MODELPARAM_VALUE.POR_CFG PARAM_VALUE.POR_CFG } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.POR_CFG}] ${MODELPARAM_VALUE.POR_CFG}
}
proc update_MODELPARAM_VALUE.PPF0_CFG { MODELPARAM_VALUE.PPF0_CFG PARAM_VALUE.PPF0_CFG } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.PPF0_CFG}] ${MODELPARAM_VALUE.PPF0_CFG}
}
proc update_MODELPARAM_VALUE.QPLL_CFG { MODELPARAM_VALUE.QPLL_CFG PARAM_VALUE.QPLL_CFG } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.QPLL_CFG}] ${MODELPARAM_VALUE.QPLL_CFG}
}
proc update_MODELPARAM_VALUE.QPLL_FBDIV { MODELPARAM_VALUE.QPLL_FBDIV PARAM_VALUE.QPLL_FBDIV } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.QPLL_FBDIV}] ${MODELPARAM_VALUE.QPLL_FBDIV}
}
proc update_MODELPARAM_VALUE.QPLL_CFG0 { MODELPARAM_VALUE.QPLL_CFG0 PARAM_VALUE.QPLL_CFG0 } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.QPLL_CFG0}] ${MODELPARAM_VALUE.QPLL_CFG0}
}
proc update_MODELPARAM_VALUE.QPLL_CFG1 { MODELPARAM_VALUE.QPLL_CFG1 PARAM_VALUE.QPLL_CFG1 } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.QPLL_CFG1}] ${MODELPARAM_VALUE.QPLL_CFG1}
}
proc update_MODELPARAM_VALUE.QPLL_CFG1_G3 { MODELPARAM_VALUE.QPLL_CFG1_G3 PARAM_VALUE.QPLL_CFG1_G3 } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.QPLL_CFG1_G3}] ${MODELPARAM_VALUE.QPLL_CFG1_G3}
}
proc update_MODELPARAM_VALUE.QPLL_CFG2 { MODELPARAM_VALUE.QPLL_CFG2 PARAM_VALUE.QPLL_CFG2 } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.QPLL_CFG2}] ${MODELPARAM_VALUE.QPLL_CFG2}
}
proc update_MODELPARAM_VALUE.QPLL_CFG2_G3 { MODELPARAM_VALUE.QPLL_CFG2_G3 PARAM_VALUE.QPLL_CFG2_G3 } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.QPLL_CFG2_G3}] ${MODELPARAM_VALUE.QPLL_CFG2_G3}
}
proc update_MODELPARAM_VALUE.QPLL_CFG3 { MODELPARAM_VALUE.QPLL_CFG3 PARAM_VALUE.QPLL_CFG3 } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.QPLL_CFG3}] ${MODELPARAM_VALUE.QPLL_CFG3}
}
proc update_MODELPARAM_VALUE.QPLL_CFG4 { MODELPARAM_VALUE.QPLL_CFG4 PARAM_VALUE.QPLL_CFG4 } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.QPLL_CFG4}] ${MODELPARAM_VALUE.QPLL_CFG4}
}
proc update_MODELPARAM_VALUE.QPLL_CP_G3 { MODELPARAM_VALUE.QPLL_CP_G3 PARAM_VALUE.QPLL_CP_G3 } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.QPLL_CP_G3}] ${MODELPARAM_VALUE.QPLL_CP_G3}
}
proc update_MODELPARAM_VALUE.QPLL_LPF { MODELPARAM_VALUE.QPLL_LPF PARAM_VALUE.QPLL_LPF } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.QPLL_LPF}] ${MODELPARAM_VALUE.QPLL_LPF}
}
proc update_MODELPARAM_VALUE.QPLL_CP { MODELPARAM_VALUE.QPLL_CP PARAM_VALUE.QPLL_CP } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.QPLL_CP}] ${MODELPARAM_VALUE.QPLL_CP}
}
proc update_MODELPARAM_VALUE.CPLL_FBDIV { MODELPARAM_VALUE.CPLL_FBDIV PARAM_VALUE.CPLL_FBDIV } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.CPLL_FBDIV}] ${MODELPARAM_VALUE.CPLL_FBDIV}
}
proc update_MODELPARAM_VALUE.CPLL_FBDIV_4_5 { MODELPARAM_VALUE.CPLL_FBDIV_4_5 PARAM_VALUE.CPLL_FBDIV_4_5 } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.CPLL_FBDIV_4_5}] ${MODELPARAM_VALUE.CPLL_FBDIV_4_5}
}
proc update_MODELPARAM_VALUE.CPLL_CFG0 { MODELPARAM_VALUE.CPLL_CFG0 PARAM_VALUE.CPLL_CFG0 } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.CPLL_CFG0}] ${MODELPARAM_VALUE.CPLL_CFG0}
}
proc update_MODELPARAM_VALUE.CPLL_CFG1 { MODELPARAM_VALUE.CPLL_CFG1 PARAM_VALUE.CPLL_CFG1 } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.CPLL_CFG1}] ${MODELPARAM_VALUE.CPLL_CFG1}
}
proc update_MODELPARAM_VALUE.CPLL_CFG2 { MODELPARAM_VALUE.CPLL_CFG2 PARAM_VALUE.CPLL_CFG2 } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.CPLL_CFG2}] ${MODELPARAM_VALUE.CPLL_CFG2}
}
proc update_MODELPARAM_VALUE.CPLL_CFG3 { MODELPARAM_VALUE.CPLL_CFG3 PARAM_VALUE.CPLL_CFG3 } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.CPLL_CFG3}] ${MODELPARAM_VALUE.CPLL_CFG3}
}
proc update_MODELPARAM_VALUE.CH_HSPMUX { MODELPARAM_VALUE.CH_HSPMUX PARAM_VALUE.CH_HSPMUX } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.CH_HSPMUX}] ${MODELPARAM_VALUE.CH_HSPMUX}
}
proc update_MODELPARAM_VALUE.PREIQ_FREQ_BST { MODELPARAM_VALUE.PREIQ_FREQ_BST PARAM_VALUE.PREIQ_FREQ_BST } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.PREIQ_FREQ_BST}] ${MODELPARAM_VALUE.PREIQ_FREQ_BST}
}
proc update_MODELPARAM_VALUE.RXPI_CFG0 { MODELPARAM_VALUE.RXPI_CFG0 PARAM_VALUE.RXPI_CFG0 } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.RXPI_CFG0}] ${MODELPARAM_VALUE.RXPI_CFG0}
}
proc update_MODELPARAM_VALUE.RXPI_CFG1 { MODELPARAM_VALUE.RXPI_CFG1 PARAM_VALUE.RXPI_CFG1 } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.RXPI_CFG1}] ${MODELPARAM_VALUE.RXPI_CFG1}
}
proc update_MODELPARAM_VALUE.RTX_BUF_CML_CTRL { MODELPARAM_VALUE.RTX_BUF_CML_CTRL PARAM_VALUE.RTX_BUF_CML_CTRL } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.RTX_BUF_CML_CTRL}] ${MODELPARAM_VALUE.RTX_BUF_CML_CTRL}
}
proc update_MODELPARAM_VALUE.TX_NUM_OF_LANES { MODELPARAM_VALUE.TX_NUM_OF_LANES PARAM_VALUE.TX_NUM_OF_LANES } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.TX_NUM_OF_LANES}] ${MODELPARAM_VALUE.TX_NUM_OF_LANES}
}
proc update_MODELPARAM_VALUE.TX_OUT_DIV { MODELPARAM_VALUE.TX_OUT_DIV PARAM_VALUE.TX_OUT_DIV } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.TX_OUT_DIV}] ${MODELPARAM_VALUE.TX_OUT_DIV}
}
proc update_MODELPARAM_VALUE.TX_CLK25_DIV { MODELPARAM_VALUE.TX_CLK25_DIV PARAM_VALUE.TX_CLK25_DIV } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.TX_CLK25_DIV}] ${MODELPARAM_VALUE.TX_CLK25_DIV}
}
proc update_MODELPARAM_VALUE.TX_LANE_INVERT { MODELPARAM_VALUE.TX_LANE_INVERT PARAM_VALUE.TX_LANE_INVERT } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.TX_LANE_INVERT}] ${MODELPARAM_VALUE.TX_LANE_INVERT}
}
proc update_MODELPARAM_VALUE.TX_PI_BIASSET { MODELPARAM_VALUE.TX_PI_BIASSET PARAM_VALUE.TX_PI_BIASSET } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.TX_PI_BIASSET}] ${MODELPARAM_VALUE.TX_PI_BIASSET}
}
proc update_MODELPARAM_VALUE.TXPI_CFG { MODELPARAM_VALUE.TXPI_CFG PARAM_VALUE.TXPI_CFG } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.TXPI_CFG}] ${MODELPARAM_VALUE.TXPI_CFG}
}
proc update_MODELPARAM_VALUE.A_TXDIFFCTRL { MODELPARAM_VALUE.A_TXDIFFCTRL PARAM_VALUE.A_TXDIFFCTRL } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.A_TXDIFFCTRL}] ${MODELPARAM_VALUE.A_TXDIFFCTRL}
}
proc update_MODELPARAM_VALUE.RX_NUM_OF_LANES { MODELPARAM_VALUE.RX_NUM_OF_LANES PARAM_VALUE.RX_NUM_OF_LANES } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.RX_NUM_OF_LANES}] ${MODELPARAM_VALUE.RX_NUM_OF_LANES}
}
proc update_MODELPARAM_VALUE.RX_OUT_DIV { MODELPARAM_VALUE.RX_OUT_DIV PARAM_VALUE.RX_OUT_DIV } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.RX_OUT_DIV}] ${MODELPARAM_VALUE.RX_OUT_DIV}
}
proc update_MODELPARAM_VALUE.RX_CLK25_DIV { MODELPARAM_VALUE.RX_CLK25_DIV PARAM_VALUE.RX_CLK25_DIV } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.RX_CLK25_DIV}] ${MODELPARAM_VALUE.RX_CLK25_DIV}
}
proc update_MODELPARAM_VALUE.RX_DFE_LPM_CFG { MODELPARAM_VALUE.RX_DFE_LPM_CFG PARAM_VALUE.RX_DFE_LPM_CFG } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.RX_DFE_LPM_CFG}] ${MODELPARAM_VALUE.RX_DFE_LPM_CFG}
}
proc update_MODELPARAM_VALUE.RX_PMA_CFG { MODELPARAM_VALUE.RX_PMA_CFG PARAM_VALUE.RX_PMA_CFG } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.RX_PMA_CFG}] ${MODELPARAM_VALUE.RX_PMA_CFG}
}
proc update_MODELPARAM_VALUE.RX_CDR_CFG { MODELPARAM_VALUE.RX_CDR_CFG PARAM_VALUE.RX_CDR_CFG } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.RX_CDR_CFG}] ${MODELPARAM_VALUE.RX_CDR_CFG}
}
proc update_MODELPARAM_VALUE.RXCDR_CFG0 { MODELPARAM_VALUE.RXCDR_CFG0 PARAM_VALUE.RXCDR_CFG0 } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.RXCDR_CFG0}] ${MODELPARAM_VALUE.RXCDR_CFG0}
}
proc update_MODELPARAM_VALUE.RXCDR_CFG2 { MODELPARAM_VALUE.RXCDR_CFG2 PARAM_VALUE.RXCDR_CFG2 } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.RXCDR_CFG2}] ${MODELPARAM_VALUE.RXCDR_CFG2}
}
proc update_MODELPARAM_VALUE.RXCDR_CFG2_GEN2 { MODELPARAM_VALUE.RXCDR_CFG2_GEN2 PARAM_VALUE.RXCDR_CFG2_GEN2 } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.RXCDR_CFG2_GEN2}] ${MODELPARAM_VALUE.RXCDR_CFG2_GEN2}
}
proc update_MODELPARAM_VALUE.RXCDR_CFG2_GEN4 { MODELPARAM_VALUE.RXCDR_CFG2_GEN4 PARAM_VALUE.RXCDR_CFG2_GEN4 } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.RXCDR_CFG2_GEN4}] ${MODELPARAM_VALUE.RXCDR_CFG2_GEN4}
}
proc update_MODELPARAM_VALUE.RXCDR_CFG3 { MODELPARAM_VALUE.RXCDR_CFG3 PARAM_VALUE.RXCDR_CFG3 } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.RXCDR_CFG3}] ${MODELPARAM_VALUE.RXCDR_CFG3}
}
proc update_MODELPARAM_VALUE.RXCDR_CFG3_GEN2 { MODELPARAM_VALUE.RXCDR_CFG3_GEN2 PARAM_VALUE.RXCDR_CFG3_GEN2 } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.RXCDR_CFG3_GEN2}] ${MODELPARAM_VALUE.RXCDR_CFG3_GEN2}
}
proc update_MODELPARAM_VALUE.RXCDR_CFG3_GEN3 { MODELPARAM_VALUE.RXCDR_CFG3_GEN3 PARAM_VALUE.RXCDR_CFG3_GEN3 } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.RXCDR_CFG3_GEN3}] ${MODELPARAM_VALUE.RXCDR_CFG3_GEN3}
}
proc update_MODELPARAM_VALUE.RXCDR_CFG3_GEN4 { MODELPARAM_VALUE.RXCDR_CFG3_GEN4 PARAM_VALUE.RXCDR_CFG3_GEN4 } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.RXCDR_CFG3_GEN4}] ${MODELPARAM_VALUE.RXCDR_CFG3_GEN4}
}
proc update_MODELPARAM_VALUE.RX_WIDEMODE_CDR { MODELPARAM_VALUE.RX_WIDEMODE_CDR PARAM_VALUE.RX_WIDEMODE_CDR } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.RX_WIDEMODE_CDR}] ${MODELPARAM_VALUE.RX_WIDEMODE_CDR}
}
proc update_MODELPARAM_VALUE.RX_XMODE_SEL { MODELPARAM_VALUE.RX_XMODE_SEL PARAM_VALUE.RX_XMODE_SEL } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.RX_XMODE_SEL}] ${MODELPARAM_VALUE.RX_XMODE_SEL}
}
proc update_MODELPARAM_VALUE.TXDRV_FREQBAND { MODELPARAM_VALUE.TXDRV_FREQBAND PARAM_VALUE.TXDRV_FREQBAND } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.TXDRV_FREQBAND}] ${MODELPARAM_VALUE.TXDRV_FREQBAND}
}
proc update_MODELPARAM_VALUE.TXFE_CFG1 { MODELPARAM_VALUE.TXFE_CFG1 PARAM_VALUE.TXFE_CFG1 } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.TXFE_CFG1}] ${MODELPARAM_VALUE.TXFE_CFG1}
}
proc update_MODELPARAM_VALUE.TXFE_CFG2 { MODELPARAM_VALUE.TXFE_CFG2 PARAM_VALUE.TXFE_CFG2 } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.TXFE_CFG2}] ${MODELPARAM_VALUE.TXFE_CFG2}
}
proc update_MODELPARAM_VALUE.TXFE_CFG3 { MODELPARAM_VALUE.TXFE_CFG3 PARAM_VALUE.TXFE_CFG3 } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.TXFE_CFG3}] ${MODELPARAM_VALUE.TXFE_CFG3}
}
proc update_MODELPARAM_VALUE.TXPI_CFG0 { MODELPARAM_VALUE.TXPI_CFG0 PARAM_VALUE.TXPI_CFG0 } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.TXPI_CFG0}] ${MODELPARAM_VALUE.TXPI_CFG0}
}
proc update_MODELPARAM_VALUE.TXPI_CFG1 { MODELPARAM_VALUE.TXPI_CFG1 PARAM_VALUE.TXPI_CFG1 } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.TXPI_CFG1}] ${MODELPARAM_VALUE.TXPI_CFG1}
}
proc update_MODELPARAM_VALUE.RX_LANE_INVERT { MODELPARAM_VALUE.RX_LANE_INVERT PARAM_VALUE.RX_LANE_INVERT } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.RX_LANE_INVERT}] ${MODELPARAM_VALUE.RX_LANE_INVERT}
}