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first commit after restructuring
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||||
<?xml version="1.0" encoding="UTF-8"?>
|
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<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
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+28
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// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
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||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
// Date : Sun Mar 19 11:34:38 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ rotate_16b_stub.v
|
||||
// Design : rotate_16b
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "cordic_v6_0_15,Vivado 2019.1.3" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, s_axis_phase_tvalid,
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||||
s_axis_phase_tdata, s_axis_cartesian_tvalid, s_axis_cartesian_tdata,
|
||||
m_axis_dout_tvalid, m_axis_dout_tdata)
|
||||
/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_phase_tvalid,s_axis_phase_tdata[15:0],s_axis_cartesian_tvalid,s_axis_cartesian_tdata[31:0],m_axis_dout_tvalid,m_axis_dout_tdata[31:0]" */;
|
||||
input aclk;
|
||||
input s_axis_phase_tvalid;
|
||||
input [15:0]s_axis_phase_tdata;
|
||||
input s_axis_cartesian_tvalid;
|
||||
input [31:0]s_axis_cartesian_tdata;
|
||||
output m_axis_dout_tvalid;
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||||
output [31:0]m_axis_dout_tdata;
|
||||
endmodule
|
||||
+36
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||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
-- Date : Sun Mar 19 11:34:38 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ rotate_16b_stub.vhdl
|
||||
-- Design : rotate_16b
|
||||
-- Purpose : Stub declaration of top-level module interface
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||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
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||||
use IEEE.STD_LOGIC_1164.ALL;
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||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
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||||
Port (
|
||||
aclk : in STD_LOGIC;
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||||
s_axis_phase_tvalid : in STD_LOGIC;
|
||||
s_axis_phase_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
s_axis_cartesian_tvalid : in STD_LOGIC;
|
||||
s_axis_cartesian_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
m_axis_dout_tvalid : out STD_LOGIC;
|
||||
m_axis_dout_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 )
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||||
);
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||||
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||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
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||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
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||||
attribute syn_black_box : boolean;
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||||
attribute black_box_pad_pin : string;
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||||
attribute syn_black_box of stub : architecture is true;
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||||
attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_phase_tvalid,s_axis_phase_tdata[15:0],s_axis_cartesian_tvalid,s_axis_cartesian_tdata[31:0],m_axis_dout_tvalid,m_axis_dout_tdata[31:0]";
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||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "cordic_v6_0_15,Vivado 2019.1.3";
|
||||
begin
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||||
end;
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||||
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+25
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||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
// Date : Sun Mar 19 11:34:36 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ atan2_16b_stub.v
|
||||
// Design : atan2_16b
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "cordic_v6_0_15,Vivado 2019.1.3" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, s_axis_cartesian_tvalid,
|
||||
s_axis_cartesian_tdata, m_axis_dout_tvalid, m_axis_dout_tdata)
|
||||
/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_cartesian_tvalid,s_axis_cartesian_tdata[31:0],m_axis_dout_tvalid,m_axis_dout_tdata[15:0]" */;
|
||||
input aclk;
|
||||
input s_axis_cartesian_tvalid;
|
||||
input [31:0]s_axis_cartesian_tdata;
|
||||
output m_axis_dout_tvalid;
|
||||
output [15:0]m_axis_dout_tdata;
|
||||
endmodule
|
||||
+34
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||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
-- Date : Sun Mar 19 11:34:36 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ atan2_16b_stub.vhdl
|
||||
-- Design : atan2_16b
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
Port (
|
||||
aclk : in STD_LOGIC;
|
||||
s_axis_cartesian_tvalid : in STD_LOGIC;
|
||||
s_axis_cartesian_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
m_axis_dout_tvalid : out STD_LOGIC;
|
||||
m_axis_dout_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 )
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_cartesian_tvalid,s_axis_cartesian_tdata[31:0],m_axis_dout_tvalid,m_axis_dout_tdata[15:0]";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "cordic_v6_0_15,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
+64
@@ -0,0 +1,64 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
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<spirit:vendor>xilinx.com</spirit:vendor>
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<spirit:library>ipcache</spirit:library>
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<spirit:name>d02f40fcf613a5a3</spirit:name>
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<spirit:version>0</spirit:version>
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<spirit:componentInstances>
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<spirit:componentInstance>
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<spirit:instanceName>atan2_16b</spirit:instanceName>
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<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="cordic" spirit:version="6.0"/>
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<spirit:configurableElementValues>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Compensation_Scaling">No_Scale_Compensation</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Width">16</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Phase_Format">Scaled_Radians</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Pipelining_Mode">Maximum</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Precision">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Round_Mode">Truncate</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cartesian_has_tlast">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cartesian_has_tuser">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cartesian_tuser_width">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.flow_control">NonBlocking</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.optimize_goal">Performance</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.phase_has_tlast">false</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.phase_has_tuser">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.phase_tuser_width">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">15</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
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|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
+15
@@ -0,0 +1,15 @@
|
||||
version:1
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
eof:1861068320
|
||||
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|
||||
version:1
|
||||
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|
||||
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|
||||
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|
||||
eof:181207711
|
||||
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@@ -0,0 +1,3 @@
|
||||
version:1
|
||||
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|
||||
eof:
|
||||
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@@ -0,0 +1,39 @@
|
||||
version:1
|
||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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|
||||
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||||
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|
||||
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||||
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|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636173636164655f647370:64656661756c743a3a6175746f:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d636f6e74726f6c5f7365745f6f70745f7468726573686f6c64:64656661756c743a3a6175746f:00:00
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a333673:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:313130392e3235384d42:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3731372e3839314d42:00:00
|
||||
eof:1583617685
|
||||
+46
@@ -0,0 +1,46 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<document>
|
||||
<!--The data in this file is primarily intended for consumption by Xilinx tools.
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
<application name="pa" timeStamp="Sun Mar 19 11:34:45 2023">
|
||||
<section name="Project Information" visible="false">
|
||||
<property name="ProjectID" value="28332aa21fe34d36834e0f603c8046b0" type="ProjectID"/>
|
||||
<property name="ProjectIteration" value="1" type="ProjectIteration"/>
|
||||
</section>
|
||||
<section name="PlanAhead Usage" visible="true">
|
||||
<item name="Project Data">
|
||||
<property name="SrcSetCount" value="1" type="SrcSetCount"/>
|
||||
<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
|
||||
<property name="DesignMode" value="RTL" type="DesignMode"/>
|
||||
<property name="SynthesisStrategy" value="Vivado Synthesis Defaults" type="SynthesisStrategy"/>
|
||||
<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
|
||||
</item>
|
||||
<item name="Java Command Handlers">
|
||||
<property name="AddExistingIPHandler" value="1" type="JavaHandler"/>
|
||||
<property name="ManageCompositeTargets" value="2" type="JavaHandler"/>
|
||||
<property name="NewIPLocationHandler" value="1" type="JavaHandler"/>
|
||||
</item>
|
||||
<item name="Gui Handlers">
|
||||
<property name="BaseDialog_OK" value="1" type="GuiHandlerData"/>
|
||||
<property name="ExpRunTreePanel_EXP_RUN_TREE_TABLE" value="1" type="GuiHandlerData"/>
|
||||
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="6" type="GuiHandlerData"/>
|
||||
<property name="GettingStartedView_MANAGE_IP" value="1" type="GuiHandlerData"/>
|
||||
<property name="GettingStartedView_START_USING_VIVADO_WITH_IP_CATALOG" value="1" type="GuiHandlerData"/>
|
||||
<property name="NewIPProjectWizard_IP_LOCATION" value="1" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_ADD_EXISTING_IP" value="1" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_GENERATE_COMPOSITE_FILE" value="1" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_RESET_COMPOSITE_FILE" value="1" type="GuiHandlerData"/>
|
||||
<property name="SimpleOutputProductDialog_GENERATE_OUTPUT_PRODUCTS_IMMEDIATELY" value="1" type="GuiHandlerData"/>
|
||||
<property name="SimpleOutputProductDialog_RESET_OUTPUT_PRODUCTS" value="1" type="GuiHandlerData"/>
|
||||
<property name="SrcChooserPanel_ADD_CONFIGURABLE_IP_FILES" value="1" type="GuiHandlerData"/>
|
||||
<property name="SrcMenu_IP_DOCUMENTATION" value="1" type="GuiHandlerData"/>
|
||||
</item>
|
||||
<item name="Other">
|
||||
<property name="GuiMode" value="58" type="GuiMode"/>
|
||||
<property name="BatchMode" value="0" type="BatchMode"/>
|
||||
<property name="TclMode" value="40" type="TclMode"/>
|
||||
</item>
|
||||
</section>
|
||||
</application>
|
||||
</document>
|
||||
+6
@@ -0,0 +1,6 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<labtools version="1" minor="0"/>
|
||||
+9
@@ -0,0 +1,9 @@
|
||||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="atan2_16b_synth_1" LaunchDir="D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||
<Run Id="rotate_16b_synth_1" LaunchDir="D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||
<Parameters>
|
||||
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
|
||||
</Parameters>
|
||||
</Runs>
|
||||
|
||||
+5
@@ -0,0 +1,5 @@
|
||||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Command="vivado.bat" Owner="Josh" Host="JOSH-ASUS-Z690" Pid="33004" HostCore="20" HostMemory="068448337920">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
+270
@@ -0,0 +1,270 @@
|
||||
//
|
||||
// Vivado(TM)
|
||||
// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
|
||||
// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved.
|
||||
//
|
||||
|
||||
// GLOBAL VARIABLES
|
||||
var ISEShell = new ActiveXObject( "WScript.Shell" );
|
||||
var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
|
||||
var ISERunDir = "";
|
||||
var ISELogFile = "runme.log";
|
||||
var ISELogFileStr = null;
|
||||
var ISELogEcho = true;
|
||||
var ISEOldVersionWSH = false;
|
||||
|
||||
|
||||
|
||||
// BOOTSTRAP
|
||||
ISEInit();
|
||||
|
||||
|
||||
|
||||
//
|
||||
// ISE FUNCTIONS
|
||||
//
|
||||
function ISEInit() {
|
||||
|
||||
// 1. RUN DIR setup
|
||||
var ISEScrFP = WScript.ScriptFullName;
|
||||
var ISEScrN = WScript.ScriptName;
|
||||
ISERunDir =
|
||||
ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
|
||||
|
||||
// 2. LOG file setup
|
||||
ISELogFileStr = ISEOpenFile( ISELogFile );
|
||||
|
||||
// 3. LOG echo?
|
||||
var ISEScriptArgs = WScript.Arguments;
|
||||
for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
|
||||
if ( ISEScriptArgs(loopi) == "-quiet" ) {
|
||||
ISELogEcho = false;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
// 4. WSH version check
|
||||
var ISEOptimalVersionWSH = 5.6;
|
||||
var ISECurrentVersionWSH = WScript.Version;
|
||||
if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
|
||||
|
||||
ISEStdErr( "" );
|
||||
ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
|
||||
ISEOptimalVersionWSH + " or higher. Downloads" );
|
||||
ISEStdErr( " for upgrading your Windows Scripting Host can be found here: " );
|
||||
ISEStdErr( " http://msdn.microsoft.com/downloads/list/webdev.asp" );
|
||||
ISEStdErr( "" );
|
||||
|
||||
ISEOldVersionWSH = true;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
function ISEStep( ISEProg, ISEArgs ) {
|
||||
|
||||
// CHECK for a STOP FILE
|
||||
if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
|
||||
ISEStdErr( "" );
|
||||
ISEStdErr( "*** Halting run - EA reset detected ***" );
|
||||
ISEStdErr( "" );
|
||||
WScript.Quit( 1 );
|
||||
}
|
||||
|
||||
// WRITE STEP HEADER to LOG
|
||||
ISEStdOut( "" );
|
||||
ISEStdOut( "*** Running " + ISEProg );
|
||||
ISEStdOut( " with args " + ISEArgs );
|
||||
ISEStdOut( "" );
|
||||
|
||||
// LAUNCH!
|
||||
var ISEExitCode = ISEExec( ISEProg, ISEArgs );
|
||||
if ( ISEExitCode != 0 ) {
|
||||
WScript.Quit( ISEExitCode );
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
function ISEExec( ISEProg, ISEArgs ) {
|
||||
|
||||
var ISEStep = ISEProg;
|
||||
if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
|
||||
ISEProg += ".bat";
|
||||
}
|
||||
|
||||
var ISECmdLine = ISEProg + " " + ISEArgs;
|
||||
var ISEExitCode = 1;
|
||||
|
||||
if ( ISEOldVersionWSH ) { // WSH 5.1
|
||||
|
||||
// BEGIN file creation
|
||||
ISETouchFile( ISEStep, "begin" );
|
||||
|
||||
// LAUNCH!
|
||||
ISELogFileStr.Close();
|
||||
ISECmdLine =
|
||||
"%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
|
||||
ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
|
||||
ISELogFileStr = ISEOpenFile( ISELogFile );
|
||||
|
||||
} else { // WSH 5.6
|
||||
|
||||
// LAUNCH!
|
||||
ISEShell.CurrentDirectory = ISERunDir;
|
||||
|
||||
// Redirect STDERR to STDOUT
|
||||
ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
|
||||
var ISEProcess = ISEShell.Exec( ISECmdLine );
|
||||
|
||||
// BEGIN file creation
|
||||
var wbemFlagReturnImmediately = 0x10;
|
||||
var wbemFlagForwardOnly = 0x20;
|
||||
var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2");
|
||||
var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly);
|
||||
var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly);
|
||||
var NOC = 0;
|
||||
var NOLP = 0;
|
||||
var TPM = 0;
|
||||
|
||||
var cpuInfos = new Enumerator(processor);
|
||||
for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) {
|
||||
var cpuInfo = cpuInfos.item();
|
||||
NOC += cpuInfo.NumberOfCores;
|
||||
NOLP += cpuInfo.NumberOfLogicalProcessors;
|
||||
}
|
||||
var csInfos = new Enumerator(computerSystem);
|
||||
for(;!csInfos.atEnd(); csInfos.moveNext()) {
|
||||
var csInfo = csInfos.item();
|
||||
TPM += csInfo.TotalPhysicalMemory;
|
||||
}
|
||||
|
||||
var ISEHOSTCORE = NOLP
|
||||
var ISEMEMTOTAL = TPM
|
||||
|
||||
var ISENetwork = WScript.CreateObject( "WScript.Network" );
|
||||
var ISEHost = ISENetwork.ComputerName;
|
||||
var ISEUser = ISENetwork.UserName;
|
||||
var ISEPid = ISEProcess.ProcessID;
|
||||
var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
|
||||
ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
|
||||
ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
|
||||
ISEBeginFile.WriteLine( " <Process Command=\"" + ISEProg +
|
||||
"\" Owner=\"" + ISEUser +
|
||||
"\" Host=\"" + ISEHost +
|
||||
"\" Pid=\"" + ISEPid +
|
||||
"\" HostCore=\"" + ISEHOSTCORE +
|
||||
"\" HostMemory=\"" + ISEMEMTOTAL +
|
||||
"\">" );
|
||||
ISEBeginFile.WriteLine( " </Process>" );
|
||||
ISEBeginFile.WriteLine( "</ProcessHandle>" );
|
||||
ISEBeginFile.Close();
|
||||
|
||||
var ISEOutStr = ISEProcess.StdOut;
|
||||
var ISEErrStr = ISEProcess.StdErr;
|
||||
|
||||
// WAIT for ISEStep to finish
|
||||
while ( ISEProcess.Status == 0 ) {
|
||||
|
||||
// dump stdout then stderr - feels a little arbitrary
|
||||
while ( !ISEOutStr.AtEndOfStream ) {
|
||||
ISEStdOut( ISEOutStr.ReadLine() );
|
||||
}
|
||||
|
||||
WScript.Sleep( 100 );
|
||||
}
|
||||
|
||||
ISEExitCode = ISEProcess.ExitCode;
|
||||
}
|
||||
|
||||
ISELogFileStr.Close();
|
||||
|
||||
// END/ERROR file creation
|
||||
if ( ISEExitCode != 0 ) {
|
||||
ISETouchFile( ISEStep, "error" );
|
||||
|
||||
} else {
|
||||
ISETouchFile( ISEStep, "end" );
|
||||
}
|
||||
|
||||
return ISEExitCode;
|
||||
}
|
||||
|
||||
|
||||
//
|
||||
// UTILITIES
|
||||
//
|
||||
function ISEStdOut( ISELine ) {
|
||||
|
||||
ISELogFileStr.WriteLine( ISELine );
|
||||
|
||||
if ( ISELogEcho ) {
|
||||
WScript.StdOut.WriteLine( ISELine );
|
||||
}
|
||||
}
|
||||
|
||||
function ISEStdErr( ISELine ) {
|
||||
|
||||
ISELogFileStr.WriteLine( ISELine );
|
||||
|
||||
if ( ISELogEcho ) {
|
||||
WScript.StdErr.WriteLine( ISELine );
|
||||
}
|
||||
}
|
||||
|
||||
function ISETouchFile( ISERoot, ISEStatus ) {
|
||||
|
||||
var ISETFile =
|
||||
ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
|
||||
ISETFile.Close();
|
||||
}
|
||||
|
||||
function ISEOpenFile( ISEFilename ) {
|
||||
|
||||
// This function has been updated to deal with a problem seen in CR #870871.
|
||||
// In that case the user runs a script that runs impl_1, and then turns around
|
||||
// and runs impl_1 -to_step write_bitstream. That second run takes place in
|
||||
// the same directory, which means we may hit some of the same files, and in
|
||||
// particular, we will open the runme.log file. Even though this script closes
|
||||
// the file (now), we see cases where a subsequent attempt to open the file
|
||||
// fails. Perhaps the OS is slow to release the lock, or the disk comes into
|
||||
// play? In any case, we try to work around this by first waiting if the file
|
||||
// is already there for an arbitrary 5 seconds. Then we use a try-catch block
|
||||
// and try to open the file 10 times with a one second delay after each attempt.
|
||||
// Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
|
||||
// If there is an unrecognized exception when trying to open the file, we output
|
||||
// an error message and write details to an exception.log file.
|
||||
var ISEFullPath = ISERunDir + "/" + ISEFilename;
|
||||
if (ISEFileSys.FileExists(ISEFullPath)) {
|
||||
// File is already there. This could be a problem. Wait in case it is still in use.
|
||||
WScript.Sleep(5000);
|
||||
}
|
||||
var i;
|
||||
for (i = 0; i < 10; ++i) {
|
||||
try {
|
||||
return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
|
||||
} catch (exception) {
|
||||
var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
|
||||
if (error_code == 52) { // 52 is bad file name or number.
|
||||
// Wait a second and try again.
|
||||
WScript.Sleep(1000);
|
||||
continue;
|
||||
} else {
|
||||
WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
|
||||
var exceptionFilePath = ISERunDir + "/exception.log";
|
||||
if (!ISEFileSys.FileExists(exceptionFilePath)) {
|
||||
WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
|
||||
var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
|
||||
exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
|
||||
exceptionFile.WriteLine("\tException name: " + exception.name);
|
||||
exceptionFile.WriteLine("\tException error code: " + error_code);
|
||||
exceptionFile.WriteLine("\tException message: " + exception.message);
|
||||
exceptionFile.Close();
|
||||
}
|
||||
throw exception;
|
||||
}
|
||||
}
|
||||
}
|
||||
// If we reached this point, we failed to open the file after 10 attempts.
|
||||
// We need to error out.
|
||||
WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
|
||||
WScript.Quit(1);
|
||||
}
|
||||
+67
@@ -0,0 +1,67 @@
|
||||
#!/bin/sh
|
||||
|
||||
#
|
||||
# Vivado(TM)
|
||||
# ISEWrap.sh: Vivado Runs Script for UNIX
|
||||
# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
HD_LOG=$1
|
||||
shift
|
||||
|
||||
# CHECK for a STOP FILE
|
||||
if [ -f .stop.rst ]
|
||||
then
|
||||
echo "" >> $HD_LOG
|
||||
echo "*** Halting run - EA reset detected ***" >> $HD_LOG
|
||||
echo "" >> $HD_LOG
|
||||
exit 1
|
||||
fi
|
||||
|
||||
ISE_STEP=$1
|
||||
shift
|
||||
|
||||
# WRITE STEP HEADER to LOG
|
||||
echo "" >> $HD_LOG
|
||||
echo "*** Running $ISE_STEP" >> $HD_LOG
|
||||
echo " with args $@" >> $HD_LOG
|
||||
echo "" >> $HD_LOG
|
||||
|
||||
# LAUNCH!
|
||||
$ISE_STEP "$@" >> $HD_LOG 2>&1 &
|
||||
|
||||
# BEGIN file creation
|
||||
ISE_PID=$!
|
||||
if [ X != X$HOSTNAME ]
|
||||
then
|
||||
ISE_HOST=$HOSTNAME #bash
|
||||
else
|
||||
ISE_HOST=$HOST #csh
|
||||
fi
|
||||
ISE_USER=$USER
|
||||
|
||||
ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
|
||||
ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
|
||||
|
||||
ISE_BEGINFILE=.$ISE_STEP.begin.rst
|
||||
/bin/touch $ISE_BEGINFILE
|
||||
echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
|
||||
echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
|
||||
echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
|
||||
echo " </Process>" >> $ISE_BEGINFILE
|
||||
echo "</ProcessHandle>" >> $ISE_BEGINFILE
|
||||
|
||||
# WAIT for ISEStep to finish
|
||||
wait $ISE_PID
|
||||
|
||||
# END/ERROR file creation
|
||||
RETVAL=$?
|
||||
if [ $RETVAL -eq 0 ]
|
||||
then
|
||||
/bin/touch .$ISE_STEP.end.rst
|
||||
else
|
||||
/bin/touch .$ISE_STEP.error.rst
|
||||
fi
|
||||
|
||||
exit $RETVAL
|
||||
|
||||
BIN
Binary file not shown.
+154
@@ -0,0 +1,154 @@
|
||||
#
|
||||
# Synthesis run script generated by Vivado
|
||||
#
|
||||
|
||||
set TIME_start [clock seconds]
|
||||
proc create_report { reportName command } {
|
||||
set status "."
|
||||
append status $reportName ".fail"
|
||||
if { [file exists $status] } {
|
||||
eval file delete [glob $status]
|
||||
}
|
||||
send_msg_id runtcl-4 info "Executing : $command"
|
||||
set retval [eval catch { $command } msg]
|
||||
if { $retval != 0 } {
|
||||
set fp [open $status w]
|
||||
close $fp
|
||||
send_msg_id runtcl-5 warning "$msg"
|
||||
}
|
||||
}
|
||||
set_param simulator.modelsimInstallPath C:/Mentor/modeltech64_2020.4/win64
|
||||
set_param project.vivado.isBlockSynthRun true
|
||||
set_msg_config -msgmgr_mode ooc_run
|
||||
create_project -in_memory -part xc7k410tffg900-2
|
||||
|
||||
set_param project.singleFileAddWarning.threshold 0
|
||||
set_param project.compositeFile.enableAutoGeneration 0
|
||||
set_param synth.vivado.isSynthRun true
|
||||
set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info
|
||||
set_property webtalk.parent_dir D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/managed_ip_project/managed_ip_project.cache/wt [current_project]
|
||||
set_property parent.project_path D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/managed_ip_project/managed_ip_project.xpr [current_project]
|
||||
set_property default_lib xil_defaultlib [current_project]
|
||||
set_property target_language Verilog [current_project]
|
||||
set_property ip_output_repo d:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/managed_ip_project/managed_ip_project.cache/ip [current_project]
|
||||
set_property ip_cache_permissions {read write} [current_project]
|
||||
read_ip -quiet D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/atan2_16b/atan2_16b.xci
|
||||
set_property used_in_implementation false [get_files -all d:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/atan2_16b/atan2_16b_ooc.xdc]
|
||||
|
||||
# Mark all dcp files as not used in implementation to prevent them from being
|
||||
# stitched into the results of this synthesis run. Any black boxes in the
|
||||
# design are intentionally left as such for best results. Dcp files will be
|
||||
# stitched into the design at a later time, either when this synthesis run is
|
||||
# opened, or when it is stitched into a dependent implementation run.
|
||||
foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
|
||||
set_property used_in_implementation false $dcp
|
||||
}
|
||||
read_xdc dont_touch.xdc
|
||||
set_property used_in_implementation false [get_files dont_touch.xdc]
|
||||
set_param ips.enableIPCacheLiteLoad 1
|
||||
|
||||
set cached_ip [config_ip_cache -export -no_bom -dir D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1 -new_name atan2_16b -ip [get_ips atan2_16b]]
|
||||
|
||||
if { $cached_ip eq {} } {
|
||||
close [open __synthesis_is_running__ w]
|
||||
|
||||
synth_design -top atan2_16b -part xc7k410tffg900-2 -mode out_of_context
|
||||
|
||||
#---------------------------------------------------------
|
||||
# Generate Checkpoint/Stub/Simulation Files For IP Cache
|
||||
#---------------------------------------------------------
|
||||
# disable binary constraint mode for IPCache checkpoints
|
||||
set_param constraints.enableBinaryConstraints false
|
||||
|
||||
catch {
|
||||
write_checkpoint -force -noxdef -rename_prefix atan2_16b_ atan2_16b.dcp
|
||||
|
||||
set ipCachedFiles {}
|
||||
write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ atan2_16b_stub.v
|
||||
lappend ipCachedFiles atan2_16b_stub.v
|
||||
|
||||
write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ atan2_16b_stub.vhdl
|
||||
lappend ipCachedFiles atan2_16b_stub.vhdl
|
||||
|
||||
write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ atan2_16b_sim_netlist.v
|
||||
lappend ipCachedFiles atan2_16b_sim_netlist.v
|
||||
|
||||
write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ atan2_16b_sim_netlist.vhdl
|
||||
lappend ipCachedFiles atan2_16b_sim_netlist.vhdl
|
||||
set TIME_taken [expr [clock seconds] - $TIME_start]
|
||||
|
||||
config_ip_cache -add -dcp atan2_16b.dcp -move_files $ipCachedFiles -use_project_ipc -synth_runtime $TIME_taken -ip [get_ips atan2_16b]
|
||||
}
|
||||
|
||||
rename_ref -prefix_all atan2_16b_
|
||||
|
||||
# disable binary constraint mode for synth run checkpoints
|
||||
set_param constraints.enableBinaryConstraints false
|
||||
write_checkpoint -force -noxdef atan2_16b.dcp
|
||||
create_report "atan2_16b_synth_1_synth_report_utilization_0" "report_utilization -file atan2_16b_utilization_synth.rpt -pb atan2_16b_utilization_synth.pb"
|
||||
|
||||
if { [catch {
|
||||
write_verilog -force -mode synth_stub D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/atan2_16b_stub.v
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_vhdl -force -mode synth_stub D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/atan2_16b_stub.vhdl
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_verilog -force -mode funcsim D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/atan2_16b_sim_netlist.v
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_vhdl -force -mode funcsim D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/atan2_16b_sim_netlist.vhdl
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
|
||||
} else {
|
||||
|
||||
|
||||
}; # end if cached_ip
|
||||
|
||||
add_files D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/atan2_16b_stub.v -of_objects [get_files D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/atan2_16b/atan2_16b.xci]
|
||||
|
||||
add_files D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/atan2_16b_stub.vhdl -of_objects [get_files D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/atan2_16b/atan2_16b.xci]
|
||||
|
||||
add_files D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/atan2_16b_sim_netlist.v -of_objects [get_files D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/atan2_16b/atan2_16b.xci]
|
||||
|
||||
add_files D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/atan2_16b_sim_netlist.vhdl -of_objects [get_files D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/atan2_16b/atan2_16b.xci]
|
||||
|
||||
add_files D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/atan2_16b.dcp -of_objects [get_files D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/atan2_16b/atan2_16b.xci]
|
||||
|
||||
if {[file isdir D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/ip_user_files/ip/atan2_16b]} {
|
||||
catch {
|
||||
file copy -force D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/atan2_16b_sim_netlist.v D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/ip_user_files/ip/atan2_16b
|
||||
}
|
||||
}
|
||||
|
||||
if {[file isdir D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/ip_user_files/ip/atan2_16b]} {
|
||||
catch {
|
||||
file copy -force D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/atan2_16b_sim_netlist.vhdl D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/ip_user_files/ip/atan2_16b
|
||||
}
|
||||
}
|
||||
|
||||
if {[file isdir D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/ip_user_files/ip/atan2_16b]} {
|
||||
catch {
|
||||
file copy -force D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/atan2_16b_stub.v D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/ip_user_files/ip/atan2_16b
|
||||
}
|
||||
}
|
||||
|
||||
if {[file isdir D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/ip_user_files/ip/atan2_16b]} {
|
||||
catch {
|
||||
file copy -force D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/atan2_16b_stub.vhdl D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/ip_user_files/ip/atan2_16b
|
||||
}
|
||||
}
|
||||
file delete __synthesis_is_running__
|
||||
close [open __synthesis_is_complete__ w]
|
||||
+454
@@ -0,0 +1,454 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2019.1.3 (64-bit)
|
||||
# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019
|
||||
# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
|
||||
# Start of session at: Sun Mar 19 11:33:55 2023
|
||||
# Process ID: 34248
|
||||
# Current directory: D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1
|
||||
# Command line: vivado.exe -log atan2_16b.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source atan2_16b.tcl
|
||||
# Log file: D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/atan2_16b.vds
|
||||
# Journal file: D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
Sourcing tcl script 'C:/Users/Josh/AppData/Roaming/Xilinx/Vivado/Vivado_init.tcl'
|
||||
source atan2_16b.tcl -notrace
|
||||
Command: synth_design -top atan2_16b -part xc7k410tffg900-2 -mode out_of_context
|
||||
Starting synth_design
|
||||
Attempting to get a license for feature 'Synthesis' and/or device 'xc7k410t'
|
||||
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k410t'
|
||||
INFO: [Device 21-403] Loading part xc7k410tffg900-2
|
||||
INFO: Launching helper process for spawning children vivado processes
|
||||
INFO: Helper process launched with PID 5448
|
||||
---------------------------------------------------------------------------------
|
||||
Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:04 . Memory (MB): peak = 884.691 ; gain = 176.910
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-638] synthesizing module 'atan2_16b' [d:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/atan2_16b/synth/atan2_16b.vhd:69]
|
||||
Parameter C_ARCHITECTURE bound to: 2 - type: integer
|
||||
Parameter C_CORDIC_FUNCTION bound to: 3 - type: integer
|
||||
Parameter C_COARSE_ROTATE bound to: 1 - type: integer
|
||||
Parameter C_DATA_FORMAT bound to: 0 - type: integer
|
||||
Parameter C_XDEVICEFAMILY bound to: kintex7 - type: string
|
||||
Parameter C_HAS_ACLKEN bound to: 0 - type: integer
|
||||
Parameter C_HAS_ACLK bound to: 1 - type: integer
|
||||
Parameter C_HAS_S_AXIS_CARTESIAN bound to: 1 - type: integer
|
||||
Parameter C_HAS_S_AXIS_PHASE bound to: 0 - type: integer
|
||||
Parameter C_HAS_ARESETN bound to: 0 - type: integer
|
||||
Parameter C_INPUT_WIDTH bound to: 16 - type: integer
|
||||
Parameter C_ITERATIONS bound to: 0 - type: integer
|
||||
Parameter C_OUTPUT_WIDTH bound to: 16 - type: integer
|
||||
Parameter C_PHASE_FORMAT bound to: 1 - type: integer
|
||||
Parameter C_PIPELINE_MODE bound to: -2 - type: integer
|
||||
Parameter C_PRECISION bound to: 0 - type: integer
|
||||
Parameter C_ROUND_MODE bound to: 0 - type: integer
|
||||
Parameter C_SCALE_COMP bound to: 0 - type: integer
|
||||
Parameter C_THROTTLE_SCHEME bound to: 3 - type: integer
|
||||
Parameter C_TLAST_RESOLUTION bound to: 0 - type: integer
|
||||
Parameter C_HAS_S_AXIS_PHASE_TUSER bound to: 0 - type: integer
|
||||
Parameter C_HAS_S_AXIS_PHASE_TLAST bound to: 0 - type: integer
|
||||
Parameter C_S_AXIS_PHASE_TDATA_WIDTH bound to: 16 - type: integer
|
||||
Parameter C_S_AXIS_PHASE_TUSER_WIDTH bound to: 1 - type: integer
|
||||
Parameter C_HAS_S_AXIS_CARTESIAN_TUSER bound to: 0 - type: integer
|
||||
Parameter C_HAS_S_AXIS_CARTESIAN_TLAST bound to: 0 - type: integer
|
||||
Parameter C_S_AXIS_CARTESIAN_TDATA_WIDTH bound to: 32 - type: integer
|
||||
Parameter C_S_AXIS_CARTESIAN_TUSER_WIDTH bound to: 1 - type: integer
|
||||
Parameter C_M_AXIS_DOUT_TDATA_WIDTH bound to: 16 - type: integer
|
||||
Parameter C_M_AXIS_DOUT_TUSER_WIDTH bound to: 1 - type: integer
|
||||
INFO: [Synth 8-3491] module 'cordic_v6_0_15' declared at 'd:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/atan2_16b/hdl/cordic_v6_0_vh_rfs.vhd:10135' bound to instance 'U0' of component 'cordic_v6_0_15' [d:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/atan2_16b/synth/atan2_16b.vhd:144]
|
||||
INFO: [Synth 8-256] done synthesizing module 'atan2_16b' (21#1) [d:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/atan2_16b/synth/atan2_16b.vhd:69]
|
||||
WARNING: [Synth 8-3331] design c_reg_fd_v12_0_6_viv__parameterized2 has unconnected port CE
|
||||
WARNING: [Synth 8-3331] design c_reg_fd_v12_0_6_viv__parameterized2 has unconnected port AINIT
|
||||
WARNING: [Synth 8-3331] design c_reg_fd_v12_0_6_viv__parameterized2 has unconnected port ACLR
|
||||
WARNING: [Synth 8-3331] design c_reg_fd_v12_0_6_viv__parameterized2 has unconnected port ASET
|
||||
WARNING: [Synth 8-3331] design c_reg_fd_v12_0_6_viv__parameterized2 has unconnected port SINIT
|
||||
WARNING: [Synth 8-3331] design c_reg_fd_v12_0_6_viv__parameterized2 has unconnected port SCLR
|
||||
WARNING: [Synth 8-3331] design c_reg_fd_v12_0_6_viv__parameterized2 has unconnected port SSET
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_lut6_legacy__parameterized3 has unconnected port c_in
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_lut6_legacy__parameterized3 has unconnected port ce
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_lut6_legacy__parameterized3 has unconnected port bypass
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_lut6_legacy__parameterized3 has unconnected port sclr
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_lut6_legacy__parameterized3 has unconnected port sset
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_lut6_legacy__parameterized3 has unconnected port sinit
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_legacy__parameterized3 has unconnected port c_in
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_legacy__parameterized3 has unconnected port b_in
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_legacy__parameterized3 has unconnected port a_signed
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_legacy__parameterized3 has unconnected port b_signed
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_viv__parameterized3 has unconnected port C_IN
|
||||
WARNING: [Synth 8-3331] design cordic_round has unconnected port round_in[3]
|
||||
WARNING: [Synth 8-3331] design cordic_round has unconnected port round_in[2]
|
||||
WARNING: [Synth 8-3331] design cordic_round has unconnected port round_in[1]
|
||||
WARNING: [Synth 8-3331] design cordic_round has unconnected port round_in[0]
|
||||
WARNING: [Synth 8-3331] design delay_bit has unconnected port SCLR
|
||||
WARNING: [Synth 8-3331] design delay_bit__parameterized3 has unconnected port WE
|
||||
WARNING: [Synth 8-3331] design delay_bit__parameterized3 has unconnected port CE
|
||||
WARNING: [Synth 8-3331] design delay_bit__parameterized3 has unconnected port SCLR
|
||||
WARNING: [Synth 8-3331] design delay_bit__parameterized3 has unconnected port CLK
|
||||
WARNING: [Synth 8-3331] design cordic_out_config has unconnected port data_x_in[19]
|
||||
WARNING: [Synth 8-3331] design cordic_out_config has unconnected port data_x_in[18]
|
||||
WARNING: [Synth 8-3331] design cordic_out_config has unconnected port data_x_in[17]
|
||||
WARNING: [Synth 8-3331] design cordic_out_config has unconnected port data_x_in[16]
|
||||
WARNING: [Synth 8-3331] design cordic_out_config has unconnected port data_x_in[15]
|
||||
WARNING: [Synth 8-3331] design cordic_out_config has unconnected port data_x_in[14]
|
||||
WARNING: [Synth 8-3331] design cordic_out_config has unconnected port data_x_in[13]
|
||||
WARNING: [Synth 8-3331] design cordic_out_config has unconnected port data_x_in[12]
|
||||
WARNING: [Synth 8-3331] design cordic_out_config has unconnected port data_x_in[11]
|
||||
WARNING: [Synth 8-3331] design cordic_out_config has unconnected port data_x_in[10]
|
||||
WARNING: [Synth 8-3331] design cordic_out_config has unconnected port data_x_in[9]
|
||||
WARNING: [Synth 8-3331] design cordic_out_config has unconnected port data_x_in[8]
|
||||
WARNING: [Synth 8-3331] design cordic_out_config has unconnected port data_x_in[7]
|
||||
WARNING: [Synth 8-3331] design cordic_out_config has unconnected port data_x_in[6]
|
||||
WARNING: [Synth 8-3331] design cordic_out_config has unconnected port data_x_in[5]
|
||||
WARNING: [Synth 8-3331] design cordic_out_config has unconnected port data_x_in[4]
|
||||
WARNING: [Synth 8-3331] design cordic_out_config has unconnected port data_x_in[3]
|
||||
WARNING: [Synth 8-3331] design cordic_out_config has unconnected port data_x_in[2]
|
||||
WARNING: [Synth 8-3331] design cordic_out_config has unconnected port data_x_in[1]
|
||||
WARNING: [Synth 8-3331] design cordic_out_config has unconnected port data_x_in[0]
|
||||
WARNING: [Synth 8-3331] design cordic_out_config has unconnected port data_y_in[19]
|
||||
WARNING: [Synth 8-3331] design cordic_out_config has unconnected port data_y_in[18]
|
||||
WARNING: [Synth 8-3331] design cordic_out_config has unconnected port data_y_in[17]
|
||||
WARNING: [Synth 8-3331] design cordic_out_config has unconnected port data_y_in[16]
|
||||
WARNING: [Synth 8-3331] design cordic_out_config has unconnected port data_y_in[15]
|
||||
WARNING: [Synth 8-3331] design cordic_out_config has unconnected port data_y_in[14]
|
||||
WARNING: [Synth 8-3331] design cordic_out_config has unconnected port data_y_in[13]
|
||||
WARNING: [Synth 8-3331] design cordic_out_config has unconnected port data_y_in[12]
|
||||
WARNING: [Synth 8-3331] design cordic_out_config has unconnected port data_y_in[11]
|
||||
WARNING: [Synth 8-3331] design cordic_out_config has unconnected port data_y_in[10]
|
||||
WARNING: [Synth 8-3331] design cordic_out_config has unconnected port data_y_in[9]
|
||||
WARNING: [Synth 8-3331] design cordic_out_config has unconnected port data_y_in[8]
|
||||
WARNING: [Synth 8-3331] design cordic_out_config has unconnected port data_y_in[7]
|
||||
WARNING: [Synth 8-3331] design cordic_out_config has unconnected port data_y_in[6]
|
||||
WARNING: [Synth 8-3331] design cordic_out_config has unconnected port data_y_in[5]
|
||||
WARNING: [Synth 8-3331] design cordic_out_config has unconnected port data_y_in[4]
|
||||
WARNING: [Synth 8-3331] design cordic_out_config has unconnected port data_y_in[3]
|
||||
WARNING: [Synth 8-3331] design cordic_out_config has unconnected port data_y_in[2]
|
||||
WARNING: [Synth 8-3331] design cordic_out_config has unconnected port data_y_in[1]
|
||||
WARNING: [Synth 8-3331] design cordic_out_config has unconnected port data_y_in[0]
|
||||
WARNING: [Synth 8-3331] design cordic_out_config has unconnected port aclr
|
||||
WARNING: [Synth 8-3331] design cordic_ctrl_slice_par has unconnected port aclr
|
||||
WARNING: [Synth 8-3331] design cordic_eng has unconnected port nd_in
|
||||
WARNING: [Synth 8-3331] design c_reg_fd_v12_0_6_viv has unconnected port CE
|
||||
WARNING: [Synth 8-3331] design c_reg_fd_v12_0_6_viv has unconnected port AINIT
|
||||
WARNING: [Synth 8-3331] design c_reg_fd_v12_0_6_viv has unconnected port ACLR
|
||||
WARNING: [Synth 8-3331] design c_reg_fd_v12_0_6_viv has unconnected port ASET
|
||||
WARNING: [Synth 8-3331] design c_reg_fd_v12_0_6_viv has unconnected port SINIT
|
||||
WARNING: [Synth 8-3331] design c_reg_fd_v12_0_6_viv has unconnected port SCLR
|
||||
WARNING: [Synth 8-3331] design c_reg_fd_v12_0_6_viv has unconnected port SSET
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_lut6_legacy__parameterized1 has unconnected port add
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_lut6_legacy__parameterized1 has unconnected port c_in
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_lut6_legacy__parameterized1 has unconnected port ce
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_lut6_legacy__parameterized1 has unconnected port bypass
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_lut6_legacy__parameterized1 has unconnected port sclr
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_lut6_legacy__parameterized1 has unconnected port sset
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_lut6_legacy__parameterized1 has unconnected port sinit
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_legacy__parameterized1 has unconnected port c_in
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_legacy__parameterized1 has unconnected port b_in
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_legacy__parameterized1 has unconnected port a_signed
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_legacy__parameterized1 has unconnected port b_signed
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_viv__parameterized1 has unconnected port C_IN
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_lut6_legacy has unconnected port add
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_lut6_legacy has unconnected port c_in
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_lut6_legacy has unconnected port ce
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_lut6_legacy has unconnected port bypass
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_lut6_legacy has unconnected port sclr
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_lut6_legacy has unconnected port sset
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_lut6_legacy has unconnected port sinit
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_legacy has unconnected port c_in
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_legacy has unconnected port b_in
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_legacy has unconnected port a_signed
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_legacy has unconnected port b_signed
|
||||
INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:16 . Memory (MB): peak = 1015.023 ; gain = 307.242
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report Check Netlist:
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
| |Item |Errors |Warnings |Status |Description |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:03 ; elapsed = 00:00:16 . Memory (MB): peak = 1015.023 ; gain = 307.242
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:16 . Memory (MB): peak = 1015.023 ; gain = 307.242
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Netlist 29-17] Analyzing 1931 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
|
||||
Processing XDC Constraints
|
||||
Initializing timing engine
|
||||
Parsing XDC File [d:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/atan2_16b/atan2_16b_ooc.xdc] for cell 'U0'
|
||||
Finished Parsing XDC File [d:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/atan2_16b/atan2_16b_ooc.xdc] for cell 'U0'
|
||||
Parsing XDC File [D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/dont_touch.xdc]
|
||||
Finished Parsing XDC File [D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/dont_touch.xdc]
|
||||
Completed Processing XDC Constraints
|
||||
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1095.203 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.061 . Memory (MB): peak = 1106.531 ; gain = 11.328
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Constraint Validation : Time (s): cpu = 00:00:04 ; elapsed = 00:00:21 . Memory (MB): peak = 1106.531 ; gain = 398.750
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Loading Part and Timing Information
|
||||
---------------------------------------------------------------------------------
|
||||
Loading part: xc7k410tffg900-2
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:04 ; elapsed = 00:00:21 . Memory (MB): peak = 1106.531 ; gain = 398.750
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Applying 'set_property' XDC Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
Applied set_property DONT_TOUCH = true for U0. (constraint file D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/dont_touch.xdc, line 9).
|
||||
---------------------------------------------------------------------------------
|
||||
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:04 ; elapsed = 00:00:21 . Memory (MB): peak = 1106.531 ; gain = 398.750
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:22 . Memory (MB): peak = 1106.531 ; gain = 398.750
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Hierarchical Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Hierarchical Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
Part Resources:
|
||||
DSPs: 1540 (col length:140)
|
||||
BRAMs: 1590 (col length: RAMB18 140 RAMB36 70)
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Cross Boundary and Area Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
Warning: Parallel synthesis criteria is not met
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.data_y_int_reg[0]' (FDR) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.phase_int_reg[19]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.data_x_int_reg[0]' (FDR) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.phase_int_reg[19]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.data_y_int_reg[1]' (FDR) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.phase_int_reg[19]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.data_x_int_reg[1]' (FDR) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.phase_int_reg[19]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.data_y_int_reg[2]' (FDR) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.phase_int_reg[19]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.data_x_int_reg[2]' (FDR) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.phase_int_reg[19]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.data_y_int_reg[3]' (FDR) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.phase_int_reg[19]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.data_x_int_reg[3]' (FDR) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.phase_int_reg[19]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_x_int_dly/gen_rtl.gen_reg.d_reg_reg[0]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_x_int_dly/gen_rtl.gen_reg.d_reg_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[0]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_x_int_dly/gen_rtl.gen_reg.d_reg_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_x_int_dly/gen_rtl.gen_reg.d_reg_reg[1]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_x_int_dly/gen_rtl.gen_reg.d_reg_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[1]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_x_int_dly/gen_rtl.gen_reg.d_reg_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_x_int_dly/gen_rtl.gen_reg.d_reg_reg[2]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_x_int_dly/gen_rtl.gen_reg.d_reg_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[2]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_x_int_dly/gen_rtl.gen_reg.d_reg_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_x_int_dly/gen_rtl.gen_reg.d_reg_reg[3]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.phase_int_reg[0]' (FDR) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.phase_int_reg[19]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.phase_int_reg[1]' (FDR) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.phase_int_reg[19]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.phase_int_reg[2]' (FDR) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.phase_int_reg[19]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.phase_int_reg[3]' (FDR) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.phase_int_reg[19]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.phase_int_reg[4]' (FDR) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.phase_int_reg[19]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.phase_int_reg[5]' (FDR) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.phase_int_reg[19]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.phase_int_reg[6]' (FDR) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.phase_int_reg[19]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.phase_int_reg[7]' (FDR) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.phase_int_reg[19]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.phase_int_reg[8]' (FDR) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.phase_int_reg[19]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.phase_int_reg[9]' (FDR) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.phase_int_reg[19]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.phase_int_reg[10]' (FDR) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.phase_int_reg[19]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.phase_int_reg[11]' (FDR) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.phase_int_reg[19]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.phase_int_reg[12]' (FDR) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.phase_int_reg[19]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.phase_int_reg[13]' (FDR) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.phase_int_reg[19]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.phase_int_reg[14]' (FDR) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.phase_int_reg[19]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.phase_int_reg[15]' (FDR) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.phase_int_reg[19]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.phase_int_reg[16]' (FDR) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.phase_int_reg[19]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.phase_int_reg[17]' (FDR) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.phase_int_reg[19]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.phase_int_reg[18]' (FDR) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.phase_int_reg[19]'
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\i_synth/gen_cordic.input_stage/gen_input_regs.phase_int_reg[19] )
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[0]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[1]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[2]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[3]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[4]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[5]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[6]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[7]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[8]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[9]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[10]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[11]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[12]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[13]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[14]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[15]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[17]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[18]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[18]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[19]'
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:04 ; elapsed = 00:00:23 . Memory (MB): peak = 1106.531 ; gain = 398.750
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Applying XDC Timing Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:05 ; elapsed = 00:00:28 . Memory (MB): peak = 1106.531 ; gain = 398.750
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Timing Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Timing Optimization : Time (s): cpu = 00:00:05 ; elapsed = 00:00:28 . Memory (MB): peak = 1106.531 ; gain = 398.750
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Technology Mapping
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Technology Mapping : Time (s): cpu = 00:00:05 ; elapsed = 00:00:29 . Memory (MB): peak = 1106.531 ; gain = 398.750
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished IO Insertion : Time (s): cpu = 00:00:05 ; elapsed = 00:00:30 . Memory (MB): peak = 1106.531 ; gain = 398.750
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report Check Netlist:
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
| |Item |Errors |Warnings |Status |Description |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Instances
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:00:05 ; elapsed = 00:00:30 . Memory (MB): peak = 1106.531 ; gain = 398.750
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Rebuilding User Hierarchy
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:05 ; elapsed = 00:00:30 . Memory (MB): peak = 1106.531 ; gain = 398.750
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Ports
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:00:05 ; elapsed = 00:00:30 . Memory (MB): peak = 1106.531 ; gain = 398.750
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:05 ; elapsed = 00:00:30 . Memory (MB): peak = 1106.531 ; gain = 398.750
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Nets
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:00:05 ; elapsed = 00:00:31 . Memory (MB): peak = 1106.531 ; gain = 398.750
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Writing Synthesis Report
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report BlackBoxes:
|
||||
+-+--------------+----------+
|
||||
| |BlackBox name |Instances |
|
||||
+-+--------------+----------+
|
||||
+-+--------------+----------+
|
||||
|
||||
Report Cell Usage:
|
||||
+------+--------+------+
|
||||
| |Cell |Count |
|
||||
+------+--------+------+
|
||||
|1 |LUT1 | 69|
|
||||
|2 |LUT2 | 344|
|
||||
|3 |LUT3 | 527|
|
||||
|4 |LUT4 | 32|
|
||||
|5 |MUXCY | 838|
|
||||
|6 |SRL16E | 5|
|
||||
|7 |SRLC32E | 1|
|
||||
|8 |XORCY | 806|
|
||||
|9 |FDRE | 929|
|
||||
+------+--------+------+
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:00:05 ; elapsed = 00:00:31 . Memory (MB): peak = 1106.531 ; gain = 398.750
|
||||
---------------------------------------------------------------------------------
|
||||
Synthesis finished with 0 errors, 0 critical warnings and 308 warnings.
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:00:02 ; elapsed = 00:00:28 . Memory (MB): peak = 1106.531 ; gain = 307.242
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:00:05 ; elapsed = 00:00:31 . Memory (MB): peak = 1106.531 ; gain = 398.750
|
||||
INFO: [Project 1-571] Translating synthesized netlist
|
||||
INFO: [Netlist 29-17] Analyzing 1644 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1122.445 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
A total of 222 instances were transformed.
|
||||
(MUXCY,XORCY) => CARRY4: 222 instances
|
||||
|
||||
INFO: [Common 17-83] Releasing license: Synthesis
|
||||
70 Infos, 100 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
synth_design completed successfully
|
||||
synth_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:37 . Memory (MB): peak = 1122.445 ; gain = 736.699
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1122.445 ; gain = 0.000
|
||||
WARNING: [Constraints 18-5210] No constraints selected for write.
|
||||
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
|
||||
INFO: [Common 17-1381] The checkpoint 'D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/atan2_16b.dcp' has been generated.
|
||||
WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used.
|
||||
INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP atan2_16b, cache-ID = d02f40fcf613a5a3
|
||||
INFO: [Coretcl 2-1174] Renamed 350 cell refs.
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1122.445 ; gain = 0.000
|
||||
WARNING: [Constraints 18-5210] No constraints selected for write.
|
||||
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
|
||||
INFO: [Common 17-1381] The checkpoint 'D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/atan2_16b.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_utilization -file atan2_16b_utilization_synth.rpt -pb atan2_16b_utilization_synth.pb
|
||||
INFO: [Common 17-206] Exiting Vivado at Sun Mar 19 11:34:39 2023...
|
||||
BIN
Binary file not shown.
BIN
Binary file not shown.
+25
@@ -0,0 +1,25 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
// Date : Sun Mar 19 11:34:38 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/atan2_16b_stub.v
|
||||
// Design : atan2_16b
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "cordic_v6_0_15,Vivado 2019.1.3" *)
|
||||
module atan2_16b(aclk, s_axis_cartesian_tvalid,
|
||||
s_axis_cartesian_tdata, m_axis_dout_tvalid, m_axis_dout_tdata)
|
||||
/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_cartesian_tvalid,s_axis_cartesian_tdata[31:0],m_axis_dout_tvalid,m_axis_dout_tdata[15:0]" */;
|
||||
input aclk;
|
||||
input s_axis_cartesian_tvalid;
|
||||
input [31:0]s_axis_cartesian_tdata;
|
||||
output m_axis_dout_tvalid;
|
||||
output [15:0]m_axis_dout_tdata;
|
||||
endmodule
|
||||
+34
@@ -0,0 +1,34 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
-- Date : Sun Mar 19 11:34:38 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/atan2_16b_stub.vhdl
|
||||
-- Design : atan2_16b
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity atan2_16b is
|
||||
Port (
|
||||
aclk : in STD_LOGIC;
|
||||
s_axis_cartesian_tvalid : in STD_LOGIC;
|
||||
s_axis_cartesian_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
m_axis_dout_tvalid : out STD_LOGIC;
|
||||
m_axis_dout_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 )
|
||||
);
|
||||
|
||||
end atan2_16b;
|
||||
|
||||
architecture stub of atan2_16b is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_cartesian_tvalid,s_axis_cartesian_tdata[31:0],m_axis_dout_tvalid,m_axis_dout_tdata[15:0]";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "cordic_v6_0_15,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
BIN
Binary file not shown.
+182
@@ -0,0 +1,182 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
| Date : Sun Mar 19 11:34:38 2023
|
||||
| Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
| Command : report_utilization -file atan2_16b_utilization_synth.rpt -pb atan2_16b_utilization_synth.pb
|
||||
| Design : atan2_16b
|
||||
| Device : 7k410tffg900-2
|
||||
| Design State : Synthesized
|
||||
-------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Utilization Design Information
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Slice Logic
|
||||
1.1 Summary of Registers by Type
|
||||
2. Memory
|
||||
3. DSP
|
||||
4. IO and GT Specific
|
||||
5. Clocking
|
||||
6. Specific Feature
|
||||
7. Primitives
|
||||
8. Black Boxes
|
||||
9. Instantiated Netlists
|
||||
|
||||
1. Slice Logic
|
||||
--------------
|
||||
|
||||
+----------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+----------------------------+------+-------+-----------+-------+
|
||||
| Slice LUTs* | 961 | 0 | 254200 | 0.38 |
|
||||
| LUT as Logic | 955 | 0 | 254200 | 0.38 |
|
||||
| LUT as Memory | 6 | 0 | 90600 | <0.01 |
|
||||
| LUT as Distributed RAM | 0 | 0 | | |
|
||||
| LUT as Shift Register | 6 | 0 | | |
|
||||
| Slice Registers | 929 | 0 | 508400 | 0.18 |
|
||||
| Register as Flip Flop | 929 | 0 | 508400 | 0.18 |
|
||||
| Register as Latch | 0 | 0 | 508400 | 0.00 |
|
||||
| F7 Muxes | 0 | 0 | 127100 | 0.00 |
|
||||
| F8 Muxes | 0 | 0 | 63550 | 0.00 |
|
||||
+----------------------------+------+-------+-----------+-------+
|
||||
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
|
||||
|
||||
|
||||
1.1 Summary of Registers by Type
|
||||
--------------------------------
|
||||
|
||||
+-------+--------------+-------------+--------------+
|
||||
| Total | Clock Enable | Synchronous | Asynchronous |
|
||||
+-------+--------------+-------------+--------------+
|
||||
| 0 | _ | - | - |
|
||||
| 0 | _ | - | Set |
|
||||
| 0 | _ | - | Reset |
|
||||
| 0 | _ | Set | - |
|
||||
| 0 | _ | Reset | - |
|
||||
| 0 | Yes | - | - |
|
||||
| 0 | Yes | - | Set |
|
||||
| 0 | Yes | - | Reset |
|
||||
| 0 | Yes | Set | - |
|
||||
| 929 | Yes | Reset | - |
|
||||
+-------+--------------+-------------+--------------+
|
||||
|
||||
|
||||
2. Memory
|
||||
---------
|
||||
|
||||
+----------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+----------------+------+-------+-----------+-------+
|
||||
| Block RAM Tile | 0 | 0 | 795 | 0.00 |
|
||||
| RAMB36/FIFO* | 0 | 0 | 795 | 0.00 |
|
||||
| RAMB18 | 0 | 0 | 1590 | 0.00 |
|
||||
+----------------+------+-------+-----------+-------+
|
||||
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
|
||||
|
||||
|
||||
3. DSP
|
||||
------
|
||||
|
||||
+-----------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-----------+------+-------+-----------+-------+
|
||||
| DSPs | 0 | 0 | 1540 | 0.00 |
|
||||
+-----------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
4. IO and GT Specific
|
||||
---------------------
|
||||
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Bonded IOB | 0 | 0 | 500 | 0.00 |
|
||||
| Bonded IPADs | 0 | 0 | 50 | 0.00 |
|
||||
| Bonded OPADs | 0 | 0 | 32 | 0.00 |
|
||||
| PHY_CONTROL | 0 | 0 | 10 | 0.00 |
|
||||
| PHASER_REF | 0 | 0 | 10 | 0.00 |
|
||||
| OUT_FIFO | 0 | 0 | 40 | 0.00 |
|
||||
| IN_FIFO | 0 | 0 | 40 | 0.00 |
|
||||
| IDELAYCTRL | 0 | 0 | 10 | 0.00 |
|
||||
| IBUFDS | 0 | 0 | 480 | 0.00 |
|
||||
| GTXE2_COMMON | 0 | 0 | 4 | 0.00 |
|
||||
| GTXE2_CHANNEL | 0 | 0 | 16 | 0.00 |
|
||||
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 40 | 0.00 |
|
||||
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 40 | 0.00 |
|
||||
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 500 | 0.00 |
|
||||
| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 |
|
||||
| IBUFDS_GTE2 | 0 | 0 | 8 | 0.00 |
|
||||
| ILOGIC | 0 | 0 | 500 | 0.00 |
|
||||
| OLOGIC | 0 | 0 | 500 | 0.00 |
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
5. Clocking
|
||||
-----------
|
||||
|
||||
+------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+------------+------+-------+-----------+-------+
|
||||
| BUFGCTRL | 0 | 0 | 32 | 0.00 |
|
||||
| BUFIO | 0 | 0 | 40 | 0.00 |
|
||||
| MMCME2_ADV | 0 | 0 | 10 | 0.00 |
|
||||
| PLLE2_ADV | 0 | 0 | 10 | 0.00 |
|
||||
| BUFMRCE | 0 | 0 | 20 | 0.00 |
|
||||
| BUFHCE | 0 | 0 | 168 | 0.00 |
|
||||
| BUFR | 0 | 0 | 40 | 0.00 |
|
||||
+------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
6. Specific Feature
|
||||
-------------------
|
||||
|
||||
+-------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-------------+------+-------+-----------+-------+
|
||||
| BSCANE2 | 0 | 0 | 4 | 0.00 |
|
||||
| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
|
||||
| DNA_PORT | 0 | 0 | 1 | 0.00 |
|
||||
| EFUSE_USR | 0 | 0 | 1 | 0.00 |
|
||||
| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
|
||||
| ICAPE2 | 0 | 0 | 2 | 0.00 |
|
||||
| PCIE_2_1 | 0 | 0 | 1 | 0.00 |
|
||||
| STARTUPE2 | 0 | 0 | 1 | 0.00 |
|
||||
| XADC | 0 | 0 | 1 | 0.00 |
|
||||
+-------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
7. Primitives
|
||||
-------------
|
||||
|
||||
+----------+------+---------------------+
|
||||
| Ref Name | Used | Functional Category |
|
||||
+----------+------+---------------------+
|
||||
| FDRE | 929 | Flop & Latch |
|
||||
| LUT3 | 527 | LUT |
|
||||
| LUT2 | 344 | LUT |
|
||||
| CARRY4 | 222 | CarryLogic |
|
||||
| LUT1 | 69 | LUT |
|
||||
| LUT4 | 32 | LUT |
|
||||
| SRL16E | 5 | Distributed Memory |
|
||||
| SRLC32E | 1 | Distributed Memory |
|
||||
+----------+------+---------------------+
|
||||
|
||||
|
||||
8. Black Boxes
|
||||
--------------
|
||||
|
||||
+----------+------+
|
||||
| Ref Name | Used |
|
||||
+----------+------+
|
||||
|
||||
|
||||
9. Instantiated Netlists
|
||||
------------------------
|
||||
|
||||
+----------+------+
|
||||
| Ref Name | Used |
|
||||
+----------+------+
|
||||
|
||||
|
||||
+16
@@ -0,0 +1,16 @@
|
||||
# This file is automatically generated.
|
||||
# It contains project source information necessary for synthesis and implementation.
|
||||
|
||||
# IP: D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/atan2_16b/atan2_16b.xci
|
||||
# IP: The module: 'atan2_16b' is the root of the design. Do not add the DONT_TOUCH constraint.
|
||||
|
||||
# XDC: d:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/atan2_16b/atan2_16b_ooc.xdc
|
||||
# XDC: The top module name and the constraint reference have the same name: 'atan2_16b'. Do not add the DONT_TOUCH constraint.
|
||||
set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet
|
||||
|
||||
# IP: D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/atan2_16b/atan2_16b.xci
|
||||
# IP: The module: 'atan2_16b' is the root of the design. Do not add the DONT_TOUCH constraint.
|
||||
|
||||
# XDC: d:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/atan2_16b/atan2_16b_ooc.xdc
|
||||
# XDC: The top module name and the constraint reference have the same name: 'atan2_16b'. Do not add the DONT_TOUCH constraint.
|
||||
#dup# set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet
|
||||
+64
@@ -0,0 +1,64 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="atan2_16b_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1679196833">
|
||||
<File Type="PA-TCL" Name="atan2_16b.tcl"/>
|
||||
<File Type="RDS-PROPCONSTRS" Name="atan2_16b_drc_synth.rpt"/>
|
||||
<File Type="REPORTS-TCL" Name="atan2_16b_reports.tcl"/>
|
||||
<File Type="RDS-RDS" Name="atan2_16b.vds"/>
|
||||
<File Type="RDS-UTIL" Name="atan2_16b_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="atan2_16b_utilization_synth.pb"/>
|
||||
<File Type="RDS-DCP" Name="atan2_16b.dcp"/>
|
||||
<File Type="VDS-TIMINGSUMMARY" Name="atan2_16b_timing_summary_synth.rpt"/>
|
||||
<File Type="VDS-TIMING-PB" Name="atan2_16b_timing_summary_synth.pb"/>
|
||||
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/atan2_16b">
|
||||
<File Path="$PPRDIR/../atan2_16b/atan2_16b.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../atan2_16b.xcix">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="atan2_16b"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_in" Type="BlockSrcs" RelSrcDir="$PSRCDIR/atan2_16b">
|
||||
<File Path="$PPRDIR/../atan2_16b/atan2_16b.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../atan2_16b.xcix">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="atan2_16b"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
</GenRun>
|
||||
+9
@@ -0,0 +1,9 @@
|
||||
REM
|
||||
REM Vivado(TM)
|
||||
REM htr.txt: a Vivado-generated description of how-to-repeat the
|
||||
REM the basic steps of a run. Note that runme.bat/sh needs
|
||||
REM to be invoked for Vivado to track run status.
|
||||
REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
REM
|
||||
|
||||
vivado -log atan2_16b.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source atan2_16b.tcl
|
||||
+33
@@ -0,0 +1,33 @@
|
||||
version:1
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:33:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:33:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c636f726469635f76365f305f31355c6174616e325f313662:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c636f726469635f76365f305f31355c726f746174655f313662:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:32:00:00
|
||||
5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3132646332383664376666633439313338383634393066623265636430303266:506172656e742050412070726f6a656374204944:00
|
||||
eof:2456185387
|
||||
+36
@@ -0,0 +1,36 @@
|
||||
//
|
||||
// Vivado(TM)
|
||||
// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
//
|
||||
|
||||
var WshShell = new ActiveXObject( "WScript.Shell" );
|
||||
var ProcEnv = WshShell.Environment( "Process" );
|
||||
var PathVal = ProcEnv("PATH");
|
||||
if ( PathVal.length == 0 ) {
|
||||
PathVal = "C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2019.1/bin;";
|
||||
} else {
|
||||
PathVal = "C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2019.1/bin;" + PathVal;
|
||||
}
|
||||
|
||||
ProcEnv("PATH") = PathVal;
|
||||
|
||||
var RDScrFP = WScript.ScriptFullName;
|
||||
var RDScrN = WScript.ScriptName;
|
||||
var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
|
||||
var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
|
||||
eval( EAInclude(ISEJScriptLib) );
|
||||
|
||||
|
||||
ISEStep( "vivado",
|
||||
"-log atan2_16b.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source atan2_16b.tcl" );
|
||||
|
||||
|
||||
|
||||
function EAInclude( EAInclFilename ) {
|
||||
var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
|
||||
var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
|
||||
var EAIFContents = EAInclFile.ReadAll();
|
||||
EAInclFile.Close();
|
||||
return EAIFContents;
|
||||
}
|
||||
+10
@@ -0,0 +1,10 @@
|
||||
@echo off
|
||||
|
||||
rem Vivado (TM)
|
||||
rem runme.bat: a Vivado-generated Script
|
||||
rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
|
||||
set HD_SDIR=%~dp0
|
||||
cd /d "%HD_SDIR%"
|
||||
cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
|
||||
+43
@@ -0,0 +1,43 @@
|
||||
#!/bin/sh
|
||||
|
||||
#
|
||||
# Vivado(TM)
|
||||
# runme.sh: a Vivado-generated Runs Script for UNIX
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
echo "This script was generated under a different operating system."
|
||||
echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script"
|
||||
exit
|
||||
|
||||
if [ -z "$PATH" ]; then
|
||||
PATH=C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2019.1/bin
|
||||
else
|
||||
PATH=C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2019.1/bin:$PATH
|
||||
fi
|
||||
export PATH
|
||||
|
||||
if [ -z "$LD_LIBRARY_PATH" ]; then
|
||||
LD_LIBRARY_PATH=
|
||||
else
|
||||
LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
|
||||
fi
|
||||
export LD_LIBRARY_PATH
|
||||
|
||||
HD_PWD='D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1'
|
||||
cd "$HD_PWD"
|
||||
|
||||
HD_LOG=runme.log
|
||||
/bin/touch $HD_LOG
|
||||
|
||||
ISEStep="./ISEWrap.sh"
|
||||
EAStep()
|
||||
{
|
||||
$ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
|
||||
if [ $? -ne 0 ]
|
||||
then
|
||||
exit
|
||||
fi
|
||||
}
|
||||
|
||||
EAStep vivado -log atan2_16b.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source atan2_16b.tcl
|
||||
BIN
Binary file not shown.
+5
@@ -0,0 +1,5 @@
|
||||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Command="vivado.bat" Owner="Josh" Host="JOSH-ASUS-Z690" Pid="24548" HostCore="20" HostMemory="068448337920">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
+270
@@ -0,0 +1,270 @@
|
||||
//
|
||||
// Vivado(TM)
|
||||
// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
|
||||
// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved.
|
||||
//
|
||||
|
||||
// GLOBAL VARIABLES
|
||||
var ISEShell = new ActiveXObject( "WScript.Shell" );
|
||||
var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
|
||||
var ISERunDir = "";
|
||||
var ISELogFile = "runme.log";
|
||||
var ISELogFileStr = null;
|
||||
var ISELogEcho = true;
|
||||
var ISEOldVersionWSH = false;
|
||||
|
||||
|
||||
|
||||
// BOOTSTRAP
|
||||
ISEInit();
|
||||
|
||||
|
||||
|
||||
//
|
||||
// ISE FUNCTIONS
|
||||
//
|
||||
function ISEInit() {
|
||||
|
||||
// 1. RUN DIR setup
|
||||
var ISEScrFP = WScript.ScriptFullName;
|
||||
var ISEScrN = WScript.ScriptName;
|
||||
ISERunDir =
|
||||
ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
|
||||
|
||||
// 2. LOG file setup
|
||||
ISELogFileStr = ISEOpenFile( ISELogFile );
|
||||
|
||||
// 3. LOG echo?
|
||||
var ISEScriptArgs = WScript.Arguments;
|
||||
for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
|
||||
if ( ISEScriptArgs(loopi) == "-quiet" ) {
|
||||
ISELogEcho = false;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
// 4. WSH version check
|
||||
var ISEOptimalVersionWSH = 5.6;
|
||||
var ISECurrentVersionWSH = WScript.Version;
|
||||
if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
|
||||
|
||||
ISEStdErr( "" );
|
||||
ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
|
||||
ISEOptimalVersionWSH + " or higher. Downloads" );
|
||||
ISEStdErr( " for upgrading your Windows Scripting Host can be found here: " );
|
||||
ISEStdErr( " http://msdn.microsoft.com/downloads/list/webdev.asp" );
|
||||
ISEStdErr( "" );
|
||||
|
||||
ISEOldVersionWSH = true;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
function ISEStep( ISEProg, ISEArgs ) {
|
||||
|
||||
// CHECK for a STOP FILE
|
||||
if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
|
||||
ISEStdErr( "" );
|
||||
ISEStdErr( "*** Halting run - EA reset detected ***" );
|
||||
ISEStdErr( "" );
|
||||
WScript.Quit( 1 );
|
||||
}
|
||||
|
||||
// WRITE STEP HEADER to LOG
|
||||
ISEStdOut( "" );
|
||||
ISEStdOut( "*** Running " + ISEProg );
|
||||
ISEStdOut( " with args " + ISEArgs );
|
||||
ISEStdOut( "" );
|
||||
|
||||
// LAUNCH!
|
||||
var ISEExitCode = ISEExec( ISEProg, ISEArgs );
|
||||
if ( ISEExitCode != 0 ) {
|
||||
WScript.Quit( ISEExitCode );
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
function ISEExec( ISEProg, ISEArgs ) {
|
||||
|
||||
var ISEStep = ISEProg;
|
||||
if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
|
||||
ISEProg += ".bat";
|
||||
}
|
||||
|
||||
var ISECmdLine = ISEProg + " " + ISEArgs;
|
||||
var ISEExitCode = 1;
|
||||
|
||||
if ( ISEOldVersionWSH ) { // WSH 5.1
|
||||
|
||||
// BEGIN file creation
|
||||
ISETouchFile( ISEStep, "begin" );
|
||||
|
||||
// LAUNCH!
|
||||
ISELogFileStr.Close();
|
||||
ISECmdLine =
|
||||
"%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
|
||||
ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
|
||||
ISELogFileStr = ISEOpenFile( ISELogFile );
|
||||
|
||||
} else { // WSH 5.6
|
||||
|
||||
// LAUNCH!
|
||||
ISEShell.CurrentDirectory = ISERunDir;
|
||||
|
||||
// Redirect STDERR to STDOUT
|
||||
ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
|
||||
var ISEProcess = ISEShell.Exec( ISECmdLine );
|
||||
|
||||
// BEGIN file creation
|
||||
var wbemFlagReturnImmediately = 0x10;
|
||||
var wbemFlagForwardOnly = 0x20;
|
||||
var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2");
|
||||
var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly);
|
||||
var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly);
|
||||
var NOC = 0;
|
||||
var NOLP = 0;
|
||||
var TPM = 0;
|
||||
|
||||
var cpuInfos = new Enumerator(processor);
|
||||
for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) {
|
||||
var cpuInfo = cpuInfos.item();
|
||||
NOC += cpuInfo.NumberOfCores;
|
||||
NOLP += cpuInfo.NumberOfLogicalProcessors;
|
||||
}
|
||||
var csInfos = new Enumerator(computerSystem);
|
||||
for(;!csInfos.atEnd(); csInfos.moveNext()) {
|
||||
var csInfo = csInfos.item();
|
||||
TPM += csInfo.TotalPhysicalMemory;
|
||||
}
|
||||
|
||||
var ISEHOSTCORE = NOLP
|
||||
var ISEMEMTOTAL = TPM
|
||||
|
||||
var ISENetwork = WScript.CreateObject( "WScript.Network" );
|
||||
var ISEHost = ISENetwork.ComputerName;
|
||||
var ISEUser = ISENetwork.UserName;
|
||||
var ISEPid = ISEProcess.ProcessID;
|
||||
var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
|
||||
ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
|
||||
ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
|
||||
ISEBeginFile.WriteLine( " <Process Command=\"" + ISEProg +
|
||||
"\" Owner=\"" + ISEUser +
|
||||
"\" Host=\"" + ISEHost +
|
||||
"\" Pid=\"" + ISEPid +
|
||||
"\" HostCore=\"" + ISEHOSTCORE +
|
||||
"\" HostMemory=\"" + ISEMEMTOTAL +
|
||||
"\">" );
|
||||
ISEBeginFile.WriteLine( " </Process>" );
|
||||
ISEBeginFile.WriteLine( "</ProcessHandle>" );
|
||||
ISEBeginFile.Close();
|
||||
|
||||
var ISEOutStr = ISEProcess.StdOut;
|
||||
var ISEErrStr = ISEProcess.StdErr;
|
||||
|
||||
// WAIT for ISEStep to finish
|
||||
while ( ISEProcess.Status == 0 ) {
|
||||
|
||||
// dump stdout then stderr - feels a little arbitrary
|
||||
while ( !ISEOutStr.AtEndOfStream ) {
|
||||
ISEStdOut( ISEOutStr.ReadLine() );
|
||||
}
|
||||
|
||||
WScript.Sleep( 100 );
|
||||
}
|
||||
|
||||
ISEExitCode = ISEProcess.ExitCode;
|
||||
}
|
||||
|
||||
ISELogFileStr.Close();
|
||||
|
||||
// END/ERROR file creation
|
||||
if ( ISEExitCode != 0 ) {
|
||||
ISETouchFile( ISEStep, "error" );
|
||||
|
||||
} else {
|
||||
ISETouchFile( ISEStep, "end" );
|
||||
}
|
||||
|
||||
return ISEExitCode;
|
||||
}
|
||||
|
||||
|
||||
//
|
||||
// UTILITIES
|
||||
//
|
||||
function ISEStdOut( ISELine ) {
|
||||
|
||||
ISELogFileStr.WriteLine( ISELine );
|
||||
|
||||
if ( ISELogEcho ) {
|
||||
WScript.StdOut.WriteLine( ISELine );
|
||||
}
|
||||
}
|
||||
|
||||
function ISEStdErr( ISELine ) {
|
||||
|
||||
ISELogFileStr.WriteLine( ISELine );
|
||||
|
||||
if ( ISELogEcho ) {
|
||||
WScript.StdErr.WriteLine( ISELine );
|
||||
}
|
||||
}
|
||||
|
||||
function ISETouchFile( ISERoot, ISEStatus ) {
|
||||
|
||||
var ISETFile =
|
||||
ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
|
||||
ISETFile.Close();
|
||||
}
|
||||
|
||||
function ISEOpenFile( ISEFilename ) {
|
||||
|
||||
// This function has been updated to deal with a problem seen in CR #870871.
|
||||
// In that case the user runs a script that runs impl_1, and then turns around
|
||||
// and runs impl_1 -to_step write_bitstream. That second run takes place in
|
||||
// the same directory, which means we may hit some of the same files, and in
|
||||
// particular, we will open the runme.log file. Even though this script closes
|
||||
// the file (now), we see cases where a subsequent attempt to open the file
|
||||
// fails. Perhaps the OS is slow to release the lock, or the disk comes into
|
||||
// play? In any case, we try to work around this by first waiting if the file
|
||||
// is already there for an arbitrary 5 seconds. Then we use a try-catch block
|
||||
// and try to open the file 10 times with a one second delay after each attempt.
|
||||
// Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
|
||||
// If there is an unrecognized exception when trying to open the file, we output
|
||||
// an error message and write details to an exception.log file.
|
||||
var ISEFullPath = ISERunDir + "/" + ISEFilename;
|
||||
if (ISEFileSys.FileExists(ISEFullPath)) {
|
||||
// File is already there. This could be a problem. Wait in case it is still in use.
|
||||
WScript.Sleep(5000);
|
||||
}
|
||||
var i;
|
||||
for (i = 0; i < 10; ++i) {
|
||||
try {
|
||||
return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
|
||||
} catch (exception) {
|
||||
var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
|
||||
if (error_code == 52) { // 52 is bad file name or number.
|
||||
// Wait a second and try again.
|
||||
WScript.Sleep(1000);
|
||||
continue;
|
||||
} else {
|
||||
WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
|
||||
var exceptionFilePath = ISERunDir + "/exception.log";
|
||||
if (!ISEFileSys.FileExists(exceptionFilePath)) {
|
||||
WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
|
||||
var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
|
||||
exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
|
||||
exceptionFile.WriteLine("\tException name: " + exception.name);
|
||||
exceptionFile.WriteLine("\tException error code: " + error_code);
|
||||
exceptionFile.WriteLine("\tException message: " + exception.message);
|
||||
exceptionFile.Close();
|
||||
}
|
||||
throw exception;
|
||||
}
|
||||
}
|
||||
}
|
||||
// If we reached this point, we failed to open the file after 10 attempts.
|
||||
// We need to error out.
|
||||
WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
|
||||
WScript.Quit(1);
|
||||
}
|
||||
+67
@@ -0,0 +1,67 @@
|
||||
#!/bin/sh
|
||||
|
||||
#
|
||||
# Vivado(TM)
|
||||
# ISEWrap.sh: Vivado Runs Script for UNIX
|
||||
# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
HD_LOG=$1
|
||||
shift
|
||||
|
||||
# CHECK for a STOP FILE
|
||||
if [ -f .stop.rst ]
|
||||
then
|
||||
echo "" >> $HD_LOG
|
||||
echo "*** Halting run - EA reset detected ***" >> $HD_LOG
|
||||
echo "" >> $HD_LOG
|
||||
exit 1
|
||||
fi
|
||||
|
||||
ISE_STEP=$1
|
||||
shift
|
||||
|
||||
# WRITE STEP HEADER to LOG
|
||||
echo "" >> $HD_LOG
|
||||
echo "*** Running $ISE_STEP" >> $HD_LOG
|
||||
echo " with args $@" >> $HD_LOG
|
||||
echo "" >> $HD_LOG
|
||||
|
||||
# LAUNCH!
|
||||
$ISE_STEP "$@" >> $HD_LOG 2>&1 &
|
||||
|
||||
# BEGIN file creation
|
||||
ISE_PID=$!
|
||||
if [ X != X$HOSTNAME ]
|
||||
then
|
||||
ISE_HOST=$HOSTNAME #bash
|
||||
else
|
||||
ISE_HOST=$HOST #csh
|
||||
fi
|
||||
ISE_USER=$USER
|
||||
|
||||
ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
|
||||
ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
|
||||
|
||||
ISE_BEGINFILE=.$ISE_STEP.begin.rst
|
||||
/bin/touch $ISE_BEGINFILE
|
||||
echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
|
||||
echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
|
||||
echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
|
||||
echo " </Process>" >> $ISE_BEGINFILE
|
||||
echo "</ProcessHandle>" >> $ISE_BEGINFILE
|
||||
|
||||
# WAIT for ISEStep to finish
|
||||
wait $ISE_PID
|
||||
|
||||
# END/ERROR file creation
|
||||
RETVAL=$?
|
||||
if [ $RETVAL -eq 0 ]
|
||||
then
|
||||
/bin/touch .$ISE_STEP.end.rst
|
||||
else
|
||||
/bin/touch .$ISE_STEP.error.rst
|
||||
fi
|
||||
|
||||
exit $RETVAL
|
||||
|
||||
+16
@@ -0,0 +1,16 @@
|
||||
# This file is automatically generated.
|
||||
# It contains project source information necessary for synthesis and implementation.
|
||||
|
||||
# IP: D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/rotate_16b/rotate_16b.xci
|
||||
# IP: The module: 'rotate_16b' is the root of the design. Do not add the DONT_TOUCH constraint.
|
||||
|
||||
# XDC: d:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/rotate_16b/rotate_16b_ooc.xdc
|
||||
# XDC: The top module name and the constraint reference have the same name: 'rotate_16b'. Do not add the DONT_TOUCH constraint.
|
||||
set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet
|
||||
|
||||
# IP: D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/rotate_16b/rotate_16b.xci
|
||||
# IP: The module: 'rotate_16b' is the root of the design. Do not add the DONT_TOUCH constraint.
|
||||
|
||||
# XDC: d:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/rotate_16b/rotate_16b_ooc.xdc
|
||||
# XDC: The top module name and the constraint reference have the same name: 'rotate_16b'. Do not add the DONT_TOUCH constraint.
|
||||
#dup# set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet
|
||||
+64
@@ -0,0 +1,64 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="rotate_16b_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1679196833">
|
||||
<File Type="PA-TCL" Name="rotate_16b.tcl"/>
|
||||
<File Type="RDS-PROPCONSTRS" Name="rotate_16b_drc_synth.rpt"/>
|
||||
<File Type="REPORTS-TCL" Name="rotate_16b_reports.tcl"/>
|
||||
<File Type="RDS-RDS" Name="rotate_16b.vds"/>
|
||||
<File Type="RDS-UTIL" Name="rotate_16b_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="rotate_16b_utilization_synth.pb"/>
|
||||
<File Type="RDS-DCP" Name="rotate_16b.dcp"/>
|
||||
<File Type="VDS-TIMINGSUMMARY" Name="rotate_16b_timing_summary_synth.rpt"/>
|
||||
<File Type="VDS-TIMING-PB" Name="rotate_16b_timing_summary_synth.pb"/>
|
||||
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/rotate_16b">
|
||||
<File Path="$PPRDIR/../rotate_16b/rotate_16b.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../rotate_16b.xcix">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="rotate_16b"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_in" Type="BlockSrcs" RelSrcDir="$PSRCDIR/rotate_16b">
|
||||
<File Path="$PPRDIR/../rotate_16b/rotate_16b.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../rotate_16b.xcix">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="rotate_16b"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
</GenRun>
|
||||
+9
@@ -0,0 +1,9 @@
|
||||
REM
|
||||
REM Vivado(TM)
|
||||
REM htr.txt: a Vivado-generated description of how-to-repeat the
|
||||
REM the basic steps of a run. Note that runme.bat/sh needs
|
||||
REM to be invoked for Vivado to track run status.
|
||||
REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
REM
|
||||
|
||||
vivado -log rotate_16b.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source rotate_16b.tcl
|
||||
+33
@@ -0,0 +1,33 @@
|
||||
version:1
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:33:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:33:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c636f726469635f76365f305f31355c6174616e325f313662:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c636f726469635f76365f305f31355c726f746174655f313662:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:32:00:00
|
||||
5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3132646332383664376666633439313338383634393066623265636430303266:506172656e742050412070726f6a656374204944:00
|
||||
eof:2456185387
|
||||
BIN
Binary file not shown.
+154
@@ -0,0 +1,154 @@
|
||||
#
|
||||
# Synthesis run script generated by Vivado
|
||||
#
|
||||
|
||||
set TIME_start [clock seconds]
|
||||
proc create_report { reportName command } {
|
||||
set status "."
|
||||
append status $reportName ".fail"
|
||||
if { [file exists $status] } {
|
||||
eval file delete [glob $status]
|
||||
}
|
||||
send_msg_id runtcl-4 info "Executing : $command"
|
||||
set retval [eval catch { $command } msg]
|
||||
if { $retval != 0 } {
|
||||
set fp [open $status w]
|
||||
close $fp
|
||||
send_msg_id runtcl-5 warning "$msg"
|
||||
}
|
||||
}
|
||||
set_param simulator.modelsimInstallPath C:/Mentor/modeltech64_2020.4/win64
|
||||
set_param project.vivado.isBlockSynthRun true
|
||||
set_msg_config -msgmgr_mode ooc_run
|
||||
create_project -in_memory -part xc7k410tffg900-2
|
||||
|
||||
set_param project.singleFileAddWarning.threshold 0
|
||||
set_param project.compositeFile.enableAutoGeneration 0
|
||||
set_param synth.vivado.isSynthRun true
|
||||
set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info
|
||||
set_property webtalk.parent_dir D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/managed_ip_project/managed_ip_project.cache/wt [current_project]
|
||||
set_property parent.project_path D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/managed_ip_project/managed_ip_project.xpr [current_project]
|
||||
set_property default_lib xil_defaultlib [current_project]
|
||||
set_property target_language Verilog [current_project]
|
||||
set_property ip_output_repo d:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/managed_ip_project/managed_ip_project.cache/ip [current_project]
|
||||
set_property ip_cache_permissions {read write} [current_project]
|
||||
read_ip -quiet D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/rotate_16b/rotate_16b.xci
|
||||
set_property used_in_implementation false [get_files -all d:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/rotate_16b/rotate_16b_ooc.xdc]
|
||||
|
||||
# Mark all dcp files as not used in implementation to prevent them from being
|
||||
# stitched into the results of this synthesis run. Any black boxes in the
|
||||
# design are intentionally left as such for best results. Dcp files will be
|
||||
# stitched into the design at a later time, either when this synthesis run is
|
||||
# opened, or when it is stitched into a dependent implementation run.
|
||||
foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
|
||||
set_property used_in_implementation false $dcp
|
||||
}
|
||||
read_xdc dont_touch.xdc
|
||||
set_property used_in_implementation false [get_files dont_touch.xdc]
|
||||
set_param ips.enableIPCacheLiteLoad 1
|
||||
|
||||
set cached_ip [config_ip_cache -export -no_bom -dir D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1 -new_name rotate_16b -ip [get_ips rotate_16b]]
|
||||
|
||||
if { $cached_ip eq {} } {
|
||||
close [open __synthesis_is_running__ w]
|
||||
|
||||
synth_design -top rotate_16b -part xc7k410tffg900-2 -mode out_of_context
|
||||
|
||||
#---------------------------------------------------------
|
||||
# Generate Checkpoint/Stub/Simulation Files For IP Cache
|
||||
#---------------------------------------------------------
|
||||
# disable binary constraint mode for IPCache checkpoints
|
||||
set_param constraints.enableBinaryConstraints false
|
||||
|
||||
catch {
|
||||
write_checkpoint -force -noxdef -rename_prefix rotate_16b_ rotate_16b.dcp
|
||||
|
||||
set ipCachedFiles {}
|
||||
write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ rotate_16b_stub.v
|
||||
lappend ipCachedFiles rotate_16b_stub.v
|
||||
|
||||
write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ rotate_16b_stub.vhdl
|
||||
lappend ipCachedFiles rotate_16b_stub.vhdl
|
||||
|
||||
write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ rotate_16b_sim_netlist.v
|
||||
lappend ipCachedFiles rotate_16b_sim_netlist.v
|
||||
|
||||
write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ rotate_16b_sim_netlist.vhdl
|
||||
lappend ipCachedFiles rotate_16b_sim_netlist.vhdl
|
||||
set TIME_taken [expr [clock seconds] - $TIME_start]
|
||||
|
||||
config_ip_cache -add -dcp rotate_16b.dcp -move_files $ipCachedFiles -use_project_ipc -synth_runtime $TIME_taken -ip [get_ips rotate_16b]
|
||||
}
|
||||
|
||||
rename_ref -prefix_all rotate_16b_
|
||||
|
||||
# disable binary constraint mode for synth run checkpoints
|
||||
set_param constraints.enableBinaryConstraints false
|
||||
write_checkpoint -force -noxdef rotate_16b.dcp
|
||||
create_report "rotate_16b_synth_1_synth_report_utilization_0" "report_utilization -file rotate_16b_utilization_synth.rpt -pb rotate_16b_utilization_synth.pb"
|
||||
|
||||
if { [catch {
|
||||
write_verilog -force -mode synth_stub D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/rotate_16b_stub.v
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_vhdl -force -mode synth_stub D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/rotate_16b_stub.vhdl
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_verilog -force -mode funcsim D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/rotate_16b_sim_netlist.v
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_vhdl -force -mode funcsim D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/rotate_16b_sim_netlist.vhdl
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
|
||||
} else {
|
||||
|
||||
|
||||
}; # end if cached_ip
|
||||
|
||||
add_files D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/rotate_16b_stub.v -of_objects [get_files D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/rotate_16b/rotate_16b.xci]
|
||||
|
||||
add_files D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/rotate_16b_stub.vhdl -of_objects [get_files D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/rotate_16b/rotate_16b.xci]
|
||||
|
||||
add_files D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/rotate_16b_sim_netlist.v -of_objects [get_files D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/rotate_16b/rotate_16b.xci]
|
||||
|
||||
add_files D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/rotate_16b_sim_netlist.vhdl -of_objects [get_files D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/rotate_16b/rotate_16b.xci]
|
||||
|
||||
add_files D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/rotate_16b.dcp -of_objects [get_files D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/rotate_16b/rotate_16b.xci]
|
||||
|
||||
if {[file isdir D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/ip_user_files/ip/rotate_16b]} {
|
||||
catch {
|
||||
file copy -force D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/rotate_16b_sim_netlist.v D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/ip_user_files/ip/rotate_16b
|
||||
}
|
||||
}
|
||||
|
||||
if {[file isdir D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/ip_user_files/ip/rotate_16b]} {
|
||||
catch {
|
||||
file copy -force D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/rotate_16b_sim_netlist.vhdl D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/ip_user_files/ip/rotate_16b
|
||||
}
|
||||
}
|
||||
|
||||
if {[file isdir D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/ip_user_files/ip/rotate_16b]} {
|
||||
catch {
|
||||
file copy -force D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/rotate_16b_stub.v D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/ip_user_files/ip/rotate_16b
|
||||
}
|
||||
}
|
||||
|
||||
if {[file isdir D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/ip_user_files/ip/rotate_16b]} {
|
||||
catch {
|
||||
file copy -force D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/rotate_16b_stub.vhdl D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/ip_user_files/ip/rotate_16b
|
||||
}
|
||||
}
|
||||
file delete __synthesis_is_running__
|
||||
close [open __synthesis_is_complete__ w]
|
||||
+452
@@ -0,0 +1,452 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2019.1.3 (64-bit)
|
||||
# SW Build 2644227 on Wed Sep 4 09:45:24 MDT 2019
|
||||
# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
|
||||
# Start of session at: Sun Mar 19 11:33:55 2023
|
||||
# Process ID: 31100
|
||||
# Current directory: D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1
|
||||
# Command line: vivado.exe -log rotate_16b.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source rotate_16b.tcl
|
||||
# Log file: D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/rotate_16b.vds
|
||||
# Journal file: D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1\vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
Sourcing tcl script 'C:/Users/Josh/AppData/Roaming/Xilinx/Vivado/Vivado_init.tcl'
|
||||
source rotate_16b.tcl -notrace
|
||||
Command: synth_design -top rotate_16b -part xc7k410tffg900-2 -mode out_of_context
|
||||
Starting synth_design
|
||||
Attempting to get a license for feature 'Synthesis' and/or device 'xc7k410t'
|
||||
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k410t'
|
||||
INFO: [Device 21-403] Loading part xc7k410tffg900-2
|
||||
INFO: Launching helper process for spawning children vivado processes
|
||||
INFO: Helper process launched with PID 8356
|
||||
---------------------------------------------------------------------------------
|
||||
Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:04 . Memory (MB): peak = 885.336 ; gain = 177.246
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-638] synthesizing module 'rotate_16b' [d:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/rotate_16b/synth/rotate_16b.vhd:71]
|
||||
Parameter C_ARCHITECTURE bound to: 2 - type: integer
|
||||
Parameter C_CORDIC_FUNCTION bound to: 0 - type: integer
|
||||
Parameter C_COARSE_ROTATE bound to: 1 - type: integer
|
||||
Parameter C_DATA_FORMAT bound to: 0 - type: integer
|
||||
Parameter C_XDEVICEFAMILY bound to: kintex7 - type: string
|
||||
Parameter C_HAS_ACLKEN bound to: 0 - type: integer
|
||||
Parameter C_HAS_ACLK bound to: 1 - type: integer
|
||||
Parameter C_HAS_S_AXIS_CARTESIAN bound to: 1 - type: integer
|
||||
Parameter C_HAS_S_AXIS_PHASE bound to: 1 - type: integer
|
||||
Parameter C_HAS_ARESETN bound to: 0 - type: integer
|
||||
Parameter C_INPUT_WIDTH bound to: 16 - type: integer
|
||||
Parameter C_ITERATIONS bound to: 0 - type: integer
|
||||
Parameter C_OUTPUT_WIDTH bound to: 16 - type: integer
|
||||
Parameter C_PHASE_FORMAT bound to: 1 - type: integer
|
||||
Parameter C_PIPELINE_MODE bound to: -2 - type: integer
|
||||
Parameter C_PRECISION bound to: 0 - type: integer
|
||||
Parameter C_ROUND_MODE bound to: 0 - type: integer
|
||||
Parameter C_SCALE_COMP bound to: 0 - type: integer
|
||||
Parameter C_THROTTLE_SCHEME bound to: 3 - type: integer
|
||||
Parameter C_TLAST_RESOLUTION bound to: 0 - type: integer
|
||||
Parameter C_HAS_S_AXIS_PHASE_TUSER bound to: 0 - type: integer
|
||||
Parameter C_HAS_S_AXIS_PHASE_TLAST bound to: 0 - type: integer
|
||||
Parameter C_S_AXIS_PHASE_TDATA_WIDTH bound to: 16 - type: integer
|
||||
Parameter C_S_AXIS_PHASE_TUSER_WIDTH bound to: 1 - type: integer
|
||||
Parameter C_HAS_S_AXIS_CARTESIAN_TUSER bound to: 0 - type: integer
|
||||
Parameter C_HAS_S_AXIS_CARTESIAN_TLAST bound to: 0 - type: integer
|
||||
Parameter C_S_AXIS_CARTESIAN_TDATA_WIDTH bound to: 32 - type: integer
|
||||
Parameter C_S_AXIS_CARTESIAN_TUSER_WIDTH bound to: 1 - type: integer
|
||||
Parameter C_M_AXIS_DOUT_TDATA_WIDTH bound to: 32 - type: integer
|
||||
Parameter C_M_AXIS_DOUT_TUSER_WIDTH bound to: 1 - type: integer
|
||||
INFO: [Synth 8-3491] module 'cordic_v6_0_15' declared at 'd:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/rotate_16b/hdl/cordic_v6_0_vh_rfs.vhd:10135' bound to instance 'U0' of component 'cordic_v6_0_15' [d:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/rotate_16b/synth/rotate_16b.vhd:149]
|
||||
INFO: [Synth 8-256] done synthesizing module 'rotate_16b' (21#1) [d:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/rotate_16b/synth/rotate_16b.vhd:71]
|
||||
WARNING: [Synth 8-3331] design delay__parameterized6 has unconnected port WE
|
||||
WARNING: [Synth 8-3331] design delay__parameterized6 has unconnected port CE
|
||||
WARNING: [Synth 8-3331] design delay__parameterized6 has unconnected port SCLR
|
||||
WARNING: [Synth 8-3331] design delay__parameterized6 has unconnected port CLK
|
||||
WARNING: [Synth 8-3331] design c_reg_fd_v12_0_6_viv__parameterized2 has unconnected port CE
|
||||
WARNING: [Synth 8-3331] design c_reg_fd_v12_0_6_viv__parameterized2 has unconnected port AINIT
|
||||
WARNING: [Synth 8-3331] design c_reg_fd_v12_0_6_viv__parameterized2 has unconnected port ACLR
|
||||
WARNING: [Synth 8-3331] design c_reg_fd_v12_0_6_viv__parameterized2 has unconnected port ASET
|
||||
WARNING: [Synth 8-3331] design c_reg_fd_v12_0_6_viv__parameterized2 has unconnected port SINIT
|
||||
WARNING: [Synth 8-3331] design c_reg_fd_v12_0_6_viv__parameterized2 has unconnected port SCLR
|
||||
WARNING: [Synth 8-3331] design c_reg_fd_v12_0_6_viv__parameterized2 has unconnected port SSET
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_lut6_legacy__parameterized3 has unconnected port c_in
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_lut6_legacy__parameterized3 has unconnected port ce
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_lut6_legacy__parameterized3 has unconnected port bypass
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_lut6_legacy__parameterized3 has unconnected port sclr
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_lut6_legacy__parameterized3 has unconnected port sset
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_lut6_legacy__parameterized3 has unconnected port sinit
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_legacy__parameterized3 has unconnected port c_in
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_legacy__parameterized3 has unconnected port b_in
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_legacy__parameterized3 has unconnected port a_signed
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_legacy__parameterized3 has unconnected port b_signed
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_viv__parameterized3 has unconnected port C_IN
|
||||
WARNING: [Synth 8-3331] design cordic_round has unconnected port round_in[3]
|
||||
WARNING: [Synth 8-3331] design cordic_round has unconnected port round_in[2]
|
||||
WARNING: [Synth 8-3331] design cordic_round has unconnected port round_in[1]
|
||||
WARNING: [Synth 8-3331] design cordic_round has unconnected port round_in[0]
|
||||
WARNING: [Synth 8-3331] design delay_bit has unconnected port SCLR
|
||||
WARNING: [Synth 8-3331] design delay_bit__parameterized3 has unconnected port WE
|
||||
WARNING: [Synth 8-3331] design delay_bit__parameterized3 has unconnected port CE
|
||||
WARNING: [Synth 8-3331] design delay_bit__parameterized3 has unconnected port SCLR
|
||||
WARNING: [Synth 8-3331] design delay_bit__parameterized3 has unconnected port CLK
|
||||
WARNING: [Synth 8-3331] design cordic_out_config has unconnected port aclr
|
||||
WARNING: [Synth 8-3331] design cordic_ctrl_slice_par has unconnected port aclr
|
||||
WARNING: [Synth 8-3331] design cordic_eng has unconnected port nd_in
|
||||
WARNING: [Synth 8-3331] design c_reg_fd_v12_0_6_viv has unconnected port CE
|
||||
WARNING: [Synth 8-3331] design c_reg_fd_v12_0_6_viv has unconnected port AINIT
|
||||
WARNING: [Synth 8-3331] design c_reg_fd_v12_0_6_viv has unconnected port ACLR
|
||||
WARNING: [Synth 8-3331] design c_reg_fd_v12_0_6_viv has unconnected port ASET
|
||||
WARNING: [Synth 8-3331] design c_reg_fd_v12_0_6_viv has unconnected port SINIT
|
||||
WARNING: [Synth 8-3331] design c_reg_fd_v12_0_6_viv has unconnected port SCLR
|
||||
WARNING: [Synth 8-3331] design c_reg_fd_v12_0_6_viv has unconnected port SSET
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_lut6_legacy__parameterized1 has unconnected port add
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_lut6_legacy__parameterized1 has unconnected port c_in
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_lut6_legacy__parameterized1 has unconnected port ce
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_lut6_legacy__parameterized1 has unconnected port bypass
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_lut6_legacy__parameterized1 has unconnected port sclr
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_lut6_legacy__parameterized1 has unconnected port sset
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_lut6_legacy__parameterized1 has unconnected port sinit
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_legacy__parameterized1 has unconnected port c_in
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_legacy__parameterized1 has unconnected port b_in
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_legacy__parameterized1 has unconnected port a_signed
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_legacy__parameterized1 has unconnected port b_signed
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_viv__parameterized1 has unconnected port C_IN
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_lut6_legacy has unconnected port add
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_lut6_legacy has unconnected port c_in
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_lut6_legacy has unconnected port ce
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_lut6_legacy has unconnected port bypass
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_lut6_legacy has unconnected port sclr
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_lut6_legacy has unconnected port sset
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_lut6_legacy has unconnected port sinit
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_legacy has unconnected port c_in
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_legacy has unconnected port b_in
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_legacy has unconnected port a_signed
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_legacy has unconnected port b_signed
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_viv has unconnected port C_IN
|
||||
WARNING: [Synth 8-3331] design cordic_v6_0_15_synth has unconnected port ND
|
||||
WARNING: [Synth 8-3331] design cordic_v6_0_15_synth has unconnected port CE
|
||||
WARNING: [Synth 8-3331] design cordic_v6_0_15_synth has unconnected port SCLR
|
||||
WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv has unconnected port SCLR
|
||||
WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv has unconnected port SSET
|
||||
WARNING: [Synth 8-3331] design xbip_pipe_v3_0_6_viv has unconnected port SINIT
|
||||
WARNING: [Synth 8-3331] design cordic_v6_0_15_viv has unconnected port aclken
|
||||
WARNING: [Synth 8-3331] design cordic_v6_0_15_viv has unconnected port aresetn
|
||||
WARNING: [Synth 8-3331] design cordic_v6_0_15_viv has unconnected port s_axis_phase_tuser[0]
|
||||
WARNING: [Synth 8-3331] design cordic_v6_0_15_viv has unconnected port s_axis_phase_tlast
|
||||
WARNING: [Synth 8-3331] design cordic_v6_0_15_viv has unconnected port s_axis_cartesian_tuser[0]
|
||||
WARNING: [Synth 8-3331] design cordic_v6_0_15_viv has unconnected port s_axis_cartesian_tlast
|
||||
WARNING: [Synth 8-3331] design cordic_v6_0_15_viv has unconnected port m_axis_dout_tready
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:17 . Memory (MB): peak = 1010.500 ; gain = 302.410
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report Check Netlist:
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
| |Item |Errors |Warnings |Status |Description |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:04 ; elapsed = 00:00:17 . Memory (MB): peak = 1010.500 ; gain = 302.410
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:17 . Memory (MB): peak = 1010.500 ; gain = 302.410
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Netlist 29-17] Analyzing 2136 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
|
||||
Processing XDC Constraints
|
||||
Initializing timing engine
|
||||
Parsing XDC File [d:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/rotate_16b/rotate_16b_ooc.xdc] for cell 'U0'
|
||||
Finished Parsing XDC File [d:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/rotate_16b/rotate_16b_ooc.xdc] for cell 'U0'
|
||||
Parsing XDC File [D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/dont_touch.xdc]
|
||||
Finished Parsing XDC File [D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/dont_touch.xdc]
|
||||
Completed Processing XDC Constraints
|
||||
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1097.137 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.063 . Memory (MB): peak = 1109.258 ; gain = 12.121
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Constraint Validation : Time (s): cpu = 00:00:05 ; elapsed = 00:00:22 . Memory (MB): peak = 1109.258 ; gain = 401.168
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Loading Part and Timing Information
|
||||
---------------------------------------------------------------------------------
|
||||
Loading part: xc7k410tffg900-2
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:05 ; elapsed = 00:00:22 . Memory (MB): peak = 1109.258 ; gain = 401.168
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Applying 'set_property' XDC Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
Applied set_property DONT_TOUCH = true for U0. (constraint file D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/dont_touch.xdc, line 9).
|
||||
---------------------------------------------------------------------------------
|
||||
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:05 ; elapsed = 00:00:22 . Memory (MB): peak = 1109.258 ; gain = 401.168
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:22 . Memory (MB): peak = 1109.258 ; gain = 401.168
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Hierarchical Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Hierarchical Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
Part Resources:
|
||||
DSPs: 1540 (col length:140)
|
||||
BRAMs: 1590 (col length: RAMB18 140 RAMB36 70)
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Cross Boundary and Area Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
Warning: Parallel synthesis criteria is not met
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_viv__parameterized3 has unconnected port C_IN
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_viv__parameterized3 has unconnected port CE
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_viv__parameterized3 has unconnected port BYPASS
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_viv__parameterized3 has unconnected port SCLR
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_viv__parameterized3 has unconnected port SSET
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_viv__parameterized3 has unconnected port SINIT
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_viv__parameterized3__49 has unconnected port C_IN
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_viv__parameterized3__49 has unconnected port CE
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_viv__parameterized3__49 has unconnected port BYPASS
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_viv__parameterized3__49 has unconnected port SCLR
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_viv__parameterized3__49 has unconnected port SSET
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_viv__parameterized3__49 has unconnected port SINIT
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_viv__parameterized3__9 has unconnected port C_IN
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_viv__parameterized3__9 has unconnected port CE
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_viv__parameterized3__9 has unconnected port BYPASS
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_viv__parameterized3__9 has unconnected port SCLR
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_viv__parameterized3__9 has unconnected port SSET
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_viv__parameterized3__9 has unconnected port SINIT
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_viv__parameterized3__48 has unconnected port C_IN
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_viv__parameterized3__48 has unconnected port CE
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_viv__parameterized3__48 has unconnected port BYPASS
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_viv__parameterized3__48 has unconnected port SCLR
|
||||
INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.data_y_int_reg[0]' (FDR) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.data_y_int_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.data_x_int_reg[0]' (FDR) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.data_y_int_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.data_y_int_reg[1]' (FDR) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.data_y_int_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.data_x_int_reg[1]' (FDR) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.data_y_int_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.data_y_int_reg[2]' (FDR) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.data_y_int_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.data_x_int_reg[2]' (FDR) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.data_y_int_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.data_y_int_reg[3]' (FDR) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.data_x_int_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.data_x_int_reg[3]' (FDR) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.phase_int_reg[0]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.phase_int_reg[0]' (FDR) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.phase_int_reg[1]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.phase_int_reg[1]' (FDR) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.phase_int_reg[2]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.phase_int_reg[2]' (FDR) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.phase_int_reg[3]'
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\i_synth/gen_cordic.input_stage/gen_input_regs.phase_int_reg[3] )
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_phase.gen_phase_int_dly/gen_rtl.gen_reg.d_reg_reg[0]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[0].eng/cntrl/engine_mode_dly/gen_rtl.gen_reg.d_reg_reg'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_phase.gen_phase_int_dly/gen_rtl.gen_reg.d_reg_reg[1]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[0].eng/cntrl/engine_mode_dly/gen_rtl.gen_reg.d_reg_reg'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_phase.gen_phase_int_dly/gen_rtl.gen_reg.d_reg_reg[2]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[0].eng/cntrl/engine_mode_dly/gen_rtl.gen_reg.d_reg_reg'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_phase.gen_phase_int_dly/gen_rtl.gen_reg.d_reg_reg[3]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[0].eng/cntrl/engine_mode_dly/gen_rtl.gen_reg.d_reg_reg'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_x_int_dly/gen_rtl.gen_reg.d_reg_reg[0]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[0].eng/cntrl/engine_mode_dly/gen_rtl.gen_reg.d_reg_reg'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[0]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[0].eng/cntrl/engine_mode_dly/gen_rtl.gen_reg.d_reg_reg'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_x_int_dly/gen_rtl.gen_reg.d_reg_reg[1]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[0].eng/cntrl/engine_mode_dly/gen_rtl.gen_reg.d_reg_reg'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[1]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[0].eng/cntrl/engine_mode_dly/gen_rtl.gen_reg.d_reg_reg'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_x_int_dly/gen_rtl.gen_reg.d_reg_reg[2]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[0].eng/cntrl/engine_mode_dly/gen_rtl.gen_reg.d_reg_reg'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[2]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[0].eng/cntrl/engine_mode_dly/gen_rtl.gen_reg.d_reg_reg'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_x_int_dly/gen_rtl.gen_reg.d_reg_reg[3]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[0].eng/cntrl/engine_mode_dly/gen_rtl.gen_reg.d_reg_reg'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[3]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[0].eng/cntrl/engine_mode_dly/gen_rtl.gen_reg.d_reg_reg'
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[0].eng/cntrl/engine_mode_dly/gen_rtl.gen_reg.d_reg_reg )
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[1].eng/cntrl/engine_mode_dly/gen_rtl.gen_reg.d_reg_reg' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[0].eng/cntrl/engine_mode_dly/gen_rtl.gen_reg.d_reg_reg'
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[0].eng/cntrl/engine_mode_dly/gen_rtl.gen_reg.d_reg_reg )
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[2].eng/cntrl/engine_mode_dly/gen_rtl.gen_reg.d_reg_reg' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[0].eng/cntrl/engine_mode_dly/gen_rtl.gen_reg.d_reg_reg'
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[0].eng/cntrl/engine_mode_dly/gen_rtl.gen_reg.d_reg_reg )
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[3].eng/cntrl/engine_mode_dly/gen_rtl.gen_reg.d_reg_reg' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[0].eng/cntrl/engine_mode_dly/gen_rtl.gen_reg.d_reg_reg'
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[0].eng/cntrl/engine_mode_dly/gen_rtl.gen_reg.d_reg_reg )
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[4].eng/cntrl/engine_mode_dly/gen_rtl.gen_reg.d_reg_reg' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[0].eng/cntrl/engine_mode_dly/gen_rtl.gen_reg.d_reg_reg'
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[0].eng/cntrl/engine_mode_dly/gen_rtl.gen_reg.d_reg_reg )
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[5].eng/cntrl/engine_mode_dly/gen_rtl.gen_reg.d_reg_reg' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[0].eng/cntrl/engine_mode_dly/gen_rtl.gen_reg.d_reg_reg'
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[0].eng/cntrl/engine_mode_dly/gen_rtl.gen_reg.d_reg_reg )
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[6].eng/cntrl/engine_mode_dly/gen_rtl.gen_reg.d_reg_reg' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[0].eng/cntrl/engine_mode_dly/gen_rtl.gen_reg.d_reg_reg'
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[0].eng/cntrl/engine_mode_dly/gen_rtl.gen_reg.d_reg_reg )
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[7].eng/cntrl/engine_mode_dly/gen_rtl.gen_reg.d_reg_reg' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[0].eng/cntrl/engine_mode_dly/gen_rtl.gen_reg.d_reg_reg'
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[0].eng/cntrl/engine_mode_dly/gen_rtl.gen_reg.d_reg_reg )
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[8].eng/cntrl/engine_mode_dly/gen_rtl.gen_reg.d_reg_reg' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[0].eng/cntrl/engine_mode_dly/gen_rtl.gen_reg.d_reg_reg'
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[0].eng/cntrl/engine_mode_dly/gen_rtl.gen_reg.d_reg_reg )
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[9].eng/cntrl/engine_mode_dly/gen_rtl.gen_reg.d_reg_reg' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[0].eng/cntrl/engine_mode_dly/gen_rtl.gen_reg.d_reg_reg'
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[0].eng/cntrl/engine_mode_dly/gen_rtl.gen_reg.d_reg_reg )
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[10].eng/cntrl/engine_mode_dly/gen_rtl.gen_reg.d_reg_reg' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[0].eng/cntrl/engine_mode_dly/gen_rtl.gen_reg.d_reg_reg'
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[0].eng/cntrl/engine_mode_dly/gen_rtl.gen_reg.d_reg_reg )
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[11].eng/cntrl/engine_mode_dly/gen_rtl.gen_reg.d_reg_reg' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[0].eng/cntrl/engine_mode_dly/gen_rtl.gen_reg.d_reg_reg'
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[0].eng/cntrl/engine_mode_dly/gen_rtl.gen_reg.d_reg_reg )
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[12].eng/cntrl/engine_mode_dly/gen_rtl.gen_reg.d_reg_reg' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[0].eng/cntrl/engine_mode_dly/gen_rtl.gen_reg.d_reg_reg'
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[0].eng/cntrl/engine_mode_dly/gen_rtl.gen_reg.d_reg_reg )
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:06 ; elapsed = 00:00:24 . Memory (MB): peak = 1109.258 ; gain = 401.168
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Applying XDC Timing Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:07 ; elapsed = 00:00:29 . Memory (MB): peak = 1109.258 ; gain = 401.168
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Timing Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Timing Optimization : Time (s): cpu = 00:00:07 ; elapsed = 00:00:29 . Memory (MB): peak = 1109.258 ; gain = 401.168
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Technology Mapping
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Technology Mapping : Time (s): cpu = 00:00:07 ; elapsed = 00:00:30 . Memory (MB): peak = 1109.258 ; gain = 401.168
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished IO Insertion : Time (s): cpu = 00:00:07 ; elapsed = 00:00:31 . Memory (MB): peak = 1109.258 ; gain = 401.168
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report Check Netlist:
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
| |Item |Errors |Warnings |Status |Description |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Instances
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:00:07 ; elapsed = 00:00:31 . Memory (MB): peak = 1109.258 ; gain = 401.168
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Rebuilding User Hierarchy
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:07 ; elapsed = 00:00:32 . Memory (MB): peak = 1109.258 ; gain = 401.168
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Ports
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:00:07 ; elapsed = 00:00:32 . Memory (MB): peak = 1109.258 ; gain = 401.168
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:32 . Memory (MB): peak = 1109.258 ; gain = 401.168
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Nets
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:00:07 ; elapsed = 00:00:32 . Memory (MB): peak = 1109.258 ; gain = 401.168
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Writing Synthesis Report
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report BlackBoxes:
|
||||
+-+--------------+----------+
|
||||
| |BlackBox name |Instances |
|
||||
+-+--------------+----------+
|
||||
+-+--------------+----------+
|
||||
|
||||
Report Cell Usage:
|
||||
+------+--------+------+
|
||||
| |Cell |Count |
|
||||
+------+--------+------+
|
||||
|1 |LUT1 | 70|
|
||||
|2 |LUT2 | 416|
|
||||
|3 |LUT3 | 592|
|
||||
|4 |LUT4 | 36|
|
||||
|5 |LUT5 | 3|
|
||||
|6 |LUT6 | 15|
|
||||
|7 |MUXCY | 971|
|
||||
|8 |SRL16E | 5|
|
||||
|9 |SRLC32E | 1|
|
||||
|10 |XORCY | 917|
|
||||
|11 |FDRE | 1105|
|
||||
+------+--------+------+
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:00:07 ; elapsed = 00:00:32 . Memory (MB): peak = 1109.258 ; gain = 401.168
|
||||
---------------------------------------------------------------------------------
|
||||
Synthesis finished with 0 errors, 0 critical warnings and 321 warnings.
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:00:02 ; elapsed = 00:00:29 . Memory (MB): peak = 1109.258 ; gain = 302.410
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:00:07 ; elapsed = 00:00:32 . Memory (MB): peak = 1109.258 ; gain = 401.168
|
||||
INFO: [Project 1-571] Translating synthesized netlist
|
||||
INFO: [Netlist 29-17] Analyzing 1888 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1126.176 ; gain = 0.000
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
A total of 257 instances were transformed.
|
||||
(MUXCY,XORCY) => CARRY4: 257 instances
|
||||
|
||||
INFO: [Common 17-83] Releasing license: Synthesis
|
||||
66 Infos, 100 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
synth_design completed successfully
|
||||
synth_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:39 . Memory (MB): peak = 1126.176 ; gain = 738.902
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1126.176 ; gain = 0.000
|
||||
WARNING: [Constraints 18-5210] No constraints selected for write.
|
||||
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
|
||||
INFO: [Common 17-1381] The checkpoint 'D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/rotate_16b.dcp' has been generated.
|
||||
WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used.
|
||||
INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP rotate_16b, cache-ID = 2387465c02ffa019
|
||||
INFO: [Coretcl 2-1174] Renamed 371 cell refs.
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1126.176 ; gain = 0.000
|
||||
WARNING: [Constraints 18-5210] No constraints selected for write.
|
||||
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
|
||||
INFO: [Common 17-1381] The checkpoint 'D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/rotate_16b.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_utilization -file rotate_16b_utilization_synth.rpt -pb rotate_16b_utilization_synth.pb
|
||||
INFO: [Common 17-206] Exiting Vivado at Sun Mar 19 11:34:41 2023...
|
||||
BIN
Binary file not shown.
BIN
Binary file not shown.
+28
@@ -0,0 +1,28 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
// Date : Sun Mar 19 11:34:40 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/rotate_16b_stub.v
|
||||
// Design : rotate_16b
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "cordic_v6_0_15,Vivado 2019.1.3" *)
|
||||
module rotate_16b(aclk, s_axis_phase_tvalid,
|
||||
s_axis_phase_tdata, s_axis_cartesian_tvalid, s_axis_cartesian_tdata,
|
||||
m_axis_dout_tvalid, m_axis_dout_tdata)
|
||||
/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_phase_tvalid,s_axis_phase_tdata[15:0],s_axis_cartesian_tvalid,s_axis_cartesian_tdata[31:0],m_axis_dout_tvalid,m_axis_dout_tdata[31:0]" */;
|
||||
input aclk;
|
||||
input s_axis_phase_tvalid;
|
||||
input [15:0]s_axis_phase_tdata;
|
||||
input s_axis_cartesian_tvalid;
|
||||
input [31:0]s_axis_cartesian_tdata;
|
||||
output m_axis_dout_tvalid;
|
||||
output [31:0]m_axis_dout_tdata;
|
||||
endmodule
|
||||
+36
@@ -0,0 +1,36 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
-- Date : Sun Mar 19 11:34:40 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/rotate_16b_stub.vhdl
|
||||
-- Design : rotate_16b
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity rotate_16b is
|
||||
Port (
|
||||
aclk : in STD_LOGIC;
|
||||
s_axis_phase_tvalid : in STD_LOGIC;
|
||||
s_axis_phase_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
s_axis_cartesian_tvalid : in STD_LOGIC;
|
||||
s_axis_cartesian_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
m_axis_dout_tvalid : out STD_LOGIC;
|
||||
m_axis_dout_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 )
|
||||
);
|
||||
|
||||
end rotate_16b;
|
||||
|
||||
architecture stub of rotate_16b is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_phase_tvalid,s_axis_phase_tdata[15:0],s_axis_cartesian_tvalid,s_axis_cartesian_tdata[31:0],m_axis_dout_tvalid,m_axis_dout_tdata[31:0]";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "cordic_v6_0_15,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
BIN
Binary file not shown.
+184
@@ -0,0 +1,184 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
---------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
| Date : Sun Mar 19 11:34:40 2023
|
||||
| Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
| Command : report_utilization -file rotate_16b_utilization_synth.rpt -pb rotate_16b_utilization_synth.pb
|
||||
| Design : rotate_16b
|
||||
| Device : 7k410tffg900-2
|
||||
| Design State : Synthesized
|
||||
---------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Utilization Design Information
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Slice Logic
|
||||
1.1 Summary of Registers by Type
|
||||
2. Memory
|
||||
3. DSP
|
||||
4. IO and GT Specific
|
||||
5. Clocking
|
||||
6. Specific Feature
|
||||
7. Primitives
|
||||
8. Black Boxes
|
||||
9. Instantiated Netlists
|
||||
|
||||
1. Slice Logic
|
||||
--------------
|
||||
|
||||
+----------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+----------------------------+------+-------+-----------+-------+
|
||||
| Slice LUTs* | 1105 | 0 | 254200 | 0.43 |
|
||||
| LUT as Logic | 1099 | 0 | 254200 | 0.43 |
|
||||
| LUT as Memory | 6 | 0 | 90600 | <0.01 |
|
||||
| LUT as Distributed RAM | 0 | 0 | | |
|
||||
| LUT as Shift Register | 6 | 0 | | |
|
||||
| Slice Registers | 1105 | 0 | 508400 | 0.22 |
|
||||
| Register as Flip Flop | 1105 | 0 | 508400 | 0.22 |
|
||||
| Register as Latch | 0 | 0 | 508400 | 0.00 |
|
||||
| F7 Muxes | 0 | 0 | 127100 | 0.00 |
|
||||
| F8 Muxes | 0 | 0 | 63550 | 0.00 |
|
||||
+----------------------------+------+-------+-----------+-------+
|
||||
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
|
||||
|
||||
|
||||
1.1 Summary of Registers by Type
|
||||
--------------------------------
|
||||
|
||||
+-------+--------------+-------------+--------------+
|
||||
| Total | Clock Enable | Synchronous | Asynchronous |
|
||||
+-------+--------------+-------------+--------------+
|
||||
| 0 | _ | - | - |
|
||||
| 0 | _ | - | Set |
|
||||
| 0 | _ | - | Reset |
|
||||
| 0 | _ | Set | - |
|
||||
| 0 | _ | Reset | - |
|
||||
| 0 | Yes | - | - |
|
||||
| 0 | Yes | - | Set |
|
||||
| 0 | Yes | - | Reset |
|
||||
| 0 | Yes | Set | - |
|
||||
| 1105 | Yes | Reset | - |
|
||||
+-------+--------------+-------------+--------------+
|
||||
|
||||
|
||||
2. Memory
|
||||
---------
|
||||
|
||||
+----------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+----------------+------+-------+-----------+-------+
|
||||
| Block RAM Tile | 0 | 0 | 795 | 0.00 |
|
||||
| RAMB36/FIFO* | 0 | 0 | 795 | 0.00 |
|
||||
| RAMB18 | 0 | 0 | 1590 | 0.00 |
|
||||
+----------------+------+-------+-----------+-------+
|
||||
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
|
||||
|
||||
|
||||
3. DSP
|
||||
------
|
||||
|
||||
+-----------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-----------+------+-------+-----------+-------+
|
||||
| DSPs | 0 | 0 | 1540 | 0.00 |
|
||||
+-----------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
4. IO and GT Specific
|
||||
---------------------
|
||||
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Bonded IOB | 0 | 0 | 500 | 0.00 |
|
||||
| Bonded IPADs | 0 | 0 | 50 | 0.00 |
|
||||
| Bonded OPADs | 0 | 0 | 32 | 0.00 |
|
||||
| PHY_CONTROL | 0 | 0 | 10 | 0.00 |
|
||||
| PHASER_REF | 0 | 0 | 10 | 0.00 |
|
||||
| OUT_FIFO | 0 | 0 | 40 | 0.00 |
|
||||
| IN_FIFO | 0 | 0 | 40 | 0.00 |
|
||||
| IDELAYCTRL | 0 | 0 | 10 | 0.00 |
|
||||
| IBUFDS | 0 | 0 | 480 | 0.00 |
|
||||
| GTXE2_COMMON | 0 | 0 | 4 | 0.00 |
|
||||
| GTXE2_CHANNEL | 0 | 0 | 16 | 0.00 |
|
||||
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 40 | 0.00 |
|
||||
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 40 | 0.00 |
|
||||
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 500 | 0.00 |
|
||||
| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 |
|
||||
| IBUFDS_GTE2 | 0 | 0 | 8 | 0.00 |
|
||||
| ILOGIC | 0 | 0 | 500 | 0.00 |
|
||||
| OLOGIC | 0 | 0 | 500 | 0.00 |
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
5. Clocking
|
||||
-----------
|
||||
|
||||
+------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+------------+------+-------+-----------+-------+
|
||||
| BUFGCTRL | 0 | 0 | 32 | 0.00 |
|
||||
| BUFIO | 0 | 0 | 40 | 0.00 |
|
||||
| MMCME2_ADV | 0 | 0 | 10 | 0.00 |
|
||||
| PLLE2_ADV | 0 | 0 | 10 | 0.00 |
|
||||
| BUFMRCE | 0 | 0 | 20 | 0.00 |
|
||||
| BUFHCE | 0 | 0 | 168 | 0.00 |
|
||||
| BUFR | 0 | 0 | 40 | 0.00 |
|
||||
+------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
6. Specific Feature
|
||||
-------------------
|
||||
|
||||
+-------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-------------+------+-------+-----------+-------+
|
||||
| BSCANE2 | 0 | 0 | 4 | 0.00 |
|
||||
| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
|
||||
| DNA_PORT | 0 | 0 | 1 | 0.00 |
|
||||
| EFUSE_USR | 0 | 0 | 1 | 0.00 |
|
||||
| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
|
||||
| ICAPE2 | 0 | 0 | 2 | 0.00 |
|
||||
| PCIE_2_1 | 0 | 0 | 1 | 0.00 |
|
||||
| STARTUPE2 | 0 | 0 | 1 | 0.00 |
|
||||
| XADC | 0 | 0 | 1 | 0.00 |
|
||||
+-------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
7. Primitives
|
||||
-------------
|
||||
|
||||
+----------+------+---------------------+
|
||||
| Ref Name | Used | Functional Category |
|
||||
+----------+------+---------------------+
|
||||
| FDRE | 1105 | Flop & Latch |
|
||||
| LUT3 | 592 | LUT |
|
||||
| LUT2 | 416 | LUT |
|
||||
| CARRY4 | 257 | CarryLogic |
|
||||
| LUT1 | 70 | LUT |
|
||||
| LUT4 | 36 | LUT |
|
||||
| LUT6 | 15 | LUT |
|
||||
| SRL16E | 5 | Distributed Memory |
|
||||
| LUT5 | 3 | LUT |
|
||||
| SRLC32E | 1 | Distributed Memory |
|
||||
+----------+------+---------------------+
|
||||
|
||||
|
||||
8. Black Boxes
|
||||
--------------
|
||||
|
||||
+----------+------+
|
||||
| Ref Name | Used |
|
||||
+----------+------+
|
||||
|
||||
|
||||
9. Instantiated Netlists
|
||||
------------------------
|
||||
|
||||
+----------+------+
|
||||
| Ref Name | Used |
|
||||
+----------+------+
|
||||
|
||||
|
||||
+36
@@ -0,0 +1,36 @@
|
||||
//
|
||||
// Vivado(TM)
|
||||
// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
//
|
||||
|
||||
var WshShell = new ActiveXObject( "WScript.Shell" );
|
||||
var ProcEnv = WshShell.Environment( "Process" );
|
||||
var PathVal = ProcEnv("PATH");
|
||||
if ( PathVal.length == 0 ) {
|
||||
PathVal = "C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2019.1/bin;";
|
||||
} else {
|
||||
PathVal = "C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado/2019.1/bin;" + PathVal;
|
||||
}
|
||||
|
||||
ProcEnv("PATH") = PathVal;
|
||||
|
||||
var RDScrFP = WScript.ScriptFullName;
|
||||
var RDScrN = WScript.ScriptName;
|
||||
var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
|
||||
var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
|
||||
eval( EAInclude(ISEJScriptLib) );
|
||||
|
||||
|
||||
ISEStep( "vivado",
|
||||
"-log rotate_16b.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source rotate_16b.tcl" );
|
||||
|
||||
|
||||
|
||||
function EAInclude( EAInclFilename ) {
|
||||
var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
|
||||
var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
|
||||
var EAIFContents = EAInclFile.ReadAll();
|
||||
EAInclFile.Close();
|
||||
return EAIFContents;
|
||||
}
|
||||
+10
@@ -0,0 +1,10 @@
|
||||
@echo off
|
||||
|
||||
rem Vivado (TM)
|
||||
rem runme.bat: a Vivado-generated Script
|
||||
rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
|
||||
set HD_SDIR=%~dp0
|
||||
cd /d "%HD_SDIR%"
|
||||
cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
|
||||
+43
@@ -0,0 +1,43 @@
|
||||
#!/bin/sh
|
||||
|
||||
#
|
||||
# Vivado(TM)
|
||||
# runme.sh: a Vivado-generated Runs Script for UNIX
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
echo "This script was generated under a different operating system."
|
||||
echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script"
|
||||
exit
|
||||
|
||||
if [ -z "$PATH" ]; then
|
||||
PATH=C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2019.1/bin
|
||||
else
|
||||
PATH=C:/Xilinx/SDK/2019.1/bin;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2019.1/ids_lite/ISE/lib/nt64:C:/Xilinx/Vivado/2019.1/bin:$PATH
|
||||
fi
|
||||
export PATH
|
||||
|
||||
if [ -z "$LD_LIBRARY_PATH" ]; then
|
||||
LD_LIBRARY_PATH=
|
||||
else
|
||||
LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
|
||||
fi
|
||||
export LD_LIBRARY_PATH
|
||||
|
||||
HD_PWD='D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1'
|
||||
cd "$HD_PWD"
|
||||
|
||||
HD_LOG=runme.log
|
||||
/bin/touch $HD_LOG
|
||||
|
||||
ISEStep="./ISEWrap.sh"
|
||||
EAStep()
|
||||
{
|
||||
$ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
|
||||
if [ $? -ne 0 ]
|
||||
then
|
||||
exit
|
||||
fi
|
||||
}
|
||||
|
||||
EAStep vivado -log rotate_16b.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source rotate_16b.tcl
|
||||
BIN
Binary file not shown.
@@ -0,0 +1,291 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Version="7" Minor="40" Path="D:/vivado-git/modules/xc7k410tffg900-2/multi_ch_cal/ip/managed_ip_project/managed_ip_project.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="12dc286d7ffc4913886490fb2ecd002f"/>
|
||||
<Option Name="Part" Val="xc7k410tffg900-2"/>
|
||||
<Option Name="CompiledLibDir" Val="C:/Mentor/CompLib/2019.1.3"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="C:/Mentor/CompLib/2019.1.3"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="BoardPart" Val=""/>
|
||||
<Option Name="SourceMgmtMode" Val="None"/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Managed_IP"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="TRUE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PPRDIR/../ip_user_files"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PPRDIR/../ip_user_files/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="DSAVendor" Val="xilinx"/>
|
||||
<Option Name="DSANumComputeUnits" Val="60"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="4"/>
|
||||
<Option Name="WTModelSimExportSim" Val="4"/>
|
||||
<Option Name="WTQuestaExportSim" Val="4"/>
|
||||
<Option Name="WTIesExportSim" Val="4"/>
|
||||
<Option Name="WTVcsExportSim" Val="4"/>
|
||||
<Option Name="WTRivieraExportSim" Val="4"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="4"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
<Option Name="SimTypes" Val="bfm"/>
|
||||
<Option Name="SimTypes" Val="tlm"/>
|
||||
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="31">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="atan2_16b" Type="BlockSrcs" RelSrcDir="$PSRCDIR/atan2_16b">
|
||||
<File Path="$PPRDIR/../atan2_16b.xcix">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../atan2_16b/atan2_16b.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="atan2_16b"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="rotate_16b" Type="BlockSrcs" RelSrcDir="$PSRCDIR/rotate_16b">
|
||||
<File Path="$PPRDIR/../rotate_16b.xcix">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../rotate_16b/rotate_16b.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="rotate_16b"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ActiveHDL">
|
||||
<Option Name="Description" Val="Active-HDL Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="10">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7k410tffg900-2" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
<Run Id="atan2_16b_synth_1" Type="Ft3:Synth" SrcSet="atan2_16b" Part="xc7k410tffg900-2" ConstrsSet="atan2_16b" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/atan2_16b_synth_1" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
<Run Id="rotate_16b_synth_1" Type="Ft3:Synth" SrcSet="rotate_16b" Part="xc7k410tffg900-2" ConstrsSet="rotate_16b" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/rotate_16b_synth_1" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
<Run Id="atan2_16b_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="atan2_16b" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="atan2_16b_synth_1" IncludeInArchive="false" GenFullBitstream="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
<Run Id="rotate_16b_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="rotate_16b" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="rotate_16b_synth_1" IncludeInArchive="false" GenFullBitstream="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<Board/>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
<BootPmcSettings Version="1" Minor="0">
|
||||
<Parameters>
|
||||
<Parameter Name="PMC_CDO.ATTRS.LOADADDR" Value="" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_FB_CLK" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_FREQ" Value="300" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_BUS_WIDTH" Value="x1" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_DATA_MODE" Value="Single" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_FREQ" Value="200" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_SLOT_TYPE" Value="SD 2.0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_FREQ" Value="200" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_SLOT_TYPE" Value="SD 2.0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSPI_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSPI_FREQ" Value="300" Type="string"/>
|
||||
<Parameter Name="BOOT.USB_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SMAP_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SMAP_DATA_WIDTH" Value="32 Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSC_FREQ" Value="33.333" Type="string"/>
|
||||
<Parameter Name="BOOT.SECONDARY.PCIE_ENABLE" Value="0" Type="string"/>
|
||||
</Parameters>
|
||||
</BootPmcSettings>
|
||||
</Project>
|
||||
Reference in New Issue
Block a user