josh/vivado-202401
Archived
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

first commit after restructuring

Browse Source
This commit is contained in:
josh
2023-04-13 13:33:41 +08:00
commit 3c2cd0ba29
15090 changed files with 6794217 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
modules/xc7z100ffg900-2/ad9361_mapping/testbenches/tb_ad9361_rx_map_cmos_dual.v
+114
View File
@@ -0,0 +1,114 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
// _ _ ____
// | | ___ ___| |__ / ___| __ _ ___
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
// \___/ \___/|___/_| |_| \____|\__,_|\___/
//
// Create Date: 2023/02/25 14:56:59
// Design Name:
// Module Name: tb_ad9361_rx_map_cmos_dual
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tb_ad9361_rx_map_cmos_dual;
reg rx_data_clk = 1'b1;
reg clk_2x_in = 1'b1;
reg clk_4x_in = 1'b1;
reg rst = 1'b1;
wire clk_in_rst, rx_data_clk_rst;
assign clk_in_rst = rst;
assign rx_data_clk_rst = rst;
reg rx_frame;
reg [11:0] rx_data;
reg rx_fifo_rst = 1'b0;
wire [11:0] rx_ch1_i, rx_ch1_q, rx_ch2_i, rx_ch2_q;
ad9361_rx_map_cmos_dual u_ad9361_rx_map_cmos_dual
(
.clk_2x_in (clk_2x_in ),// input clk_2x_in
.clk_in_rst (clk_in_rst ),// input clk_in_rst
.rx_data_clk (rx_data_clk ),// input rx_data_clk
.rx_data_clk_rst (rx_data_clk_rst ),// input rx_data_clk_rst
.rx_fifo_rst (rx_fifo_rst ),// input rx_fifo_rst
.rx_frame (rx_frame ),// input rx_frame
.rx_data (rx_data ),// input [11:0] rx_data
.rx_ch1_i (rx_ch1_i ),// output [11:0] rx_ch1_i
.rx_ch1_q (rx_ch1_q ),// output [11:0] rx_ch1_q
.rx_ch2_i (rx_ch2_i ),// output [11:0] rx_ch2_i
.rx_ch2_q (rx_ch2_q ) // output [11:0] rx_ch2_q
);
initial begin
#102 rst = 1'b0;
#10000 rx_fifo_rst = 1'b1;
#100 rx_fifo_rst = 1'b0;
end
always #5 clk_4x_in = ~clk_4x_in;
always begin
#3;
clk_2x_in = ~clk_2x_in;
#7;
end
always begin
#6;
rx_data_clk = ~rx_data_clk;
#14;
end
reg [1:0] rx_cnt;
always @(posedge clk_4x_in) begin
if (rst) begin
rx_cnt <= 'b0;
end
else begin
rx_cnt <= rx_cnt + 1'b1;
end
end
always @(posedge clk_4x_in) begin
if (rst) begin
rx_frame <= 'b0;
rx_data <= 'b0;
end
else begin
rx_data <= rx_data + 12'd1;
case (rx_cnt[1])
1'b0: begin
rx_frame <= 1'b1;
end
1'd1: begin
rx_frame <= 1'b0;
end
endcase
end
end
endmodule
modules/xc7z100ffg900-2/ad9361_mapping/testbenches/tb_ad9361_rx_map_cmos_single.v
+89
View File
@@ -0,0 +1,89 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
// _ _ ____
// | | ___ ___| |__ / ___| __ _ ___
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
// \___/ \___/|___/_| |_| \____|\__,_|\___/
//
// Create Date: 2022/07/01 17:37:27
// Design Name:
// Module Name: tb_ad9361_rx_map_cmos_single
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tb_ad9361_rx_map_cmos_single;
reg clk_in = 1'b1;
reg clk_2x_in = 1'b1;
reg rx_data_clk = 1'b1;
reg rst = 1'b1;
wire clk_in_rst, rx_data_clk_rst;
assign clk_in_rst = rst;
assign rx_data_clk_rst = rst;
reg rx_frame = 'b0;
reg [11:0] rx_data = 'b0;
reg rx_fifo_rst = 'b0;
wire [11:0] rx_data_i, rx_data_q;
ad9361_rx_map_cmos_single u_ad9361_rx_map_cmos_single
(
.clk_in (clk_in ),
.clk_in_rst (clk_in_rst ),
.rx_data_clk (rx_data_clk ),
.rx_data_clk_rst(rx_data_clk_rst),
.rx_fifo_rst (rx_fifo_rst ),
.rx_frame (rx_frame ),
.rx_data (rx_data ),
.rx_data_i (rx_data_i ),
.rx_data_q (rx_data_q )
);
initial begin
#102 rst = 1'b0;
#1000 rx_fifo_rst = 1'b1;
#100 rx_fifo_rst = 1'b0;
end
always begin
#5 clk_2x_in = ~clk_2x_in;
end
always begin
#3 rx_data_clk = ~rx_data_clk;
#7 clk_in = ~clk_in;
end
always @(posedge clk_2x_in) begin
if (rst) begin
rx_frame <= 'b0;
rx_data <= 'b0;
end
else begin
rx_frame <= ~rx_frame;
rx_data <= rx_data + 1'b1;
end
end
endmodule
modules/xc7z100ffg900-2/ad9361_mapping/testbenches/tb_ad9361_rx_map_lvds_dual.v
+121
View File
@@ -0,0 +1,121 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
// _ _ ____
// | | ___ ___| |__ / ___| __ _ ___
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
// \___/ \___/|___/_| |_| \____|\__,_|\___/
//
// Create Date: 2023/02/25 14:56:59
// Design Name:
// Module Name: tb_ad9361_rx_map_lvds_dual
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tb_ad9361_rx_map_lvds_dual;
reg rx_data_clk = 1'b1;
reg clk_4x_in = 1'b1;
reg clk_8x_in = 1'b1;
reg rst = 1'b1;
wire clk_in_rst, rx_data_clk_rst;
assign clk_in_rst = rst;
assign rx_data_clk_rst = rst;
reg rx_frame_p, rx_frame_n;
reg [5:0] rx_data_p, rx_data_n;
reg rx_fifo_rst = 1'b0;
wire [11:0] rx_ch1_i, rx_ch1_q, rx_ch2_i, rx_ch2_q;
ad9361_rx_map_lvds_dual u_ad9361_rx_map_lvds_dual
(
.clk_4x_in (clk_4x_in ),// input clk_4x_in
.clk_in_rst (clk_in_rst ),// input clk_in_rst
.rx_data_clk (rx_data_clk ),// input rx_data_clk
.rx_data_clk_rst (rx_data_clk_rst ),// input rx_data_clk_rst
.rx_fifo_rst (rx_fifo_rst ),// input rx_fifo_rst
.rx_frame_p (rx_frame_p ),// input rx_frame_p
.rx_frame_n (rx_frame_n ),// input rx_frame_n
.rx_data_p (rx_data_p ),// input [ 5:0] rx_data_p
.rx_data_n (rx_data_n ),// input [ 5:0] rx_data_n
.rx_ch1_i (rx_ch1_i ),// output [11:0] rx_ch1_i
.rx_ch1_q (rx_ch1_q ),// output [11:0] rx_ch1_q
.rx_ch2_i (rx_ch2_i ),// output [11:0] rx_ch2_i
.rx_ch2_q (rx_ch2_q ) // output [11:0] rx_ch2_q
);
initial begin
#102 rst = 1'b0;
#10000 rx_fifo_rst = 1'b1;
#100 rx_fifo_rst = 1'b0;
end
always #5 clk_8x_in = ~clk_8x_in;
always begin
#3;
clk_4x_in = ~clk_4x_in;
#7;
end
always begin
#23;
rx_data_clk = ~rx_data_clk;
#17;
end
reg [2:0] rx_cnt;
always @(posedge clk_8x_in) begin
if (rst) begin
rx_cnt <= 'b0;
end
else begin
rx_cnt <= rx_cnt + 1'b1;
end
end
always @(posedge clk_8x_in) begin
if (rst) begin
rx_frame_p <= 1'b0;
rx_frame_n <= 1'b1;
rx_data_p <= 6'b000000;
rx_data_n <= 6'b111111;
end
else begin
rx_data_p <= rx_data_p + 12'd1;
rx_data_n <= ~(rx_data_p + 12'd1);
case (rx_cnt[2])
1'b0: begin
rx_frame_p <= 1'b1;
rx_frame_n <= 1'b0;
end
1'd1: begin
rx_frame_p <= 1'b0;
rx_frame_n <= 1'b1;
end
endcase
end
end
endmodule
modules/xc7z100ffg900-2/ad9361_mapping/testbenches/tb_ad9361_tx_map_cmos_dual.v
+92
View File
@@ -0,0 +1,92 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
// _ _ ____
// | | ___ ___| |__ / ___| __ _ ___
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
// \___/ \___/|___/_| |_| \____|\__,_|\___/
//
// Create Date: 2023/02/25 14:56:59
// Design Name:
// Module Name: tb_ad9361_tx_map_cmos_dual
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tb_ad9361_tx_map_cmos_dual;
reg tx_data_clk = 1'b1;
reg clk_2x_in = 1'b1;
reg rst = 1'b1;
wire clk_in_rst, tx_data_clk_rst;
assign clk_in_rst = rst;
assign tx_data_clk_rst = rst;
reg [11:0] tx_ch1_i = 'b0;
reg [11:0] tx_ch1_q = 'b0;
reg [11:0] tx_ch2_i = 'b0;
reg [11:0] tx_ch2_q = 'b0;
wire clk_out;
wire tx_frame;
wire tx_data;
ad9361_tx_map_cmos_dual u_ad9361_tx_map_cmos_dual
(
.clk_2x_in (clk_2x_in ),
.clk_in_rst (clk_in_rst ),
.tx_data_clk (tx_data_clk ),
.tx_data_clk_rst(tx_data_clk_rst),
.tx_ch1_i (tx_ch1_i ),
.tx_ch1_q (tx_ch1_q ),
.tx_ch2_i (tx_ch2_i ),
.tx_ch2_q (tx_ch2_q ),
.clk_out (clk_out ),
.tx_frame (tx_frame ),
.tx_data (tx_data )
);
initial begin
#102 rst = 1'b0;
end
always #5 clk_2x_in = ~clk_2x_in;
always begin
#3;
tx_data_clk = ~tx_data_clk;
#7;
end
always @(posedge tx_data_clk) begin
if (tx_data_clk_rst) begin
tx_ch1_i <= 'b0;
tx_ch1_q <= 'b0;
tx_ch2_i <= 'b0;
tx_ch2_q <= 'b0;
end
else begin
tx_ch1_i <= tx_ch1_i + 12'd1;
tx_ch1_q <= tx_ch1_q + 12'd2;
tx_ch2_i <= tx_ch2_i + 12'd3;
tx_ch2_q <= tx_ch2_q + 12'd4;
end
end
endmodule
modules/xc7z100ffg900-2/ad9361_mapping/testbenches/tb_ad9361_tx_map_cmos_single.v
+77
View File
@@ -0,0 +1,77 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2023/02/25 14:56:59
// Design Name:
// Module Name: tb_ad9361_tx_map_cmos_single
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tb_ad9361_tx_map_cmos_single;
reg clk_in = 1'b1;
reg tx_data_clk = 1'b1;
reg rst = 1'b1;
wire clk_in_rst, tx_data_clk_rst;
assign clk_in_rst = rst;
assign tx_data_clk_rst = rst;
reg [11:0] tx_data_i = 'b0;
reg [11:0] tx_data_q = 'b0;
wire clk_out;
wire tx_frame;
wire tx_data;
ad9361_tx_map_cmos_single u_ad9361_tx_map_cmos_single
(
.clk_in (clk_in ),
.clk_in_rst (clk_in_rst ),
.tx_data_clk (tx_data_clk ),
.tx_data_clk_rst (tx_data_clk_rst ),
.tx_data_i (tx_data_i ),
.tx_data_q (tx_data_q ),
.clk_out (clk_out ),
.tx_frame (tx_frame ),
.tx_data (tx_data )
);
initial begin
#102 rst = 1'b0;
end
always begin
#3 clk_in = ~clk_in;
#7 tx_data_clk = ~tx_data_clk;
end
always @(posedge clk_in) begin
if (rst) begin
tx_data_i <= 'b0;
tx_data_q <= 'b0;
end
else begin
tx_data_i <= tx_data_i + 12'd1;
tx_data_q <= tx_data_q + 12'd2;
end
end
endmodule
modules/xc7z100ffg900-2/ad9361_mapping/testbenches/tb_ad9361_tx_map_lvds_dual.v
+95
View File
@@ -0,0 +1,95 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
// _ _ ____
// | | ___ ___| |__ / ___| __ _ ___
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
// \___/ \___/|___/_| |_| \____|\__,_|\___/
//
// Create Date: 2023/02/25 14:56:59
// Design Name:
// Module Name: tb_ad9361_tx_map_lvds_dual
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tb_ad9361_tx_map_lvds_dual;
reg tx_data_clk = 1'b1;
reg clk_4x_in = 1'b1;
reg rst = 1'b1;
wire clk_in_rst, tx_data_clk_rst;
assign clk_in_rst = rst;
assign tx_data_clk_rst = rst;
reg [11:0] tx_ch1_i = 'b0;
reg [11:0] tx_ch1_q = 'b0;
reg [11:0] tx_ch2_i = 'b0;
reg [11:0] tx_ch2_q = 'b0;
wire clk_out_p, clk_out_n;
wire tx_frame_p, tx_frame_n;
wire [5:0] tx_data_p, tx_data_n;
ad9361_tx_map_lvds_dual u_ad9361_tx_map_lvds_dual
(
.clk_4x_in (clk_4x_in ), // input clk_4x_in
.clk_in_rst (clk_in_rst ), // input clk_in_rst
.tx_data_clk (tx_data_clk ), // input tx_data_clk
.tx_data_clk_rst (tx_data_clk_rst ), // input tx_data_clk_rst
.tx_ch1_i (tx_ch1_i ), // input [11:0] tx_ch1_i
.tx_ch1_q (tx_ch1_q ), // input [11:0] tx_ch1_q
.tx_ch2_i (tx_ch2_i ), // input [11:0] tx_ch2_i
.tx_ch2_q (tx_ch2_q ), // input [11:0] tx_ch2_q
.clk_out_p (clk_out_p ), // output clk_out_p
.clk_out_n (clk_out_n ), // output clk_out_n
.tx_frame_p (tx_frame_p ), // output tx_frame_p
.tx_frame_n (tx_frame_n ), // output tx_frame_n
.tx_data_p (tx_data_p ), // output [ 5:0] tx_data_p
.tx_data_n (tx_data_n ) // output [ 5:0] tx_data_n
);
initial begin
#102 rst = 1'b0;
end
always #5 clk_4x_in = ~clk_4x_in;
always begin
#13;
tx_data_clk = ~tx_data_clk;
#7;
end
always @(posedge tx_data_clk) begin
if (tx_data_clk_rst) begin
tx_ch1_i <= 'b0;
tx_ch1_q <= 'b0;
tx_ch2_i <= 'b0;
tx_ch2_q <= 'b0;
end
else begin
tx_ch1_i <= tx_ch1_i + 12'd1;
tx_ch1_q <= tx_ch1_q + 12'd2;
tx_ch2_i <= tx_ch2_i + 12'd3;
tx_ch2_q <= tx_ch2_q + 12'd4;
end
end
endmodule