Archived
first commit after restructuring
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|
||||
-211,
|
||||
-231,
|
||||
-250,
|
||||
-268,
|
||||
-284,
|
||||
-298,
|
||||
-311,
|
||||
-322,
|
||||
-332,
|
||||
-340,
|
||||
-346,
|
||||
-351,
|
||||
-354,
|
||||
-356,
|
||||
-356,
|
||||
-354,
|
||||
-351,
|
||||
-347,
|
||||
-341,
|
||||
-333,
|
||||
-325,
|
||||
-314,
|
||||
-303,
|
||||
-291,
|
||||
-277,
|
||||
-263,
|
||||
-247,
|
||||
-231,
|
||||
-213,
|
||||
-195,
|
||||
-177,
|
||||
-158,
|
||||
-138,
|
||||
-118,
|
||||
-98,
|
||||
-77,
|
||||
-56,
|
||||
-36,
|
||||
-15,
|
||||
5,
|
||||
26,
|
||||
46,
|
||||
66,
|
||||
85,
|
||||
104,
|
||||
122,
|
||||
139,
|
||||
156,
|
||||
172,
|
||||
187,
|
||||
202,
|
||||
215,
|
||||
228,
|
||||
239,
|
||||
249,
|
||||
259,
|
||||
267,
|
||||
274,
|
||||
280,
|
||||
285,
|
||||
288,
|
||||
291,
|
||||
292,
|
||||
292,
|
||||
291,
|
||||
289,
|
||||
285,
|
||||
281,
|
||||
275,
|
||||
268,
|
||||
261,
|
||||
252,
|
||||
243,
|
||||
232,
|
||||
221,
|
||||
209,
|
||||
196,
|
||||
182,
|
||||
168,
|
||||
153,
|
||||
138,
|
||||
122,
|
||||
106,
|
||||
89,
|
||||
73,
|
||||
56,
|
||||
38,
|
||||
21,
|
||||
4,
|
||||
-13,
|
||||
-30,
|
||||
-47;
|
||||
@@ -0,0 +1,258 @@
|
||||
MEMORY_INITIALIZATION_RADIX = 10;
|
||||
MEMORY_INITIALIZATION_VECTOR =
|
||||
-2147483647,
|
||||
-2130640638,
|
||||
-2113797629,
|
||||
-2096954620,
|
||||
-2080111611,
|
||||
-2063268602,
|
||||
-2046425593,
|
||||
-2029582584,
|
||||
-2012739575,
|
||||
-1995896566,
|
||||
-1979053557,
|
||||
-1962210548,
|
||||
-1945367539,
|
||||
-1928524530,
|
||||
-1911681521,
|
||||
-1894838512,
|
||||
-1877995503,
|
||||
-1861152494,
|
||||
-1844309485,
|
||||
-1827466476,
|
||||
-1810623467,
|
||||
-1793780458,
|
||||
-1776937449,
|
||||
-1760094440,
|
||||
-1743251431,
|
||||
-1726408422,
|
||||
-1709565413,
|
||||
-1692722404,
|
||||
-1675879395,
|
||||
-1659036386,
|
||||
-1642193377,
|
||||
-1625350368,
|
||||
-1608507359,
|
||||
-1591664350,
|
||||
-1574821341,
|
||||
-1557978332,
|
||||
-1541135323,
|
||||
-1524292314,
|
||||
-1507449305,
|
||||
-1490606296,
|
||||
-1473763287,
|
||||
-1456920278,
|
||||
-1440077269,
|
||||
-1423234260,
|
||||
-1406391251,
|
||||
-1389548242,
|
||||
-1372705233,
|
||||
-1355862224,
|
||||
-1339019215,
|
||||
-1322176206,
|
||||
-1305333197,
|
||||
-1288490188,
|
||||
-1271647179,
|
||||
-1254804170,
|
||||
-1237961161,
|
||||
-1221118152,
|
||||
-1204275143,
|
||||
-1187432134,
|
||||
-1170589125,
|
||||
-1153746116,
|
||||
-1136903107,
|
||||
-1120060098,
|
||||
-1103217089,
|
||||
-1086374080,
|
||||
-1069531071,
|
||||
-1052688062,
|
||||
-1035845053,
|
||||
-1019002044,
|
||||
-1002159035,
|
||||
-985316026,
|
||||
-968473017,
|
||||
-951630008,
|
||||
-934786999,
|
||||
-917943990,
|
||||
-901100981,
|
||||
-884257972,
|
||||
-867414963,
|
||||
-850571954,
|
||||
-833728945,
|
||||
-816885936,
|
||||
-800042927,
|
||||
-783199918,
|
||||
-766356909,
|
||||
-749513900,
|
||||
-732670891,
|
||||
-715827882,
|
||||
-698984873,
|
||||
-682141864,
|
||||
-665298855,
|
||||
-648455846,
|
||||
-631612837,
|
||||
-614769828,
|
||||
-597926819,
|
||||
-581083810,
|
||||
-564240801,
|
||||
-547397792,
|
||||
-530554783,
|
||||
-513711774,
|
||||
-496868765,
|
||||
-480025756,
|
||||
-463182747,
|
||||
-446339738,
|
||||
-429496729,
|
||||
-412653720,
|
||||
-395810711,
|
||||
-378967702,
|
||||
-362124693,
|
||||
-345281684,
|
||||
-328438675,
|
||||
-311595666,
|
||||
-294752657,
|
||||
-277909648,
|
||||
-261066639,
|
||||
-244223630,
|
||||
-227380621,
|
||||
-210537612,
|
||||
-193694603,
|
||||
-176851594,
|
||||
-160008585,
|
||||
-143165576,
|
||||
-126322567,
|
||||
-109479558,
|
||||
-92636549,
|
||||
-75793540,
|
||||
-58950531,
|
||||
-42107522,
|
||||
-25264513,
|
||||
-8421504,
|
||||
8421504,
|
||||
25264513,
|
||||
42107522,
|
||||
58950531,
|
||||
75793540,
|
||||
92636549,
|
||||
109479558,
|
||||
126322567,
|
||||
143165576,
|
||||
160008585,
|
||||
176851594,
|
||||
193694603,
|
||||
210537612,
|
||||
227380621,
|
||||
244223630,
|
||||
261066639,
|
||||
277909648,
|
||||
294752657,
|
||||
311595666,
|
||||
328438675,
|
||||
345281684,
|
||||
362124693,
|
||||
378967702,
|
||||
395810711,
|
||||
412653720,
|
||||
429496729,
|
||||
446339738,
|
||||
463182747,
|
||||
480025756,
|
||||
496868765,
|
||||
513711774,
|
||||
530554783,
|
||||
547397792,
|
||||
564240801,
|
||||
581083810,
|
||||
597926819,
|
||||
614769828,
|
||||
631612837,
|
||||
648455846,
|
||||
665298855,
|
||||
682141864,
|
||||
698984873,
|
||||
715827882,
|
||||
732670891,
|
||||
749513900,
|
||||
766356909,
|
||||
783199918,
|
||||
800042927,
|
||||
816885936,
|
||||
833728945,
|
||||
850571954,
|
||||
867414963,
|
||||
884257972,
|
||||
901100981,
|
||||
917943990,
|
||||
934786999,
|
||||
951630008,
|
||||
968473017,
|
||||
985316026,
|
||||
1002159035,
|
||||
1019002044,
|
||||
1035845053,
|
||||
1052688062,
|
||||
1069531071,
|
||||
1086374080,
|
||||
1103217089,
|
||||
1120060098,
|
||||
1136903107,
|
||||
1153746116,
|
||||
1170589125,
|
||||
1187432134,
|
||||
1204275143,
|
||||
1221118152,
|
||||
1237961161,
|
||||
1254804170,
|
||||
1271647179,
|
||||
1288490188,
|
||||
1305333197,
|
||||
1322176206,
|
||||
1339019215,
|
||||
1355862224,
|
||||
1372705233,
|
||||
1389548242,
|
||||
1406391251,
|
||||
1423234260,
|
||||
1440077269,
|
||||
1456920278,
|
||||
1473763287,
|
||||
1490606296,
|
||||
1507449305,
|
||||
1524292314,
|
||||
1541135323,
|
||||
1557978332,
|
||||
1574821341,
|
||||
1591664350,
|
||||
1608507359,
|
||||
1625350368,
|
||||
1642193377,
|
||||
1659036386,
|
||||
1675879395,
|
||||
1692722404,
|
||||
1709565413,
|
||||
1726408422,
|
||||
1743251431,
|
||||
1760094440,
|
||||
1776937449,
|
||||
1793780458,
|
||||
1810623467,
|
||||
1827466476,
|
||||
1844309485,
|
||||
1861152494,
|
||||
1877995503,
|
||||
1894838512,
|
||||
1911681521,
|
||||
1928524530,
|
||||
1945367539,
|
||||
1962210548,
|
||||
1979053557,
|
||||
1995896566,
|
||||
2012739575,
|
||||
2029582584,
|
||||
2046425593,
|
||||
2063268602,
|
||||
2080111611,
|
||||
2096954620,
|
||||
2113797629,
|
||||
2130640638,
|
||||
2147483647;
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
@@ -0,0 +1 @@
|
||||
The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.
|
||||
@@ -0,0 +1,71 @@
|
||||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
// IP VLNV: xilinx.com:ip:cmpy:6.0
|
||||
// IP Revision: 17
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
cmpy_18x8 your_instance_name (
|
||||
.aclk(aclk), // input wire aclk
|
||||
.s_axis_a_tvalid(s_axis_a_tvalid), // input wire s_axis_a_tvalid
|
||||
.s_axis_a_tdata(s_axis_a_tdata), // input wire [47 : 0] s_axis_a_tdata
|
||||
.s_axis_b_tvalid(s_axis_b_tvalid), // input wire s_axis_b_tvalid
|
||||
.s_axis_b_tdata(s_axis_b_tdata), // input wire [15 : 0] s_axis_b_tdata
|
||||
.m_axis_dout_tvalid(m_axis_dout_tvalid), // output wire m_axis_dout_tvalid
|
||||
.m_axis_dout_tdata(m_axis_dout_tdata) // output wire [63 : 0] m_axis_dout_tdata
|
||||
);
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
// You must compile the wrapper file cmpy_18x8.v when simulating
|
||||
// the core, cmpy_18x8. When compiling the wrapper file, be sure to
|
||||
// reference the Verilog simulation library.
|
||||
|
||||
@@ -0,0 +1,87 @@
|
||||
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:cmpy:6.0
|
||||
-- IP Revision: 17
|
||||
|
||||
-- The following code must appear in the VHDL architecture header.
|
||||
|
||||
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
|
||||
COMPONENT cmpy_18x8
|
||||
PORT (
|
||||
aclk : IN STD_LOGIC;
|
||||
s_axis_a_tvalid : IN STD_LOGIC;
|
||||
s_axis_a_tdata : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
|
||||
s_axis_b_tvalid : IN STD_LOGIC;
|
||||
s_axis_b_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
m_axis_dout_tvalid : OUT STD_LOGIC;
|
||||
m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
||||
|
||||
-- The following code must appear in the VHDL architecture
|
||||
-- body. Substitute your own instance name and net names.
|
||||
|
||||
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
|
||||
your_instance_name : cmpy_18x8
|
||||
PORT MAP (
|
||||
aclk => aclk,
|
||||
s_axis_a_tvalid => s_axis_a_tvalid,
|
||||
s_axis_a_tdata => s_axis_a_tdata,
|
||||
s_axis_b_tvalid => s_axis_b_tvalid,
|
||||
s_axis_b_tdata => s_axis_b_tdata,
|
||||
m_axis_dout_tvalid => m_axis_dout_tvalid,
|
||||
m_axis_dout_tdata => m_axis_dout_tdata
|
||||
);
|
||||
-- INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
-- You must compile the wrapper file cmpy_18x8.vhd when simulating
|
||||
-- the core, cmpy_18x8. When compiling the wrapper file, be sure to
|
||||
-- reference the VHDL simulation library.
|
||||
|
||||
BIN
Binary file not shown.
BIN
Binary file not shown.
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|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Thu Mar 30 15:31:48 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/modules/xc7z100ffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x8_synth_1/cmpy_18x8_stub.v
|
||||
// Design : cmpy_18x8
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z100ffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "cmpy_v6_0_17,Vivado 2019.1.3" *)
|
||||
module cmpy_18x8(aclk, s_axis_a_tvalid, s_axis_a_tdata,
|
||||
s_axis_b_tvalid, s_axis_b_tdata, m_axis_dout_tvalid, m_axis_dout_tdata)
|
||||
/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_a_tvalid,s_axis_a_tdata[47:0],s_axis_b_tvalid,s_axis_b_tdata[15:0],m_axis_dout_tvalid,m_axis_dout_tdata[63:0]" */;
|
||||
input aclk;
|
||||
input s_axis_a_tvalid;
|
||||
input [47:0]s_axis_a_tdata;
|
||||
input s_axis_b_tvalid;
|
||||
input [15:0]s_axis_b_tdata;
|
||||
output m_axis_dout_tvalid;
|
||||
output [63:0]m_axis_dout_tdata;
|
||||
endmodule
|
||||
@@ -0,0 +1,36 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Thu Mar 30 15:31:48 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/modules/xc7z100ffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x8_synth_1/cmpy_18x8_stub.vhdl
|
||||
-- Design : cmpy_18x8
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z100ffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity cmpy_18x8 is
|
||||
Port (
|
||||
aclk : in STD_LOGIC;
|
||||
s_axis_a_tvalid : in STD_LOGIC;
|
||||
s_axis_a_tdata : in STD_LOGIC_VECTOR ( 47 downto 0 );
|
||||
s_axis_b_tvalid : in STD_LOGIC;
|
||||
s_axis_b_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
m_axis_dout_tvalid : out STD_LOGIC;
|
||||
m_axis_dout_tdata : out STD_LOGIC_VECTOR ( 63 downto 0 )
|
||||
);
|
||||
|
||||
end cmpy_18x8;
|
||||
|
||||
architecture stub of cmpy_18x8 is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_a_tvalid,s_axis_a_tdata[47:0],s_axis_b_tvalid,s_axis_b_tdata[15:0],m_axis_dout_tvalid,m_axis_dout_tdata[63:0]";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "cmpy_v6_0_17,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
+387
@@ -0,0 +1,387 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- (c) Copyright 2011 - 2013 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--------------------------------------------------------------------------------
|
||||
-- Description:
|
||||
-- This is an example testbench for the Complex Multiplier IP core.
|
||||
-- The testbench has been generated by Vivado to accompany the IP core
|
||||
-- instance you have generated.
|
||||
--
|
||||
-- This testbench is for demonstration purposes only. See note below for
|
||||
-- instructions on how to use it with your core.
|
||||
--
|
||||
-- See the Complex Multiplier product guide for further information
|
||||
-- about this core.
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Using this testbench
|
||||
--
|
||||
-- This testbench instantiates your generated Complex Multiplier core
|
||||
-- instance named "cmpy_18x8".
|
||||
--
|
||||
-- Use Vivado's Run Simulation flow to run this testbench. See the Vivado
|
||||
-- documentation for details.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
use ieee.math_real.all;
|
||||
|
||||
entity tb_cmpy_18x8 is
|
||||
end tb_cmpy_18x8;
|
||||
|
||||
architecture tb of tb_cmpy_18x8 is
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Timing constants
|
||||
-----------------------------------------------------------------------
|
||||
constant CLOCK_PERIOD : time := 100 ns;
|
||||
constant T_HOLD : time := 10 ns;
|
||||
constant T_STROBE : time := CLOCK_PERIOD - (1 ns);
|
||||
constant TEST_CYCLES : integer := 3000;
|
||||
constant PHASE_CYCLES : integer := 1000;
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- DUT input signals
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
-- General inputs
|
||||
signal aclk : std_logic := '0'; -- the master clock
|
||||
|
||||
-- Slave channel A inputs
|
||||
signal s_axis_a_tvalid : std_logic := '0'; -- TVALID for channel A
|
||||
signal s_axis_a_tdata : std_logic_vector(47 downto 0) := (others => '0'); -- TDATA for channel A
|
||||
|
||||
-- Slave channel B inputs
|
||||
signal s_axis_b_tvalid : std_logic := '0'; -- TVALID for channel B
|
||||
signal s_axis_b_tdata : std_logic_vector(15 downto 0) := (others => '0'); -- TDATA for channel B
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- DUT output signals
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
-- Master channel DOUT outputs
|
||||
signal m_axis_dout_tvalid : std_logic := '0'; -- TVALID for channel DOUT
|
||||
signal m_axis_dout_tdata : std_logic_vector(63 downto 0) := (others => '0'); -- TDATA for channel DOUT
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Aliases for AXI channel TDATA fields
|
||||
-- These are a convenience for viewing data in a simulator waveform viewer.
|
||||
-- If using ModelSim or Questa, add "-voptargs=+acc=n" to the vsim command
|
||||
-- to prevent the simulator optimizing away these signals.
|
||||
-----------------------------------------------------------------------
|
||||
signal s_axis_a_tdata_real : std_logic_vector(17 downto 0) := (others => '0');
|
||||
signal s_axis_a_tdata_imag : std_logic_vector(17 downto 0) := (others => '0');
|
||||
signal s_axis_b_tdata_real : std_logic_vector(7 downto 0) := (others => '0');
|
||||
signal s_axis_b_tdata_imag : std_logic_vector(7 downto 0) := (others => '0');
|
||||
signal m_axis_dout_tdata_real : std_logic_vector(26 downto 0) := (others => '0');
|
||||
signal m_axis_dout_tdata_imag : std_logic_vector(26 downto 0) := (others => '0');
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Testbench signals
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
signal cycles : integer := 0; -- Clock cycle counter
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Constants, types and functions to create input data
|
||||
-- Treat the complex multiplier as a mixer that is combining two
|
||||
-- sinusoids exp(+/-jwt) of different frequencies and amplitudes:
|
||||
-- channel A: exp(+jwt), frequency = clock / 30, amplitude = fullscale >> 3
|
||||
-- channel B: exp(-jwt), frequency = clock / 32, amplitude = fullscale
|
||||
-- The output of the complex multiplier is a sinusoid with a frequency
|
||||
-- equal to the difference between the input frequencies.
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
constant IP_A_DEPTH : integer := 30;
|
||||
constant IP_A_WIDTH : integer := 18;
|
||||
constant IP_A_SHIFT : integer := 3; -- bit shift for amplitude
|
||||
constant IP_B_DEPTH : integer := 32;
|
||||
constant IP_B_WIDTH : integer := 8;
|
||||
constant IP_B_SHIFT : integer := 0; -- no bit shift, max amplitude
|
||||
type T_IP_INT_ENTRY is record
|
||||
re : integer;
|
||||
im : integer;
|
||||
end record;
|
||||
type T_IP_A_ENTRY is record
|
||||
re : std_logic_vector(IP_A_WIDTH-1 downto 0);
|
||||
im : std_logic_vector(IP_A_WIDTH-1 downto 0);
|
||||
end record;
|
||||
type T_IP_B_ENTRY is record
|
||||
re : std_logic_vector(IP_B_WIDTH-1 downto 0);
|
||||
im : std_logic_vector(IP_B_WIDTH-1 downto 0);
|
||||
end record;
|
||||
type T_IP_A_TABLE is array (0 to IP_A_DEPTH-1) of T_IP_A_ENTRY;
|
||||
type T_IP_B_TABLE is array (0 to IP_B_DEPTH-1) of T_IP_B_ENTRY;
|
||||
|
||||
-- Common function to calculate sine and cosine values
|
||||
function create_ip_entry(index, depth, width : integer) return T_IP_INT_ENTRY is
|
||||
variable result : T_IP_INT_ENTRY;
|
||||
variable theta : real;
|
||||
variable limited_width : integer := width - 2;
|
||||
begin
|
||||
if limited_width > 30 then
|
||||
limited_width := 30;
|
||||
end if;
|
||||
theta := real(index) / real(depth) * 2.0 * MATH_PI;
|
||||
result.re := integer(round(cos(theta) * real(2**limited_width-1)));
|
||||
result.im := integer(round(sin(theta) * real(2**limited_width-1)));
|
||||
return result;
|
||||
end function create_ip_entry;
|
||||
|
||||
-- Use separate functions to calculate channel A and B sinusoids as they return different types
|
||||
function create_ip_a_table return T_IP_A_TABLE is
|
||||
variable result : T_IP_A_TABLE;
|
||||
variable entry_int : T_IP_INT_ENTRY;
|
||||
begin
|
||||
for i in 0 to IP_A_DEPTH-1 loop
|
||||
entry_int := create_ip_entry(i, IP_A_DEPTH, IP_A_WIDTH - IP_A_SHIFT);
|
||||
result(i).re := std_logic_vector(to_signed(entry_int.re, IP_A_WIDTH));
|
||||
result(i).im := std_logic_vector(to_signed(entry_int.im, IP_A_WIDTH));
|
||||
end loop;
|
||||
return result;
|
||||
end function create_ip_a_table;
|
||||
|
||||
function create_ip_b_table return T_IP_B_TABLE is
|
||||
variable result : T_IP_B_TABLE;
|
||||
variable entry_int : T_IP_INT_ENTRY;
|
||||
begin
|
||||
for i in 0 to IP_B_DEPTH-1 loop
|
||||
entry_int := create_ip_entry(IP_B_DEPTH-1-i, IP_B_DEPTH, IP_B_WIDTH - IP_B_SHIFT); -- note rotation direction
|
||||
result(i).re := std_logic_vector(to_signed(entry_int.re, IP_B_WIDTH));
|
||||
result(i).im := std_logic_vector(to_signed(entry_int.im, IP_B_WIDTH));
|
||||
end loop;
|
||||
return result;
|
||||
end function create_ip_b_table;
|
||||
|
||||
-- Call the functions to create the data
|
||||
constant IP_A_DATA : T_IP_A_TABLE := create_ip_a_table;
|
||||
constant IP_B_DATA : T_IP_B_TABLE := create_ip_b_table;
|
||||
|
||||
|
||||
begin
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Instantiate the DUT
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
dut : entity work.cmpy_18x8
|
||||
port map (
|
||||
aclk => aclk,
|
||||
s_axis_a_tvalid => s_axis_a_tvalid,
|
||||
s_axis_a_tdata => s_axis_a_tdata,
|
||||
s_axis_b_tvalid => s_axis_b_tvalid,
|
||||
s_axis_b_tdata => s_axis_b_tdata,
|
||||
m_axis_dout_tvalid => m_axis_dout_tvalid,
|
||||
m_axis_dout_tdata => m_axis_dout_tdata
|
||||
);
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Generate clock
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
clock_gen : process
|
||||
begin
|
||||
aclk <= '0';
|
||||
wait for CLOCK_PERIOD;
|
||||
loop
|
||||
cycles <= cycles + 1;
|
||||
aclk <= '0';
|
||||
wait for CLOCK_PERIOD/2;
|
||||
aclk <= '1';
|
||||
wait for CLOCK_PERIOD/2;
|
||||
if cycles >= TEST_CYCLES then
|
||||
report "Not a real failure. Simulation finished successfully. Test completed successfully" severity failure;
|
||||
wait;
|
||||
end if;
|
||||
end loop;
|
||||
end process clock_gen;
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Generate inputs
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
stimuli : process
|
||||
variable ip_a_index : integer := 0;
|
||||
variable ip_b_index : integer := 0;
|
||||
variable a_tvalid_nxt : std_logic := '0';
|
||||
variable b_tvalid_nxt : std_logic := '0';
|
||||
variable phase2_cycles : integer := 1;
|
||||
variable phase2_count : integer := 0;
|
||||
constant PHASE2_LIMIT : integer := 30;
|
||||
begin
|
||||
|
||||
-- Test is stopped in clock_gen process, use endless loop here
|
||||
loop
|
||||
|
||||
-- Drive inputs T_HOLD time after rising edge of clock
|
||||
wait until rising_edge(aclk);
|
||||
wait for T_HOLD;
|
||||
|
||||
-- Drive AXI TVALID signals to demonstrate different types of operation
|
||||
case cycles is -- do different types of operation at different phases of the test
|
||||
when 0 to PHASE_CYCLES * 1 - 1 =>
|
||||
-- Phase 1: inputs always valid, no missing input data
|
||||
a_tvalid_nxt := '1';
|
||||
b_tvalid_nxt := '1';
|
||||
when PHASE_CYCLES * 1 to PHASE_CYCLES * 2 - 1 =>
|
||||
-- Phase 2: deprive channel A of valid transactions at an increasing rate
|
||||
b_tvalid_nxt := '1';
|
||||
if phase2_count < phase2_cycles then
|
||||
a_tvalid_nxt := '0';
|
||||
else
|
||||
a_tvalid_nxt := '1';
|
||||
end if;
|
||||
phase2_count := phase2_count + 1;
|
||||
if phase2_count >= PHASE2_LIMIT then
|
||||
phase2_count := 0;
|
||||
phase2_cycles := phase2_cycles + 1;
|
||||
end if;
|
||||
when PHASE_CYCLES * 2 to PHASE_CYCLES * 3 - 1 =>
|
||||
-- Phase 3: deprive channel A of 1 out of 2 transactions, and channel B of 1 out of 3 transactions
|
||||
if cycles mod 2 = 0 then
|
||||
a_tvalid_nxt := '0';
|
||||
else
|
||||
a_tvalid_nxt := '1';
|
||||
end if;
|
||||
if cycles mod 3 = 0 then
|
||||
b_tvalid_nxt := '0';
|
||||
else
|
||||
b_tvalid_nxt := '1';
|
||||
end if;
|
||||
when others =>
|
||||
-- Test will stop imminently - do nothing
|
||||
null;
|
||||
end case;
|
||||
|
||||
-- Drive handshake signals with local variable values
|
||||
s_axis_a_tvalid <= a_tvalid_nxt;
|
||||
s_axis_b_tvalid <= b_tvalid_nxt;
|
||||
|
||||
-- Drive AXI slave channel A payload
|
||||
-- Drive '0's on payload signals when not valid
|
||||
if a_tvalid_nxt /= '1' then
|
||||
s_axis_a_tdata <= (others => '0');
|
||||
else
|
||||
-- TDATA: Real and imaginary components are each 18 bits wide and byte-aligned at their LSBs
|
||||
s_axis_a_tdata(17 downto 0) <= IP_A_DATA(ip_a_index).re;
|
||||
s_axis_a_tdata(23 downto 18) <= (others => IP_A_DATA(ip_a_index).re(17)); -- sign-extend;
|
||||
s_axis_a_tdata(41 downto 24) <= IP_A_DATA(ip_a_index).im;
|
||||
s_axis_a_tdata(47 downto 42) <= (others => IP_A_DATA(ip_a_index).im(17)); -- sign-extend;
|
||||
end if;
|
||||
|
||||
-- Drive AXI slave channel B payload
|
||||
-- Drive '0's on payload signals when not valid
|
||||
if b_tvalid_nxt /= '1' then
|
||||
s_axis_b_tdata <= (others => '0');
|
||||
else
|
||||
-- TDATA: Real and imaginary components are each 8 bits wide and byte-aligned at their LSBs
|
||||
s_axis_b_tdata(7 downto 0) <= IP_B_DATA(ip_b_index).re;
|
||||
s_axis_b_tdata(15 downto 8) <= IP_B_DATA(ip_b_index).im;
|
||||
end if;
|
||||
|
||||
-- Increment input data indices
|
||||
if a_tvalid_nxt = '1' then
|
||||
ip_a_index := ip_a_index + 1;
|
||||
if ip_a_index = IP_A_DEPTH then
|
||||
ip_a_index := 0;
|
||||
end if;
|
||||
end if;
|
||||
if b_tvalid_nxt = '1' then
|
||||
ip_b_index := ip_b_index + 1;
|
||||
if ip_b_index = IP_B_DEPTH then
|
||||
ip_b_index := 0;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
end loop;
|
||||
|
||||
end process stimuli;
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Check outputs
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
check_outputs : process
|
||||
variable check_ok : boolean := true;
|
||||
begin
|
||||
|
||||
-- Check outputs T_STROBE time after rising edge of clock
|
||||
wait until rising_edge(aclk);
|
||||
wait for T_STROBE;
|
||||
|
||||
-- Do not check the output payload values, as this requires the behavioral model
|
||||
-- which would make this demonstration testbench unwieldy.
|
||||
-- Instead, check the protocol of the DOUT channel:
|
||||
-- check that the payload is valid (not X) when TVALID is high
|
||||
|
||||
if m_axis_dout_tvalid = '1' then
|
||||
if is_x(m_axis_dout_tdata) then
|
||||
report "ERROR: m_axis_dout_tdata is invalid when m_axis_dout_tvalid is high" severity error;
|
||||
check_ok := false;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
|
||||
assert check_ok
|
||||
report "ERROR: terminating test with failures." severity failure;
|
||||
|
||||
end process check_outputs;
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Assign TDATA fields to aliases, for easy simulator waveform viewing
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
s_axis_a_tdata_real <= s_axis_a_tdata(17 downto 0);
|
||||
s_axis_a_tdata_imag <= s_axis_a_tdata(41 downto 24);
|
||||
s_axis_b_tdata_real <= s_axis_b_tdata(7 downto 0);
|
||||
s_axis_b_tdata_imag <= s_axis_b_tdata(15 downto 8);
|
||||
m_axis_dout_tdata_real <= m_axis_dout_tdata(26 downto 0);
|
||||
m_axis_dout_tdata_imag <= m_axis_dout_tdata(58 downto 32);
|
||||
|
||||
end tb;
|
||||
|
||||
@@ -0,0 +1,202 @@
|
||||
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:cmpy:6.0
|
||||
-- IP Revision: 17
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY cmpy_v6_0_17;
|
||||
USE cmpy_v6_0_17.cmpy_v6_0_17;
|
||||
|
||||
ENTITY cmpy_18x8 IS
|
||||
PORT (
|
||||
aclk : IN STD_LOGIC;
|
||||
s_axis_a_tvalid : IN STD_LOGIC;
|
||||
s_axis_a_tdata : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
|
||||
s_axis_b_tvalid : IN STD_LOGIC;
|
||||
s_axis_b_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
m_axis_dout_tvalid : OUT STD_LOGIC;
|
||||
m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
|
||||
);
|
||||
END cmpy_18x8;
|
||||
|
||||
ARCHITECTURE cmpy_18x8_arch OF cmpy_18x8 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF cmpy_18x8_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT cmpy_v6_0_17 IS
|
||||
GENERIC (
|
||||
C_VERBOSITY : INTEGER;
|
||||
C_XDEVICEFAMILY : STRING;
|
||||
C_XDEVICE : STRING;
|
||||
C_A_WIDTH : INTEGER;
|
||||
C_B_WIDTH : INTEGER;
|
||||
C_OUT_WIDTH : INTEGER;
|
||||
C_LATENCY : INTEGER;
|
||||
C_MULT_TYPE : INTEGER;
|
||||
C_OPTIMIZE_GOAL : INTEGER;
|
||||
HAS_NEGATE : INTEGER;
|
||||
SINGLE_OUTPUT : INTEGER;
|
||||
ROUND : INTEGER;
|
||||
USE_DSP_CASCADES : INTEGER;
|
||||
C_THROTTLE_SCHEME : INTEGER;
|
||||
C_HAS_ACLKEN : INTEGER;
|
||||
C_HAS_ARESETN : INTEGER;
|
||||
C_HAS_S_AXIS_A_TUSER : INTEGER;
|
||||
C_HAS_S_AXIS_A_TLAST : INTEGER;
|
||||
C_HAS_S_AXIS_B_TUSER : INTEGER;
|
||||
C_HAS_S_AXIS_B_TLAST : INTEGER;
|
||||
C_HAS_S_AXIS_CTRL_TUSER : INTEGER;
|
||||
C_HAS_S_AXIS_CTRL_TLAST : INTEGER;
|
||||
C_TLAST_RESOLUTION : INTEGER;
|
||||
C_S_AXIS_A_TDATA_WIDTH : INTEGER;
|
||||
C_S_AXIS_A_TUSER_WIDTH : INTEGER;
|
||||
C_S_AXIS_B_TDATA_WIDTH : INTEGER;
|
||||
C_S_AXIS_B_TUSER_WIDTH : INTEGER;
|
||||
C_S_AXIS_CTRL_TDATA_WIDTH : INTEGER;
|
||||
C_S_AXIS_CTRL_TUSER_WIDTH : INTEGER;
|
||||
C_M_AXIS_DOUT_TDATA_WIDTH : INTEGER;
|
||||
C_M_AXIS_DOUT_TUSER_WIDTH : INTEGER
|
||||
);
|
||||
PORT (
|
||||
aclk : IN STD_LOGIC;
|
||||
aclken : IN STD_LOGIC;
|
||||
aresetn : IN STD_LOGIC;
|
||||
s_axis_a_tvalid : IN STD_LOGIC;
|
||||
s_axis_a_tready : OUT STD_LOGIC;
|
||||
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axis_a_tlast : IN STD_LOGIC;
|
||||
s_axis_a_tdata : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
|
||||
s_axis_b_tvalid : IN STD_LOGIC;
|
||||
s_axis_b_tready : OUT STD_LOGIC;
|
||||
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axis_b_tlast : IN STD_LOGIC;
|
||||
s_axis_b_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
s_axis_ctrl_tvalid : IN STD_LOGIC;
|
||||
s_axis_ctrl_tready : OUT STD_LOGIC;
|
||||
s_axis_ctrl_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axis_ctrl_tlast : IN STD_LOGIC;
|
||||
s_axis_ctrl_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axis_dout_tvalid : OUT STD_LOGIC;
|
||||
m_axis_dout_tready : IN STD_LOGIC;
|
||||
m_axis_dout_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
m_axis_dout_tlast : OUT STD_LOGIC;
|
||||
m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT cmpy_v6_0_17;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axis_dout_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DOUT TDATA";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axis_dout_tvalid: SIGNAL IS "XIL_INTERFACENAME M_AXIS_DOUT, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axis_dout_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DOUT TVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_b_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_B, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_a_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_A, TDATA_NUM_BYTES 6, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF aclk: SIGNAL IS "XIL_INTERFACENAME aclk_intf, ASSOCIATED_BUSIF S_AXIS_CTRL:S_AXIS_B:S_AXIS_A:M_AXIS_DOUT, ASSOCIATED_RESET aresetn, ASSOCIATED_CLKEN aclken, FREQ_HZ 10000000, PHASE 0.000, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
|
||||
BEGIN
|
||||
U0 : cmpy_v6_0_17
|
||||
GENERIC MAP (
|
||||
C_VERBOSITY => 0,
|
||||
C_XDEVICEFAMILY => "zynq",
|
||||
C_XDEVICE => "xc7z100",
|
||||
C_A_WIDTH => 18,
|
||||
C_B_WIDTH => 8,
|
||||
C_OUT_WIDTH => 27,
|
||||
C_LATENCY => 4,
|
||||
C_MULT_TYPE => 0,
|
||||
C_OPTIMIZE_GOAL => 0,
|
||||
HAS_NEGATE => 0,
|
||||
SINGLE_OUTPUT => 0,
|
||||
ROUND => 0,
|
||||
USE_DSP_CASCADES => 1,
|
||||
C_THROTTLE_SCHEME => 3,
|
||||
C_HAS_ACLKEN => 0,
|
||||
C_HAS_ARESETN => 0,
|
||||
C_HAS_S_AXIS_A_TUSER => 0,
|
||||
C_HAS_S_AXIS_A_TLAST => 0,
|
||||
C_HAS_S_AXIS_B_TUSER => 0,
|
||||
C_HAS_S_AXIS_B_TLAST => 0,
|
||||
C_HAS_S_AXIS_CTRL_TUSER => 0,
|
||||
C_HAS_S_AXIS_CTRL_TLAST => 0,
|
||||
C_TLAST_RESOLUTION => 0,
|
||||
C_S_AXIS_A_TDATA_WIDTH => 48,
|
||||
C_S_AXIS_A_TUSER_WIDTH => 1,
|
||||
C_S_AXIS_B_TDATA_WIDTH => 16,
|
||||
C_S_AXIS_B_TUSER_WIDTH => 1,
|
||||
C_S_AXIS_CTRL_TDATA_WIDTH => 8,
|
||||
C_S_AXIS_CTRL_TUSER_WIDTH => 1,
|
||||
C_M_AXIS_DOUT_TDATA_WIDTH => 64,
|
||||
C_M_AXIS_DOUT_TUSER_WIDTH => 1
|
||||
)
|
||||
PORT MAP (
|
||||
aclk => aclk,
|
||||
aclken => '1',
|
||||
aresetn => '1',
|
||||
s_axis_a_tvalid => s_axis_a_tvalid,
|
||||
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
s_axis_a_tlast => '0',
|
||||
s_axis_a_tdata => s_axis_a_tdata,
|
||||
s_axis_b_tvalid => s_axis_b_tvalid,
|
||||
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
s_axis_b_tlast => '0',
|
||||
s_axis_b_tdata => s_axis_b_tdata,
|
||||
s_axis_ctrl_tvalid => '0',
|
||||
s_axis_ctrl_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
s_axis_ctrl_tlast => '0',
|
||||
s_axis_ctrl_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
|
||||
m_axis_dout_tvalid => m_axis_dout_tvalid,
|
||||
m_axis_dout_tready => '0',
|
||||
m_axis_dout_tdata => m_axis_dout_tdata
|
||||
);
|
||||
END cmpy_18x8_arch;
|
||||
@@ -0,0 +1,69 @@
|
||||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
// IP VLNV: xilinx.com:ip:dds_compiler:6.0
|
||||
// IP Revision: 18
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
dds_32b_8b your_instance_name (
|
||||
.aclk(aclk), // input wire aclk
|
||||
.s_axis_config_tvalid(s_axis_config_tvalid), // input wire s_axis_config_tvalid
|
||||
.s_axis_config_tdata(s_axis_config_tdata), // input wire [31 : 0] s_axis_config_tdata
|
||||
.m_axis_data_tvalid(m_axis_data_tvalid), // output wire m_axis_data_tvalid
|
||||
.m_axis_data_tdata(m_axis_data_tdata) // output wire [15 : 0] m_axis_data_tdata
|
||||
);
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
// You must compile the wrapper file dds_32b_8b.v when simulating
|
||||
// the core, dds_32b_8b. When compiling the wrapper file, be sure to
|
||||
// reference the Verilog simulation library.
|
||||
|
||||
@@ -0,0 +1,83 @@
|
||||
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:dds_compiler:6.0
|
||||
-- IP Revision: 18
|
||||
|
||||
-- The following code must appear in the VHDL architecture header.
|
||||
|
||||
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
|
||||
COMPONENT dds_32b_8b
|
||||
PORT (
|
||||
aclk : IN STD_LOGIC;
|
||||
s_axis_config_tvalid : IN STD_LOGIC;
|
||||
s_axis_config_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axis_data_tvalid : OUT STD_LOGIC;
|
||||
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
||||
|
||||
-- The following code must appear in the VHDL architecture
|
||||
-- body. Substitute your own instance name and net names.
|
||||
|
||||
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
|
||||
your_instance_name : dds_32b_8b
|
||||
PORT MAP (
|
||||
aclk => aclk,
|
||||
s_axis_config_tvalid => s_axis_config_tvalid,
|
||||
s_axis_config_tdata => s_axis_config_tdata,
|
||||
m_axis_data_tvalid => m_axis_data_tvalid,
|
||||
m_axis_data_tdata => m_axis_data_tdata
|
||||
);
|
||||
-- INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
-- You must compile the wrapper file dds_32b_8b.vhd when simulating
|
||||
-- the core, dds_32b_8b. When compiling the wrapper file, be sure to
|
||||
-- reference the VHDL simulation library.
|
||||
|
||||
BIN
Binary file not shown.
BIN
Binary file not shown.
@@ -0,0 +1,25 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Thu Apr 13 10:40:35 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/modules/xc7z100ffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_synth_1/dds_32b_8b_stub.v
|
||||
// Design : dds_32b_8b
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z100ffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "dds_compiler_v6_0_18,Vivado 2019.1.3" *)
|
||||
module dds_32b_8b(aclk, s_axis_config_tvalid,
|
||||
s_axis_config_tdata, m_axis_data_tvalid, m_axis_data_tdata)
|
||||
/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_config_tvalid,s_axis_config_tdata[31:0],m_axis_data_tvalid,m_axis_data_tdata[15:0]" */;
|
||||
input aclk;
|
||||
input s_axis_config_tvalid;
|
||||
input [31:0]s_axis_config_tdata;
|
||||
output m_axis_data_tvalid;
|
||||
output [15:0]m_axis_data_tdata;
|
||||
endmodule
|
||||
@@ -0,0 +1,34 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Thu Apr 13 10:40:35 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/modules/xc7z100ffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_synth_1/dds_32b_8b_stub.vhdl
|
||||
-- Design : dds_32b_8b
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z100ffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity dds_32b_8b is
|
||||
Port (
|
||||
aclk : in STD_LOGIC;
|
||||
s_axis_config_tvalid : in STD_LOGIC;
|
||||
s_axis_config_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
m_axis_data_tvalid : out STD_LOGIC;
|
||||
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 )
|
||||
);
|
||||
|
||||
end dds_32b_8b;
|
||||
|
||||
architecture stub of dds_32b_8b is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_config_tvalid,s_axis_config_tdata[31:0],m_axis_data_tvalid,m_axis_data_tdata[15:0]";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "dds_compiler_v6_0_18,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
+235
@@ -0,0 +1,235 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- (c) Copyright 2010 - 2013 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--------------------------------------------------------------------------------
|
||||
-- Description:
|
||||
-- This is an example testbench for the DDS Compiler IP core.
|
||||
-- The testbench has been generated by Vivado to accompany the IP core
|
||||
-- instance you have generated.
|
||||
--
|
||||
-- This testbench is for demonstration purposes only. See note below for
|
||||
-- instructions on how to use it with your core.
|
||||
--
|
||||
-- See the DDS Compiler product guide for further information
|
||||
-- about this core.
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Using this testbench
|
||||
--
|
||||
-- This testbench instantiates your generated DDS Compiler core
|
||||
-- instance named "dds_32b_8b".
|
||||
--
|
||||
-- Use Vivado's Run Simulation flow to run this testbench. See the Vivado
|
||||
-- documentation for details.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
use ieee.math_real.all;
|
||||
|
||||
entity tb_dds_32b_8b is
|
||||
end tb_dds_32b_8b;
|
||||
|
||||
architecture tb of tb_dds_32b_8b is
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Timing constants
|
||||
-----------------------------------------------------------------------
|
||||
constant CLOCK_PERIOD : time := 100 ns;
|
||||
constant T_HOLD : time := 10 ns;
|
||||
constant T_STROBE : time := CLOCK_PERIOD - (1 ns);
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- DUT input signals
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
-- General inputs
|
||||
signal aclk : std_logic := '0'; -- the master clock
|
||||
|
||||
-- Config slave channel signals
|
||||
signal s_axis_config_tvalid : std_logic := '0'; -- payload is valid
|
||||
signal s_axis_config_tdata : std_logic_vector(31 downto 0) := (others => '0'); -- data payload
|
||||
|
||||
-- Data master channel signals
|
||||
signal m_axis_data_tvalid : std_logic := '0'; -- payload is valid
|
||||
signal m_axis_data_tdata : std_logic_vector(15 downto 0) := (others => '0'); -- data payload
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Aliases for AXI channel TDATA and TUSER fields
|
||||
-- These are a convenience for viewing data in a simulator waveform viewer.
|
||||
-- If using ModelSim or Questa, add "-voptargs=+acc=n" to the vsim command
|
||||
-- to prevent the simulator optimizing away these signals.
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
-- Config slave channel alias signals
|
||||
signal s_axis_config_tdata_inc : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
-- Data master channel alias signals
|
||||
signal m_axis_data_tdata_cosine : std_logic_vector(7 downto 0) := (others => '0');
|
||||
signal m_axis_data_tdata_sine : std_logic_vector(7 downto 0) := (others => '0');
|
||||
|
||||
|
||||
signal end_of_simulation : boolean := false;
|
||||
|
||||
begin
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Instantiate the DUT
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
dut : entity work.dds_32b_8b
|
||||
port map (
|
||||
aclk => aclk
|
||||
,s_axis_config_tvalid => s_axis_config_tvalid
|
||||
,s_axis_config_tdata => s_axis_config_tdata
|
||||
,m_axis_data_tvalid => m_axis_data_tvalid
|
||||
,m_axis_data_tdata => m_axis_data_tdata
|
||||
);
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Generate clock
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
clock_gen : process
|
||||
begin
|
||||
aclk <= '0';
|
||||
if (end_of_simulation) then
|
||||
wait;
|
||||
else
|
||||
wait for CLOCK_PERIOD;
|
||||
loop
|
||||
aclk <= '0';
|
||||
wait for CLOCK_PERIOD/2;
|
||||
aclk <= '1';
|
||||
wait for CLOCK_PERIOD/2;
|
||||
end loop;
|
||||
end if;
|
||||
end process clock_gen;
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Generate inputs
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
stimuli : process
|
||||
begin
|
||||
|
||||
-- Drive inputs T_HOLD time after rising edge of clock
|
||||
wait until rising_edge(aclk);
|
||||
wait for T_HOLD;
|
||||
|
||||
-- Program the core with the initial configuration.
|
||||
-- The phase increment value here is derived from the output frequency value set in the CORE Generator GUI.
|
||||
s_axis_config_tvalid <= '1';
|
||||
s_axis_config_tdata <= (others => '0'); -- set unused TDATA bits to zero
|
||||
s_axis_config_tdata(31 downto 0) <= "00000000000000001101101001110100"; -- phase increment
|
||||
wait for CLOCK_PERIOD;
|
||||
s_axis_config_tvalid <= '0';
|
||||
|
||||
-- Run for long enough to produce 5 periods of outputs
|
||||
wait for CLOCK_PERIOD * 384001;
|
||||
|
||||
-- Configure the core with a different configuration:
|
||||
-- set phase increment to half of its current value
|
||||
s_axis_config_tvalid <= '1';
|
||||
s_axis_config_tdata <= (others => '0'); -- set unused TDATA bits to zero
|
||||
s_axis_config_tdata(31 downto 0) <= "00000000000000000110110100111010"; -- current phase increment / 2
|
||||
wait for CLOCK_PERIOD;
|
||||
s_axis_config_tvalid <= '0';
|
||||
|
||||
-- Run for long enough to produce 5 periods of outputs
|
||||
wait for CLOCK_PERIOD * 768002;
|
||||
|
||||
-- End of test
|
||||
end_of_simulation <= true;
|
||||
report "Not a real failure. Simulation finished successfully. Test completed successfully" severity failure;
|
||||
wait;
|
||||
|
||||
end process stimuli;
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Check outputs
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
check_outputs : process
|
||||
variable check_ok : boolean := true;
|
||||
begin
|
||||
|
||||
-- Check outputs T_STROBE time after rising edge of clock
|
||||
wait until rising_edge(aclk);
|
||||
wait for T_STROBE;
|
||||
|
||||
-- Do not check the output payload values, as this requires the behavioral model
|
||||
-- which would make this demonstration testbench unwieldy.
|
||||
-- Instead, check the protocol of the data master channel:
|
||||
-- check that the payload is valid (not X) when TVALID is high
|
||||
|
||||
if m_axis_data_tvalid = '1' then
|
||||
if is_x(m_axis_data_tdata) then
|
||||
report "ERROR: m_axis_data_tdata is invalid when m_axis_data_tvalid is high" severity error;
|
||||
check_ok := false;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
|
||||
assert check_ok
|
||||
report "ERROR: terminating test with failures." severity failure;
|
||||
|
||||
end process check_outputs;
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Assign TDATA fields to aliases, for easy simulator waveform viewing
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
-- Config slave channel alias signals
|
||||
s_axis_config_tdata_inc <= s_axis_config_tdata(31 downto 0);
|
||||
|
||||
-- Data master channel alias signals: update these only when they are valid
|
||||
m_axis_data_tdata_cosine <= m_axis_data_tdata(7 downto 0) when m_axis_data_tvalid = '1';
|
||||
m_axis_data_tdata_sine <= m_axis_data_tdata(15 downto 8) when m_axis_data_tvalid = '1';
|
||||
|
||||
end tb;
|
||||
|
||||
@@ -0,0 +1,232 @@
|
||||
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:dds_compiler:6.0
|
||||
-- IP Revision: 18
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY dds_compiler_v6_0_18;
|
||||
USE dds_compiler_v6_0_18.dds_compiler_v6_0_18;
|
||||
|
||||
ENTITY dds_32b_8b IS
|
||||
PORT (
|
||||
aclk : IN STD_LOGIC;
|
||||
s_axis_config_tvalid : IN STD_LOGIC;
|
||||
s_axis_config_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axis_data_tvalid : OUT STD_LOGIC;
|
||||
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
|
||||
);
|
||||
END dds_32b_8b;
|
||||
|
||||
ARCHITECTURE dds_32b_8b_arch OF dds_32b_8b IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF dds_32b_8b_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT dds_compiler_v6_0_18 IS
|
||||
GENERIC (
|
||||
C_XDEVICEFAMILY : STRING;
|
||||
C_MODE_OF_OPERATION : INTEGER;
|
||||
C_MODULUS : INTEGER;
|
||||
C_ACCUMULATOR_WIDTH : INTEGER;
|
||||
C_CHANNELS : INTEGER;
|
||||
C_HAS_PHASE_OUT : INTEGER;
|
||||
C_HAS_PHASEGEN : INTEGER;
|
||||
C_HAS_SINCOS : INTEGER;
|
||||
C_LATENCY : INTEGER;
|
||||
C_MEM_TYPE : INTEGER;
|
||||
C_NEGATIVE_COSINE : INTEGER;
|
||||
C_NEGATIVE_SINE : INTEGER;
|
||||
C_NOISE_SHAPING : INTEGER;
|
||||
C_OUTPUTS_REQUIRED : INTEGER;
|
||||
C_OUTPUT_FORM : INTEGER;
|
||||
C_OUTPUT_WIDTH : INTEGER;
|
||||
C_PHASE_ANGLE_WIDTH : INTEGER;
|
||||
C_PHASE_INCREMENT : INTEGER;
|
||||
C_PHASE_INCREMENT_VALUE : STRING;
|
||||
C_RESYNC : INTEGER;
|
||||
C_PHASE_OFFSET : INTEGER;
|
||||
C_PHASE_OFFSET_VALUE : STRING;
|
||||
C_OPTIMISE_GOAL : INTEGER;
|
||||
C_USE_DSP48 : INTEGER;
|
||||
C_POR_MODE : INTEGER;
|
||||
C_AMPLITUDE : INTEGER;
|
||||
C_HAS_ACLKEN : INTEGER;
|
||||
C_HAS_ARESETN : INTEGER;
|
||||
C_HAS_TLAST : INTEGER;
|
||||
C_HAS_TREADY : INTEGER;
|
||||
C_HAS_S_PHASE : INTEGER;
|
||||
C_S_PHASE_TDATA_WIDTH : INTEGER;
|
||||
C_S_PHASE_HAS_TUSER : INTEGER;
|
||||
C_S_PHASE_TUSER_WIDTH : INTEGER;
|
||||
C_HAS_S_CONFIG : INTEGER;
|
||||
C_S_CONFIG_SYNC_MODE : INTEGER;
|
||||
C_S_CONFIG_TDATA_WIDTH : INTEGER;
|
||||
C_HAS_M_DATA : INTEGER;
|
||||
C_M_DATA_TDATA_WIDTH : INTEGER;
|
||||
C_M_DATA_HAS_TUSER : INTEGER;
|
||||
C_M_DATA_TUSER_WIDTH : INTEGER;
|
||||
C_HAS_M_PHASE : INTEGER;
|
||||
C_M_PHASE_TDATA_WIDTH : INTEGER;
|
||||
C_M_PHASE_HAS_TUSER : INTEGER;
|
||||
C_M_PHASE_TUSER_WIDTH : INTEGER;
|
||||
C_DEBUG_INTERFACE : INTEGER;
|
||||
C_CHAN_WIDTH : INTEGER
|
||||
);
|
||||
PORT (
|
||||
aclk : IN STD_LOGIC;
|
||||
aclken : IN STD_LOGIC;
|
||||
aresetn : IN STD_LOGIC;
|
||||
s_axis_phase_tvalid : IN STD_LOGIC;
|
||||
s_axis_phase_tready : OUT STD_LOGIC;
|
||||
s_axis_phase_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axis_phase_tlast : IN STD_LOGIC;
|
||||
s_axis_phase_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axis_config_tvalid : IN STD_LOGIC;
|
||||
s_axis_config_tready : OUT STD_LOGIC;
|
||||
s_axis_config_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axis_config_tlast : IN STD_LOGIC;
|
||||
m_axis_data_tvalid : OUT STD_LOGIC;
|
||||
m_axis_data_tready : IN STD_LOGIC;
|
||||
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
m_axis_data_tlast : OUT STD_LOGIC;
|
||||
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
m_axis_phase_tvalid : OUT STD_LOGIC;
|
||||
m_axis_phase_tready : IN STD_LOGIC;
|
||||
m_axis_phase_tdata : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
m_axis_phase_tlast : OUT STD_LOGIC;
|
||||
m_axis_phase_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
event_pinc_invalid : OUT STD_LOGIC;
|
||||
event_poff_invalid : OUT STD_LOGIC;
|
||||
event_phase_in_invalid : OUT STD_LOGIC;
|
||||
event_s_phase_tlast_missing : OUT STD_LOGIC;
|
||||
event_s_phase_tlast_unexpected : OUT STD_LOGIC;
|
||||
event_s_phase_chanid_incorrect : OUT STD_LOGIC;
|
||||
event_s_config_tlast_missing : OUT STD_LOGIC;
|
||||
event_s_config_tlast_unexpected : OUT STD_LOGIC
|
||||
);
|
||||
END COMPONENT dds_compiler_v6_0_18;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axis_data_tvalid: SIGNAL IS "XIL_INTERFACENAME M_AXIS_DATA, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_config_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_CONFIG TDATA";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_config_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_CONFIG, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_config_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_CONFIG TVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF aclk: SIGNAL IS "XIL_INTERFACENAME aclk_intf, ASSOCIATED_BUSIF M_AXIS_PHASE:S_AXIS_CONFIG:M_AXIS_DATA:S_AXIS_PHASE, ASSOCIATED_RESET aresetn, ASSOCIATED_CLKEN aclken, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
|
||||
BEGIN
|
||||
U0 : dds_compiler_v6_0_18
|
||||
GENERIC MAP (
|
||||
C_XDEVICEFAMILY => "zynq",
|
||||
C_MODE_OF_OPERATION => 0,
|
||||
C_MODULUS => 9,
|
||||
C_ACCUMULATOR_WIDTH => 32,
|
||||
C_CHANNELS => 1,
|
||||
C_HAS_PHASE_OUT => 0,
|
||||
C_HAS_PHASEGEN => 1,
|
||||
C_HAS_SINCOS => 1,
|
||||
C_LATENCY => 3,
|
||||
C_MEM_TYPE => 1,
|
||||
C_NEGATIVE_COSINE => 0,
|
||||
C_NEGATIVE_SINE => 0,
|
||||
C_NOISE_SHAPING => 0,
|
||||
C_OUTPUTS_REQUIRED => 2,
|
||||
C_OUTPUT_FORM => 0,
|
||||
C_OUTPUT_WIDTH => 8,
|
||||
C_PHASE_ANGLE_WIDTH => 8,
|
||||
C_PHASE_INCREMENT => 1,
|
||||
C_PHASE_INCREMENT_VALUE => "1101101001110100,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0",
|
||||
C_RESYNC => 0,
|
||||
C_PHASE_OFFSET => 0,
|
||||
C_PHASE_OFFSET_VALUE => "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0",
|
||||
C_OPTIMISE_GOAL => 0,
|
||||
C_USE_DSP48 => 0,
|
||||
C_POR_MODE => 0,
|
||||
C_AMPLITUDE => 0,
|
||||
C_HAS_ACLKEN => 0,
|
||||
C_HAS_ARESETN => 0,
|
||||
C_HAS_TLAST => 0,
|
||||
C_HAS_TREADY => 0,
|
||||
C_HAS_S_PHASE => 0,
|
||||
C_S_PHASE_TDATA_WIDTH => 1,
|
||||
C_S_PHASE_HAS_TUSER => 0,
|
||||
C_S_PHASE_TUSER_WIDTH => 1,
|
||||
C_HAS_S_CONFIG => 1,
|
||||
C_S_CONFIG_SYNC_MODE => 0,
|
||||
C_S_CONFIG_TDATA_WIDTH => 32,
|
||||
C_HAS_M_DATA => 1,
|
||||
C_M_DATA_TDATA_WIDTH => 16,
|
||||
C_M_DATA_HAS_TUSER => 0,
|
||||
C_M_DATA_TUSER_WIDTH => 1,
|
||||
C_HAS_M_PHASE => 0,
|
||||
C_M_PHASE_TDATA_WIDTH => 1,
|
||||
C_M_PHASE_HAS_TUSER => 0,
|
||||
C_M_PHASE_TUSER_WIDTH => 1,
|
||||
C_DEBUG_INTERFACE => 0,
|
||||
C_CHAN_WIDTH => 1
|
||||
)
|
||||
PORT MAP (
|
||||
aclk => aclk,
|
||||
aclken => '1',
|
||||
aresetn => '1',
|
||||
s_axis_phase_tvalid => '0',
|
||||
s_axis_phase_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
s_axis_phase_tlast => '0',
|
||||
s_axis_phase_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
s_axis_config_tvalid => s_axis_config_tvalid,
|
||||
s_axis_config_tdata => s_axis_config_tdata,
|
||||
s_axis_config_tlast => '0',
|
||||
m_axis_data_tvalid => m_axis_data_tvalid,
|
||||
m_axis_data_tready => '0',
|
||||
m_axis_data_tdata => m_axis_data_tdata,
|
||||
m_axis_phase_tready => '0'
|
||||
);
|
||||
END dds_32b_8b_arch;
|
||||
@@ -0,0 +1,67 @@
|
||||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
|
||||
// IP Revision: 3
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
hop_rom your_instance_name (
|
||||
.clka(clka), // input wire clka
|
||||
.addra(addra), // input wire [7 : 0] addra
|
||||
.douta(douta) // output wire [31 : 0] douta
|
||||
);
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
// You must compile the wrapper file hop_rom.v when simulating
|
||||
// the core, hop_rom. When compiling the wrapper file, be sure to
|
||||
// reference the Verilog simulation library.
|
||||
|
||||
@@ -0,0 +1,79 @@
|
||||
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
|
||||
-- IP Revision: 3
|
||||
|
||||
-- The following code must appear in the VHDL architecture header.
|
||||
|
||||
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
|
||||
COMPONENT hop_rom
|
||||
PORT (
|
||||
clka : IN STD_LOGIC;
|
||||
addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
||||
|
||||
-- The following code must appear in the VHDL architecture
|
||||
-- body. Substitute your own instance name and net names.
|
||||
|
||||
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
|
||||
your_instance_name : hop_rom
|
||||
PORT MAP (
|
||||
clka => clka,
|
||||
addra => addra,
|
||||
douta => douta
|
||||
);
|
||||
-- INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
-- You must compile the wrapper file hop_rom.vhd when simulating
|
||||
-- the core, hop_rom. When compiling the wrapper file, be sure to
|
||||
-- reference the VHDL simulation library.
|
||||
|
||||
Binary file not shown.
BIN
Binary file not shown.
@@ -0,0 +1,22 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Thu Mar 30 15:31:15 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/modules/xc7z100ffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/hop_rom_synth_1/hop_rom_stub.v
|
||||
// Design : hop_rom
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z100ffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "blk_mem_gen_v8_4_3,Vivado 2019.1.3" *)
|
||||
module hop_rom(clka, addra, douta)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clka,addra[7:0],douta[31:0]" */;
|
||||
input clka;
|
||||
input [7:0]addra;
|
||||
output [31:0]douta;
|
||||
endmodule
|
||||
@@ -0,0 +1,32 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Thu Mar 30 15:31:15 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/modules/xc7z100ffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/hop_rom_synth_1/hop_rom_stub.vhdl
|
||||
-- Design : hop_rom
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z100ffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity hop_rom is
|
||||
Port (
|
||||
clka : in STD_LOGIC;
|
||||
addra : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
douta : out STD_LOGIC_VECTOR ( 31 downto 0 )
|
||||
);
|
||||
|
||||
end hop_rom;
|
||||
|
||||
architecture stub of hop_rom is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clka,addra[7:0],douta[31:0]";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_3,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
@@ -0,0 +1,211 @@
|
||||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
|
||||
// IP Revision: 3
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module hop_rom (
|
||||
clka,
|
||||
addra,
|
||||
douta
|
||||
);
|
||||
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
|
||||
input wire clka;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
|
||||
input wire [7 : 0] addra;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
|
||||
output wire [31 : 0] douta;
|
||||
|
||||
blk_mem_gen_v8_4_3 #(
|
||||
.C_FAMILY("zynq"),
|
||||
.C_XDEVICEFAMILY("zynq"),
|
||||
.C_ELABORATION_DIR("./"),
|
||||
.C_INTERFACE_TYPE(0),
|
||||
.C_AXI_TYPE(1),
|
||||
.C_AXI_SLAVE_TYPE(0),
|
||||
.C_USE_BRAM_BLOCK(0),
|
||||
.C_ENABLE_32BIT_ADDRESS(0),
|
||||
.C_CTRL_ECC_ALGO("NONE"),
|
||||
.C_HAS_AXI_ID(0),
|
||||
.C_AXI_ID_WIDTH(4),
|
||||
.C_MEM_TYPE(3),
|
||||
.C_BYTE_SIZE(9),
|
||||
.C_ALGORITHM(1),
|
||||
.C_PRIM_TYPE(1),
|
||||
.C_LOAD_INIT_FILE(1),
|
||||
.C_INIT_FILE_NAME("hop_rom.mif"),
|
||||
.C_INIT_FILE("hop_rom.mem"),
|
||||
.C_USE_DEFAULT_DATA(0),
|
||||
.C_DEFAULT_DATA("0"),
|
||||
.C_HAS_RSTA(0),
|
||||
.C_RST_PRIORITY_A("CE"),
|
||||
.C_RSTRAM_A(0),
|
||||
.C_INITA_VAL("0"),
|
||||
.C_HAS_ENA(0),
|
||||
.C_HAS_REGCEA(0),
|
||||
.C_USE_BYTE_WEA(0),
|
||||
.C_WEA_WIDTH(1),
|
||||
.C_WRITE_MODE_A("WRITE_FIRST"),
|
||||
.C_WRITE_WIDTH_A(32),
|
||||
.C_READ_WIDTH_A(32),
|
||||
.C_WRITE_DEPTH_A(256),
|
||||
.C_READ_DEPTH_A(256),
|
||||
.C_ADDRA_WIDTH(8),
|
||||
.C_HAS_RSTB(0),
|
||||
.C_RST_PRIORITY_B("CE"),
|
||||
.C_RSTRAM_B(0),
|
||||
.C_INITB_VAL("0"),
|
||||
.C_HAS_ENB(0),
|
||||
.C_HAS_REGCEB(0),
|
||||
.C_USE_BYTE_WEB(0),
|
||||
.C_WEB_WIDTH(1),
|
||||
.C_WRITE_MODE_B("WRITE_FIRST"),
|
||||
.C_WRITE_WIDTH_B(32),
|
||||
.C_READ_WIDTH_B(32),
|
||||
.C_WRITE_DEPTH_B(256),
|
||||
.C_READ_DEPTH_B(256),
|
||||
.C_ADDRB_WIDTH(8),
|
||||
.C_HAS_MEM_OUTPUT_REGS_A(1),
|
||||
.C_HAS_MEM_OUTPUT_REGS_B(0),
|
||||
.C_HAS_MUX_OUTPUT_REGS_A(1),
|
||||
.C_HAS_MUX_OUTPUT_REGS_B(0),
|
||||
.C_MUX_PIPELINE_STAGES(0),
|
||||
.C_HAS_SOFTECC_INPUT_REGS_A(0),
|
||||
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
|
||||
.C_USE_SOFTECC(0),
|
||||
.C_USE_ECC(0),
|
||||
.C_EN_ECC_PIPE(0),
|
||||
.C_READ_LATENCY_A(1),
|
||||
.C_READ_LATENCY_B(1),
|
||||
.C_HAS_INJECTERR(0),
|
||||
.C_SIM_COLLISION_CHECK("ALL"),
|
||||
.C_COMMON_CLK(0),
|
||||
.C_DISABLE_WARN_BHV_COLL(0),
|
||||
.C_EN_SLEEP_PIN(0),
|
||||
.C_USE_URAM(0),
|
||||
.C_EN_RDADDRA_CHG(0),
|
||||
.C_EN_RDADDRB_CHG(0),
|
||||
.C_EN_DEEPSLEEP_PIN(0),
|
||||
.C_EN_SHUTDOWN_PIN(0),
|
||||
.C_EN_SAFETY_CKT(0),
|
||||
.C_DISABLE_WARN_BHV_RANGE(0),
|
||||
.C_COUNT_36K_BRAM("0"),
|
||||
.C_COUNT_18K_BRAM("1"),
|
||||
.C_EST_POWER_SUMMARY("Estimated Power for IP : 3.375199 mW")
|
||||
) inst (
|
||||
.clka(clka),
|
||||
.rsta(1'D0),
|
||||
.ena(1'D0),
|
||||
.regcea(1'D0),
|
||||
.wea(1'B0),
|
||||
.addra(addra),
|
||||
.dina(32'B0),
|
||||
.douta(douta),
|
||||
.clkb(1'D0),
|
||||
.rstb(1'D0),
|
||||
.enb(1'D0),
|
||||
.regceb(1'D0),
|
||||
.web(1'B0),
|
||||
.addrb(8'B0),
|
||||
.dinb(32'B0),
|
||||
.doutb(),
|
||||
.injectsbiterr(1'D0),
|
||||
.injectdbiterr(1'D0),
|
||||
.eccpipece(1'D0),
|
||||
.sbiterr(),
|
||||
.dbiterr(),
|
||||
.rdaddrecc(),
|
||||
.sleep(1'D0),
|
||||
.deepsleep(1'D0),
|
||||
.shutdown(1'D0),
|
||||
.rsta_busy(),
|
||||
.rstb_busy(),
|
||||
.s_aclk(1'H0),
|
||||
.s_aresetn(1'D0),
|
||||
.s_axi_awid(4'B0),
|
||||
.s_axi_awaddr(32'B0),
|
||||
.s_axi_awlen(8'B0),
|
||||
.s_axi_awsize(3'B0),
|
||||
.s_axi_awburst(2'B0),
|
||||
.s_axi_awvalid(1'D0),
|
||||
.s_axi_awready(),
|
||||
.s_axi_wdata(32'B0),
|
||||
.s_axi_wstrb(1'B0),
|
||||
.s_axi_wlast(1'D0),
|
||||
.s_axi_wvalid(1'D0),
|
||||
.s_axi_wready(),
|
||||
.s_axi_bid(),
|
||||
.s_axi_bresp(),
|
||||
.s_axi_bvalid(),
|
||||
.s_axi_bready(1'D0),
|
||||
.s_axi_arid(4'B0),
|
||||
.s_axi_araddr(32'B0),
|
||||
.s_axi_arlen(8'B0),
|
||||
.s_axi_arsize(3'B0),
|
||||
.s_axi_arburst(2'B0),
|
||||
.s_axi_arvalid(1'D0),
|
||||
.s_axi_arready(),
|
||||
.s_axi_rid(),
|
||||
.s_axi_rdata(),
|
||||
.s_axi_rresp(),
|
||||
.s_axi_rlast(),
|
||||
.s_axi_rvalid(),
|
||||
.s_axi_rready(1'D0),
|
||||
.s_axi_injectsbiterr(1'D0),
|
||||
.s_axi_injectdbiterr(1'D0),
|
||||
.s_axi_sbiterr(),
|
||||
.s_axi_dbiterr(),
|
||||
.s_axi_rdaddrecc()
|
||||
);
|
||||
endmodule
|
||||
+261
@@ -0,0 +1,261 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- (c) Copyright 2011 - 2013 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--------------------------------------------------------------------------------
|
||||
-- Description:
|
||||
-- This is an example testbench for the FIR Compiler IP core.
|
||||
-- The testbench has been generated by Vivado to accompany the IP core
|
||||
-- instance you have generated.
|
||||
--
|
||||
-- This testbench is for demonstration purposes only. See note below for
|
||||
-- instructions on how to use it with your core.
|
||||
--
|
||||
-- See the FIR Compiler product guide for further information
|
||||
-- about this core.
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Using this testbench
|
||||
--
|
||||
-- This testbench instantiates your generated FIR Compiler core
|
||||
-- instance named "hrc_64_12_025".
|
||||
--
|
||||
-- Use Vivado's Run Simulation flow to run this testbench. See the Vivado
|
||||
-- documentation for details.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity tb_hrc_64_12_025 is
|
||||
end tb_hrc_64_12_025;
|
||||
|
||||
architecture tb of tb_hrc_64_12_025 is
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Timing constants
|
||||
-----------------------------------------------------------------------
|
||||
constant CLOCK_PERIOD : time := 100 ns;
|
||||
constant T_HOLD : time := 10 ns;
|
||||
constant T_STROBE : time := CLOCK_PERIOD - (1 ns);
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- DUT signals
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
-- General signals
|
||||
signal aclk : std_logic := '0'; -- the master clock
|
||||
|
||||
-- Data slave channel signals
|
||||
signal s_axis_data_tvalid : std_logic := '0'; -- payload is valid
|
||||
signal s_axis_data_tready : std_logic := '1'; -- slave is ready
|
||||
signal s_axis_data_tdata : std_logic_vector(7 downto 0) := (others => '0'); -- data payload
|
||||
|
||||
-- Data master channel signals
|
||||
signal m_axis_data_tvalid : std_logic := '0'; -- payload is valid
|
||||
signal m_axis_data_tdata : std_logic_vector(23 downto 0) := (others => '0'); -- data payload
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Aliases for AXI channel TDATA and TUSER fields
|
||||
-- These are a convenience for viewing data in a simulator waveform viewer.
|
||||
-- If using ModelSim or Questa, add "-voptargs=+acc=n" to the vsim command
|
||||
-- to prevent the simulator optimizing away these signals.
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
-- Data slave channel alias signals
|
||||
signal s_axis_data_tdata_data : std_logic_vector(1 downto 0) := (others => '0');
|
||||
|
||||
-- Data master channel alias signals
|
||||
signal m_axis_data_tdata_data : std_logic_vector(17 downto 0) := (others => '0');
|
||||
|
||||
|
||||
begin
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Instantiate the DUT
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
dut : entity work.hrc_64_12_025
|
||||
port map (
|
||||
aclk => aclk,
|
||||
s_axis_data_tvalid => s_axis_data_tvalid,
|
||||
s_axis_data_tready => s_axis_data_tready,
|
||||
s_axis_data_tdata => s_axis_data_tdata,
|
||||
m_axis_data_tvalid => m_axis_data_tvalid,
|
||||
m_axis_data_tdata => m_axis_data_tdata
|
||||
);
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Generate clock
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
clock_gen : process
|
||||
begin
|
||||
aclk <= '0';
|
||||
wait for CLOCK_PERIOD;
|
||||
loop
|
||||
aclk <= '0';
|
||||
wait for CLOCK_PERIOD/2;
|
||||
aclk <= '1';
|
||||
wait for CLOCK_PERIOD/2;
|
||||
end loop;
|
||||
end process clock_gen;
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Generate inputs
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
stimuli : process
|
||||
|
||||
-- Procedure to drive a number of input samples with specific data
|
||||
-- data is the data value to drive on the tdata signal
|
||||
-- samples is the number of zero-data input samples to drive
|
||||
procedure drive_data ( data : std_logic_vector(7 downto 0);
|
||||
samples : natural := 1 ) is
|
||||
variable ip_count : integer := 0;
|
||||
begin
|
||||
ip_count := 0;
|
||||
loop
|
||||
s_axis_data_tvalid <= '1';
|
||||
s_axis_data_tdata <= data;
|
||||
loop
|
||||
wait until rising_edge(aclk);
|
||||
exit when s_axis_data_tready = '1';
|
||||
end loop;
|
||||
ip_count := ip_count + 1;
|
||||
wait for T_HOLD;
|
||||
-- Input rate is 1 input each 64 clock cycles: drive valid inputs at this rate
|
||||
s_axis_data_tvalid <= '0';
|
||||
wait for CLOCK_PERIOD * 63;
|
||||
exit when ip_count >= samples;
|
||||
end loop;
|
||||
end procedure drive_data;
|
||||
|
||||
-- Procedure to drive a number of zero-data input samples
|
||||
-- samples is the number of zero-data input samples to drive
|
||||
procedure drive_zeros ( samples : natural := 1 ) is
|
||||
begin
|
||||
drive_data((others => '0'), samples);
|
||||
end procedure drive_zeros;
|
||||
|
||||
-- Procedure to drive an impulse and let the impulse response emerge on the data master channel
|
||||
-- samples is the number of input samples to drive; default is enough for impulse response output to emerge
|
||||
procedure drive_impulse ( samples : natural := 901 ) is
|
||||
variable impulse : std_logic_vector(7 downto 0);
|
||||
begin
|
||||
impulse := (others => '0'); -- initialize unused bits to zero
|
||||
impulse(1 downto 0) := "01";
|
||||
drive_data(impulse);
|
||||
if samples > 1 then
|
||||
drive_zeros(samples-1);
|
||||
end if;
|
||||
end procedure drive_impulse;
|
||||
|
||||
begin
|
||||
|
||||
-- Drive inputs T_HOLD time after rising edge of clock
|
||||
wait until rising_edge(aclk);
|
||||
wait for T_HOLD;
|
||||
|
||||
-- Drive a single impulse and let the impulse response emerge
|
||||
drive_impulse;
|
||||
|
||||
-- Drive another impulse, during which demonstrate use and effect of AXI handshaking signals
|
||||
drive_impulse(2); -- start of impulse; data is now zero
|
||||
s_axis_data_tvalid <= '0';
|
||||
wait for CLOCK_PERIOD * 320; -- provide no data for 5 input samples worth
|
||||
drive_zeros(2); -- 2 normal input samples
|
||||
s_axis_data_tvalid <= '1';
|
||||
wait for CLOCK_PERIOD * 320; -- provide data as fast as the core can accept it for 5 input samples worth
|
||||
drive_zeros(892); -- back to normal operation
|
||||
|
||||
-- End of test
|
||||
report "Not a real failure. Simulation finished successfully. Test completed successfully" severity failure;
|
||||
wait;
|
||||
|
||||
end process stimuli;
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Check outputs
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
check_outputs : process
|
||||
variable check_ok : boolean := true;
|
||||
begin
|
||||
|
||||
-- Check outputs T_STROBE time after rising edge of clock
|
||||
wait until rising_edge(aclk);
|
||||
wait for T_STROBE;
|
||||
|
||||
-- Do not check the output payload values, as this requires the behavioral model
|
||||
-- which would make this demonstration testbench unwieldy.
|
||||
-- Instead, check the protocol of the master DATA channel:
|
||||
-- check that the payload is valid (not X) when TVALID is high
|
||||
|
||||
if m_axis_data_tvalid = '1' then
|
||||
if is_x(m_axis_data_tdata) then
|
||||
report "ERROR: m_axis_data_tdata is invalid when m_axis_data_tvalid is high" severity error;
|
||||
check_ok := false;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
|
||||
assert check_ok
|
||||
report "ERROR: terminating test with failures." severity failure;
|
||||
|
||||
end process check_outputs;
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Assign TDATA / TUSER fields to aliases, for easy simulator waveform viewing
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
-- Data slave channel alias signals
|
||||
s_axis_data_tdata_data <= s_axis_data_tdata(1 downto 0);
|
||||
|
||||
-- Data master channel alias signals: update these only when they are valid
|
||||
m_axis_data_tdata_data <= m_axis_data_tdata(17 downto 0) when m_axis_data_tvalid = '1';
|
||||
|
||||
end tb;
|
||||
@@ -0,0 +1,70 @@
|
||||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
// IP VLNV: xilinx.com:ip:fir_compiler:7.2
|
||||
// IP Revision: 12
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
hrc_64_12_025 your_instance_name (
|
||||
.aclk(aclk), // input wire aclk
|
||||
.s_axis_data_tvalid(s_axis_data_tvalid), // input wire s_axis_data_tvalid
|
||||
.s_axis_data_tready(s_axis_data_tready), // output wire s_axis_data_tready
|
||||
.s_axis_data_tdata(s_axis_data_tdata), // input wire [7 : 0] s_axis_data_tdata
|
||||
.m_axis_data_tvalid(m_axis_data_tvalid), // output wire m_axis_data_tvalid
|
||||
.m_axis_data_tdata(m_axis_data_tdata) // output wire [23 : 0] m_axis_data_tdata
|
||||
);
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
// You must compile the wrapper file hrc_64_12_025.v when simulating
|
||||
// the core, hrc_64_12_025. When compiling the wrapper file, be sure to
|
||||
// reference the Verilog simulation library.
|
||||
|
||||
@@ -0,0 +1,85 @@
|
||||
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:fir_compiler:7.2
|
||||
-- IP Revision: 12
|
||||
|
||||
-- The following code must appear in the VHDL architecture header.
|
||||
|
||||
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
|
||||
COMPONENT hrc_64_12_025
|
||||
PORT (
|
||||
aclk : IN STD_LOGIC;
|
||||
s_axis_data_tvalid : IN STD_LOGIC;
|
||||
s_axis_data_tready : OUT STD_LOGIC;
|
||||
s_axis_data_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axis_data_tvalid : OUT STD_LOGIC;
|
||||
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
||||
|
||||
-- The following code must appear in the VHDL architecture
|
||||
-- body. Substitute your own instance name and net names.
|
||||
|
||||
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
|
||||
your_instance_name : hrc_64_12_025
|
||||
PORT MAP (
|
||||
aclk => aclk,
|
||||
s_axis_data_tvalid => s_axis_data_tvalid,
|
||||
s_axis_data_tready => s_axis_data_tready,
|
||||
s_axis_data_tdata => s_axis_data_tdata,
|
||||
m_axis_data_tvalid => m_axis_data_tvalid,
|
||||
m_axis_data_tdata => m_axis_data_tdata
|
||||
);
|
||||
-- INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
-- You must compile the wrapper file hrc_64_12_025.vhd when simulating
|
||||
-- the core, hrc_64_12_025. When compiling the wrapper file, be sure to
|
||||
-- reference the VHDL simulation library.
|
||||
|
||||
BIN
Binary file not shown.
LFS
BIN
Binary file not shown.
+26
@@ -0,0 +1,26 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Thu Mar 30 15:29:56 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/modules/xc7z100ffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/hrc_64_12_025_synth_1/hrc_64_12_025_stub.v
|
||||
// Design : hrc_64_12_025
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z100ffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "fir_compiler_v7_2_12,Vivado 2019.1.3" *)
|
||||
module hrc_64_12_025(aclk, s_axis_data_tvalid, s_axis_data_tready,
|
||||
s_axis_data_tdata, m_axis_data_tvalid, m_axis_data_tdata)
|
||||
/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[7:0],m_axis_data_tvalid,m_axis_data_tdata[23:0]" */;
|
||||
input aclk;
|
||||
input s_axis_data_tvalid;
|
||||
output s_axis_data_tready;
|
||||
input [7:0]s_axis_data_tdata;
|
||||
output m_axis_data_tvalid;
|
||||
output [23:0]m_axis_data_tdata;
|
||||
endmodule
|
||||
+35
@@ -0,0 +1,35 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Thu Mar 30 15:29:56 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/modules/xc7z100ffg900-2/tx_qpsk/ip/managed_ip_project/managed_ip_project.runs/hrc_64_12_025_synth_1/hrc_64_12_025_stub.vhdl
|
||||
-- Design : hrc_64_12_025
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z100ffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity hrc_64_12_025 is
|
||||
Port (
|
||||
aclk : in STD_LOGIC;
|
||||
s_axis_data_tvalid : in STD_LOGIC;
|
||||
s_axis_data_tready : out STD_LOGIC;
|
||||
s_axis_data_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
m_axis_data_tvalid : out STD_LOGIC;
|
||||
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 23 downto 0 )
|
||||
);
|
||||
|
||||
end hrc_64_12_025;
|
||||
|
||||
architecture stub of hrc_64_12_025 is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[7:0],m_axis_data_tvalid,m_axis_data_tdata[23:0]";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "fir_compiler_v7_2_12,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
+281
@@ -0,0 +1,281 @@
|
||||
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:fir_compiler:7.2
|
||||
-- IP Revision: 12
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY fir_compiler_v7_2_12;
|
||||
USE fir_compiler_v7_2_12.fir_compiler_v7_2_12;
|
||||
|
||||
ENTITY hrc_64_12_025 IS
|
||||
PORT (
|
||||
aclk : IN STD_LOGIC;
|
||||
s_axis_data_tvalid : IN STD_LOGIC;
|
||||
s_axis_data_tready : OUT STD_LOGIC;
|
||||
s_axis_data_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axis_data_tvalid : OUT STD_LOGIC;
|
||||
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
|
||||
);
|
||||
END hrc_64_12_025;
|
||||
|
||||
ARCHITECTURE hrc_64_12_025_arch OF hrc_64_12_025 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF hrc_64_12_025_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT fir_compiler_v7_2_12 IS
|
||||
GENERIC (
|
||||
C_XDEVICEFAMILY : STRING;
|
||||
C_ELABORATION_DIR : STRING;
|
||||
C_COMPONENT_NAME : STRING;
|
||||
C_COEF_FILE : STRING;
|
||||
C_COEF_FILE_LINES : INTEGER;
|
||||
C_FILTER_TYPE : INTEGER;
|
||||
C_INTERP_RATE : INTEGER;
|
||||
C_DECIM_RATE : INTEGER;
|
||||
C_ZERO_PACKING_FACTOR : INTEGER;
|
||||
C_SYMMETRY : INTEGER;
|
||||
C_NUM_FILTS : INTEGER;
|
||||
C_NUM_TAPS : INTEGER;
|
||||
C_NUM_CHANNELS : INTEGER;
|
||||
C_CHANNEL_PATTERN : STRING;
|
||||
C_ROUND_MODE : INTEGER;
|
||||
C_COEF_RELOAD : INTEGER;
|
||||
C_NUM_RELOAD_SLOTS : INTEGER;
|
||||
C_COL_MODE : INTEGER;
|
||||
C_COL_PIPE_LEN : INTEGER;
|
||||
C_COL_CONFIG : STRING;
|
||||
C_OPTIMIZATION : INTEGER;
|
||||
C_DATA_PATH_WIDTHS : STRING;
|
||||
C_DATA_IP_PATH_WIDTHS : STRING;
|
||||
C_DATA_PX_PATH_WIDTHS : STRING;
|
||||
C_DATA_WIDTH : INTEGER;
|
||||
C_COEF_PATH_WIDTHS : STRING;
|
||||
C_COEF_WIDTH : INTEGER;
|
||||
C_DATA_PATH_SRC : STRING;
|
||||
C_COEF_PATH_SRC : STRING;
|
||||
C_PX_PATH_SRC : STRING;
|
||||
C_DATA_PATH_SIGN : STRING;
|
||||
C_COEF_PATH_SIGN : STRING;
|
||||
C_ACCUM_PATH_WIDTHS : STRING;
|
||||
C_OUTPUT_WIDTH : INTEGER;
|
||||
C_OUTPUT_PATH_WIDTHS : STRING;
|
||||
C_ACCUM_OP_PATH_WIDTHS : STRING;
|
||||
C_EXT_MULT_CNFG : STRING;
|
||||
C_DATA_PATH_PSAMP_SRC : STRING;
|
||||
C_OP_PATH_PSAMP_SRC : STRING;
|
||||
C_NUM_MADDS : INTEGER;
|
||||
C_OPT_MADDS : STRING;
|
||||
C_OVERSAMPLING_RATE : INTEGER;
|
||||
C_INPUT_RATE : INTEGER;
|
||||
C_OUTPUT_RATE : INTEGER;
|
||||
C_DATA_MEMTYPE : INTEGER;
|
||||
C_COEF_MEMTYPE : INTEGER;
|
||||
C_IPBUFF_MEMTYPE : INTEGER;
|
||||
C_OPBUFF_MEMTYPE : INTEGER;
|
||||
C_DATAPATH_MEMTYPE : INTEGER;
|
||||
C_MEM_ARRANGEMENT : INTEGER;
|
||||
C_DATA_MEM_PACKING : INTEGER;
|
||||
C_COEF_MEM_PACKING : INTEGER;
|
||||
C_FILTS_PACKED : INTEGER;
|
||||
C_LATENCY : INTEGER;
|
||||
C_HAS_ARESETn : INTEGER;
|
||||
C_HAS_ACLKEN : INTEGER;
|
||||
C_DATA_HAS_TLAST : INTEGER;
|
||||
C_S_DATA_HAS_FIFO : INTEGER;
|
||||
C_S_DATA_HAS_TUSER : INTEGER;
|
||||
C_S_DATA_TDATA_WIDTH : INTEGER;
|
||||
C_S_DATA_TUSER_WIDTH : INTEGER;
|
||||
C_M_DATA_HAS_TREADY : INTEGER;
|
||||
C_M_DATA_HAS_TUSER : INTEGER;
|
||||
C_M_DATA_TDATA_WIDTH : INTEGER;
|
||||
C_M_DATA_TUSER_WIDTH : INTEGER;
|
||||
C_HAS_CONFIG_CHANNEL : INTEGER;
|
||||
C_CONFIG_SYNC_MODE : INTEGER;
|
||||
C_CONFIG_PACKET_SIZE : INTEGER;
|
||||
C_CONFIG_TDATA_WIDTH : INTEGER;
|
||||
C_RELOAD_TDATA_WIDTH : INTEGER
|
||||
);
|
||||
PORT (
|
||||
aresetn : IN STD_LOGIC;
|
||||
aclk : IN STD_LOGIC;
|
||||
aclken : IN STD_LOGIC;
|
||||
s_axis_data_tvalid : IN STD_LOGIC;
|
||||
s_axis_data_tready : OUT STD_LOGIC;
|
||||
s_axis_data_tlast : IN STD_LOGIC;
|
||||
s_axis_data_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axis_data_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
s_axis_config_tvalid : IN STD_LOGIC;
|
||||
s_axis_config_tready : OUT STD_LOGIC;
|
||||
s_axis_config_tlast : IN STD_LOGIC;
|
||||
s_axis_config_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axis_reload_tvalid : IN STD_LOGIC;
|
||||
s_axis_reload_tready : OUT STD_LOGIC;
|
||||
s_axis_reload_tlast : IN STD_LOGIC;
|
||||
s_axis_reload_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
m_axis_data_tvalid : OUT STD_LOGIC;
|
||||
m_axis_data_tready : IN STD_LOGIC;
|
||||
m_axis_data_tlast : OUT STD_LOGIC;
|
||||
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
|
||||
event_s_data_tlast_missing : OUT STD_LOGIC;
|
||||
event_s_data_tlast_unexpected : OUT STD_LOGIC;
|
||||
event_s_data_chanid_incorrect : OUT STD_LOGIC;
|
||||
event_s_config_tlast_missing : OUT STD_LOGIC;
|
||||
event_s_config_tlast_unexpected : OUT STD_LOGIC;
|
||||
event_s_reload_tlast_missing : OUT STD_LOGIC;
|
||||
event_s_reload_tlast_unexpected : OUT STD_LOGIC
|
||||
);
|
||||
END COMPONENT fir_compiler_v7_2_12;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axis_data_tvalid: SIGNAL IS "XIL_INTERFACENAME M_AXIS_DATA, TDATA_NUM_BYTES 3, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TREADY";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_data_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_DATA, TDATA_NUM_BYTES 1, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF aclk: SIGNAL IS "XIL_INTERFACENAME aclk_intf, ASSOCIATED_BUSIF S_AXIS_CONFIG:M_AXIS_DATA:S_AXIS_DATA:S_AXIS_RELOAD, ASSOCIATED_RESET aresetn, ASSOCIATED_CLKEN aclken, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
|
||||
BEGIN
|
||||
U0 : fir_compiler_v7_2_12
|
||||
GENERIC MAP (
|
||||
C_XDEVICEFAMILY => "zynq",
|
||||
C_ELABORATION_DIR => "./",
|
||||
C_COMPONENT_NAME => "hrc_64_12_025",
|
||||
C_COEF_FILE => "hrc_64_12_025.mif",
|
||||
C_COEF_FILE_LINES => 448,
|
||||
C_FILTER_TYPE => 2,
|
||||
C_INTERP_RATE => 64,
|
||||
C_DECIM_RATE => 1,
|
||||
C_ZERO_PACKING_FACTOR => 1,
|
||||
C_SYMMETRY => 1,
|
||||
C_NUM_FILTS => 1,
|
||||
C_NUM_TAPS => 769,
|
||||
C_NUM_CHANNELS => 1,
|
||||
C_CHANNEL_PATTERN => "fixed",
|
||||
C_ROUND_MODE => 0,
|
||||
C_COEF_RELOAD => 0,
|
||||
C_NUM_RELOAD_SLOTS => 1,
|
||||
C_COL_MODE => 1,
|
||||
C_COL_PIPE_LEN => 4,
|
||||
C_COL_CONFIG => "7",
|
||||
C_OPTIMIZATION => 0,
|
||||
C_DATA_PATH_WIDTHS => "2",
|
||||
C_DATA_IP_PATH_WIDTHS => "2",
|
||||
C_DATA_PX_PATH_WIDTHS => "2",
|
||||
C_DATA_WIDTH => 2,
|
||||
C_COEF_PATH_WIDTHS => "17",
|
||||
C_COEF_WIDTH => 16,
|
||||
C_DATA_PATH_SRC => "0",
|
||||
C_COEF_PATH_SRC => "0",
|
||||
C_PX_PATH_SRC => "0",
|
||||
C_DATA_PATH_SIGN => "0",
|
||||
C_COEF_PATH_SIGN => "0",
|
||||
C_ACCUM_PATH_WIDTHS => "19",
|
||||
C_OUTPUT_WIDTH => 18,
|
||||
C_OUTPUT_PATH_WIDTHS => "18",
|
||||
C_ACCUM_OP_PATH_WIDTHS => "18",
|
||||
C_EXT_MULT_CNFG => "none",
|
||||
C_DATA_PATH_PSAMP_SRC => "0",
|
||||
C_OP_PATH_PSAMP_SRC => "0",
|
||||
C_NUM_MADDS => 7,
|
||||
C_OPT_MADDS => "none",
|
||||
C_OVERSAMPLING_RATE => 1,
|
||||
C_INPUT_RATE => 64,
|
||||
C_OUTPUT_RATE => 1,
|
||||
C_DATA_MEMTYPE => 0,
|
||||
C_COEF_MEMTYPE => 2,
|
||||
C_IPBUFF_MEMTYPE => 0,
|
||||
C_OPBUFF_MEMTYPE => 2,
|
||||
C_DATAPATH_MEMTYPE => 0,
|
||||
C_MEM_ARRANGEMENT => 1,
|
||||
C_DATA_MEM_PACKING => 0,
|
||||
C_COEF_MEM_PACKING => 0,
|
||||
C_FILTS_PACKED => 0,
|
||||
C_LATENCY => 17,
|
||||
C_HAS_ARESETn => 0,
|
||||
C_HAS_ACLKEN => 0,
|
||||
C_DATA_HAS_TLAST => 0,
|
||||
C_S_DATA_HAS_FIFO => 0,
|
||||
C_S_DATA_HAS_TUSER => 0,
|
||||
C_S_DATA_TDATA_WIDTH => 8,
|
||||
C_S_DATA_TUSER_WIDTH => 1,
|
||||
C_M_DATA_HAS_TREADY => 0,
|
||||
C_M_DATA_HAS_TUSER => 0,
|
||||
C_M_DATA_TDATA_WIDTH => 24,
|
||||
C_M_DATA_TUSER_WIDTH => 1,
|
||||
C_HAS_CONFIG_CHANNEL => 0,
|
||||
C_CONFIG_SYNC_MODE => 0,
|
||||
C_CONFIG_PACKET_SIZE => 0,
|
||||
C_CONFIG_TDATA_WIDTH => 1,
|
||||
C_RELOAD_TDATA_WIDTH => 1
|
||||
)
|
||||
PORT MAP (
|
||||
aresetn => '1',
|
||||
aclk => aclk,
|
||||
aclken => '1',
|
||||
s_axis_data_tvalid => s_axis_data_tvalid,
|
||||
s_axis_data_tready => s_axis_data_tready,
|
||||
s_axis_data_tlast => '0',
|
||||
s_axis_data_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
s_axis_data_tdata => s_axis_data_tdata,
|
||||
s_axis_config_tvalid => '0',
|
||||
s_axis_config_tlast => '0',
|
||||
s_axis_config_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
s_axis_reload_tvalid => '0',
|
||||
s_axis_reload_tlast => '0',
|
||||
s_axis_reload_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
m_axis_data_tvalid => m_axis_data_tvalid,
|
||||
m_axis_data_tready => '1',
|
||||
m_axis_data_tdata => m_axis_data_tdata
|
||||
);
|
||||
END hrc_64_12_025_arch;
|
||||
+3821
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
+27417
File diff suppressed because it is too large
Load Diff
+55945
File diff suppressed because it is too large
Load Diff
+17045
File diff suppressed because it is too large
Load Diff
+1367
File diff suppressed because it is too large
Load Diff
+1317
File diff suppressed because it is too large
Load Diff
+1127
File diff suppressed because it is too large
Load Diff
+2403
File diff suppressed because it is too large
Load Diff
+418
@@ -0,0 +1,418 @@
|
||||
`protect begin_protected
|
||||
`protect version = 1
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
122,
|
||||
104,
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
383,
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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2101,
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
2717,
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||||
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||||
3955,
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||||
4597,
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
13126,
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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00001242 0 5 0 2 333 369
|
||||
ffffe44e 0 5 0 1 333 369
|
||||
000011c8 0 5 0 2 334 368
|
||||
ffffe2ea 0 5 0 1 334 368
|
||||
00001139 0 5 0 2 335 367
|
||||
ffffe199 0 5 0 1 335 367
|
||||
00001092 0 5 0 2 336 366
|
||||
ffffe05c 0 5 0 1 336 366
|
||||
00000fd8 0 5 0 2 337 365
|
||||
ffffdf30 0 5 0 1 337 365
|
||||
00000f0a 0 5 0 2 338 364
|
||||
ffffde1a 0 5 0 1 338 364
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
00000151 0 5 0 2 350 352
|
||||
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|
||||
ffffeb98 0 5 0 0 351 0
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
ffff8f7d 0 6 0 2 392 438
|
||||
000085bd 0 6 0 1 392 438
|
||||
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|
||||
00008700 0 6 0 1 393 437
|
||||
ffff96b0 0 6 0 2 394 436
|
||||
00008836 0 6 0 1 394 436
|
||||
ffff9a8a 0 6 0 2 395 435
|
||||
00008960 0 6 0 1 395 435
|
||||
ffff9e8d 0 6 0 2 396 434
|
||||
00008a7d 0 6 0 1 396 434
|
||||
ffffa2b8 0 6 0 2 397 433
|
||||
00008b8a 0 6 0 1 397 433
|
||||
ffffa70a 0 6 0 2 398 432
|
||||
00008c8c 0 6 0 1 398 432
|
||||
ffffab7f 0 6 0 2 399 431
|
||||
00008d7f 0 6 0 1 399 431
|
||||
ffffb017 0 6 0 2 400 430
|
||||
00008e65 0 6 0 1 400 430
|
||||
ffffb4d2 0 6 0 2 401 429
|
||||
00008f3c 0 6 0 1 401 429
|
||||
ffffb9aa 0 6 0 2 402 428
|
||||
00009006 0 6 0 1 402 428
|
||||
ffffbea0 0 6 0 2 403 427
|
||||
000090c0 0 6 0 1 403 427
|
||||
ffffc3b1 0 6 0 2 404 426
|
||||
0000916d 0 6 0 1 404 426
|
||||
ffffc8db 0 6 0 2 405 425
|
||||
0000920b 0 6 0 1 405 425
|
||||
ffffce1c 0 6 0 2 406 424
|
||||
0000929a 0 6 0 1 406 424
|
||||
ffffd372 0 6 0 2 407 423
|
||||
0000931a 0 6 0 1 407 423
|
||||
ffffd8db 0 6 0 2 408 422
|
||||
0000938b 0 6 0 1 408 422
|
||||
ffffde53 0 6 0 2 409 421
|
||||
000093ed 0 6 0 1 409 421
|
||||
ffffe3db 0 6 0 2 410 420
|
||||
00009441 0 6 0 1 410 420
|
||||
ffffe96d 0 6 0 2 411 419
|
||||
00009485 0 6 0 1 411 419
|
||||
ffffef0a 0 6 0 2 412 418
|
||||
000094ba 0 6 0 1 412 418
|
||||
fffff4ae 0 6 0 2 413 417
|
||||
000094e0 0 6 0 1 413 417
|
||||
fffffa55 0 6 0 2 414 416
|
||||
000094f7 0 6 0 1 414 416
|
||||
00004a7f 0 6 0 0 415 0
|
||||
00007fff 0 6 0 0 447 0
|
||||
+258
@@ -0,0 +1,258 @@
|
||||
MEMORY_INITIALIZATION_RADIX = 10;
|
||||
MEMORY_INITIALIZATION_VECTOR =
|
||||
-2147483647,
|
||||
-2130640638,
|
||||
-2113797629,
|
||||
-2096954620,
|
||||
-2080111611,
|
||||
-2063268602,
|
||||
-2046425593,
|
||||
-2029582584,
|
||||
-2012739575,
|
||||
-1995896566,
|
||||
-1979053557,
|
||||
-1962210548,
|
||||
-1945367539,
|
||||
-1928524530,
|
||||
-1911681521,
|
||||
-1894838512,
|
||||
-1877995503,
|
||||
-1861152494,
|
||||
-1844309485,
|
||||
-1827466476,
|
||||
-1810623467,
|
||||
-1793780458,
|
||||
-1776937449,
|
||||
-1760094440,
|
||||
-1743251431,
|
||||
-1726408422,
|
||||
-1709565413,
|
||||
-1692722404,
|
||||
-1675879395,
|
||||
-1659036386,
|
||||
-1642193377,
|
||||
-1625350368,
|
||||
-1608507359,
|
||||
-1591664350,
|
||||
-1574821341,
|
||||
-1557978332,
|
||||
-1541135323,
|
||||
-1524292314,
|
||||
-1507449305,
|
||||
-1490606296,
|
||||
-1473763287,
|
||||
-1456920278,
|
||||
-1440077269,
|
||||
-1423234260,
|
||||
-1406391251,
|
||||
-1389548242,
|
||||
-1372705233,
|
||||
-1355862224,
|
||||
-1339019215,
|
||||
-1322176206,
|
||||
-1305333197,
|
||||
-1288490188,
|
||||
-1271647179,
|
||||
-1254804170,
|
||||
-1237961161,
|
||||
-1221118152,
|
||||
-1204275143,
|
||||
-1187432134,
|
||||
-1170589125,
|
||||
-1153746116,
|
||||
-1136903107,
|
||||
-1120060098,
|
||||
-1103217089,
|
||||
-1086374080,
|
||||
-1069531071,
|
||||
-1052688062,
|
||||
-1035845053,
|
||||
-1019002044,
|
||||
-1002159035,
|
||||
-985316026,
|
||||
-968473017,
|
||||
-951630008,
|
||||
-934786999,
|
||||
-917943990,
|
||||
-901100981,
|
||||
-884257972,
|
||||
-867414963,
|
||||
-850571954,
|
||||
-833728945,
|
||||
-816885936,
|
||||
-800042927,
|
||||
-783199918,
|
||||
-766356909,
|
||||
-749513900,
|
||||
-732670891,
|
||||
-715827882,
|
||||
-698984873,
|
||||
-682141864,
|
||||
-665298855,
|
||||
-648455846,
|
||||
-631612837,
|
||||
-614769828,
|
||||
-597926819,
|
||||
-581083810,
|
||||
-564240801,
|
||||
-547397792,
|
||||
-530554783,
|
||||
-513711774,
|
||||
-496868765,
|
||||
-480025756,
|
||||
-463182747,
|
||||
-446339738,
|
||||
-429496729,
|
||||
-412653720,
|
||||
-395810711,
|
||||
-378967702,
|
||||
-362124693,
|
||||
-345281684,
|
||||
-328438675,
|
||||
-311595666,
|
||||
-294752657,
|
||||
-277909648,
|
||||
-261066639,
|
||||
-244223630,
|
||||
-227380621,
|
||||
-210537612,
|
||||
-193694603,
|
||||
-176851594,
|
||||
-160008585,
|
||||
-143165576,
|
||||
-126322567,
|
||||
-109479558,
|
||||
-92636549,
|
||||
-75793540,
|
||||
-58950531,
|
||||
-42107522,
|
||||
-25264513,
|
||||
-8421504,
|
||||
8421504,
|
||||
25264513,
|
||||
42107522,
|
||||
58950531,
|
||||
75793540,
|
||||
92636549,
|
||||
109479558,
|
||||
126322567,
|
||||
143165576,
|
||||
160008585,
|
||||
176851594,
|
||||
193694603,
|
||||
210537612,
|
||||
227380621,
|
||||
244223630,
|
||||
261066639,
|
||||
277909648,
|
||||
294752657,
|
||||
311595666,
|
||||
328438675,
|
||||
345281684,
|
||||
362124693,
|
||||
378967702,
|
||||
395810711,
|
||||
412653720,
|
||||
429496729,
|
||||
446339738,
|
||||
463182747,
|
||||
480025756,
|
||||
496868765,
|
||||
513711774,
|
||||
530554783,
|
||||
547397792,
|
||||
564240801,
|
||||
581083810,
|
||||
597926819,
|
||||
614769828,
|
||||
631612837,
|
||||
648455846,
|
||||
665298855,
|
||||
682141864,
|
||||
698984873,
|
||||
715827882,
|
||||
732670891,
|
||||
749513900,
|
||||
766356909,
|
||||
783199918,
|
||||
800042927,
|
||||
816885936,
|
||||
833728945,
|
||||
850571954,
|
||||
867414963,
|
||||
884257972,
|
||||
901100981,
|
||||
917943990,
|
||||
934786999,
|
||||
951630008,
|
||||
968473017,
|
||||
985316026,
|
||||
1002159035,
|
||||
1019002044,
|
||||
1035845053,
|
||||
1052688062,
|
||||
1069531071,
|
||||
1086374080,
|
||||
1103217089,
|
||||
1120060098,
|
||||
1136903107,
|
||||
1153746116,
|
||||
1170589125,
|
||||
1187432134,
|
||||
1204275143,
|
||||
1221118152,
|
||||
1237961161,
|
||||
1254804170,
|
||||
1271647179,
|
||||
1288490188,
|
||||
1305333197,
|
||||
1322176206,
|
||||
1339019215,
|
||||
1355862224,
|
||||
1372705233,
|
||||
1389548242,
|
||||
1406391251,
|
||||
1423234260,
|
||||
1440077269,
|
||||
1456920278,
|
||||
1473763287,
|
||||
1490606296,
|
||||
1507449305,
|
||||
1524292314,
|
||||
1541135323,
|
||||
1557978332,
|
||||
1574821341,
|
||||
1591664350,
|
||||
1608507359,
|
||||
1625350368,
|
||||
1642193377,
|
||||
1659036386,
|
||||
1675879395,
|
||||
1692722404,
|
||||
1709565413,
|
||||
1726408422,
|
||||
1743251431,
|
||||
1760094440,
|
||||
1776937449,
|
||||
1793780458,
|
||||
1810623467,
|
||||
1827466476,
|
||||
1844309485,
|
||||
1861152494,
|
||||
1877995503,
|
||||
1894838512,
|
||||
1911681521,
|
||||
1928524530,
|
||||
1945367539,
|
||||
1962210548,
|
||||
1979053557,
|
||||
1995896566,
|
||||
2012739575,
|
||||
2029582584,
|
||||
2046425593,
|
||||
2063268602,
|
||||
2080111611,
|
||||
2096954620,
|
||||
2113797629,
|
||||
2130640638,
|
||||
2147483647;
|
||||
@@ -0,0 +1,83 @@
|
||||
################################################################################
|
||||
# Vivado (TM) v2019.1.3 (64-bit)
|
||||
#
|
||||
# README.txt: Please read the sections below to understand the steps required
|
||||
# to simulate the design for a simulator, the directory structure
|
||||
# and the generated exported files.
|
||||
#
|
||||
################################################################################
|
||||
|
||||
1. Simulate Design
|
||||
|
||||
To simulate design, cd to the simulator directory and execute the script.
|
||||
|
||||
For example:-
|
||||
|
||||
% cd questa
|
||||
% ./top.sh
|
||||
|
||||
The export simulation flow requires the Xilinx pre-compiled simulation library
|
||||
components for the target simulator. These components are referred using the
|
||||
'-lib_map_path' switch. If this switch is specified, then the export simulation
|
||||
will automatically set this library path in the generated script and update,
|
||||
copy the simulator setup file(s) in the exported directory.
|
||||
|
||||
If '-lib_map_path' is not specified, then the pre-compiled simulation library
|
||||
information will not be included in the exported scripts and that may cause
|
||||
simulation errors when running this script. Alternatively, you can provide the
|
||||
library information using this switch while executing the generated script.
|
||||
|
||||
For example:-
|
||||
|
||||
% ./top.sh -lib_map_path /design/questa/clibs
|
||||
|
||||
Please refer to the generated script header 'Prerequisite' section for more details.
|
||||
|
||||
2. Directory Structure
|
||||
|
||||
By default, if the -directory switch is not specified, export_simulation will
|
||||
create the following directory structure:-
|
||||
|
||||
<current_working_directory>/export_sim/<simulator>
|
||||
|
||||
For example, if the current working directory is /tmp/test, export_simulation
|
||||
will create the following directory path:-
|
||||
|
||||
/tmp/test/export_sim/questa
|
||||
|
||||
If -directory switch is specified, export_simulation will create a simulator
|
||||
sub-directory under the specified directory path.
|
||||
|
||||
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
|
||||
command will create the following directory:-
|
||||
|
||||
/tmp/test/my_test_area/func_sim/questa
|
||||
|
||||
By default, if -simulator is not specified, export_simulation will create a
|
||||
simulator sub-directory for each simulator and export the files for each simulator
|
||||
in this sub-directory respectively.
|
||||
|
||||
IMPORTANT: Please note that the simulation library path must be specified manually
|
||||
in the generated script for the respective simulator. Please refer to the generated
|
||||
script header 'Prerequisite' section for more details.
|
||||
|
||||
3. Exported script and files
|
||||
|
||||
Export simulation will create the driver shell script, setup files and copy the
|
||||
design sources in the output directory path.
|
||||
|
||||
By default, when the -script_name switch is not specified, export_simulation will
|
||||
create the following script name:-
|
||||
|
||||
<simulation_top>.sh (Unix)
|
||||
When exporting the files for an IP using the -of_objects switch, export_simulation
|
||||
will create the following script name:-
|
||||
|
||||
<ip-name>.sh (Unix)
|
||||
Export simulation will create the setup files for the target simulator specified
|
||||
with the -simulator switch.
|
||||
|
||||
For example, if the target simulator is "ies", export_simulation will create the
|
||||
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
|
||||
file.
|
||||
|
||||
+49
@@ -0,0 +1,49 @@
|
||||
################################################################################
|
||||
# Vivado (TM) v2019.1.3 (64-bit)
|
||||
#
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Thu Mar 30 15:31:26 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
1. How to run the generated simulation script:-
|
||||
|
||||
From the shell prompt in the current directory, issue the following command:-
|
||||
|
||||
./cmpy_18x8.sh
|
||||
|
||||
This command will launch the 'compile', 'elaborate' and 'simulate' functions
|
||||
implemented in the script file for the 3-step flow. These functions are called
|
||||
from the main 'run' function in the script file.
|
||||
|
||||
The 'run' function first executes the 'setup' function, the purpose of which is to
|
||||
create simulator specific setup files, create design library mappings and library
|
||||
directories and copy 'glbl.v' from the Vivado software install location into the
|
||||
current directory.
|
||||
|
||||
The 'setup' function is also used for removing the simulator generated data in
|
||||
order to reset the current directory to the original state when export_simulation
|
||||
was launched from Vivado. This generated data can be removed by specifying the
|
||||
'-reset_run' switch to the './cmpy_18x8.sh' script.
|
||||
|
||||
./cmpy_18x8.sh -reset_run
|
||||
|
||||
To keep the generated data from the previous run but regenerate the setup files and
|
||||
library directories, use the '-noclean_files' switch.
|
||||
|
||||
./cmpy_18x8.sh -noclean_files
|
||||
|
||||
For more information on the script, please type './cmpy_18x8.sh -help'.
|
||||
|
||||
2. Additional design information files:-
|
||||
|
||||
export_simulation generates following additional file that can be used for fetching
|
||||
the design files information or for integrating with external custom scripts.
|
||||
|
||||
Name : file_info.txt
|
||||
Purpose: This file contains detail design file information based on the compile order
|
||||
when export_simulation was executed from Vivado. The file contains information
|
||||
about the file type, name, whether it is part of the IP, associated library
|
||||
and the file path information.
|
||||
Executable
+152
@@ -0,0 +1,152 @@
|
||||
#!/bin/bash -f
|
||||
#*********************************************************************************************************
|
||||
# Vivado (TM) v2019.1.3 (64-bit)
|
||||
#
|
||||
# Filename : cmpy_18x8.sh
|
||||
# Simulator : Aldec Active-HDL Simulator
|
||||
# Description : Simulation script for compiling, elaborating and verifying the project source files.
|
||||
# The script will automatically create the design libraries sub-directories in the run
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Thu Mar 30 15:31:26 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
# usage: cmpy_18x8.sh [-help]
|
||||
# usage: cmpy_18x8.sh [-lib_map_path]
|
||||
# usage: cmpy_18x8.sh [-noclean_files]
|
||||
# usage: cmpy_18x8.sh [-reset_run]
|
||||
#
|
||||
# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
|
||||
# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
|
||||
# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
|
||||
# that points to these libraries and rerun export_simulation. For more information about this switch please
|
||||
# type 'export_simulation -help' in the Tcl shell.
|
||||
#
|
||||
# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
|
||||
# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
|
||||
# executing this script. Please type 'cmpy_18x8.sh -help' for more information.
|
||||
#
|
||||
# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
|
||||
#
|
||||
#*********************************************************************************************************
|
||||
|
||||
|
||||
# Script info
|
||||
echo -e "cmpy_18x8.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
|
||||
|
||||
# Main steps
|
||||
run()
|
||||
{
|
||||
check_args $# $1
|
||||
setup $1 $2
|
||||
compile
|
||||
simulate
|
||||
}
|
||||
|
||||
# RUN_STEP: <compile>
|
||||
compile()
|
||||
{
|
||||
# Compile design files
|
||||
source compile.do 2>&1 | tee -a compile.log
|
||||
|
||||
}
|
||||
|
||||
# RUN_STEP: <simulate>
|
||||
simulate()
|
||||
{
|
||||
runvsimsa -l simulate.log -do "do {simulate.do}"
|
||||
}
|
||||
|
||||
# STEP: setup
|
||||
setup()
|
||||
{
|
||||
case $1 in
|
||||
"-lib_map_path" )
|
||||
if [[ ($2 == "") ]]; then
|
||||
echo -e "ERROR: Simulation library directory path not specified (type \"./cmpy_18x8.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
map_setup_file $2
|
||||
;;
|
||||
"-reset_run" )
|
||||
reset_run
|
||||
echo -e "INFO: Simulation run files deleted.\n"
|
||||
exit 0
|
||||
;;
|
||||
"-noclean_files" )
|
||||
# do not remove previous data
|
||||
;;
|
||||
* )
|
||||
map_setup_file $2
|
||||
esac
|
||||
|
||||
# Add any setup/initialization commands here:-
|
||||
|
||||
# <user specific commands>
|
||||
|
||||
}
|
||||
|
||||
# Map library.cfg file
|
||||
map_setup_file()
|
||||
{
|
||||
file="library.cfg"
|
||||
lib_map_path=""
|
||||
if [[ ($1 != "") ]]; then
|
||||
lib_map_path="$1"
|
||||
fi
|
||||
if [[ ($lib_map_path != "") ]]; then
|
||||
src_file="$lib_map_path/$file"
|
||||
if [[ -e $src_file ]]; then
|
||||
vmap -link $lib_map_path
|
||||
fi
|
||||
fi
|
||||
}
|
||||
|
||||
# Delete generated data from the previous run
|
||||
reset_run()
|
||||
{
|
||||
files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl)
|
||||
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
|
||||
file="${files_to_remove[i]}"
|
||||
if [[ -e $file ]]; then
|
||||
rm -rf $file
|
||||
fi
|
||||
done
|
||||
}
|
||||
|
||||
# Check command line arguments
|
||||
check_args()
|
||||
{
|
||||
if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
|
||||
echo -e "ERROR: Unknown option specified '$2' (type \"./cmpy_18x8.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
|
||||
if [[ ($2 == "-help" || $2 == "-h") ]]; then
|
||||
usage
|
||||
fi
|
||||
}
|
||||
|
||||
# Script usage
|
||||
usage()
|
||||
{
|
||||
msg="Usage: cmpy_18x8.sh [-help]\n\
|
||||
Usage: cmpy_18x8.sh [-lib_map_path]\n\
|
||||
Usage: cmpy_18x8.sh [-reset_run]\n\
|
||||
Usage: cmpy_18x8.sh [-noclean_files]\n\n\
|
||||
[-help] -- Print help information for this script\n\n\
|
||||
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
|
||||
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
|
||||
[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
|
||||
from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
|
||||
-noclean_files switch.\n\n\
|
||||
[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
|
||||
echo -e $msg
|
||||
exit 1
|
||||
}
|
||||
|
||||
# Launch script
|
||||
run $1 $2
|
||||
+52
@@ -0,0 +1,52 @@
|
||||
vlib work
|
||||
vlib activehdl
|
||||
|
||||
vlib activehdl/xil_defaultlib
|
||||
vlib activehdl/xpm
|
||||
vlib activehdl/xbip_utils_v3_0_10
|
||||
vlib activehdl/axi_utils_v2_0_6
|
||||
vlib activehdl/xbip_pipe_v3_0_6
|
||||
vlib activehdl/xbip_bram18k_v3_0_6
|
||||
vlib activehdl/mult_gen_v12_0_15
|
||||
vlib activehdl/cmpy_v6_0_17
|
||||
|
||||
vmap xil_defaultlib activehdl/xil_defaultlib
|
||||
vmap xpm activehdl/xpm
|
||||
vmap xbip_utils_v3_0_10 activehdl/xbip_utils_v3_0_10
|
||||
vmap axi_utils_v2_0_6 activehdl/axi_utils_v2_0_6
|
||||
vmap xbip_pipe_v3_0_6 activehdl/xbip_pipe_v3_0_6
|
||||
vmap xbip_bram18k_v3_0_6 activehdl/xbip_bram18k_v3_0_6
|
||||
vmap mult_gen_v12_0_15 activehdl/mult_gen_v12_0_15
|
||||
vmap cmpy_v6_0_17 activehdl/cmpy_v6_0_17
|
||||
|
||||
vlog -work xil_defaultlib -sv2k12 \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
|
||||
vcom -work xpm -93 \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
|
||||
vcom -work xbip_utils_v3_0_10 -93 \
|
||||
"../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \
|
||||
|
||||
vcom -work axi_utils_v2_0_6 -93 \
|
||||
"../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \
|
||||
|
||||
vcom -work xbip_pipe_v3_0_6 -93 \
|
||||
"../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd" \
|
||||
|
||||
vcom -work xbip_bram18k_v3_0_6 -93 \
|
||||
"../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd" \
|
||||
|
||||
vcom -work mult_gen_v12_0_15 -93 \
|
||||
"../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd" \
|
||||
|
||||
vcom -work cmpy_v6_0_17 -93 \
|
||||
"../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd" \
|
||||
|
||||
vcom -work xil_defaultlib -93 \
|
||||
"../../../ip/cmpy_18x8/sim/cmpy_18x8.vhd" \
|
||||
|
||||
|
||||
vlog -work xil_defaultlib \
|
||||
"glbl.v"
|
||||
|
||||
+10
@@ -0,0 +1,10 @@
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
||||
xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,
|
||||
axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,
|
||||
xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd,
|
||||
xbip_bram18k_v3_0_vh_rfs.vhd,vhdl,xbip_bram18k_v3_0_6,../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd,
|
||||
mult_gen_v12_0_vh_rfs.vhd,vhdl,mult_gen_v12_0_15,../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd,
|
||||
cmpy_v6_0_vh_rfs.vhd,vhdl,cmpy_v6_0_17,../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd,
|
||||
cmpy_18x8.vhd,vhdl,xil_defaultlib,../../../ip/cmpy_18x8/sim/cmpy_18x8.vhd,
|
||||
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||
+71
@@ -0,0 +1,71 @@
|
||||
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
+17
@@ -0,0 +1,17 @@
|
||||
onbreak {quit -force}
|
||||
onerror {quit -force}
|
||||
|
||||
asim -t 1ps +access +r +m+cmpy_18x8 -L xil_defaultlib -L xpm -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_15 -L cmpy_v6_0_17 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.cmpy_18x8 xil_defaultlib.glbl
|
||||
|
||||
do {wave.do}
|
||||
|
||||
view wave
|
||||
view structure
|
||||
|
||||
do {cmpy_18x8.udo}
|
||||
|
||||
run -all
|
||||
|
||||
endsim
|
||||
|
||||
quit -force
|
||||
+2
@@ -0,0 +1,2 @@
|
||||
add wave *
|
||||
add wave /glbl/GSR
|
||||
@@ -0,0 +1,48 @@
|
||||
################################################################################
|
||||
# Vivado (TM) v2019.1.3 (64-bit)
|
||||
#
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Thu Mar 30 15:31:26 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
1. How to run the generated simulation script:-
|
||||
|
||||
From the shell prompt in the current directory, issue the following command:-
|
||||
|
||||
./cmpy_18x8.sh
|
||||
|
||||
This command will launch the 'execute' function for the single-step flow. This
|
||||
function is called from the main 'run' function in the script file.
|
||||
|
||||
The 'run' function first executes the 'setup' function, the purpose of which is to
|
||||
create simulator specific setup files, create design library mappings and library
|
||||
directories and copy 'glbl.v' from the Vivado software install location into the
|
||||
current directory.
|
||||
|
||||
The 'setup' function is also used for removing the simulator generated data in
|
||||
order to reset the current directory to the original state when export_simulation
|
||||
was launched from Vivado. This generated data can be removed by specifying the
|
||||
'-reset_run' switch to the './cmpy_18x8.sh' script.
|
||||
|
||||
./cmpy_18x8.sh -reset_run
|
||||
|
||||
To keep the generated data from the previous run but regenerate the setup files and
|
||||
library directories, use the '-noclean_files' switch.
|
||||
|
||||
./cmpy_18x8.sh -noclean_files
|
||||
|
||||
For more information on the script, please type './cmpy_18x8.sh -help'.
|
||||
|
||||
2. Additional design information files:-
|
||||
|
||||
export_simulation generates following additional file that can be used for fetching
|
||||
the design files information or for integrating with external custom scripts.
|
||||
|
||||
Name : file_info.txt
|
||||
Purpose: This file contains detail design file information based on the compile order
|
||||
when export_simulation was executed from Vivado. The file contains information
|
||||
about the file type, name, whether it is part of the IP, associated library
|
||||
and the file path information.
|
||||
+175
@@ -0,0 +1,175 @@
|
||||
#!/bin/bash -f
|
||||
#*********************************************************************************************************
|
||||
# Vivado (TM) v2019.1.3 (64-bit)
|
||||
#
|
||||
# Filename : cmpy_18x8.sh
|
||||
# Simulator : Cadence Incisive Enterprise Simulator
|
||||
# Description : Simulation script for compiling, elaborating and verifying the project source files.
|
||||
# The script will automatically create the design libraries sub-directories in the run
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Thu Mar 30 15:31:26 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
# usage: cmpy_18x8.sh [-help]
|
||||
# usage: cmpy_18x8.sh [-lib_map_path]
|
||||
# usage: cmpy_18x8.sh [-noclean_files]
|
||||
# usage: cmpy_18x8.sh [-reset_run]
|
||||
#
|
||||
# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
|
||||
# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
|
||||
# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
|
||||
# that points to these libraries and rerun export_simulation. For more information about this switch please
|
||||
# type 'export_simulation -help' in the Tcl shell.
|
||||
#
|
||||
# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
|
||||
# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
|
||||
# executing this script. Please type 'cmpy_18x8.sh -help' for more information.
|
||||
#
|
||||
# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
|
||||
#
|
||||
#*********************************************************************************************************
|
||||
|
||||
# Directory path for design sources and include directories (if any) wrt this path
|
||||
ref_dir="."
|
||||
|
||||
# Override directory with 'export_sim_ref_dir' env path value if set in the shell
|
||||
if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
|
||||
ref_dir="$export_sim_ref_dir"
|
||||
fi
|
||||
|
||||
# Set the compiled library directory
|
||||
ref_lib_dir="."
|
||||
|
||||
# Command line options
|
||||
irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen"
|
||||
|
||||
# Design libraries
|
||||
design_libs=(xil_defaultlib xpm xbip_utils_v3_0_10 axi_utils_v2_0_6 xbip_pipe_v3_0_6 xbip_bram18k_v3_0_6 mult_gen_v12_0_15 cmpy_v6_0_17)
|
||||
|
||||
# Simulation root library directory
|
||||
sim_lib_dir="ies_lib"
|
||||
|
||||
# Script info
|
||||
echo -e "cmpy_18x8.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
|
||||
|
||||
# Main steps
|
||||
run()
|
||||
{
|
||||
check_args $# $1
|
||||
setup $1 $2
|
||||
execute
|
||||
}
|
||||
|
||||
# RUN_STEP: <execute>
|
||||
execute()
|
||||
{
|
||||
irun $irun_opts \
|
||||
-reflib "$ref_lib_dir/unisim:unisim" \
|
||||
-reflib "$ref_lib_dir/unisims_ver:unisims_ver" \
|
||||
-reflib "$ref_lib_dir/secureip:secureip" \
|
||||
-reflib "$ref_lib_dir/unimacro:unimacro" \
|
||||
-reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \
|
||||
-top xil_defaultlib.cmpy_18x8 \
|
||||
-f run.f \
|
||||
-top glbl \
|
||||
glbl.v
|
||||
}
|
||||
|
||||
# STEP: setup
|
||||
setup()
|
||||
{
|
||||
case $1 in
|
||||
"-lib_map_path" )
|
||||
if [[ ($2 == "") ]]; then
|
||||
echo -e "ERROR: Simulation library directory path not specified (type \"./cmpy_18x8.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
else
|
||||
ref_lib_dir=$2
|
||||
fi
|
||||
;;
|
||||
"-reset_run" )
|
||||
reset_run
|
||||
echo -e "INFO: Simulation run files deleted.\n"
|
||||
exit 0
|
||||
;;
|
||||
"-noclean_files" )
|
||||
# do not remove previous data
|
||||
;;
|
||||
* )
|
||||
esac
|
||||
|
||||
create_lib_dir
|
||||
|
||||
# Add any setup/initialization commands here:-
|
||||
|
||||
# <user specific commands>
|
||||
|
||||
}
|
||||
|
||||
# Create design library directory paths
|
||||
create_lib_dir()
|
||||
{
|
||||
if [[ -e $sim_lib_dir ]]; then
|
||||
rm -rf $sim_lib_dir
|
||||
fi
|
||||
|
||||
for (( i=0; i<${#design_libs[*]}; i++ )); do
|
||||
lib="${design_libs[i]}"
|
||||
lib_dir="$sim_lib_dir/$lib"
|
||||
if [[ ! -e $lib_dir ]]; then
|
||||
mkdir -p $lib_dir
|
||||
fi
|
||||
done
|
||||
}
|
||||
|
||||
# Delete generated data from the previous run
|
||||
reset_run()
|
||||
{
|
||||
files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs)
|
||||
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
|
||||
file="${files_to_remove[i]}"
|
||||
if [[ -e $file ]]; then
|
||||
rm -rf $file
|
||||
fi
|
||||
done
|
||||
|
||||
create_lib_dir
|
||||
}
|
||||
|
||||
# Check command line arguments
|
||||
check_args()
|
||||
{
|
||||
if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
|
||||
echo -e "ERROR: Unknown option specified '$2' (type \"./cmpy_18x8.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
|
||||
if [[ ($2 == "-help" || $2 == "-h") ]]; then
|
||||
usage
|
||||
fi
|
||||
}
|
||||
|
||||
# Script usage
|
||||
usage()
|
||||
{
|
||||
msg="Usage: cmpy_18x8.sh [-help]\n\
|
||||
Usage: cmpy_18x8.sh [-lib_map_path]\n\
|
||||
Usage: cmpy_18x8.sh [-reset_run]\n\
|
||||
Usage: cmpy_18x8.sh [-noclean_files]\n\n\
|
||||
[-help] -- Print help information for this script\n\n\
|
||||
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
|
||||
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
|
||||
[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
|
||||
from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
|
||||
-noclean_files switch.\n\n\
|
||||
[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
|
||||
echo -e $msg
|
||||
exit 1
|
||||
}
|
||||
|
||||
# Launch script
|
||||
run $1 $2
|
||||
+10
@@ -0,0 +1,10 @@
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
||||
xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,
|
||||
axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,
|
||||
xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd,
|
||||
xbip_bram18k_v3_0_vh_rfs.vhd,vhdl,xbip_bram18k_v3_0_6,../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd,
|
||||
mult_gen_v12_0_vh_rfs.vhd,vhdl,mult_gen_v12_0_15,../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd,
|
||||
cmpy_v6_0_vh_rfs.vhd,vhdl,cmpy_v6_0_17,../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd,
|
||||
cmpy_18x8.vhd,vhdl,xil_defaultlib,../../../ip/cmpy_18x8/sim/cmpy_18x8.vhd,
|
||||
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||
@@ -0,0 +1,71 @@
|
||||
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
@@ -0,0 +1,31 @@
|
||||
-makelib ies_lib/xil_defaultlib -sv \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
-endlib
|
||||
-makelib ies_lib/xpm \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
-endlib
|
||||
-makelib ies_lib/xbip_utils_v3_0_10 \
|
||||
"../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \
|
||||
-endlib
|
||||
-makelib ies_lib/axi_utils_v2_0_6 \
|
||||
"../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \
|
||||
-endlib
|
||||
-makelib ies_lib/xbip_pipe_v3_0_6 \
|
||||
"../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd" \
|
||||
-endlib
|
||||
-makelib ies_lib/xbip_bram18k_v3_0_6 \
|
||||
"../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd" \
|
||||
-endlib
|
||||
-makelib ies_lib/mult_gen_v12_0_15 \
|
||||
"../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd" \
|
||||
-endlib
|
||||
-makelib ies_lib/cmpy_v6_0_17 \
|
||||
"../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd" \
|
||||
-endlib
|
||||
-makelib ies_lib/xil_defaultlib \
|
||||
"../../../ip/cmpy_18x8/sim/cmpy_18x8.vhd" \
|
||||
-endlib
|
||||
-makelib ies_lib/xil_defaultlib \
|
||||
glbl.v
|
||||
-endlib
|
||||
|
||||
+49
@@ -0,0 +1,49 @@
|
||||
################################################################################
|
||||
# Vivado (TM) v2019.1.3 (64-bit)
|
||||
#
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Thu Mar 30 15:31:26 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
1. How to run the generated simulation script:-
|
||||
|
||||
From the shell prompt in the current directory, issue the following command:-
|
||||
|
||||
./cmpy_18x8.sh
|
||||
|
||||
This command will launch the 'compile', 'elaborate' and 'simulate' functions
|
||||
implemented in the script file for the 3-step flow. These functions are called
|
||||
from the main 'run' function in the script file.
|
||||
|
||||
The 'run' function first executes the 'setup' function, the purpose of which is to
|
||||
create simulator specific setup files, create design library mappings and library
|
||||
directories and copy 'glbl.v' from the Vivado software install location into the
|
||||
current directory.
|
||||
|
||||
The 'setup' function is also used for removing the simulator generated data in
|
||||
order to reset the current directory to the original state when export_simulation
|
||||
was launched from Vivado. This generated data can be removed by specifying the
|
||||
'-reset_run' switch to the './cmpy_18x8.sh' script.
|
||||
|
||||
./cmpy_18x8.sh -reset_run
|
||||
|
||||
To keep the generated data from the previous run but regenerate the setup files and
|
||||
library directories, use the '-noclean_files' switch.
|
||||
|
||||
./cmpy_18x8.sh -noclean_files
|
||||
|
||||
For more information on the script, please type './cmpy_18x8.sh -help'.
|
||||
|
||||
2. Additional design information files:-
|
||||
|
||||
export_simulation generates following additional file that can be used for fetching
|
||||
the design files information or for integrating with external custom scripts.
|
||||
|
||||
Name : file_info.txt
|
||||
Purpose: This file contains detail design file information based on the compile order
|
||||
when export_simulation was executed from Vivado. The file contains information
|
||||
about the file type, name, whether it is part of the IP, associated library
|
||||
and the file path information.
|
||||
Executable
+167
@@ -0,0 +1,167 @@
|
||||
#!/bin/bash -f
|
||||
#*********************************************************************************************************
|
||||
# Vivado (TM) v2019.1.3 (64-bit)
|
||||
#
|
||||
# Filename : cmpy_18x8.sh
|
||||
# Simulator : Mentor Graphics ModelSim Simulator
|
||||
# Description : Simulation script for compiling, elaborating and verifying the project source files.
|
||||
# The script will automatically create the design libraries sub-directories in the run
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Thu Mar 30 15:31:26 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
# usage: cmpy_18x8.sh [-help]
|
||||
# usage: cmpy_18x8.sh [-lib_map_path]
|
||||
# usage: cmpy_18x8.sh [-noclean_files]
|
||||
# usage: cmpy_18x8.sh [-reset_run]
|
||||
#
|
||||
# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
|
||||
# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
|
||||
# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
|
||||
# that points to these libraries and rerun export_simulation. For more information about this switch please
|
||||
# type 'export_simulation -help' in the Tcl shell.
|
||||
#
|
||||
# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
|
||||
# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
|
||||
# executing this script. Please type 'cmpy_18x8.sh -help' for more information.
|
||||
#
|
||||
# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
|
||||
#
|
||||
#*********************************************************************************************************
|
||||
|
||||
|
||||
# Script info
|
||||
echo -e "cmpy_18x8.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
|
||||
|
||||
# Main steps
|
||||
run()
|
||||
{
|
||||
check_args $# $1
|
||||
setup $1 $2
|
||||
compile
|
||||
simulate
|
||||
}
|
||||
|
||||
# RUN_STEP: <compile>
|
||||
compile()
|
||||
{
|
||||
# Compile design files
|
||||
source compile.do 2>&1 | tee -a compile.log
|
||||
|
||||
}
|
||||
|
||||
# RUN_STEP: <simulate>
|
||||
simulate()
|
||||
{
|
||||
vsim -64 -c -do "do {simulate.do}" -l simulate.log
|
||||
}
|
||||
|
||||
# STEP: setup
|
||||
setup()
|
||||
{
|
||||
case $1 in
|
||||
"-lib_map_path" )
|
||||
if [[ ($2 == "") ]]; then
|
||||
echo -e "ERROR: Simulation library directory path not specified (type \"./cmpy_18x8.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
copy_setup_file $2
|
||||
;;
|
||||
"-reset_run" )
|
||||
reset_run
|
||||
echo -e "INFO: Simulation run files deleted.\n"
|
||||
exit 0
|
||||
;;
|
||||
"-noclean_files" )
|
||||
# do not remove previous data
|
||||
;;
|
||||
* )
|
||||
copy_setup_file $2
|
||||
esac
|
||||
|
||||
create_lib_dir
|
||||
|
||||
# Add any setup/initialization commands here:-
|
||||
|
||||
# <user specific commands>
|
||||
|
||||
}
|
||||
|
||||
# Copy modelsim.ini file
|
||||
copy_setup_file()
|
||||
{
|
||||
file="modelsim.ini"
|
||||
if [[ ($1 != "") ]]; then
|
||||
lib_map_path="$1"
|
||||
else
|
||||
lib_map_path="/home/josh/Software/Xilinx/CompLib/Model/2019.1"
|
||||
fi
|
||||
if [[ ($lib_map_path != "") ]]; then
|
||||
src_file="$lib_map_path/$file"
|
||||
cp $src_file .
|
||||
fi
|
||||
}
|
||||
|
||||
# Create design library directory
|
||||
create_lib_dir()
|
||||
{
|
||||
lib_dir="modelsim_lib"
|
||||
if [[ -e $lib_dir ]]; then
|
||||
rm -rf $lib_dir
|
||||
fi
|
||||
|
||||
mkdir $lib_dir
|
||||
|
||||
}
|
||||
|
||||
# Delete generated data from the previous run
|
||||
reset_run()
|
||||
{
|
||||
files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib)
|
||||
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
|
||||
file="${files_to_remove[i]}"
|
||||
if [[ -e $file ]]; then
|
||||
rm -rf $file
|
||||
fi
|
||||
done
|
||||
|
||||
create_lib_dir
|
||||
}
|
||||
|
||||
# Check command line arguments
|
||||
check_args()
|
||||
{
|
||||
if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
|
||||
echo -e "ERROR: Unknown option specified '$2' (type \"./cmpy_18x8.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
|
||||
if [[ ($2 == "-help" || $2 == "-h") ]]; then
|
||||
usage
|
||||
fi
|
||||
}
|
||||
|
||||
# Script usage
|
||||
usage()
|
||||
{
|
||||
msg="Usage: cmpy_18x8.sh [-help]\n\
|
||||
Usage: cmpy_18x8.sh [-lib_map_path]\n\
|
||||
Usage: cmpy_18x8.sh [-reset_run]\n\
|
||||
Usage: cmpy_18x8.sh [-noclean_files]\n\n\
|
||||
[-help] -- Print help information for this script\n\n\
|
||||
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
|
||||
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
|
||||
[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
|
||||
from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
|
||||
-noclean_files switch.\n\n\
|
||||
[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
|
||||
echo -e $msg
|
||||
exit 1
|
||||
}
|
||||
|
||||
# Launch script
|
||||
run $1 $2
|
||||
+11
@@ -0,0 +1,11 @@
|
||||
vlib modelsim_lib/work
|
||||
vlib modelsim_lib/msim
|
||||
|
||||
vlib modelsim_lib/msim/xil_defaultlib
|
||||
|
||||
vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib
|
||||
|
||||
vcom -work xil_defaultlib -64 -93 \
|
||||
"../../../ip/cmpy_18x8/sim/cmpy_18x8.vhd" \
|
||||
|
||||
|
||||
+1
@@ -0,0 +1 @@
|
||||
cmpy_18x8.vhd,vhdl,xil_defaultlib,../../../ip/cmpy_18x8/sim/cmpy_18x8.vhd,
|
||||
+16
@@ -0,0 +1,16 @@
|
||||
onbreak {quit -f}
|
||||
onerror {quit -f}
|
||||
|
||||
vsim -voptargs="+acc" -t 1ps -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_15 -L cmpy_v6_0_17 -L xil_defaultlib -L secureip -L xpm -lib xil_defaultlib xil_defaultlib.cmpy_18x8
|
||||
|
||||
do {wave.do}
|
||||
|
||||
view wave
|
||||
view structure
|
||||
view signals
|
||||
|
||||
do {cmpy_18x8.udo}
|
||||
|
||||
run -all
|
||||
|
||||
quit -force
|
||||
+1
@@ -0,0 +1 @@
|
||||
add wave *
|
||||
+49
@@ -0,0 +1,49 @@
|
||||
################################################################################
|
||||
# Vivado (TM) v2019.1.3 (64-bit)
|
||||
#
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Thu Mar 30 15:31:26 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
1. How to run the generated simulation script:-
|
||||
|
||||
From the shell prompt in the current directory, issue the following command:-
|
||||
|
||||
./cmpy_18x8.sh
|
||||
|
||||
This command will launch the 'compile', 'elaborate' and 'simulate' functions
|
||||
implemented in the script file for the 3-step flow. These functions are called
|
||||
from the main 'run' function in the script file.
|
||||
|
||||
The 'run' function first executes the 'setup' function, the purpose of which is to
|
||||
create simulator specific setup files, create design library mappings and library
|
||||
directories and copy 'glbl.v' from the Vivado software install location into the
|
||||
current directory.
|
||||
|
||||
The 'setup' function is also used for removing the simulator generated data in
|
||||
order to reset the current directory to the original state when export_simulation
|
||||
was launched from Vivado. This generated data can be removed by specifying the
|
||||
'-reset_run' switch to the './cmpy_18x8.sh' script.
|
||||
|
||||
./cmpy_18x8.sh -reset_run
|
||||
|
||||
To keep the generated data from the previous run but regenerate the setup files and
|
||||
library directories, use the '-noclean_files' switch.
|
||||
|
||||
./cmpy_18x8.sh -noclean_files
|
||||
|
||||
For more information on the script, please type './cmpy_18x8.sh -help'.
|
||||
|
||||
2. Additional design information files:-
|
||||
|
||||
export_simulation generates following additional file that can be used for fetching
|
||||
the design files information or for integrating with external custom scripts.
|
||||
|
||||
Name : file_info.txt
|
||||
Purpose: This file contains detail design file information based on the compile order
|
||||
when export_simulation was executed from Vivado. The file contains information
|
||||
about the file type, name, whether it is part of the IP, associated library
|
||||
and the file path information.
|
||||
Executable
+175
@@ -0,0 +1,175 @@
|
||||
#!/bin/bash -f
|
||||
#*********************************************************************************************************
|
||||
# Vivado (TM) v2019.1.3 (64-bit)
|
||||
#
|
||||
# Filename : cmpy_18x8.sh
|
||||
# Simulator : Mentor Graphics Questa Advanced Simulator
|
||||
# Description : Simulation script for compiling, elaborating and verifying the project source files.
|
||||
# The script will automatically create the design libraries sub-directories in the run
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Thu Mar 30 15:31:26 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
# usage: cmpy_18x8.sh [-help]
|
||||
# usage: cmpy_18x8.sh [-lib_map_path]
|
||||
# usage: cmpy_18x8.sh [-noclean_files]
|
||||
# usage: cmpy_18x8.sh [-reset_run]
|
||||
#
|
||||
# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
|
||||
# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
|
||||
# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
|
||||
# that points to these libraries and rerun export_simulation. For more information about this switch please
|
||||
# type 'export_simulation -help' in the Tcl shell.
|
||||
#
|
||||
# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
|
||||
# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
|
||||
# executing this script. Please type 'cmpy_18x8.sh -help' for more information.
|
||||
#
|
||||
# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
|
||||
#
|
||||
#*********************************************************************************************************
|
||||
|
||||
|
||||
# Script info
|
||||
echo -e "cmpy_18x8.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
|
||||
|
||||
# Main steps
|
||||
run()
|
||||
{
|
||||
check_args $# $1
|
||||
setup $1 $2
|
||||
compile
|
||||
elaborate
|
||||
simulate
|
||||
}
|
||||
|
||||
# RUN_STEP: <compile>
|
||||
compile()
|
||||
{
|
||||
# Compile design files
|
||||
source compile.do 2>&1 | tee -a compile.log
|
||||
|
||||
}
|
||||
|
||||
# RUN_STEP: <elaborate>
|
||||
elaborate()
|
||||
{
|
||||
source elaborate.do 2>&1 | tee -a elaborate.log
|
||||
}
|
||||
|
||||
# RUN_STEP: <simulate>
|
||||
simulate()
|
||||
{
|
||||
vsim -64 -c -do "do {simulate.do}" -l simulate.log
|
||||
}
|
||||
|
||||
# STEP: setup
|
||||
setup()
|
||||
{
|
||||
case $1 in
|
||||
"-lib_map_path" )
|
||||
if [[ ($2 == "") ]]; then
|
||||
echo -e "ERROR: Simulation library directory path not specified (type \"./cmpy_18x8.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
copy_setup_file $2
|
||||
;;
|
||||
"-reset_run" )
|
||||
reset_run
|
||||
echo -e "INFO: Simulation run files deleted.\n"
|
||||
exit 0
|
||||
;;
|
||||
"-noclean_files" )
|
||||
# do not remove previous data
|
||||
;;
|
||||
* )
|
||||
copy_setup_file $2
|
||||
esac
|
||||
|
||||
create_lib_dir
|
||||
|
||||
# Add any setup/initialization commands here:-
|
||||
|
||||
# <user specific commands>
|
||||
|
||||
}
|
||||
|
||||
# Copy modelsim.ini file
|
||||
copy_setup_file()
|
||||
{
|
||||
file="modelsim.ini"
|
||||
lib_map_path="<SPECIFY_COMPILED_LIB_PATH>"
|
||||
if [[ ($1 != "" && -e $1) ]]; then
|
||||
lib_map_path="$1"
|
||||
else
|
||||
echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n"
|
||||
fi
|
||||
if [[ ($lib_map_path != "") ]]; then
|
||||
src_file="$lib_map_path/$file"
|
||||
cp $src_file .
|
||||
fi
|
||||
}
|
||||
|
||||
# Create design library directory
|
||||
create_lib_dir()
|
||||
{
|
||||
lib_dir="questa_lib"
|
||||
if [[ -e $lib_dir ]]; then
|
||||
rm -rf $lib_dir
|
||||
fi
|
||||
|
||||
mkdir $lib_dir
|
||||
|
||||
}
|
||||
|
||||
# Delete generated data from the previous run
|
||||
reset_run()
|
||||
{
|
||||
files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib)
|
||||
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
|
||||
file="${files_to_remove[i]}"
|
||||
if [[ -e $file ]]; then
|
||||
rm -rf $file
|
||||
fi
|
||||
done
|
||||
|
||||
create_lib_dir
|
||||
}
|
||||
|
||||
# Check command line arguments
|
||||
check_args()
|
||||
{
|
||||
if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
|
||||
echo -e "ERROR: Unknown option specified '$2' (type \"./cmpy_18x8.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
|
||||
if [[ ($2 == "-help" || $2 == "-h") ]]; then
|
||||
usage
|
||||
fi
|
||||
}
|
||||
|
||||
# Script usage
|
||||
usage()
|
||||
{
|
||||
msg="Usage: cmpy_18x8.sh [-help]\n\
|
||||
Usage: cmpy_18x8.sh [-lib_map_path]\n\
|
||||
Usage: cmpy_18x8.sh [-reset_run]\n\
|
||||
Usage: cmpy_18x8.sh [-noclean_files]\n\n\
|
||||
[-help] -- Print help information for this script\n\n\
|
||||
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
|
||||
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
|
||||
[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
|
||||
from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
|
||||
-noclean_files switch.\n\n\
|
||||
[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
|
||||
echo -e $msg
|
||||
exit 1
|
||||
}
|
||||
|
||||
# Launch script
|
||||
run $1 $2
|
||||
+52
@@ -0,0 +1,52 @@
|
||||
vlib questa_lib/work
|
||||
vlib questa_lib/msim
|
||||
|
||||
vlib questa_lib/msim/xil_defaultlib
|
||||
vlib questa_lib/msim/xpm
|
||||
vlib questa_lib/msim/xbip_utils_v3_0_10
|
||||
vlib questa_lib/msim/axi_utils_v2_0_6
|
||||
vlib questa_lib/msim/xbip_pipe_v3_0_6
|
||||
vlib questa_lib/msim/xbip_bram18k_v3_0_6
|
||||
vlib questa_lib/msim/mult_gen_v12_0_15
|
||||
vlib questa_lib/msim/cmpy_v6_0_17
|
||||
|
||||
vmap xil_defaultlib questa_lib/msim/xil_defaultlib
|
||||
vmap xpm questa_lib/msim/xpm
|
||||
vmap xbip_utils_v3_0_10 questa_lib/msim/xbip_utils_v3_0_10
|
||||
vmap axi_utils_v2_0_6 questa_lib/msim/axi_utils_v2_0_6
|
||||
vmap xbip_pipe_v3_0_6 questa_lib/msim/xbip_pipe_v3_0_6
|
||||
vmap xbip_bram18k_v3_0_6 questa_lib/msim/xbip_bram18k_v3_0_6
|
||||
vmap mult_gen_v12_0_15 questa_lib/msim/mult_gen_v12_0_15
|
||||
vmap cmpy_v6_0_17 questa_lib/msim/cmpy_v6_0_17
|
||||
|
||||
vlog -work xil_defaultlib -64 -sv \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
|
||||
vcom -work xpm -64 -93 \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
|
||||
vcom -work xbip_utils_v3_0_10 -64 -93 \
|
||||
"../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \
|
||||
|
||||
vcom -work axi_utils_v2_0_6 -64 -93 \
|
||||
"../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \
|
||||
|
||||
vcom -work xbip_pipe_v3_0_6 -64 -93 \
|
||||
"../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd" \
|
||||
|
||||
vcom -work xbip_bram18k_v3_0_6 -64 -93 \
|
||||
"../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd" \
|
||||
|
||||
vcom -work mult_gen_v12_0_15 -64 -93 \
|
||||
"../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd" \
|
||||
|
||||
vcom -work cmpy_v6_0_17 -64 -93 \
|
||||
"../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd" \
|
||||
|
||||
vcom -work xil_defaultlib -64 -93 \
|
||||
"../../../ip/cmpy_18x8/sim/cmpy_18x8.vhd" \
|
||||
|
||||
|
||||
vlog -work xil_defaultlib \
|
||||
"glbl.v"
|
||||
|
||||
+1
@@ -0,0 +1 @@
|
||||
vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_15 -L cmpy_v6_0_17 -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.cmpy_18x8 xil_defaultlib.glbl -o cmpy_18x8_opt
|
||||
+10
@@ -0,0 +1,10 @@
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
||||
xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,
|
||||
axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,
|
||||
xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd,
|
||||
xbip_bram18k_v3_0_vh_rfs.vhd,vhdl,xbip_bram18k_v3_0_6,../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd,
|
||||
mult_gen_v12_0_vh_rfs.vhd,vhdl,mult_gen_v12_0_15,../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd,
|
||||
cmpy_v6_0_vh_rfs.vhd,vhdl,cmpy_v6_0_17,../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd,
|
||||
cmpy_18x8.vhd,vhdl,xil_defaultlib,../../../ip/cmpy_18x8/sim/cmpy_18x8.vhd,
|
||||
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||
@@ -0,0 +1,71 @@
|
||||
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
+16
@@ -0,0 +1,16 @@
|
||||
onbreak {quit -f}
|
||||
onerror {quit -f}
|
||||
|
||||
vsim -t 1ps -lib xil_defaultlib cmpy_18x8_opt
|
||||
|
||||
do {wave.do}
|
||||
|
||||
view wave
|
||||
view structure
|
||||
view signals
|
||||
|
||||
do {cmpy_18x8.udo}
|
||||
|
||||
run -all
|
||||
|
||||
quit -force
|
||||
@@ -0,0 +1,2 @@
|
||||
add wave *
|
||||
add wave /glbl/GSR
|
||||
+49
@@ -0,0 +1,49 @@
|
||||
################################################################################
|
||||
# Vivado (TM) v2019.1.3 (64-bit)
|
||||
#
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Thu Mar 30 15:31:26 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
1. How to run the generated simulation script:-
|
||||
|
||||
From the shell prompt in the current directory, issue the following command:-
|
||||
|
||||
./cmpy_18x8.sh
|
||||
|
||||
This command will launch the 'compile', 'elaborate' and 'simulate' functions
|
||||
implemented in the script file for the 3-step flow. These functions are called
|
||||
from the main 'run' function in the script file.
|
||||
|
||||
The 'run' function first executes the 'setup' function, the purpose of which is to
|
||||
create simulator specific setup files, create design library mappings and library
|
||||
directories and copy 'glbl.v' from the Vivado software install location into the
|
||||
current directory.
|
||||
|
||||
The 'setup' function is also used for removing the simulator generated data in
|
||||
order to reset the current directory to the original state when export_simulation
|
||||
was launched from Vivado. This generated data can be removed by specifying the
|
||||
'-reset_run' switch to the './cmpy_18x8.sh' script.
|
||||
|
||||
./cmpy_18x8.sh -reset_run
|
||||
|
||||
To keep the generated data from the previous run but regenerate the setup files and
|
||||
library directories, use the '-noclean_files' switch.
|
||||
|
||||
./cmpy_18x8.sh -noclean_files
|
||||
|
||||
For more information on the script, please type './cmpy_18x8.sh -help'.
|
||||
|
||||
2. Additional design information files:-
|
||||
|
||||
export_simulation generates following additional file that can be used for fetching
|
||||
the design files information or for integrating with external custom scripts.
|
||||
|
||||
Name : file_info.txt
|
||||
Purpose: This file contains detail design file information based on the compile order
|
||||
when export_simulation was executed from Vivado. The file contains information
|
||||
about the file type, name, whether it is part of the IP, associated library
|
||||
and the file path information.
|
||||
Executable
+154
@@ -0,0 +1,154 @@
|
||||
#!/bin/bash -f
|
||||
#*********************************************************************************************************
|
||||
# Vivado (TM) v2019.1.3 (64-bit)
|
||||
#
|
||||
# Filename : cmpy_18x8.sh
|
||||
# Simulator : Aldec Riviera-PRO Simulator
|
||||
# Description : Simulation script for compiling, elaborating and verifying the project source files.
|
||||
# The script will automatically create the design libraries sub-directories in the run
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Thu Mar 30 15:31:26 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
# usage: cmpy_18x8.sh [-help]
|
||||
# usage: cmpy_18x8.sh [-lib_map_path]
|
||||
# usage: cmpy_18x8.sh [-noclean_files]
|
||||
# usage: cmpy_18x8.sh [-reset_run]
|
||||
#
|
||||
# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
|
||||
# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
|
||||
# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
|
||||
# that points to these libraries and rerun export_simulation. For more information about this switch please
|
||||
# type 'export_simulation -help' in the Tcl shell.
|
||||
#
|
||||
# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
|
||||
# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
|
||||
# executing this script. Please type 'cmpy_18x8.sh -help' for more information.
|
||||
#
|
||||
# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
|
||||
#
|
||||
#*********************************************************************************************************
|
||||
|
||||
|
||||
# Script info
|
||||
echo -e "cmpy_18x8.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
|
||||
|
||||
# Main steps
|
||||
run()
|
||||
{
|
||||
check_args $# $1
|
||||
setup $1 $2
|
||||
compile
|
||||
simulate
|
||||
}
|
||||
|
||||
# RUN_STEP: <compile>
|
||||
compile()
|
||||
{
|
||||
# Compile design files
|
||||
source compile.do 2>&1 | tee -a compile.log
|
||||
|
||||
}
|
||||
|
||||
# RUN_STEP: <simulate>
|
||||
simulate()
|
||||
{
|
||||
runvsimsa -l simulate.log -do "do {simulate.do}"
|
||||
}
|
||||
|
||||
# STEP: setup
|
||||
setup()
|
||||
{
|
||||
case $1 in
|
||||
"-lib_map_path" )
|
||||
if [[ ($2 == "") ]]; then
|
||||
echo -e "ERROR: Simulation library directory path not specified (type \"./cmpy_18x8.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
map_setup_file $2
|
||||
;;
|
||||
"-reset_run" )
|
||||
reset_run
|
||||
echo -e "INFO: Simulation run files deleted.\n"
|
||||
exit 0
|
||||
;;
|
||||
"-noclean_files" )
|
||||
# do not remove previous data
|
||||
;;
|
||||
* )
|
||||
map_setup_file $2
|
||||
esac
|
||||
|
||||
# Add any setup/initialization commands here:-
|
||||
|
||||
# <user specific commands>
|
||||
|
||||
}
|
||||
|
||||
# Map library.cfg file
|
||||
map_setup_file()
|
||||
{
|
||||
file="library.cfg"
|
||||
lib_map_path="<SPECIFY_COMPILED_LIB_PATH>"
|
||||
if [[ ($1 != "" && -e $1) ]]; then
|
||||
lib_map_path="$1"
|
||||
else
|
||||
echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n"
|
||||
fi
|
||||
if [[ ($lib_map_path != "") ]]; then
|
||||
src_file="$lib_map_path/$file"
|
||||
if [[ -e $src_file ]]; then
|
||||
vmap -link $lib_map_path
|
||||
fi
|
||||
fi
|
||||
}
|
||||
|
||||
# Delete generated data from the previous run
|
||||
reset_run()
|
||||
{
|
||||
files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera)
|
||||
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
|
||||
file="${files_to_remove[i]}"
|
||||
if [[ -e $file ]]; then
|
||||
rm -rf $file
|
||||
fi
|
||||
done
|
||||
}
|
||||
|
||||
# Check command line arguments
|
||||
check_args()
|
||||
{
|
||||
if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
|
||||
echo -e "ERROR: Unknown option specified '$2' (type \"./cmpy_18x8.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
|
||||
if [[ ($2 == "-help" || $2 == "-h") ]]; then
|
||||
usage
|
||||
fi
|
||||
}
|
||||
|
||||
# Script usage
|
||||
usage()
|
||||
{
|
||||
msg="Usage: cmpy_18x8.sh [-help]\n\
|
||||
Usage: cmpy_18x8.sh [-lib_map_path]\n\
|
||||
Usage: cmpy_18x8.sh [-reset_run]\n\
|
||||
Usage: cmpy_18x8.sh [-noclean_files]\n\n\
|
||||
[-help] -- Print help information for this script\n\n\
|
||||
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
|
||||
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
|
||||
[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
|
||||
from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
|
||||
-noclean_files switch.\n\n\
|
||||
[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
|
||||
echo -e $msg
|
||||
exit 1
|
||||
}
|
||||
|
||||
# Launch script
|
||||
run $1 $2
|
||||
+52
@@ -0,0 +1,52 @@
|
||||
vlib work
|
||||
vlib riviera
|
||||
|
||||
vlib riviera/xil_defaultlib
|
||||
vlib riviera/xpm
|
||||
vlib riviera/xbip_utils_v3_0_10
|
||||
vlib riviera/axi_utils_v2_0_6
|
||||
vlib riviera/xbip_pipe_v3_0_6
|
||||
vlib riviera/xbip_bram18k_v3_0_6
|
||||
vlib riviera/mult_gen_v12_0_15
|
||||
vlib riviera/cmpy_v6_0_17
|
||||
|
||||
vmap xil_defaultlib riviera/xil_defaultlib
|
||||
vmap xpm riviera/xpm
|
||||
vmap xbip_utils_v3_0_10 riviera/xbip_utils_v3_0_10
|
||||
vmap axi_utils_v2_0_6 riviera/axi_utils_v2_0_6
|
||||
vmap xbip_pipe_v3_0_6 riviera/xbip_pipe_v3_0_6
|
||||
vmap xbip_bram18k_v3_0_6 riviera/xbip_bram18k_v3_0_6
|
||||
vmap mult_gen_v12_0_15 riviera/mult_gen_v12_0_15
|
||||
vmap cmpy_v6_0_17 riviera/cmpy_v6_0_17
|
||||
|
||||
vlog -work xil_defaultlib -sv2k12 \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
|
||||
vcom -work xpm -93 \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
|
||||
vcom -work xbip_utils_v3_0_10 -93 \
|
||||
"../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \
|
||||
|
||||
vcom -work axi_utils_v2_0_6 -93 \
|
||||
"../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \
|
||||
|
||||
vcom -work xbip_pipe_v3_0_6 -93 \
|
||||
"../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd" \
|
||||
|
||||
vcom -work xbip_bram18k_v3_0_6 -93 \
|
||||
"../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd" \
|
||||
|
||||
vcom -work mult_gen_v12_0_15 -93 \
|
||||
"../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd" \
|
||||
|
||||
vcom -work cmpy_v6_0_17 -93 \
|
||||
"../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd" \
|
||||
|
||||
vcom -work xil_defaultlib -93 \
|
||||
"../../../ip/cmpy_18x8/sim/cmpy_18x8.vhd" \
|
||||
|
||||
|
||||
vlog -work xil_defaultlib \
|
||||
"glbl.v"
|
||||
|
||||
+10
@@ -0,0 +1,10 @@
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
||||
xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,
|
||||
axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,
|
||||
xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd,
|
||||
xbip_bram18k_v3_0_vh_rfs.vhd,vhdl,xbip_bram18k_v3_0_6,../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd,
|
||||
mult_gen_v12_0_vh_rfs.vhd,vhdl,mult_gen_v12_0_15,../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd,
|
||||
cmpy_v6_0_vh_rfs.vhd,vhdl,cmpy_v6_0_17,../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd,
|
||||
cmpy_18x8.vhd,vhdl,xil_defaultlib,../../../ip/cmpy_18x8/sim/cmpy_18x8.vhd,
|
||||
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||
@@ -0,0 +1,71 @@
|
||||
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
+17
@@ -0,0 +1,17 @@
|
||||
onbreak {quit -force}
|
||||
onerror {quit -force}
|
||||
|
||||
asim -t 1ps +access +r +m+cmpy_18x8 -L xil_defaultlib -L xpm -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_15 -L cmpy_v6_0_17 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.cmpy_18x8 xil_defaultlib.glbl
|
||||
|
||||
do {wave.do}
|
||||
|
||||
view wave
|
||||
view structure
|
||||
|
||||
do {cmpy_18x8.udo}
|
||||
|
||||
run -all
|
||||
|
||||
endsim
|
||||
|
||||
quit -force
|
||||
@@ -0,0 +1,2 @@
|
||||
add wave *
|
||||
add wave /glbl/GSR
|
||||
@@ -0,0 +1,49 @@
|
||||
################################################################################
|
||||
# Vivado (TM) v2019.1.3 (64-bit)
|
||||
#
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Thu Mar 30 15:31:26 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
1. How to run the generated simulation script:-
|
||||
|
||||
From the shell prompt in the current directory, issue the following command:-
|
||||
|
||||
./cmpy_18x8.sh
|
||||
|
||||
This command will launch the 'compile', 'elaborate' and 'simulate' functions
|
||||
implemented in the script file for the 3-step flow. These functions are called
|
||||
from the main 'run' function in the script file.
|
||||
|
||||
The 'run' function first executes the 'setup' function, the purpose of which is to
|
||||
create simulator specific setup files, create design library mappings and library
|
||||
directories and copy 'glbl.v' from the Vivado software install location into the
|
||||
current directory.
|
||||
|
||||
The 'setup' function is also used for removing the simulator generated data in
|
||||
order to reset the current directory to the original state when export_simulation
|
||||
was launched from Vivado. This generated data can be removed by specifying the
|
||||
'-reset_run' switch to the './cmpy_18x8.sh' script.
|
||||
|
||||
./cmpy_18x8.sh -reset_run
|
||||
|
||||
To keep the generated data from the previous run but regenerate the setup files and
|
||||
library directories, use the '-noclean_files' switch.
|
||||
|
||||
./cmpy_18x8.sh -noclean_files
|
||||
|
||||
For more information on the script, please type './cmpy_18x8.sh -help'.
|
||||
|
||||
2. Additional design information files:-
|
||||
|
||||
export_simulation generates following additional file that can be used for fetching
|
||||
the design files information or for integrating with external custom scripts.
|
||||
|
||||
Name : file_info.txt
|
||||
Purpose: This file contains detail design file information based on the compile order
|
||||
when export_simulation was executed from Vivado. The file contains information
|
||||
about the file type, name, whether it is part of the IP, associated library
|
||||
and the file path information.
|
||||
+218
@@ -0,0 +1,218 @@
|
||||
#!/bin/bash -f
|
||||
#*********************************************************************************************************
|
||||
# Vivado (TM) v2019.1.3 (64-bit)
|
||||
#
|
||||
# Filename : cmpy_18x8.sh
|
||||
# Simulator : Synopsys Verilog Compiler Simulator
|
||||
# Description : Simulation script for compiling, elaborating and verifying the project source files.
|
||||
# The script will automatically create the design libraries sub-directories in the run
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Thu Mar 30 15:31:26 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
# usage: cmpy_18x8.sh [-help]
|
||||
# usage: cmpy_18x8.sh [-lib_map_path]
|
||||
# usage: cmpy_18x8.sh [-noclean_files]
|
||||
# usage: cmpy_18x8.sh [-reset_run]
|
||||
#
|
||||
# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
|
||||
# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
|
||||
# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
|
||||
# that points to these libraries and rerun export_simulation. For more information about this switch please
|
||||
# type 'export_simulation -help' in the Tcl shell.
|
||||
#
|
||||
# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
|
||||
# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
|
||||
# executing this script. Please type 'cmpy_18x8.sh -help' for more information.
|
||||
#
|
||||
# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
|
||||
#
|
||||
#*********************************************************************************************************
|
||||
|
||||
# Directory path for design sources and include directories (if any) wrt this path
|
||||
ref_dir="."
|
||||
|
||||
# Override directory with 'export_sim_ref_dir' env path value if set in the shell
|
||||
if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
|
||||
ref_dir="$export_sim_ref_dir"
|
||||
fi
|
||||
|
||||
# Command line options
|
||||
vlogan_opts="-full64"
|
||||
vhdlan_opts="-full64"
|
||||
vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log"
|
||||
vcs_sim_opts="-ucli -licqueue -l simulate.log"
|
||||
|
||||
# Design libraries
|
||||
design_libs=(xil_defaultlib)
|
||||
|
||||
# Simulation root library directory
|
||||
sim_lib_dir="vcs_lib"
|
||||
|
||||
# Script info
|
||||
echo -e "cmpy_18x8.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
|
||||
|
||||
# Main steps
|
||||
run()
|
||||
{
|
||||
check_args $# $1
|
||||
setup $1 $2
|
||||
compile
|
||||
elaborate
|
||||
simulate
|
||||
}
|
||||
|
||||
# RUN_STEP: <compile>
|
||||
compile()
|
||||
{
|
||||
# Compile design files
|
||||
vhdlan -work xil_defaultlib $vhdlan_opts \
|
||||
"$ref_dir/../../../ip/cmpy_18x8/sim/cmpy_18x8.vhd" \
|
||||
2>&1 | tee -a vhdlan.log
|
||||
|
||||
|
||||
|
||||
}
|
||||
|
||||
# RUN_STEP: <elaborate>
|
||||
elaborate()
|
||||
{
|
||||
vcs $vcs_elab_opts xil_defaultlib.cmpy_18x8 -o cmpy_18x8_simv
|
||||
}
|
||||
|
||||
# RUN_STEP: <simulate>
|
||||
simulate()
|
||||
{
|
||||
./cmpy_18x8_simv $vcs_sim_opts -do simulate.do
|
||||
}
|
||||
|
||||
# STEP: setup
|
||||
setup()
|
||||
{
|
||||
case $1 in
|
||||
"-lib_map_path" )
|
||||
if [[ ($2 == "") ]]; then
|
||||
echo -e "ERROR: Simulation library directory path not specified (type \"./cmpy_18x8.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
create_lib_mappings $2
|
||||
;;
|
||||
"-reset_run" )
|
||||
reset_run
|
||||
echo -e "INFO: Simulation run files deleted.\n"
|
||||
exit 0
|
||||
;;
|
||||
"-noclean_files" )
|
||||
# do not remove previous data
|
||||
;;
|
||||
* )
|
||||
create_lib_mappings $2
|
||||
esac
|
||||
|
||||
create_lib_dir
|
||||
|
||||
# Add any setup/initialization commands here:-
|
||||
|
||||
# <user specific commands>
|
||||
|
||||
}
|
||||
|
||||
# Define design library mappings
|
||||
create_lib_mappings()
|
||||
{
|
||||
file="synopsys_sim.setup"
|
||||
if [[ -e $file ]]; then
|
||||
if [[ ($1 == "") ]]; then
|
||||
return
|
||||
else
|
||||
rm -rf $file
|
||||
fi
|
||||
fi
|
||||
|
||||
touch $file
|
||||
|
||||
if [[ ($1 != "") ]]; then
|
||||
lib_map_path="$1"
|
||||
else
|
||||
lib_map_path="/home/josh/Software/Xilinx/CompLib/VCS/2019.1"
|
||||
fi
|
||||
|
||||
for (( i=0; i<${#design_libs[*]}; i++ )); do
|
||||
lib="${design_libs[i]}"
|
||||
mapping="$lib:$sim_lib_dir/$lib"
|
||||
echo $mapping >> $file
|
||||
done
|
||||
|
||||
if [[ ($lib_map_path != "") ]]; then
|
||||
incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup"
|
||||
echo $incl_ref >> $file
|
||||
fi
|
||||
}
|
||||
|
||||
# Create design library directory paths
|
||||
create_lib_dir()
|
||||
{
|
||||
if [[ -e $sim_lib_dir ]]; then
|
||||
rm -rf $sim_lib_dir
|
||||
fi
|
||||
|
||||
for (( i=0; i<${#design_libs[*]}; i++ )); do
|
||||
lib="${design_libs[i]}"
|
||||
lib_dir="$sim_lib_dir/$lib"
|
||||
if [[ ! -e $lib_dir ]]; then
|
||||
mkdir -p $lib_dir
|
||||
fi
|
||||
done
|
||||
}
|
||||
|
||||
# Delete generated data from the previous run
|
||||
reset_run()
|
||||
{
|
||||
files_to_remove=(ucli.key cmpy_18x8_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc cmpy_18x8_simv.daidir)
|
||||
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
|
||||
file="${files_to_remove[i]}"
|
||||
if [[ -e $file ]]; then
|
||||
rm -rf $file
|
||||
fi
|
||||
done
|
||||
|
||||
create_lib_dir
|
||||
}
|
||||
|
||||
# Check command line arguments
|
||||
check_args()
|
||||
{
|
||||
if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
|
||||
echo -e "ERROR: Unknown option specified '$2' (type \"./cmpy_18x8.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
|
||||
if [[ ($2 == "-help" || $2 == "-h") ]]; then
|
||||
usage
|
||||
fi
|
||||
}
|
||||
|
||||
# Script usage
|
||||
usage()
|
||||
{
|
||||
msg="Usage: cmpy_18x8.sh [-help]\n\
|
||||
Usage: cmpy_18x8.sh [-lib_map_path]\n\
|
||||
Usage: cmpy_18x8.sh [-reset_run]\n\
|
||||
Usage: cmpy_18x8.sh [-noclean_files]\n\n\
|
||||
[-help] -- Print help information for this script\n\n\
|
||||
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
|
||||
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
|
||||
[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
|
||||
from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
|
||||
-noclean_files switch.\n\n\
|
||||
[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
|
||||
echo -e $msg
|
||||
exit 1
|
||||
}
|
||||
|
||||
# Launch script
|
||||
run $1 $2
|
||||
+1
@@ -0,0 +1 @@
|
||||
cmpy_18x8.vhd,vhdl,xil_defaultlib,../../../ip/cmpy_18x8/sim/cmpy_18x8.vhd,
|
||||
@@ -0,0 +1,2 @@
|
||||
run
|
||||
quit
|
||||
+48
@@ -0,0 +1,48 @@
|
||||
################################################################################
|
||||
# Vivado (TM) v2019.1.3 (64-bit)
|
||||
#
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Thu Mar 30 15:31:26 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
1. How to run the generated simulation script:-
|
||||
|
||||
From the shell prompt in the current directory, issue the following command:-
|
||||
|
||||
./cmpy_18x8.sh
|
||||
|
||||
This command will launch the 'execute' function for the single-step flow. This
|
||||
function is called from the main 'run' function in the script file.
|
||||
|
||||
The 'run' function first executes the 'setup' function, the purpose of which is to
|
||||
create simulator specific setup files, create design library mappings and library
|
||||
directories and copy 'glbl.v' from the Vivado software install location into the
|
||||
current directory.
|
||||
|
||||
The 'setup' function is also used for removing the simulator generated data in
|
||||
order to reset the current directory to the original state when export_simulation
|
||||
was launched from Vivado. This generated data can be removed by specifying the
|
||||
'-reset_run' switch to the './cmpy_18x8.sh' script.
|
||||
|
||||
./cmpy_18x8.sh -reset_run
|
||||
|
||||
To keep the generated data from the previous run but regenerate the setup files and
|
||||
library directories, use the '-noclean_files' switch.
|
||||
|
||||
./cmpy_18x8.sh -noclean_files
|
||||
|
||||
For more information on the script, please type './cmpy_18x8.sh -help'.
|
||||
|
||||
2. Additional design information files:-
|
||||
|
||||
export_simulation generates following additional file that can be used for fetching
|
||||
the design files information or for integrating with external custom scripts.
|
||||
|
||||
Name : file_info.txt
|
||||
Purpose: This file contains detail design file information based on the compile order
|
||||
when export_simulation was executed from Vivado. The file contains information
|
||||
about the file type, name, whether it is part of the IP, associated library
|
||||
and the file path information.
|
||||
Executable
+175
@@ -0,0 +1,175 @@
|
||||
#!/bin/bash -f
|
||||
#*********************************************************************************************************
|
||||
# Vivado (TM) v2019.1.3 (64-bit)
|
||||
#
|
||||
# Filename : cmpy_18x8.sh
|
||||
# Simulator : Cadence Xcelium Parallel Simulator
|
||||
# Description : Simulation script for compiling, elaborating and verifying the project source files.
|
||||
# The script will automatically create the design libraries sub-directories in the run
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Thu Mar 30 15:31:26 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
# usage: cmpy_18x8.sh [-help]
|
||||
# usage: cmpy_18x8.sh [-lib_map_path]
|
||||
# usage: cmpy_18x8.sh [-noclean_files]
|
||||
# usage: cmpy_18x8.sh [-reset_run]
|
||||
#
|
||||
# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
|
||||
# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
|
||||
# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
|
||||
# that points to these libraries and rerun export_simulation. For more information about this switch please
|
||||
# type 'export_simulation -help' in the Tcl shell.
|
||||
#
|
||||
# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
|
||||
# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
|
||||
# executing this script. Please type 'cmpy_18x8.sh -help' for more information.
|
||||
#
|
||||
# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
|
||||
#
|
||||
#*********************************************************************************************************
|
||||
|
||||
# Directory path for design sources and include directories (if any) wrt this path
|
||||
ref_dir="."
|
||||
|
||||
# Override directory with 'export_sim_ref_dir' env path value if set in the shell
|
||||
if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
|
||||
ref_dir="$export_sim_ref_dir"
|
||||
fi
|
||||
|
||||
# Set the compiled library directory
|
||||
ref_lib_dir="."
|
||||
|
||||
# Command line options
|
||||
xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen"
|
||||
|
||||
# Design libraries
|
||||
design_libs=(xil_defaultlib xpm xbip_utils_v3_0_10 axi_utils_v2_0_6 xbip_pipe_v3_0_6 xbip_bram18k_v3_0_6 mult_gen_v12_0_15 cmpy_v6_0_17)
|
||||
|
||||
# Simulation root library directory
|
||||
sim_lib_dir="xcelium_lib"
|
||||
|
||||
# Script info
|
||||
echo -e "cmpy_18x8.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
|
||||
|
||||
# Main steps
|
||||
run()
|
||||
{
|
||||
check_args $# $1
|
||||
setup $1 $2
|
||||
execute
|
||||
}
|
||||
|
||||
# RUN_STEP: <execute>
|
||||
execute()
|
||||
{
|
||||
xrun $xrun_opts \
|
||||
-reflib "$ref_lib_dir/unisim:unisim" \
|
||||
-reflib "$ref_lib_dir/unisims_ver:unisims_ver" \
|
||||
-reflib "$ref_lib_dir/secureip:secureip" \
|
||||
-reflib "$ref_lib_dir/unimacro:unimacro" \
|
||||
-reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \
|
||||
-top xil_defaultlib.cmpy_18x8 \
|
||||
-f run.f \
|
||||
-top glbl \
|
||||
glbl.v
|
||||
}
|
||||
|
||||
# STEP: setup
|
||||
setup()
|
||||
{
|
||||
case $1 in
|
||||
"-lib_map_path" )
|
||||
if [[ ($2 == "") ]]; then
|
||||
echo -e "ERROR: Simulation library directory path not specified (type \"./cmpy_18x8.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
else
|
||||
ref_lib_dir=$2
|
||||
fi
|
||||
;;
|
||||
"-reset_run" )
|
||||
reset_run
|
||||
echo -e "INFO: Simulation run files deleted.\n"
|
||||
exit 0
|
||||
;;
|
||||
"-noclean_files" )
|
||||
# do not remove previous data
|
||||
;;
|
||||
* )
|
||||
esac
|
||||
|
||||
create_lib_dir
|
||||
|
||||
# Add any setup/initialization commands here:-
|
||||
|
||||
# <user specific commands>
|
||||
|
||||
}
|
||||
|
||||
# Create design library directory paths
|
||||
create_lib_dir()
|
||||
{
|
||||
if [[ -e $sim_lib_dir ]]; then
|
||||
rm -rf $sim_lib_dir
|
||||
fi
|
||||
|
||||
for (( i=0; i<${#design_libs[*]}; i++ )); do
|
||||
lib="${design_libs[i]}"
|
||||
lib_dir="$sim_lib_dir/$lib"
|
||||
if [[ ! -e $lib_dir ]]; then
|
||||
mkdir -p $lib_dir
|
||||
fi
|
||||
done
|
||||
}
|
||||
|
||||
# Delete generated data from the previous run
|
||||
reset_run()
|
||||
{
|
||||
files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium)
|
||||
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
|
||||
file="${files_to_remove[i]}"
|
||||
if [[ -e $file ]]; then
|
||||
rm -rf $file
|
||||
fi
|
||||
done
|
||||
|
||||
create_lib_dir
|
||||
}
|
||||
|
||||
# Check command line arguments
|
||||
check_args()
|
||||
{
|
||||
if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
|
||||
echo -e "ERROR: Unknown option specified '$2' (type \"./cmpy_18x8.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
|
||||
if [[ ($2 == "-help" || $2 == "-h") ]]; then
|
||||
usage
|
||||
fi
|
||||
}
|
||||
|
||||
# Script usage
|
||||
usage()
|
||||
{
|
||||
msg="Usage: cmpy_18x8.sh [-help]\n\
|
||||
Usage: cmpy_18x8.sh [-lib_map_path]\n\
|
||||
Usage: cmpy_18x8.sh [-reset_run]\n\
|
||||
Usage: cmpy_18x8.sh [-noclean_files]\n\n\
|
||||
[-help] -- Print help information for this script\n\n\
|
||||
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
|
||||
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
|
||||
[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
|
||||
from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
|
||||
-noclean_files switch.\n\n\
|
||||
[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
|
||||
echo -e $msg
|
||||
exit 1
|
||||
}
|
||||
|
||||
# Launch script
|
||||
run $1 $2
|
||||
+10
@@ -0,0 +1,10 @@
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
||||
xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,
|
||||
axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,
|
||||
xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd,
|
||||
xbip_bram18k_v3_0_vh_rfs.vhd,vhdl,xbip_bram18k_v3_0_6,../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd,
|
||||
mult_gen_v12_0_vh_rfs.vhd,vhdl,mult_gen_v12_0_15,../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd,
|
||||
cmpy_v6_0_vh_rfs.vhd,vhdl,cmpy_v6_0_17,../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd,
|
||||
cmpy_18x8.vhd,vhdl,xil_defaultlib,../../../ip/cmpy_18x8/sim/cmpy_18x8.vhd,
|
||||
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||
@@ -0,0 +1,71 @@
|
||||
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
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