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first commit after restructuring
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`ifndef sc_util_v1_0_4_constants_GLOBAL_CONSTANTS
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`define sc_util_v1_0_4_constants_GLOBAL_CONSTANTS
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parameter integer K_MAX_NUM_BYTES = 128;
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parameter integer K_MAX_BYTE_SIZE = 7;
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parameter integer K_MAX_DATA_WIDTH = 1024;
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parameter integer K_MAX_DATA_SIZE = 10;
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parameter integer K_MIN_NUM_BYTES = 4;
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parameter integer K_MIN_BYTE_SIZE = 2;
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parameter integer K_MIN_DATA_WIDTH = 32;
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parameter integer K_MIN_DATA_SIZE = 5;
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parameter integer K_MAX_NUM_AXI4LITE_BYTES = 8;
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parameter integer K_MAX_AXI4LITE_BYTE_SIZE = 3;
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parameter integer K_MAX_AXI4LITE_DATA_WIDTH = 64;
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parameter integer K_MAX_AXI4LITE_DATA_SIZE = 6;
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parameter integer K_DATA_BITS_PER_BYTE = 9;
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||||
parameter integer K_MAX_BYTE_FACTOR = 16;
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parameter integer K_MAX_BYTE_MAGNITUDE = 5;
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parameter integer K_MAX_ADDR_WIDTH = 64;
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parameter integer K_MAX_ID_WIDTH = 32;
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parameter integer K_MAX_MEP_IDENTIFIER_WIDTH = 8;
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parameter integer K_MAX_USER_WIDTH = 1024;
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parameter integer K_MAX_USER_PAYLD = 512;
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parameter integer K_MAX_NUM_SSC = 16;
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parameter integer K_MAX_SSC_SIZE = 4;
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parameter integer K_MAX_NUM_MSC = 64;
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parameter integer K_MAX_MSC_SIZE = 6;
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parameter integer K_MAX_SWBD_PORTS = 16;
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parameter integer K_MAX_SWBD_SIZE = 4;
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parameter integer K_MAX_CASCADES = 16;
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parameter integer K_MAX_TIERS = 4;
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parameter integer K_MAX_THREADS = 16;
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parameter integer K_MAX_THREAD_SIZE = 4;
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parameter integer K_MAX_NUM_SEG = 256;
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parameter integer K_MAX_SEG_WIDTH = 8;
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parameter integer K_MAX_EP_ROUTE_WIDTH = 64;
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parameter integer K_MAX_SC_ROUTE_WIDTH = 64;
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parameter integer K_MAX_CMD_PTR = 5;
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parameter integer K_MAX_LUTRAM_PTR = 8;
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parameter integer K_MAX_BRAM_PTR = 12;
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parameter integer K_MIN_BRAM_PTR = 9;
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parameter integer K_MAX_SYNC_RATIO = 8;
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parameter integer K_MAX_PIPELINES = 8;
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parameter integer K_LOG_MAX_PIPELINES = 3;
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parameter integer K_MAX_LATENCY = 15;
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parameter integer K_LOG_MAX_LATENCY = 4;
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parameter integer K_AXIS_ARB_TDATA_NUM_BYTES = 2;
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parameter integer K_MAX_USER_BITS_PER_BYTE = 4;
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parameter integer K_MAX_INFO_WIDTH = 1;
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parameter integer K_MAX_OUTSTANDING_REQ = 3;
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parameter integer K_AXI_SIZE_WIDTH = 3;
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parameter integer K_AXI_BURST_WIDTH = 2;
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parameter integer K_AXI_RESP_WIDTH = 2;
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parameter integer K_AXI_LAST_WIDTH = 1;
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parameter integer K_AXI_LEN_WIDTH = 8;
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parameter integer K_AXI_EXCL_LEN_WIDTH = 4;
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parameter integer K_AXI_LOCK_WIDTH = 1;
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parameter integer K_AXI3_LEN_WIDTH = 4;
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parameter integer K_AXI3_LOCK_WIDTH = 2;
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parameter integer K_AXI_PROT_WIDTH = 3;
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parameter integer K_AXI_QOS_WIDTH = 4;
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parameter integer K_AXI_CACHE_WIDTH = 4;
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parameter integer K_MAX_ACCEPTANCE = 256;
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parameter integer K_MAX_FANOUT = 200;
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parameter integer K_MAX_READ_WATERMARK = 4096;
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parameter integer K_MAX_BURST_LENGTH = 256;
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parameter integer CH_R = 0;
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parameter integer CH_W = 1;
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parameter integer CH_AR = 2;
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parameter integer CH_AW = 3;
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parameter integer CH_B = 4;
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parameter integer CLK_DOWN = -2;
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parameter integer CLK_SYNC_ALIAS = -1;
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parameter integer CLK_ASYNC = 0;
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parameter integer CLK_SYNC = 1;
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parameter integer CLK_UP = 2;
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parameter integer CLKEN_NONE = 0;
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parameter integer CLKEN_S = 1;
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parameter integer CLKEN_M = 2;
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parameter integer CLKEN_S_AND_M = 3;
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parameter integer ARB_BYPASS = 0;
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parameter integer ARB_ROUNDROBIN = 1;
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parameter integer ARB_SLAVE = 2;
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parameter integer FIFO_LUTRAM = 0;
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parameter integer FIFO_BRAM = 1;
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parameter integer FIFO_NONE = 2;
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parameter integer FIFO_IP_XPM_MEMORY = 0;
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parameter integer FIFO_IP_FG = 1;
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parameter integer FIFO_IP_XPM_FIFO = 2;
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parameter integer K_T_STRUCT_EXCLUSIVE_WIDTH = 11;
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parameter integer K_T_STATIC_ADDR_PAYLD_WIDTH = 102;
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parameter integer K_T_STATIC_RDATA_PAYLD_WIDTH = 17;
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parameter integer K_T_STATIC_WDATA_PAYLD_WIDTH = 15;
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parameter integer K_T_STATIC_BRSP_PAYLD_WIDTH = 2;
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parameter integer K_T_EXCLUSIVE_WIDTH = 43;
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parameter integer K_T_ADDR_AUGMENT_WIDTH = 114;
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parameter integer K_T_DATA_AUGMENT_WIDTH = 14;
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parameter integer K_T_BRSP_AUGMENT_WIDTH = 0;
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parameter integer K_USABLE_T_ADDR_CASCADE_WIDTH = 626;
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parameter integer K_USABLE_T_DATA_CASCADE_WIDTH = 526;
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parameter integer K_USABLE_T_BRSP_CASCADE_WIDTH = 512;
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parameter integer K_T_CASCADE_WIDTH = 627;
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parameter integer K_T_SEG_LEN_WIDTH = 8;
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parameter integer K_USABLE_T_ADDR_SIDEBAND_WIDTH = 699;
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parameter integer K_USABLE_T_DATA_SIDEBAND_WIDTH = 691;
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parameter integer K_USABLE_T_BRSP_SIDEBAND_WIDTH = 691;
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parameter integer K_T_SIDEBAND_WIDTH = 700;
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parameter integer K_USABLE_T_AXPAYLD_WIDTH = 808;
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parameter integer K_USABLE_T_WPAYLD_WIDTH = 1853;
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parameter integer K_USABLE_T_RPAYLD_WIDTH = 1759;
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parameter integer K_USABLE_T_BPAYLD_WIDTH = 734;
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parameter integer K_T_PAYLD_WIDTH = 1854;
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parameter integer K_MAX_PAYLD_WIDTH = 1854;
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parameter integer K_USABLE_T_AXVECTOR_WIDTH = 1145;
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parameter integer K_USABLE_T_WVECTOR_WIDTH = 2177;
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parameter integer K_USABLE_T_RVECTOR_WIDTH = 2083;
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parameter integer K_USABLE_T_BVECTOR_WIDTH = 1058;
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parameter integer K_STATIC_AXVECTOR_WIDTH = 25;
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parameter integer K_STATIC_WVECTOR_WIDTH = 1;
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parameter integer K_STATIC_RVECTOR_WIDTH = 3;
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parameter integer K_STATIC_BVECTOR_WIDTH = 2;
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parameter integer K_T_VECTOR_WIDTH = 2178;
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parameter integer K_MAX_VECTOR_WIDTH = 2178;
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`endif
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+297
@@ -0,0 +1,297 @@
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// (c) Copyright 2016 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//-----------------------------------------------------------------------------
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||||
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/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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// cascade parameters and typedefs
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/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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typedef logic [((T_SC_AWUSER_WIDTH == 0) ? 1 : T_SC_AWUSER_WIDTH)-1:0] t_sc_awuser;
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||||
typedef logic [((T_SC_ARUSER_WIDTH == 0) ? 1 : T_SC_ARUSER_WIDTH)-1:0] t_sc_aruser;
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||||
typedef logic [((T_SC_BUSER_WIDTH == 0) ? 1 : T_SC_BUSER_WIDTH )-1:0] t_sc_buser;
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||||
typedef logic [((T_SC_RUSER_BITS_PER_BYTE == 0) ? 1 : (T_SC_RUSER_BITS_PER_BYTE*(T_SC_RDATA_WIDTH/8)))-1:0] t_sc_ruser;
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typedef logic [((T_SC_WUSER_BITS_PER_BYTE == 0) ? 1 : (T_SC_WUSER_BITS_PER_BYTE*(T_SC_WDATA_WIDTH/8)))-1:0] t_sc_wuser;
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typedef logic [T_SC_ADDR_WIDTH-1:0] t_sc_addr;
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||||
typedef logic [T_SC_MSC_ROUTE_WIDTH-1:0] t_sc_msc_route;
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||||
typedef logic [T_SC_SSC_ROUTE_WIDTH-1:0] t_sc_ssc_route;
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||||
typedef logic [(T_SC_ID_WIDTH==0?1:T_SC_ID_WIDTH)-1:0] t_sc_id;
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||||
typedef logic [(T_SC_WUSER_BITS_PER_BYTE+8)-1:0] t_sc_wuserdata_unit;
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||||
typedef logic [(T_SC_RUSER_BITS_PER_BYTE+8)-1:0] t_sc_ruserdata_unit;
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||||
typedef logic [T_SC_RDATA_WIDTH -1:0] t_sc_rdata;
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||||
typedef logic [T_SC_WDATA_WIDTH-1:0] t_sc_wdata;
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||||
typedef logic [(T_SC_WDATA_WIDTH/8)-1:0] t_sc_wstrb;
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||||
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||||
typedef struct packed {
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||||
t_sc_wuserdata_unit userdata;
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||||
logic strb;
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} t_sc_wdata_unit;
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||||
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||||
typedef struct packed {
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||||
t_sc_ruserdata_unit userdata;
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} t_sc_rdata_unit;
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||||
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typedef struct packed {
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t_sc_id id;
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||||
t_axi_len len;
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||||
t_axi_size size;
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} t_sc_addr_exclusive;
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/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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// payld parameters and typedefs
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/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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typedef struct packed {
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t_axi_cache cache;
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t_axi_qos qos;
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t_axi_prot prot;
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t_axi_lock lock;
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||||
t_sc_addr addr;
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||||
t_sc_id id;
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||||
t_sc_aruser user;
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||||
t_max_byte_size last_offset;
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||||
t_sc_addr_exclusive exclusive;
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||||
t_max_ep_route ep_route;
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||||
t_axi_len seg_len;
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t_sc_msc_route sc_route;
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} t_sc_arpayld;
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typedef struct packed {
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t_axi_cache cache;
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t_axi_qos qos;
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t_axi_prot prot;
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t_axi_lock lock;
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||||
t_sc_addr addr;
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||||
t_sc_id id;
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||||
t_sc_awuser user;
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||||
t_max_byte_size last_offset;
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||||
t_sc_addr_exclusive exclusive;
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||||
t_max_ep_route ep_route;
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||||
t_axi_len seg_len;
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||||
t_sc_msc_route sc_route;
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||||
} t_sc_awpayld;
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||||
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typedef struct packed {
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||||
t_sc_wdata_unit[(T_SC_WDATA_WIDTH/8)-1:0] bytes;
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||||
t_axi_last last;
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||||
t_max_byte_size last_offset;
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||||
t_max_byte_size first_offset;
|
||||
t_sc_msc_route sc_route;
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||||
} t_sc_wpayld;
|
||||
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||||
typedef struct packed {
|
||||
t_sc_rdata_unit[(T_SC_RDATA_WIDTH/8)-1:0] bytes;
|
||||
t_axi_last last;
|
||||
t_axi_resp resp;
|
||||
t_sc_id id;
|
||||
t_max_byte_size last_offset;
|
||||
t_max_byte_size first_offset;
|
||||
t_sc_ssc_route sc_route;
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||||
} t_sc_rpayld;
|
||||
|
||||
typedef struct packed {
|
||||
t_axi_resp resp;
|
||||
t_sc_id id;
|
||||
t_sc_buser user;
|
||||
t_sc_ssc_route sc_route;
|
||||
} t_sc_bpayld;
|
||||
|
||||
//synthesis translate_off
|
||||
`ifdef MODEL_TECH
|
||||
|
||||
function string sprint_sc_addr_exclusive(
|
||||
input t_sc_addr_exclusive excl
|
||||
);
|
||||
string str;
|
||||
str = "";
|
||||
str = $sformatf("exclusive.id = 0x%0x\n%s", excl.id,str);
|
||||
str = $sformatf("exclusive.len = 0x%0x\n%s", excl.len,str);
|
||||
str = $sformatf("exclusive.size = 0x%0x\n%s", excl.size,str);
|
||||
return (str);
|
||||
endfunction
|
||||
|
||||
function string sprint_sc_awpayld(
|
||||
input t_sc_awpayld pay
|
||||
);
|
||||
string str;
|
||||
str = "";
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||||
str = sprint_sc_addr_exclusive(pay.exclusive);
|
||||
str = $sformatf("ep_route = 0x%0x\n%s", pay.ep_route,str);
|
||||
str = $sformatf("user = 0x%0x\n%s", pay.user,str);
|
||||
str = $sformatf("sc_route = 0x%0x\n%s", pay.sc_route,str);
|
||||
str = $sformatf("seg_len = 0x%0x\n%s", pay.seg_len,str);
|
||||
str = $sformatf("id = 0x%0x\n%s", pay.id,str);
|
||||
str = $sformatf("addr = 0x%0x\n%s", pay.addr,str);
|
||||
str = $sformatf("lock = 0x%0x\n%s", pay.lock,str);
|
||||
str = $sformatf("prot = 0x%0x\n%s", pay.prot,str);
|
||||
str = $sformatf("qos = 0x%0x\n%s", pay.qos,str);
|
||||
str = $sformatf("cache = 0x%0x\n%s", pay.cache,str);
|
||||
str = $sformatf("AWPAYLD\n%s",str);
|
||||
return (str);
|
||||
endfunction : sprint_sc_awpayld
|
||||
|
||||
function string sprint_sc_arpayld(
|
||||
input t_sc_arpayld pay
|
||||
);
|
||||
string str;
|
||||
str = "";
|
||||
str = sprint_sc_addr_exclusive(pay.exclusive);
|
||||
str = $sformatf("ep_route = 0x%0x\n%s", pay.ep_route,str);
|
||||
str = $sformatf("user = 0x%0x\n%s", pay.user,str);
|
||||
str = $sformatf("sc_route = 0x%0x\n%s", pay.sc_route,str);
|
||||
str = $sformatf("seg_len = 0x%0x\n%s", pay.seg_len,str);
|
||||
str = $sformatf("id = 0x%0x\n%s", pay.id,str);
|
||||
str = $sformatf("addr = 0x%0x\n%s", pay.addr,str);
|
||||
str = $sformatf("lock = 0x%0x\n%s", pay.lock,str);
|
||||
str = $sformatf("prot = 0x%0x\n%s", pay.prot,str);
|
||||
str = $sformatf("qos = 0x%0x\n%s", pay.qos,str);
|
||||
str = $sformatf("cache = 0x%0x\n%s", pay.cache,str);
|
||||
str = $sformatf("ARPAYLD\n%s",str);
|
||||
return (str);
|
||||
endfunction : sprint_sc_arpayld
|
||||
|
||||
function string sprint_sc_wpayld(
|
||||
input t_sc_wpayld pay
|
||||
);
|
||||
string str;
|
||||
string strb;
|
||||
string data;
|
||||
str = "";
|
||||
strb = "";
|
||||
data = "";
|
||||
str = $sformatf("first_offset = 0x%0x\n%s", pay.first_offset,str);
|
||||
str = $sformatf("last_offset = 0x%0x\n%s", pay.last_offset,str);
|
||||
str = $sformatf("sc_route = 0x%0x\n%S", pay.sc_route,str);
|
||||
str = $sformatf("last = 0x%0x\n%s", pay.last,str);
|
||||
for (int i = 0; i < T_SC_WDATA_WIDTH/8;i++) begin
|
||||
data = $sformatf("%0x%s", pay.bytes[i].userdata, data);
|
||||
strb = $sformatf("%0x%s", pay.bytes[i].strb, strb);
|
||||
end
|
||||
str = $sformatf("WPAYLD\n%sdata:%s\nstrb:%d\n",str,data,strb);
|
||||
return (str);
|
||||
endfunction : sprint_sc_wpayld
|
||||
|
||||
function string sprint_sc_rpayld(
|
||||
input t_sc_rpayld pay
|
||||
);
|
||||
string str;
|
||||
string data;
|
||||
str = "";
|
||||
data = "";
|
||||
str = $sformatf("first_offset = 0x%0x\n%s", pay.first_offset,str);
|
||||
str = $sformatf("last_offset = 0x%0x\n%s", pay.last_offset,str);
|
||||
str = $sformatf("sc_route = 0x%0x\n%S", pay.sc_route,str);
|
||||
str = $sformatf("id = 0x%0x\n%s", pay.id,str);
|
||||
str = $sformatf("resp = 0x%0x\n%s", pay.resp,str);
|
||||
str = $sformatf("last = 0x%0x\n%s", pay.last,str);
|
||||
for (int i = 0; i < T_SC_RDATA_WIDTH/8;i++) begin
|
||||
data = $sformatf("%0x%s", pay.bytes[i].userdata, data);
|
||||
end
|
||||
str = $sformatf("RPAYLD\n%sdata:%s\n",str,data);
|
||||
return (str);
|
||||
endfunction : sprint_sc_rpayld
|
||||
|
||||
function string sprint_sc_bpayld(
|
||||
input t_sc_bpayld pay
|
||||
);
|
||||
string str;
|
||||
str = "";
|
||||
str = $sformatf("user = 0x%0x\n%s", pay.user,str);
|
||||
str = $sformatf("sc_route = 0x%0x\n%s", pay.sc_route,str);
|
||||
str = $sformatf("id = 0x%0x\n%s", pay.id,str);
|
||||
str = $sformatf("resp = 0x%0x\n%s", pay.resp,str);
|
||||
str = $sformatf("BPAYLD\n%s",str);
|
||||
return (str);
|
||||
endfunction : sprint_sc_bpayld
|
||||
`endif
|
||||
//synthesis translate_on
|
||||
|
||||
|
||||
typedef struct packed {
|
||||
t_axi_cache cache;
|
||||
t_axi_qos qos;
|
||||
t_axi_prot prot;
|
||||
t_axi_lock lock;
|
||||
t_axi_len len;
|
||||
t_sc_addr addr;
|
||||
t_sc_id id;
|
||||
t_axi_size size;
|
||||
t_axi_burst burst;
|
||||
t_sc_awuser user;
|
||||
} t_sc_awvector;
|
||||
|
||||
typedef struct packed {
|
||||
t_axi_cache cache;
|
||||
t_axi_qos qos;
|
||||
t_axi_prot prot;
|
||||
t_axi_lock lock;
|
||||
t_axi_len len;
|
||||
t_sc_addr addr;
|
||||
t_sc_id id;
|
||||
t_axi_size size;
|
||||
t_axi_burst burst;
|
||||
t_sc_aruser user;
|
||||
} t_sc_arvector;
|
||||
|
||||
typedef struct packed {
|
||||
t_sc_wstrb strb;
|
||||
t_sc_wdata data;
|
||||
t_axi_last last;
|
||||
t_sc_wuser user;
|
||||
} t_sc_wvector;
|
||||
|
||||
typedef struct packed {
|
||||
t_sc_rdata data;
|
||||
t_axi_last last;
|
||||
t_axi_resp resp;
|
||||
t_sc_id id;
|
||||
t_sc_ruser user;
|
||||
} t_sc_rvector;
|
||||
|
||||
|
||||
typedef struct packed {
|
||||
t_axi_resp resp;
|
||||
t_sc_id id;
|
||||
t_sc_buser user;
|
||||
} t_sc_bvector;
|
||||
+80
@@ -0,0 +1,80 @@
|
||||
`timescale 1ns / 1ps
|
||||
/*
|
||||
-------------------------------------------------------------------------------
|
||||
-- $Id: util_vector_logic.v 2.0 2017/01/01
|
||||
-------------------------------------------------------------------------------
|
||||
--
|
||||
-- ***************************************************************************
|
||||
-- ** Copyright(C) 2017 by Xilinx, Inc. All rights reserved. **
|
||||
-- ** **
|
||||
-- ** This text contains proprietary, confidential **
|
||||
-- ** information of Xilinx, Inc. , is distributed by **
|
||||
-- ** under license from Xilinx, Inc., and may be used, **
|
||||
-- ** copied and/or disclosed only pursuant to the terms **
|
||||
-- ** of a valid license agreement with Xilinx, Inc. **
|
||||
-- ** **
|
||||
-- ** Unmodified source code is guaranteed to place and route, **
|
||||
-- ** function and run at speed according to the datasheet **
|
||||
-- ** specification. Source code is provided "as-is", with no **
|
||||
-- ** obligation on the part of Xilinx to provide support. **
|
||||
-- ** **
|
||||
-- ** Xilinx Hotline support of source code IP shall only include **
|
||||
-- ** standard level Xilinx Hotline support, and will only address **
|
||||
-- ** issues and questions related to the standard released Netlist **
|
||||
-- ** version of the core (and thus indirectly, the original core source). **
|
||||
-- ** **
|
||||
-- ** The Xilinx Support Hotline does not have access to source **
|
||||
-- ** code and therefore cannot answer specific questions related **
|
||||
-- ** to source HDL. The Xilinx Support Hotline will only be able **
|
||||
-- ** to confirm the problem in the Netlist version of the core. **
|
||||
-- ** **
|
||||
-- ** This copyright and support notice must be retained as part **
|
||||
-- ** of this text at all times. **
|
||||
-- ***************************************************************************
|
||||
--
|
||||
-------------------------------------------------------------------------------
|
||||
-- Filename: util_vector_logic.v
|
||||
--
|
||||
-- Description:
|
||||
--
|
||||
-- Verilog-Standard:
|
||||
-------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
|
||||
module util_vector_logic_v2_0_1_util_vector_logic ( Op1, Op2, Res);
|
||||
|
||||
parameter C_OPERATION = "and";
|
||||
parameter integer C_SIZE = 8;
|
||||
|
||||
input [C_SIZE - 1:0] Op1;
|
||||
input [C_SIZE - 1:0] Op2;
|
||||
output [C_SIZE - 1:0] Res;
|
||||
|
||||
//wire [C_SIZE - 1:0] Res;
|
||||
//parameter C_Oper = C_OPERATION;
|
||||
|
||||
generate if (C_OPERATION == "and") begin: GEN_AND_OP
|
||||
assign Res = Op1 & Op2;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (C_OPERATION == "or") begin: GEN_OR_OP
|
||||
assign Res = Op1 | Op2;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (C_OPERATION == "xor") begin: GEN_XOR_OP
|
||||
assign Res = Op1 ^ Op2;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (C_OPERATION == "not") begin: GEN_NOT_OP
|
||||
assign Res = ~Op1;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule // module util_vector_logic
|
||||
|
||||
|
||||
|
||||
+31
@@ -0,0 +1,31 @@
|
||||
//------------------------------------------------------------------------
|
||||
//--
|
||||
//-- Filename : xlconstant.v
|
||||
//--
|
||||
//-- Date : 06/05/12
|
||||
//--
|
||||
//-- Description : VERILOG description of a constant block. This
|
||||
//-- block does not use a core.
|
||||
//--
|
||||
//------------------------------------------------------------------------
|
||||
|
||||
|
||||
//------------------------------------------------------------------------
|
||||
//--
|
||||
//-- Module : xlconstant
|
||||
//--
|
||||
//-- Architecture : behavior
|
||||
//--
|
||||
//-- Description : Top level VERILOG description of constant block
|
||||
//--
|
||||
//------------------------------------------------------------------------
|
||||
`timescale 1ps/1ps
|
||||
module xlconstant_v1_1_6_xlconstant (dout);
|
||||
parameter CONST_VAL = 1;
|
||||
parameter CONST_WIDTH = 1;
|
||||
output [CONST_WIDTH-1:0] dout;
|
||||
|
||||
assign dout = CONST_VAL;
|
||||
endmodule
|
||||
|
||||
|
||||
+348
@@ -0,0 +1,348 @@
|
||||
`pragma protect begin_protected
|
||||
`pragma protect version = 1
|
||||
`pragma protect encrypt_agent = "XILINX"
|
||||
`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2019.1"
|
||||
`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
|
||||
`pragma protect key_block
|
||||
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|
||||
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|
||||
|
||||
`pragma protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-2", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
|
||||
`pragma protect key_block
|
||||
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||||
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|
||||
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|
||||
|
||||
`pragma protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
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||||
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||||
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||||
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||||
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||||
|
||||
`pragma protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
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||||
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||||
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||||
|
||||
`pragma protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2019_02", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
|
||||
`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
|
||||
`pragma protect key_block
|
||||
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||||
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|
||||
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|
||||
|
||||
`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-2", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
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||||
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||||
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||||
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||||
a8ujlKdosw9/kOA5tJwaGV5Ewja1MaiwpG/loA==
|
||||
|
||||
`pragma protect data_method = "AES128-CBC"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 16160)
|
||||
`pragma protect data_block
|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
`pragma protect end_protected
|
||||
+3702
File diff suppressed because it is too large
Load Diff
+1646
File diff suppressed because it is too large
Load Diff
+842
@@ -0,0 +1,842 @@
|
||||
/*****************************************************************************
|
||||
* File : processing_system7_vip_v1_0_7_apis.v
|
||||
*
|
||||
* Date : 2012-11
|
||||
*
|
||||
* Description : Set of Zynq VIP APIs that are used for writing tests.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
/* API for setting the STOP_ON_ERROR*/
|
||||
task automatic set_stop_on_error;
|
||||
input LEVEL;
|
||||
begin
|
||||
$display("[%0d] : %0s : Setting Stop On Error as %0b",$time, DISP_INFO, LEVEL);
|
||||
STOP_ON_ERROR = LEVEL;
|
||||
// M_AXI_GP0.master.set_stop_on_error(LEVEL);
|
||||
// M_AXI_GP1.master.set_stop_on_error(LEVEL);
|
||||
// S_AXI_GP0.slave.set_stop_on_error(LEVEL);
|
||||
// S_AXI_GP1.slave.set_stop_on_error(LEVEL);
|
||||
// S_AXI_HP0.slave.set_stop_on_error(LEVEL);
|
||||
// S_AXI_HP1.slave.set_stop_on_error(LEVEL);
|
||||
// S_AXI_HP2.slave.set_stop_on_error(LEVEL);
|
||||
// S_AXI_HP3.slave.set_stop_on_error(LEVEL);
|
||||
// S_AXI_ACP.slave.set_stop_on_error(LEVEL);
|
||||
M_AXI_GP0.STOP_ON_ERROR = LEVEL;
|
||||
M_AXI_GP1.STOP_ON_ERROR = LEVEL;
|
||||
S_AXI_GP0.STOP_ON_ERROR = LEVEL;
|
||||
S_AXI_GP1.STOP_ON_ERROR = LEVEL;
|
||||
S_AXI_HP0.STOP_ON_ERROR = LEVEL;
|
||||
S_AXI_HP1.STOP_ON_ERROR = LEVEL;
|
||||
S_AXI_HP2.STOP_ON_ERROR = LEVEL;
|
||||
S_AXI_HP3.STOP_ON_ERROR = LEVEL;
|
||||
S_AXI_ACP.STOP_ON_ERROR = LEVEL;
|
||||
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API for setting the verbosity for channel level info*/
|
||||
task automatic set_channel_level_info;
|
||||
input [1023:0] name;
|
||||
input LEVEL;
|
||||
begin
|
||||
$display("[%0d] : [%0s] : %0s Port/s : Setting Channel Level Info as %0b",$time, DISP_INFO, name , LEVEL);
|
||||
case(name)
|
||||
// "M_AXI_GP0" : M_AXI_GP0.master.set_channel_level_info(LEVEL);
|
||||
// "M_AXI_GP1" : M_AXI_GP1.master.set_channel_level_info(LEVEL);
|
||||
// "S_AXI_GP0" : S_AXI_GP0.slave.set_channel_level_info(LEVEL);
|
||||
// "S_AXI_GP1" : S_AXI_GP1.slave.set_channel_level_info(LEVEL);
|
||||
// "S_AXI_HP0" : S_AXI_HP0.slave.set_channel_level_info(LEVEL);
|
||||
// "S_AXI_HP1" : S_AXI_HP1.slave.set_channel_level_info(LEVEL);
|
||||
// "S_AXI_HP2" : S_AXI_HP2.slave.set_channel_level_info(LEVEL);
|
||||
// "S_AXI_HP3" : S_AXI_HP3.slave.set_channel_level_info(LEVEL);
|
||||
// "S_AXI_ACP" : S_AXI_ACP.slave.set_channel_level_info(LEVEL);
|
||||
"ALL" : begin
|
||||
// M_AXI_GP0.master.set_channel_level_info(LEVEL);
|
||||
// M_AXI_GP1.master.set_channel_level_info(LEVEL);
|
||||
// S_AXI_GP0.slave.set_channel_level_info(LEVEL);
|
||||
// S_AXI_GP1.slave.set_channel_level_info(LEVEL);
|
||||
// S_AXI_HP0.slave.set_channel_level_info(LEVEL);
|
||||
// S_AXI_HP1.slave.set_channel_level_info(LEVEL);
|
||||
// S_AXI_HP2.slave.set_channel_level_info(LEVEL);
|
||||
// S_AXI_HP3.slave.set_channel_level_info(LEVEL);
|
||||
// S_AXI_ACP.slave.set_channel_level_info(LEVEL);
|
||||
end
|
||||
default : $display("[%0d] : %0s : Invalid Port name (%0s)",$time, DISP_ERR, name);
|
||||
endcase
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API for setting the verbosity for function level info*/
|
||||
task automatic set_function_level_info;
|
||||
input [1023:0] name;
|
||||
input LEVEL;
|
||||
begin
|
||||
$display("[%0d] : [%0s] : %0s Port/s : Setting Function Level Info as %0b",$time, DISP_INFO, name , LEVEL);
|
||||
case(name)
|
||||
// "M_AXI_GP0" : M_AXI_GP0.master.set_function_level_info(LEVEL);
|
||||
// "M_AXI_GP1" : M_AXI_GP1.master.set_function_level_info(LEVEL);
|
||||
// "S_AXI_GP0" : S_AXI_GP0.slave.set_function_level_info(LEVEL);
|
||||
// "S_AXI_GP1" : S_AXI_GP1.slave.set_function_level_info(LEVEL);
|
||||
// "S_AXI_HP0" : S_AXI_HP0.slave.set_function_level_info(LEVEL);
|
||||
// "S_AXI_HP1" : S_AXI_HP1.slave.set_function_level_info(LEVEL);
|
||||
// "S_AXI_HP2" : S_AXI_HP2.slave.set_function_level_info(LEVEL);
|
||||
// "S_AXI_HP3" : S_AXI_HP3.slave.set_function_level_info(LEVEL);
|
||||
// "S_AXI_ACP" : S_AXI_ACP.slave.set_function_level_info(LEVEL);
|
||||
"ALL" : begin
|
||||
// M_AXI_GP0.master.set_function_level_info(LEVEL);
|
||||
// M_AXI_GP1.master.set_function_level_info(LEVEL);
|
||||
// S_AXI_GP0.slave.set_function_level_info(LEVEL);
|
||||
// S_AXI_GP1.slave.set_function_level_info(LEVEL);
|
||||
// S_AXI_HP0.slave.set_function_level_info(LEVEL);
|
||||
// S_AXI_HP1.slave.set_function_level_info(LEVEL);
|
||||
// S_AXI_HP2.slave.set_function_level_info(LEVEL);
|
||||
// S_AXI_HP3.slave.set_function_level_info(LEVEL);
|
||||
// S_AXI_ACP.slave.set_function_level_info(LEVEL);
|
||||
end
|
||||
default : $display("[%0d] : %0s : Invalid Port name (%0s)",$time, DISP_ERR, name);
|
||||
endcase
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API for setting the Message verbosity */
|
||||
task automatic set_debug_level_info;
|
||||
input LEVEL;
|
||||
begin
|
||||
$display("[%0d] : %0s : Setting Debug Level Info as %0b",$time, DISP_INFO, LEVEL);
|
||||
DEBUG_INFO = LEVEL;
|
||||
M_AXI_GP0.DEBUG_INFO = LEVEL;
|
||||
M_AXI_GP1.DEBUG_INFO = LEVEL;
|
||||
S_AXI_GP0.DEBUG_INFO = LEVEL;
|
||||
S_AXI_GP1.DEBUG_INFO = LEVEL;
|
||||
S_AXI_HP0.DEBUG_INFO = LEVEL;
|
||||
S_AXI_HP1.DEBUG_INFO = LEVEL;
|
||||
S_AXI_HP2.DEBUG_INFO = LEVEL;
|
||||
S_AXI_HP3.DEBUG_INFO = LEVEL;
|
||||
S_AXI_ACP.DEBUG_INFO = LEVEL;
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API for setting ARQos Values */
|
||||
task automatic set_arqos;
|
||||
input [1023:0] name;
|
||||
input [axi_qos_width-1:0] value;
|
||||
begin
|
||||
$display("[%0d] : [%0s] : %0s Port/s : Setting AWQOS as %0b",$time, DISP_INFO, name , value);
|
||||
case(name)
|
||||
"S_AXI_GP0" : S_AXI_GP0.set_arqos(value);
|
||||
"S_AXI_GP1" : S_AXI_GP1.set_arqos(value);
|
||||
"S_AXI_HP0" : S_AXI_HP0.set_arqos(value);
|
||||
"S_AXI_HP1" : S_AXI_HP1.set_arqos(value);
|
||||
"S_AXI_HP2" : S_AXI_HP2.set_arqos(value);
|
||||
"S_AXI_HP3" : S_AXI_HP3.set_arqos(value);
|
||||
"S_AXI_ACP" : S_AXI_ACP.set_arqos(value);
|
||||
default : $display("[%0d] : %0s : Invalid Slave Port name (%0s)",$time, DISP_ERR, name);
|
||||
endcase
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API for setting AWQos Values */
|
||||
task automatic set_awqos;
|
||||
input [1023:0] name;
|
||||
input [axi_qos_width-1:0] value;
|
||||
begin
|
||||
$display("[%0d] : [%0s] : %0s Port/s : Setting ARQOS as %0b",$time, DISP_INFO, name , value);
|
||||
case(name)
|
||||
"S_AXI_GP0" : S_AXI_GP0.set_awqos(value);
|
||||
"S_AXI_GP1" : S_AXI_GP1.set_awqos(value);
|
||||
"S_AXI_HP0" : S_AXI_HP0.set_awqos(value);
|
||||
"S_AXI_HP1" : S_AXI_HP1.set_awqos(value);
|
||||
"S_AXI_HP2" : S_AXI_HP2.set_awqos(value);
|
||||
"S_AXI_HP3" : S_AXI_HP3.set_awqos(value);
|
||||
"S_AXI_ACP" : S_AXI_ACP.set_awqos(value);
|
||||
default : $display("[%0d] : %0s : Invalid Slave Port (%0s)",$time, DISP_ERR, name);
|
||||
endcase
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API for soft reset control */
|
||||
task automatic fpga_soft_reset;
|
||||
input[data_width-1:0] reset_ctrl;
|
||||
begin
|
||||
if(DEBUG_INFO) $display("[%0d] : %0s : FPGA Soft Reset called for 0x%0h",$time, DISP_INFO, reset_ctrl);
|
||||
gen_rst.fpga_soft_reset(reset_ctrl);
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API for por and strb reset control */
|
||||
// task automatic por_srstb_reset;
|
||||
// input por_reset_ctrl;
|
||||
// begin
|
||||
// if(DEBUG_INFO) $display("[%0d] : %0s : POR and STRB Reset called for 0x%0h",$time, DISP_INFO, por_reset_ctrl);
|
||||
// // gen_rst.por_srstb_reset(por_reset_ctrl);
|
||||
// gen_rst.por_srstb_reset(por_reset_ctrl);
|
||||
//
|
||||
// end
|
||||
// endtask
|
||||
|
||||
/* API for pre-loading memories from (DDR/OCM model) */
|
||||
task automatic pre_load_mem_from_file;
|
||||
input [(max_chars*8)-1:0] file_name;
|
||||
input [addr_width-1:0] start_addr;
|
||||
input [int_width-1:0] no_of_bytes;
|
||||
reg [1:0] mem_type;
|
||||
integer succ;
|
||||
begin
|
||||
mem_type = decode_address(start_addr);
|
||||
succ = $fopen(file_name,"r");
|
||||
if(succ == 0) begin
|
||||
$display("[%0d] : %0s : '%0s' doesn't exist. 'pre_load_mem_from_file' call failed ...\n",$time, DISP_ERR, file_name);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end
|
||||
else if(check_addr_aligned(start_addr)) begin
|
||||
case(mem_type)
|
||||
OCM_MEM : begin
|
||||
if (!C_HIGH_OCM_EN)
|
||||
ocmc.ocm.pre_load_mem_from_file(file_name,start_addr,no_of_bytes);
|
||||
else
|
||||
ocmc.ocm.pre_load_mem_from_file(file_name,(start_addr - high_ocm_start_addr),no_of_bytes);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : %0s : Starting Address(0x%0h) -> OCM Memory is pre-loaded with %0d bytes of data from file %0s",$time, DISP_INFO, start_addr, no_of_bytes, file_name);
|
||||
end
|
||||
DDR_MEM : begin
|
||||
ddrc.ddr.pre_load_mem_from_file(file_name,start_addr,no_of_bytes);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : %0s : Starting Address(0x%0h) -> DDR Memory is pre-loaded with %0d bytes of data from file %0s",$time, DISP_INFO, start_addr, no_of_bytes, file_name);
|
||||
end
|
||||
default : begin
|
||||
$display("[%0d] : %0s : Address(0x%0h) is out-of-range. 'pre_load_mem_from_file' call failed ...\n",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end
|
||||
endcase
|
||||
end else begin
|
||||
$display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'pre_load_mem_from_file' call failed ...",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR)
|
||||
$stop;
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API for pre-loading memories (DDR/OCM) */
|
||||
task automatic pre_load_mem;
|
||||
input [1:0] data_type;
|
||||
input [addr_width-1:0] start_addr;
|
||||
input [int_width-1:0] no_of_bytes;
|
||||
reg [1:0] mem_type;
|
||||
begin
|
||||
mem_type = decode_address(start_addr);
|
||||
if(check_addr_aligned(start_addr)) begin
|
||||
case(mem_type)
|
||||
OCM_MEM : begin
|
||||
if (!C_HIGH_OCM_EN)
|
||||
ocmc.ocm.pre_load_mem(data_type,start_addr,no_of_bytes);
|
||||
else
|
||||
ocmc.ocm.pre_load_mem(data_type,(start_addr - high_ocm_start_addr),no_of_bytes);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : %0s : Starting Address(0x%0h) -> OCM Memory is pre-loaded with %0d bytes of data",$time, DISP_INFO, start_addr, no_of_bytes);
|
||||
end
|
||||
DDR_MEM : begin
|
||||
ddrc.ddr.pre_load_mem(data_type,start_addr,no_of_bytes);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : %0s : Starting Address(0x%0h) -> DDR Memory is pre-loaded with %0d bytes of data",$time, DISP_INFO, start_addr, no_of_bytes);
|
||||
end
|
||||
default : begin
|
||||
$display("[%0d] : %0s : Address(0x%0h) is out-of-range. 'pre_load_mem' call failed ...\n",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end
|
||||
endcase
|
||||
end else begin
|
||||
$display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'pre_load_mem' call failed ...",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API for backdoor write to memories (DDR/OCM) */
|
||||
task automatic write_mem;
|
||||
input [max_burst_bits-1 :0] data;
|
||||
input [addr_width-1:0] start_addr;
|
||||
input [max_burst_bytes_width:0] no_of_bytes;
|
||||
reg [1:0] mem_type;
|
||||
integer succ;
|
||||
begin
|
||||
mem_type = decode_address(start_addr);
|
||||
if(check_addr_aligned(start_addr)) begin
|
||||
case(mem_type)
|
||||
OCM_MEM : begin
|
||||
if (!C_HIGH_OCM_EN)
|
||||
ocmc.ocm.write_mem(data,start_addr,no_of_bytes,all_strb_valid);
|
||||
else
|
||||
ocmc.ocm.write_mem(data,(start_addr - high_ocm_start_addr),no_of_bytes,all_strb_valid);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : %0s : Starting Address(0x%0h) -> Write %0d bytes of data to OCM Memory",$time, DISP_INFO, start_addr, no_of_bytes);
|
||||
end
|
||||
DDR_MEM : begin
|
||||
ddrc.ddr.write_mem(data,start_addr,no_of_bytes,all_strb_valid);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : %0s : Starting Address(0x%0h) -> Write %0d bytes of data to DDR Memory",$time, DISP_INFO, start_addr, no_of_bytes);
|
||||
end
|
||||
default : begin
|
||||
$display("[%0d] : %0s : Address(0x%0h) is out-of-range. 'write_mem' call failed ...\n",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end
|
||||
endcase
|
||||
end else begin
|
||||
$display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'write_mem' call failed ...",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR)
|
||||
$stop;
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
/* read_memory */
|
||||
task automatic read_mem;
|
||||
input [addr_width-1:0] start_addr;
|
||||
input [max_burst_bytes_width :0] no_of_bytes;
|
||||
output[max_burst_bits-1 :0] data;
|
||||
reg [1:0] mem_type;
|
||||
integer succ;
|
||||
begin
|
||||
mem_type = decode_address(start_addr);
|
||||
if(check_addr_aligned(start_addr)) begin
|
||||
case(mem_type)
|
||||
OCM_MEM : begin
|
||||
if (!C_HIGH_OCM_EN)
|
||||
ocmc.ocm.read_mem(data,start_addr,no_of_bytes);
|
||||
else
|
||||
ocmc.ocm.read_mem(data,(start_addr - high_ocm_start_addr),no_of_bytes);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : %0s : Starting Address(0x%0h) -> Read %0d bytes of data from OCM Memory ",$time, DISP_INFO, start_addr, no_of_bytes);
|
||||
end
|
||||
DDR_MEM : begin
|
||||
ddrc.ddr.read_mem(data,start_addr,no_of_bytes);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : %0s : Starting Address(0x%0h) -> Read %0d bytes of data from DDR Memory",$time, DISP_INFO, start_addr, no_of_bytes);
|
||||
end
|
||||
default : begin
|
||||
$display("[%0d] : %0s : Address(0x%0h) is out-of-range. 'read_mem' call failed ...\n",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end
|
||||
endcase
|
||||
end else begin
|
||||
$display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'read_mem' call failed ...",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR)
|
||||
$stop;
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API for backdoor read to memories (DDR/OCM) */
|
||||
task automatic peek_mem_to_file;
|
||||
input [(max_chars*8)-1:0] file_name;
|
||||
input [addr_width-1:0] start_addr;
|
||||
input [int_width-1:0] no_of_bytes;
|
||||
reg [1:0] mem_type;
|
||||
integer succ;
|
||||
begin
|
||||
mem_type = decode_address(start_addr);
|
||||
if(check_addr_aligned(start_addr)) begin
|
||||
case(mem_type)
|
||||
OCM_MEM : begin
|
||||
if (!C_HIGH_OCM_EN)
|
||||
ocmc.ocm.peek_mem_to_file(file_name,start_addr,no_of_bytes);
|
||||
else
|
||||
ocmc.ocm.peek_mem_to_file(file_name,(start_addr - high_ocm_start_addr),no_of_bytes);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : %0s : Starting Address(0x%0h) -> Peeked %0d bytes of data from OCM Memory to file %0s",$time, DISP_INFO, start_addr, no_of_bytes, file_name);
|
||||
end
|
||||
DDR_MEM : begin
|
||||
ddrc.ddr.peek_mem_to_file(file_name,start_addr,no_of_bytes);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : %0s : Starting Address(0x%0h) -> Peeked %0d bytes of data from DDR Memory to file %0s",$time, DISP_INFO, start_addr, no_of_bytes, file_name);
|
||||
end
|
||||
default : begin
|
||||
$display("[%0d] : %0s : Address(0x%0h) is out-of-range. 'peek_mem_to_file' call failed ...\n",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end
|
||||
endcase
|
||||
end else begin
|
||||
$display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'peek_mem_to_file' call failed ...",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR)
|
||||
$stop;
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API to read interrupt status */
|
||||
task automatic read_interrupt;
|
||||
output[irq_width-1:0] irq_status;
|
||||
begin
|
||||
irq_status = IRQ_F2P;
|
||||
if(DEBUG_INFO) $display("[%0d] : %0s : Reading Interrupt Status as 0x%0h",$time, DISP_INFO, irq_status);
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API to wait on interrup */
|
||||
task automatic wait_interrupt;
|
||||
input [3:0] irq;
|
||||
output[irq_width-1:0] irq_status;
|
||||
begin
|
||||
if(DEBUG_INFO) $display("[%0d] : %0s : Waiting on Interrupt irq[%0d]",$time, DISP_INFO, irq);
|
||||
|
||||
case(irq)
|
||||
0 : wait(IRQ_F2P[0] === 1'b1);
|
||||
1 : wait(IRQ_F2P[1] === 1'b1);
|
||||
2 : wait(IRQ_F2P[2] === 1'b1);
|
||||
3 : wait(IRQ_F2P[3] === 1'b1);
|
||||
4 : wait(IRQ_F2P[4] === 1'b1);
|
||||
5 : wait(IRQ_F2P[5] === 1'b1);
|
||||
6 : wait(IRQ_F2P[6] === 1'b1);
|
||||
7 : wait(IRQ_F2P[7] === 1'b1);
|
||||
8 : wait(IRQ_F2P[8] === 1'b1);
|
||||
9 : wait(IRQ_F2P[9] === 1'b1);
|
||||
10: wait(IRQ_F2P[10] === 1'b1);
|
||||
11: wait(IRQ_F2P[11] === 1'b1);
|
||||
12: wait(IRQ_F2P[12] === 1'b1);
|
||||
13: wait(IRQ_F2P[13] === 1'b1);
|
||||
14: wait(IRQ_F2P[14] === 1'b1);
|
||||
15: wait(IRQ_F2P[15] === 1'b1);
|
||||
default : $display("[%0d] : %0s : Only 16 Interrupt lines (irq_fp0:irq_fp15) are supported",$time, DISP_ERR);
|
||||
endcase
|
||||
if(DEBUG_INFO) $display("[%0d] : %0s : Received Interrupt irq[%0d]",$time, DISP_INFO, irq);
|
||||
irq_status = IRQ_F2P;
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API to wait for a certain match pattern*/
|
||||
task automatic wait_mem_update;
|
||||
input[addr_width-1:0] address;
|
||||
input[data_width-1:0] data_in;
|
||||
output[data_width-1:0] data_out;
|
||||
reg[data_width-1:0] datao;
|
||||
begin
|
||||
if(mem_update_key) begin
|
||||
mem_update_key = 0;
|
||||
if(DEBUG_INFO) $display("[%0d] : %0s : 'wait_mem_update' called for Address(0x%0h) , Match Pattern(0x%0h) \n",$time, DISP_INFO, address, data_in);
|
||||
if(check_addr_aligned(address)) begin
|
||||
ddrc.ddr.wait_mem_update(address, datao);
|
||||
if(datao != data_in)begin
|
||||
$display("[%0d] : %0s : Address(0x%0h) -> DATA PATTERN MATCH FAILED, Expected data = 0x%0h, Received data = 0x%0h \n",$time, DISP_ERR, address, data_in,datao);
|
||||
$stop;
|
||||
end else
|
||||
$display("[%0d] : %0s : Address(0x%0h) -> DATA PATTERN(0x%0h) MATCHED \n",$time, DISP_INFO, address, data_in);
|
||||
data_out = datao;
|
||||
end else begin
|
||||
$display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'wait_mem_update' call failed ...\n",$time, DISP_ERR, address);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end
|
||||
mem_update_key = 1;
|
||||
end else
|
||||
$display("[%0d] : %0s : One instance of 'wait_mem_update' thread is already running.Only one instance can be called at a time ...\n",$time, DISP_WARN);
|
||||
end
|
||||
endtask
|
||||
|
||||
|
||||
/* API to initiate a WRITE transaction on one of the AXI-Master ports*/
|
||||
task automatic write_from_file;
|
||||
input [(max_chars*8)-1:0] file_name;
|
||||
input [addr_width-1:0] start_addr;
|
||||
input [int_width-1:0] wr_size;
|
||||
output [axi_rsp_width-1:0] response;
|
||||
integer succ;
|
||||
begin
|
||||
succ = $fopen(file_name,"r");
|
||||
if(succ == 0) begin
|
||||
$display("[%0d] : %0s : '%0s' doesn't exist. 'write_from_file' call failed ...\n",$time, DISP_ERR, file_name);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end
|
||||
else if(!check_master_address(start_addr)) begin
|
||||
$display("[%0d] : %0s : Master Address(0x%0h) is out of range\n",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end else if(check_addr_aligned(start_addr)) begin
|
||||
$fclose(succ);
|
||||
// case(start_addr[31:30])
|
||||
if (start_addr[31:30] === 2'b01) begin
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes from file %0s",$time, DISP_INFO, start_addr, wr_size, file_name);
|
||||
M_AXI_GP0.write_from_file(file_name,start_addr,wr_size,response);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP0 : %0s : Done AXI Write for Starting Address(0x%0h)",$time, DISP_INFO, start_addr);
|
||||
end else if(start_addr[31:30] === 2'b10) begin
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes from file %0s",$time, DISP_INFO, start_addr, wr_size, file_name);
|
||||
M_AXI_GP1.write_from_file(file_name,start_addr,wr_size,response);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP1 : %0s : Done AXI Write for Starting Address(0x%0h)",$time, DISP_INFO, start_addr);
|
||||
end else begin
|
||||
$display("[%0d] : %0s : Invalid Address(0x%0h) 'write_from_file' call failed ...\n",$time, DISP_ERR, start_addr);
|
||||
end
|
||||
// endcase
|
||||
end else begin
|
||||
$display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'write_from_file' call failed ...\n",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API to initiate a READ transaction on one of the AXI-Master ports*/
|
||||
task automatic read_to_file;
|
||||
input [(max_chars*8)-1:0] file_name;
|
||||
input [addr_width-1:0] start_addr;
|
||||
input [int_width-1:0] rd_size;
|
||||
output [axi_rsp_width-1:0] response;
|
||||
begin
|
||||
if(!check_master_address(start_addr)) begin
|
||||
$display("[%0d] : %0s : Master Address(0x%0h) is out of range\n",$time, DISP_ERR , start_addr);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end else if(check_addr_aligned(start_addr)) begin
|
||||
// case(start_addr[31:30])
|
||||
if (start_addr[31:30] === 2'b01) begin
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Read -> %0d bytes to file %0s",$time, DISP_INFO, start_addr, rd_size, file_name);
|
||||
M_AXI_GP0.read_to_file(file_name,start_addr,rd_size,response);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP0 : %0s : Done AXI Read for Starting Address(0x%0h)",$time, DISP_INFO, start_addr);
|
||||
end else if(start_addr[31:30] === 2'b10) begin
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Read -> %0d bytes to file %0s",$time, DISP_INFO, start_addr, rd_size, file_name);
|
||||
M_AXI_GP1.read_to_file(file_name,start_addr,rd_size,response);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP1 : %0s : Done AXI Read for Starting Address(0x%0h)",$time, DISP_INFO, start_addr);
|
||||
// end
|
||||
// default : $display("[%0d] : %0s : Invalid Address(0x%0h) 'read_to_file' call failed ...\n",$time, DISP_ERR, start_addr);
|
||||
// endcase
|
||||
end else begin
|
||||
$display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'read_to_file' call failed ...\n",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API to initiate a WRITE transaction(<= 128 bytes) on one of the AXI-Master ports*/
|
||||
task automatic write_data;
|
||||
input [addr_width-1:0] start_addr;
|
||||
input [max_transfer_bytes_width:0] wr_size;
|
||||
input [(max_transfer_bytes*8)-1:0] w_data;
|
||||
output [axi_rsp_width-1:0] response;
|
||||
reg[511:0] rsp;
|
||||
begin
|
||||
if(!check_master_address(start_addr)) begin
|
||||
$display("[%0d] : %0s : Master Address(0x%0h) is out of range. 'write_data' call failed ...\n",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end else if(wr_size > max_transfer_bytes) begin
|
||||
$display("[%0d] : %0s : Byte Size supported is 128 bytes only. 'write_data' call failed ...\n",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end else if(start_addr[31:30] === GP_M0) begin
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO, start_addr, wr_size);
|
||||
M_AXI_GP0.write_data(start_addr,wr_size,w_data,response);
|
||||
rsp = get_resp(response);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP0 : %0s : Done AXI Write for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp);
|
||||
end else if(start_addr[31:30] === GP_M1) begin
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO, start_addr, wr_size);
|
||||
M_AXI_GP1.write_data(start_addr,wr_size,w_data,response);
|
||||
rsp = get_resp(response);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP1 : %0s : Done AXI Write for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp);
|
||||
end else
|
||||
$display("[%0d] : %0s : Invalid Address(0x%0h) 'write_data' call failed ...\n",$time, DISP_ERR, start_addr);
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API to initiate a READ transaction(<= 128 bytes) on one of the AXI-Master ports*/
|
||||
task automatic read_data;
|
||||
input [addr_width-1:0] start_addr;
|
||||
input [max_transfer_bytes_width:0] rd_size;
|
||||
output[(max_transfer_bytes*8)-1:0] rd_data;
|
||||
output [axi_rsp_width-1:0] response;
|
||||
reg[511:0] rsp;
|
||||
begin
|
||||
if(!check_master_address(start_addr)) begin
|
||||
$display("[%0d] : %0s : Master Address(0x%0h) is out of range 'read_data' call failed ...\n",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end else if(rd_size > max_transfer_bytes) begin
|
||||
$display("[%0d] : %0s : Byte Size supported is 128 bytes only.'read_data' call failed ... \n",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end else if(start_addr[31:30] === GP_M0) begin
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Read -> %0d bytes",$time, DISP_INFO, start_addr, rd_size);
|
||||
M_AXI_GP0.read_data(start_addr,rd_size,rd_data,response);
|
||||
rsp = get_resp(response);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP0 : %0s : Done AXI Read for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp);
|
||||
end else if(start_addr[31:30] === GP_M1) begin
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Read -> %0d bytes",$time, DISP_INFO, start_addr, rd_size);
|
||||
M_AXI_GP1.read_data(start_addr,rd_size,rd_data,response);
|
||||
rsp = get_resp(response);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP1 : %0s : Done AXI Read for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp);
|
||||
end else
|
||||
$display("[%0d] : %0s : Invalid Address(0x%0h) 'read_data' call failed ...\n",$time, DISP_ERR, start_addr);
|
||||
end
|
||||
endtask
|
||||
|
||||
/* Hooks to call to VIP APIs */
|
||||
task automatic write_burst(input [addr_width-1:0] start_addr,input [axi_len_width-1:0] len,input [axi_size_width-1:0] siz,input [axi_brst_type_width-1:0] burst,input [axi_lock_width-1:0] lck,input [axi_cache_width-1:0] cache,input [axi_prot_width-1:0] prot,input [(axi_mgp_data_width*axi_burst_len)-1:0] data,input integer datasize, output [axi_rsp_width-1:0] response);
|
||||
reg[511:0] rsp;
|
||||
begin
|
||||
if(!check_master_address(start_addr)) begin
|
||||
$display("[%0d] : %0s : Master Address(0x%0h) is out of range. 'write_burst' call failed ...\n",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end else if(start_addr[31:30] === 2'b01) begin
|
||||
// end else if(start_addr[31:30] === GP_M0) begin
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO, start_addr, datasize);
|
||||
M_AXI_GP0.write_burst(start_addr,len,siz,burst,lck,cache,prot,data,datasize,response);
|
||||
rsp = get_resp(response);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP0 : %0s : Done AXI Write for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp);
|
||||
end else if(start_addr[31:30] === 2'b10) begin
|
||||
// end else if(start_addr[31:30] === GP_M1) begin
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO, start_addr, datasize);
|
||||
M_AXI_GP1.write_burst(start_addr,len,siz,burst,lck,cache,prot,data,datasize,response);
|
||||
rsp = get_resp(response);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP1 : %0s : Done AXI Write for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp);
|
||||
end else
|
||||
$display("[%0d] : %0s : Invalid Address(0x%0h) 'write_burst' call failed ... \n",$time, DISP_ERR, start_addr);
|
||||
end
|
||||
endtask
|
||||
|
||||
task automatic write_burst_concurrent(input [addr_width-1:0] start_addr,input [axi_len_width-1:0] len,input [axi_size_width-1:0] siz,input [axi_brst_type_width-1:0] burst,input [axi_lock_width-1:0] lck,input [axi_cache_width-1:0] cache,input [axi_prot_width-1:0] prot,input [(axi_mgp_data_width*axi_burst_len)-1:0] data,input integer datasize, output [axi_rsp_width-1:0] response);
|
||||
reg[511:0] rsp; /// string for response
|
||||
begin
|
||||
if(!check_master_address(start_addr)) begin
|
||||
$display("[%0d] : %0s : Master Address(0x%0h) is out of range. 'write_burst_concurrent' call failed ...\n",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end else if(start_addr[31:30] === 2'b01) begin
|
||||
// end else if(start_addr[31:30] === GP_M0) begin
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO, start_addr, datasize);
|
||||
M_AXI_GP0.write_burst_concurrent(start_addr,len,siz,burst,lck,cache,prot,data,datasize,response);
|
||||
rsp = get_resp(response);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP0 : %0s : Done AXI Write for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp);
|
||||
end else if(start_addr[31:30] === 2'b10) begin
|
||||
// end else if(start_addr[31:30] === GP_M1) begin
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Write -> %0d bytes",$time, DISP_INFO, start_addr, datasize);
|
||||
M_AXI_GP1.write_burst_concurrent(start_addr,len,siz,burst,lck,cache,prot,data,datasize,response);
|
||||
rsp = get_resp(response);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP1 : %0s : Done AXI Write for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp);
|
||||
end else
|
||||
$display("[%0d] : %0s : Invalid Address(0x%0h) 'write_burst_concurrent' call failed ... \n",$time, DISP_ERR, start_addr);
|
||||
end
|
||||
endtask
|
||||
|
||||
task automatic read_burst;
|
||||
input [addr_width-1:0] start_addr;
|
||||
input [axi_len_width-1:0] len;
|
||||
input [axi_size_width-1:0] siz;
|
||||
input [axi_brst_type_width-1:0] burst;
|
||||
input [axi_lock_width-1:0] lck;
|
||||
input [axi_cache_width-1:0] cache;
|
||||
input [axi_prot_width-1:0] prot;
|
||||
output [(axi_mgp_data_width*axi_burst_len)-1:0] data;
|
||||
output [(axi_rsp_width*axi_burst_len)-1:0] response;
|
||||
reg[511:0] rsp;
|
||||
begin
|
||||
if(!check_master_address(start_addr)) begin
|
||||
$display("[%0d] : %0s : Master Address(0x%0h) is out of range. 'read_burst' call failed ...\n",$time, DISP_ERR, start_addr);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end else if(start_addr[31:30] === 2'b01) begin
|
||||
// end else if(start_addr[31:30] === GP_M0) begin
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP0 : %0s : Starting Address(0x%0h) -> AXI Read",$time, DISP_INFO, start_addr);
|
||||
M_AXI_GP0.read_burst(start_addr,len,siz,burst,lck,cache,prot,data,response);
|
||||
rsp = get_resp(response);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP0 : %0s : Done AXI Read for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp);
|
||||
end else if(start_addr[31:30] === 2'b10) begin
|
||||
// end else if(start_addr[31:30] === GP_M1) begin
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP1 : %0s : Starting Address(0x%0h) -> AXI Read",$time, DISP_INFO, start_addr);
|
||||
M_AXI_GP1.read_burst(start_addr,len,siz,burst,lck,cache,prot,data,response);
|
||||
rsp = get_resp(response);
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP1 : %0s : Done AXI Read for Starting Address(0x%0h) with Response '%0s'",$time, DISP_INFO, start_addr, rsp);
|
||||
end else
|
||||
$display("[%0d] : %0s : Invalid Address(0x%0h) 'read_burst' call failed ... \n",$time, DISP_ERR, start_addr);
|
||||
end
|
||||
endtask
|
||||
|
||||
task automatic wait_reg_update;
|
||||
input [addr_width-1:0] addr;
|
||||
input [data_width-1:0] data_i;
|
||||
input [data_width-1:0] mask_i;
|
||||
input [int_width-1:0] time_interval;
|
||||
input [int_width-1:0] time_out;
|
||||
output [data_width-1:0] data_o;
|
||||
|
||||
reg upd_done0;
|
||||
reg upd_done1;
|
||||
begin
|
||||
if(!check_master_address(addr)) begin
|
||||
$display("[%0d] : %0s : Address(0x%0h) is out of range. 'wait_reg_update' call failed ...\n",$time, DISP_ERR, addr);
|
||||
if(STOP_ON_ERROR) $stop;
|
||||
end else if(addr[31:30] === 2'b01) begin
|
||||
// end else if(addr[31:30] === GP_M0) begin
|
||||
if(reg_update_key_0) begin
|
||||
reg_update_key_0 = 0;
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP0 : %0s : 'wait_reg_update' called for Address(0x%0h), Mask(0x%0h), Match Pattern(0x%0h) \n ",$time, DISP_INFO, addr, mask_i, data_i);
|
||||
M_AXI_GP0.wait_reg_update(addr, data_i, mask_i, time_interval, time_out, data_o, upd_done0);
|
||||
if(DEBUG_INFO && upd_done0)
|
||||
$display("[%0d] : M_AXI_GP0 : %0s : Register mapped at Address(0x%0h) is updated ",$time, DISP_INFO, addr);
|
||||
reg_update_key_0 = 1;
|
||||
end else
|
||||
$display("[%0d] : M_AXI_GP0 : One instance of 'wait_reg_update' thread is already running.Only one instance can be called at a time ...\n",$time, DISP_WARN);
|
||||
end else if(addr[31:30] === 2'b10) begin
|
||||
// end else if(addr[31:30] === GP_M1) begin
|
||||
if(reg_update_key_1) begin
|
||||
reg_update_key_1 = 0;
|
||||
if(DEBUG_INFO)
|
||||
$display("[%0d] : M_AXI_GP1 : %0s : 'wait_reg_update' called for Address(0x%0h), Mask(0x%0h), Match Pattern(0x%0h) \n ",$time, DISP_INFO, addr, mask_i, data_i);
|
||||
M_AXI_GP1.wait_reg_update(addr, data_i, mask_i, time_interval, time_out, data_o, upd_done1);
|
||||
if(DEBUG_INFO && upd_done1)
|
||||
$display("[%0d] : M_AXI_GP1 : %0s : Register mapped at Address(0x%0h) is updated ",$time, DISP_INFO, addr);
|
||||
reg_update_key_1 = 1;
|
||||
end else
|
||||
$display("[%0d] : M_AXI_GP1 : One instance of 'wait_reg_update' thread is already running.Only one instance can be called at a time ...\n",$time, DISP_WARN);
|
||||
end else
|
||||
$display("[%0d] : %0s : Invalid Address(0x%0h) 'wait_reg_update' call failed ... \n",$time, DISP_ERR, addr);
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API to read register map */
|
||||
task read_register_map;
|
||||
input [addr_width-1:0] start_addr;
|
||||
input [max_regs_width:0] no_of_registers;
|
||||
output[max_burst_bits-1 :0] data;
|
||||
reg [max_regs_width:0] no_of_regs;
|
||||
begin
|
||||
no_of_regs = no_of_registers;
|
||||
if(no_of_registers > 32) begin
|
||||
$display("[%0d] : %0s : No_of_Registers(%0d) exceeds the supported number (32).\n Only 32 registers will be read.",$time, DISP_ERR, start_addr);
|
||||
no_of_regs = 32;
|
||||
end
|
||||
if(check_addr_aligned(start_addr)) begin
|
||||
if(decode_address(start_addr) == REG_MEM) begin
|
||||
if(DEBUG_INFO) $display("[%0d] : %0s : Reading Registers starting address (0x%0h) -> %0d registers",$time, DISP_INFO, start_addr,no_of_regs );
|
||||
regc.regm.read_reg_mem(data,start_addr,no_of_regs*4); /// as each register is of 4 bytes
|
||||
if(DEBUG_INFO) $display("[%0d] : %0s : DONE -> Reading Registers starting address (0x%0h), Data returned(0x%0h)",$time, DISP_INFO, start_addr, data );
|
||||
end else begin
|
||||
$display("[%0d] : %0s : Invalid Address(0x%0h) for Register Read. 'read_register_map' call failed ...",$time, DISP_ERR, start_addr);
|
||||
end
|
||||
end else begin
|
||||
data = 0;
|
||||
$display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'read_register_map' call failed ...",$time, DISP_ERR, start_addr);
|
||||
end
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API to read single register */
|
||||
task read_register;
|
||||
input [addr_width-1:0] addr;
|
||||
output[data_width-1:0] data;
|
||||
begin
|
||||
if(check_addr_aligned(addr)) begin
|
||||
if(decode_address(addr) == REG_MEM) begin
|
||||
if(DEBUG_INFO) $display("[%0d] : %0s : Reading Register (0x%0h) ",$time, DISP_INFO, addr );
|
||||
regc.regm.get_data(addr >> 2, data);
|
||||
if(DEBUG_INFO) $display("[%0d] : %0s : DONE -> Reading Register (0x%0h), Data returned(0x%0h)",$time, DISP_INFO, addr, data );
|
||||
end else begin
|
||||
$display("[%0d] : %0s : Invalid Address(0x%0h) for Register Read. 'read_register' call failed ...",$time, DISP_ERR, addr);
|
||||
end
|
||||
end else begin
|
||||
data = 0;
|
||||
$display("[%0d] : %0s : Address(0x%0h) has to be 32-bit aligned. 'read_register' call failed ...",$time, DISP_ERR, addr);
|
||||
end
|
||||
|
||||
end
|
||||
endtask
|
||||
|
||||
/* API to set the AXI-Slave profile*/
|
||||
task automatic set_slave_profile;
|
||||
input[1023:0] name;
|
||||
input[1:0] latency ;
|
||||
begin
|
||||
if(DEBUG_INFO) $display("[%0d] : %0s : %0s Port/s : Setting Slave profile",$time, DISP_INFO, name);
|
||||
case(name)
|
||||
"S_AXI_GP0" : S_AXI_GP0.set_latency_type(latency);
|
||||
"S_AXI_GP1" : S_AXI_GP1.set_latency_type(latency);
|
||||
"S_AXI_HP0" : S_AXI_HP0.set_latency_type(latency);
|
||||
"S_AXI_HP1" : S_AXI_HP1.set_latency_type(latency);
|
||||
"S_AXI_HP2" : S_AXI_HP2.set_latency_type(latency);
|
||||
"S_AXI_HP3" : S_AXI_HP3.set_latency_type(latency);
|
||||
"S_AXI_ACP" : S_AXI_ACP.set_latency_type(latency);
|
||||
"ALL" : begin
|
||||
S_AXI_GP0.set_latency_type(latency);
|
||||
S_AXI_GP1.set_latency_type(latency);
|
||||
S_AXI_HP0.set_latency_type(latency);
|
||||
S_AXI_HP1.set_latency_type(latency);
|
||||
S_AXI_HP2.set_latency_type(latency);
|
||||
S_AXI_HP3.set_latency_type(latency);
|
||||
S_AXI_ACP.set_latency_type(latency);
|
||||
end
|
||||
endcase
|
||||
end
|
||||
endtask
|
||||
|
||||
|
||||
/*------------------------------ LOCAL APIs ------------------------------------------------ */
|
||||
|
||||
/* local API for address decoding*/
|
||||
function automatic [1:0] decode_address;
|
||||
input [addr_width-1:0] address;
|
||||
begin
|
||||
if(!C_HIGH_OCM_EN && (address < ocm_end_addr || address >= ocm_low_addr ))
|
||||
decode_address = OCM_MEM; /// OCM
|
||||
else if(address >= ddr_start_addr && address <= ddr_end_addr)
|
||||
decode_address = DDR_MEM; /// DDR
|
||||
else if(C_HIGH_OCM_EN && address >= high_ocm_start_addr)
|
||||
decode_address = OCM_MEM; /// OCM
|
||||
else if(address >= reg_start_addr && reg_start_addr <= reg_end_addr)
|
||||
decode_address = REG_MEM; /// Register Map
|
||||
else
|
||||
decode_address = INVALID_MEM_TYPE; /// ERROR in Address
|
||||
end
|
||||
endfunction
|
||||
|
||||
/* local API for checking address is 32-bit (4-byte) aligned */
|
||||
function automatic check_addr_aligned;
|
||||
input [addr_width-1:0] address;
|
||||
begin
|
||||
if((address%4) !=0 ) begin //
|
||||
check_addr_aligned = 0; ///not_aligned
|
||||
end else
|
||||
check_addr_aligned = 1;
|
||||
end
|
||||
endfunction
|
||||
|
||||
/* local API to check address for GP Masters */
|
||||
function check_master_address;
|
||||
input [addr_width-1:0] address;
|
||||
begin
|
||||
if(address >= m_axi_gp0_baseaddr && address <= m_axi_gp0_highaddr)
|
||||
check_master_address = 1'b1;
|
||||
else if(address >= m_axi_gp1_baseaddr && address <= m_axi_gp1_highaddr)
|
||||
check_master_address = 1'b1;
|
||||
else
|
||||
check_master_address = 1'b0; /// ERROR in Address
|
||||
end
|
||||
endfunction
|
||||
|
||||
/* Response decode */
|
||||
function automatic [511:0] get_resp;
|
||||
input[axi_rsp_width-1:0] response;
|
||||
begin
|
||||
case(response)
|
||||
2'b00 : get_resp = "OKAY";
|
||||
2'b01 : get_resp = "EXOKAY";
|
||||
2'b10 : get_resp = "SLVERR";
|
||||
2'b11 : get_resp = "DECERR";
|
||||
endcase
|
||||
end
|
||||
endfunction
|
||||
+94
@@ -0,0 +1,94 @@
|
||||
/*****************************************************************************
|
||||
* File : processing_system7_vip_v1_0_7_axi_acp.v
|
||||
*
|
||||
* Date : 2012-11
|
||||
*
|
||||
* Description : Connections for ACP port
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
/* AXI Slave ACP */
|
||||
processing_system7_vip_v1_0_7_axi_slave_acp #( C_USE_S_AXI_ACP, // enable
|
||||
axi_acp_name, // name
|
||||
axi_acp_data_width, // data width
|
||||
addr_width, /// address width
|
||||
axi_acp_id_width, // ID width
|
||||
C_S_AXI_ACP_BASEADDR, // slave base address
|
||||
C_S_AXI_ACP_HIGHADDR,// slave size
|
||||
axi_acp_outstanding, // outstanding transactions // 7 Reads and 3 Writes
|
||||
axi_slv_excl_support, // Exclusive access support
|
||||
axi_acp_wr_outstanding,
|
||||
axi_acp_rd_outstanding)
|
||||
S_AXI_ACP(.S_RESETN (net_axi_acp_rstn),
|
||||
.S_ACLK (S_AXI_ACP_ACLK),
|
||||
// Write Address Channel
|
||||
.S_AWID (S_AXI_ACP_AWID),
|
||||
.S_AWADDR (S_AXI_ACP_AWADDR),
|
||||
.S_AWLEN (S_AXI_ACP_AWLEN),
|
||||
.S_AWSIZE (S_AXI_ACP_AWSIZE),
|
||||
.S_AWBURST (S_AXI_ACP_AWBURST),
|
||||
.S_AWLOCK (S_AXI_ACP_AWLOCK),
|
||||
.S_AWCACHE (S_AXI_ACP_AWCACHE),
|
||||
.S_AWPROT (S_AXI_ACP_AWPROT),
|
||||
.S_AWVALID (S_AXI_ACP_AWVALID),
|
||||
.S_AWREADY (S_AXI_ACP_AWREADY),
|
||||
// Write Data Channel Signals.
|
||||
.S_WID (S_AXI_ACP_WID),
|
||||
.S_WDATA (S_AXI_ACP_WDATA),
|
||||
.S_WSTRB (S_AXI_ACP_WSTRB),
|
||||
.S_WLAST (S_AXI_ACP_WLAST),
|
||||
.S_WVALID (S_AXI_ACP_WVALID),
|
||||
.S_WREADY (S_AXI_ACP_WREADY),
|
||||
// Write Response Channel Signals.
|
||||
.S_BID (S_AXI_ACP_BID),
|
||||
.S_BRESP (S_AXI_ACP_BRESP),
|
||||
.S_BVALID (S_AXI_ACP_BVALID),
|
||||
.S_BREADY (S_AXI_ACP_BREADY),
|
||||
// Read Address Channel Signals.
|
||||
.S_ARID (S_AXI_ACP_ARID),
|
||||
.S_ARADDR (S_AXI_ACP_ARADDR),
|
||||
.S_ARLEN (S_AXI_ACP_ARLEN),
|
||||
.S_ARSIZE (S_AXI_ACP_ARSIZE),
|
||||
.S_ARBURST (S_AXI_ACP_ARBURST),
|
||||
.S_ARLOCK (S_AXI_ACP_ARLOCK),
|
||||
.S_ARCACHE (S_AXI_ACP_ARCACHE),
|
||||
.S_ARPROT (S_AXI_ACP_ARPROT),
|
||||
.S_ARVALID (S_AXI_ACP_ARVALID),
|
||||
.S_ARREADY (S_AXI_ACP_ARREADY),
|
||||
// Read Data Channel Signals.
|
||||
.S_RID (S_AXI_ACP_RID),
|
||||
.S_RDATA (S_AXI_ACP_RDATA),
|
||||
.S_RRESP (S_AXI_ACP_RRESP),
|
||||
.S_RLAST (S_AXI_ACP_RLAST),
|
||||
.S_RVALID (S_AXI_ACP_RVALID),
|
||||
.S_RREADY (S_AXI_ACP_RREADY),
|
||||
// Side band signals
|
||||
.S_AWQOS (S_AXI_ACP_AWQOS),
|
||||
.S_ARQOS (S_AXI_ACP_ARQOS), // Side band signals
|
||||
|
||||
.SW_CLK (net_sw_clk),
|
||||
/* This goes to port 0 of DDR and port 0 of OCM , port 0 of REG*/
|
||||
.WR_DATA_ACK_DDR (ddr_wr_ack_port0),
|
||||
.WR_DATA_ACK_OCM (ocm_wr_ack_port0),
|
||||
.WR_DATA (net_wr_data_acp),
|
||||
.WR_DATA_STRB (net_wr_strb_acp),
|
||||
.WR_ADDR (net_wr_addr_acp),
|
||||
.WR_BYTES (net_wr_bytes_acp),
|
||||
.WR_DATA_VALID_DDR (ddr_wr_dv_port0),
|
||||
.WR_DATA_VALID_OCM (ocm_wr_dv_port0),
|
||||
.WR_QOS (net_wr_qos_acp),
|
||||
|
||||
.RD_REQ_DDR (ddr_rd_req_port0),
|
||||
.RD_REQ_OCM (ocm_rd_req_port0),
|
||||
.RD_REQ_REG (reg_rd_req_port0),
|
||||
.RD_ADDR (net_rd_addr_acp),
|
||||
.RD_DATA_DDR (ddr_rd_data_port0),
|
||||
.RD_DATA_OCM (ocm_rd_data_port0),
|
||||
.RD_DATA_REG (reg_rd_data_port0),
|
||||
.RD_BYTES (net_rd_bytes_acp),
|
||||
.RD_DATA_VALID_DDR (ddr_rd_dv_port0),
|
||||
.RD_DATA_VALID_OCM (ocm_rd_dv_port0),
|
||||
.RD_DATA_VALID_REG (reg_rd_dv_port0),
|
||||
.RD_QOS (net_rd_qos_acp)
|
||||
|
||||
);
|
||||
+311
@@ -0,0 +1,311 @@
|
||||
/*****************************************************************************
|
||||
* File : processing_system7_vip_v1_0_7_axi_gp.v
|
||||
*
|
||||
* Date : 2012-11
|
||||
*
|
||||
* Description : Connections for AXI GP ports
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
/* IDs for Masters
|
||||
// l2m1 (CPU000)
|
||||
12'b11_000_000_00_00
|
||||
12'b11_010_000_00_00
|
||||
12'b11_011_000_00_00
|
||||
12'b11_100_000_00_00
|
||||
12'b11_101_000_00_00
|
||||
12'b11_110_000_00_00
|
||||
12'b11_111_000_00_00
|
||||
// l2m1 (CPU001)
|
||||
12'b11_000_001_00_00
|
||||
12'b11_010_001_00_00
|
||||
12'b11_011_001_00_00
|
||||
12'b11_100_001_00_00
|
||||
12'b11_101_001_00_00
|
||||
12'b11_110_001_00_00
|
||||
12'b11_111_001_00_00
|
||||
*/
|
||||
|
||||
/* AXI -Master GP0 */
|
||||
processing_system7_vip_v1_0_7_axi_master #(C_USE_M_AXI_GP0, // enable
|
||||
axi_mgp0_name,// name
|
||||
axi_mgp_data_width, /// Data Width
|
||||
addr_width, /// Address width
|
||||
axi_mgp_id_width, //// ID Width
|
||||
axi_mgp_outstanding, //// Outstanding transactions
|
||||
axi_mst_excl_support, // EXCL Access Support
|
||||
axi_mgp_wr_id, //WR_ID
|
||||
axi_mgp_rd_id) //RD_ID
|
||||
M_AXI_GP0(.M_RESETN (net_axi_mgp0_rstn),
|
||||
.M_ACLK (M_AXI_GP0_ACLK),
|
||||
// Write Address Channel
|
||||
.M_AWID (M_AXI_GP0_AWID_FULL),
|
||||
.M_AWADDR (M_AXI_GP0_AWADDR),
|
||||
.M_AWLEN (M_AXI_GP0_AWLEN),
|
||||
.M_AWSIZE (M_AXI_GP0_AWSIZE),
|
||||
.M_AWBURST (M_AXI_GP0_AWBURST),
|
||||
.M_AWLOCK (M_AXI_GP0_AWLOCK),
|
||||
.M_AWCACHE (M_AXI_GP0_AWCACHE),
|
||||
.M_AWPROT (M_AXI_GP0_AWPROT),
|
||||
.M_AWVALID (M_AXI_GP0_AWVALID),
|
||||
.M_AWREADY (M_AXI_GP0_AWREADY),
|
||||
// Write Data Channel Signals.
|
||||
.M_WID (M_AXI_GP0_WID_FULL),
|
||||
.M_WDATA (M_AXI_GP0_WDATA),
|
||||
.M_WSTRB (M_AXI_GP0_WSTRB),
|
||||
.M_WLAST (M_AXI_GP0_WLAST),
|
||||
.M_WVALID (M_AXI_GP0_WVALID),
|
||||
.M_WREADY (M_AXI_GP0_WREADY),
|
||||
// Write Response Channel Signals.
|
||||
.M_BID (M_AXI_GP0_BID_FULL),
|
||||
.M_BRESP (M_AXI_GP0_BRESP),
|
||||
.M_BVALID (M_AXI_GP0_BVALID),
|
||||
.M_BREADY (M_AXI_GP0_BREADY),
|
||||
// Read Address Channel Signals.
|
||||
.M_ARID (M_AXI_GP0_ARID_FULL),
|
||||
.M_ARADDR (M_AXI_GP0_ARADDR),
|
||||
.M_ARLEN (M_AXI_GP0_ARLEN),
|
||||
.M_ARSIZE (M_AXI_GP0_ARSIZE),
|
||||
.M_ARBURST (M_AXI_GP0_ARBURST),
|
||||
.M_ARLOCK (M_AXI_GP0_ARLOCK),
|
||||
.M_ARCACHE (M_AXI_GP0_ARCACHE),
|
||||
.M_ARPROT (M_AXI_GP0_ARPROT),
|
||||
.M_ARVALID (M_AXI_GP0_ARVALID),
|
||||
.M_ARREADY (M_AXI_GP0_ARREADY),
|
||||
// Read Data Channel Signals.
|
||||
.M_RID (M_AXI_GP0_RID_FULL),
|
||||
.M_RDATA (M_AXI_GP0_RDATA),
|
||||
.M_RRESP (M_AXI_GP0_RRESP),
|
||||
.M_RLAST (M_AXI_GP0_RLAST),
|
||||
.M_RVALID (M_AXI_GP0_RVALID),
|
||||
.M_RREADY (M_AXI_GP0_RREADY),
|
||||
// Side band signals
|
||||
.M_AWQOS (M_AXI_GP0_AWQOS),
|
||||
.M_ARQOS (M_AXI_GP0_ARQOS)
|
||||
);
|
||||
|
||||
/* AXI Master GP1 */
|
||||
processing_system7_vip_v1_0_7_axi_master #(C_USE_M_AXI_GP1, // enable
|
||||
axi_mgp1_name,// name
|
||||
axi_mgp_data_width, /// Data Width
|
||||
addr_width, /// Address width
|
||||
axi_mgp_id_width, //// ID Width
|
||||
axi_mgp_outstanding, //// Outstanding transactions
|
||||
axi_mst_excl_support, // EXCL Access Support
|
||||
axi_mgp_wr_id, //WR_ID
|
||||
axi_mgp_rd_id) //RD_ID
|
||||
M_AXI_GP1(.M_RESETN (net_axi_mgp1_rstn),
|
||||
.M_ACLK (M_AXI_GP1_ACLK),
|
||||
// Write Address Channel
|
||||
.M_AWID (M_AXI_GP1_AWID_FULL),
|
||||
.M_AWADDR (M_AXI_GP1_AWADDR),
|
||||
.M_AWLEN (M_AXI_GP1_AWLEN),
|
||||
.M_AWSIZE (M_AXI_GP1_AWSIZE),
|
||||
.M_AWBURST (M_AXI_GP1_AWBURST),
|
||||
.M_AWLOCK (M_AXI_GP1_AWLOCK),
|
||||
.M_AWCACHE (M_AXI_GP1_AWCACHE),
|
||||
.M_AWPROT (M_AXI_GP1_AWPROT),
|
||||
.M_AWVALID (M_AXI_GP1_AWVALID),
|
||||
.M_AWREADY (M_AXI_GP1_AWREADY),
|
||||
// Write Data Channel Signals.
|
||||
.M_WID (M_AXI_GP1_WID_FULL),
|
||||
.M_WDATA (M_AXI_GP1_WDATA),
|
||||
.M_WSTRB (M_AXI_GP1_WSTRB),
|
||||
.M_WLAST (M_AXI_GP1_WLAST),
|
||||
.M_WVALID (M_AXI_GP1_WVALID),
|
||||
.M_WREADY (M_AXI_GP1_WREADY),
|
||||
// Write Response Channel Signals.
|
||||
.M_BID (M_AXI_GP1_BID_FULL),
|
||||
.M_BRESP (M_AXI_GP1_BRESP),
|
||||
.M_BVALID (M_AXI_GP1_BVALID),
|
||||
.M_BREADY (M_AXI_GP1_BREADY),
|
||||
// Read Address Channel Signals.
|
||||
.M_ARID (M_AXI_GP1_ARID_FULL),
|
||||
.M_ARADDR (M_AXI_GP1_ARADDR),
|
||||
.M_ARLEN (M_AXI_GP1_ARLEN),
|
||||
.M_ARSIZE (M_AXI_GP1_ARSIZE),
|
||||
.M_ARBURST (M_AXI_GP1_ARBURST),
|
||||
.M_ARLOCK (M_AXI_GP1_ARLOCK),
|
||||
.M_ARCACHE (M_AXI_GP1_ARCACHE),
|
||||
.M_ARPROT (M_AXI_GP1_ARPROT),
|
||||
.M_ARVALID (M_AXI_GP1_ARVALID),
|
||||
.M_ARREADY (M_AXI_GP1_ARREADY),
|
||||
// Read Data Channel Signals.
|
||||
.M_RID (M_AXI_GP1_RID_FULL),
|
||||
.M_RDATA (M_AXI_GP1_RDATA),
|
||||
.M_RRESP (M_AXI_GP1_RRESP),
|
||||
.M_RLAST (M_AXI_GP1_RLAST),
|
||||
.M_RVALID (M_AXI_GP1_RVALID),
|
||||
.M_RREADY (M_AXI_GP1_RREADY),
|
||||
// Side band signals
|
||||
.M_AWQOS (M_AXI_GP1_AWQOS),
|
||||
.M_ARQOS (M_AXI_GP1_ARQOS)
|
||||
);
|
||||
|
||||
/* AXI Slave GP0 */
|
||||
processing_system7_vip_v1_0_7_axi_slave #(C_USE_S_AXI_GP0, /// enable
|
||||
axi_sgp0_name, //name
|
||||
axi_sgp_data_width, /// data width
|
||||
addr_width, /// address width
|
||||
axi_sgp_id_width, /// ID width
|
||||
C_S_AXI_GP0_BASEADDR,//// base address
|
||||
C_S_AXI_GP0_HIGHADDR,/// Memory size (high_addr - base_addr)
|
||||
axi_sgp_outstanding, // outstanding transactions
|
||||
axi_slv_excl_support, // exclusive access not supported
|
||||
axi_sgp_wr_outstanding,
|
||||
axi_sgp_rd_outstanding)
|
||||
S_AXI_GP0(.S_RESETN (net_axi_gp0_rstn),
|
||||
.S_ACLK (S_AXI_GP0_ACLK),
|
||||
// Write Address Channel
|
||||
.S_AWID (S_AXI_GP0_AWID),
|
||||
.S_AWADDR (S_AXI_GP0_AWADDR),
|
||||
.S_AWLEN (S_AXI_GP0_AWLEN),
|
||||
.S_AWSIZE (S_AXI_GP0_AWSIZE),
|
||||
.S_AWBURST (S_AXI_GP0_AWBURST),
|
||||
.S_AWLOCK (S_AXI_GP0_AWLOCK),
|
||||
.S_AWCACHE (S_AXI_GP0_AWCACHE),
|
||||
.S_AWPROT (S_AXI_GP0_AWPROT),
|
||||
.S_AWVALID (S_AXI_GP0_AWVALID),
|
||||
.S_AWREADY (S_AXI_GP0_AWREADY),
|
||||
// Write Data Channel Signals.
|
||||
.S_WID (S_AXI_GP0_WID),
|
||||
.S_WDATA (S_AXI_GP0_WDATA),
|
||||
.S_WSTRB (S_AXI_GP0_WSTRB),
|
||||
.S_WLAST (S_AXI_GP0_WLAST),
|
||||
.S_WVALID (S_AXI_GP0_WVALID),
|
||||
.S_WREADY (S_AXI_GP0_WREADY),
|
||||
// Write Response Channel Signals.
|
||||
.S_BID (S_AXI_GP0_BID),
|
||||
.S_BRESP (S_AXI_GP0_BRESP),
|
||||
.S_BVALID (S_AXI_GP0_BVALID),
|
||||
.S_BREADY (S_AXI_GP0_BREADY),
|
||||
// Read Address Channel Signals.
|
||||
.S_ARID (S_AXI_GP0_ARID),
|
||||
.S_ARADDR (S_AXI_GP0_ARADDR),
|
||||
.S_ARLEN (S_AXI_GP0_ARLEN),
|
||||
.S_ARSIZE (S_AXI_GP0_ARSIZE),
|
||||
.S_ARBURST (S_AXI_GP0_ARBURST),
|
||||
.S_ARLOCK (S_AXI_GP0_ARLOCK),
|
||||
.S_ARCACHE (S_AXI_GP0_ARCACHE),
|
||||
.S_ARPROT (S_AXI_GP0_ARPROT),
|
||||
.S_ARVALID (S_AXI_GP0_ARVALID),
|
||||
.S_ARREADY (S_AXI_GP0_ARREADY),
|
||||
// Read Data Channel Signals.
|
||||
.S_RID (S_AXI_GP0_RID),
|
||||
.S_RDATA (S_AXI_GP0_RDATA),
|
||||
.S_RRESP (S_AXI_GP0_RRESP),
|
||||
.S_RLAST (S_AXI_GP0_RLAST),
|
||||
.S_RVALID (S_AXI_GP0_RVALID),
|
||||
.S_RREADY (S_AXI_GP0_RREADY),
|
||||
// Side band signals
|
||||
.S_AWQOS (S_AXI_GP0_AWQOS),
|
||||
.S_ARQOS (S_AXI_GP0_ARQOS),
|
||||
|
||||
.SW_CLK (net_sw_clk),
|
||||
.WR_DATA_ACK_OCM (net_wr_ack_ocm_gp0),
|
||||
.WR_DATA_ACK_DDR (net_wr_ack_ddr_gp0),
|
||||
.WR_DATA (net_wr_data_gp0),
|
||||
.WR_DATA_STRB (net_wr_strb_gp0),
|
||||
.WR_ADDR (net_wr_addr_gp0),
|
||||
.WR_BYTES (net_wr_bytes_gp0),
|
||||
.WR_DATA_VALID_OCM (net_wr_dv_ocm_gp0),
|
||||
.WR_DATA_VALID_DDR (net_wr_dv_ddr_gp0),
|
||||
.WR_QOS (net_wr_qos_gp0),
|
||||
.RD_REQ_DDR (net_rd_req_ddr_gp0),
|
||||
.RD_REQ_OCM (net_rd_req_ocm_gp0),
|
||||
.RD_REQ_REG (net_rd_req_reg_gp0),
|
||||
.RD_ADDR (net_rd_addr_gp0),
|
||||
.RD_DATA_DDR (net_rd_data_ddr_gp0),
|
||||
.RD_DATA_OCM (net_rd_data_ocm_gp0),
|
||||
.RD_DATA_REG (net_rd_data_reg_gp0),
|
||||
.RD_BYTES (net_rd_bytes_gp0),
|
||||
.RD_DATA_VALID_DDR (net_rd_dv_ddr_gp0),
|
||||
.RD_DATA_VALID_OCM (net_rd_dv_ocm_gp0),
|
||||
.RD_DATA_VALID_REG (net_rd_dv_reg_gp0),
|
||||
.RD_QOS (net_rd_qos_gp0)
|
||||
|
||||
);
|
||||
|
||||
/* AXI Slave GP1 */
|
||||
processing_system7_vip_v1_0_7_axi_slave #(C_USE_S_AXI_GP1, /// enable
|
||||
axi_sgp1_name, //name
|
||||
axi_sgp_data_width, /// data width
|
||||
addr_width, /// address width
|
||||
axi_sgp_id_width, /// ID width
|
||||
C_S_AXI_GP1_BASEADDR,//// base address
|
||||
C_S_AXI_GP1_HIGHADDR,/// HIGh_addr
|
||||
axi_sgp_outstanding, // outstanding transactions
|
||||
axi_slv_excl_support, // exclusive access
|
||||
axi_sgp_wr_outstanding,
|
||||
axi_sgp_rd_outstanding)
|
||||
S_AXI_GP1(.S_RESETN (net_axi_gp1_rstn),
|
||||
.S_ACLK (S_AXI_GP1_ACLK),
|
||||
// Write Address Channel
|
||||
.S_AWID (S_AXI_GP1_AWID),
|
||||
.S_AWADDR (S_AXI_GP1_AWADDR),
|
||||
.S_AWLEN (S_AXI_GP1_AWLEN),
|
||||
.S_AWSIZE (S_AXI_GP1_AWSIZE),
|
||||
.S_AWBURST (S_AXI_GP1_AWBURST),
|
||||
.S_AWLOCK (S_AXI_GP1_AWLOCK),
|
||||
.S_AWCACHE (S_AXI_GP1_AWCACHE),
|
||||
.S_AWPROT (S_AXI_GP1_AWPROT),
|
||||
.S_AWVALID (S_AXI_GP1_AWVALID),
|
||||
.S_AWREADY (S_AXI_GP1_AWREADY),
|
||||
// Write Data Channel Signals.
|
||||
.S_WID (S_AXI_GP1_WID),
|
||||
.S_WDATA (S_AXI_GP1_WDATA),
|
||||
.S_WSTRB (S_AXI_GP1_WSTRB),
|
||||
.S_WLAST (S_AXI_GP1_WLAST),
|
||||
.S_WVALID (S_AXI_GP1_WVALID),
|
||||
.S_WREADY (S_AXI_GP1_WREADY),
|
||||
// Write Response Channel Signals.
|
||||
.S_BID (S_AXI_GP1_BID),
|
||||
.S_BRESP (S_AXI_GP1_BRESP),
|
||||
.S_BVALID (S_AXI_GP1_BVALID),
|
||||
.S_BREADY (S_AXI_GP1_BREADY),
|
||||
// Read Address Channel Signals.
|
||||
.S_ARID (S_AXI_GP1_ARID),
|
||||
.S_ARADDR (S_AXI_GP1_ARADDR),
|
||||
.S_ARLEN (S_AXI_GP1_ARLEN),
|
||||
.S_ARSIZE (S_AXI_GP1_ARSIZE),
|
||||
.S_ARBURST (S_AXI_GP1_ARBURST),
|
||||
.S_ARLOCK (S_AXI_GP1_ARLOCK),
|
||||
.S_ARCACHE (S_AXI_GP1_ARCACHE),
|
||||
.S_ARPROT (S_AXI_GP1_ARPROT),
|
||||
.S_ARVALID (S_AXI_GP1_ARVALID),
|
||||
.S_ARREADY (S_AXI_GP1_ARREADY),
|
||||
// Read Data Channel Signals.
|
||||
.S_RID (S_AXI_GP1_RID),
|
||||
.S_RDATA (S_AXI_GP1_RDATA),
|
||||
.S_RRESP (S_AXI_GP1_RRESP),
|
||||
.S_RLAST (S_AXI_GP1_RLAST),
|
||||
.S_RVALID (S_AXI_GP1_RVALID),
|
||||
.S_RREADY (S_AXI_GP1_RREADY),
|
||||
// Side band signals
|
||||
.S_AWQOS (S_AXI_GP1_AWQOS),
|
||||
.S_ARQOS (S_AXI_GP1_ARQOS),
|
||||
|
||||
.SW_CLK (net_sw_clk),
|
||||
.WR_DATA_ACK_DDR (net_wr_ack_ddr_gp1),
|
||||
.WR_DATA_ACK_OCM (net_wr_ack_ocm_gp1),
|
||||
.WR_DATA (net_wr_data_gp1),
|
||||
.WR_DATA_STRB (net_wr_strb_gp1),
|
||||
.WR_ADDR (net_wr_addr_gp1),
|
||||
.WR_BYTES (net_wr_bytes_gp1),
|
||||
.WR_DATA_VALID_OCM (net_wr_dv_ocm_gp1),
|
||||
.WR_DATA_VALID_DDR (net_wr_dv_ddr_gp1),
|
||||
.WR_QOS (net_wr_qos_gp1),
|
||||
.RD_REQ_OCM (net_rd_req_ocm_gp1),
|
||||
.RD_REQ_DDR (net_rd_req_ddr_gp1),
|
||||
.RD_REQ_REG (net_rd_req_reg_gp1),
|
||||
.RD_ADDR (net_rd_addr_gp1),
|
||||
.RD_DATA_DDR (net_rd_data_ddr_gp1),
|
||||
.RD_DATA_OCM (net_rd_data_ocm_gp1),
|
||||
.RD_DATA_REG (net_rd_data_reg_gp1),
|
||||
.RD_BYTES (net_rd_bytes_gp1),
|
||||
.RD_DATA_VALID_OCM (net_rd_dv_ocm_gp1),
|
||||
.RD_DATA_VALID_DDR (net_rd_dv_ddr_gp1),
|
||||
.RD_DATA_VALID_REG (net_rd_dv_reg_gp1),
|
||||
.RD_QOS (net_rd_qos_gp1)
|
||||
|
||||
);
|
||||
+350
@@ -0,0 +1,350 @@
|
||||
/*****************************************************************************
|
||||
* File : processing_system7_vip_v1_0_7_axi_hp.v
|
||||
*
|
||||
* Date : 2012-11
|
||||
*
|
||||
* Description : Connections for AXI HP ports
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
/* AXI Slave HP0 */
|
||||
processing_system7_vip_v1_0_7_afi_slave #( C_USE_S_AXI_HP0, // enable
|
||||
axi_hp0_name, // name
|
||||
C_S_AXI_HP0_DATA_WIDTH, // data width
|
||||
addr_width, /// address width
|
||||
axi_hp_id_width, // ID width
|
||||
C_S_AXI_HP0_BASEADDR, // slave base address
|
||||
C_S_AXI_HP0_HIGHADDR, // slave size
|
||||
axi_hp_outstanding, // outstanding transactions // dynamic for AFI ports
|
||||
axi_slv_excl_support) // Exclusive access support
|
||||
S_AXI_HP0(.S_RESETN (net_axi_hp0_rstn),
|
||||
.S_ACLK (S_AXI_HP0_ACLK),
|
||||
// Write Address channel
|
||||
.S_AWID (S_AXI_HP0_AWID),
|
||||
.S_AWADDR (S_AXI_HP0_AWADDR),
|
||||
.S_AWLEN (S_AXI_HP0_AWLEN),
|
||||
.S_AWSIZE (S_AXI_HP0_AWSIZE),
|
||||
.S_AWBURST (S_AXI_HP0_AWBURST),
|
||||
.S_AWLOCK (S_AXI_HP0_AWLOCK),
|
||||
.S_AWCACHE (S_AXI_HP0_AWCACHE),
|
||||
.S_AWPROT (S_AXI_HP0_AWPROT),
|
||||
.S_AWVALID (S_AXI_HP0_AWVALID),
|
||||
.S_AWREADY (S_AXI_HP0_AWREADY),
|
||||
// Write Data channel signals.
|
||||
.S_WID (S_AXI_HP0_WID),
|
||||
.S_WDATA (S_AXI_HP0_WDATA),
|
||||
.S_WSTRB (S_AXI_HP0_WSTRB),
|
||||
.S_WLAST (S_AXI_HP0_WLAST),
|
||||
.S_WVALID (S_AXI_HP0_WVALID),
|
||||
.S_WREADY (S_AXI_HP0_WREADY),
|
||||
// Write Response channel signals.
|
||||
.S_BID (S_AXI_HP0_BID),
|
||||
.S_BRESP (S_AXI_HP0_BRESP),
|
||||
.S_BVALID (S_AXI_HP0_BVALID),
|
||||
.S_BREADY (S_AXI_HP0_BREADY),
|
||||
// Read Address channel signals.
|
||||
.S_ARID (S_AXI_HP0_ARID),
|
||||
.S_ARADDR (S_AXI_HP0_ARADDR),
|
||||
.S_ARLEN (S_AXI_HP0_ARLEN),
|
||||
.S_ARSIZE (S_AXI_HP0_ARSIZE),
|
||||
.S_ARBURST (S_AXI_HP0_ARBURST),
|
||||
.S_ARLOCK (S_AXI_HP0_ARLOCK),
|
||||
.S_ARCACHE (S_AXI_HP0_ARCACHE),
|
||||
.S_ARPROT (S_AXI_HP0_ARPROT),
|
||||
.S_ARVALID (S_AXI_HP0_ARVALID),
|
||||
.S_ARREADY (S_AXI_HP0_ARREADY),
|
||||
// Read Data channel signals.
|
||||
.S_RID (S_AXI_HP0_RID),
|
||||
.S_RDATA (S_AXI_HP0_RDATA),
|
||||
.S_RRESP (S_AXI_HP0_RRESP),
|
||||
.S_RLAST (S_AXI_HP0_RLAST),
|
||||
.S_RVALID (S_AXI_HP0_RVALID),
|
||||
.S_RREADY (S_AXI_HP0_RREADY),
|
||||
// Side band signals
|
||||
.S_AWQOS (S_AXI_HP0_AWQOS),
|
||||
.S_ARQOS (S_AXI_HP0_ARQOS),
|
||||
// these are needed only for HP ports
|
||||
.S_RDISSUECAP1_EN (S_AXI_HP0_RDISSUECAP1_EN),
|
||||
.S_WRISSUECAP1_EN (S_AXI_HP0_WRISSUECAP1_EN),
|
||||
.S_RCOUNT (S_AXI_HP0_RCOUNT),
|
||||
.S_WCOUNT (S_AXI_HP0_WCOUNT),
|
||||
.S_RACOUNT (S_AXI_HP0_RACOUNT),
|
||||
.S_WACOUNT (S_AXI_HP0_WACOUNT),
|
||||
|
||||
.SW_CLK (net_sw_clk),
|
||||
.WR_DATA_ACK_DDR (net_wr_ack_ddr_hp0),
|
||||
.WR_DATA_ACK_OCM (net_wr_ack_ocm_hp0),
|
||||
.WR_DATA (net_wr_data_hp0),
|
||||
.WR_DATA_STRB (net_wr_strb_hp0),
|
||||
.WR_ADDR (net_wr_addr_hp0),
|
||||
.WR_BYTES (net_wr_bytes_hp0),
|
||||
.WR_DATA_VALID_DDR (net_wr_dv_ddr_hp0),
|
||||
.WR_DATA_VALID_OCM (net_wr_dv_ocm_hp0),
|
||||
.WR_QOS (net_wr_qos_hp0),
|
||||
.RD_REQ_DDR (net_rd_req_ddr_hp0),
|
||||
.RD_REQ_OCM (net_rd_req_ocm_hp0),
|
||||
.RD_ADDR (net_rd_addr_hp0),
|
||||
.RD_DATA_DDR (net_rd_data_ddr_hp0),
|
||||
.RD_DATA_OCM (net_rd_data_ocm_hp0),
|
||||
.RD_BYTES (net_rd_bytes_hp0),
|
||||
.RD_DATA_VALID_DDR (net_rd_dv_ddr_hp0),
|
||||
.RD_DATA_VALID_OCM (net_rd_dv_ocm_hp0),
|
||||
.RD_QOS (net_rd_qos_hp0)
|
||||
);
|
||||
|
||||
/* AXI Slave HP1 */
|
||||
processing_system7_vip_v1_0_7_afi_slave #( C_USE_S_AXI_HP1, // enable
|
||||
axi_hp1_name, // name
|
||||
C_S_AXI_HP1_DATA_WIDTH, // data width
|
||||
addr_width, /// address width
|
||||
axi_hp_id_width, // ID width
|
||||
C_S_AXI_HP1_BASEADDR, // slave base address
|
||||
C_S_AXI_HP1_HIGHADDR, // Slave size
|
||||
axi_hp_outstanding, // outstanding transactions // dynamic for AFI ports
|
||||
axi_slv_excl_support) // Exclusive access support
|
||||
S_AXI_HP1(.S_RESETN (net_axi_hp1_rstn),
|
||||
.S_ACLK (S_AXI_HP1_ACLK),
|
||||
// Write Address channel
|
||||
.S_AWID (S_AXI_HP1_AWID),
|
||||
.S_AWADDR (S_AXI_HP1_AWADDR),
|
||||
.S_AWLEN (S_AXI_HP1_AWLEN),
|
||||
.S_AWSIZE (S_AXI_HP1_AWSIZE),
|
||||
.S_AWBURST (S_AXI_HP1_AWBURST),
|
||||
.S_AWLOCK (S_AXI_HP1_AWLOCK),
|
||||
.S_AWCACHE (S_AXI_HP1_AWCACHE),
|
||||
.S_AWPROT (S_AXI_HP1_AWPROT),
|
||||
.S_AWVALID (S_AXI_HP1_AWVALID),
|
||||
.S_AWREADY (S_AXI_HP1_AWREADY),
|
||||
// Write Data channel signals.
|
||||
.S_WID (S_AXI_HP1_WID),
|
||||
.S_WDATA (S_AXI_HP1_WDATA),
|
||||
.S_WSTRB (S_AXI_HP1_WSTRB),
|
||||
.S_WLAST (S_AXI_HP1_WLAST),
|
||||
.S_WVALID (S_AXI_HP1_WVALID),
|
||||
.S_WREADY (S_AXI_HP1_WREADY),
|
||||
// Write Response channel signals.
|
||||
.S_BID (S_AXI_HP1_BID),
|
||||
.S_BRESP (S_AXI_HP1_BRESP),
|
||||
.S_BVALID (S_AXI_HP1_BVALID),
|
||||
.S_BREADY (S_AXI_HP1_BREADY),
|
||||
// Read Address channel signals.
|
||||
.S_ARID (S_AXI_HP1_ARID),
|
||||
.S_ARADDR (S_AXI_HP1_ARADDR),
|
||||
.S_ARLEN (S_AXI_HP1_ARLEN),
|
||||
.S_ARSIZE (S_AXI_HP1_ARSIZE),
|
||||
.S_ARBURST (S_AXI_HP1_ARBURST),
|
||||
.S_ARLOCK (S_AXI_HP1_ARLOCK),
|
||||
.S_ARCACHE (S_AXI_HP1_ARCACHE),
|
||||
.S_ARPROT (S_AXI_HP1_ARPROT),
|
||||
.S_ARVALID (S_AXI_HP1_ARVALID),
|
||||
.S_ARREADY (S_AXI_HP1_ARREADY),
|
||||
// Read Data channel signals.
|
||||
.S_RID (S_AXI_HP1_RID),
|
||||
.S_RDATA (S_AXI_HP1_RDATA),
|
||||
.S_RRESP (S_AXI_HP1_RRESP),
|
||||
.S_RLAST (S_AXI_HP1_RLAST),
|
||||
.S_RVALID (S_AXI_HP1_RVALID),
|
||||
.S_RREADY (S_AXI_HP1_RREADY),
|
||||
// Side band signals
|
||||
.S_AWQOS (S_AXI_HP1_AWQOS),
|
||||
.S_ARQOS (S_AXI_HP1_ARQOS),
|
||||
// these are needed only for HP ports
|
||||
.S_RDISSUECAP1_EN (S_AXI_HP1_RDISSUECAP1_EN),
|
||||
.S_WRISSUECAP1_EN (S_AXI_HP1_WRISSUECAP1_EN),
|
||||
.S_RCOUNT (S_AXI_HP1_RCOUNT),
|
||||
.S_WCOUNT (S_AXI_HP1_WCOUNT),
|
||||
.S_RACOUNT (S_AXI_HP1_RACOUNT),
|
||||
.S_WACOUNT (S_AXI_HP1_WACOUNT),
|
||||
|
||||
.SW_CLK (net_sw_clk),
|
||||
.WR_DATA_ACK_DDR (net_wr_ack_ddr_hp1),
|
||||
.WR_DATA_ACK_OCM (net_wr_ack_ocm_hp1),
|
||||
.WR_DATA (net_wr_data_hp1),
|
||||
.WR_DATA_STRB (net_wr_strb_hp1),
|
||||
.WR_ADDR (net_wr_addr_hp1),
|
||||
.WR_BYTES (net_wr_bytes_hp1),
|
||||
.WR_DATA_VALID_DDR (net_wr_dv_ddr_hp1),
|
||||
.WR_DATA_VALID_OCM (net_wr_dv_ocm_hp1),
|
||||
.WR_QOS (net_wr_qos_hp1),
|
||||
.RD_REQ_DDR (net_rd_req_ddr_hp1),
|
||||
.RD_REQ_OCM (net_rd_req_ocm_hp1),
|
||||
.RD_ADDR (net_rd_addr_hp1),
|
||||
.RD_DATA_DDR (net_rd_data_ddr_hp1),
|
||||
.RD_DATA_OCM (net_rd_data_ocm_hp1),
|
||||
.RD_BYTES (net_rd_bytes_hp1),
|
||||
.RD_DATA_VALID_DDR (net_rd_dv_ddr_hp1),
|
||||
.RD_DATA_VALID_OCM (net_rd_dv_ocm_hp1),
|
||||
.RD_QOS (net_rd_qos_hp1)
|
||||
|
||||
);
|
||||
|
||||
/* AXI Slave HP2 */
|
||||
processing_system7_vip_v1_0_7_afi_slave #( C_USE_S_AXI_HP2, // enable
|
||||
axi_hp2_name, // name
|
||||
C_S_AXI_HP2_DATA_WIDTH, // data width
|
||||
addr_width, /// address width
|
||||
axi_hp_id_width, // ID width
|
||||
C_S_AXI_HP2_BASEADDR, // slave base address
|
||||
C_S_AXI_HP2_HIGHADDR, // SLave size
|
||||
axi_hp_outstanding, // outstanding transactions // dynamic for AFI ports
|
||||
axi_slv_excl_support) // Exclusive access support
|
||||
S_AXI_HP2(.S_RESETN (net_axi_hp2_rstn),
|
||||
.S_ACLK (S_AXI_HP2_ACLK),
|
||||
// Write Address channel
|
||||
.S_AWID (S_AXI_HP2_AWID),
|
||||
.S_AWADDR (S_AXI_HP2_AWADDR),
|
||||
.S_AWLEN (S_AXI_HP2_AWLEN),
|
||||
.S_AWSIZE (S_AXI_HP2_AWSIZE),
|
||||
.S_AWBURST (S_AXI_HP2_AWBURST),
|
||||
.S_AWLOCK (S_AXI_HP2_AWLOCK),
|
||||
.S_AWCACHE (S_AXI_HP2_AWCACHE),
|
||||
.S_AWPROT (S_AXI_HP2_AWPROT),
|
||||
.S_AWVALID (S_AXI_HP2_AWVALID),
|
||||
.S_AWREADY (S_AXI_HP2_AWREADY),
|
||||
// Write Data channel signals.
|
||||
.S_WID (S_AXI_HP2_WID),
|
||||
.S_WDATA (S_AXI_HP2_WDATA),
|
||||
.S_WSTRB (S_AXI_HP2_WSTRB),
|
||||
.S_WLAST (S_AXI_HP2_WLAST),
|
||||
.S_WVALID (S_AXI_HP2_WVALID),
|
||||
.S_WREADY (S_AXI_HP2_WREADY),
|
||||
// Write Response channel signals.
|
||||
.S_BID (S_AXI_HP2_BID),
|
||||
.S_BRESP (S_AXI_HP2_BRESP),
|
||||
.S_BVALID (S_AXI_HP2_BVALID),
|
||||
.S_BREADY (S_AXI_HP2_BREADY),
|
||||
// Read Address channel signals.
|
||||
.S_ARID (S_AXI_HP2_ARID),
|
||||
.S_ARADDR (S_AXI_HP2_ARADDR),
|
||||
.S_ARLEN (S_AXI_HP2_ARLEN),
|
||||
.S_ARSIZE (S_AXI_HP2_ARSIZE),
|
||||
.S_ARBURST (S_AXI_HP2_ARBURST),
|
||||
.S_ARLOCK (S_AXI_HP2_ARLOCK),
|
||||
.S_ARCACHE (S_AXI_HP2_ARCACHE),
|
||||
.S_ARPROT (S_AXI_HP2_ARPROT),
|
||||
.S_ARVALID (S_AXI_HP2_ARVALID),
|
||||
.S_ARREADY (S_AXI_HP2_ARREADY),
|
||||
// Read Data channel signals.
|
||||
.S_RID (S_AXI_HP2_RID),
|
||||
.S_RDATA (S_AXI_HP2_RDATA),
|
||||
.S_RRESP (S_AXI_HP2_RRESP),
|
||||
.S_RLAST (S_AXI_HP2_RLAST),
|
||||
.S_RVALID (S_AXI_HP2_RVALID),
|
||||
.S_RREADY (S_AXI_HP2_RREADY),
|
||||
// Side band signals
|
||||
.S_AWQOS (S_AXI_HP2_AWQOS),
|
||||
.S_ARQOS (S_AXI_HP2_ARQOS),
|
||||
// these are needed only for HP ports
|
||||
.S_RDISSUECAP1_EN (S_AXI_HP2_RDISSUECAP1_EN),
|
||||
.S_WRISSUECAP1_EN (S_AXI_HP2_WRISSUECAP1_EN),
|
||||
.S_RCOUNT (S_AXI_HP2_RCOUNT),
|
||||
.S_WCOUNT (S_AXI_HP2_WCOUNT),
|
||||
.S_RACOUNT (S_AXI_HP2_RACOUNT),
|
||||
.S_WACOUNT (S_AXI_HP2_WACOUNT),
|
||||
|
||||
.SW_CLK (net_sw_clk),
|
||||
.WR_DATA_ACK_DDR (net_wr_ack_ddr_hp2),
|
||||
.WR_DATA_ACK_OCM (net_wr_ack_ocm_hp2),
|
||||
.WR_DATA (net_wr_data_hp2),
|
||||
.WR_DATA_STRB (net_wr_strb_hp2),
|
||||
.WR_ADDR (net_wr_addr_hp2),
|
||||
.WR_BYTES (net_wr_bytes_hp2),
|
||||
.WR_DATA_VALID_DDR (net_wr_dv_ddr_hp2),
|
||||
.WR_DATA_VALID_OCM (net_wr_dv_ocm_hp2),
|
||||
.WR_QOS (net_wr_qos_hp2),
|
||||
.RD_REQ_DDR (net_rd_req_ddr_hp2),
|
||||
.RD_REQ_OCM (net_rd_req_ocm_hp2),
|
||||
.RD_ADDR (net_rd_addr_hp2),
|
||||
.RD_DATA_DDR (net_rd_data_ddr_hp2),
|
||||
.RD_DATA_OCM (net_rd_data_ocm_hp2),
|
||||
.RD_BYTES (net_rd_bytes_hp2),
|
||||
.RD_DATA_VALID_DDR (net_rd_dv_ddr_hp2),
|
||||
.RD_DATA_VALID_OCM (net_rd_dv_ocm_hp2),
|
||||
.RD_QOS (net_rd_qos_hp2)
|
||||
|
||||
);
|
||||
|
||||
/* AXI Slave HP3 */
|
||||
processing_system7_vip_v1_0_7_afi_slave #( C_USE_S_AXI_HP3, // enable
|
||||
axi_hp3_name, // name
|
||||
C_S_AXI_HP3_DATA_WIDTH, // data width
|
||||
addr_width, /// address width
|
||||
axi_hp_id_width, // ID width
|
||||
C_S_AXI_HP3_BASEADDR, // slave base address
|
||||
C_S_AXI_HP3_HIGHADDR, // SLave size
|
||||
axi_hp_outstanding, // outstanding transactions // dynamic for AFI ports
|
||||
axi_slv_excl_support) // Exclusive access support
|
||||
S_AXI_HP3(.S_RESETN (net_axi_hp3_rstn),
|
||||
.S_ACLK (S_AXI_HP3_ACLK),
|
||||
// Write ADDRESS CHANNEL
|
||||
.S_AWID (S_AXI_HP3_AWID),
|
||||
.S_AWADDR (S_AXI_HP3_AWADDR),
|
||||
.S_AWLEN (S_AXI_HP3_AWLEN),
|
||||
.S_AWSIZE (S_AXI_HP3_AWSIZE),
|
||||
.S_AWBURST (S_AXI_HP3_AWBURST),
|
||||
.S_AWLOCK (S_AXI_HP3_AWLOCK),
|
||||
.S_AWCACHE (S_AXI_HP3_AWCACHE),
|
||||
.S_AWPROT (S_AXI_HP3_AWPROT),
|
||||
.S_AWVALID (S_AXI_HP3_AWVALID),
|
||||
.S_AWREADY (S_AXI_HP3_AWREADY),
|
||||
// Write Data channel signals.
|
||||
.S_WID (S_AXI_HP3_WID),
|
||||
.S_WDATA (S_AXI_HP3_WDATA),
|
||||
.S_WSTRB (S_AXI_HP3_WSTRB),
|
||||
.S_WLAST (S_AXI_HP3_WLAST),
|
||||
.S_WVALID (S_AXI_HP3_WVALID),
|
||||
.S_WREADY (S_AXI_HP3_WREADY),
|
||||
// Write Response channel signals.
|
||||
.S_BID (S_AXI_HP3_BID),
|
||||
.S_BRESP (S_AXI_HP3_BRESP),
|
||||
.S_BVALID (S_AXI_HP3_BVALID),
|
||||
.S_BREADY (S_AXI_HP3_BREADY),
|
||||
// Read Address channel signals.
|
||||
.S_ARID (S_AXI_HP3_ARID),
|
||||
.S_ARADDR (S_AXI_HP3_ARADDR),
|
||||
.S_ARLEN (S_AXI_HP3_ARLEN),
|
||||
.S_ARSIZE (S_AXI_HP3_ARSIZE),
|
||||
.S_ARBURST (S_AXI_HP3_ARBURST),
|
||||
.S_ARLOCK (S_AXI_HP3_ARLOCK),
|
||||
.S_ARCACHE (S_AXI_HP3_ARCACHE),
|
||||
.S_ARPROT (S_AXI_HP3_ARPROT),
|
||||
.S_ARVALID (S_AXI_HP3_ARVALID),
|
||||
.S_ARREADY (S_AXI_HP3_ARREADY),
|
||||
// Read Data channel signals.
|
||||
.S_RID (S_AXI_HP3_RID),
|
||||
.S_RDATA (S_AXI_HP3_RDATA),
|
||||
.S_RRESP (S_AXI_HP3_RRESP),
|
||||
.S_RLAST (S_AXI_HP3_RLAST),
|
||||
.S_RVALID (S_AXI_HP3_RVALID),
|
||||
.S_RREADY (S_AXI_HP3_RREADY),
|
||||
// Side band signals
|
||||
.S_AWQOS (S_AXI_HP3_AWQOS),
|
||||
.S_ARQOS (S_AXI_HP3_ARQOS),
|
||||
// these are needed only for HP ports
|
||||
.S_RDISSUECAP1_EN (S_AXI_HP3_RDISSUECAP1_EN),
|
||||
.S_WRISSUECAP1_EN (S_AXI_HP3_WRISSUECAP1_EN),
|
||||
.S_RCOUNT (S_AXI_HP3_RCOUNT),
|
||||
.S_WCOUNT (S_AXI_HP3_WCOUNT),
|
||||
.S_RACOUNT (S_AXI_HP3_RACOUNT),
|
||||
.S_WACOUNT (S_AXI_HP3_WACOUNT),
|
||||
|
||||
.SW_CLK (net_sw_clk),
|
||||
.WR_DATA_ACK_DDR (net_wr_ack_ddr_hp3),
|
||||
.WR_DATA_ACK_OCM (net_wr_ack_ocm_hp3),
|
||||
.WR_DATA (net_wr_data_hp3),
|
||||
.WR_DATA_STRB (net_wr_strb_hp3),
|
||||
.WR_ADDR (net_wr_addr_hp3),
|
||||
.WR_BYTES (net_wr_bytes_hp3),
|
||||
.WR_DATA_VALID_DDR (net_wr_dv_ddr_hp3),
|
||||
.WR_DATA_VALID_OCM (net_wr_dv_ocm_hp3),
|
||||
.WR_QOS (net_wr_qos_hp3),
|
||||
.RD_REQ_DDR (net_rd_req_ddr_hp3),
|
||||
.RD_REQ_OCM (net_rd_req_ocm_hp3),
|
||||
.RD_ADDR (net_rd_addr_hp3),
|
||||
.RD_DATA_DDR (net_rd_data_ddr_hp3),
|
||||
.RD_DATA_OCM (net_rd_data_ocm_hp3),
|
||||
.RD_BYTES (net_rd_bytes_hp3),
|
||||
.RD_DATA_VALID_DDR (net_rd_dv_ddr_hp3),
|
||||
.RD_DATA_VALID_OCM (net_rd_dv_ocm_hp3),
|
||||
.RD_QOS (net_rd_qos_hp3)
|
||||
);
|
||||
+244
@@ -0,0 +1,244 @@
|
||||
/*****************************************************************************
|
||||
* File : processing_system7_vip_v1_0_7_local_params.v
|
||||
*
|
||||
* Date : 2012-11
|
||||
*
|
||||
* Description : Parameters used in Zynq VIP
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
|
||||
/* local */
|
||||
parameter m_axi_gp0_baseaddr = 32'h4000_0000;
|
||||
parameter m_axi_gp1_baseaddr = 32'h8000_0000;
|
||||
parameter m_axi_gp0_highaddr = 32'h7FFF_FFFF;
|
||||
parameter m_axi_gp1_highaddr = 32'hBFFF_FFFF;
|
||||
|
||||
parameter addr_width = 32; // maximum address width
|
||||
parameter data_width = 32; // maximum data width.
|
||||
parameter max_chars = 128; // max characters for file name
|
||||
parameter mem_width = data_width/8; /// memory width in bytes
|
||||
parameter shft_addr_bits = clogb2(mem_width); /// Address to be right shifted
|
||||
parameter int_width = 32; //integre width
|
||||
|
||||
/* for internal read/write APIs used for data transfers */
|
||||
parameter max_burst_len = 16; /// maximum brst length on axi
|
||||
parameter max_data_width = 64; // maximum data width for internal AXI bursts
|
||||
parameter max_burst_bits = (max_data_width * max_burst_len); // maximum data width for internal AXI bursts
|
||||
parameter max_burst_bytes = (max_burst_bits)/8; // maximum data bytes in each transfer
|
||||
parameter max_burst_bytes_width = clogb2(max_burst_bytes); // maximum data width for internal AXI bursts
|
||||
|
||||
parameter max_registers = 32;
|
||||
parameter max_regs_width = clogb2(max_registers);
|
||||
|
||||
parameter REG_MEM = 2'b00, DDR_MEM = 2'b01, OCM_MEM = 2'b10, INVALID_MEM_TYPE = 2'b11;
|
||||
|
||||
/* Interrupt bits supported */
|
||||
parameter irq_width = 16;
|
||||
|
||||
/* GP Master0 & Master1 address decode */
|
||||
parameter GP_M0 = 2'b01;
|
||||
parameter GP_M1 = 2'b10;
|
||||
|
||||
parameter ALL_RANDOM= 2'b00;
|
||||
parameter ALL_ZEROS = 2'b01;
|
||||
parameter ALL_ONES = 2'b10;
|
||||
|
||||
parameter ddr_start_addr = 32'h0008_0000;
|
||||
parameter ddr_end_addr = 32'h7FFF_FFFF;
|
||||
|
||||
parameter ocm_start_addr = 32'h0000_0000;
|
||||
parameter ocm_end_addr = 32'h0003_FFFF;
|
||||
parameter high_ocm_start_addr = 32'hFFFC_0000;
|
||||
parameter high_ocm_end_addr = 32'hFFFF_FFFF;
|
||||
parameter ocm_low_addr = 32'hFFFF_0000;
|
||||
|
||||
parameter reg_start_addr = 32'hE000_0000;
|
||||
parameter reg_end_addr = 32'hF8F0_2F80;
|
||||
|
||||
|
||||
/* for Master port APIs and AXI protocol related signal widths*/
|
||||
parameter axi_burst_len = 16;
|
||||
parameter axi_len_width = clogb2(axi_burst_len);
|
||||
parameter axi_size_width = 3;
|
||||
parameter axi_brst_type_width = 2;
|
||||
parameter axi_lock_width = 2;
|
||||
parameter axi_cache_width = 4;
|
||||
parameter axi_prot_width = 3;
|
||||
parameter axi_rsp_width = 2;
|
||||
parameter axi_mgp_data_width = 32;
|
||||
parameter axi_mgp_id_width = 12;
|
||||
parameter axi_mgp_outstanding = 8;
|
||||
parameter axi_mgp_wr_id = 12'hC00;
|
||||
parameter axi_mgp_rd_id = 12'hC0C;
|
||||
parameter axi_mgp0_name = "M_AXI_GP0";
|
||||
parameter axi_mgp1_name = "M_AXI_GP1";
|
||||
parameter axi_qos_width = 4;
|
||||
parameter max_transfer_bytes = 256; // For Master APIs.
|
||||
parameter max_transfer_bytes_width = clogb2(max_transfer_bytes); // For Master APIs.
|
||||
|
||||
|
||||
/* for GP slave ports*/
|
||||
parameter axi_sgp_data_width = 32;
|
||||
parameter axi_sgp_id_width = 6;
|
||||
parameter axi_sgp_rd_outstanding = 8;
|
||||
parameter axi_sgp_wr_outstanding = 8;
|
||||
parameter axi_sgp_outstanding = axi_sgp_rd_outstanding + axi_sgp_wr_outstanding;
|
||||
parameter axi_sgp0_name = "S_AXI_GP0";
|
||||
parameter axi_sgp1_name = "S_AXI_GP1";
|
||||
|
||||
/* for ACP slave ports*/
|
||||
parameter axi_acp_data_width = 64;
|
||||
parameter axi_acp_id_width = 3;
|
||||
parameter axi_acp_rd_outstanding = 7;
|
||||
parameter axi_acp_wr_outstanding = 3;
|
||||
parameter axi_acp_outstanding = axi_acp_rd_outstanding + axi_acp_wr_outstanding;
|
||||
parameter axi_acp_name = "S_AXI_ACP";
|
||||
|
||||
/* for HP slave ports*/
|
||||
parameter axi_hp_id_width = 6;
|
||||
parameter axi_hp_outstanding = 256; /// dynamic based on RCOUNT, WCOUNT ..
|
||||
parameter axi_hp0_name = "S_AXI_HP0";
|
||||
parameter axi_hp1_name = "S_AXI_HP1";
|
||||
parameter axi_hp2_name = "S_AXI_HP2";
|
||||
parameter axi_hp3_name = "S_AXI_HP3";
|
||||
|
||||
|
||||
parameter axi_slv_excl_support = 0; // For Slave ports EXCL access is not supported
|
||||
parameter axi_mst_excl_support = 1; // For Master ports EXCL access is supported
|
||||
|
||||
/* AXI transfer types */
|
||||
parameter AXI_FIXED = 2'b00;
|
||||
parameter AXI_INCR = 2'b01;
|
||||
parameter AXI_WRAP = 2'b10;
|
||||
|
||||
/* Exclusive Access */
|
||||
parameter AXI_NRML = 2'b00;
|
||||
parameter AXI_EXCL = 2'b01;
|
||||
parameter AXI_LOCK = 2'b10;
|
||||
|
||||
/* AXI Response types */
|
||||
parameter AXI_OK = 2'b00;
|
||||
parameter AXI_EXCL_OK = 2'b01;
|
||||
parameter AXI_SLV_ERR = 2'b10;
|
||||
parameter AXI_DEC_ERR = 2'b11;
|
||||
|
||||
function automatic integer clogb2;
|
||||
input [31:0] value;
|
||||
begin
|
||||
value = value - 1;
|
||||
for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1) begin
|
||||
value = value >> 1;
|
||||
end
|
||||
end
|
||||
endfunction
|
||||
|
||||
/* needed only for AFI modules and axi_slave modules for internal WRITE FIFOs and RESP FIFOs and interconnect fifo models */
|
||||
/* WR FIFO data */
|
||||
// parameter wr_fifo_data_bits = axi_qos_width + addr_width + max_burst_bits + (max_burst_bytes_width+1);
|
||||
// parameter wr_fifo_data_bits = axi_qos_width + addr_width + max_burst_bits + (max_burst_bytes_width+1);
|
||||
// parameter wr_fifo_data_bits = ((data_bus_width/8)*axi_burst_len) + (data_bus_width*axi_burst_len) + axi_qos_width + addr_width + (max_burst_bytes_width+1);
|
||||
// parameter wr_bytes_lsb = 0;
|
||||
// parameter wr_bytes_msb = max_burst_bytes_width;
|
||||
// parameter wr_addr_lsb = wr_bytes_msb + 1;
|
||||
// parameter wr_addr_msb = wr_addr_lsb + addr_width-1;
|
||||
// parameter wr_data_lsb = wr_addr_msb + 1;
|
||||
// parameter wr_data_msb = wr_data_lsb + max_burst_bits-1;
|
||||
// parameter wr_data_msb = wr_data_lsb + (data_bus_width*axi_burst_len)-1;
|
||||
// parameter wr_qos_lsb = wr_data_msb + 1;
|
||||
// `parameter wr_qos_msb = wr_qos_lsb + axi_qos_width-1;
|
||||
|
||||
/* WR AFI FIFO data */
|
||||
/* ID - 1071:1066
|
||||
Resp - 1065:1064
|
||||
data - 1063:40
|
||||
address - 39:8
|
||||
valid_bytes - 7:0
|
||||
*/
|
||||
// parameter wr_afi_fifo_data_bits = axi_qos_width + axi_len_width + axi_hp_id_width + axi_rsp_width + max_burst_bits + addr_width + (max_burst_bytes_width+1);
|
||||
// parameter wr_afi_bytes_lsb = 0;
|
||||
// parameter wr_afi_bytes_msb = max_burst_bytes_width;
|
||||
// parameter wr_afi_addr_lsb = wr_afi_bytes_msb + 1;
|
||||
// parameter wr_afi_addr_msb = wr_afi_addr_lsb + addr_width-1;
|
||||
// parameter wr_afi_data_lsb = wr_afi_addr_msb + 1;
|
||||
// parameter wr_afi_rsp_msb = wr_afi_rsp_lsb + axi_rsp_width-1;
|
||||
// parameter wr_afi_id_lsb = wr_afi_rsp_msb + 1;
|
||||
// parameter wr_afi_id_msb = wr_afi_id_lsb + axi_hp_id_width-1;
|
||||
// parameter wr_afi_ln_lsb = wr_afi_id_msb + 1;
|
||||
// parameter wr_afi_ln_msb = wr_afi_ln_lsb + axi_len_width-1;
|
||||
// parameter wr_afi_qos_lsb = wr_afi_ln_msb + 1;
|
||||
// parameter wr_afi_qos_msb = wr_afi_qos_lsb + axi_qos_width-1;
|
||||
|
||||
|
||||
parameter afi_fifo_size = 1024; /// AFI FIFO is stored as 1024-bytes
|
||||
parameter afi_fifo_databits = 64; /// AFI FIFO is stored as 64-bits i.e 8 bytes per location (8 bytes(64-bits) * 128 locations = 1024 bytes)
|
||||
parameter afi_fifo_locations= afi_fifo_size/(afi_fifo_databits/8); /// AFI FIFO is stored as 128-locations with 8 bytes per location
|
||||
|
||||
/* for interconnect fifo models */
|
||||
parameter intr_max_outstanding = 8;
|
||||
parameter intr_cnt_width = clogb2(intr_max_outstanding)+1;
|
||||
parameter rd_info_bits = addr_width + axi_size_width + axi_brst_type_width + axi_len_width + axi_hp_id_width + axi_rsp_width + (max_burst_bytes_width+1);
|
||||
parameter rd_afi_fifo_bits = max_burst_bits + rd_info_bits ;
|
||||
|
||||
//Read Burst Data, addr, size, burst, len, RID, RRESP, valid bytes
|
||||
parameter rd_afi_bytes_lsb = 0;
|
||||
parameter rd_afi_bytes_msb = max_burst_bytes_width;
|
||||
parameter rd_afi_rsp_lsb = rd_afi_bytes_msb + 1;
|
||||
parameter rd_afi_rsp_msb = rd_afi_rsp_lsb + axi_rsp_width-1;
|
||||
parameter rd_afi_id_lsb = rd_afi_rsp_msb + 1;
|
||||
parameter rd_afi_id_msb = rd_afi_id_lsb + axi_hp_id_width-1;
|
||||
parameter rd_afi_ln_lsb = rd_afi_id_msb + 1;
|
||||
parameter rd_afi_ln_msb = rd_afi_ln_lsb + axi_len_width-1;
|
||||
parameter rd_afi_brst_lsb = rd_afi_ln_msb + 1;
|
||||
parameter rd_afi_brst_msb = rd_afi_brst_lsb + axi_brst_type_width-1;
|
||||
parameter rd_afi_siz_lsb = rd_afi_brst_msb + 1;
|
||||
parameter rd_afi_siz_msb = rd_afi_siz_lsb + axi_size_width-1;
|
||||
parameter rd_afi_addr_lsb = rd_afi_siz_msb + 1;
|
||||
parameter rd_afi_addr_msb = rd_afi_addr_lsb + addr_width-1;
|
||||
parameter rd_afi_data_lsb = rd_afi_addr_msb + 1;
|
||||
parameter rd_afi_data_msb = rd_afi_data_lsb + max_burst_bits-1;
|
||||
|
||||
|
||||
/* Latency types */
|
||||
parameter BEST_CASE = 0;
|
||||
parameter AVG_CASE = 1;
|
||||
parameter WORST_CASE = 2;
|
||||
parameter RANDOM_CASE = 3;
|
||||
|
||||
/* Latency Parameters ACP */
|
||||
parameter acp_wr_min = 21;
|
||||
parameter acp_wr_avg = 16;
|
||||
parameter acp_wr_max = 27;
|
||||
parameter acp_rd_min = 34;
|
||||
parameter acp_rd_avg = 125;
|
||||
parameter acp_rd_max = 130;
|
||||
|
||||
/* Latency Parameters GP */
|
||||
parameter gp_wr_min = 21;
|
||||
parameter gp_wr_avg = 16;
|
||||
parameter gp_wr_max = 46;
|
||||
parameter gp_rd_min = 38;
|
||||
parameter gp_rd_avg = 125;
|
||||
parameter gp_rd_max = 130;
|
||||
|
||||
/* Latency Parameters HP */
|
||||
parameter afi_wr_min = 37;
|
||||
parameter afi_wr_avg = 41;
|
||||
parameter afi_wr_max = 42;
|
||||
parameter afi_rd_min = 41;
|
||||
parameter afi_rd_avg = 221;
|
||||
parameter afi_rd_max = 229;
|
||||
|
||||
/* ID VALID and INVALID */
|
||||
parameter secure_access_enabled = 0;
|
||||
parameter id_invalid = 0;
|
||||
parameter id_valid = 1;
|
||||
|
||||
/* Display */
|
||||
parameter DISP_INFO = "*ZYNQ_VIP_INFO";
|
||||
parameter DISP_WARN = "*ZYNQ_VIP_WARNING";
|
||||
parameter DISP_ERR = "*ZYNQ_VIP_ERROR";
|
||||
parameter DISP_INT_INFO = "ZYNQ_VIP_INT_INFO";
|
||||
|
||||
parameter all_strb_valid = 2048'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF;
|
||||
|
||||
+2924
File diff suppressed because it is too large
Load Diff
+10519
File diff suppressed because it is too large
Load Diff
+433
@@ -0,0 +1,433 @@
|
||||
/*****************************************************************************
|
||||
* File : processing_system7_vip_v1_0_7_unused_ports.v
|
||||
*
|
||||
* Date : 2012-11
|
||||
*
|
||||
* Description : Semantic checks for unused ports.
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
/* CAN */
|
||||
assign CAN0_PHY_TX = 0;
|
||||
assign CAN1_PHY_TX = 0;
|
||||
always @(CAN0_PHY_RX or CAN1_PHY_RX)
|
||||
begin
|
||||
if(CAN0_PHY_RX | CAN1_PHY_RX)
|
||||
$display("[%0d] : %0s : CAN Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* ETHERNET */
|
||||
/* ------------------------------------------- */
|
||||
|
||||
assign ENET0_GMII_TX_EN = 0;
|
||||
assign ENET0_GMII_TX_ER = 0;
|
||||
assign ENET0_MDIO_MDC = 0;
|
||||
assign ENET0_MDIO_O = 0; /// confirm
|
||||
assign ENET0_MDIO_T = 0;
|
||||
assign ENET0_PTP_DELAY_REQ_RX = 0;
|
||||
assign ENET0_PTP_DELAY_REQ_TX = 0;
|
||||
assign ENET0_PTP_PDELAY_REQ_RX = 0;
|
||||
assign ENET0_PTP_PDELAY_REQ_TX = 0;
|
||||
assign ENET0_PTP_PDELAY_RESP_RX = 0;
|
||||
assign ENET0_PTP_PDELAY_RESP_TX = 0;
|
||||
assign ENET0_PTP_SYNC_FRAME_RX = 0;
|
||||
assign ENET0_PTP_SYNC_FRAME_TX = 0;
|
||||
assign ENET0_SOF_RX = 0;
|
||||
assign ENET0_SOF_TX = 0;
|
||||
assign ENET0_GMII_TXD = 0;
|
||||
always@(ENET0_GMII_COL or ENET0_GMII_CRS or ENET0_EXT_INTIN or
|
||||
ENET0_GMII_RX_CLK or ENET0_GMII_RX_DV or ENET0_GMII_RX_ER or
|
||||
ENET0_GMII_TX_CLK or ENET0_MDIO_I or ENET0_GMII_RXD)
|
||||
begin
|
||||
if(ENET0_GMII_COL | ENET0_GMII_CRS | ENET0_EXT_INTIN |
|
||||
ENET0_GMII_RX_CLK | ENET0_GMII_RX_DV | ENET0_GMII_RX_ER |
|
||||
ENET0_GMII_TX_CLK | ENET0_MDIO_I )
|
||||
$display("[%0d] : %0s : ETHERNET Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
assign ENET1_GMII_TX_EN = 0;
|
||||
assign ENET1_GMII_TX_ER = 0;
|
||||
assign ENET1_MDIO_MDC = 0;
|
||||
assign ENET1_MDIO_O = 0;/// confirm
|
||||
assign ENET1_MDIO_T = 0;
|
||||
assign ENET1_PTP_DELAY_REQ_RX = 0;
|
||||
assign ENET1_PTP_DELAY_REQ_TX = 0;
|
||||
assign ENET1_PTP_PDELAY_REQ_RX = 0;
|
||||
assign ENET1_PTP_PDELAY_REQ_TX = 0;
|
||||
assign ENET1_PTP_PDELAY_RESP_RX = 0;
|
||||
assign ENET1_PTP_PDELAY_RESP_TX = 0;
|
||||
assign ENET1_PTP_SYNC_FRAME_RX = 0;
|
||||
assign ENET1_PTP_SYNC_FRAME_TX = 0;
|
||||
assign ENET1_SOF_RX = 0;
|
||||
assign ENET1_SOF_TX = 0;
|
||||
assign ENET1_GMII_TXD = 0;
|
||||
always@(ENET1_GMII_COL or ENET1_GMII_CRS or ENET1_EXT_INTIN or
|
||||
ENET1_GMII_RX_CLK or ENET1_GMII_RX_DV or ENET1_GMII_RX_ER or
|
||||
ENET1_GMII_TX_CLK or ENET1_MDIO_I or ENET1_GMII_RXD)
|
||||
begin
|
||||
if(ENET1_GMII_COL | ENET1_GMII_CRS | ENET1_EXT_INTIN |
|
||||
ENET1_GMII_RX_CLK | ENET1_GMII_RX_DV | ENET1_GMII_RX_ER |
|
||||
ENET1_GMII_TX_CLK | ENET1_MDIO_I )
|
||||
$display("[%0d] : %0s : ETHERNET Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* GPIO */
|
||||
/* ------------------------------------------- */
|
||||
|
||||
assign GPIO_O = 0;
|
||||
assign GPIO_T = 0;
|
||||
always@(GPIO_I)
|
||||
begin
|
||||
// if(GPIO_I !== 0)
|
||||
// $display("[%0d] : %0s : GPIO Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* I2C */
|
||||
/* ------------------------------------------- */
|
||||
|
||||
assign I2C0_SDA_O = 0;
|
||||
assign I2C0_SDA_T = 0;
|
||||
assign I2C0_SCL_O = 0;
|
||||
assign I2C0_SCL_T = 0;
|
||||
assign I2C1_SDA_O = 0;
|
||||
assign I2C1_SDA_T = 0;
|
||||
assign I2C1_SCL_O = 0;
|
||||
assign I2C1_SCL_T = 0;
|
||||
always@(I2C0_SDA_I or I2C0_SCL_I or I2C1_SDA_I or I2C1_SCL_I )
|
||||
begin
|
||||
if(I2C0_SDA_I | I2C0_SCL_I | I2C1_SDA_I | I2C1_SCL_I)
|
||||
$display("[%0d] : %0s : I2C Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* JTAG */
|
||||
/* ------------------------------------------- */
|
||||
|
||||
assign PJTAG_TD_T = 0;
|
||||
assign PJTAG_TD_O = 0;
|
||||
always@(PJTAG_TCK or PJTAG_TMS or PJTAG_TD_I)
|
||||
begin
|
||||
if(PJTAG_TCK | PJTAG_TMS | PJTAG_TD_I)
|
||||
$display("[%0d] : %0s : JTAG Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* SDIO */
|
||||
/* ------------------------------------------- */
|
||||
|
||||
assign SDIO0_CLK = 0;
|
||||
assign SDIO0_CMD_O = 0;
|
||||
assign SDIO0_CMD_T = 0;
|
||||
assign SDIO0_DATA_O = 0;
|
||||
assign SDIO0_DATA_T = 0;
|
||||
assign SDIO0_LED = 0;
|
||||
assign SDIO0_BUSPOW = 0;
|
||||
assign SDIO0_BUSVOLT = 0;
|
||||
always@(SDIO0_CLK_FB or SDIO0_CMD_I or SDIO0_DATA_I or SDIO0_CDN or SDIO0_WP )
|
||||
begin
|
||||
if(SDIO0_CLK_FB | SDIO0_CMD_I | SDIO0_CDN | SDIO0_WP )
|
||||
$display("[%0d] : %0s : SDIO Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
assign SDIO1_CLK = 0;
|
||||
assign SDIO1_CMD_O = 0;
|
||||
assign SDIO1_CMD_T = 0;
|
||||
assign SDIO1_DATA_O = 0;
|
||||
assign SDIO1_DATA_T = 0;
|
||||
assign SDIO1_LED = 0;
|
||||
assign SDIO1_BUSPOW = 0;
|
||||
assign SDIO1_BUSVOLT = 0;
|
||||
always@(SDIO1_CLK_FB or SDIO1_CMD_I or SDIO1_DATA_I or SDIO1_CDN or SDIO1_WP )
|
||||
begin
|
||||
if(SDIO1_CLK_FB | SDIO1_CMD_I | SDIO1_CDN | SDIO1_WP )
|
||||
$display("[%0d] : %0s : SDIO Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* SPI */
|
||||
/* ------------------------------------------- */
|
||||
|
||||
assign SPI0_SCLK_O = 0;
|
||||
assign SPI0_SCLK_T = 0;
|
||||
assign SPI0_MOSI_O = 0;
|
||||
assign SPI0_MOSI_T = 0;
|
||||
assign SPI0_MISO_O = 0;
|
||||
assign SPI0_MISO_T = 0;
|
||||
assign SPI0_SS_O = 0; /// confirm
|
||||
assign SPI0_SS1_O = 0;/// confirm
|
||||
assign SPI0_SS2_O = 0;/// confirm
|
||||
assign SPI0_SS_T = 0;
|
||||
always@(SPI0_SCLK_I or SPI0_MOSI_I or SPI0_MISO_I or SPI0_SS_I)
|
||||
begin
|
||||
if(SPI0_SCLK_I | SPI0_MOSI_I | SPI0_MISO_I | SPI0_SS_I)
|
||||
$display("[%0d] : %0s : SPI Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
assign SPI1_SCLK_O = 0;
|
||||
assign SPI1_SCLK_T = 0;
|
||||
assign SPI1_MOSI_O = 0;
|
||||
assign SPI1_MOSI_T = 0;
|
||||
assign SPI1_MISO_O = 0;
|
||||
assign SPI1_MISO_T = 0;
|
||||
assign SPI1_SS_O = 0;
|
||||
assign SPI1_SS1_O = 0;
|
||||
assign SPI1_SS2_O = 0;
|
||||
assign SPI1_SS_T = 0;
|
||||
always@(SPI1_SCLK_I or SPI1_MOSI_I or SPI1_MISO_I or SPI1_SS_I)
|
||||
begin
|
||||
if(SPI1_SCLK_I | SPI1_MOSI_I | SPI1_MISO_I | SPI1_SS_I)
|
||||
$display("[%0d] : %0s : SPI Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* UART */
|
||||
/* ------------------------------------------- */
|
||||
/// confirm
|
||||
assign UART0_DTRN = 0;
|
||||
assign UART0_RTSN = 0;
|
||||
assign UART0_TX = 0;
|
||||
always@(UART0_CTSN or UART0_DCDN or UART0_DSRN or UART0_RIN or UART0_RX)
|
||||
begin
|
||||
if(UART0_CTSN | UART0_DCDN | UART0_DSRN | UART0_RIN | UART0_RX)
|
||||
$display("[%0d] : %0s : UART Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
assign UART1_DTRN = 0;
|
||||
assign UART1_RTSN = 0;
|
||||
assign UART1_TX = 0;
|
||||
always@(UART1_CTSN or UART1_DCDN or UART1_DSRN or UART1_RIN or UART1_RX)
|
||||
begin
|
||||
if(UART1_CTSN | UART1_DCDN | UART1_DSRN | UART1_RIN | UART1_RX)
|
||||
$display("[%0d] : %0s : UART Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* TTC */
|
||||
/* ------------------------------------------- */
|
||||
|
||||
assign TTC0_WAVE0_OUT = 0;
|
||||
assign TTC0_WAVE1_OUT = 0;
|
||||
assign TTC0_WAVE2_OUT = 0;
|
||||
always@(TTC0_CLK0_IN or TTC0_CLK1_IN or TTC0_CLK2_IN)
|
||||
begin
|
||||
if(TTC0_CLK0_IN | TTC0_CLK1_IN | TTC0_CLK2_IN)
|
||||
$display("[%0d] : %0s : TTC Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
assign TTC1_WAVE0_OUT = 0;
|
||||
assign TTC1_WAVE1_OUT = 0;
|
||||
assign TTC1_WAVE2_OUT = 0;
|
||||
always@(TTC1_CLK0_IN or TTC1_CLK1_IN or TTC1_CLK2_IN)
|
||||
begin
|
||||
if(TTC1_CLK0_IN | TTC1_CLK1_IN | TTC1_CLK2_IN)
|
||||
$display("[%0d] : %0s : TTC Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* WDT */
|
||||
/* ------------------------------------------- */
|
||||
|
||||
assign WDT_RST_OUT = 0;
|
||||
always@(WDT_CLK_IN)
|
||||
begin
|
||||
if(WDT_CLK_IN)
|
||||
$display("[%0d] : %0s : WDT Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* TRACE */
|
||||
/* ------------------------------------------- */
|
||||
|
||||
assign TRACE_CTL = 0;
|
||||
assign TRACE_DATA = 0;
|
||||
always@(TRACE_CLK)
|
||||
begin
|
||||
if(TRACE_CLK)
|
||||
$display("[%0d] : %0s : TRACE Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* USB */
|
||||
/* ------------------------------------------- */
|
||||
assign USB0_PORT_INDCTL = 0;
|
||||
assign USB0_VBUS_PWRSELECT = 0;
|
||||
always@(USB0_VBUS_PWRFAULT)
|
||||
begin
|
||||
if(USB0_VBUS_PWRFAULT)
|
||||
$display("[%0d] : %0s : USB Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
assign USB1_PORT_INDCTL = 0;
|
||||
assign USB1_VBUS_PWRSELECT = 0;
|
||||
always@(USB1_VBUS_PWRFAULT)
|
||||
begin
|
||||
if(USB1_VBUS_PWRFAULT)
|
||||
$display("[%0d] : %0s : USB Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
always@(SRAM_INTIN)
|
||||
begin
|
||||
if(SRAM_INTIN)
|
||||
$display("[%0d] : %0s : SRAM_INTIN is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* DMA */
|
||||
/* ------------------------------------------- */
|
||||
|
||||
assign DMA0_DATYPE = 0;
|
||||
assign DMA0_DAVALID = 0;
|
||||
assign DMA0_DRREADY = 0;
|
||||
assign DMA0_RSTN = 0;
|
||||
always@(DMA0_ACLK or DMA0_DAREADY or DMA0_DRLAST or DMA0_DRVALID or DMA0_DRTYPE)
|
||||
begin
|
||||
if(DMA0_ACLK | DMA0_DAREADY | DMA0_DRLAST | DMA0_DRVALID | DMA0_DRTYPE)
|
||||
$display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
assign DMA1_DATYPE = 0;
|
||||
assign DMA1_DAVALID = 0;
|
||||
assign DMA1_DRREADY = 0;
|
||||
assign DMA1_RSTN = 0;
|
||||
always@(DMA1_ACLK or DMA1_DAREADY or DMA1_DRLAST or DMA1_DRVALID or DMA1_DRTYPE)
|
||||
begin
|
||||
if(DMA1_ACLK | DMA1_DAREADY | DMA1_DRLAST | DMA1_DRVALID | DMA1_DRTYPE)
|
||||
$display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
assign DMA2_DATYPE = 0;
|
||||
assign DMA2_DAVALID = 0;
|
||||
assign DMA2_DRREADY = 0;
|
||||
assign DMA2_RSTN = 0;
|
||||
always@(DMA2_ACLK or DMA2_DAREADY or DMA2_DRLAST or DMA2_DRVALID or DMA2_DRTYPE)
|
||||
begin
|
||||
if(DMA2_ACLK | DMA2_DAREADY | DMA2_DRLAST | DMA2_DRVALID | DMA2_DRTYPE)
|
||||
$display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
assign DMA3_DATYPE = 0;
|
||||
assign DMA3_DAVALID = 0;
|
||||
assign DMA3_DRREADY = 0;
|
||||
assign DMA3_RSTN = 0;
|
||||
always@(DMA3_ACLK or DMA3_DAREADY or DMA3_DRLAST or DMA3_DRVALID or DMA3_DRTYPE)
|
||||
begin
|
||||
if(DMA3_ACLK | DMA3_DAREADY | DMA3_DRLAST | DMA3_DRVALID | DMA3_DRTYPE)
|
||||
$display("[%0d] : %0s : DMA Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* FTM */
|
||||
/* ------------------------------------------- */
|
||||
|
||||
assign FTMT_F2P_TRIGACK = 0;
|
||||
assign FTMT_P2F_TRIG = 0;
|
||||
assign FTMT_P2F_DEBUG = 0;
|
||||
always@(FTMD_TRACEIN_DATA or FTMD_TRACEIN_VALID or FTMD_TRACEIN_CLK or
|
||||
FTMD_TRACEIN_ATID or FTMT_F2P_TRIG or FTMT_F2P_DEBUG or FTMT_P2F_TRIGACK)
|
||||
begin
|
||||
if(FTMD_TRACEIN_DATA | FTMD_TRACEIN_VALID | FTMD_TRACEIN_CLK | FTMD_TRACEIN_ATID | FTMT_F2P_TRIG | FTMT_F2P_DEBUG | FTMT_P2F_TRIGACK)
|
||||
$display("[%0d] : %0s : FTM Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* EVENT */
|
||||
/* ------------------------------------------- */
|
||||
|
||||
assign EVENT_EVENTO = 0;
|
||||
assign EVENT_STANDBYWFE = 0;
|
||||
assign EVENT_STANDBYWFI = 0;
|
||||
always@(EVENT_EVENTI)
|
||||
begin
|
||||
if(EVENT_EVENTI)
|
||||
$display("[%0d] : %0s : EVENT Interface is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* MIO */
|
||||
/* ------------------------------------------- */
|
||||
|
||||
always@(MIO)
|
||||
begin
|
||||
// if(MIO !== 0)
|
||||
// $display("[%0d] : %0s : MIO is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* FCLK_TRIG */
|
||||
/* ------------------------------------------- */
|
||||
|
||||
always@(FCLK_CLKTRIG3_N or FCLK_CLKTRIG2_N or FCLK_CLKTRIG1_N or FCLK_CLKTRIG0_N )
|
||||
begin
|
||||
if(FCLK_CLKTRIG3_N | FCLK_CLKTRIG2_N | FCLK_CLKTRIG1_N | FCLK_CLKTRIG0_N )
|
||||
$display("[%0d] : %0s : FCLK_TRIG is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* MISC */
|
||||
/* ------------------------------------------- */
|
||||
|
||||
always@(FPGA_IDLE_N)
|
||||
begin
|
||||
if(FPGA_IDLE_N)
|
||||
$display("[%0d] : %0s : FPGA_IDLE_N is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
always@(DDR_ARB)
|
||||
begin
|
||||
// if(DDR_ARB !== 0)
|
||||
// $display("[%0d] : %0s : DDR_ARB is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
always@(Core0_nFIQ or Core0_nIRQ or Core1_nFIQ or Core1_nIRQ )
|
||||
begin
|
||||
if(Core0_nFIQ | Core0_nIRQ | Core1_nFIQ | Core1_nIRQ)
|
||||
$display("[%0d] : %0s : CORE FIQ,IRQ is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* DDR */
|
||||
/* ------------------------------------------- */
|
||||
|
||||
assign DDR_WEB = 0;
|
||||
always@(DDR_Clk or DDR_CS_n)
|
||||
begin
|
||||
if(!DDR_CS_n)
|
||||
$display("[%0d] : %0s : EXTERNAL DDR is not supported.",$time, DISP_ERR);
|
||||
end
|
||||
|
||||
/* ------------------------------------------- */
|
||||
/* IRQ_P2F */
|
||||
/* ------------------------------------------- */
|
||||
|
||||
assign IRQ_P2F_DMAC_ABORT = 0;
|
||||
assign IRQ_P2F_DMAC0 = 0;
|
||||
assign IRQ_P2F_DMAC1 = 0;
|
||||
assign IRQ_P2F_DMAC2 = 0;
|
||||
assign IRQ_P2F_DMAC3 = 0;
|
||||
assign IRQ_P2F_DMAC4 = 0;
|
||||
assign IRQ_P2F_DMAC5 = 0;
|
||||
assign IRQ_P2F_DMAC6 = 0;
|
||||
assign IRQ_P2F_DMAC7 = 0;
|
||||
assign IRQ_P2F_SMC = 0;
|
||||
assign IRQ_P2F_QSPI = 0;
|
||||
assign IRQ_P2F_CTI = 0;
|
||||
assign IRQ_P2F_GPIO = 0;
|
||||
assign IRQ_P2F_USB0 = 0;
|
||||
assign IRQ_P2F_ENET0 = 0;
|
||||
assign IRQ_P2F_ENET_WAKE0 = 0;
|
||||
assign IRQ_P2F_SDIO0 = 0;
|
||||
assign IRQ_P2F_I2C0 = 0;
|
||||
assign IRQ_P2F_SPI0 = 0;
|
||||
assign IRQ_P2F_UART0 = 0;
|
||||
assign IRQ_P2F_CAN0 = 0;
|
||||
assign IRQ_P2F_USB1 = 0;
|
||||
assign IRQ_P2F_ENET1 = 0;
|
||||
assign IRQ_P2F_ENET_WAKE1 = 0;
|
||||
assign IRQ_P2F_SDIO1 = 0;
|
||||
assign IRQ_P2F_I2C1 = 0;
|
||||
assign IRQ_P2F_SPI1 = 0;
|
||||
assign IRQ_P2F_UART1 = 0;
|
||||
assign IRQ_P2F_CAN1 = 0;
|
||||
+13831
File diff suppressed because it is too large
Load Diff
+4274
File diff suppressed because it is too large
Load Diff
+409
@@ -0,0 +1,409 @@
|
||||
//-----------------------------------------------------------------------------
|
||||
//-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
|
||||
//--
|
||||
//-- This file contains confidential and proprietary information
|
||||
//-- of Xilinx, Inc. and is protected under U.S. and
|
||||
//-- international copyright and other intellectual property
|
||||
//-- laws.
|
||||
//--
|
||||
//-- DISCLAIMER
|
||||
//-- This disclaimer is not a license and does not grant any
|
||||
//-- rights to the materials distributed herewith. Except as
|
||||
//-- otherwise provided in a valid license issued to you by
|
||||
//-- Xilinx, and to the maximum extent permitted by applicable
|
||||
//-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
//-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
//-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
//-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
//-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
//-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
//-- including negligence, or under any other theory of
|
||||
//-- liability) for any loss or damage of any kind or nature
|
||||
//-- related to, arising under or in connection with these
|
||||
//-- materials, including for any direct, or any indirect,
|
||||
//-- special, incidental, or consequential loss or damage
|
||||
//-- (including loss of data, profits, goodwill, or any type of
|
||||
//-- loss or damage suffered as a result of any action brought
|
||||
//-- by a third party) even if such damage or loss was
|
||||
//-- reasonably foreseeable or Xilinx had been advised of the
|
||||
//-- possibility of the same.
|
||||
//--
|
||||
//-- CRITICAL APPLICATIONS
|
||||
//-- Xilinx products are not designed or intended to be fail-
|
||||
//-- safe, or for use in any application requiring fail-safe
|
||||
//-- performance, such as life-support or safety devices or
|
||||
//-- systems, Class III medical devices, nuclear facilities,
|
||||
//-- applications related to the deployment of airbags, or any
|
||||
//-- other applications that could lead to death, personal
|
||||
//-- injury, or severe property or environmental damage
|
||||
//-- (individually and collectively, "Critical
|
||||
//-- Applications"). Customer assumes the sole risk and
|
||||
//-- liability of any use of Xilinx products in Critical
|
||||
//-- Applications, subject only to applicable laws and
|
||||
//-- regulations governing limitations on product liability.
|
||||
//--
|
||||
//-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
//-- PART OF THIS FILE AT ALL TIMES.
|
||||
//-----------------------------------------------------------------------------
|
||||
//
|
||||
// Description: ACP Transaction Checker
|
||||
//
|
||||
// Check for optimized ACP transactions and flag if they are broken.
|
||||
//
|
||||
//
|
||||
//
|
||||
// Verilog-standard: Verilog 2001
|
||||
//--------------------------------------------------------------------------
|
||||
//
|
||||
// Structure:
|
||||
// atc
|
||||
// aw_atc
|
||||
// w_atc
|
||||
// b_atc
|
||||
//
|
||||
//--------------------------------------------------------------------------
|
||||
`timescale 1ps/1ps
|
||||
`default_nettype none
|
||||
|
||||
module processing_system7_v5_5_atc #
|
||||
(
|
||||
parameter C_FAMILY = "rtl",
|
||||
// FPGA Family. Current version: virtex6, spartan6 or later.
|
||||
parameter integer C_AXI_ID_WIDTH = 4,
|
||||
// Width of all ID signals on SI and MI side of checker.
|
||||
// Range: >= 1.
|
||||
parameter integer C_AXI_ADDR_WIDTH = 32,
|
||||
// Width of all ADDR signals on SI and MI side of checker.
|
||||
// Range: 32.
|
||||
parameter integer C_AXI_DATA_WIDTH = 64,
|
||||
// Width of all DATA signals on SI and MI side of checker.
|
||||
// Range: 64.
|
||||
parameter integer C_AXI_AWUSER_WIDTH = 1,
|
||||
// Width of AWUSER signals.
|
||||
// Range: >= 1.
|
||||
parameter integer C_AXI_ARUSER_WIDTH = 1,
|
||||
// Width of ARUSER signals.
|
||||
// Range: >= 1.
|
||||
parameter integer C_AXI_WUSER_WIDTH = 1,
|
||||
// Width of WUSER signals.
|
||||
// Range: >= 1.
|
||||
parameter integer C_AXI_RUSER_WIDTH = 1,
|
||||
// Width of RUSER signals.
|
||||
// Range: >= 1.
|
||||
parameter integer C_AXI_BUSER_WIDTH = 1
|
||||
// Width of BUSER signals.
|
||||
// Range: >= 1.
|
||||
)
|
||||
(
|
||||
// Global Signals
|
||||
input wire ACLK,
|
||||
input wire ARESETN,
|
||||
|
||||
// Slave Interface Write Address Ports
|
||||
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
|
||||
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
|
||||
input wire [4-1:0] S_AXI_AWLEN,
|
||||
input wire [3-1:0] S_AXI_AWSIZE,
|
||||
input wire [2-1:0] S_AXI_AWBURST,
|
||||
input wire [2-1:0] S_AXI_AWLOCK,
|
||||
input wire [4-1:0] S_AXI_AWCACHE,
|
||||
input wire [3-1:0] S_AXI_AWPROT,
|
||||
input wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER,
|
||||
input wire S_AXI_AWVALID,
|
||||
output wire S_AXI_AWREADY,
|
||||
// Slave Interface Write Data Ports
|
||||
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID,
|
||||
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
|
||||
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
|
||||
input wire S_AXI_WLAST,
|
||||
input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
|
||||
input wire S_AXI_WVALID,
|
||||
output wire S_AXI_WREADY,
|
||||
// Slave Interface Write Response Ports
|
||||
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
|
||||
output wire [2-1:0] S_AXI_BRESP,
|
||||
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
|
||||
output wire S_AXI_BVALID,
|
||||
input wire S_AXI_BREADY,
|
||||
// Slave Interface Read Address Ports
|
||||
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
|
||||
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR,
|
||||
input wire [4-1:0] S_AXI_ARLEN,
|
||||
input wire [3-1:0] S_AXI_ARSIZE,
|
||||
input wire [2-1:0] S_AXI_ARBURST,
|
||||
input wire [2-1:0] S_AXI_ARLOCK,
|
||||
input wire [4-1:0] S_AXI_ARCACHE,
|
||||
input wire [3-1:0] S_AXI_ARPROT,
|
||||
input wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER,
|
||||
input wire S_AXI_ARVALID,
|
||||
output wire S_AXI_ARREADY,
|
||||
// Slave Interface Read Data Ports
|
||||
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID,
|
||||
output wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
|
||||
output wire [2-1:0] S_AXI_RRESP,
|
||||
output wire S_AXI_RLAST,
|
||||
output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
|
||||
output wire S_AXI_RVALID,
|
||||
input wire S_AXI_RREADY,
|
||||
|
||||
// Master Interface Write Address Port
|
||||
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID,
|
||||
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
|
||||
output wire [4-1:0] M_AXI_AWLEN,
|
||||
output wire [3-1:0] M_AXI_AWSIZE,
|
||||
output wire [2-1:0] M_AXI_AWBURST,
|
||||
output wire [2-1:0] M_AXI_AWLOCK,
|
||||
output wire [4-1:0] M_AXI_AWCACHE,
|
||||
output wire [3-1:0] M_AXI_AWPROT,
|
||||
output wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER,
|
||||
output wire M_AXI_AWVALID,
|
||||
input wire M_AXI_AWREADY,
|
||||
// Master Interface Write Data Ports
|
||||
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID,
|
||||
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
|
||||
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
|
||||
output wire M_AXI_WLAST,
|
||||
output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
|
||||
output wire M_AXI_WVALID,
|
||||
input wire M_AXI_WREADY,
|
||||
// Master Interface Write Response Ports
|
||||
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
|
||||
input wire [2-1:0] M_AXI_BRESP,
|
||||
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
|
||||
input wire M_AXI_BVALID,
|
||||
output wire M_AXI_BREADY,
|
||||
// Master Interface Read Address Port
|
||||
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID,
|
||||
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR,
|
||||
output wire [4-1:0] M_AXI_ARLEN,
|
||||
output wire [3-1:0] M_AXI_ARSIZE,
|
||||
output wire [2-1:0] M_AXI_ARBURST,
|
||||
output wire [2-1:0] M_AXI_ARLOCK,
|
||||
output wire [4-1:0] M_AXI_ARCACHE,
|
||||
output wire [3-1:0] M_AXI_ARPROT,
|
||||
output wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER,
|
||||
output wire M_AXI_ARVALID,
|
||||
input wire M_AXI_ARREADY,
|
||||
// Master Interface Read Data Ports
|
||||
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID,
|
||||
input wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
|
||||
input wire [2-1:0] M_AXI_RRESP,
|
||||
input wire M_AXI_RLAST,
|
||||
input wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER,
|
||||
input wire M_AXI_RVALID,
|
||||
output wire M_AXI_RREADY,
|
||||
|
||||
output wire ERROR_TRIGGER,
|
||||
output wire [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
|
||||
);
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Functions
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Local params
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
localparam C_FIFO_DEPTH_LOG = 4;
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Internal signals
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Internal reset.
|
||||
reg ARESET;
|
||||
|
||||
// AW->W command queue signals.
|
||||
wire cmd_w_valid;
|
||||
wire cmd_w_check;
|
||||
wire [C_AXI_ID_WIDTH-1:0] cmd_w_id;
|
||||
wire cmd_w_ready;
|
||||
|
||||
// W->B command queue signals.
|
||||
wire cmd_b_push;
|
||||
wire cmd_b_error;
|
||||
wire [C_AXI_ID_WIDTH-1:0] cmd_b_id;
|
||||
wire cmd_b_full;
|
||||
wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr;
|
||||
wire cmd_b_ready;
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Handle Internal Reset
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
always @ (posedge ACLK) begin
|
||||
ARESET <= !ARESETN;
|
||||
end
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Handle Write Channels (AW/W/B)
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Write Address Channel.
|
||||
processing_system7_v5_5_aw_atc #
|
||||
(
|
||||
.C_FAMILY (C_FAMILY),
|
||||
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
|
||||
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
|
||||
.C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH),
|
||||
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
|
||||
) write_addr_inst
|
||||
(
|
||||
// Global Signals
|
||||
.ARESET (ARESET),
|
||||
.ACLK (ACLK),
|
||||
|
||||
// Command Interface (Out)
|
||||
.cmd_w_valid (cmd_w_valid),
|
||||
.cmd_w_check (cmd_w_check),
|
||||
.cmd_w_id (cmd_w_id),
|
||||
.cmd_w_ready (cmd_w_ready),
|
||||
.cmd_b_addr (cmd_b_addr),
|
||||
.cmd_b_ready (cmd_b_ready),
|
||||
|
||||
// Slave Interface Write Address Ports
|
||||
.S_AXI_AWID (S_AXI_AWID),
|
||||
.S_AXI_AWADDR (S_AXI_AWADDR),
|
||||
.S_AXI_AWLEN (S_AXI_AWLEN),
|
||||
.S_AXI_AWSIZE (S_AXI_AWSIZE),
|
||||
.S_AXI_AWBURST (S_AXI_AWBURST),
|
||||
.S_AXI_AWLOCK (S_AXI_AWLOCK),
|
||||
.S_AXI_AWCACHE (S_AXI_AWCACHE),
|
||||
.S_AXI_AWPROT (S_AXI_AWPROT),
|
||||
.S_AXI_AWUSER (S_AXI_AWUSER),
|
||||
.S_AXI_AWVALID (S_AXI_AWVALID),
|
||||
.S_AXI_AWREADY (S_AXI_AWREADY),
|
||||
|
||||
// Master Interface Write Address Port
|
||||
.M_AXI_AWID (M_AXI_AWID),
|
||||
.M_AXI_AWADDR (M_AXI_AWADDR),
|
||||
.M_AXI_AWLEN (M_AXI_AWLEN),
|
||||
.M_AXI_AWSIZE (M_AXI_AWSIZE),
|
||||
.M_AXI_AWBURST (M_AXI_AWBURST),
|
||||
.M_AXI_AWLOCK (M_AXI_AWLOCK),
|
||||
.M_AXI_AWCACHE (M_AXI_AWCACHE),
|
||||
.M_AXI_AWPROT (M_AXI_AWPROT),
|
||||
.M_AXI_AWUSER (M_AXI_AWUSER),
|
||||
.M_AXI_AWVALID (M_AXI_AWVALID),
|
||||
.M_AXI_AWREADY (M_AXI_AWREADY)
|
||||
);
|
||||
|
||||
// Write Data channel.
|
||||
processing_system7_v5_5_w_atc #
|
||||
(
|
||||
.C_FAMILY (C_FAMILY),
|
||||
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
|
||||
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
|
||||
.C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH)
|
||||
) write_data_inst
|
||||
(
|
||||
// Global Signals
|
||||
.ARESET (ARESET),
|
||||
.ACLK (ACLK),
|
||||
|
||||
// Command Interface (In)
|
||||
.cmd_w_valid (cmd_w_valid),
|
||||
.cmd_w_check (cmd_w_check),
|
||||
.cmd_w_id (cmd_w_id),
|
||||
.cmd_w_ready (cmd_w_ready),
|
||||
|
||||
// Command Interface (Out)
|
||||
.cmd_b_push (cmd_b_push),
|
||||
.cmd_b_error (cmd_b_error),
|
||||
.cmd_b_id (cmd_b_id),
|
||||
.cmd_b_full (cmd_b_full),
|
||||
|
||||
// Slave Interface Write Data Ports
|
||||
.S_AXI_WID (S_AXI_WID),
|
||||
.S_AXI_WDATA (S_AXI_WDATA),
|
||||
.S_AXI_WSTRB (S_AXI_WSTRB),
|
||||
.S_AXI_WLAST (S_AXI_WLAST),
|
||||
.S_AXI_WUSER (S_AXI_WUSER),
|
||||
.S_AXI_WVALID (S_AXI_WVALID),
|
||||
.S_AXI_WREADY (S_AXI_WREADY),
|
||||
|
||||
// Master Interface Write Data Ports
|
||||
.M_AXI_WID (M_AXI_WID),
|
||||
.M_AXI_WDATA (M_AXI_WDATA),
|
||||
.M_AXI_WSTRB (M_AXI_WSTRB),
|
||||
.M_AXI_WLAST (M_AXI_WLAST),
|
||||
.M_AXI_WUSER (M_AXI_WUSER),
|
||||
.M_AXI_WVALID (M_AXI_WVALID),
|
||||
.M_AXI_WREADY (M_AXI_WREADY)
|
||||
);
|
||||
|
||||
// Write Response channel.
|
||||
processing_system7_v5_5_b_atc #
|
||||
(
|
||||
.C_FAMILY (C_FAMILY),
|
||||
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
|
||||
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH),
|
||||
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
|
||||
) write_response_inst
|
||||
(
|
||||
// Global Signals
|
||||
.ARESET (ARESET),
|
||||
.ACLK (ACLK),
|
||||
|
||||
// Command Interface (In)
|
||||
.cmd_b_push (cmd_b_push),
|
||||
.cmd_b_error (cmd_b_error),
|
||||
.cmd_b_id (cmd_b_id),
|
||||
.cmd_b_full (cmd_b_full),
|
||||
.cmd_b_addr (cmd_b_addr),
|
||||
.cmd_b_ready (cmd_b_ready),
|
||||
|
||||
// Slave Interface Write Response Ports
|
||||
.S_AXI_BID (S_AXI_BID),
|
||||
.S_AXI_BRESP (S_AXI_BRESP),
|
||||
.S_AXI_BUSER (S_AXI_BUSER),
|
||||
.S_AXI_BVALID (S_AXI_BVALID),
|
||||
.S_AXI_BREADY (S_AXI_BREADY),
|
||||
|
||||
// Master Interface Write Response Ports
|
||||
.M_AXI_BID (M_AXI_BID),
|
||||
.M_AXI_BRESP (M_AXI_BRESP),
|
||||
.M_AXI_BUSER (M_AXI_BUSER),
|
||||
.M_AXI_BVALID (M_AXI_BVALID),
|
||||
.M_AXI_BREADY (M_AXI_BREADY),
|
||||
|
||||
// Trigger detection
|
||||
.ERROR_TRIGGER (ERROR_TRIGGER),
|
||||
.ERROR_TRANSACTION_ID (ERROR_TRANSACTION_ID)
|
||||
);
|
||||
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Handle Read Channels (AR/R)
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Read Address Port
|
||||
assign M_AXI_ARID = S_AXI_ARID;
|
||||
assign M_AXI_ARADDR = S_AXI_ARADDR;
|
||||
assign M_AXI_ARLEN = S_AXI_ARLEN;
|
||||
assign M_AXI_ARSIZE = S_AXI_ARSIZE;
|
||||
assign M_AXI_ARBURST = S_AXI_ARBURST;
|
||||
assign M_AXI_ARLOCK = S_AXI_ARLOCK;
|
||||
assign M_AXI_ARCACHE = S_AXI_ARCACHE;
|
||||
assign M_AXI_ARPROT = S_AXI_ARPROT;
|
||||
assign M_AXI_ARUSER = S_AXI_ARUSER;
|
||||
assign M_AXI_ARVALID = S_AXI_ARVALID;
|
||||
assign S_AXI_ARREADY = M_AXI_ARREADY;
|
||||
|
||||
// Read Data Port
|
||||
assign S_AXI_RID = M_AXI_RID;
|
||||
assign S_AXI_RDATA = M_AXI_RDATA;
|
||||
assign S_AXI_RRESP = M_AXI_RRESP;
|
||||
assign S_AXI_RLAST = M_AXI_RLAST;
|
||||
assign S_AXI_RUSER = M_AXI_RUSER;
|
||||
assign S_AXI_RVALID = M_AXI_RVALID;
|
||||
assign M_AXI_RREADY = S_AXI_RREADY;
|
||||
|
||||
|
||||
endmodule
|
||||
`default_nettype wire
|
||||
+298
@@ -0,0 +1,298 @@
|
||||
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
|
||||
// --
|
||||
// -- This file contains confidential and proprietary information
|
||||
// -- of Xilinx, Inc. and is protected under U.S. and
|
||||
// -- international copyright and other intellectual property
|
||||
// -- laws.
|
||||
// --
|
||||
// -- DISCLAIMER
|
||||
// -- This disclaimer is not a license and does not grant any
|
||||
// -- rights to the materials distributed herewith. Except as
|
||||
// -- otherwise provided in a valid license issued to you by
|
||||
// -- Xilinx, and to the maximum extent permitted by applicable
|
||||
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// -- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// -- including negligence, or under any other theory of
|
||||
// -- liability) for any loss or damage of any kind or nature
|
||||
// -- related to, arising under or in connection with these
|
||||
// -- materials, including for any direct, or any indirect,
|
||||
// -- special, incidental, or consequential loss or damage
|
||||
// -- (including loss of data, profits, goodwill, or any type of
|
||||
// -- loss or damage suffered as a result of any action brought
|
||||
// -- by a third party) even if such damage or loss was
|
||||
// -- reasonably foreseeable or Xilinx had been advised of the
|
||||
// -- possibility of the same.
|
||||
// --
|
||||
// -- CRITICAL APPLICATIONS
|
||||
// -- Xilinx products are not designed or intended to be fail-
|
||||
// -- safe, or for use in any application requiring fail-safe
|
||||
// -- performance, such as life-support or safety devices or
|
||||
// -- systems, Class III medical devices, nuclear facilities,
|
||||
// -- applications related to the deployment of airbags, or any
|
||||
// -- other applications that could lead to death, personal
|
||||
// -- injury, or severe property or environmental damage
|
||||
// -- (individually and collectively, "Critical
|
||||
// -- Applications"). Customer assumes the sole risk and
|
||||
// -- liability of any use of Xilinx products in Critical
|
||||
// -- Applications, subject only to applicable laws and
|
||||
// -- regulations governing limitations on product liability.
|
||||
// --
|
||||
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// -- PART OF THIS FILE AT ALL TIMES.
|
||||
//-----------------------------------------------------------------------------
|
||||
//
|
||||
// Description: Address Write Channel for ATC
|
||||
//
|
||||
//
|
||||
// Verilog-standard: Verilog 2001
|
||||
//--------------------------------------------------------------------------
|
||||
//
|
||||
// Structure:
|
||||
// aw_atc
|
||||
//
|
||||
//--------------------------------------------------------------------------
|
||||
`timescale 1ps/1ps
|
||||
|
||||
|
||||
module processing_system7_v5_5_aw_atc #
|
||||
(
|
||||
parameter C_FAMILY = "rtl",
|
||||
// FPGA Family. Current version: virtex6, spartan6 or later.
|
||||
parameter integer C_AXI_ID_WIDTH = 4,
|
||||
// Width of all ID signals on SI and MI side of checker.
|
||||
// Range: >= 1.
|
||||
parameter integer C_AXI_ADDR_WIDTH = 32,
|
||||
// Width of all ADDR signals on SI and MI side of checker.
|
||||
// Range: 32.
|
||||
parameter integer C_AXI_AWUSER_WIDTH = 1,
|
||||
// Width of AWUSER signals.
|
||||
// Range: >= 1.
|
||||
parameter integer C_FIFO_DEPTH_LOG = 4
|
||||
)
|
||||
(
|
||||
// Global Signals
|
||||
input wire ARESET,
|
||||
input wire ACLK,
|
||||
|
||||
// Command Interface
|
||||
output reg cmd_w_valid,
|
||||
output wire cmd_w_check,
|
||||
output wire [C_AXI_ID_WIDTH-1:0] cmd_w_id,
|
||||
input wire cmd_w_ready,
|
||||
input wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr,
|
||||
input wire cmd_b_ready,
|
||||
|
||||
// Slave Interface Write Address Port
|
||||
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
|
||||
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
|
||||
input wire [4-1:0] S_AXI_AWLEN,
|
||||
input wire [3-1:0] S_AXI_AWSIZE,
|
||||
input wire [2-1:0] S_AXI_AWBURST,
|
||||
input wire [2-1:0] S_AXI_AWLOCK,
|
||||
input wire [4-1:0] S_AXI_AWCACHE,
|
||||
input wire [3-1:0] S_AXI_AWPROT,
|
||||
input wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER,
|
||||
input wire S_AXI_AWVALID,
|
||||
output wire S_AXI_AWREADY,
|
||||
|
||||
// Master Interface Write Address Port
|
||||
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID,
|
||||
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
|
||||
output wire [4-1:0] M_AXI_AWLEN,
|
||||
output wire [3-1:0] M_AXI_AWSIZE,
|
||||
output wire [2-1:0] M_AXI_AWBURST,
|
||||
output wire [2-1:0] M_AXI_AWLOCK,
|
||||
output wire [4-1:0] M_AXI_AWCACHE,
|
||||
output wire [3-1:0] M_AXI_AWPROT,
|
||||
output wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER,
|
||||
output wire M_AXI_AWVALID,
|
||||
input wire M_AXI_AWREADY
|
||||
);
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Local params
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Constants for burst types.
|
||||
localparam [2-1:0] C_FIX_BURST = 2'b00;
|
||||
localparam [2-1:0] C_INCR_BURST = 2'b01;
|
||||
localparam [2-1:0] C_WRAP_BURST = 2'b10;
|
||||
|
||||
// Constants for size.
|
||||
localparam [3-1:0] C_OPTIMIZED_SIZE = 3'b011;
|
||||
|
||||
// Constants for length.
|
||||
localparam [4-1:0] C_OPTIMIZED_LEN = 4'b0011;
|
||||
|
||||
// Constants for cacheline address.
|
||||
localparam [4-1:0] C_NO_ADDR_OFFSET = 5'b0;
|
||||
|
||||
// Command FIFO settings
|
||||
localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1;
|
||||
localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG;
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Variables for generating parameter controlled instances.
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
integer index;
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Functions
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Internal signals
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Transaction properties.
|
||||
wire access_is_incr;
|
||||
wire access_is_wrap;
|
||||
wire access_is_coherent;
|
||||
wire access_optimized_size;
|
||||
wire incr_addr_boundary;
|
||||
wire incr_is_optimized;
|
||||
wire wrap_is_optimized;
|
||||
wire access_is_optimized;
|
||||
|
||||
// Command FIFO.
|
||||
wire cmd_w_push;
|
||||
reg cmd_full;
|
||||
reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr;
|
||||
wire [C_FIFO_DEPTH_LOG-1:0] all_addr_ptr;
|
||||
reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0];
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Transaction Decode:
|
||||
//
|
||||
// Detect if transaction is of correct typ, size and length to qualify as
|
||||
// an optimized transaction that has to be checked for errors.
|
||||
//
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Transaction burst type.
|
||||
assign access_is_incr = ( S_AXI_AWBURST == C_INCR_BURST );
|
||||
assign access_is_wrap = ( S_AXI_AWBURST == C_WRAP_BURST );
|
||||
|
||||
// Transaction has to be Coherent.
|
||||
assign access_is_coherent = ( S_AXI_AWUSER[0] == 1'b1 ) &
|
||||
( S_AXI_AWCACHE[1] == 1'b1 );
|
||||
|
||||
// Transaction cacheline boundary address.
|
||||
assign incr_addr_boundary = ( S_AXI_AWADDR[4:0] == C_NO_ADDR_OFFSET );
|
||||
|
||||
// Transaction length & size.
|
||||
assign access_optimized_size = ( S_AXI_AWSIZE == C_OPTIMIZED_SIZE ) &
|
||||
( S_AXI_AWLEN == C_OPTIMIZED_LEN );
|
||||
|
||||
// Transaction is optimized.
|
||||
assign incr_is_optimized = access_is_incr & access_is_coherent & access_optimized_size & incr_addr_boundary;
|
||||
assign wrap_is_optimized = access_is_wrap & access_is_coherent & access_optimized_size;
|
||||
assign access_is_optimized = ( incr_is_optimized | wrap_is_optimized );
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Command FIFO:
|
||||
//
|
||||
// Since supported write interleaving is only 1, it is safe to use only a
|
||||
// simple SRL based FIFO as a command queue.
|
||||
//
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Determine when transaction infromation is pushed to the FIFO.
|
||||
assign cmd_w_push = S_AXI_AWVALID & M_AXI_AWREADY & ~cmd_full;
|
||||
|
||||
// SRL FIFO Pointer.
|
||||
always @ (posedge ACLK) begin
|
||||
if (ARESET) begin
|
||||
addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
|
||||
end else begin
|
||||
if ( cmd_w_push & ~cmd_w_ready ) begin
|
||||
addr_ptr <= addr_ptr + 1;
|
||||
end else if ( ~cmd_w_push & cmd_w_ready ) begin
|
||||
addr_ptr <= addr_ptr - 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// Total number of buffered commands.
|
||||
assign all_addr_ptr = addr_ptr + cmd_b_addr + 2;
|
||||
|
||||
// FIFO Flags.
|
||||
always @ (posedge ACLK) begin
|
||||
if (ARESET) begin
|
||||
cmd_full <= 1'b0;
|
||||
cmd_w_valid <= 1'b0;
|
||||
end else begin
|
||||
if ( cmd_w_push & ~cmd_w_ready ) begin
|
||||
cmd_w_valid <= 1'b1;
|
||||
end else if ( ~cmd_w_push & cmd_w_ready ) begin
|
||||
cmd_w_valid <= ( addr_ptr != 0 );
|
||||
end
|
||||
if ( cmd_w_push & ~cmd_b_ready ) begin
|
||||
// Going to full.
|
||||
cmd_full <= ( all_addr_ptr == C_FIFO_DEPTH-3 );
|
||||
end else if ( ~cmd_w_push & cmd_b_ready ) begin
|
||||
// Pop in middle of queue doesn't affect full status.
|
||||
cmd_full <= ( all_addr_ptr == C_FIFO_DEPTH-2 );
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// Infere SRL for storage.
|
||||
always @ (posedge ACLK) begin
|
||||
if ( cmd_w_push ) begin
|
||||
for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin
|
||||
data_srl[index+1] <= data_srl[index];
|
||||
end
|
||||
data_srl[0] <= {access_is_optimized, S_AXI_AWID};
|
||||
end
|
||||
end
|
||||
|
||||
// Get current transaction info.
|
||||
assign {cmd_w_check, cmd_w_id} = data_srl[addr_ptr];
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Transaction Throttling:
|
||||
//
|
||||
// Stall commands if FIFO is full.
|
||||
//
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Propagate masked valid.
|
||||
assign M_AXI_AWVALID = S_AXI_AWVALID & ~cmd_full;
|
||||
|
||||
// Return ready with push back.
|
||||
assign S_AXI_AWREADY = M_AXI_AWREADY & ~cmd_full;
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Address Write propagation:
|
||||
//
|
||||
// All information is simply forwarded on from the SI- to MI-Side untouched.
|
||||
//
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// 1:1 mapping.
|
||||
assign M_AXI_AWID = S_AXI_AWID;
|
||||
assign M_AXI_AWADDR = S_AXI_AWADDR;
|
||||
assign M_AXI_AWLEN = S_AXI_AWLEN;
|
||||
assign M_AXI_AWSIZE = S_AXI_AWSIZE;
|
||||
assign M_AXI_AWBURST = S_AXI_AWBURST;
|
||||
assign M_AXI_AWLOCK = S_AXI_AWLOCK;
|
||||
assign M_AXI_AWCACHE = S_AXI_AWCACHE;
|
||||
assign M_AXI_AWPROT = S_AXI_AWPROT;
|
||||
assign M_AXI_AWUSER = S_AXI_AWUSER;
|
||||
|
||||
|
||||
endmodule
|
||||
+413
@@ -0,0 +1,413 @@
|
||||
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
|
||||
// --
|
||||
// -- This file contains confidential and proprietary information
|
||||
// -- of Xilinx, Inc. and is protected under U.S. and
|
||||
// -- international copyright and other intellectual property
|
||||
// -- laws.
|
||||
// --
|
||||
// -- DISCLAIMER
|
||||
// -- This disclaimer is not a license and does not grant any
|
||||
// -- rights to the materials distributed herewith. Except as
|
||||
// -- otherwise provided in a valid license issued to you by
|
||||
// -- Xilinx, and to the maximum extent permitted by applicable
|
||||
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// -- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// -- including negligence, or under any other theory of
|
||||
// -- liability) for any loss or damage of any kind or nature
|
||||
// -- related to, arising under or in connection with these
|
||||
// -- materials, including for any direct, or any indirect,
|
||||
// -- special, incidental, or consequential loss or damage
|
||||
// -- (including loss of data, profits, goodwill, or any type of
|
||||
// -- loss or damage suffered as a result of any action brought
|
||||
// -- by a third party) even if such damage or loss was
|
||||
// -- reasonably foreseeable or Xilinx had been advised of the
|
||||
// -- possibility of the same.
|
||||
// --
|
||||
// -- CRITICAL APPLICATIONS
|
||||
// -- Xilinx products are not designed or intended to be fail-
|
||||
// -- safe, or for use in any application requiring fail-safe
|
||||
// -- performance, such as life-support or safety devices or
|
||||
// -- systems, Class III medical devices, nuclear facilities,
|
||||
// -- applications related to the deployment of airbags, or any
|
||||
// -- other applications that could lead to death, personal
|
||||
// -- injury, or severe property or environmental damage
|
||||
// -- (individually and collectively, "Critical
|
||||
// -- Applications"). Customer assumes the sole risk and
|
||||
// -- liability of any use of Xilinx products in Critical
|
||||
// -- Applications, subject only to applicable laws and
|
||||
// -- regulations governing limitations on product liability.
|
||||
// --
|
||||
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// -- PART OF THIS FILE AT ALL TIMES.
|
||||
//-----------------------------------------------------------------------------
|
||||
//
|
||||
// Description: Write Response Channel for ATC
|
||||
//
|
||||
//
|
||||
// Verilog-standard: Verilog 2001
|
||||
//--------------------------------------------------------------------------
|
||||
//
|
||||
// Structure:
|
||||
// b_atc
|
||||
//
|
||||
//--------------------------------------------------------------------------
|
||||
`timescale 1ps/1ps
|
||||
|
||||
|
||||
module processing_system7_v5_5_b_atc #
|
||||
(
|
||||
parameter C_FAMILY = "rtl",
|
||||
// FPGA Family. Current version: virtex6, spartan6 or later.
|
||||
parameter integer C_AXI_ID_WIDTH = 4,
|
||||
// Width of all ID signals on SI and MI side of checker.
|
||||
// Range: >= 1.
|
||||
parameter integer C_AXI_BUSER_WIDTH = 1,
|
||||
// Width of AWUSER signals.
|
||||
// Range: >= 1.
|
||||
parameter integer C_FIFO_DEPTH_LOG = 4
|
||||
)
|
||||
(
|
||||
// Global Signals
|
||||
input wire ARESET,
|
||||
input wire ACLK,
|
||||
|
||||
// Command Interface
|
||||
input wire cmd_b_push,
|
||||
input wire cmd_b_error,
|
||||
input wire [C_AXI_ID_WIDTH-1:0] cmd_b_id,
|
||||
output wire cmd_b_ready,
|
||||
output wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr,
|
||||
output reg cmd_b_full,
|
||||
|
||||
// Slave Interface Write Response Ports
|
||||
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
|
||||
output reg [2-1:0] S_AXI_BRESP,
|
||||
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
|
||||
output wire S_AXI_BVALID,
|
||||
input wire S_AXI_BREADY,
|
||||
|
||||
// Master Interface Write Response Ports
|
||||
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
|
||||
input wire [2-1:0] M_AXI_BRESP,
|
||||
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
|
||||
input wire M_AXI_BVALID,
|
||||
output wire M_AXI_BREADY,
|
||||
|
||||
// Trigger detection
|
||||
output reg ERROR_TRIGGER,
|
||||
output reg [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
|
||||
);
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Local params
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Constants for packing levels.
|
||||
localparam [2-1:0] C_RESP_OKAY = 2'b00;
|
||||
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
|
||||
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
|
||||
localparam [2-1:0] C_RESP_DECERR = 2'b11;
|
||||
|
||||
// Command FIFO settings
|
||||
localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1;
|
||||
localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG;
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Variables for generating parameter controlled instances.
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
integer index;
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Functions
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Internal signals
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Command Queue.
|
||||
reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr;
|
||||
reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0];
|
||||
reg cmd_b_valid;
|
||||
wire cmd_b_ready_i;
|
||||
wire inject_error;
|
||||
wire [C_AXI_ID_WIDTH-1:0] current_id;
|
||||
|
||||
// Search command.
|
||||
wire found_match;
|
||||
wire use_match;
|
||||
wire matching_id;
|
||||
|
||||
// Manage valid command.
|
||||
wire write_valid_cmd;
|
||||
reg [C_FIFO_DEPTH-2:0] valid_cmd;
|
||||
reg [C_FIFO_DEPTH-2:0] updated_valid_cmd;
|
||||
reg [C_FIFO_DEPTH-2:0] next_valid_cmd;
|
||||
reg [C_FIFO_DEPTH_LOG-1:0] search_addr_ptr;
|
||||
reg [C_FIFO_DEPTH_LOG-1:0] collapsed_addr_ptr;
|
||||
|
||||
// Pipelined data
|
||||
reg [C_AXI_ID_WIDTH-1:0] M_AXI_BID_I;
|
||||
reg [2-1:0] M_AXI_BRESP_I;
|
||||
reg [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER_I;
|
||||
reg M_AXI_BVALID_I;
|
||||
wire M_AXI_BREADY_I;
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Command Queue:
|
||||
//
|
||||
// Keep track of depth of Queue to generate full flag.
|
||||
//
|
||||
// Also generate valid to mark pressence of commands in Queue.
|
||||
//
|
||||
// Maintain Queue and extract data from currently searched entry.
|
||||
//
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// SRL FIFO Pointer.
|
||||
always @ (posedge ACLK) begin
|
||||
if (ARESET) begin
|
||||
addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
|
||||
end else begin
|
||||
if ( cmd_b_push & ~cmd_b_ready_i ) begin
|
||||
// Pushing data increase length/addr.
|
||||
addr_ptr <= addr_ptr + 1;
|
||||
end else if ( cmd_b_ready_i ) begin
|
||||
// Collapse addr when data is popped.
|
||||
addr_ptr <= collapsed_addr_ptr;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// FIFO Flags.
|
||||
always @ (posedge ACLK) begin
|
||||
if (ARESET) begin
|
||||
cmd_b_full <= 1'b0;
|
||||
cmd_b_valid <= 1'b0;
|
||||
end else begin
|
||||
if ( cmd_b_push & ~cmd_b_ready_i ) begin
|
||||
cmd_b_full <= ( addr_ptr == C_FIFO_DEPTH-3 );
|
||||
cmd_b_valid <= 1'b1;
|
||||
end else if ( ~cmd_b_push & cmd_b_ready_i ) begin
|
||||
cmd_b_full <= 1'b0;
|
||||
cmd_b_valid <= ( collapsed_addr_ptr != C_FIFO_DEPTH-1 );
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// Infere SRL for storage.
|
||||
always @ (posedge ACLK) begin
|
||||
if ( cmd_b_push ) begin
|
||||
for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin
|
||||
data_srl[index+1] <= data_srl[index];
|
||||
end
|
||||
data_srl[0] <= {cmd_b_error, cmd_b_id};
|
||||
end
|
||||
end
|
||||
|
||||
// Get current transaction info.
|
||||
assign {inject_error, current_id} = data_srl[search_addr_ptr];
|
||||
|
||||
// Assign outputs.
|
||||
assign cmd_b_addr = collapsed_addr_ptr;
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Search Command Queue:
|
||||
//
|
||||
// Search for matching valid command in queue.
|
||||
//
|
||||
// A command is found when an valid entry with correct ID is found. The queue
|
||||
// is search from the oldest entry, i.e. from a high value.
|
||||
// When new commands are pushed the search address has to be updated to always
|
||||
// start the search from the oldest available.
|
||||
//
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Handle search addr.
|
||||
always @ (posedge ACLK) begin
|
||||
if (ARESET) begin
|
||||
search_addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
|
||||
end else begin
|
||||
if ( cmd_b_ready_i ) begin
|
||||
// Collapse addr when data is popped.
|
||||
search_addr_ptr <= collapsed_addr_ptr;
|
||||
|
||||
end else if ( M_AXI_BVALID_I & cmd_b_valid & ~found_match & ~cmd_b_push ) begin
|
||||
// Skip non valid command.
|
||||
search_addr_ptr <= search_addr_ptr - 1;
|
||||
|
||||
end else if ( cmd_b_push ) begin
|
||||
search_addr_ptr <= search_addr_ptr + 1;
|
||||
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// Check if searched command is valid and match ID (for existing response on MI side).
|
||||
assign matching_id = ( M_AXI_BID_I == current_id );
|
||||
assign found_match = valid_cmd[search_addr_ptr] & matching_id & M_AXI_BVALID_I;
|
||||
assign use_match = found_match & S_AXI_BREADY;
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Track Used Commands:
|
||||
//
|
||||
// Actions that affect Valid Command:
|
||||
// * When a new command is pushed
|
||||
// => Shift valid vector one step
|
||||
// * When a command is used
|
||||
// => Clear corresponding valid bit
|
||||
//
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Valid command status is updated when a command is used or a new one is pushed.
|
||||
assign write_valid_cmd = cmd_b_push | cmd_b_ready_i;
|
||||
|
||||
// Update the used command valid bit.
|
||||
always @ *
|
||||
begin
|
||||
updated_valid_cmd = valid_cmd;
|
||||
updated_valid_cmd[search_addr_ptr] = ~use_match;
|
||||
end
|
||||
|
||||
// Shift valid vector when command is pushed.
|
||||
always @ *
|
||||
begin
|
||||
if ( cmd_b_push ) begin
|
||||
next_valid_cmd = {updated_valid_cmd[C_FIFO_DEPTH-3:0], 1'b1};
|
||||
end else begin
|
||||
next_valid_cmd = updated_valid_cmd;
|
||||
end
|
||||
end
|
||||
|
||||
// Valid signals for next cycle.
|
||||
always @ (posedge ACLK) begin
|
||||
if (ARESET) begin
|
||||
valid_cmd <= {C_FIFO_WIDTH{1'b0}};
|
||||
end else if ( write_valid_cmd ) begin
|
||||
valid_cmd <= next_valid_cmd;
|
||||
end
|
||||
end
|
||||
|
||||
// Detect oldest available command in Queue.
|
||||
always @ *
|
||||
begin
|
||||
// Default to empty.
|
||||
collapsed_addr_ptr = {C_FIFO_DEPTH_LOG{1'b1}};
|
||||
|
||||
for (index = 0; index < C_FIFO_DEPTH-2 ; index = index + 1) begin
|
||||
if ( next_valid_cmd[index] ) begin
|
||||
collapsed_addr_ptr = index;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Pipe incoming data:
|
||||
//
|
||||
// The B channel is piped to improve timing and avoid impact in search
|
||||
// mechanism due to late arriving signals.
|
||||
//
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Clock data.
|
||||
always @ (posedge ACLK) begin
|
||||
if (ARESET) begin
|
||||
M_AXI_BID_I <= {C_AXI_ID_WIDTH{1'b0}};
|
||||
M_AXI_BRESP_I <= 2'b00;
|
||||
M_AXI_BUSER_I <= {C_AXI_BUSER_WIDTH{1'b0}};
|
||||
M_AXI_BVALID_I <= 1'b0;
|
||||
end else begin
|
||||
if ( M_AXI_BREADY_I | ~M_AXI_BVALID_I ) begin
|
||||
M_AXI_BVALID_I <= 1'b0;
|
||||
end
|
||||
if (M_AXI_BVALID & ( M_AXI_BREADY_I | ~M_AXI_BVALID_I) ) begin
|
||||
M_AXI_BID_I <= M_AXI_BID;
|
||||
M_AXI_BRESP_I <= M_AXI_BRESP;
|
||||
M_AXI_BUSER_I <= M_AXI_BUSER;
|
||||
M_AXI_BVALID_I <= 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// Generate ready to get new transaction.
|
||||
assign M_AXI_BREADY = M_AXI_BREADY_I | ~M_AXI_BVALID_I;
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Inject Error:
|
||||
//
|
||||
// BRESP is modified according to command information.
|
||||
//
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Inject error in response.
|
||||
always @ *
|
||||
begin
|
||||
if ( inject_error ) begin
|
||||
S_AXI_BRESP = C_RESP_SLVERROR;
|
||||
end else begin
|
||||
S_AXI_BRESP = M_AXI_BRESP_I;
|
||||
end
|
||||
end
|
||||
|
||||
// Handle interrupt generation.
|
||||
always @ (posedge ACLK) begin
|
||||
if (ARESET) begin
|
||||
ERROR_TRIGGER <= 1'b0;
|
||||
ERROR_TRANSACTION_ID <= {C_AXI_ID_WIDTH{1'b0}};
|
||||
end else begin
|
||||
if ( inject_error & cmd_b_ready_i ) begin
|
||||
ERROR_TRIGGER <= 1'b1;
|
||||
ERROR_TRANSACTION_ID <= M_AXI_BID_I;
|
||||
end else begin
|
||||
ERROR_TRIGGER <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Transaction Throttling:
|
||||
//
|
||||
// Response is passed forward when a matching entry has been found in queue.
|
||||
// Both ready and valid are set when the command is completed.
|
||||
//
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Propagate masked valid.
|
||||
assign S_AXI_BVALID = M_AXI_BVALID_I & cmd_b_valid & found_match;
|
||||
|
||||
// Return ready with push back.
|
||||
assign M_AXI_BREADY_I = cmd_b_valid & use_match;
|
||||
|
||||
// Command has been handled.
|
||||
assign cmd_b_ready_i = M_AXI_BVALID_I & cmd_b_valid & use_match;
|
||||
assign cmd_b_ready = cmd_b_ready_i;
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Write Response Propagation:
|
||||
//
|
||||
// All information is simply forwarded on from MI- to SI-Side untouched.
|
||||
//
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// 1:1 mapping.
|
||||
assign S_AXI_BID = M_AXI_BID_I;
|
||||
assign S_AXI_BUSER = M_AXI_BUSER_I;
|
||||
|
||||
|
||||
endmodule
|
||||
+310
@@ -0,0 +1,310 @@
|
||||
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
|
||||
// --
|
||||
// -- This file contains confidential and proprietary information
|
||||
// -- of Xilinx, Inc. and is protected under U.S. and
|
||||
// -- international copyright and other intellectual property
|
||||
// -- laws.
|
||||
// --
|
||||
// -- DISCLAIMER
|
||||
// -- This disclaimer is not a license and does not grant any
|
||||
// -- rights to the materials distributed herewith. Except as
|
||||
// -- otherwise provided in a valid license issued to you by
|
||||
// -- Xilinx, and to the maximum extent permitted by applicable
|
||||
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// -- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// -- including negligence, or under any other theory of
|
||||
// -- liability) for any loss or damage of any kind or nature
|
||||
// -- related to, arising under or in connection with these
|
||||
// -- materials, including for any direct, or any indirect,
|
||||
// -- special, incidental, or consequential loss or damage
|
||||
// -- (including loss of data, profits, goodwill, or any type of
|
||||
// -- loss or damage suffered as a result of any action brought
|
||||
// -- by a third party) even if such damage or loss was
|
||||
// -- reasonably foreseeable or Xilinx had been advised of the
|
||||
// -- possibility of the same.
|
||||
// --
|
||||
// -- CRITICAL APPLICATIONS
|
||||
// -- Xilinx products are not designed or intended to be fail-
|
||||
// -- safe, or for use in any application requiring fail-safe
|
||||
// -- performance, such as life-support or safety devices or
|
||||
// -- systems, Class III medical devices, nuclear facilities,
|
||||
// -- applications related to the deployment of airbags, or any
|
||||
// -- other applications that could lead to death, personal
|
||||
// -- injury, or severe property or environmental damage
|
||||
// -- (individually and collectively, "Critical
|
||||
// -- Applications"). Customer assumes the sole risk and
|
||||
// -- liability of any use of Xilinx products in Critical
|
||||
// -- Applications, subject only to applicable laws and
|
||||
// -- regulations governing limitations on product liability.
|
||||
// --
|
||||
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// -- PART OF THIS FILE AT ALL TIMES.
|
||||
//-----------------------------------------------------------------------------
|
||||
// Filename: trace_buffer.v
|
||||
// Description: Trace port buffer
|
||||
//-----------------------------------------------------------------------------
|
||||
// Structure: This section shows the hierarchical structure of
|
||||
// pss_wrapper.
|
||||
//
|
||||
// --processing_system7
|
||||
// |
|
||||
// --trace_buffer
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
|
||||
module processing_system7_v5_5_trace_buffer #
|
||||
(
|
||||
parameter integer FIFO_SIZE = 128,
|
||||
parameter integer USE_TRACE_DATA_EDGE_DETECTOR = 0,
|
||||
parameter integer C_DELAY_CLKS = 12
|
||||
)
|
||||
(
|
||||
input wire TRACE_CLK,
|
||||
input wire RST,
|
||||
input wire TRACE_VALID_IN,
|
||||
input wire [3:0] TRACE_ATID_IN,
|
||||
input wire [31:0] TRACE_DATA_IN,
|
||||
output wire TRACE_VALID_OUT,
|
||||
output wire [3:0] TRACE_ATID_OUT,
|
||||
output wire [31:0] TRACE_DATA_OUT
|
||||
);
|
||||
|
||||
//------------------------------------------------------------
|
||||
// Architecture section
|
||||
//------------------------------------------------------------
|
||||
|
||||
// function called clogb2 that returns an integer which has the
|
||||
// value of the ceiling of the log base 2.
|
||||
|
||||
function integer clogb2 (input integer bit_depth);
|
||||
integer i;
|
||||
integer temp_log;
|
||||
begin
|
||||
temp_log = 0;
|
||||
for(i=bit_depth; i > 0; i = i>>1)
|
||||
clogb2 = temp_log;
|
||||
temp_log=temp_log+1;
|
||||
end
|
||||
endfunction
|
||||
|
||||
localparam DEPTH = clogb2(FIFO_SIZE-1);
|
||||
|
||||
wire [31:0] reset_zeros;
|
||||
reg [31:0] trace_pedge; // write enable for FIFO
|
||||
reg [31:0] ti;
|
||||
reg [31:0] tom;
|
||||
|
||||
reg [3:0] atid;
|
||||
|
||||
reg [31:0] trace_fifo [FIFO_SIZE-1:0];//Memory
|
||||
|
||||
reg [4:0] dly_ctr;
|
||||
reg [DEPTH-1:0] fifo_wp;
|
||||
reg [DEPTH-1:0] fifo_rp;
|
||||
|
||||
reg fifo_re;
|
||||
wire fifo_empty;
|
||||
wire fifo_full;
|
||||
reg fifo_full_reg;
|
||||
|
||||
assign reset_zeros = 32'h0;
|
||||
|
||||
|
||||
// Pipeline Stage for Traceport ATID ports
|
||||
always @(posedge TRACE_CLK) begin
|
||||
// process pedge_ti
|
||||
// rising clock edge
|
||||
if((RST == 1'b1)) begin
|
||||
atid <= reset_zeros;
|
||||
end
|
||||
else begin
|
||||
atid <= TRACE_ATID_IN;
|
||||
end
|
||||
end
|
||||
|
||||
assign TRACE_ATID_OUT = atid;
|
||||
|
||||
/////////////////////////////////////////////
|
||||
// Generate FIFO data based on TRACE_VALID_IN
|
||||
/////////////////////////////////////////////
|
||||
generate
|
||||
if (USE_TRACE_DATA_EDGE_DETECTOR == 0) begin : gen_no_data_edge_detector
|
||||
/////////////////////////////////////////////
|
||||
|
||||
// memory update process
|
||||
// Update memory when positive edge detected and FIFO not full
|
||||
always @(posedge TRACE_CLK) begin
|
||||
if (TRACE_VALID_IN == 1'b1 && fifo_full_reg != 1'b1) begin
|
||||
trace_fifo[fifo_wp] <= TRACE_DATA_IN;
|
||||
end
|
||||
end
|
||||
|
||||
// fifo write pointer
|
||||
always @(posedge TRACE_CLK) begin
|
||||
// process
|
||||
if(RST == 1'b1) begin
|
||||
fifo_wp <= {DEPTH{1'b0}};
|
||||
end
|
||||
else if(TRACE_VALID_IN ) begin
|
||||
if(fifo_wp == (FIFO_SIZE - 1)) begin
|
||||
if (fifo_empty) begin
|
||||
fifo_wp <= {DEPTH{1'b0}};
|
||||
end
|
||||
end
|
||||
else begin
|
||||
fifo_wp <= fifo_wp + 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
/////////////////////////////////////////////
|
||||
// Generate FIFO data based on data edge
|
||||
/////////////////////////////////////////////
|
||||
end else begin : gen_data_edge_detector
|
||||
/////////////////////////////////////////////
|
||||
|
||||
|
||||
// purpose: check for pos edge on any trace input
|
||||
always @(posedge TRACE_CLK) begin
|
||||
// process pedge_ti
|
||||
// rising clock edge
|
||||
if((RST == 1'b1)) begin
|
||||
ti <= reset_zeros;
|
||||
trace_pedge <= reset_zeros;
|
||||
end
|
||||
else begin
|
||||
ti <= TRACE_DATA_IN;
|
||||
trace_pedge <= (~ti & TRACE_DATA_IN);
|
||||
//trace_pedge <= ((~ti ^ TRACE_DATA_IN)) & ~ti;
|
||||
// posedge only
|
||||
end
|
||||
end
|
||||
|
||||
// memory update process
|
||||
// Update memory when positive edge detected and FIFO not full
|
||||
always @(posedge TRACE_CLK) begin
|
||||
if(|(trace_pedge) == 1'b1 && fifo_full_reg != 1'b1) begin
|
||||
trace_fifo[fifo_wp] <= trace_pedge;
|
||||
end
|
||||
end
|
||||
|
||||
// fifo write pointer
|
||||
always @(posedge TRACE_CLK) begin
|
||||
// process
|
||||
if(RST == 1'b1) begin
|
||||
fifo_wp <= {DEPTH{1'b0}};
|
||||
end
|
||||
else if(|(trace_pedge) == 1'b1) begin
|
||||
if(fifo_wp == (FIFO_SIZE - 1)) begin
|
||||
if (fifo_empty) begin
|
||||
fifo_wp <= {DEPTH{1'b0}};
|
||||
end
|
||||
end
|
||||
else begin
|
||||
fifo_wp <= fifo_wp + 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
||||
always @(posedge TRACE_CLK) begin
|
||||
tom <= trace_fifo[fifo_rp] ;
|
||||
end
|
||||
|
||||
|
||||
// // fifo write pointer
|
||||
// always @(posedge TRACE_CLK) begin
|
||||
// // process
|
||||
// if(RST == 1'b1) begin
|
||||
// fifo_wp <= {DEPTH{1'b0}};
|
||||
// end
|
||||
// else if(|(trace_pedge) == 1'b1) begin
|
||||
// if(fifo_wp == (FIFO_SIZE - 1)) begin
|
||||
// fifo_wp <= {DEPTH{1'b0}};
|
||||
// end
|
||||
// else begin
|
||||
// fifo_wp <= fifo_wp + 1;
|
||||
// end
|
||||
// end
|
||||
// end
|
||||
|
||||
|
||||
// fifo read pointer update
|
||||
always @(posedge TRACE_CLK) begin
|
||||
if(RST == 1'b1) begin
|
||||
fifo_rp <= {DEPTH{1'b0}};
|
||||
fifo_re <= 1'b0;
|
||||
end
|
||||
else if(fifo_empty != 1'b1 && dly_ctr == 5'b00000 && fifo_re == 1'b0) begin
|
||||
fifo_re <= 1'b1;
|
||||
if(fifo_rp == (FIFO_SIZE - 1)) begin
|
||||
fifo_rp <= {DEPTH{1'b0}};
|
||||
end
|
||||
else begin
|
||||
fifo_rp <= fifo_rp + 1;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
fifo_re <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
// delay counter update
|
||||
always @(posedge TRACE_CLK) begin
|
||||
if(RST == 1'b1) begin
|
||||
dly_ctr <= 5'h0;
|
||||
end
|
||||
else if (fifo_re == 1'b1) begin
|
||||
dly_ctr <= C_DELAY_CLKS-1;
|
||||
end
|
||||
else if(dly_ctr != 5'h0) begin
|
||||
dly_ctr <= dly_ctr - 1;
|
||||
end
|
||||
end
|
||||
|
||||
// fifo empty update
|
||||
assign fifo_empty = (fifo_wp == fifo_rp) ? 1'b1 : 1'b0;
|
||||
|
||||
// fifo full update
|
||||
assign fifo_full = (fifo_wp == FIFO_SIZE-1)? 1'b1 : 1'b0;
|
||||
|
||||
always @(posedge TRACE_CLK) begin
|
||||
if(RST == 1'b1) begin
|
||||
fifo_full_reg <= 1'b0;
|
||||
end
|
||||
else if (fifo_empty) begin
|
||||
fifo_full_reg <= 1'b0;
|
||||
end else begin
|
||||
fifo_full_reg <= fifo_full;
|
||||
end
|
||||
end
|
||||
|
||||
// always @(posedge TRACE_CLK) begin
|
||||
// if(RST == 1'b1) begin
|
||||
// fifo_full_reg <= 1'b0;
|
||||
// end
|
||||
// else if ((fifo_wp == FIFO_SIZE-1) && (|(trace_pedge) == 1'b1)) begin
|
||||
// fifo_full_reg <= 1'b1;
|
||||
// end
|
||||
// else begin
|
||||
// fifo_full_reg <= 1'b0;
|
||||
// end
|
||||
// end
|
||||
//
|
||||
assign TRACE_DATA_OUT = tom;
|
||||
|
||||
assign TRACE_VALID_OUT = fifo_re;
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
+244
@@ -0,0 +1,244 @@
|
||||
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
|
||||
// --
|
||||
// -- This file contains confidential and proprietary information
|
||||
// -- of Xilinx, Inc. and is protected under U.S. and
|
||||
// -- international copyright and other intellectual property
|
||||
// -- laws.
|
||||
// --
|
||||
// -- DISCLAIMER
|
||||
// -- This disclaimer is not a license and does not grant any
|
||||
// -- rights to the materials distributed herewith. Except as
|
||||
// -- otherwise provided in a valid license issued to you by
|
||||
// -- Xilinx, and to the maximum extent permitted by applicable
|
||||
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// -- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// -- including negligence, or under any other theory of
|
||||
// -- liability) for any loss or damage of any kind or nature
|
||||
// -- related to, arising under or in connection with these
|
||||
// -- materials, including for any direct, or any indirect,
|
||||
// -- special, incidental, or consequential loss or damage
|
||||
// -- (including loss of data, profits, goodwill, or any type of
|
||||
// -- loss or damage suffered as a result of any action brought
|
||||
// -- by a third party) even if such damage or loss was
|
||||
// -- reasonably foreseeable or Xilinx had been advised of the
|
||||
// -- possibility of the same.
|
||||
// --
|
||||
// -- CRITICAL APPLICATIONS
|
||||
// -- Xilinx products are not designed or intended to be fail-
|
||||
// -- safe, or for use in any application requiring fail-safe
|
||||
// -- performance, such as life-support or safety devices or
|
||||
// -- systems, Class III medical devices, nuclear facilities,
|
||||
// -- applications related to the deployment of airbags, or any
|
||||
// -- other applications that could lead to death, personal
|
||||
// -- injury, or severe property or environmental damage
|
||||
// -- (individually and collectively, "Critical
|
||||
// -- Applications"). Customer assumes the sole risk and
|
||||
// -- liability of any use of Xilinx products in Critical
|
||||
// -- Applications, subject only to applicable laws and
|
||||
// -- regulations governing limitations on product liability.
|
||||
// --
|
||||
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// -- PART OF THIS FILE AT ALL TIMES.
|
||||
//-----------------------------------------------------------------------------
|
||||
//
|
||||
// Description: Write Channel for ATC
|
||||
//
|
||||
//
|
||||
// Verilog-standard: Verilog 2001
|
||||
//--------------------------------------------------------------------------
|
||||
//
|
||||
// Structure:
|
||||
// w_atc
|
||||
//
|
||||
//--------------------------------------------------------------------------
|
||||
`timescale 1ps/1ps
|
||||
|
||||
|
||||
module processing_system7_v5_5_w_atc #
|
||||
(
|
||||
parameter C_FAMILY = "rtl",
|
||||
// FPGA Family. Current version: virtex6, spartan6 or later.
|
||||
parameter integer C_AXI_ID_WIDTH = 4,
|
||||
// Width of all ID signals on SI and MI side of checker.
|
||||
// Range: >= 1.
|
||||
parameter integer C_AXI_DATA_WIDTH = 64,
|
||||
// Width of all DATA signals on SI and MI side of checker.
|
||||
// Range: 64.
|
||||
parameter integer C_AXI_WUSER_WIDTH = 1
|
||||
// Width of AWUSER signals.
|
||||
// Range: >= 1.
|
||||
)
|
||||
(
|
||||
// Global Signals
|
||||
input wire ARESET,
|
||||
input wire ACLK,
|
||||
|
||||
// Command Interface (In)
|
||||
input wire cmd_w_valid,
|
||||
input wire cmd_w_check,
|
||||
input wire [C_AXI_ID_WIDTH-1:0] cmd_w_id,
|
||||
output wire cmd_w_ready,
|
||||
|
||||
// Command Interface (Out)
|
||||
output wire cmd_b_push,
|
||||
output wire cmd_b_error,
|
||||
output reg [C_AXI_ID_WIDTH-1:0] cmd_b_id,
|
||||
input wire cmd_b_full,
|
||||
|
||||
// Slave Interface Write Port
|
||||
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID,
|
||||
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
|
||||
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
|
||||
input wire S_AXI_WLAST,
|
||||
input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
|
||||
input wire S_AXI_WVALID,
|
||||
output wire S_AXI_WREADY,
|
||||
|
||||
// Master Interface Write Address Port
|
||||
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID,
|
||||
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
|
||||
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
|
||||
output wire M_AXI_WLAST,
|
||||
output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
|
||||
output wire M_AXI_WVALID,
|
||||
input wire M_AXI_WREADY
|
||||
);
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Local params
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Variables for generating parameter controlled instances.
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Functions
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Internal signals
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Detecttion.
|
||||
wire any_strb_deasserted;
|
||||
wire incoming_strb_issue;
|
||||
reg first_word;
|
||||
reg strb_issue;
|
||||
|
||||
// Data flow.
|
||||
wire data_pop;
|
||||
wire cmd_b_push_blocked;
|
||||
reg cmd_b_push_i;
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Detect error:
|
||||
//
|
||||
// Detect and accumulate error when a transaction shall be scanned for
|
||||
// potential issues.
|
||||
// Accumulation of error is restarted for each ne transaction.
|
||||
//
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Check stobe information
|
||||
assign any_strb_deasserted = ( S_AXI_WSTRB != {C_AXI_DATA_WIDTH/8{1'b1}} );
|
||||
assign incoming_strb_issue = cmd_w_valid & S_AXI_WVALID & cmd_w_check & any_strb_deasserted;
|
||||
|
||||
// Keep track of first word in a transaction.
|
||||
always @ (posedge ACLK) begin
|
||||
if (ARESET) begin
|
||||
first_word <= 1'b1;
|
||||
end else if ( data_pop ) begin
|
||||
first_word <= S_AXI_WLAST;
|
||||
end
|
||||
end
|
||||
|
||||
// Keep track of error status.
|
||||
always @ (posedge ACLK) begin
|
||||
if (ARESET) begin
|
||||
strb_issue <= 1'b0;
|
||||
cmd_b_id <= {C_AXI_ID_WIDTH{1'b0}};
|
||||
end else if ( data_pop ) begin
|
||||
if ( first_word ) begin
|
||||
strb_issue <= incoming_strb_issue;
|
||||
end else begin
|
||||
strb_issue <= incoming_strb_issue | strb_issue;
|
||||
end
|
||||
cmd_b_id <= cmd_w_id;
|
||||
end
|
||||
end
|
||||
|
||||
assign cmd_b_error = strb_issue;
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Control command queue to B:
|
||||
//
|
||||
// Push command to B queue when all data for the transaction has flowed
|
||||
// through.
|
||||
// Delay pipelined command until there is room in the Queue.
|
||||
//
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Detect when data is popped.
|
||||
assign data_pop = S_AXI_WVALID & M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked;
|
||||
|
||||
// Push command when last word in transfered (pipelined).
|
||||
always @ (posedge ACLK) begin
|
||||
if (ARESET) begin
|
||||
cmd_b_push_i <= 1'b0;
|
||||
end else begin
|
||||
cmd_b_push_i <= ( S_AXI_WLAST & data_pop ) | cmd_b_push_blocked;
|
||||
end
|
||||
end
|
||||
|
||||
// Detect if pipelined push is blocked.
|
||||
assign cmd_b_push_blocked = cmd_b_push_i & cmd_b_full;
|
||||
|
||||
// Assign output.
|
||||
assign cmd_b_push = cmd_b_push_i & ~cmd_b_full;
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Transaction Throttling:
|
||||
//
|
||||
// Stall commands if FIFO is full or there is no valid command information
|
||||
// from AW.
|
||||
//
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Propagate masked valid.
|
||||
assign M_AXI_WVALID = S_AXI_WVALID & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked;
|
||||
|
||||
// Return ready with push back.
|
||||
assign S_AXI_WREADY = M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked;
|
||||
|
||||
// End of burst.
|
||||
assign cmd_w_ready = S_AXI_WVALID & M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked & S_AXI_WLAST;
|
||||
|
||||
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
// Write propagation:
|
||||
//
|
||||
// All information is simply forwarded on from the SI- to MI-Side untouched.
|
||||
//
|
||||
/////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// 1:1 mapping.
|
||||
assign M_AXI_WID = S_AXI_WID;
|
||||
assign M_AXI_WDATA = S_AXI_WDATA;
|
||||
assign M_AXI_WSTRB = S_AXI_WSTRB;
|
||||
assign M_AXI_WLAST = S_AXI_WLAST;
|
||||
assign M_AXI_WUSER = S_AXI_WUSER;
|
||||
|
||||
|
||||
endmodule
|
||||
+3013
File diff suppressed because it is too large
Load Diff
+71
@@ -0,0 +1,71 @@
|
||||
// (c) Copyright 2015 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//-----------------------------------------------------------------------------
|
||||
// Begin sc_node_v1_0_10_structs.svh
|
||||
//-----------------------------------------------------------------------------
|
||||
typedef logic [C_NUM_MI-1:0] t_route;
|
||||
typedef logic [C_INFO_WIDTH-1:0] t_info;
|
||||
typedef logic [C_LOG_MAX_DOWNSIZER_RATIO-1:0] t_downsizer_count;
|
||||
typedef logic [C_LOG_NUM_SI-1:0] t_source;
|
||||
typedef struct packed {
|
||||
t_max_byte_size end_pntr;
|
||||
t_max_byte_size start_pntr;
|
||||
t_downsizer_count repeat_count;
|
||||
} t_send;
|
||||
|
||||
typedef struct packed {
|
||||
t_source source;
|
||||
t_route sc_route;
|
||||
t_info info;
|
||||
} t_req;
|
||||
|
||||
typedef struct packed {
|
||||
t_send send;
|
||||
t_req req;
|
||||
} t_reqsend;
|
||||
//-----------------------------------------------------------------------------
|
||||
// end sc_node_v1_0_10_structs.svh
|
||||
//-----------------------------------------------------------------------------
|
||||
+5389
File diff suppressed because it is too large
Load Diff
+348
@@ -0,0 +1,348 @@
|
||||
`pragma protect begin_protected
|
||||
`pragma protect version = 1
|
||||
`pragma protect encrypt_agent = "XILINX"
|
||||
`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2019.1"
|
||||
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|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
|
||||
`pragma protect key_block
|
||||
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|
||||
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|
||||
|
||||
`pragma protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-2", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
|
||||
`pragma protect key_block
|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
|
||||
`pragma protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
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||||
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||||
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|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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||||
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||||
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||||
|
||||
`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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||||
`pragma protect key_block
|
||||
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||||
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|
||||
|
||||
`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-2", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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||||
`pragma protect key_block
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||||
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||||
|
||||
`pragma protect data_method = "AES128-CBC"
|
||||
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|
||||
`pragma protect data_block
|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
`pragma protect end_protected
|
||||
+225
@@ -0,0 +1,225 @@
|
||||
`pragma protect begin_protected
|
||||
`pragma protect version = 1
|
||||
`pragma protect encrypt_agent = "XILINX"
|
||||
`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2019.1"
|
||||
`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
|
||||
`pragma protect key_block
|
||||
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|
||||
qXX/K8xOuQ==
|
||||
|
||||
`pragma protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-2", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
|
||||
`pragma protect key_block
|
||||
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|
||||
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|
||||
DCgcXIbKRBreCq4f89o=
|
||||
|
||||
`pragma protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
9ezImbWfJ4w7FbQsZTMC2uytZYWq2KOV9cD/iA==
|
||||
|
||||
`pragma protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
t0QkxhBhwgmp7RAupHm12whYj3Qh2rhIrNbRIQ==
|
||||
|
||||
`pragma protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2019_02", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
|
||||
`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
|
||||
`pragma protect key_block
|
||||
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|
||||
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|
||||
Q3VuJYLKc8FoOFviMio=
|
||||
|
||||
`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-2", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
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|
||||
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|
||||
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|
||||
FfNieEAwVKyzHLFdHYs2PuclbqJq8KOswbU9yq6AtpqKGBYQnIqiID7Wfo7PM8QNp+wrA3pPE7mB
|
||||
0OeDdt5chXsg9Ybujf24v4hyNZEgSoI439vZtw==
|
||||
|
||||
`pragma protect data_method = "AES128-CBC"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 9136)
|
||||
`pragma protect data_block
|
||||
b8rUZ7HQ+COS+uN3pTGSCSBCfakg/e6HGKiTQSNZp/vRHVxXoFG7pW2kYxUrwk0ovkrnG/5X6brY
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
BX7C+5zF9upFg9ABDgf/mmeQ3vLMVRrJudGYOvpZiTTnYn+/PHWX0usziWPuuTAm6gaG3mdzGXs2
|
||||
I3U0Ds5kYrNG4f9dJ0Cm2NSE/ekoYGQR3HzRY6KvVpvjgQ/XbuDRoG/WIx3V/cRhd5aYowoR3ONR
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
j6e0Kp/CC98hdXoPvAm9UG/KIc4gFgNG12BCKqQ1o27cOIyEPo8tN0vFsKkCE5SMP6IV7hAYANSY
|
||||
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|
||||
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|
||||
VALhSZ7dNVBxFCv/sQlQ5dD35kmbp6IfZxQbDk7iVquTTP85IoOuZ2ujKLtp1OqiKNRi7roD4e39
|
||||
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|
||||
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|
||||
TDaOuut1lKVY6B05Rdp6IHd4BRtt3IrvKIG7yjofuGUdsL64r4lPHhoXQQF5tZQF9jKZCCk7FlXT
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
OZJZEEVF1eiNd4cTTe5EqaAvDm4T4cCY6rnNxWuB9ON9b93MifBzn47dvqZFFeKpkQyAstpCfO2H
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
4mvHKxDMbWpAfkYR+tO9Ag==
|
||||
`pragma protect end_protected
|
||||
+671
@@ -0,0 +1,671 @@
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Company: Xilinx
|
||||
// Engineer: Jim Tatsukawa, Karl Kurbjun and Carl Ribbing
|
||||
// Date: 7/30/2014
|
||||
// Design Name: MMCME2 DRP
|
||||
// Module Name: mmcme2_drp_func.h
|
||||
// Version: 1.04
|
||||
// Target Devices: 7 Series || MMCM
|
||||
// Tool versions: 2014.3
|
||||
// Description: This header provides the functions necessary to
|
||||
// calculate the DRP register values for the V6 MMCM.
|
||||
//
|
||||
// Revision Notes: 3/12 - Updating lookup_low/lookup_high (CR)
|
||||
// 4/13 - Fractional divide function in mmcm_frac_count_calc function. CRS610807
|
||||
//
|
||||
// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
|
||||
// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
|
||||
// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
|
||||
// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
|
||||
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
|
||||
// APPLICATION OR STANDARD, XILINX IS MAKING NO
|
||||
// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
|
||||
// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
|
||||
// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
|
||||
// REQUIRE FOR YOUR IMPLEMENTATION. XILINX
|
||||
// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
|
||||
// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
|
||||
// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
|
||||
// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
|
||||
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
|
||||
// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
// PURPOSE.
|
||||
//
|
||||
// (c) Copyright 2009-2010 Xilinx, Inc.
|
||||
// All rights reserved.
|
||||
//
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// These are user functions that should not be modified. Changes to the defines
|
||||
// or code within the functions may alter the accuracy of the calculations.
|
||||
|
||||
// Define debug to provide extra messages durring elaboration
|
||||
//`define DEBUG 1
|
||||
|
||||
// FRAC_PRECISION describes the width of the fractional portion of the fixed
|
||||
// point numbers. These should not be modified, they are for development
|
||||
// only
|
||||
`define FRAC_PRECISION 10
|
||||
// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
|
||||
// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs
|
||||
// greater than 32
|
||||
`define FIXED_WIDTH 32
|
||||
|
||||
// This function takes a fixed point number and rounds it to the nearest
|
||||
// fractional precision bit.
|
||||
function [`FIXED_WIDTH:1] round_frac
|
||||
(
|
||||
// Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
|
||||
input [`FIXED_WIDTH:1] decimal,
|
||||
|
||||
// This describes the precision of the fraction, for example a value
|
||||
// of 1 would modify the fractional so that instead of being a .16
|
||||
// fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
|
||||
input [`FIXED_WIDTH:1] precision
|
||||
);
|
||||
|
||||
begin
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("round_frac - decimal: %h, precision: %h", decimal, precision);
|
||||
`endif
|
||||
// If the fractional precision bit is high then round up
|
||||
if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
|
||||
round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
|
||||
end else begin
|
||||
round_frac = decimal;
|
||||
end
|
||||
`ifdef DEBUG
|
||||
$display("round_frac: %h", round_frac);
|
||||
`endif
|
||||
end
|
||||
endfunction
|
||||
|
||||
// This function calculates high_time, low_time, w_edge, and no_count
|
||||
// of a non-fractional counter based on the divide and duty cycle
|
||||
//
|
||||
// NOTE: high_time and low_time are returned as integers between 0 and 63
|
||||
// inclusive. 64 should equal 6'b000000 (in other words it is okay to
|
||||
// ignore the overflow)
|
||||
function [13:0] mmcm_pll_divider
|
||||
(
|
||||
input [7:0] divide, // Max divide is 128
|
||||
input [31:0] duty_cycle // Duty cycle is multiplied by 100,000
|
||||
);
|
||||
|
||||
reg [`FIXED_WIDTH:1] duty_cycle_fix;
|
||||
|
||||
// High/Low time is initially calculated with a wider integer to prevent a
|
||||
// calculation error when it overflows to 64.
|
||||
reg [6:0] high_time;
|
||||
reg [6:0] low_time;
|
||||
reg w_edge;
|
||||
reg no_count;
|
||||
|
||||
reg [`FIXED_WIDTH:1] temp;
|
||||
|
||||
begin
|
||||
// Duty Cycle must be between 0 and 1,000
|
||||
if(duty_cycle <=0 || duty_cycle >= 100000) begin
|
||||
`ifndef SYNTHESIS
|
||||
$display("ERROR: duty_cycle: %d is invalid", duty_cycle);
|
||||
`endif
|
||||
$finish;
|
||||
end
|
||||
|
||||
// Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
|
||||
duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("duty_cycle_fix: %h", duty_cycle_fix);
|
||||
`endif
|
||||
|
||||
// If the divide is 1 nothing needs to be set except the no_count bit.
|
||||
// Other values are dummies
|
||||
if(divide == 7'h01) begin
|
||||
high_time = 7'h01;
|
||||
w_edge = 1'b0;
|
||||
low_time = 7'h01;
|
||||
no_count = 1'b1;
|
||||
end else begin
|
||||
temp = round_frac(duty_cycle_fix*divide, 1);
|
||||
|
||||
// comes from above round_frac
|
||||
high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1];
|
||||
// If the duty cycle * divide rounded is .5 or greater then this bit
|
||||
// is set.
|
||||
w_edge = temp[`FRAC_PRECISION]; // comes from round_frac
|
||||
|
||||
// If the high time comes out to 0, it needs to be set to at least 1
|
||||
// and w_edge set to 0
|
||||
if(high_time == 7'h00) begin
|
||||
high_time = 7'h01;
|
||||
w_edge = 1'b0;
|
||||
end
|
||||
|
||||
if(high_time == divide) begin
|
||||
high_time = divide - 1;
|
||||
w_edge = 1'b1;
|
||||
end
|
||||
|
||||
// Calculate low_time based on the divide setting and set no_count to
|
||||
// 0 as it is only used when divide is 1.
|
||||
low_time = divide - high_time;
|
||||
no_count = 1'b0;
|
||||
end
|
||||
|
||||
// Set the return value.
|
||||
mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
|
||||
end
|
||||
endfunction
|
||||
|
||||
// This function calculates mx, delay_time, and phase_mux
|
||||
// of a non-fractional counter based on the divide and phase
|
||||
//
|
||||
// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
|
||||
// is used.
|
||||
function [10:0] mmcm_pll_phase
|
||||
(
|
||||
// divide must be an integer (use fractional if not)
|
||||
// assumed that divide already checked to be valid
|
||||
input [7:0] divide, // Max divide is 128
|
||||
|
||||
// Phase is given in degrees (-360,000 to 360,000)
|
||||
input signed [31:0] phase
|
||||
);
|
||||
|
||||
reg [`FIXED_WIDTH:1] phase_in_cycles;
|
||||
reg [`FIXED_WIDTH:1] phase_fixed;
|
||||
reg [1:0] mx;
|
||||
reg [5:0] delay_time;
|
||||
reg [2:0] phase_mux;
|
||||
|
||||
reg [`FIXED_WIDTH:1] temp;
|
||||
|
||||
begin
|
||||
`ifdef DEBUG
|
||||
$display("mmcm_pll_phase-divide:%d,phase:%d",
|
||||
divide, phase);
|
||||
`endif
|
||||
|
||||
if ((phase < -360000) || (phase > 360000)) begin
|
||||
`ifndef SYNTHESIS
|
||||
$display("ERROR: phase of $phase is not between -360000 and 360000");
|
||||
`endif
|
||||
$finish;
|
||||
end
|
||||
|
||||
// If phase is less than 0, convert it to a positive phase shift
|
||||
// Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
|
||||
if(phase < 0) begin
|
||||
phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
|
||||
end else begin
|
||||
phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
|
||||
end
|
||||
|
||||
// Put phase in terms of decimal number of vco clock cycles
|
||||
phase_in_cycles = ( phase_fixed * divide ) / 360;
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("phase_in_cycles: %h", phase_in_cycles);
|
||||
`endif
|
||||
|
||||
|
||||
temp = round_frac(phase_in_cycles, 3);
|
||||
|
||||
// set mx to 2'b00 that the phase mux from the VCO is enabled
|
||||
mx = 2'b00;
|
||||
phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
|
||||
delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("temp: %h", temp);
|
||||
`endif
|
||||
|
||||
// Setup the return value
|
||||
mmcm_pll_phase={mx, phase_mux, delay_time};
|
||||
end
|
||||
endfunction
|
||||
|
||||
// This function takes the divide value and outputs the necessary lock values
|
||||
function [39:0] mmcm_pll_lock_lookup
|
||||
(
|
||||
input [6:0] divide // Max divide is 64
|
||||
);
|
||||
|
||||
reg [2559:0] lookup;
|
||||
|
||||
begin
|
||||
lookup = {
|
||||
// This table is composed of:
|
||||
// LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
|
||||
40'b00110_00110_1111101000_1111101001_0000000001,
|
||||
40'b00110_00110_1111101000_1111101001_0000000001,
|
||||
40'b01000_01000_1111101000_1111101001_0000000001,
|
||||
40'b01011_01011_1111101000_1111101001_0000000001,
|
||||
40'b01110_01110_1111101000_1111101001_0000000001,
|
||||
40'b10001_10001_1111101000_1111101001_0000000001,
|
||||
40'b10011_10011_1111101000_1111101001_0000000001,
|
||||
40'b10110_10110_1111101000_1111101001_0000000001,
|
||||
40'b11001_11001_1111101000_1111101001_0000000001,
|
||||
40'b11100_11100_1111101000_1111101001_0000000001,
|
||||
40'b11111_11111_1110000100_1111101001_0000000001,
|
||||
40'b11111_11111_1100111001_1111101001_0000000001,
|
||||
40'b11111_11111_1011101110_1111101001_0000000001,
|
||||
40'b11111_11111_1010111100_1111101001_0000000001,
|
||||
40'b11111_11111_1010001010_1111101001_0000000001,
|
||||
40'b11111_11111_1001110001_1111101001_0000000001,
|
||||
40'b11111_11111_1000111111_1111101001_0000000001,
|
||||
40'b11111_11111_1000100110_1111101001_0000000001,
|
||||
40'b11111_11111_1000001101_1111101001_0000000001,
|
||||
40'b11111_11111_0111110100_1111101001_0000000001,
|
||||
40'b11111_11111_0111011011_1111101001_0000000001,
|
||||
40'b11111_11111_0111000010_1111101001_0000000001,
|
||||
40'b11111_11111_0110101001_1111101001_0000000001,
|
||||
40'b11111_11111_0110010000_1111101001_0000000001,
|
||||
40'b11111_11111_0110010000_1111101001_0000000001,
|
||||
40'b11111_11111_0101110111_1111101001_0000000001,
|
||||
40'b11111_11111_0101011110_1111101001_0000000001,
|
||||
40'b11111_11111_0101011110_1111101001_0000000001,
|
||||
40'b11111_11111_0101000101_1111101001_0000000001,
|
||||
40'b11111_11111_0101000101_1111101001_0000000001,
|
||||
40'b11111_11111_0100101100_1111101001_0000000001,
|
||||
40'b11111_11111_0100101100_1111101001_0000000001,
|
||||
40'b11111_11111_0100101100_1111101001_0000000001,
|
||||
40'b11111_11111_0100010011_1111101001_0000000001,
|
||||
40'b11111_11111_0100010011_1111101001_0000000001,
|
||||
40'b11111_11111_0100010011_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001
|
||||
};
|
||||
|
||||
// Set lookup_entry with the explicit bits from lookup with a part select
|
||||
mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40];
|
||||
`ifdef DEBUG
|
||||
$display("lock_lookup: %b", mmcm_pll_lock_lookup);
|
||||
`endif
|
||||
end
|
||||
endfunction
|
||||
|
||||
// This function takes the divide value and the bandwidth setting of the MMCM
|
||||
// and outputs the digital filter settings necessary.
|
||||
function [9:0] mmcm_pll_filter_lookup
|
||||
(
|
||||
input [6:0] divide, // Max divide is 64
|
||||
input [8*9:0] BANDWIDTH
|
||||
);
|
||||
|
||||
reg [639:0] lookup_low;
|
||||
reg [639:0] lookup_high;
|
||||
|
||||
reg [9:0] lookup_entry;
|
||||
|
||||
begin
|
||||
lookup_low = {
|
||||
// CP_RES_LFHF
|
||||
10'b0010_1111_00,
|
||||
10'b0010_1111_00,
|
||||
10'b0010_1111_00,
|
||||
10'b0010_1111_00,
|
||||
10'b0010_0111_00,
|
||||
10'b0010_1011_00,
|
||||
10'b0010_1101_00,
|
||||
10'b0010_0011_00,
|
||||
10'b0010_0101_00,
|
||||
10'b0010_0101_00,
|
||||
10'b0010_1001_00,
|
||||
10'b0010_1110_00,
|
||||
10'b0010_1110_00,
|
||||
10'b0010_1110_00,
|
||||
10'b0010_1110_00,
|
||||
10'b0010_0001_00,
|
||||
10'b0010_0001_00,
|
||||
10'b0010_0001_00,
|
||||
10'b0010_0110_00,
|
||||
10'b0010_0110_00,
|
||||
10'b0010_0110_00,
|
||||
10'b0010_0110_00,
|
||||
10'b0010_0110_00,
|
||||
10'b0010_0110_00,
|
||||
10'b0010_0110_00,
|
||||
10'b0010_1010_00,
|
||||
10'b0010_1010_00,
|
||||
10'b0010_1010_00,
|
||||
10'b0010_1010_00,
|
||||
10'b0010_1010_00,
|
||||
10'b0010_1100_00,
|
||||
10'b0010_1100_00,
|
||||
10'b0010_1100_00,
|
||||
10'b0010_1100_00,
|
||||
10'b0010_1100_00,
|
||||
10'b0010_1100_00,
|
||||
10'b0010_1100_00,
|
||||
10'b0010_1100_00,
|
||||
10'b0010_1100_00,
|
||||
10'b0010_1100_00,
|
||||
10'b0010_1100_00,
|
||||
10'b0010_1100_00,
|
||||
10'b0010_1100_00,
|
||||
10'b0010_1100_00,
|
||||
10'b0010_1100_00,
|
||||
10'b0010_1100_00,
|
||||
10'b0010_1100_00,
|
||||
10'b0010_0010_00,
|
||||
10'b0010_0010_00,
|
||||
10'b0010_0010_00,
|
||||
10'b0010_0010_00,
|
||||
10'b0010_0010_00,
|
||||
10'b0010_0010_00,
|
||||
10'b0010_0010_00,
|
||||
10'b0010_0010_00,
|
||||
10'b0010_0010_00,
|
||||
10'b0010_0010_00,
|
||||
10'b0010_0010_00,
|
||||
10'b0010_0010_00,
|
||||
10'b0010_0010_00,
|
||||
10'b0010_0010_00,
|
||||
10'b0010_0010_00,
|
||||
10'b0010_0010_00,
|
||||
10'b0010_0010_00
|
||||
};
|
||||
|
||||
lookup_high = {
|
||||
// CP_RES_LFHF
|
||||
10'b0010_1111_00,
|
||||
10'b0100_1111_00,
|
||||
10'b0101_1011_00,
|
||||
10'b0111_0111_00,
|
||||
10'b1101_0111_00,
|
||||
10'b1110_1011_00,
|
||||
10'b1110_1101_00,
|
||||
10'b1111_0011_00,
|
||||
10'b1110_0101_00,
|
||||
10'b1111_0101_00,
|
||||
10'b1111_1001_00,
|
||||
10'b1101_0001_00,
|
||||
10'b1111_1001_00,
|
||||
10'b1111_1001_00,
|
||||
10'b1111_1001_00,
|
||||
10'b1111_1001_00,
|
||||
10'b1111_0101_00,
|
||||
10'b1111_0101_00,
|
||||
10'b1100_0001_00,
|
||||
10'b1100_0001_00,
|
||||
10'b1100_0001_00,
|
||||
10'b0101_1100_00,
|
||||
10'b0101_1100_00,
|
||||
10'b0101_1100_00,
|
||||
10'b0101_1100_00,
|
||||
10'b0011_0100_00,
|
||||
10'b0011_0100_00,
|
||||
10'b0011_0100_00,
|
||||
10'b0011_0100_00,
|
||||
10'b0011_0100_00,
|
||||
10'b0011_0100_00,
|
||||
10'b0011_0100_00,
|
||||
10'b0011_0100_00,
|
||||
10'b0011_0100_00,
|
||||
10'b0011_0100_00,
|
||||
10'b0011_0100_00,
|
||||
10'b0011_0100_00,
|
||||
10'b0011_0100_00,
|
||||
10'b0011_0100_00,
|
||||
10'b0011_0100_00,
|
||||
10'b0011_0100_00,
|
||||
10'b0010_1000_00,
|
||||
10'b0010_1000_00,
|
||||
10'b0010_1000_00,
|
||||
10'b0010_1000_00,
|
||||
10'b0010_1000_00,
|
||||
10'b0111_0001_00,
|
||||
10'b0111_0001_00,
|
||||
10'b0100_1100_00,
|
||||
10'b0100_1100_00,
|
||||
10'b0100_1100_00,
|
||||
10'b0100_1100_00,
|
||||
10'b0110_0001_00,
|
||||
10'b0110_0001_00,
|
||||
10'b0101_0110_00,
|
||||
10'b0101_0110_00,
|
||||
10'b0101_0110_00,
|
||||
10'b0010_0100_00,
|
||||
10'b0010_0100_00,
|
||||
10'b0010_0100_00,
|
||||
10'b0010_0100_00,
|
||||
10'b0100_1010_00,
|
||||
10'b0011_1100_00,
|
||||
10'b0011_1100_00
|
||||
};
|
||||
|
||||
// Set lookup_entry with the explicit bits from lookup with a part select
|
||||
if(BANDWIDTH == "LOW") begin
|
||||
// Low Bandwidth
|
||||
mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10];
|
||||
end else begin
|
||||
// High or optimized bandwidth
|
||||
mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10];
|
||||
end
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("filter_lookup: %b", mmcm_pll_filter_lookup);
|
||||
`endif
|
||||
end
|
||||
endfunction
|
||||
|
||||
// This function takes in the divide, phase, and duty cycle
|
||||
// setting to calculate the upper and lower counter registers.
|
||||
function [37:0] mmcm_pll_count_calc
|
||||
(
|
||||
input [7:0] divide, // Max divide is 128
|
||||
input signed [31:0] phase,
|
||||
input [31:0] duty_cycle // Multiplied by 100,000
|
||||
);
|
||||
|
||||
reg [13:0] div_calc;
|
||||
reg [16:0] phase_calc;
|
||||
|
||||
begin
|
||||
`ifdef DEBUG
|
||||
$display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
|
||||
divide, phase, duty_cycle);
|
||||
`endif
|
||||
|
||||
// w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
|
||||
div_calc = mmcm_pll_divider(divide, duty_cycle);
|
||||
// mx[10:9], pm[8:6], dt[5:0]
|
||||
phase_calc = mmcm_pll_phase(divide, phase);
|
||||
|
||||
// Return value is the upper and lower address of counter
|
||||
// Upper address is:
|
||||
// RESERVED [31:26]
|
||||
// MX [25:24]
|
||||
// EDGE [23]
|
||||
// NOCOUNT [22]
|
||||
// DELAY_TIME [21:16]
|
||||
// Lower Address is:
|
||||
// PHASE_MUX [15:13]
|
||||
// RESERVED [12]
|
||||
// HIGH_TIME [11:6]
|
||||
// LOW_TIME [5:0]
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
|
||||
divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0],
|
||||
div_calc[13], div_calc[12],
|
||||
phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]);
|
||||
`endif
|
||||
|
||||
mmcm_pll_count_calc =
|
||||
{
|
||||
// Upper Address
|
||||
6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0],
|
||||
// Lower Address
|
||||
phase_calc[8:6], 1'b0, div_calc[11:0]
|
||||
};
|
||||
end
|
||||
endfunction
|
||||
|
||||
|
||||
// This function takes in the divide, phase, and duty cycle
|
||||
// setting to calculate the upper and lower counter registers.
|
||||
// for fractional multiply/divide functions.
|
||||
//
|
||||
//
|
||||
function [37:0] mmcm_frac_count_calc
|
||||
(
|
||||
input [7:0] divide, // Max divide is 128
|
||||
input signed [31:0] phase,
|
||||
input [31:0] duty_cycle, // Multiplied by 1,000
|
||||
input [9:0] frac // Multiplied by 1000
|
||||
);
|
||||
|
||||
//Required for fractional divide calculations
|
||||
reg [7:0] lt_frac;
|
||||
reg [7:0] ht_frac;
|
||||
|
||||
reg /*[7:0]*/ wf_fall_frac;
|
||||
reg /*[7:0]*/ wf_rise_frac;
|
||||
|
||||
reg [31:0] a;
|
||||
reg [7:0] pm_rise_frac_filtered ;
|
||||
reg [7:0] pm_fall_frac_filtered ;
|
||||
reg [7:0] clkout0_divide_int;
|
||||
reg [2:0] clkout0_divide_frac;
|
||||
reg [7:0] even_part_high;
|
||||
reg [7:0] even_part_low;
|
||||
|
||||
reg [7:0] odd;
|
||||
reg [7:0] odd_and_frac;
|
||||
|
||||
reg [7:0] pm_fall;
|
||||
reg [7:0] pm_rise;
|
||||
reg [7:0] dt;
|
||||
reg [7:0] dt_int;
|
||||
reg [63:0] dt_calc;
|
||||
|
||||
reg [7:0] pm_rise_frac;
|
||||
reg [7:0] pm_fall_frac;
|
||||
|
||||
reg [31:0] a_per_in_octets;
|
||||
reg [31:0] a_phase_in_cycles;
|
||||
|
||||
parameter precision = 0.125;
|
||||
|
||||
reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11
|
||||
reg [31: 0] phase_pos;
|
||||
reg [31: 0] phase_vco;
|
||||
reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11
|
||||
reg [13:0] div_calc;
|
||||
reg [16:0] phase_calc;
|
||||
|
||||
begin
|
||||
`ifdef DEBUG
|
||||
$display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d",
|
||||
divide, phase, duty_cycle);
|
||||
`endif
|
||||
|
||||
//convert phase to fixed
|
||||
if ((phase < -360000) || (phase > 360000)) begin
|
||||
`ifndef SYNTHESIS
|
||||
$display("ERROR: phase of $phase is not between -360000 and 360000");
|
||||
`endif
|
||||
$finish;
|
||||
end
|
||||
|
||||
|
||||
// Return value is
|
||||
// Transfer data
|
||||
// RESERVED [37:36]
|
||||
// FRAC_TIME [35:33]
|
||||
// FRAC_WF_FALL [32]
|
||||
// Upper address is:
|
||||
// RESERVED [31:26]
|
||||
// MX [25:24]
|
||||
// EDGE [23]
|
||||
// NOCOUNT [22]
|
||||
// DELAY_TIME [21:16]
|
||||
// Lower Address is:
|
||||
// PHASE_MUX [15:13]
|
||||
// RESERVED [12]
|
||||
// HIGH_TIME [11:6]
|
||||
// LOW_TIME [5:0]
|
||||
|
||||
|
||||
|
||||
clkout0_divide_frac = frac / 125;
|
||||
clkout0_divide_int = divide;
|
||||
|
||||
even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2);
|
||||
even_part_low = even_part_high;
|
||||
|
||||
odd = clkout0_divide_int - even_part_high - even_part_low;
|
||||
odd_and_frac = (8*odd) + clkout0_divide_frac;
|
||||
|
||||
lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1)
|
||||
ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1)
|
||||
|
||||
pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2
|
||||
pm_rise = 0; //0
|
||||
|
||||
wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || ((clkout0_divide_frac == 1) && (clkout0_divide_int == 2));//CRS610807
|
||||
wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0)
|
||||
|
||||
|
||||
|
||||
//Calculate phase in fractional cycles
|
||||
a_per_in_octets = (8 * divide) + (frac / 125) ;
|
||||
a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors
|
||||
pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000};
|
||||
|
||||
dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8)
|
||||
dt = dt_calc[7:0];
|
||||
|
||||
pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a;
|
||||
|
||||
dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt)
|
||||
pm_fall_frac = pm_fall + pm_rise_frac;
|
||||
pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000};
|
||||
|
||||
div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6]
|
||||
phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]}
|
||||
|
||||
mmcm_frac_count_calc[37:0] =
|
||||
{ 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac,
|
||||
1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0],
|
||||
pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0]
|
||||
} ;
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac);
|
||||
`endif
|
||||
|
||||
end
|
||||
endfunction
|
||||
|
||||
+531
@@ -0,0 +1,531 @@
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Company: Xilinx
|
||||
// Engineer: Jim Tatsukawa, Karl Kurbjun and Carl Ribbing
|
||||
// Date: 7/30/2014
|
||||
// Design Name: PLLE2 DRP
|
||||
// Module Name: plle2_drp_func.h
|
||||
// Version: 2.00
|
||||
// Target Devices: 7 Series || PLL
|
||||
// Tool versions: 2014.3
|
||||
// Description: This header provides the functions necessary to
|
||||
// calculate the DRP register values for the V6 PLL.
|
||||
// Updated for CR663854.
|
||||
//
|
||||
// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
|
||||
// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
|
||||
// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
|
||||
// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
|
||||
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
|
||||
// APPLICATION OR STANDARD, XILINX IS MAKING NO
|
||||
// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
|
||||
// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
|
||||
// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
|
||||
// REQUIRE FOR YOUR IMPLEMENTATION. XILINX
|
||||
// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
|
||||
// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
|
||||
// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
|
||||
// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
|
||||
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
|
||||
// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
// PURPOSE.
|
||||
//
|
||||
// (c) Copyright 2009-2010 Xilinx, Inc.
|
||||
// All rights reserved.
|
||||
//
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// These are user functions that should not be modified. Changes to the defines
|
||||
// or code within the functions may alter the accuracy of the calculations.
|
||||
|
||||
// Define debug to provide extra messages durring elaboration
|
||||
//`define DEBUG 1
|
||||
|
||||
// FRAC_PRECISION describes the width of the fractional portion of the fixed
|
||||
// point numbers. These should not be modified, they are for development
|
||||
// only
|
||||
`define FRAC_PRECISION 10
|
||||
// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
|
||||
// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs
|
||||
// greater than 32
|
||||
`define FIXED_WIDTH 32
|
||||
|
||||
// This function takes a fixed point number and rounds it to the nearest
|
||||
// fractional precision bit.
|
||||
function [`FIXED_WIDTH:1] round_frac
|
||||
(
|
||||
// Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
|
||||
input [`FIXED_WIDTH:1] decimal,
|
||||
|
||||
// This describes the precision of the fraction, for example a value
|
||||
// of 1 would modify the fractional so that instead of being a .16
|
||||
// fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
|
||||
input [`FIXED_WIDTH:1] precision
|
||||
);
|
||||
|
||||
begin
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("round_frac - decimal: %h, precision: %h", decimal, precision);
|
||||
`endif
|
||||
// If the fractional precision bit is high then round up
|
||||
if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
|
||||
round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
|
||||
end else begin
|
||||
round_frac = decimal;
|
||||
end
|
||||
`ifdef DEBUG
|
||||
$display("round_frac: %h", round_frac);
|
||||
`endif
|
||||
end
|
||||
endfunction
|
||||
|
||||
// This function calculates high_time, low_time, w_edge, and no_count
|
||||
// of a non-fractional counter based on the divide and duty cycle
|
||||
//
|
||||
// NOTE: high_time and low_time are returned as integers between 0 and 63
|
||||
// inclusive. 64 should equal 6'b000000 (in other words it is okay to
|
||||
// ignore the overflow)
|
||||
function [13:0] mmcm_pll_divider
|
||||
(
|
||||
input [7:0] divide, // Max divide is 128
|
||||
input [31:0] duty_cycle // Duty cycle is multiplied by 100,000
|
||||
);
|
||||
|
||||
reg [`FIXED_WIDTH:1] duty_cycle_fix;
|
||||
|
||||
// High/Low time is initially calculated with a wider integer to prevent a
|
||||
// calculation error when it overflows to 64.
|
||||
reg [6:0] high_time;
|
||||
reg [6:0] low_time;
|
||||
reg w_edge;
|
||||
reg no_count;
|
||||
|
||||
reg [`FIXED_WIDTH:1] temp;
|
||||
|
||||
begin
|
||||
// Duty Cycle must be between 0 and 1,000
|
||||
if(duty_cycle <=0 || duty_cycle >= 100000) begin
|
||||
`ifndef SYNTHESIS
|
||||
$display("ERROR: duty_cycle: %d is invalid", duty_cycle);
|
||||
`endif
|
||||
$finish;
|
||||
end
|
||||
|
||||
// Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
|
||||
duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("duty_cycle_fix: %h", duty_cycle_fix);
|
||||
`endif
|
||||
|
||||
// If the divide is 1 nothing needs to be set except the no_count bit.
|
||||
// Other values are dummies
|
||||
if(divide == 7'h01) begin
|
||||
high_time = 7'h01;
|
||||
w_edge = 1'b0;
|
||||
low_time = 7'h01;
|
||||
no_count = 1'b1;
|
||||
end else begin
|
||||
temp = round_frac(duty_cycle_fix*divide, 1);
|
||||
|
||||
// comes from above round_frac
|
||||
high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1];
|
||||
// If the duty cycle * divide rounded is .5 or greater then this bit
|
||||
// is set.
|
||||
w_edge = temp[`FRAC_PRECISION]; // comes from round_frac
|
||||
|
||||
// If the high time comes out to 0, it needs to be set to at least 1
|
||||
// and w_edge set to 0
|
||||
if(high_time == 7'h00) begin
|
||||
high_time = 7'h01;
|
||||
w_edge = 1'b0;
|
||||
end
|
||||
|
||||
if(high_time == divide) begin
|
||||
high_time = divide - 1;
|
||||
w_edge = 1'b1;
|
||||
end
|
||||
|
||||
// Calculate low_time based on the divide setting and set no_count to
|
||||
// 0 as it is only used when divide is 1.
|
||||
low_time = divide - high_time;
|
||||
no_count = 1'b0;
|
||||
end
|
||||
|
||||
// Set the return value.
|
||||
mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
|
||||
end
|
||||
endfunction
|
||||
|
||||
// This function calculates mx, delay_time, and phase_mux
|
||||
// of a non-fractional counter based on the divide and phase
|
||||
//
|
||||
// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
|
||||
// is used.
|
||||
function [10:0] mmcm_pll_phase
|
||||
(
|
||||
// divide must be an integer (use fractional if not)
|
||||
// assumed that divide already checked to be valid
|
||||
input [7:0] divide, // Max divide is 128
|
||||
|
||||
// Phase is given in degrees (-360,000 to 360,000)
|
||||
input signed [31:0] phase
|
||||
);
|
||||
|
||||
reg [`FIXED_WIDTH:1] phase_in_cycles;
|
||||
reg [`FIXED_WIDTH:1] phase_fixed;
|
||||
reg [1:0] mx;
|
||||
reg [5:0] delay_time;
|
||||
reg [2:0] phase_mux;
|
||||
|
||||
reg [`FIXED_WIDTH:1] temp;
|
||||
|
||||
begin
|
||||
`ifdef DEBUG
|
||||
$display("mmcm_pll_phase-divide:%d,phase:%d",
|
||||
divide, phase);
|
||||
`endif
|
||||
|
||||
if ((phase < -360000) || (phase > 360000)) begin
|
||||
`ifndef SYNTHESIS
|
||||
$display("ERROR: phase of $phase is not between -360000 and 360000");
|
||||
`endif
|
||||
$finish;
|
||||
end
|
||||
|
||||
// If phase is less than 0, convert it to a positive phase shift
|
||||
// Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
|
||||
if(phase < 0) begin
|
||||
phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
|
||||
end else begin
|
||||
phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
|
||||
end
|
||||
|
||||
// Put phase in terms of decimal number of vco clock cycles
|
||||
phase_in_cycles = ( phase_fixed * divide ) / 360;
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("phase_in_cycles: %h", phase_in_cycles);
|
||||
`endif
|
||||
|
||||
|
||||
temp = round_frac(phase_in_cycles, 3);
|
||||
|
||||
// set mx to 2'b00 that the phase mux from the VCO is enabled
|
||||
mx = 2'b00;
|
||||
phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
|
||||
delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("temp: %h", temp);
|
||||
`endif
|
||||
|
||||
// Setup the return value
|
||||
mmcm_pll_phase={mx, phase_mux, delay_time};
|
||||
end
|
||||
endfunction
|
||||
|
||||
// This function takes the divide value and outputs the necessary lock values
|
||||
function [39:0] mmcm_pll_lock_lookup
|
||||
(
|
||||
input [6:0] divide // Max divide is 64
|
||||
);
|
||||
|
||||
reg [2559:0] lookup;
|
||||
|
||||
begin
|
||||
lookup = {
|
||||
// This table is composed of:
|
||||
// LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
|
||||
40'b00110_00110_1111101000_1111101001_0000000001,
|
||||
40'b00110_00110_1111101000_1111101001_0000000001,
|
||||
40'b01000_01000_1111101000_1111101001_0000000001,
|
||||
40'b01011_01011_1111101000_1111101001_0000000001,
|
||||
40'b01110_01110_1111101000_1111101001_0000000001,
|
||||
40'b10001_10001_1111101000_1111101001_0000000001,
|
||||
40'b10011_10011_1111101000_1111101001_0000000001,
|
||||
40'b10110_10110_1111101000_1111101001_0000000001,
|
||||
40'b11001_11001_1111101000_1111101001_0000000001,
|
||||
40'b11100_11100_1111101000_1111101001_0000000001,
|
||||
40'b11111_11111_1110000100_1111101001_0000000001,
|
||||
40'b11111_11111_1100111001_1111101001_0000000001,
|
||||
40'b11111_11111_1011101110_1111101001_0000000001,
|
||||
40'b11111_11111_1010111100_1111101001_0000000001,
|
||||
40'b11111_11111_1010001010_1111101001_0000000001,
|
||||
40'b11111_11111_1001110001_1111101001_0000000001,
|
||||
40'b11111_11111_1000111111_1111101001_0000000001,
|
||||
40'b11111_11111_1000100110_1111101001_0000000001,
|
||||
40'b11111_11111_1000001101_1111101001_0000000001,
|
||||
40'b11111_11111_0111110100_1111101001_0000000001,
|
||||
40'b11111_11111_0111011011_1111101001_0000000001,
|
||||
40'b11111_11111_0111000010_1111101001_0000000001,
|
||||
40'b11111_11111_0110101001_1111101001_0000000001,
|
||||
40'b11111_11111_0110010000_1111101001_0000000001,
|
||||
40'b11111_11111_0110010000_1111101001_0000000001,
|
||||
40'b11111_11111_0101110111_1111101001_0000000001,
|
||||
40'b11111_11111_0101011110_1111101001_0000000001,
|
||||
40'b11111_11111_0101011110_1111101001_0000000001,
|
||||
40'b11111_11111_0101000101_1111101001_0000000001,
|
||||
40'b11111_11111_0101000101_1111101001_0000000001,
|
||||
40'b11111_11111_0100101100_1111101001_0000000001,
|
||||
40'b11111_11111_0100101100_1111101001_0000000001,
|
||||
40'b11111_11111_0100101100_1111101001_0000000001,
|
||||
40'b11111_11111_0100010011_1111101001_0000000001,
|
||||
40'b11111_11111_0100010011_1111101001_0000000001,
|
||||
40'b11111_11111_0100010011_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001
|
||||
};
|
||||
|
||||
// Set lookup_entry with the explicit bits from lookup with a part select
|
||||
mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40];
|
||||
`ifdef DEBUG
|
||||
$display("lock_lookup: %b", mmcm_pll_lock_lookup);
|
||||
`endif
|
||||
end
|
||||
endfunction
|
||||
|
||||
// This function takes the divide value and the bandwidth setting of the PLL
|
||||
// and outputs the digital filter settings necessary.
|
||||
function [9:0] mmcm_pll_filter_lookup
|
||||
(
|
||||
input [6:0] divide, // Max divide is 64
|
||||
input [8*9:0] BANDWIDTH
|
||||
);
|
||||
|
||||
reg [639:0] lookup_low;
|
||||
reg [639:0] lookup_high;
|
||||
|
||||
reg [9:0] lookup_entry;
|
||||
|
||||
begin
|
||||
lookup_low = {
|
||||
// CP_RES_LFHF
|
||||
10'b0010_1111_00,
|
||||
10'b0010_1111_00,
|
||||
10'b0010_0111_00,
|
||||
10'b0010_1101_00,
|
||||
10'b0010_0101_00,
|
||||
10'b0010_0101_00,
|
||||
10'b0010_1001_00,
|
||||
10'b0010_1110_00,
|
||||
10'b0010_1110_00,
|
||||
10'b0010_0001_00,
|
||||
10'b0010_0001_00,
|
||||
10'b0010_0110_00,
|
||||
10'b0010_0110_00,
|
||||
10'b0010_0110_00,
|
||||
10'b0010_0110_00,
|
||||
10'b0010_1010_00,
|
||||
10'b0010_1010_00,
|
||||
10'b0010_1010_00,
|
||||
10'b0010_1010_00,
|
||||
10'b0010_1100_00,
|
||||
10'b0010_1100_00,
|
||||
10'b0010_1100_00,
|
||||
10'b0010_1100_00,
|
||||
10'b0010_1100_00,
|
||||
10'b0010_1100_00,
|
||||
10'b0010_1100_00,
|
||||
10'b0010_1100_00,
|
||||
10'b0010_1100_00,
|
||||
10'b0010_1100_00,
|
||||
10'b0010_1100_00,
|
||||
10'b0010_0010_00,
|
||||
10'b0010_0010_00,
|
||||
10'b0010_0010_00,
|
||||
10'b0010_0010_00,
|
||||
10'b0010_0010_00,
|
||||
10'b0010_0010_00,
|
||||
10'b0010_0010_00,
|
||||
10'b0010_0010_00,
|
||||
10'b0010_0010_00,
|
||||
10'b0010_0010_00,
|
||||
10'b0011_1100_00,
|
||||
10'b0011_1100_00,
|
||||
10'b0011_1100_00,
|
||||
10'b0011_1100_00,
|
||||
10'b0011_1100_00,
|
||||
10'b0011_1100_00,
|
||||
10'b0011_1100_00,
|
||||
10'b0010_0100_00,
|
||||
10'b0010_0100_00,
|
||||
10'b0010_0100_00,
|
||||
10'b0010_0100_00,
|
||||
10'b0010_0100_00,
|
||||
10'b0010_0100_00,
|
||||
10'b0010_0100_00,
|
||||
10'b0010_0100_00,
|
||||
10'b0010_0100_00,
|
||||
10'b0010_0100_00,
|
||||
10'b0010_0100_00,
|
||||
10'b0010_0100_00,
|
||||
10'b0010_0100_00,
|
||||
10'b0010_0100_00,
|
||||
10'b0010_0100_00,
|
||||
10'b0010_0100_00,
|
||||
10'b0010_0100_00
|
||||
};
|
||||
|
||||
lookup_high = {
|
||||
// CP_RES_LFHF
|
||||
10'b0011_0111_00,
|
||||
10'b0011_0111_00,
|
||||
10'b0101_1111_00,
|
||||
10'b0111_1111_00,
|
||||
10'b0111_1011_00,
|
||||
10'b1101_0111_00,
|
||||
10'b1110_1011_00,
|
||||
10'b1110_1101_00,
|
||||
10'b1111_1101_00,
|
||||
10'b1111_0111_00,
|
||||
10'b1111_1011_00,
|
||||
10'b1111_1101_00,
|
||||
10'b1111_0011_00,
|
||||
10'b1110_0101_00,
|
||||
10'b1111_0101_00,
|
||||
10'b1111_0101_00,
|
||||
10'b1111_0101_00,
|
||||
10'b1111_0101_00,
|
||||
10'b0111_0110_00,
|
||||
10'b0111_0110_00,
|
||||
10'b0111_0110_00,
|
||||
10'b0111_0110_00,
|
||||
10'b0101_1100_00,
|
||||
10'b0101_1100_00,
|
||||
10'b0101_1100_00,
|
||||
10'b1100_0001_00,
|
||||
10'b1100_0001_00,
|
||||
10'b1100_0001_00,
|
||||
10'b1100_0001_00,
|
||||
10'b1100_0001_00,
|
||||
10'b1100_0001_00,
|
||||
10'b1100_0001_00,
|
||||
10'b1100_0001_00,
|
||||
10'b0100_0010_00,
|
||||
10'b0100_0010_00,
|
||||
10'b0100_0010_00,
|
||||
10'b0010_1000_00,
|
||||
10'b0010_1000_00,
|
||||
10'b0010_1000_00,
|
||||
10'b0011_0100_00,
|
||||
10'b0010_1000_00,
|
||||
10'b0010_1000_00,
|
||||
10'b0010_1000_00,
|
||||
10'b0010_1000_00,
|
||||
10'b0010_1000_00,
|
||||
10'b0010_1000_00,
|
||||
10'b0010_1000_00,
|
||||
10'b0010_1000_00,
|
||||
10'b0010_1000_00,
|
||||
10'b0010_1000_00,
|
||||
10'b0010_1000_00,
|
||||
10'b0010_1000_00,
|
||||
10'b0010_1000_00,
|
||||
10'b0100_1100_00,
|
||||
10'b0100_1100_00,
|
||||
10'b0100_1100_00,
|
||||
10'b0100_1100_00,
|
||||
10'b0100_1100_00,
|
||||
10'b0100_1100_00,
|
||||
10'b0100_1100_00,
|
||||
10'b0010_0100_00,
|
||||
10'b0010_0100_00,
|
||||
10'b0010_0100_00,
|
||||
10'b0010_0100_00
|
||||
};
|
||||
|
||||
// Set lookup_entry with the explicit bits from lookup with a part select
|
||||
if(BANDWIDTH == "LOW") begin
|
||||
// Low Bandwidth
|
||||
mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10];
|
||||
end else begin
|
||||
// High or optimized bandwidth
|
||||
mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10];
|
||||
end
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("filter_lookup: %b", mmcm_pll_filter_lookup);
|
||||
`endif
|
||||
end
|
||||
endfunction
|
||||
|
||||
// This function takes in the divide, phase, and duty cycle
|
||||
// setting to calculate the upper and lower counter registers.
|
||||
function [37:0] mmcm_pll_count_calc
|
||||
(
|
||||
input [7:0] divide, // Max divide is 128
|
||||
input signed [31:0] phase,
|
||||
input [31:0] duty_cycle // Multiplied by 100,000
|
||||
);
|
||||
|
||||
reg [13:0] div_calc;
|
||||
reg [16:0] phase_calc;
|
||||
|
||||
begin
|
||||
`ifdef DEBUG
|
||||
$display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
|
||||
divide, phase, duty_cycle);
|
||||
`endif
|
||||
|
||||
// w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
|
||||
div_calc = mmcm_pll_divider(divide, duty_cycle);
|
||||
// mx[10:9], pm[8:6], dt[5:0]
|
||||
phase_calc = mmcm_pll_phase(divide, phase);
|
||||
|
||||
// Return value is the upper and lower address of counter
|
||||
// Upper address is:
|
||||
// RESERVED [31:26]
|
||||
// MX [25:24]
|
||||
// EDGE [23]
|
||||
// NOCOUNT [22]
|
||||
// DELAY_TIME [21:16]
|
||||
// Lower Address is:
|
||||
// PHASE_MUX [15:13]
|
||||
// RESERVED [12]
|
||||
// HIGH_TIME [11:6]
|
||||
// LOW_TIME [5:0]
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
|
||||
divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0],
|
||||
div_calc[13], div_calc[12],
|
||||
phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]);
|
||||
`endif
|
||||
|
||||
mmcm_pll_count_calc =
|
||||
{
|
||||
// Upper Address
|
||||
6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0],
|
||||
// Lower Address
|
||||
phase_calc[8:6], 1'b0, div_calc[11:0]
|
||||
};
|
||||
end
|
||||
endfunction
|
||||
+671
@@ -0,0 +1,671 @@
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Company: Xilinx
|
||||
// Engineer: Jim Tatsukawa
|
||||
// Date: 7/30/2014
|
||||
// Design Name: MMCME2 DRP
|
||||
// Module Name: mmcme2_drp_func.h
|
||||
// Version: 1.04
|
||||
// Target Devices: UltraScale Architecture || MMCM
|
||||
// Tool versions: 2014.3
|
||||
// Description: This header provides the functions necessary to
|
||||
// calculate the DRP register values for the V6 MMCM.
|
||||
//
|
||||
// Revision Notes: 3/22 - Updating lookup_low/lookup_high (CR)
|
||||
// 4/13 - Fractional divide function in mmcm_frac_count_calc function. CRS610807
|
||||
//
|
||||
// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
|
||||
// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
|
||||
// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
|
||||
// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
|
||||
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
|
||||
// APPLICATION OR STANDARD, XILINX IS MAKING NO
|
||||
// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
|
||||
// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
|
||||
// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
|
||||
// REQUIRE FOR YOUR IMPLEMENTATION. XILINX
|
||||
// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
|
||||
// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
|
||||
// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
|
||||
// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
|
||||
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
|
||||
// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
// PURPOSE.
|
||||
//
|
||||
// (c) Copyright 2009-2010 Xilinx, Inc.
|
||||
// All rights reserved.
|
||||
//
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// These are user functions that should not be modified. Changes to the defines
|
||||
// or code within the functions may alter the accuracy of the calculations.
|
||||
|
||||
// Define debug to provide extra messages durring elaboration
|
||||
//`define DEBUG 1
|
||||
|
||||
// FRAC_PRECISION describes the width of the fractional portion of the fixed
|
||||
// point numbers. These should not be modified, they are for development
|
||||
// only
|
||||
`define FRAC_PRECISION 10
|
||||
// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
|
||||
// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs
|
||||
// greater than 32
|
||||
`define FIXED_WIDTH 32
|
||||
|
||||
// This function takes a fixed point number and rounds it to the nearest
|
||||
// fractional precision bit.
|
||||
function [`FIXED_WIDTH:1] round_frac
|
||||
(
|
||||
// Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
|
||||
input [`FIXED_WIDTH:1] decimal,
|
||||
|
||||
// This describes the precision of the fraction, for example a value
|
||||
// of 1 would modify the fractional so that instead of being a .16
|
||||
// fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
|
||||
input [`FIXED_WIDTH:1] precision
|
||||
);
|
||||
|
||||
begin
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("round_frac - decimal: %h, precision: %h", decimal, precision);
|
||||
`endif
|
||||
// If the fractional precision bit is high then round up
|
||||
if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
|
||||
round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
|
||||
end else begin
|
||||
round_frac = decimal;
|
||||
end
|
||||
`ifdef DEBUG
|
||||
$display("round_frac: %h", round_frac);
|
||||
`endif
|
||||
end
|
||||
endfunction
|
||||
|
||||
// This function calculates high_time, low_time, w_edge, and no_count
|
||||
// of a non-fractional counter based on the divide and duty cycle
|
||||
//
|
||||
// NOTE: high_time and low_time are returned as integers between 0 and 63
|
||||
// inclusive. 64 should equal 6'b000000 (in other words it is okay to
|
||||
// ignore the overflow)
|
||||
function [13:0] mmcm_pll_divider
|
||||
(
|
||||
input [7:0] divide, // Max divide is 128
|
||||
input [31:0] duty_cycle // Duty cycle is multiplied by 100,000
|
||||
);
|
||||
|
||||
reg [`FIXED_WIDTH:1] duty_cycle_fix;
|
||||
|
||||
// High/Low time is initially calculated with a wider integer to prevent a
|
||||
// calculation error when it overflows to 64.
|
||||
reg [6:0] high_time;
|
||||
reg [6:0] low_time;
|
||||
reg w_edge;
|
||||
reg no_count;
|
||||
|
||||
reg [`FIXED_WIDTH:1] temp;
|
||||
|
||||
begin
|
||||
// Duty Cycle must be between 0 and 1,000
|
||||
if(duty_cycle <=0 || duty_cycle >= 100000) begin
|
||||
`ifndef SYNTHESIS
|
||||
$display("ERROR: duty_cycle: %d is invalid", duty_cycle);
|
||||
`endif
|
||||
$finish;
|
||||
end
|
||||
|
||||
// Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
|
||||
duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("duty_cycle_fix: %h", duty_cycle_fix);
|
||||
`endif
|
||||
|
||||
// If the divide is 1 nothing needs to be set except the no_count bit.
|
||||
// Other values are dummies
|
||||
if(divide == 7'h01) begin
|
||||
high_time = 7'h01;
|
||||
w_edge = 1'b0;
|
||||
low_time = 7'h01;
|
||||
no_count = 1'b1;
|
||||
end else begin
|
||||
temp = round_frac(duty_cycle_fix*divide, 1);
|
||||
|
||||
// comes from above round_frac
|
||||
high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1];
|
||||
// If the duty cycle * divide rounded is .5 or greater then this bit
|
||||
// is set.
|
||||
w_edge = temp[`FRAC_PRECISION]; // comes from round_frac
|
||||
|
||||
// If the high time comes out to 0, it needs to be set to at least 1
|
||||
// and w_edge set to 0
|
||||
if(high_time == 7'h00) begin
|
||||
high_time = 7'h01;
|
||||
w_edge = 1'b0;
|
||||
end
|
||||
|
||||
if(high_time == divide) begin
|
||||
high_time = divide - 1;
|
||||
w_edge = 1'b1;
|
||||
end
|
||||
|
||||
// Calculate low_time based on the divide setting and set no_count to
|
||||
// 0 as it is only used when divide is 1.
|
||||
low_time = divide - high_time;
|
||||
no_count = 1'b0;
|
||||
end
|
||||
|
||||
// Set the return value.
|
||||
mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
|
||||
end
|
||||
endfunction
|
||||
|
||||
// This function calculates mx, delay_time, and phase_mux
|
||||
// of a non-fractional counter based on the divide and phase
|
||||
//
|
||||
// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
|
||||
// is used.
|
||||
function [10:0] mmcm_pll_phase
|
||||
(
|
||||
// divide must be an integer (use fractional if not)
|
||||
// assumed that divide already checked to be valid
|
||||
input [7:0] divide, // Max divide is 128
|
||||
|
||||
// Phase is given in degrees (-360,000 to 360,000)
|
||||
input signed [31:0] phase
|
||||
);
|
||||
|
||||
reg [`FIXED_WIDTH:1] phase_in_cycles;
|
||||
reg [`FIXED_WIDTH:1] phase_fixed;
|
||||
reg [1:0] mx;
|
||||
reg [5:0] delay_time;
|
||||
reg [2:0] phase_mux;
|
||||
|
||||
reg [`FIXED_WIDTH:1] temp;
|
||||
|
||||
begin
|
||||
`ifdef DEBUG
|
||||
$display("mmcm_pll_phase-divide:%d,phase:%d",
|
||||
divide, phase);
|
||||
`endif
|
||||
|
||||
if ((phase < -360000) || (phase > 360000)) begin
|
||||
`ifndef SYNTHESIS
|
||||
$display("ERROR: phase of $phase is not between -360000 and 360000");
|
||||
`endif
|
||||
$finish;
|
||||
end
|
||||
|
||||
// If phase is less than 0, convert it to a positive phase shift
|
||||
// Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
|
||||
if(phase < 0) begin
|
||||
phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
|
||||
end else begin
|
||||
phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
|
||||
end
|
||||
|
||||
// Put phase in terms of decimal number of vco clock cycles
|
||||
phase_in_cycles = ( phase_fixed * divide ) / 360;
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("phase_in_cycles: %h", phase_in_cycles);
|
||||
`endif
|
||||
|
||||
|
||||
temp = round_frac(phase_in_cycles, 3);
|
||||
|
||||
// set mx to 2'b00 that the phase mux from the VCO is enabled
|
||||
mx = 2'b00;
|
||||
phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
|
||||
delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("temp: %h", temp);
|
||||
`endif
|
||||
|
||||
// Setup the return value
|
||||
mmcm_pll_phase={mx, phase_mux, delay_time};
|
||||
end
|
||||
endfunction
|
||||
|
||||
// This function takes the divide value and outputs the necessary lock values
|
||||
function [39:0] mmcm_pll_lock_lookup
|
||||
(
|
||||
input [6:0] divide // Max divide is 64
|
||||
);
|
||||
|
||||
reg [2559:0] lookup;
|
||||
|
||||
begin
|
||||
lookup = {
|
||||
// This table is composed of:
|
||||
// LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
|
||||
40'b00110_00110_1111101000_1111101001_0000000001,
|
||||
40'b00110_00110_1111101000_1111101001_0000000001,
|
||||
40'b01000_01000_1111101000_1111101001_0000000001,
|
||||
40'b01011_01011_1111101000_1111101001_0000000001,
|
||||
40'b01110_01110_1111101000_1111101001_0000000001,
|
||||
40'b10001_10001_1111101000_1111101001_0000000001,
|
||||
40'b10011_10011_1111101000_1111101001_0000000001,
|
||||
40'b10110_10110_1111101000_1111101001_0000000001,
|
||||
40'b11001_11001_1111101000_1111101001_0000000001,
|
||||
40'b11100_11100_1111101000_1111101001_0000000001,
|
||||
40'b11111_11111_1110000100_1111101001_0000000001,
|
||||
40'b11111_11111_1100111001_1111101001_0000000001,
|
||||
40'b11111_11111_1011101110_1111101001_0000000001,
|
||||
40'b11111_11111_1010111100_1111101001_0000000001,
|
||||
40'b11111_11111_1010001010_1111101001_0000000001,
|
||||
40'b11111_11111_1001110001_1111101001_0000000001,
|
||||
40'b11111_11111_1000111111_1111101001_0000000001,
|
||||
40'b11111_11111_1000100110_1111101001_0000000001,
|
||||
40'b11111_11111_1000001101_1111101001_0000000001,
|
||||
40'b11111_11111_0111110100_1111101001_0000000001,
|
||||
40'b11111_11111_0111011011_1111101001_0000000001,
|
||||
40'b11111_11111_0111000010_1111101001_0000000001,
|
||||
40'b11111_11111_0110101001_1111101001_0000000001,
|
||||
40'b11111_11111_0110010000_1111101001_0000000001,
|
||||
40'b11111_11111_0110010000_1111101001_0000000001,
|
||||
40'b11111_11111_0101110111_1111101001_0000000001,
|
||||
40'b11111_11111_0101011110_1111101001_0000000001,
|
||||
40'b11111_11111_0101011110_1111101001_0000000001,
|
||||
40'b11111_11111_0101000101_1111101001_0000000001,
|
||||
40'b11111_11111_0101000101_1111101001_0000000001,
|
||||
40'b11111_11111_0100101100_1111101001_0000000001,
|
||||
40'b11111_11111_0100101100_1111101001_0000000001,
|
||||
40'b11111_11111_0100101100_1111101001_0000000001,
|
||||
40'b11111_11111_0100010011_1111101001_0000000001,
|
||||
40'b11111_11111_0100010011_1111101001_0000000001,
|
||||
40'b11111_11111_0100010011_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001
|
||||
};
|
||||
|
||||
// Set lookup_entry with the explicit bits from lookup with a part select
|
||||
mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40];
|
||||
`ifdef DEBUG
|
||||
$display("lock_lookup: %b", mmcm_pll_lock_lookup);
|
||||
`endif
|
||||
end
|
||||
endfunction
|
||||
|
||||
// This function takes the divide value and the bandwidth setting of the MMCM
|
||||
// and outputs the digital filter settings necessary.
|
||||
function [9:0] mmcm_pll_filter_lookup
|
||||
(
|
||||
input [6:0] divide, // Max divide is 64
|
||||
input [8*9:0] BANDWIDTH
|
||||
);
|
||||
|
||||
reg [639:0] lookup_low;
|
||||
reg [639:0] lookup_high;
|
||||
|
||||
reg [9:0] lookup_entry;
|
||||
|
||||
begin
|
||||
lookup_low = {
|
||||
// CP_RES_LFHF
|
||||
10'b0010_1111_11,
|
||||
10'b0010_1111_11,
|
||||
10'b0010_1111_11,
|
||||
10'b0010_1111_11,
|
||||
10'b0010_1111_11,
|
||||
10'b0010_1111_11,
|
||||
10'b0010_0111_11,
|
||||
10'b0010_0111_11,
|
||||
10'b0010_0111_11,
|
||||
10'b0010_1101_11,
|
||||
10'b0010_1101_11,
|
||||
10'b0010_1101_11,
|
||||
10'b0010_0011_11,
|
||||
10'b0010_0101_11,
|
||||
10'b0010_0101_11,
|
||||
10'b0010_0101_11,
|
||||
10'b0010_1001_11,
|
||||
10'b0010_1001_11,
|
||||
10'b0010_1110_11,
|
||||
10'b0010_1110_11,
|
||||
10'b0010_1110_11,
|
||||
10'b0010_1110_11,
|
||||
10'b0010_1110_11,
|
||||
10'b0010_1110_11,
|
||||
10'b0010_0001_11,
|
||||
10'b0010_0001_11,
|
||||
10'b0010_0001_11,
|
||||
10'b0010_0001_11,
|
||||
10'b0010_0001_11,
|
||||
10'b0010_0110_11,
|
||||
10'b0010_0110_11,
|
||||
10'b0010_0110_11,
|
||||
10'b0010_0110_11,
|
||||
10'b0010_0110_11,
|
||||
10'b0010_0110_11,
|
||||
10'b0010_0110_11,
|
||||
10'b0010_0110_11,
|
||||
10'b0010_0110_11,
|
||||
10'b0010_0110_11,
|
||||
10'b0010_1010_11,
|
||||
10'b0010_1010_11,
|
||||
10'b0010_1010_11,
|
||||
10'b0010_1010_11,
|
||||
10'b0010_1010_11,
|
||||
10'b0010_1010_11,
|
||||
10'b0010_1010_11,
|
||||
10'b0010_1010_11,
|
||||
10'b0010_1100_11,
|
||||
10'b0010_1100_11,
|
||||
10'b0010_1100_11,
|
||||
10'b0010_1100_11,
|
||||
10'b0010_1100_11,
|
||||
10'b0010_1100_11,
|
||||
10'b0010_1100_11,
|
||||
10'b0010_1100_11,
|
||||
10'b0010_1100_11,
|
||||
10'b0010_1100_11,
|
||||
10'b0010_1100_11,
|
||||
10'b0010_1100_11,
|
||||
10'b0010_1100_11,
|
||||
10'b0010_1100_11,
|
||||
10'b0010_1100_11,
|
||||
10'b0010_1100_11,
|
||||
10'b0010_1100_11
|
||||
};
|
||||
|
||||
lookup_high = {
|
||||
// CP_RES_LFHF
|
||||
10'b0010_1111_11,
|
||||
10'b0010_1111_11,
|
||||
10'b0010_1011_11,
|
||||
10'b0011_1111_11,
|
||||
10'b0100_1111_11,
|
||||
10'b0100_1111_11,
|
||||
10'b0101_1111_11,
|
||||
10'b0110_1111_11,
|
||||
10'b0111_1111_11,
|
||||
10'b0111_1111_11,
|
||||
10'b1100_1111_11,
|
||||
10'b1101_1111_11,
|
||||
10'b1110_1111_11,
|
||||
10'b1111_1111_11,
|
||||
10'b1111_1111_11,
|
||||
10'b1110_0111_11,
|
||||
10'b1110_1011_11,
|
||||
10'b1111_0111_11,
|
||||
10'b1111_1011_11,
|
||||
10'b1111_1011_11,
|
||||
10'b1110_1101_11,
|
||||
10'b1111_1101_11,
|
||||
10'b1111_1101_11,
|
||||
10'b1111_0011_11,
|
||||
10'b1111_0011_11,
|
||||
10'b1111_0011_11,
|
||||
10'b1110_0101_11,
|
||||
10'b1110_0101_11,
|
||||
10'b1110_0101_11,
|
||||
10'b1111_0101_11,
|
||||
10'b1111_0101_11,
|
||||
10'b1111_0101_11,
|
||||
10'b1111_1001_11,
|
||||
10'b1111_1001_11,
|
||||
10'b1111_1001_11,
|
||||
10'b1111_1001_11,
|
||||
10'b1111_1001_11,
|
||||
10'b1110_1110_11,
|
||||
10'b1110_1110_11,
|
||||
10'b1110_1110_11,
|
||||
10'b1110_1110_11,
|
||||
10'b1111_1110_11,
|
||||
10'b1111_1110_11,
|
||||
10'b1111_1110_11,
|
||||
10'b1111_1110_11,
|
||||
10'b1111_1110_11,
|
||||
10'b1111_1110_11,
|
||||
10'b1111_1110_11,
|
||||
10'b1110_0001_11,
|
||||
10'b1110_0001_11,
|
||||
10'b1110_0001_11,
|
||||
10'b1110_0001_11,
|
||||
10'b1110_0001_11,
|
||||
10'b1100_0110_11,
|
||||
10'b1100_0110_11,
|
||||
10'b1100_0110_11,
|
||||
10'b1100_0110_11,
|
||||
10'b1100_0110_11,
|
||||
10'b1100_0110_11,
|
||||
10'b1100_0110_11,
|
||||
10'b1100_1010_11,
|
||||
10'b1100_1010_11,
|
||||
10'b1100_1010_11,
|
||||
10'b1100_1010_11
|
||||
};
|
||||
|
||||
// Set lookup_entry with the explicit bits from lookup with a part select
|
||||
if(BANDWIDTH == "LOW") begin
|
||||
// Low Bandwidth
|
||||
mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10];
|
||||
end else begin
|
||||
// High or optimized bandwidth
|
||||
mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10];
|
||||
end
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("filter_lookup: %b", mmcm_pll_filter_lookup);
|
||||
`endif
|
||||
end
|
||||
endfunction
|
||||
|
||||
// This function takes in the divide, phase, and duty cycle
|
||||
// setting to calculate the upper and lower counter registers.
|
||||
function [37:0] mmcm_pll_count_calc
|
||||
(
|
||||
input [7:0] divide, // Max divide is 128
|
||||
input signed [31:0] phase,
|
||||
input [31:0] duty_cycle // Multiplied by 100,000
|
||||
);
|
||||
|
||||
reg [13:0] div_calc;
|
||||
reg [16:0] phase_calc;
|
||||
|
||||
begin
|
||||
`ifdef DEBUG
|
||||
$display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
|
||||
divide, phase, duty_cycle);
|
||||
`endif
|
||||
|
||||
// w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
|
||||
div_calc = mmcm_pll_divider(divide, duty_cycle);
|
||||
// mx[10:9], pm[8:6], dt[5:0]
|
||||
phase_calc = mmcm_pll_phase(divide, phase);
|
||||
|
||||
// Return value is the upper and lower address of counter
|
||||
// Upper address is:
|
||||
// RESERVED [31:26]
|
||||
// MX [25:24]
|
||||
// EDGE [23]
|
||||
// NOCOUNT [22]
|
||||
// DELAY_TIME [21:16]
|
||||
// Lower Address is:
|
||||
// PHASE_MUX [15:13]
|
||||
// RESERVED [12]
|
||||
// HIGH_TIME [11:6]
|
||||
// LOW_TIME [5:0]
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
|
||||
divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0],
|
||||
div_calc[13], div_calc[12],
|
||||
phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]);
|
||||
`endif
|
||||
|
||||
mmcm_pll_count_calc =
|
||||
{
|
||||
// Upper Address
|
||||
6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0],
|
||||
// Lower Address
|
||||
phase_calc[8:6], 1'b0, div_calc[11:0]
|
||||
};
|
||||
end
|
||||
endfunction
|
||||
|
||||
|
||||
// This function takes in the divide, phase, and duty cycle
|
||||
// setting to calculate the upper and lower counter registers.
|
||||
// for fractional multiply/divide functions.
|
||||
//
|
||||
//
|
||||
function [37:0] mmcm_frac_count_calc
|
||||
(
|
||||
input [7:0] divide, // Max divide is 128
|
||||
input signed [31:0] phase,
|
||||
input [31:0] duty_cycle, // Multiplied by 1,000
|
||||
input [9:0] frac // Multiplied by 1000
|
||||
);
|
||||
|
||||
//Required for fractional divide calculations
|
||||
reg [7:0] lt_frac;
|
||||
reg [7:0] ht_frac;
|
||||
|
||||
reg /*[7:0]*/ wf_fall_frac;
|
||||
reg /*[7:0]*/ wf_rise_frac;
|
||||
|
||||
reg [31:0] a;
|
||||
reg [7:0] pm_rise_frac_filtered ;
|
||||
reg [7:0] pm_fall_frac_filtered ;
|
||||
reg [7:0] clkout0_divide_int;
|
||||
reg [2:0] clkout0_divide_frac;
|
||||
reg [7:0] even_part_high;
|
||||
reg [7:0] even_part_low;
|
||||
|
||||
reg [7:0] odd;
|
||||
reg [7:0] odd_and_frac;
|
||||
|
||||
reg [7:0] pm_fall;
|
||||
reg [7:0] pm_rise;
|
||||
reg [7:0] dt;
|
||||
reg [7:0] dt_int;
|
||||
reg [63:0] dt_calc;
|
||||
|
||||
reg [7:0] pm_rise_frac;
|
||||
reg [7:0] pm_fall_frac;
|
||||
|
||||
reg [31:0] a_per_in_octets;
|
||||
reg [31:0] a_phase_in_cycles;
|
||||
|
||||
parameter precision = 0.125;
|
||||
|
||||
reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11
|
||||
reg [31: 0] phase_pos;
|
||||
reg [31: 0] phase_vco;
|
||||
reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11
|
||||
reg [13:0] div_calc;
|
||||
reg [16:0] phase_calc;
|
||||
|
||||
begin
|
||||
`ifdef DEBUG
|
||||
$display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d",
|
||||
divide, phase, duty_cycle);
|
||||
`endif
|
||||
|
||||
//convert phase to fixed
|
||||
if ((phase < -360000) || (phase > 360000)) begin
|
||||
`ifndef SYNTHESIS
|
||||
$display("ERROR: phase of $phase is not between -360000 and 360000");
|
||||
`endif
|
||||
$finish;
|
||||
end
|
||||
|
||||
|
||||
// Return value is
|
||||
// Transfer data
|
||||
// RESERVED [37:36]
|
||||
// FRAC_TIME [35:33]
|
||||
// FRAC_WF_FALL [32]
|
||||
// Upper address is:
|
||||
// RESERVED [31:26]
|
||||
// MX [25:24]
|
||||
// EDGE [23]
|
||||
// NOCOUNT [22]
|
||||
// DELAY_TIME [21:16]
|
||||
// Lower Address is:
|
||||
// PHASE_MUX [15:13]
|
||||
// RESERVED [12]
|
||||
// HIGH_TIME [11:6]
|
||||
// LOW_TIME [5:0]
|
||||
|
||||
|
||||
|
||||
clkout0_divide_frac = frac / 125;
|
||||
clkout0_divide_int = divide;
|
||||
|
||||
even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2);
|
||||
even_part_low = even_part_high;
|
||||
|
||||
odd = clkout0_divide_int - even_part_high - even_part_low;
|
||||
odd_and_frac = (8*odd) + clkout0_divide_frac;
|
||||
|
||||
lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1)
|
||||
ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1)
|
||||
|
||||
pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2
|
||||
pm_rise = 0; //0
|
||||
|
||||
wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || ((clkout0_divide_frac == 1) && (clkout0_divide_int == 2));//CRS610807
|
||||
wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0)
|
||||
|
||||
|
||||
|
||||
//Calculate phase in fractional cycles
|
||||
a_per_in_octets = (8 * divide) + (frac / 125) ;
|
||||
a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors
|
||||
pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000};
|
||||
|
||||
dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8)
|
||||
dt = dt_calc[7:0];
|
||||
|
||||
pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a;
|
||||
|
||||
dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt)
|
||||
pm_fall_frac = pm_fall + pm_rise_frac;
|
||||
pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000};
|
||||
|
||||
div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6]
|
||||
phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]}
|
||||
|
||||
mmcm_frac_count_calc[37:0] =
|
||||
{ 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac,
|
||||
1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0],
|
||||
pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0]
|
||||
} ;
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac);
|
||||
`endif
|
||||
|
||||
end
|
||||
endfunction
|
||||
|
||||
+530
@@ -0,0 +1,530 @@
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Company: Xilinx
|
||||
// Engineer: Jim Tatsukawa
|
||||
// Date: 6/15/2015
|
||||
// Design Name: PLLE3 DRP
|
||||
// Module Name: plle3_drp_func.h
|
||||
// Version: 1.10
|
||||
// Target Devices: UltraScale Architecture
|
||||
// Tool versions: 2015.1
|
||||
// Description: This header provides the functions necessary to
|
||||
// calculate the DRP register values for the V6 PLL.
|
||||
//
|
||||
// Revision Notes: 8/11 - PLLE3 updated for PLLE3 file 4564419
|
||||
// Revision Notes: 6/15 - pll_filter_lookup fixed for max M of 19
|
||||
// PM_Rise bits have been removed for PLLE3
|
||||
//
|
||||
// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
|
||||
// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
|
||||
// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
|
||||
// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
|
||||
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
|
||||
// APPLICATION OR STANDARD, XILINX IS MAKING NO
|
||||
// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
|
||||
// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
|
||||
// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
|
||||
// REQUIRE FOR YOUR IMPLEMENTATION. XILINX
|
||||
// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
|
||||
// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
|
||||
// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
|
||||
// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
|
||||
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
|
||||
// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
// PURPOSE.
|
||||
//
|
||||
// (c) Copyright 2009-2010 Xilinx, Inc.
|
||||
// All rights reserved.
|
||||
//
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// These are user functions that should not be modified. Changes to the defines
|
||||
// or code within the functions may alter the accuracy of the calculations.
|
||||
|
||||
// Define debug to provide extra messages durring elaboration
|
||||
//`define DEBUG 1
|
||||
|
||||
// FRAC_PRECISION describes the width of the fractional portion of the fixed
|
||||
// point numbers. These should not be modified, they are for development
|
||||
// only
|
||||
`define FRAC_PRECISION 10
|
||||
// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
|
||||
// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs
|
||||
// greater than 32
|
||||
`define FIXED_WIDTH 32
|
||||
|
||||
// This function takes a fixed point number and rounds it to the nearest
|
||||
// fractional precision bit.
|
||||
function [`FIXED_WIDTH:1] round_frac
|
||||
(
|
||||
// Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
|
||||
input [`FIXED_WIDTH:1] decimal,
|
||||
|
||||
// This describes the precision of the fraction, for example a value
|
||||
// of 1 would modify the fractional so that instead of being a .16
|
||||
// fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
|
||||
input [`FIXED_WIDTH:1] precision
|
||||
);
|
||||
|
||||
begin
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("round_frac - decimal: %h, precision: %h", decimal, precision);
|
||||
`endif
|
||||
// If the fractional precision bit is high then round up
|
||||
if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
|
||||
round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
|
||||
end else begin
|
||||
round_frac = decimal;
|
||||
end
|
||||
`ifdef DEBUG
|
||||
$display("round_frac: %h", round_frac);
|
||||
`endif
|
||||
end
|
||||
endfunction
|
||||
|
||||
// This function calculates high_time, low_time, w_edge, and no_count
|
||||
// of a non-fractional counter based on the divide and duty cycle
|
||||
//
|
||||
// NOTE: high_time and low_time are returned as integers between 0 and 63
|
||||
// inclusive. 64 should equal 6'b000000 (in other words it is okay to
|
||||
// ignore the overflow)
|
||||
function [13:0] mmcm_pll_divider
|
||||
(
|
||||
input [7:0] divide, // Max divide is 128
|
||||
input [31:0] duty_cycle // Duty cycle is multiplied by 100,000
|
||||
);
|
||||
|
||||
reg [`FIXED_WIDTH:1] duty_cycle_fix;
|
||||
|
||||
// High/Low time is initially calculated with a wider integer to prevent a
|
||||
// calculation error when it overflows to 64.
|
||||
reg [6:0] high_time;
|
||||
reg [6:0] low_time;
|
||||
reg w_edge;
|
||||
reg no_count;
|
||||
|
||||
reg [`FIXED_WIDTH:1] temp;
|
||||
|
||||
begin
|
||||
// Duty Cycle must be between 0 and 1,000
|
||||
if(duty_cycle <=0 || duty_cycle >= 100000) begin
|
||||
`ifndef SYNTHESIS
|
||||
$display("ERROR: duty_cycle: %d is invalid", duty_cycle);
|
||||
`endif
|
||||
$finish;
|
||||
end
|
||||
|
||||
// Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
|
||||
duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("duty_cycle_fix: %h", duty_cycle_fix);
|
||||
`endif
|
||||
|
||||
// If the divide is 1 nothing needs to be set except the no_count bit.
|
||||
// Other values are dummies
|
||||
if(divide == 7'h01) begin
|
||||
high_time = 7'h01;
|
||||
w_edge = 1'b0;
|
||||
low_time = 7'h01;
|
||||
no_count = 1'b1;
|
||||
end else begin
|
||||
temp = round_frac(duty_cycle_fix*divide, 1);
|
||||
|
||||
// comes from above round_frac
|
||||
high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1];
|
||||
// If the duty cycle * divide rounded is .5 or greater then this bit
|
||||
// is set.
|
||||
w_edge = temp[`FRAC_PRECISION]; // comes from round_frac
|
||||
|
||||
// If the high time comes out to 0, it needs to be set to at least 1
|
||||
// and w_edge set to 0
|
||||
if(high_time == 7'h00) begin
|
||||
high_time = 7'h01;
|
||||
w_edge = 1'b0;
|
||||
end
|
||||
|
||||
if(high_time == divide) begin
|
||||
high_time = divide - 1;
|
||||
w_edge = 1'b1;
|
||||
end
|
||||
|
||||
// Calculate low_time based on the divide setting and set no_count to
|
||||
// 0 as it is only used when divide is 1.
|
||||
low_time = divide - high_time;
|
||||
no_count = 1'b0;
|
||||
end
|
||||
|
||||
// Set the return value.
|
||||
mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
|
||||
end
|
||||
endfunction
|
||||
|
||||
// This function calculates mx, delay_time, and phase_mux
|
||||
// of a non-fractional counter based on the divide and phase
|
||||
//
|
||||
// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
|
||||
// is used.
|
||||
function [10:0] mmcm_pll_phase
|
||||
(
|
||||
// divide must be an integer (use fractional if not)
|
||||
// assumed that divide already checked to be valid
|
||||
input [7:0] divide, // Max divide is 128
|
||||
|
||||
// Phase is given in degrees (-360,000 to 360,000)
|
||||
input signed [31:0] phase
|
||||
);
|
||||
|
||||
reg [`FIXED_WIDTH:1] phase_in_cycles;
|
||||
reg [`FIXED_WIDTH:1] phase_fixed;
|
||||
reg [1:0] mx;
|
||||
reg [5:0] delay_time;
|
||||
reg [2:0] phase_mux;
|
||||
|
||||
reg [`FIXED_WIDTH:1] temp;
|
||||
|
||||
begin
|
||||
`ifdef DEBUG
|
||||
$display("mmcm_pll_phase-divide:%d,phase:%d",
|
||||
divide, phase);
|
||||
`endif
|
||||
|
||||
if ((phase < -360000) || (phase > 360000)) begin
|
||||
`ifndef SYNTHESIS
|
||||
$display("ERROR: phase of $phase is not between -360000 and 360000");
|
||||
`endif
|
||||
$finish;
|
||||
end
|
||||
|
||||
// If phase is less than 0, convert it to a positive phase shift
|
||||
// Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
|
||||
if(phase < 0) begin
|
||||
phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
|
||||
end else begin
|
||||
phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
|
||||
end
|
||||
|
||||
// Put phase in terms of decimal number of vco clock cycles
|
||||
phase_in_cycles = ( phase_fixed * divide ) / 360;
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("phase_in_cycles: %h", phase_in_cycles);
|
||||
`endif
|
||||
|
||||
|
||||
temp = round_frac(phase_in_cycles, 3);
|
||||
|
||||
// set mx to 2'b00 that the phase mux from the VCO is enabled
|
||||
mx = 2'b00;
|
||||
phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
|
||||
delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("temp: %h", temp);
|
||||
`endif
|
||||
|
||||
// Setup the return value
|
||||
mmcm_pll_phase={mx, phase_mux, delay_time};
|
||||
end
|
||||
endfunction
|
||||
|
||||
// This function takes the divide value and outputs the necessary lock values
|
||||
function [39:0] mmcm_pll_lock_lookup
|
||||
(
|
||||
input [6:0] divide // Max divide is 64
|
||||
);
|
||||
|
||||
reg [759:0] lookup;
|
||||
|
||||
begin
|
||||
lookup = {
|
||||
// This table is composed of:
|
||||
// LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
|
||||
40'b00110_00110_1111101000_1111101001_0000000001, //1
|
||||
40'b00110_00110_1111101000_1111101001_0000000001, //2
|
||||
40'b01000_01000_1111101000_1111101001_0000000001, //3
|
||||
40'b01011_01011_1111101000_1111101001_0000000001, //4
|
||||
40'b01110_01110_1111101000_1111101001_0000000001, //5
|
||||
40'b10001_10001_1111101000_1111101001_0000000001, //6
|
||||
40'b10011_10011_1111101000_1111101001_0000000001, //7
|
||||
40'b10110_10110_1111101000_1111101001_0000000001, //8
|
||||
40'b11001_11001_1111101000_1111101001_0000000001, //9
|
||||
40'b11100_11100_1111101000_1111101001_0000000001, //10
|
||||
40'b11111_11111_1110000100_1111101001_0000000001, //11
|
||||
40'b11111_11111_1100111001_1111101001_0000000001, //12
|
||||
40'b11111_11111_1011101110_1111101001_0000000001, //13
|
||||
40'b11111_11111_1010111100_1111101001_0000000001, //14
|
||||
40'b11111_11111_1010001010_1111101001_0000000001, //15
|
||||
40'b11111_11111_1001110001_1111101001_0000000001, //16
|
||||
40'b11111_11111_1000111111_1111101001_0000000001, //17
|
||||
40'b11111_11111_1000100110_1111101001_0000000001, //18
|
||||
40'b11111_11111_1000001101_1111101001_0000000001 //19
|
||||
|
||||
};
|
||||
|
||||
// Set lookup_entry with the explicit bits from lookup with a part select
|
||||
mmcm_pll_lock_lookup = lookup[ ((19-divide)*40) +: 40];
|
||||
`ifdef DEBUG
|
||||
$display("lock_lookup: %b", mmcm_pll_lock_lookup);
|
||||
`endif
|
||||
end
|
||||
endfunction
|
||||
|
||||
// This function takes the divide value and the bandwidth setting of the PLL
|
||||
// and outputs the digital filter settings necessary. Removing bandwidth setting for PLLE3.
|
||||
function [9:0] mmcm_pll_filter_lookup
|
||||
(
|
||||
input [6:0] divide // Max divide is 19
|
||||
);
|
||||
|
||||
reg [639:0] lookup;
|
||||
reg [9:0] lookup_entry;
|
||||
|
||||
begin
|
||||
|
||||
lookup = {
|
||||
// CP_RES_LFHF
|
||||
10'b0010_1111_01, //1
|
||||
10'b0010_0011_11, //2
|
||||
10'b0011_0011_11, //3
|
||||
10'b0010_0001_11, //4
|
||||
10'b0010_0110_11, //5
|
||||
10'b0010_1010_11, //6
|
||||
10'b0010_1010_11, //7
|
||||
10'b0011_0110_11, //8
|
||||
10'b0010_1100_11, //9
|
||||
10'b0010_1100_11, //10
|
||||
10'b0010_1100_11, //11
|
||||
10'b0010_0010_11, //12
|
||||
10'b0011_1100_11, //13
|
||||
10'b0011_1100_11, //14
|
||||
10'b0011_1100_11, //15
|
||||
10'b0011_1100_11, //16
|
||||
10'b0011_0010_11, //17
|
||||
10'b0011_0010_11, //18
|
||||
10'b0011_0010_11 //19
|
||||
};
|
||||
|
||||
mmcm_pll_filter_lookup = lookup [ ((19-divide)*10) +: 10];
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("filter_lookup: %b", mmcm_pll_filter_lookup);
|
||||
`endif
|
||||
end
|
||||
endfunction
|
||||
|
||||
// This function set the CLKOUTPHY divide settings to match
|
||||
// the desired CLKOUTPHY_MODE setting. To create VCO_X2, then
|
||||
// the CLKOUTPHY will be set to 2'b00 since the VCO is internally
|
||||
// doubled and 2'b00 will represent divide by 1. Similarly "VCO" // will need to divide the doubled clock VCO clock frequency by // 2 therefore 2'b01 will match a divide by 2.And VCO_HALF will // need to divide the doubled VCO by 4, therefore 2'b10
|
||||
function [9:0] mmcm_pll_clkoutphy_calc
|
||||
(
|
||||
input [8*9:0] CLKOUTPHY_MODE
|
||||
);
|
||||
|
||||
if(CLKOUTPHY_MODE == "VCO_X2") begin
|
||||
mmcm_pll_clkoutphy_calc= 2'b00;
|
||||
end else if(CLKOUTPHY_MODE == "VCO") begin
|
||||
mmcm_pll_clkoutphy_calc= 2'b01;
|
||||
end else if(CLKOUTPHY_MODE == "CLKIN") begin
|
||||
mmcm_pll_clkoutphy_calc= 2'b11;
|
||||
end else begin // Assume "VCO_HALF"
|
||||
mmcm_pll_clkoutphy_calc= 2'b10;
|
||||
end
|
||||
|
||||
endfunction
|
||||
|
||||
|
||||
// This function takes in the divide, phase, and duty cycle
|
||||
// setting to calculate the upper and lower counter registers.
|
||||
function [37:0] mmcm_pll_count_calc
|
||||
(
|
||||
input [7:0] divide, // Max divide is 128
|
||||
input signed [31:0] phase,
|
||||
input [31:0] duty_cycle // Multiplied by 100,000
|
||||
);
|
||||
|
||||
reg [13:0] div_calc;
|
||||
reg [16:0] phase_calc;
|
||||
|
||||
begin
|
||||
`ifdef DEBUG
|
||||
$display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
|
||||
divide, phase, duty_cycle);
|
||||
`endif
|
||||
|
||||
// w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
|
||||
div_calc = mmcm_pll_divider(divide, duty_cycle);
|
||||
// mx[10:9], pm[8:6], dt[5:0]
|
||||
phase_calc = mmcm_pll_phase(divide, phase);
|
||||
|
||||
// Return value is the upper and lower address of counter
|
||||
// Upper address is:
|
||||
// RESERVED [31:26]
|
||||
// MX [25:24]
|
||||
// EDGE [23]
|
||||
// NOCOUNT [22]
|
||||
// DELAY_TIME [21:16]
|
||||
// Lower Address is:
|
||||
// PHASE_MUX [15:13]
|
||||
// RESERVED [12]
|
||||
// HIGH_TIME [11:6]
|
||||
// LOW_TIME [5:0]
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
|
||||
divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0],
|
||||
div_calc[13], div_calc[12],
|
||||
phase_calc[16:15], phase_calc[5:0], 3'b000);//Removed PM_Rise bits
|
||||
`endif
|
||||
|
||||
mmcm_pll_count_calc =
|
||||
{
|
||||
// Upper Address
|
||||
6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0],
|
||||
// Lower Address
|
||||
phase_calc[8:6], 1'b0, div_calc[11:0]
|
||||
};
|
||||
end
|
||||
endfunction
|
||||
|
||||
|
||||
// This function takes in the divide, phase, and duty cycle
|
||||
// setting to calculate the upper and lower counter registers.
|
||||
// for fractional multiply/divide functions.
|
||||
//
|
||||
//
|
||||
function [37:0] mmcm_pll_frac_count_calc
|
||||
(
|
||||
input [7:0] divide, // Max divide is 128
|
||||
input signed [31:0] phase,
|
||||
input [31:0] duty_cycle, // Multiplied by 1,000
|
||||
input [9:0] frac // Multiplied by 1000
|
||||
);
|
||||
|
||||
//Required for fractional divide calculations
|
||||
reg [7:0] lt_frac;
|
||||
reg [7:0] ht_frac;
|
||||
|
||||
reg /*[7:0]*/ wf_fall_frac;
|
||||
reg /*[7:0]*/ wf_rise_frac;
|
||||
|
||||
reg [31:0] a;
|
||||
reg [7:0] pm_rise_frac_filtered ;
|
||||
reg [7:0] pm_fall_frac_filtered ;
|
||||
reg [7:0] clkout0_divide_int;
|
||||
reg [2:0] clkout0_divide_frac;
|
||||
reg [7:0] even_part_high;
|
||||
reg [7:0] even_part_low;
|
||||
|
||||
reg [7:0] odd;
|
||||
reg [7:0] odd_and_frac;
|
||||
|
||||
reg [7:0] pm_fall;
|
||||
reg [7:0] pm_rise;
|
||||
reg [7:0] dt;
|
||||
reg [7:0] dt_int;
|
||||
reg [63:0] dt_calc;
|
||||
|
||||
reg [7:0] pm_rise_frac;
|
||||
reg [7:0] pm_fall_frac;
|
||||
|
||||
reg [31:0] a_per_in_octets;
|
||||
reg [31:0] a_phase_in_cycles;
|
||||
|
||||
parameter precision = 0.125;
|
||||
|
||||
reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11
|
||||
reg [31: 0] phase_pos;
|
||||
reg [31: 0] phase_vco;
|
||||
reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11
|
||||
reg [13:0] div_calc;
|
||||
reg [16:0] phase_calc;
|
||||
|
||||
begin
|
||||
`ifdef DEBUG
|
||||
$display("mmcm_pll_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d",
|
||||
divide, phase, duty_cycle);
|
||||
`endif
|
||||
|
||||
//convert phase to fixed
|
||||
if ((phase < -360000) || (phase > 360000)) begin
|
||||
`ifndef SYNTHESIS
|
||||
$display("ERROR: phase of $phase is not between -360000 and 360000");
|
||||
`endif
|
||||
$finish;
|
||||
end
|
||||
|
||||
|
||||
// Return value is
|
||||
// Transfer data
|
||||
// RESERVED [37:36]
|
||||
// FRAC_TIME [35:33]
|
||||
// FRAC_WF_FALL [32]
|
||||
// Upper address is:
|
||||
// RESERVED [31:26]
|
||||
// MX [25:24]
|
||||
// EDGE [23]
|
||||
// NOCOUNT [22]
|
||||
// DELAY_TIME [21:16]
|
||||
// Lower Address is:
|
||||
// PHASE_MUX [15:13]
|
||||
// RESERVED [12]
|
||||
// HIGH_TIME [11:6]
|
||||
// LOW_TIME [5:0]
|
||||
|
||||
|
||||
|
||||
clkout0_divide_frac = frac / 125;
|
||||
clkout0_divide_int = divide;
|
||||
|
||||
even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2);
|
||||
even_part_low = even_part_high;
|
||||
|
||||
odd = clkout0_divide_int - even_part_high - even_part_low;
|
||||
odd_and_frac = (8*odd) + clkout0_divide_frac;
|
||||
|
||||
lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1)
|
||||
ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1)
|
||||
|
||||
pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2
|
||||
pm_rise = 0; //0
|
||||
|
||||
wf_fall_frac = (odd_and_frac >=2) && (odd_and_frac <=9);//IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0)
|
||||
wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0)
|
||||
|
||||
|
||||
|
||||
//Calculate phase in fractional cycles
|
||||
a_per_in_octets = (8 * divide) + (frac / 125) ;
|
||||
a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors
|
||||
pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000};
|
||||
|
||||
dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8)
|
||||
dt = dt_calc[7:0];
|
||||
|
||||
pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a;
|
||||
|
||||
dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt)
|
||||
pm_fall_frac = pm_fall + pm_rise_frac;
|
||||
pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000};
|
||||
|
||||
div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6]
|
||||
phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]}
|
||||
|
||||
mmcm_pll_frac_count_calc[37:0] =
|
||||
{ 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac,
|
||||
1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0],
|
||||
3'b000, 1'b0, ht_frac[5:0], lt_frac[5:0] //Removed PM_Rise bits
|
||||
// pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0]
|
||||
} ;
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, 3'b000, ht_frac, lt_frac);
|
||||
`endif
|
||||
|
||||
end
|
||||
endfunction
|
||||
|
||||
|
||||
+861
@@ -0,0 +1,861 @@
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Company: Xilinx
|
||||
// Engineer: Jim Tatsukawa. Updated by Ralf Krueger
|
||||
// Date: 7/30/2014
|
||||
// Design Name: MMCME4 DRP
|
||||
// Module Name: mmcme4_drp_func.h
|
||||
// Version: 1.31
|
||||
// Target Devices: UltraScale Plus Architecture
|
||||
// Tool versions: 2017.1
|
||||
// Description: This header provides the functions necessary to
|
||||
// calculate the DRP register values for UltraScal+ MMCM.
|
||||
//
|
||||
// Revision Notes: 3/22 - Updating lookup_low/lookup_high (CR)
|
||||
// 4/13 - Fractional divide function in mmcm_frac_count_calc function
|
||||
// 2/28/17 - Updated for Ultrascale Plus
|
||||
//
|
||||
// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
|
||||
// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
|
||||
// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
|
||||
// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
|
||||
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
|
||||
// APPLICATION OR STANDARD, XILINX IS MAKING NO
|
||||
// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
|
||||
// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
|
||||
// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
|
||||
// REQUIRE FOR YOUR IMPLEMENTATION. XILINX
|
||||
// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
|
||||
// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
|
||||
// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
|
||||
// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
|
||||
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
|
||||
// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
// PURPOSE.
|
||||
//
|
||||
// (c) Copyright 2009-2017 Xilinx, Inc.
|
||||
// All rights reserved.
|
||||
//
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// These are user functions that should not be modified. Changes to the defines
|
||||
// or code within the functions may alter the accuracy of the calculations.
|
||||
|
||||
// Define debug to provide extra messages during elaboration
|
||||
//`define DEBUG 1
|
||||
|
||||
// FRAC_PRECISION describes the width of the fractional portion of the fixed
|
||||
// point numbers. These should not be modified, they are for development only
|
||||
`define FRAC_PRECISION 10
|
||||
// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
|
||||
// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs
|
||||
// greater than 32
|
||||
`define FIXED_WIDTH 32
|
||||
|
||||
// This function takes a fixed point number and rounds it to the nearest
|
||||
// fractional precision bit.
|
||||
function [`FIXED_WIDTH:1] round_frac
|
||||
(
|
||||
// Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
|
||||
input [`FIXED_WIDTH:1] decimal,
|
||||
|
||||
// This describes the precision of the fraction, for example a value
|
||||
// of 1 would modify the fractional so that instead of being a .16
|
||||
// fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
|
||||
input [`FIXED_WIDTH:1] precision
|
||||
);
|
||||
|
||||
begin
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("round_frac - decimal: %h, precision: %h", decimal, precision);
|
||||
`endif
|
||||
// If the fractional precision bit is high then round up
|
||||
if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
|
||||
round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
|
||||
end else begin
|
||||
round_frac = decimal;
|
||||
end
|
||||
`ifdef DEBUG
|
||||
$display("round_frac: %h", round_frac);
|
||||
`endif
|
||||
end
|
||||
endfunction
|
||||
|
||||
// This function calculates high_time, low_time, w_edge, and no_count
|
||||
// of a non-fractional counter based on the divide and duty cycle
|
||||
//
|
||||
// NOTE: high_time and low_time are returned as integers between 0 and 63
|
||||
// inclusive. 64 should equal 6'b000000 (in other words it is okay to
|
||||
// ignore the overflow)
|
||||
function [13:0] mmcm_pll_divider
|
||||
(
|
||||
input [7:0] divide, // Max divide is 128
|
||||
input [31:0] duty_cycle // Duty cycle is multiplied by 100,000
|
||||
);
|
||||
|
||||
reg [`FIXED_WIDTH:1] duty_cycle_fix;
|
||||
|
||||
// High/Low time is initially calculated with a wider integer to prevent a
|
||||
// calculation error when it overflows to 64.
|
||||
reg [6:0] high_time;
|
||||
reg [6:0] low_time;
|
||||
reg w_edge;
|
||||
reg no_count;
|
||||
|
||||
reg [`FIXED_WIDTH:1] temp;
|
||||
|
||||
begin
|
||||
// Duty Cycle must be between 0 and 1,000
|
||||
if(duty_cycle <=0 || duty_cycle >= 100000) begin
|
||||
`ifndef SYNTHESIS
|
||||
$display("ERROR: duty_cycle: %d is invalid", duty_cycle);
|
||||
`endif
|
||||
$finish;
|
||||
end
|
||||
|
||||
// Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
|
||||
duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("duty_cycle_fix: %h", duty_cycle_fix);
|
||||
`endif
|
||||
|
||||
// If the divide is 1 nothing needs to be set except the no_count bit.
|
||||
// Other values are dummies
|
||||
if(divide == 7'h01) begin
|
||||
high_time = 7'h01;
|
||||
w_edge = 1'b0;
|
||||
low_time = 7'h01;
|
||||
no_count = 1'b1;
|
||||
end else begin
|
||||
temp = round_frac(duty_cycle_fix*divide, 1);
|
||||
|
||||
// comes from above round_frac
|
||||
high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1];
|
||||
// If the duty cycle * divide rounded is .5 or greater then this bit
|
||||
// is set.
|
||||
w_edge = temp[`FRAC_PRECISION]; // comes from round_frac
|
||||
|
||||
// If the high time comes out to 0, it needs to be set to at least 1
|
||||
// and w_edge set to 0
|
||||
if(high_time == 7'h00) begin
|
||||
high_time = 7'h01;
|
||||
w_edge = 1'b0;
|
||||
end
|
||||
|
||||
if(high_time == divide) begin
|
||||
high_time = divide - 1;
|
||||
w_edge = 1'b1;
|
||||
end
|
||||
|
||||
// Calculate low_time based on the divide setting and set no_count to
|
||||
// 0 as it is only used when divide is 1.
|
||||
low_time = divide - high_time;
|
||||
no_count = 1'b0;
|
||||
end
|
||||
|
||||
// Set the return value.
|
||||
mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
|
||||
end
|
||||
endfunction
|
||||
|
||||
// This function calculates mx, delay_time, and phase_mux
|
||||
// of a non-fractional counter based on the divide and phase
|
||||
//
|
||||
// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
|
||||
// is used.
|
||||
function [10:0] mmcm_pll_phase
|
||||
(
|
||||
// divide must be an integer (use fractional if not)
|
||||
// assumed that divide already checked to be valid
|
||||
input [7:0] divide, // Max divide is 128
|
||||
|
||||
// Phase is given in degrees (-360,000 to 360,000)
|
||||
input signed [31:0] phase
|
||||
);
|
||||
|
||||
reg [`FIXED_WIDTH:1] phase_in_cycles;
|
||||
reg [`FIXED_WIDTH:1] phase_fixed;
|
||||
reg [1:0] mx;
|
||||
reg [5:0] delay_time;
|
||||
reg [2:0] phase_mux;
|
||||
|
||||
reg [`FIXED_WIDTH:1] temp;
|
||||
|
||||
begin
|
||||
`ifdef DEBUG
|
||||
$display("mmcm_phase-divide:%d,phase:%d", divide, phase);
|
||||
`endif
|
||||
|
||||
if ((phase < -360000) || (phase > 360000)) begin
|
||||
`ifndef SYNTHESIS
|
||||
$display("ERROR: phase of $phase is not between -360000 and 360000");
|
||||
`endif
|
||||
$finish;
|
||||
end
|
||||
|
||||
// If phase is less than 0, convert it to a positive phase shift
|
||||
// Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
|
||||
if(phase < 0) begin
|
||||
phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
|
||||
end else begin
|
||||
phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
|
||||
end
|
||||
|
||||
// Put phase in terms of decimal number of vco clock cycles
|
||||
phase_in_cycles = ( phase_fixed * divide ) / 360;
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("phase_in_cycles: %h", phase_in_cycles);
|
||||
`endif
|
||||
|
||||
temp = round_frac(phase_in_cycles, 3);
|
||||
|
||||
// set mx to 2'b00 that the phase mux from the VCO is enabled
|
||||
mx = 2'b00;
|
||||
phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
|
||||
delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("temp: %h", temp);
|
||||
`endif
|
||||
|
||||
// Setup the return value
|
||||
mmcm_pll_phase={mx, phase_mux, delay_time};
|
||||
end
|
||||
endfunction
|
||||
|
||||
// This function takes the divide value and outputs the necessary lock values
|
||||
function [39:0] mmcm_pll_lock_lookup
|
||||
(
|
||||
input [7:0] divide // Max M divide is 128 in UltrascalePlus
|
||||
);
|
||||
|
||||
reg [5119:0] lookup;
|
||||
|
||||
begin
|
||||
lookup = {
|
||||
// This table is composed of:
|
||||
// LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
|
||||
40'b00110_00110_1111101000_1111101001_0000000001, // M=1 (not allowed)
|
||||
40'b00110_00110_1111101000_1111101001_0000000001, // M=2
|
||||
40'b01000_01000_1111101000_1111101001_0000000001, // M=3
|
||||
40'b01011_01011_1111101000_1111101001_0000000001, // M=4
|
||||
40'b01110_01110_1111101000_1111101001_0000000001, // M=5
|
||||
40'b10001_10001_1111101000_1111101001_0000000001, // M=6
|
||||
40'b10011_10011_1111101000_1111101001_0000000001, // M=7
|
||||
40'b10110_10110_1111101000_1111101001_0000000001,
|
||||
40'b11001_11001_1111101000_1111101001_0000000001,
|
||||
40'b11100_11100_1111101000_1111101001_0000000001,
|
||||
40'b11111_11111_1110000100_1111101001_0000000001,
|
||||
40'b11111_11111_1100111001_1111101001_0000000001,
|
||||
40'b11111_11111_1011101110_1111101001_0000000001,
|
||||
40'b11111_11111_1010111100_1111101001_0000000001,
|
||||
40'b11111_11111_1010001010_1111101001_0000000001,
|
||||
40'b11111_11111_1001110001_1111101001_0000000001,
|
||||
40'b11111_11111_1000111111_1111101001_0000000001,
|
||||
40'b11111_11111_1000100110_1111101001_0000000001,
|
||||
40'b11111_11111_1000001101_1111101001_0000000001,
|
||||
40'b11111_11111_0111110100_1111101001_0000000001,
|
||||
40'b11111_11111_0111011011_1111101001_0000000001,
|
||||
40'b11111_11111_0111000010_1111101001_0000000001,
|
||||
40'b11111_11111_0110101001_1111101001_0000000001,
|
||||
40'b11111_11111_0110010000_1111101001_0000000001,
|
||||
40'b11111_11111_0110010000_1111101001_0000000001,
|
||||
40'b11111_11111_0101110111_1111101001_0000000001,
|
||||
40'b11111_11111_0101011110_1111101001_0000000001,
|
||||
40'b11111_11111_0101011110_1111101001_0000000001,
|
||||
40'b11111_11111_0101000101_1111101001_0000000001,
|
||||
40'b11111_11111_0101000101_1111101001_0000000001,
|
||||
40'b11111_11111_0100101100_1111101001_0000000001,
|
||||
40'b11111_11111_0100101100_1111101001_0000000001,
|
||||
40'b11111_11111_0100101100_1111101001_0000000001,
|
||||
40'b11111_11111_0100010011_1111101001_0000000001,
|
||||
40'b11111_11111_0100010011_1111101001_0000000001,
|
||||
40'b11111_11111_0100010011_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001,
|
||||
40'b11111_11111_0011111010_1111101001_0000000001, // M=127
|
||||
40'b11111_11111_0011111010_1111101001_0000000001 // M=128
|
||||
};
|
||||
|
||||
// Set lookup_entry with the explicit bits from lookup with a part select
|
||||
mmcm_pll_lock_lookup = lookup[ ((128-divide)*40) +: 40];
|
||||
`ifdef DEBUG
|
||||
$display("lock_lookup: %b", mmcm_pll_lock_lookup);
|
||||
`endif
|
||||
end
|
||||
endfunction
|
||||
|
||||
// This function takes the divide value and the bandwidth setting of the MMCM
|
||||
// and outputs the digital filter settings necessary.
|
||||
function [9:0] mmcm_pll_filter_lookup
|
||||
(
|
||||
input [7:0] divide, // input [7:0] divide // Max M divide is 128 in UltraScalePlus
|
||||
input [8*9:0] BANDWIDTH
|
||||
);
|
||||
|
||||
reg [1279:0] lookup_low;
|
||||
reg [1279:0] lookup_high;
|
||||
|
||||
reg [9:0] lookup_entry;
|
||||
|
||||
begin
|
||||
lookup_low = {
|
||||
// CP_RES_LFHF
|
||||
10'b0011_1111_11, // M=1 - not legal
|
||||
10'b0011_1111_11, // M=2
|
||||
10'b0011_1101_11, // M=3
|
||||
10'b0011_0101_11, // M=4
|
||||
10'b0011_1001_11, // M=5
|
||||
10'b0011_1110_11, // M=6
|
||||
10'b0011_1110_11, // M=7
|
||||
10'b0011_0001_11,
|
||||
10'b0011_0110_11,
|
||||
10'b0011_0110_11,
|
||||
10'b0011_0110_11,
|
||||
10'b0011_1010_11,
|
||||
10'b0011_1010_11,
|
||||
10'b0011_1010_11,
|
||||
10'b0100_0110_11,
|
||||
10'b0011_1100_11,
|
||||
10'b1110_0110_11,
|
||||
10'b1111_0110_11,
|
||||
10'b1110_1010_11,
|
||||
10'b1110_1010_11,
|
||||
10'b1111_1010_11,
|
||||
10'b1111_1010_11,
|
||||
10'b1111_1010_11,
|
||||
10'b1111_1010_11,
|
||||
10'b1111_1010_11,
|
||||
10'b1101_1100_11,
|
||||
10'b1101_1100_11,
|
||||
10'b1101_1100_11,
|
||||
10'b1110_1100_11,
|
||||
10'b1110_1100_11,
|
||||
10'b1110_1100_11,
|
||||
10'b1111_1100_11,
|
||||
10'b1111_1100_11,
|
||||
10'b1111_1100_11,
|
||||
10'b1111_1100_11,
|
||||
10'b1111_1100_11,
|
||||
10'b1111_1100_11,
|
||||
10'b1110_0010_11,
|
||||
10'b1110_0010_11,
|
||||
10'b1110_0010_11,
|
||||
10'b1110_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1100_0100_11,
|
||||
10'b1100_0100_11,
|
||||
10'b1100_0100_11,
|
||||
10'b1100_0100_11,
|
||||
10'b1100_0100_11,
|
||||
10'b1100_0100_11,
|
||||
10'b1100_0100_11,
|
||||
10'b1100_0100_11,
|
||||
10'b1101_0100_11,
|
||||
10'b1101_0100_11,
|
||||
10'b1101_0100_11,
|
||||
10'b1101_0100_11,
|
||||
10'b1101_0100_11,
|
||||
10'b1101_0100_11,
|
||||
10'b1101_0100_11,
|
||||
10'b1110_0100_11,
|
||||
10'b1110_0100_11,
|
||||
10'b1110_0100_11,
|
||||
10'b1110_0100_11,
|
||||
10'b1110_0100_11,
|
||||
10'b1110_0100_11,
|
||||
10'b1110_0100_11,
|
||||
10'b1110_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1101_1000_11,
|
||||
10'b1101_1000_11,
|
||||
10'b1101_1000_11,
|
||||
10'b1101_1000_11,
|
||||
10'b1101_1000_11,
|
||||
10'b1101_1000_11,
|
||||
10'b1101_1000_11,
|
||||
10'b1101_1000_11, // M=127
|
||||
10'b1101_1000_11 // M=128
|
||||
};
|
||||
|
||||
lookup_high = {
|
||||
// CP_RES_LFHF
|
||||
10'b0111_1111_11, // M=1 - not legal
|
||||
10'b0111_1111_11, // M=2
|
||||
10'b1110_1111_11, // M=3
|
||||
10'b1111_1111_11, // M=4
|
||||
10'b1111_1011_11, // M=5
|
||||
10'b1111_1101_11, // M=6
|
||||
10'b1111_0011_11, // M=7
|
||||
10'b1110_0101_11,
|
||||
10'b1111_1001_11,
|
||||
10'b1111_1001_11,
|
||||
10'b1110_1110_11,
|
||||
10'b1111_1110_11,
|
||||
10'b1111_0001_11,
|
||||
10'b1111_0001_11,
|
||||
10'b1111_0001_11,
|
||||
10'b1110_0110_11,
|
||||
10'b1110_0110_11,
|
||||
10'b1111_0110_11,
|
||||
10'b1110_1010_11,
|
||||
10'b1110_1010_11,
|
||||
10'b1111_1010_11,
|
||||
10'b1111_1010_11,
|
||||
10'b1111_1010_11,
|
||||
10'b1111_1010_11,
|
||||
10'b1111_1010_11,
|
||||
10'b1101_1100_11,
|
||||
10'b1101_1100_11,
|
||||
10'b1101_1100_11,
|
||||
10'b1110_1100_11,
|
||||
10'b1110_1100_11,
|
||||
10'b1110_1100_11,
|
||||
10'b1111_1100_11,
|
||||
10'b1111_1100_11,
|
||||
10'b1111_1100_11,
|
||||
10'b1111_1100_11,
|
||||
10'b1111_1100_11,
|
||||
10'b1111_1100_11,
|
||||
10'b1110_0010_11,
|
||||
10'b1110_0010_11,
|
||||
10'b1110_0010_11,
|
||||
10'b1110_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1111_0010_11,
|
||||
10'b1100_0100_11,
|
||||
10'b1100_0100_11,
|
||||
10'b1100_0100_11,
|
||||
10'b1100_0100_11,
|
||||
10'b1100_0100_11,
|
||||
10'b1100_0100_11,
|
||||
10'b1100_0100_11,
|
||||
10'b1100_0100_11,
|
||||
10'b1101_0100_11,
|
||||
10'b1101_0100_11,
|
||||
10'b1101_0100_11,
|
||||
10'b1101_0100_11,
|
||||
10'b1101_0100_11,
|
||||
10'b1101_0100_11,
|
||||
10'b1101_0100_11,
|
||||
10'b1110_0100_11,
|
||||
10'b1110_0100_11,
|
||||
10'b1110_0100_11,
|
||||
10'b1110_0100_11,
|
||||
10'b1110_0100_11,
|
||||
10'b1110_0100_11,
|
||||
10'b1110_0100_11,
|
||||
10'b1110_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1111_0100_11,
|
||||
10'b1101_1000_11,
|
||||
10'b1101_1000_11,
|
||||
10'b1101_1000_11,
|
||||
10'b1101_1000_11,
|
||||
10'b1101_1000_11,
|
||||
10'b1101_1000_11,
|
||||
10'b1101_1000_11,
|
||||
10'b1101_1000_11,
|
||||
10'b1101_1000_11 // M=128
|
||||
};
|
||||
|
||||
// Set lookup_entry with the explicit bits from lookup with a part select
|
||||
if(BANDWIDTH == "LOW") begin
|
||||
// Low Bandwidth
|
||||
mmcm_pll_filter_lookup = lookup_low[ ((128-divide)*10) +: 10];
|
||||
end else begin
|
||||
// High or optimized bandwidth
|
||||
mmcm_pll_filter_lookup = lookup_high[ ((128-divide)*10) +: 10];
|
||||
end
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("filter_lookup: %b", mmcm_pll_filter_lookup);
|
||||
`endif
|
||||
end
|
||||
endfunction
|
||||
|
||||
// This function takes in the divide, phase, and duty cycle
|
||||
// setting to calculate the upper and lower counter registers.
|
||||
function [37:0] mmcm_pll_count_calc
|
||||
(
|
||||
input [7:0] divide, // Max divide is 128
|
||||
input signed [31:0] phase,
|
||||
input [31:0] duty_cycle // Multiplied by 100,000
|
||||
);
|
||||
|
||||
reg [13:0] div_calc;
|
||||
reg [16:0] phase_calc;
|
||||
|
||||
begin
|
||||
`ifdef DEBUG
|
||||
$display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
|
||||
divide, phase, duty_cycle);
|
||||
`endif
|
||||
|
||||
// w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
|
||||
div_calc = mmcm_pll_divider(divide, duty_cycle);
|
||||
// mx[10:9], pm[8:6], dt[5:0]
|
||||
phase_calc = mmcm_pll_phase(divide, phase);
|
||||
|
||||
// Return value is the upper and lower address of counter
|
||||
// Upper address is:
|
||||
// RESERVED [31:26]
|
||||
// MX [25:24]
|
||||
// EDGE [23]
|
||||
// NOCOUNT [22]
|
||||
// DELAY_TIME [21:16]
|
||||
// Lower Address is:
|
||||
// PHASE_MUX [15:13]
|
||||
// RESERVED [12]
|
||||
// HIGH_TIME [11:6]
|
||||
// LOW_TIME [5:0]
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
|
||||
divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0],
|
||||
div_calc[13], div_calc[12],
|
||||
phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]);
|
||||
`endif
|
||||
|
||||
mmcm_pll_count_calc =
|
||||
{
|
||||
// Upper Address
|
||||
6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0],
|
||||
// Lower Address
|
||||
phase_calc[8:6], 1'b0, div_calc[11:0]
|
||||
};
|
||||
end
|
||||
endfunction
|
||||
|
||||
|
||||
// This function takes in the divide, phase, and duty cycle
|
||||
// setting to calculate the upper and lower counter registers.
|
||||
// for fractional multiply/divide functions.
|
||||
//
|
||||
//
|
||||
function [37:0] mmcm_frac_count_calc
|
||||
(
|
||||
input [7:0] divide, // Max divide is 128
|
||||
input signed [31:0] phase,
|
||||
input [31:0] duty_cycle, // Multiplied by 100,000. Not programmable in fractional
|
||||
input [9:0] frac // Multiplied by 1000
|
||||
);
|
||||
|
||||
//Required for fractional divide calculations
|
||||
reg [7:0] lt_frac;
|
||||
reg [7:0] ht_frac;
|
||||
|
||||
reg /*[7:0]*/ wf_fall_frac;
|
||||
reg /*[7:0]*/ wf_rise_frac;
|
||||
|
||||
reg [31:0] a;
|
||||
reg [7:0] pm_rise_frac_filtered ;
|
||||
reg [7:0] pm_fall_frac_filtered ;
|
||||
reg [7:0] clkout0_divide_int;
|
||||
reg [2:0] clkout0_divide_frac;
|
||||
reg [7:0] even_part_high;
|
||||
reg [7:0] even_part_low;
|
||||
|
||||
reg [7:0] odd;
|
||||
reg [7:0] odd_and_frac;
|
||||
|
||||
reg [7:0] pm_fall;
|
||||
reg [7:0] pm_rise;
|
||||
reg [7:0] dt;
|
||||
reg [7:0] dt_int;
|
||||
reg [63:0] dt_calc;
|
||||
|
||||
reg [7:0] pm_rise_frac;
|
||||
reg [7:0] pm_fall_frac;
|
||||
|
||||
reg [31:0] a_per_in_octets;
|
||||
reg [31:0] a_phase_in_cycles;
|
||||
|
||||
parameter precision = 0.125;
|
||||
|
||||
reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11
|
||||
reg [31: 0] phase_pos;
|
||||
reg [31: 0] phase_vco;
|
||||
reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11
|
||||
reg [13:0] div_calc;
|
||||
reg [16:0] phase_calc;
|
||||
|
||||
begin
|
||||
`ifdef DEBUG
|
||||
$display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d",
|
||||
divide, phase, duty_cycle);
|
||||
`endif
|
||||
|
||||
//convert phase to fixed
|
||||
if ((phase < -360000) || (phase > 360000)) begin
|
||||
`ifndef SYNTHESIS
|
||||
$display("ERROR: phase of $phase is not between -360000 and 360000");
|
||||
`endif
|
||||
$finish;
|
||||
end
|
||||
|
||||
|
||||
// Return value is
|
||||
// Transfer data
|
||||
// RESERVED [37:36]
|
||||
// FRAC_TIME [35:33]
|
||||
// FRAC_WF_FALL [32]
|
||||
// Upper address is:
|
||||
// RESERVED [31:26]
|
||||
// MX [25:24]
|
||||
// EDGE [23]
|
||||
// NOCOUNT [22]
|
||||
// DELAY_TIME [21:16]
|
||||
// Lower Address is:
|
||||
// PHASE_MUX [15:13]
|
||||
// RESERVED [12]
|
||||
// HIGH_TIME [11:6]
|
||||
// LOW_TIME [5:0]
|
||||
|
||||
|
||||
|
||||
clkout0_divide_frac = frac / 125;
|
||||
clkout0_divide_int = divide;
|
||||
|
||||
even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2);
|
||||
even_part_low = even_part_high;
|
||||
|
||||
odd = clkout0_divide_int - even_part_high - even_part_low;
|
||||
odd_and_frac = (8*odd) + clkout0_divide_frac;
|
||||
|
||||
lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1)
|
||||
ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1)
|
||||
|
||||
pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2
|
||||
pm_rise = 0; //0
|
||||
|
||||
wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || (clkout0_divide_int == 2 && clkout0_divide_frac == 1); //IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0)
|
||||
wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8); //IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0)
|
||||
|
||||
|
||||
|
||||
//Calculate phase in fractional cycles
|
||||
a_per_in_octets = (8 * divide) + (frac / 125) ;
|
||||
a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors
|
||||
pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000};
|
||||
|
||||
dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8)
|
||||
dt = dt_calc[7:0];
|
||||
|
||||
pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a;
|
||||
|
||||
dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt)
|
||||
pm_fall_frac = pm_fall + pm_rise_frac;
|
||||
pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000};
|
||||
|
||||
div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6]
|
||||
phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]}
|
||||
|
||||
mmcm_frac_count_calc[37:0] =
|
||||
{ 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac,
|
||||
1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], 2'b00, dt[5:0],
|
||||
pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0]
|
||||
} ;
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac);
|
||||
`endif
|
||||
|
||||
end
|
||||
endfunction
|
||||
|
||||
+536
@@ -0,0 +1,536 @@
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Company: Xilinx
|
||||
// Engineer: Jim Tatsukawa, Ralf Krueger, updated for Ultrascale+
|
||||
// Date: 6/15/2015
|
||||
// Design Name: PLLE4 DRP
|
||||
// Module Name: plle4_drp_func.h
|
||||
// Version: 2.0
|
||||
// Target Devices: UltraScale+ Architecture
|
||||
// Tool versions: 2017.1
|
||||
// Description: This header provides the functions necessary to
|
||||
// calculate the DRP register values for the V6 PLL.
|
||||
//
|
||||
// Revision Notes: 8/11 - PLLE3 updated for PLLE3 file 4564419
|
||||
// Revision Notes: 6/15 - pll_filter_lookup fixed for max M of 19
|
||||
// M_Rise bits have been removed for PLLE3
|
||||
// Revision Notes: 2/28/17 - pll_filter_lookup and CPRES updated for
|
||||
// Ultrascale+ and for max M of 21
|
||||
//
|
||||
// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
|
||||
// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
|
||||
// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
|
||||
// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
|
||||
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
|
||||
// APPLICATION OR STANDARD, XILINX IS MAKING NO
|
||||
// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
|
||||
// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
|
||||
// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
|
||||
// REQUIRE FOR YOUR IMPLEMENTATION. XILINX
|
||||
// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
|
||||
// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
|
||||
// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
|
||||
// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
|
||||
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
|
||||
// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
// PURPOSE.
|
||||
//
|
||||
// (c) Copyright 2009-2017 Xilinx, Inc.
|
||||
// All rights reserved.
|
||||
//
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// These are user functions that should not be modified. Changes to the defines
|
||||
// or code within the functions may alter the accuracy of the calculations.
|
||||
|
||||
// Define debug to provide extra messages durring elaboration
|
||||
//`define DEBUG 1
|
||||
|
||||
// FRAC_PRECISION describes the width of the fractional portion of the fixed
|
||||
// point numbers. These should not be modified, they are for development
|
||||
// only
|
||||
`define FRAC_PRECISION 10
|
||||
// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
|
||||
// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs
|
||||
// greater than 32
|
||||
`define FIXED_WIDTH 32
|
||||
|
||||
// This function takes a fixed point number and rounds it to the nearest
|
||||
// fractional precision bit.
|
||||
function [`FIXED_WIDTH:1] round_frac
|
||||
(
|
||||
// Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
|
||||
input [`FIXED_WIDTH:1] decimal,
|
||||
|
||||
// This describes the precision of the fraction, for example a value
|
||||
// of 1 would modify the fractional so that instead of being a .16
|
||||
// fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
|
||||
input [`FIXED_WIDTH:1] precision
|
||||
);
|
||||
|
||||
begin
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("round_frac - decimal: %h, precision: %h", decimal, precision);
|
||||
`endif
|
||||
// If the fractional precision bit is high then round up
|
||||
if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
|
||||
round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
|
||||
end else begin
|
||||
round_frac = decimal;
|
||||
end
|
||||
`ifdef DEBUG
|
||||
$display("round_frac: %h", round_frac);
|
||||
`endif
|
||||
end
|
||||
endfunction
|
||||
|
||||
// This function calculates high_time, low_time, w_edge, and no_count
|
||||
// of a non-fractional counter based on the divide and duty cycle
|
||||
//
|
||||
// NOTE: high_time and low_time are returned as integers between 0 and 63
|
||||
// inclusive. 64 should equal 6'b000000 (in other words it is okay to
|
||||
// ignore the overflow)
|
||||
function [13:0] mmcm_pll_divider
|
||||
(
|
||||
input [7:0] divide, // Max divide is 128
|
||||
input [31:0] duty_cycle // Duty cycle is multiplied by 100,000
|
||||
);
|
||||
|
||||
reg [`FIXED_WIDTH:1] duty_cycle_fix;
|
||||
|
||||
// High/Low time is initially calculated with a wider integer to prevent a
|
||||
// calculation error when it overflows to 64.
|
||||
reg [6:0] high_time;
|
||||
reg [6:0] low_time;
|
||||
reg w_edge;
|
||||
reg no_count;
|
||||
|
||||
reg [`FIXED_WIDTH:1] temp;
|
||||
|
||||
begin
|
||||
// Duty Cycle must be between 0 and 1,000
|
||||
if(duty_cycle <=0 || duty_cycle >= 100000) begin
|
||||
`ifndef SYNTHESIS
|
||||
$display("ERROR: duty_cycle: %d is invalid", duty_cycle);
|
||||
`endif
|
||||
$finish;
|
||||
end
|
||||
|
||||
// Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
|
||||
duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("duty_cycle_fix: %h", duty_cycle_fix);
|
||||
`endif
|
||||
|
||||
// If the divide is 1 nothing needs to be set except the no_count bit.
|
||||
// Other values are dummies
|
||||
if(divide == 7'h01) begin
|
||||
high_time = 7'h01;
|
||||
w_edge = 1'b0;
|
||||
low_time = 7'h01;
|
||||
no_count = 1'b1;
|
||||
end else begin
|
||||
temp = round_frac(duty_cycle_fix*divide, 1);
|
||||
|
||||
// comes from above round_frac
|
||||
high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1];
|
||||
// If the duty cycle * divide rounded is .5 or greater then this bit
|
||||
// is set.
|
||||
w_edge = temp[`FRAC_PRECISION]; // comes from round_frac
|
||||
|
||||
// If the high time comes out to 0, it needs to be set to at least 1
|
||||
// and w_edge set to 0
|
||||
if(high_time == 7'h00) begin
|
||||
high_time = 7'h01;
|
||||
w_edge = 1'b0;
|
||||
end
|
||||
|
||||
if(high_time == divide) begin
|
||||
high_time = divide - 1;
|
||||
w_edge = 1'b1;
|
||||
end
|
||||
|
||||
// Calculate low_time based on the divide setting and set no_count to
|
||||
// 0 as it is only used when divide is 1.
|
||||
low_time = divide - high_time;
|
||||
no_count = 1'b0;
|
||||
end
|
||||
|
||||
// Set the return value.
|
||||
mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
|
||||
end
|
||||
endfunction
|
||||
|
||||
// This function calculates mx, delay_time, and phase_mux
|
||||
// of a non-fractional counter based on the divide and phase
|
||||
//
|
||||
// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
|
||||
// is used.
|
||||
function [10:0] mmcm_pll_phase
|
||||
(
|
||||
// divide must be an integer (use fractional if not)
|
||||
// assumed that divide already checked to be valid
|
||||
input [7:0] divide, // Max divide is 128
|
||||
|
||||
// Phase is given in degrees (-360,000 to 360,000)
|
||||
input signed [31:0] phase
|
||||
);
|
||||
|
||||
reg [`FIXED_WIDTH:1] phase_in_cycles;
|
||||
reg [`FIXED_WIDTH:1] phase_fixed;
|
||||
reg [1:0] mx;
|
||||
reg [5:0] delay_time;
|
||||
reg [2:0] phase_mux;
|
||||
|
||||
reg [`FIXED_WIDTH:1] temp;
|
||||
|
||||
begin
|
||||
`ifdef DEBUG
|
||||
$display("pll_phase-divide:%d,phase:%d",
|
||||
divide, phase);
|
||||
`endif
|
||||
|
||||
if ((phase < -360000) || (phase > 360000)) begin
|
||||
`ifndef SYNTHESIS
|
||||
$display("ERROR: phase of $phase is not between -360000 and 360000");
|
||||
`endif
|
||||
$finish;
|
||||
end
|
||||
|
||||
// If phase is less than 0, convert it to a positive phase shift
|
||||
// Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
|
||||
if(phase < 0) begin
|
||||
phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
|
||||
end else begin
|
||||
phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
|
||||
end
|
||||
|
||||
// Put phase in terms of decimal number of vco clock cycles
|
||||
phase_in_cycles = ( phase_fixed * divide ) / 360;
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("phase_in_cycles: %h", phase_in_cycles);
|
||||
`endif
|
||||
|
||||
|
||||
temp = round_frac(phase_in_cycles, 3);
|
||||
|
||||
// set mx to 2'b00 that the phase mux from the VCO is enabled
|
||||
mx = 2'b00;
|
||||
phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
|
||||
delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("temp: %h", temp);
|
||||
`endif
|
||||
|
||||
// Setup the return value
|
||||
mmcm_pll_phase={mx, phase_mux, delay_time};
|
||||
end
|
||||
endfunction
|
||||
|
||||
// This function takes the divide value and outputs the necessary lock values
|
||||
function [39:0] mmcm_pll_lock_lookup
|
||||
(
|
||||
input [6:0] divide // Max divide is 21
|
||||
);
|
||||
|
||||
reg [839:0] lookup;
|
||||
|
||||
begin
|
||||
lookup = {
|
||||
// This table is composed of:
|
||||
// LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
|
||||
40'b00110_00110_1111101000_1111101001_0000000001, //1 illegal in Ultrascale+
|
||||
40'b00110_00110_1111101000_1111101001_0000000001, //2
|
||||
40'b01000_01000_1111101000_1111101001_0000000001, //3
|
||||
40'b01011_01011_1111101000_1111101001_0000000001, //4
|
||||
40'b01110_01110_1111101000_1111101001_0000000001, //5
|
||||
40'b10001_10001_1111101000_1111101001_0000000001, //6
|
||||
40'b10011_10011_1111101000_1111101001_0000000001, //7
|
||||
40'b10110_10110_1111101000_1111101001_0000000001, //8
|
||||
40'b11001_11001_1111101000_1111101001_0000000001, //9
|
||||
40'b11100_11100_1111101000_1111101001_0000000001, //10
|
||||
40'b11111_11111_1110000100_1111101001_0000000001, //11
|
||||
40'b11111_11111_1100111001_1111101001_0000000001, //12
|
||||
40'b11111_11111_1011101110_1111101001_0000000001, //13
|
||||
40'b11111_11111_1010111100_1111101001_0000000001, //14
|
||||
40'b11111_11111_1010001010_1111101001_0000000001, //15
|
||||
40'b11111_11111_1001110001_1111101001_0000000001, //16
|
||||
40'b11111_11111_1000111111_1111101001_0000000001, //17
|
||||
40'b11111_11111_1000100110_1111101001_0000000001, //18
|
||||
40'b11111_11111_1000001101_1111101001_0000000001, //19
|
||||
40'b11111_11111_0111110100_1111101001_0000000001, //20
|
||||
40'b11111_11111_0111011011_1111101001_0000000001 //21
|
||||
};
|
||||
|
||||
// Set lookup_entry with the explicit bits from lookup with a part select
|
||||
mmcm_pll_lock_lookup = lookup[ ((21-divide)*40) +: 40];
|
||||
`ifdef DEBUG
|
||||
$display("lock_lookup: %b", pll_lock_lookup);
|
||||
`endif
|
||||
end
|
||||
endfunction
|
||||
|
||||
// This function takes the divide value and the bandwidth setting of the PLL
|
||||
// and outputs the digital filter settings necessary. Removing bandwidth setting for PLLE3.
|
||||
function [9:0] mmcm_pll_filter_lookup
|
||||
(
|
||||
input [6:0] divide // Max divide is 21
|
||||
);
|
||||
|
||||
reg [209:0] lookup;
|
||||
reg [9:0] lookup_entry;
|
||||
|
||||
begin
|
||||
|
||||
lookup = {
|
||||
// CP_RES_LFHF
|
||||
10'b0011_0111_11, //1 not legal in Ultrascale+
|
||||
10'b0011_0111_11, //2
|
||||
10'b0011_0011_11, //3
|
||||
10'b0011_1001_11, //4
|
||||
10'b0011_0001_11, //5
|
||||
10'b0100_1110_11, //6
|
||||
10'b0011_0110_11, //7
|
||||
10'b0011_1010_11, //8
|
||||
10'b0111_1001_11, //9
|
||||
10'b0111_1001_11, //10
|
||||
10'b0101_0110_11, //11
|
||||
10'b1100_0101_11, //12
|
||||
10'b0101_1010_11, //13
|
||||
10'b0110_0110_11, //14
|
||||
10'b0110_1010_11, //15
|
||||
10'b0111_0110_11, //16
|
||||
10'b1111_0101_11, //17
|
||||
10'b1100_0110_11, //18
|
||||
10'b1110_0001_11, //19
|
||||
10'b1101_0110_11, //20
|
||||
10'b1111_0001_11 //21
|
||||
};
|
||||
|
||||
mmcm_pll_filter_lookup = lookup [ ((21-divide)*10) +: 10];
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("filter_lookup: %b", pll_filter_lookup);
|
||||
`endif
|
||||
end
|
||||
endfunction
|
||||
|
||||
// This function set the CLKOUTPHY divide settings to match
|
||||
// the desired CLKOUTPHY_MODE setting. To create VCO_X2, then
|
||||
// the CLKOUTPHY will be set to 2'b00 since the VCO is internally
|
||||
// doubled and 2'b00 will represent divide by 1. Similarly "VCO"
|
||||
// will need to divide the doubled clock VCO clock frequency by
|
||||
// 2 therefore 2'b01 will match a divide by 2.And VCO_HALF will
|
||||
// need to divide the doubled VCO by 4, therefore 2'b10
|
||||
function [9:0] mmcm_pll_clkoutphy_calc
|
||||
(
|
||||
input [8*9:0] CLKOUTPHY_MODE
|
||||
);
|
||||
|
||||
if(CLKOUTPHY_MODE == "VCO_X2") begin
|
||||
mmcm_pll_clkoutphy_calc= 2'b00;
|
||||
end else if(CLKOUTPHY_MODE == "VCO") begin
|
||||
mmcm_pll_clkoutphy_calc= 2'b01;
|
||||
end else if(CLKOUTPHY_MODE == "CLKIN") begin
|
||||
mmcm_pll_clkoutphy_calc= 2'b11;
|
||||
end else begin // Assume "VCO_HALF"
|
||||
mmcm_pll_clkoutphy_calc= 2'b10;
|
||||
end
|
||||
|
||||
endfunction
|
||||
|
||||
|
||||
// This function takes in the divide, phase, and duty cycle
|
||||
// setting to calculate the upper and lower counter registers.
|
||||
function [37:0] mmcm_pll_count_calc
|
||||
(
|
||||
input [7:0] divide, // Max divide is 128
|
||||
input signed [31:0] phase,
|
||||
input [31:0] duty_cycle // Multiplied by 100,000
|
||||
);
|
||||
|
||||
reg [13:0] div_calc;
|
||||
reg [16:0] phase_calc;
|
||||
|
||||
begin
|
||||
`ifdef DEBUG
|
||||
$display("pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
|
||||
divide, phase, duty_cycle);
|
||||
`endif
|
||||
|
||||
// w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
|
||||
div_calc = mmcm_pll_divider(divide, duty_cycle);
|
||||
// mx[10:9], pm[8:6], dt[5:0]
|
||||
phase_calc = mmcm_pll_phase(divide, phase);
|
||||
|
||||
// Return value is the upper and lower address of counter
|
||||
// Upper address is:
|
||||
// RESERVED [31:26]
|
||||
// MX [25:24]
|
||||
// EDGE [23]
|
||||
// NOCOUNT [22]
|
||||
// DELAY_TIME [21:16]
|
||||
// Lower Address is:
|
||||
// PHASE_MUX [15:13]
|
||||
// RESERVED [12]
|
||||
// HIGH_TIME [11:6]
|
||||
// LOW_TIME [5:0]
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
|
||||
divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0],
|
||||
div_calc[13], div_calc[12],
|
||||
phase_calc[16:15], phase_calc[5:0], 3'b000); //Removed PM_Rise bits
|
||||
`endif
|
||||
|
||||
mmcm_pll_count_calc =
|
||||
{
|
||||
// Upper Address
|
||||
6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0],
|
||||
// Lower Address
|
||||
phase_calc[8:6], 1'b0, div_calc[11:0]
|
||||
};
|
||||
end
|
||||
endfunction
|
||||
|
||||
|
||||
// This function takes in the divide, phase, and duty cycle
|
||||
// setting to calculate the upper and lower counter registers.
|
||||
// for fractional multiply/divide functions.
|
||||
//
|
||||
//
|
||||
function [37:0] mmcm_pll_frac_count_calc
|
||||
(
|
||||
input [7:0] divide, // Max divide is 128
|
||||
input signed [31:0] phase,
|
||||
input [31:0] duty_cycle, // Multiplied by 1,000
|
||||
input [9:0] frac // Multiplied by 1000
|
||||
);
|
||||
|
||||
//Required for fractional divide calculations
|
||||
reg [7:0] lt_frac;
|
||||
reg [7:0] ht_frac;
|
||||
|
||||
reg /*[7:0]*/ wf_fall_frac;
|
||||
reg /*[7:0]*/ wf_rise_frac;
|
||||
|
||||
reg [31:0] a;
|
||||
reg [7:0] pm_rise_frac_filtered ;
|
||||
reg [7:0] pm_fall_frac_filtered ;
|
||||
reg [7:0] clkout0_divide_int;
|
||||
reg [2:0] clkout0_divide_frac;
|
||||
reg [7:0] even_part_high;
|
||||
reg [7:0] even_part_low;
|
||||
|
||||
reg [7:0] odd;
|
||||
reg [7:0] odd_and_frac;
|
||||
|
||||
reg [7:0] pm_fall;
|
||||
reg [7:0] pm_rise;
|
||||
reg [7:0] dt;
|
||||
reg [7:0] dt_int;
|
||||
reg [63:0] dt_calc;
|
||||
|
||||
reg [7:0] pm_rise_frac;
|
||||
reg [7:0] pm_fall_frac;
|
||||
|
||||
reg [31:0] a_per_in_octets;
|
||||
reg [31:0] a_phase_in_cycles;
|
||||
|
||||
parameter precision = 0.125;
|
||||
|
||||
reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11
|
||||
reg [31: 0] phase_pos;
|
||||
reg [31: 0] phase_vco;
|
||||
reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11
|
||||
reg [13:0] div_calc;
|
||||
reg [16:0] phase_calc;
|
||||
|
||||
begin
|
||||
`ifdef DEBUG
|
||||
$display("pll_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d",
|
||||
divide, phase, duty_cycle);
|
||||
`endif
|
||||
|
||||
//convert phase to fixed
|
||||
if ((phase < -360000) || (phase > 360000)) begin
|
||||
`ifndef SYNTHESIS
|
||||
$display("ERROR: phase of $phase is not between -360000 and 360000");
|
||||
`endif
|
||||
$finish;
|
||||
end
|
||||
|
||||
|
||||
// Return value is
|
||||
// Transfer data
|
||||
// RESERVED [37:36]
|
||||
// FRAC_TIME [35:33]
|
||||
// FRAC_WF_FALL [32]
|
||||
// Upper address is:
|
||||
// RESERVED [31:26]
|
||||
// MX [25:24]
|
||||
// EDGE [23]
|
||||
// NOCOUNT [22]
|
||||
// DELAY_TIME [21:16]
|
||||
// Lower Address is:
|
||||
// PHASE_MUX [15:13]
|
||||
// RESERVED [12]
|
||||
// HIGH_TIME [11:6]
|
||||
// LOW_TIME [5:0]
|
||||
|
||||
|
||||
|
||||
clkout0_divide_frac = frac / 125;
|
||||
clkout0_divide_int = divide;
|
||||
|
||||
even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2);
|
||||
even_part_low = even_part_high;
|
||||
|
||||
odd = clkout0_divide_int - even_part_high - even_part_low;
|
||||
odd_and_frac = (8*odd) + clkout0_divide_frac;
|
||||
|
||||
lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1)
|
||||
ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1)
|
||||
|
||||
pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2
|
||||
pm_rise = 0; //0
|
||||
|
||||
wf_fall_frac = (odd_and_frac >=2) && (odd_and_frac <=9);//IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0)
|
||||
wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0)
|
||||
|
||||
|
||||
|
||||
//Calculate phase in fractional cycles
|
||||
a_per_in_octets = (8 * divide) + (frac / 125) ;
|
||||
a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors
|
||||
pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000};
|
||||
|
||||
dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8)
|
||||
dt = dt_calc[7:0];
|
||||
|
||||
pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a;
|
||||
|
||||
dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt)
|
||||
pm_fall_frac = pm_fall + pm_rise_frac;
|
||||
pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000};
|
||||
|
||||
div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6]
|
||||
phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]}
|
||||
|
||||
mmcm_pll_frac_count_calc[37:0] =
|
||||
{ 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac,
|
||||
1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0],
|
||||
3'b000, 1'b0, ht_frac[5:0], lt_frac[5:0] //Removed PM_Rise bits
|
||||
} ;
|
||||
|
||||
`ifdef DEBUG
|
||||
$display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, 3'b000, ht_frac, lt_frac);
|
||||
`endif
|
||||
|
||||
end
|
||||
endfunction
|
||||
|
||||
+1116
File diff suppressed because it is too large
Load Diff
+633
@@ -0,0 +1,633 @@
|
||||
// (c) Copyright 2016 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//-----------------------------------------------------------------------------
|
||||
//
|
||||
// AXI VIP wrapper
|
||||
//
|
||||
// Verilog-standard: Verilog 2001
|
||||
//--------------------------------------------------------------------------
|
||||
//
|
||||
// Structure:
|
||||
// axi_vip
|
||||
//
|
||||
//--------------------------------------------------------------------------
|
||||
|
||||
`timescale 1ps/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings="yes" *)
|
||||
module axi_vip_v1_1_5_top #
|
||||
(
|
||||
parameter C_AXI_PROTOCOL = 0,
|
||||
parameter C_AXI_INTERFACE_MODE = 1, //master, slave and bypass
|
||||
parameter integer C_AXI_ADDR_WIDTH = 32,
|
||||
parameter integer C_AXI_WDATA_WIDTH = 32,
|
||||
parameter integer C_AXI_RDATA_WIDTH = 32,
|
||||
parameter integer C_AXI_WID_WIDTH = 0,
|
||||
parameter integer C_AXI_RID_WIDTH = 0,
|
||||
parameter integer C_AXI_AWUSER_WIDTH = 0,
|
||||
parameter integer C_AXI_ARUSER_WIDTH = 0,
|
||||
parameter integer C_AXI_WUSER_WIDTH = 0,
|
||||
parameter integer C_AXI_RUSER_WIDTH = 0,
|
||||
parameter integer C_AXI_BUSER_WIDTH = 0,
|
||||
parameter integer C_AXI_SUPPORTS_NARROW = 1,
|
||||
parameter integer C_AXI_HAS_BURST = 1,
|
||||
parameter integer C_AXI_HAS_LOCK = 1,
|
||||
parameter integer C_AXI_HAS_CACHE = 1,
|
||||
parameter integer C_AXI_HAS_REGION = 1,
|
||||
parameter integer C_AXI_HAS_PROT = 1,
|
||||
parameter integer C_AXI_HAS_QOS = 1,
|
||||
parameter integer C_AXI_HAS_WSTRB = 1,
|
||||
parameter integer C_AXI_HAS_BRESP = 1,
|
||||
parameter integer C_AXI_HAS_RRESP = 1,
|
||||
parameter integer C_AXI_HAS_ARESETN = 1
|
||||
)
|
||||
(
|
||||
//NOTE: C_AXI_INTERFACE_MODE =0 means MASTER MODE, 1 means PASS-THROUGH MODE and 2 means SLAVE MODE
|
||||
//Please refer xgui tcl and coreinfo.yml
|
||||
|
||||
// System Signals
|
||||
input wire aclk,
|
||||
input wire aclken,
|
||||
input wire aresetn,
|
||||
|
||||
// Slave Interface Write Address Ports
|
||||
input wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0] s_axi_awid,
|
||||
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
|
||||
input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,
|
||||
input wire [3-1:0] s_axi_awsize,
|
||||
input wire [2-1:0] s_axi_awburst,
|
||||
input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,
|
||||
input wire [4-1:0] s_axi_awcache,
|
||||
input wire [3-1:0] s_axi_awprot,
|
||||
input wire [4-1:0] s_axi_awregion,
|
||||
input wire [4-1:0] s_axi_awqos,
|
||||
input wire [C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,
|
||||
input wire s_axi_awvalid,
|
||||
output wire s_axi_awready,
|
||||
|
||||
// Slave Interface Write Data Ports
|
||||
input wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0] s_axi_wid,
|
||||
input wire [C_AXI_WDATA_WIDTH-1:0] s_axi_wdata,
|
||||
input wire [C_AXI_WDATA_WIDTH/8==0 ?0:C_AXI_WDATA_WIDTH/8-1:0] s_axi_wstrb,
|
||||
input wire s_axi_wlast,
|
||||
input wire [C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0] s_axi_wuser,
|
||||
input wire s_axi_wvalid,
|
||||
output wire s_axi_wready,
|
||||
|
||||
// Slave Interface Write Response Ports
|
||||
output wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0] s_axi_bid,
|
||||
output wire [2-1:0] s_axi_bresp,
|
||||
output wire [C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0] s_axi_buser,
|
||||
output wire s_axi_bvalid,
|
||||
input wire s_axi_bready,
|
||||
|
||||
// Slave Interface Read Address Ports
|
||||
input wire [C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0] s_axi_arid,
|
||||
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
|
||||
input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,
|
||||
input wire [3-1:0] s_axi_arsize,
|
||||
input wire [2-1:0] s_axi_arburst,
|
||||
input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,
|
||||
input wire [4-1:0] s_axi_arcache,
|
||||
input wire [3-1:0] s_axi_arprot,
|
||||
input wire [4-1:0] s_axi_arregion,
|
||||
input wire [4-1:0] s_axi_arqos,
|
||||
input wire [C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,
|
||||
input wire s_axi_arvalid,
|
||||
output wire s_axi_arready,
|
||||
|
||||
// Slave Interface Read Data Ports
|
||||
output wire [C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0] s_axi_rid,
|
||||
output wire [C_AXI_RDATA_WIDTH-1:0] s_axi_rdata,
|
||||
output wire [2-1:0] s_axi_rresp,
|
||||
output wire s_axi_rlast,
|
||||
output wire [C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,
|
||||
output wire s_axi_rvalid,
|
||||
input wire s_axi_rready,
|
||||
|
||||
// Master Interface Write Address Port
|
||||
output wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0] m_axi_awid,
|
||||
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
|
||||
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
|
||||
output wire [3-1:0] m_axi_awsize,
|
||||
output wire [2-1:0] m_axi_awburst,
|
||||
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
|
||||
output wire [4-1:0] m_axi_awcache,
|
||||
output wire [3-1:0] m_axi_awprot,
|
||||
output wire [4-1:0] m_axi_awregion,
|
||||
output wire [4-1:0] m_axi_awqos,
|
||||
output wire [C_AXI_AWUSER_WIDTH==0?0:C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
|
||||
output wire m_axi_awvalid,
|
||||
input wire m_axi_awready,
|
||||
|
||||
// Master Interface Write Data Ports
|
||||
output wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0] m_axi_wid,
|
||||
output wire [C_AXI_WDATA_WIDTH-1:0] m_axi_wdata,
|
||||
output wire [C_AXI_WDATA_WIDTH/8 ==0?0:C_AXI_WDATA_WIDTH/8-1:0] m_axi_wstrb,
|
||||
output wire m_axi_wlast,
|
||||
output wire [C_AXI_WUSER_WIDTH==0?0:C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
|
||||
output wire m_axi_wvalid,
|
||||
input wire m_axi_wready,
|
||||
|
||||
// Master Interface Write Response Ports
|
||||
input wire [C_AXI_WID_WIDTH==0?0:C_AXI_WID_WIDTH-1:0] m_axi_bid,
|
||||
input wire [2-1:0] m_axi_bresp,
|
||||
input wire [C_AXI_BUSER_WIDTH==0?0:C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
|
||||
input wire m_axi_bvalid,
|
||||
output wire m_axi_bready,
|
||||
|
||||
// Master Interface Read Address Port
|
||||
output wire [C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0] m_axi_arid,
|
||||
output wire [ C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
|
||||
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
|
||||
output wire [3-1:0] m_axi_arsize,
|
||||
output wire [2-1:0] m_axi_arburst,
|
||||
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
|
||||
output wire [4-1:0] m_axi_arcache,
|
||||
output wire [3-1:0] m_axi_arprot,
|
||||
output wire [4-1:0] m_axi_arregion,
|
||||
output wire [4-1:0] m_axi_arqos,
|
||||
output wire [C_AXI_ARUSER_WIDTH==0?0:C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
|
||||
output wire m_axi_arvalid,
|
||||
input wire m_axi_arready,
|
||||
|
||||
// Master Interface Read Data Ports
|
||||
input wire [C_AXI_RID_WIDTH==0?0:C_AXI_RID_WIDTH-1:0] m_axi_rid,
|
||||
input wire [C_AXI_RDATA_WIDTH-1:0] m_axi_rdata,
|
||||
input wire [2-1:0] m_axi_rresp,
|
||||
input wire m_axi_rlast,
|
||||
input wire [C_AXI_RUSER_WIDTH==0?0:C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
|
||||
input wire m_axi_rvalid,
|
||||
output wire m_axi_rready
|
||||
);
|
||||
|
||||
/**********************************************************************************************
|
||||
* NOTE:
|
||||
* C_AXI_INTERFACE_MODE =0 -- MASTER MODE,
|
||||
* C_AXI_INTERFACE_MODE =1 -- PASS-THROUGH MODE
|
||||
* C_AXI_INTERFACE_MODE =2 -- SLAVE MODE
|
||||
* Please refer xgui tcl and coreinfo.yml
|
||||
* User can change PASS_THROUGH VIP to run time master mode or run time slave mode during
|
||||
* the simulation
|
||||
*********************************************************************************************/
|
||||
|
||||
/**********************************************************************************************
|
||||
* Master_mode means that either the dut is statically being configured to be in master mode
|
||||
* or it statically being configured to be pass-through mode and switched to be in master mode
|
||||
* in run time.
|
||||
|
||||
* Slave mode means that either the dut is statically being configured to be in slave mode
|
||||
* or it statically being configured to be pass-through mode and switched to be in slave mode
|
||||
* in run time.
|
||||
|
||||
* Pass-through mode means that either the dut is statically being configured to be in
|
||||
* pass-through mode or it statically being configured to be pass-through mode and switched
|
||||
* to be in master/slave mode and then switch back to be in pass-through mode in run time
|
||||
*********************************************************************************************/
|
||||
|
||||
logic runtime_master =0;
|
||||
logic runtime_slave =0;
|
||||
|
||||
wire run_slave_mode;
|
||||
wire run_master_mode;
|
||||
wire run_passth_mode;
|
||||
wire compile_master_mode;
|
||||
wire compile_slave_mode;
|
||||
wire master_mode;
|
||||
wire slave_mode;
|
||||
|
||||
assign run_master_mode = (C_AXI_INTERFACE_MODE ==1 && runtime_master ==1 &&runtime_slave ==0);
|
||||
assign run_slave_mode = C_AXI_INTERFACE_MODE ==1 && runtime_slave ==1 && runtime_master ==0;
|
||||
assign run_passth_mode = (runtime_slave ==0 && runtime_master ==0);
|
||||
|
||||
assign compile_master_mode = (C_AXI_INTERFACE_MODE ==0 || C_AXI_INTERFACE_MODE ==1 )&& run_passth_mode ;
|
||||
assign compile_slave_mode = (C_AXI_INTERFACE_MODE ==2 || C_AXI_INTERFACE_MODE ==1) && run_passth_mode ;
|
||||
|
||||
assign master_mode = compile_master_mode || run_master_mode;
|
||||
assign slave_mode = compile_slave_mode || run_slave_mode;
|
||||
|
||||
// Slave Interface Write Address Ports Internal
|
||||
assign IF.AWID = slave_mode? s_axi_awid : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{1'bz}};
|
||||
assign IF.AWADDR = slave_mode? s_axi_awaddr : {C_AXI_ADDR_WIDTH{1'bz}};
|
||||
assign IF.AWLEN = slave_mode? s_axi_awlen : {((C_AXI_PROTOCOL == 1) ? 4 : 8){1'bz}};
|
||||
assign IF.AWSIZE = slave_mode? (C_AXI_SUPPORTS_NARROW==0 ? $clog2(C_AXI_WDATA_WIDTH/8): s_axi_awsize): {3{1'bz}};
|
||||
assign IF.AWBURST = slave_mode? s_axi_awburst : {2{1'bz}};
|
||||
assign IF.AWLOCK = slave_mode? s_axi_awlock : {((C_AXI_PROTOCOL == 1) ? 2 : 1){1'bz}};
|
||||
assign IF.AWCACHE = slave_mode? s_axi_awcache : {4{1'bz}};
|
||||
assign IF.AWPROT = slave_mode? s_axi_awprot : {3{1'bz}};
|
||||
assign IF.AWREGION = slave_mode? s_axi_awregion : {4{1'bz}};
|
||||
assign IF.AWQOS = slave_mode? s_axi_awqos : {4{1'bz}};
|
||||
assign IF.AWUSER = slave_mode? s_axi_awuser : {C_AXI_AWUSER_WIDTH==0?1:C_AXI_AWUSER_WIDTH{1'bz}};
|
||||
assign IF.AWVALID = slave_mode? s_axi_awvalid : {1'bz};
|
||||
assign s_axi_awready = slave_mode? IF.AWREADY : {1'b0};
|
||||
|
||||
// Slave Interface Write Data Ports
|
||||
assign IF.WID = slave_mode? s_axi_wid : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{1'bz}};
|
||||
assign IF.WDATA = slave_mode? s_axi_wdata : {C_AXI_WDATA_WIDTH{1'bz}};
|
||||
assign IF.WSTRB = slave_mode? s_axi_wstrb : {(C_AXI_WDATA_WIDTH/8){1'bz}};
|
||||
assign IF.WLAST = slave_mode? s_axi_wlast: {1'bz};
|
||||
assign IF.WUSER = slave_mode? s_axi_wuser : {C_AXI_WUSER_WIDTH==0?1:C_AXI_WUSER_WIDTH{1'bz}};
|
||||
assign IF.WVALID = slave_mode? s_axi_wvalid : {1'bz};
|
||||
assign s_axi_wready = slave_mode? IF.WREADY : {1'b0};
|
||||
|
||||
// Slave Interface Write Response Ports
|
||||
assign s_axi_bid = slave_mode? IF.BID : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{1'b0}};
|
||||
assign s_axi_bresp = slave_mode? IF.BRESP : {2{1'b0}};
|
||||
assign s_axi_buser = slave_mode? IF.BUSER : {C_AXI_BUSER_WIDTH==0?1:C_AXI_BUSER_WIDTH{1'b0}};
|
||||
assign s_axi_bvalid = slave_mode? IF.BVALID : {1{1'b0}};
|
||||
assign IF.BREADY = slave_mode? s_axi_bready :{1{1'bz}};
|
||||
|
||||
// Slave Interface Read Address Ports
|
||||
assign IF.ARID = slave_mode? s_axi_arid :{C_AXI_RID_WIDTH==0?1:C_AXI_RID_WIDTH{1'bz}};
|
||||
assign IF.ARADDR = slave_mode? s_axi_araddr : {C_AXI_ADDR_WIDTH{1'bz}} ;
|
||||
assign IF.ARLEN = slave_mode? s_axi_arlen: {((C_AXI_PROTOCOL == 1) ? 4 : 8){1'bz}};
|
||||
assign IF.ARSIZE = slave_mode? (C_AXI_SUPPORTS_NARROW==0 ? $clog2(C_AXI_WDATA_WIDTH/8): s_axi_arsize) : {3{1'bz}};
|
||||
assign IF.ARBURST = slave_mode? s_axi_arburst : {2{1'bz}};
|
||||
assign IF.ARLOCK = slave_mode? s_axi_arlock : {((C_AXI_PROTOCOL == 1) ? 2 : 1){1'bz}};
|
||||
assign IF.ARCACHE = slave_mode? s_axi_arcache : {4{1'bz}};
|
||||
assign IF.ARPROT = slave_mode? s_axi_arprot : {3{1'bz}};
|
||||
assign IF.ARREGION = slave_mode? s_axi_arregion :{4{1'bz}} ;
|
||||
assign IF.ARQOS = slave_mode? s_axi_arqos : {4{1'bz}};
|
||||
assign IF.ARUSER = slave_mode? s_axi_aruser :{C_AXI_ARUSER_WIDTH==0?1:C_AXI_ARUSER_WIDTH{1'bz}};
|
||||
assign IF.ARVALID = slave_mode? s_axi_arvalid : {1'bz};
|
||||
assign s_axi_arready = slave_mode? IF.ARREADY : {1'b0};
|
||||
|
||||
//Slave Interface Read Data Ports
|
||||
assign s_axi_rid = slave_mode? IF.RID: {C_AXI_RID_WIDTH==0?1:C_AXI_RID_WIDTH{1'b0}};
|
||||
assign s_axi_rdata = slave_mode? IF.RDATA : {C_AXI_RDATA_WIDTH{1'b0}};
|
||||
assign s_axi_rresp = slave_mode? IF.RRESP : {2{1'b0}};
|
||||
assign s_axi_rlast = slave_mode? IF.RLAST : {{1'b0}};
|
||||
assign s_axi_ruser = slave_mode? IF.RUSER : {C_AXI_RUSER_WIDTH==0?1:C_AXI_RUSER_WIDTH{1'b0}};
|
||||
assign s_axi_rvalid = slave_mode? IF.RVALID : {{1'b0}};
|
||||
assign IF.RREADY = slave_mode? s_axi_rready:{{1'bz}};
|
||||
|
||||
// Master Interface Write Address Port
|
||||
assign m_axi_awid = master_mode? IF.AWID : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{1'b0}};
|
||||
assign m_axi_awaddr = master_mode? IF.AWADDR : {C_AXI_ADDR_WIDTH{1'b0}};
|
||||
assign m_axi_awlen = master_mode? IF.AWLEN : {((C_AXI_PROTOCOL == 1) ? 4 : 8){1'b0}};
|
||||
assign m_axi_awsize = master_mode? IF.AWSIZE : {3{1'b0}};
|
||||
assign m_axi_awburst = master_mode? IF.AWBURST : {2{1'b0}};
|
||||
assign m_axi_awlock = master_mode? IF.AWLOCK : {((C_AXI_PROTOCOL == 1) ? 2 : 1){1'b0}};
|
||||
assign m_axi_awcache = master_mode? IF.AWCACHE : {4{1'b0}};
|
||||
assign m_axi_awprot = master_mode? IF.AWPROT : {3{1'b0}};
|
||||
assign m_axi_awregion = master_mode? IF.AWREGION : {4{1'b0}};
|
||||
assign m_axi_awqos = master_mode? IF.AWQOS : {4{1'b0}};
|
||||
assign m_axi_awuser = master_mode? IF.AWUSER : {C_AXI_AWUSER_WIDTH==0?1:C_AXI_AWUSER_WIDTH{1'b0}};
|
||||
assign m_axi_awvalid = master_mode? IF.AWVALID :{1'b0};
|
||||
assign IF.AWREADY = master_mode? m_axi_awready :{1'bz};
|
||||
|
||||
// Master Interface Write Data Ports Internal
|
||||
assign m_axi_wid = master_mode? IF.WID : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{1'b0}};
|
||||
assign m_axi_wdata = master_mode? IF.WDATA : {C_AXI_WDATA_WIDTH{1'b0}};
|
||||
assign m_axi_wstrb = master_mode? IF.WSTRB : {(C_AXI_WDATA_WIDTH/8){1'b0}};
|
||||
assign m_axi_wlast = master_mode? IF.WLAST : {1'b0};
|
||||
assign m_axi_wuser = master_mode? IF.WUSER : {C_AXI_WUSER_WIDTH==0?1:C_AXI_WUSER_WIDTH{1'b0}};
|
||||
assign m_axi_wvalid = master_mode? IF.WVALID : {1'b0};
|
||||
assign IF.WREADY = master_mode? m_axi_wready : {1'bz};
|
||||
|
||||
// Master Interface Write Response Ports Internal
|
||||
assign IF.BID = master_mode? m_axi_bid : {C_AXI_WID_WIDTH==0?1:C_AXI_WID_WIDTH{1'bz}};
|
||||
assign IF.BRESP = master_mode? m_axi_bresp : {2{1'bz}};
|
||||
assign IF.BUSER = master_mode? m_axi_buser : {C_AXI_BUSER_WIDTH==0?1:C_AXI_BUSER_WIDTH{1'bz}};
|
||||
assign IF.BVALID = master_mode? m_axi_bvalid : 1'bz;
|
||||
assign m_axi_bready = master_mode? IF.BREADY : 1'b0;
|
||||
|
||||
// Master Interface Read Address Port Internal
|
||||
assign m_axi_arid = master_mode? IF.ARID : {C_AXI_RID_WIDTH==0?1:C_AXI_RID_WIDTH{1'b0}};
|
||||
assign m_axi_araddr = master_mode? IF.ARADDR : {C_AXI_ADDR_WIDTH{1'b0}};
|
||||
assign m_axi_arlen = master_mode? IF.ARLEN : {((C_AXI_PROTOCOL == 1) ? 4 : 8){1'b0}};
|
||||
assign m_axi_arsize = master_mode? IF.ARSIZE : {3{1'b0}};
|
||||
assign m_axi_arburst = master_mode? IF.ARBURST : {2{1'b0}};
|
||||
assign m_axi_arlock = master_mode? IF.ARLOCK : {((C_AXI_PROTOCOL == 1) ? 2 : 1){1'b0}};
|
||||
assign m_axi_arcache = master_mode?IF.ARCACHE : {4{1'b0}};
|
||||
assign m_axi_arprot = master_mode? IF.ARPROT : {3{1'b0}};
|
||||
assign m_axi_arregion = master_mode? IF.ARREGION : {4{1'b0}};
|
||||
assign m_axi_arqos = master_mode? IF.ARQOS : {4{1'b0}};
|
||||
assign m_axi_aruser = master_mode? IF.ARUSER : {C_AXI_ARUSER_WIDTH==0?1:C_AXI_ARUSER_WIDTH{1'b0}};
|
||||
assign m_axi_arvalid = master_mode? IF.ARVALID :{1'b0};
|
||||
assign IF.ARREADY = master_mode? m_axi_arready : {1{1'bz}};
|
||||
|
||||
// Master Interface Read Data Ports Internal
|
||||
assign IF.RID = master_mode? m_axi_rid : {C_AXI_RID_WIDTH==0?1:C_AXI_RID_WIDTH{1'bz}};
|
||||
assign IF.RDATA = master_mode? m_axi_rdata : {C_AXI_RDATA_WIDTH{1'bz}};
|
||||
assign IF.RRESP = master_mode? m_axi_rresp : {2{1'bz}};
|
||||
assign IF.RLAST = master_mode? m_axi_rlast : {1{1'bz}};
|
||||
assign IF.RUSER = master_mode? m_axi_ruser : {C_AXI_RUSER_WIDTH==0?1:C_AXI_RUSER_WIDTH{1'bz}};
|
||||
assign IF.RVALID = master_mode? m_axi_rvalid : {1{1'bz}};
|
||||
assign m_axi_rready = master_mode? IF.RREADY : {1{1'b0}};
|
||||
|
||||
axi_vip_if #(
|
||||
.C_AXI_PROTOCOL(C_AXI_PROTOCOL),
|
||||
.C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH ),
|
||||
.C_AXI_WDATA_WIDTH(C_AXI_WDATA_WIDTH ),
|
||||
.C_AXI_RDATA_WIDTH(C_AXI_RDATA_WIDTH ),
|
||||
.C_AXI_WID_WIDTH(C_AXI_WID_WIDTH ),
|
||||
.C_AXI_RID_WIDTH(C_AXI_RID_WIDTH ),
|
||||
.C_AXI_AWUSER_WIDTH(C_AXI_AWUSER_WIDTH ),
|
||||
.C_AXI_WUSER_WIDTH(C_AXI_WUSER_WIDTH ),
|
||||
.C_AXI_BUSER_WIDTH(C_AXI_BUSER_WIDTH ),
|
||||
.C_AXI_ARUSER_WIDTH(C_AXI_ARUSER_WIDTH ),
|
||||
.C_AXI_RUSER_WIDTH(C_AXI_RUSER_WIDTH ),
|
||||
.C_AXI_SUPPORTS_NARROW(C_AXI_SUPPORTS_NARROW),
|
||||
.C_AXI_HAS_BURST(C_AXI_HAS_BURST),
|
||||
.C_AXI_HAS_LOCK(C_AXI_HAS_LOCK),
|
||||
.C_AXI_HAS_CACHE(C_AXI_HAS_CACHE),
|
||||
.C_AXI_HAS_REGION(C_AXI_HAS_REGION),
|
||||
.C_AXI_HAS_PROT(C_AXI_HAS_PROT),
|
||||
.C_AXI_HAS_QOS(C_AXI_HAS_QOS),
|
||||
.C_AXI_HAS_WSTRB(C_AXI_HAS_WSTRB),
|
||||
.C_AXI_HAS_BRESP(C_AXI_HAS_BRESP),
|
||||
.C_AXI_HAS_RRESP(C_AXI_HAS_RRESP),
|
||||
.C_AXI_HAS_ARESETN(C_AXI_HAS_ARESETN)
|
||||
) IF (
|
||||
.ACLK(aclk),
|
||||
.ARESET_N(aresetn),
|
||||
.ACLKEN(aclken)
|
||||
);
|
||||
|
||||
|
||||
//synthesis translate_off
|
||||
initial begin
|
||||
$display("XilinxAXIVIP: Found at Path: %m");
|
||||
end
|
||||
|
||||
//set IF mode to be in the correct mode according to C_AXI_INTERFACE_MODE,Default is monitor mode
|
||||
generate
|
||||
initial begin
|
||||
if(C_AXI_INTERFACE_MODE ==0) begin
|
||||
IF.set_intf_master;
|
||||
end else if(C_AXI_INTERFACE_MODE ==2) begin
|
||||
IF.set_intf_slave;
|
||||
end else if(C_AXI_INTERFACE_MODE ==1) begin
|
||||
$display("This AXI VIP is in passthrough mode");
|
||||
end else begin
|
||||
$fatal(0,"This AXI VIP's mode is out of range");
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
/*
|
||||
Function: set_passthrough_mode
|
||||
Sets AXI VIP passthrough into run time passthrough mode
|
||||
*/
|
||||
function void set_passthrough_mode();
|
||||
if (C_AXI_INTERFACE_MODE == 1) begin
|
||||
runtime_master = 0;
|
||||
runtime_slave = 0;
|
||||
IF.set_intf_monitor();
|
||||
end else begin
|
||||
$fatal(0,"XilinxAXIVIP: VIP was not initially configured as Pass-through. Cannot change mode.Delete non-Passthrough VIP's API call of set_passthrough_mode in the testbench. Refer PG267 section about Useful Coding Guidelines and Example for how to use master/slave/passthrough VIP");
|
||||
end
|
||||
endfunction: set_passthrough_mode
|
||||
|
||||
/*
|
||||
Function: set_master_mode
|
||||
Sets AXI VIP passthrough into run time master mode
|
||||
*/
|
||||
function void set_master_mode();
|
||||
if (C_AXI_INTERFACE_MODE == 1) begin
|
||||
runtime_master = 1;
|
||||
runtime_slave = 0;
|
||||
IF.set_intf_master();
|
||||
end else begin
|
||||
$fatal(0,"XilinxAXIVIP: VIP was not initially configured as Pass-through. Cannot change mode.Delete non-Passthrough VIP's API call of set_master_mode in the testbench .Refer PG267 section about Useful Coding Guidelines and Example for how to use master/slave/passthrough VIP ");
|
||||
end
|
||||
endfunction : set_master_mode
|
||||
|
||||
/*
|
||||
Function: set_slave_mode
|
||||
Sets AXI VIP passthrough into run time slave mode
|
||||
*/
|
||||
function void set_slave_mode();
|
||||
if (C_AXI_INTERFACE_MODE == 1) begin
|
||||
runtime_master = 0;
|
||||
runtime_slave = 1;
|
||||
IF.set_intf_slave();
|
||||
end else begin
|
||||
$fatal(0,"XilinxAXIVIP: VIP was not initially configured as Pass-through. Cannot change mode.Delete non-Passthrough VIP's API call of set_slave_mode in the testbench.Refer PG267 section about Useful Coding Guidelines and Example for how to use master/slave/passthrough VIP");
|
||||
end
|
||||
endfunction : set_slave_mode
|
||||
|
||||
/*
|
||||
Function: set_xilinx_slave_ready_check
|
||||
Sets xilinx_slave_ready_check_enable of IF to be 1
|
||||
*/
|
||||
function void set_xilinx_slave_ready_check();
|
||||
IF.xilinx_slave_ready_check_enable = 1;
|
||||
endfunction
|
||||
|
||||
/*
|
||||
Function: clr_xilinx_slave_ready_check
|
||||
Sets xilinx_slave_ready_check_enable of IF to be 0
|
||||
*/
|
||||
function void clr_xilinx_slave_ready_check();
|
||||
IF.xilinx_slave_ready_check_enable = 0;
|
||||
endfunction
|
||||
|
||||
/*
|
||||
Function: set_max_aw_wait_cycles (not available in VIVADO Simulator)
|
||||
Sets max_aw_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function void set_max_aw_wait_cycles(input integer unsigned new_num);
|
||||
IF.PC.max_aw_wait_cycles = new_num;
|
||||
endfunction : set_max_aw_wait_cycles
|
||||
|
||||
/*
|
||||
Function: set_max_ar_wait_cycles (not available in VIVADO Simulator)
|
||||
Sets max_ar_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function void set_max_ar_wait_cycles(input integer unsigned new_num);
|
||||
IF.PC.max_ar_wait_cycles = new_num;
|
||||
endfunction : set_max_ar_wait_cycles
|
||||
|
||||
/*
|
||||
Function: set_max_r_wait_cycles (not available in VIVADO Simulator)
|
||||
Sets max_r_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function void set_max_r_wait_cycles(input integer unsigned new_num);
|
||||
IF.PC.max_r_wait_cycles = new_num;
|
||||
endfunction : set_max_r_wait_cycles
|
||||
|
||||
/*
|
||||
Function: set_max_b_wait_cycles (not available in VIVADO Simulator)
|
||||
Sets max_b_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function void set_max_b_wait_cycles(input integer unsigned new_num);
|
||||
IF.PC.max_b_wait_cycles = new_num;
|
||||
endfunction : set_max_b_wait_cycles
|
||||
|
||||
/*
|
||||
Function: set_max_w_wait_cycles (not available in VIVADO Simulator)
|
||||
Sets max_w_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function void set_max_w_wait_cycles(input integer unsigned new_num);
|
||||
IF.PC.max_w_wait_cycles = new_num;
|
||||
endfunction : set_max_w_wait_cycles
|
||||
|
||||
/*
|
||||
Function: set_max_wlast_wait_cycles (not available in VIVADO Simulator)
|
||||
Sets max_wlast_to_awvalid_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function void set_max_wlast_wait_cycles(input integer unsigned new_num);
|
||||
IF.PC.max_wlast_to_awvalid_wait_cycles = new_num;
|
||||
endfunction : set_max_wlast_wait_cycles
|
||||
|
||||
/*
|
||||
Function: set_max_rtransfer_wait_cycles (not available in VIVADO Simulator)
|
||||
Sets max_rtransfer_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function void set_max_rtransfers_wait_cycles(input integer unsigned new_num);
|
||||
IF.PC.max_rtransfers_wait_cycles = new_num;
|
||||
endfunction : set_max_rtransfers_wait_cycles
|
||||
|
||||
/*
|
||||
Function: set_max_wtransfer_wait_cycles (not available in VIVADO Simulator)
|
||||
Sets max_wtransfer_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function void set_max_wtransfers_wait_cycles(input integer unsigned new_num);
|
||||
IF.PC.max_wtransfers_wait_cycles = new_num;
|
||||
endfunction : set_max_wtransfers_wait_cycles
|
||||
|
||||
/*
|
||||
Function: set_max_wlcmd_wait_cycles (not available in VIVADO Simulator)
|
||||
Sets max_wlcmd_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function void set_max_wlcmd_wait_cycles(input integer unsigned new_num);
|
||||
IF.PC.max_wlcmd_wait_cycles = new_num;
|
||||
endfunction : set_max_wlcmd_wait_cycles
|
||||
|
||||
/*
|
||||
Function: get_max_aw_wait_cycles (not available in VIVADO Simulator)
|
||||
Returns max_aw_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function integer unsigned get_max_aw_wait_cycles();
|
||||
return(IF.PC.max_aw_wait_cycles);
|
||||
endfunction : get_max_aw_wait_cycles
|
||||
|
||||
/*
|
||||
Function: get_max_ar_wait_cycles (not available in VIVADO Simulator)
|
||||
Returns max_ar_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function integer unsigned get_max_ar_wait_cycles();
|
||||
return(IF.PC.max_ar_wait_cycles);
|
||||
endfunction : get_max_ar_wait_cycles
|
||||
|
||||
/*
|
||||
Function: get_max_r_wait_cycles (not available in VIVADO Simulator)
|
||||
Returns max_r_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function integer unsigned get_max_r_wait_cycles();
|
||||
return(IF.PC.max_r_wait_cycles);
|
||||
endfunction : get_max_r_wait_cycles
|
||||
|
||||
/*
|
||||
Function: get_max_b_wait_cycles (not available in VIVADO Simulator)
|
||||
Returns max_b_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function integer unsigned get_max_b_wait_cycles();
|
||||
return(IF.PC.max_b_wait_cycles);
|
||||
endfunction : get_max_b_wait_cycles
|
||||
|
||||
/*
|
||||
Function: get_max_w_wait_cycles (not available in VIVADO Simulator)
|
||||
Returns max_w_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function integer unsigned get_max_w_wait_cycles();
|
||||
return(IF.PC.max_w_wait_cycles);
|
||||
endfunction :get_max_w_wait_cycles
|
||||
|
||||
/*
|
||||
Function: get_max_wlast_wait_cycles (not available in VIVADO Simulator)
|
||||
Returns max_wlast_to_awvalid_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function integer unsigned get_max_wlast_wait_cycles();
|
||||
return(IF.PC.max_wlast_to_awvalid_wait_cycles);
|
||||
endfunction :get_max_wlast_wait_cycles
|
||||
|
||||
/*
|
||||
Function: get_max_rtransfer_wait_cycles (not available in VIVADO Simulator)
|
||||
Returns max_rtransfer_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function integer unsigned get_max_rtransfers_wait_cycles();
|
||||
return(IF.PC.max_rtransfers_wait_cycles);
|
||||
endfunction :get_max_rtransfers_wait_cycles
|
||||
|
||||
/*
|
||||
Function: get_max_wtransfer_wait_cycles (not available in VIVADO Simulator)
|
||||
Returns max_wtransfer_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function integer unsigned get_max_wtransfers_wait_cycles();
|
||||
return(IF.PC.max_wtransfers_wait_cycles);
|
||||
endfunction :get_max_wtransfers_wait_cycles
|
||||
|
||||
/*
|
||||
Function: get_max_wlcmd_wait_cycles (not available in VIVADO Simulator)
|
||||
Returns max_wlcmd_wait_cycles of PC(ARM Protocol Checker)
|
||||
*/
|
||||
function integer unsigned get_max_wlcmd_wait_cycles();
|
||||
return(IF.PC.max_wlcmd_wait_cycles);
|
||||
endfunction :get_max_wlcmd_wait_cycles
|
||||
|
||||
/*
|
||||
Function: set_fatal_to_warnings (not available in VIVADO Simulator)
|
||||
Sets fatal_to_warnings of PC(ARM Protocol Checker) to be 1
|
||||
*/
|
||||
function void set_fatal_to_warnings();
|
||||
IF.PC.fatal_to_warnings = 1;
|
||||
endfunction : set_fatal_to_warnings
|
||||
|
||||
/*
|
||||
Function: clr_fatal_to_warnings (not available in VIVADO Simulator)
|
||||
Sets fatal_to_warnings of PC(ARM Protocol Checker) to be 0
|
||||
*/
|
||||
function void clr_fatal_to_warnings();
|
||||
IF.PC.fatal_to_warnings = 0;
|
||||
endfunction : clr_fatal_to_warnings
|
||||
//synthesis translate_on
|
||||
|
||||
endmodule // axi_vip_v1_1_5_top
|
||||
|
||||
|
||||
+138
@@ -0,0 +1,138 @@
|
||||
// (c) Copyright 2012 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//-----------------------------------------------------------------------------
|
||||
//
|
||||
// Generic Functions used by AXI Infrastructure Modules
|
||||
//
|
||||
// Verilog-standard: Verilog 2001
|
||||
//--------------------------------------------------------------------------
|
||||
// Global Parameters:
|
||||
//
|
||||
// Functions:
|
||||
//
|
||||
// Tasks:
|
||||
//--------------------------------------------------------------------------
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// BEGIN Global Parameters
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
localparam G_AXI_AWADDR_INDEX = 0;
|
||||
localparam G_AXI_AWADDR_WIDTH = C_AXI_ADDR_WIDTH;
|
||||
localparam G_AXI_AWPROT_INDEX = G_AXI_AWADDR_INDEX + G_AXI_AWADDR_WIDTH;
|
||||
localparam G_AXI_AWPROT_WIDTH = 3;
|
||||
localparam G_AXI_AWSIZE_INDEX = G_AXI_AWPROT_INDEX + G_AXI_AWPROT_WIDTH;
|
||||
localparam G_AXI_AWSIZE_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 3;
|
||||
localparam G_AXI_AWBURST_INDEX = G_AXI_AWSIZE_INDEX + G_AXI_AWSIZE_WIDTH;
|
||||
localparam G_AXI_AWBURST_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 2;
|
||||
localparam G_AXI_AWCACHE_INDEX = G_AXI_AWBURST_INDEX + G_AXI_AWBURST_WIDTH;
|
||||
localparam G_AXI_AWCACHE_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 4;
|
||||
localparam G_AXI_AWLEN_INDEX = G_AXI_AWCACHE_INDEX + G_AXI_AWCACHE_WIDTH;
|
||||
localparam G_AXI_AWLEN_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_PROTOCOL == 1) ? 4 : 8;
|
||||
localparam G_AXI_AWLOCK_INDEX = G_AXI_AWLEN_INDEX + G_AXI_AWLEN_WIDTH;
|
||||
localparam G_AXI_AWLOCK_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_PROTOCOL == 1) ? 2 : 1;
|
||||
localparam G_AXI_AWID_INDEX = G_AXI_AWLOCK_INDEX + G_AXI_AWLOCK_WIDTH;
|
||||
localparam G_AXI_AWID_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : C_AXI_ID_WIDTH;
|
||||
localparam G_AXI_AWQOS_INDEX = G_AXI_AWID_INDEX + G_AXI_AWID_WIDTH;
|
||||
localparam G_AXI_AWQOS_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 4;
|
||||
localparam G_AXI_AWREGION_INDEX = G_AXI_AWQOS_INDEX + G_AXI_AWQOS_WIDTH;
|
||||
localparam G_AXI_AWREGION_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_REGION_SIGNALS == 0) ? 0 : 4;
|
||||
localparam G_AXI_AWUSER_INDEX = G_AXI_AWREGION_INDEX + G_AXI_AWREGION_WIDTH;
|
||||
localparam G_AXI_AWUSER_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_USER_SIGNALS == 0) ? 0 : C_AXI_AWUSER_WIDTH;
|
||||
localparam G_AXI_AWPAYLOAD_WIDTH = G_AXI_AWUSER_INDEX + G_AXI_AWUSER_WIDTH;
|
||||
localparam G_AXI_ARADDR_INDEX = 0;
|
||||
localparam G_AXI_ARADDR_WIDTH = C_AXI_ADDR_WIDTH;
|
||||
localparam G_AXI_ARPROT_INDEX = G_AXI_ARADDR_INDEX + G_AXI_ARADDR_WIDTH;
|
||||
localparam G_AXI_ARPROT_WIDTH = 3;
|
||||
localparam G_AXI_ARSIZE_INDEX = G_AXI_ARPROT_INDEX + G_AXI_ARPROT_WIDTH;
|
||||
localparam G_AXI_ARSIZE_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 3;
|
||||
localparam G_AXI_ARBURST_INDEX = G_AXI_ARSIZE_INDEX + G_AXI_ARSIZE_WIDTH;
|
||||
localparam G_AXI_ARBURST_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 2;
|
||||
localparam G_AXI_ARCACHE_INDEX = G_AXI_ARBURST_INDEX + G_AXI_ARBURST_WIDTH;
|
||||
localparam G_AXI_ARCACHE_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 4;
|
||||
localparam G_AXI_ARLEN_INDEX = G_AXI_ARCACHE_INDEX + G_AXI_ARCACHE_WIDTH;
|
||||
localparam G_AXI_ARLEN_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_PROTOCOL == 1) ? 4 : 8;
|
||||
localparam G_AXI_ARLOCK_INDEX = G_AXI_ARLEN_INDEX + G_AXI_ARLEN_WIDTH;
|
||||
localparam G_AXI_ARLOCK_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_PROTOCOL == 1) ? 2 : 1;
|
||||
localparam G_AXI_ARID_INDEX = G_AXI_ARLOCK_INDEX + G_AXI_ARLOCK_WIDTH;
|
||||
localparam G_AXI_ARID_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : C_AXI_ID_WIDTH;
|
||||
localparam G_AXI_ARQOS_INDEX = G_AXI_ARID_INDEX + G_AXI_ARID_WIDTH;
|
||||
localparam G_AXI_ARQOS_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 4;
|
||||
localparam G_AXI_ARREGION_INDEX = G_AXI_ARQOS_INDEX + G_AXI_ARQOS_WIDTH;
|
||||
localparam G_AXI_ARREGION_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_REGION_SIGNALS == 0) ? 0 : 4;
|
||||
localparam G_AXI_ARUSER_INDEX = G_AXI_ARREGION_INDEX + G_AXI_ARREGION_WIDTH;
|
||||
localparam G_AXI_ARUSER_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_USER_SIGNALS == 0) ? 0 : C_AXI_ARUSER_WIDTH;
|
||||
localparam G_AXI_ARPAYLOAD_WIDTH = G_AXI_ARUSER_INDEX + G_AXI_ARUSER_WIDTH;
|
||||
// Write channel widths
|
||||
localparam G_AXI_WDATA_INDEX = 0;
|
||||
localparam G_AXI_WDATA_WIDTH = C_AXI_DATA_WIDTH;
|
||||
localparam G_AXI_WSTRB_INDEX = G_AXI_WDATA_INDEX + G_AXI_WDATA_WIDTH;
|
||||
localparam G_AXI_WSTRB_WIDTH = C_AXI_DATA_WIDTH / 8;
|
||||
localparam G_AXI_WLAST_INDEX = G_AXI_WSTRB_INDEX + G_AXI_WSTRB_WIDTH;
|
||||
localparam G_AXI_WLAST_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 1;
|
||||
localparam G_AXI_WID_INDEX = G_AXI_WLAST_INDEX + G_AXI_WLAST_WIDTH;
|
||||
localparam G_AXI_WID_WIDTH = (C_AXI_PROTOCOL != 1) ? 0 : C_AXI_ID_WIDTH;
|
||||
localparam G_AXI_WUSER_INDEX = G_AXI_WID_INDEX + G_AXI_WID_WIDTH;
|
||||
localparam G_AXI_WUSER_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_USER_SIGNALS == 0) ? 0 : C_AXI_WUSER_WIDTH;
|
||||
localparam G_AXI_WPAYLOAD_WIDTH = G_AXI_WUSER_INDEX + G_AXI_WUSER_WIDTH;
|
||||
// Write Response channel Widths
|
||||
localparam G_AXI_BRESP_INDEX = 0;
|
||||
localparam G_AXI_BRESP_WIDTH = 2;
|
||||
localparam G_AXI_BID_INDEX = G_AXI_BRESP_INDEX + G_AXI_BRESP_WIDTH;
|
||||
localparam G_AXI_BID_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : C_AXI_ID_WIDTH;
|
||||
localparam G_AXI_BUSER_INDEX = G_AXI_BID_INDEX + G_AXI_BID_WIDTH;
|
||||
localparam G_AXI_BUSER_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_USER_SIGNALS == 0) ? 0 : C_AXI_BUSER_WIDTH;
|
||||
localparam G_AXI_BPAYLOAD_WIDTH = G_AXI_BUSER_INDEX + G_AXI_BUSER_WIDTH;
|
||||
// Read channel widths
|
||||
localparam G_AXI_RDATA_INDEX = 0;
|
||||
localparam G_AXI_RDATA_WIDTH = C_AXI_DATA_WIDTH;
|
||||
localparam G_AXI_RRESP_INDEX = G_AXI_RDATA_INDEX + G_AXI_RDATA_WIDTH;
|
||||
localparam G_AXI_RRESP_WIDTH = 2;
|
||||
localparam G_AXI_RLAST_INDEX = G_AXI_RRESP_INDEX + G_AXI_RRESP_WIDTH;
|
||||
localparam G_AXI_RLAST_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : 1;
|
||||
localparam G_AXI_RID_INDEX = G_AXI_RLAST_INDEX + G_AXI_RLAST_WIDTH;
|
||||
localparam G_AXI_RID_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : C_AXI_ID_WIDTH;
|
||||
localparam G_AXI_RUSER_INDEX = G_AXI_RID_INDEX + G_AXI_RID_WIDTH;
|
||||
localparam G_AXI_RUSER_WIDTH = (C_AXI_PROTOCOL == 2) ? 0 : (C_AXI_SUPPORTS_USER_SIGNALS == 0) ? 0 : C_AXI_RUSER_WIDTH;
|
||||
localparam G_AXI_RPAYLOAD_WIDTH = G_AXI_RUSER_INDEX + G_AXI_RUSER_WIDTH;
|
||||
+670
@@ -0,0 +1,670 @@
|
||||
// (c) Copyright 2012 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//-----------------------------------------------------------------------------
|
||||
//
|
||||
// axis to vector
|
||||
// A generic module to merge all axi signals into one signal called payload.
|
||||
// This is strictly wires, so no clk, reset, aclken, valid/ready are required.
|
||||
//
|
||||
// Verilog-standard: Verilog 2001
|
||||
//--------------------------------------------------------------------------
|
||||
//
|
||||
|
||||
`timescale 1ps/1ps
|
||||
`default_nettype none
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings="yes" *)
|
||||
module axi_infrastructure_v1_1_0_axi2vector #
|
||||
(
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Parameter Definitions
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
parameter integer C_AXI_PROTOCOL = 0,
|
||||
parameter integer C_AXI_ID_WIDTH = 4,
|
||||
parameter integer C_AXI_ADDR_WIDTH = 32,
|
||||
parameter integer C_AXI_DATA_WIDTH = 32,
|
||||
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
|
||||
parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,
|
||||
parameter integer C_AXI_AWUSER_WIDTH = 1,
|
||||
parameter integer C_AXI_WUSER_WIDTH = 1,
|
||||
parameter integer C_AXI_BUSER_WIDTH = 1,
|
||||
parameter integer C_AXI_ARUSER_WIDTH = 1,
|
||||
parameter integer C_AXI_RUSER_WIDTH = 1,
|
||||
parameter integer C_AWPAYLOAD_WIDTH = 61,
|
||||
parameter integer C_WPAYLOAD_WIDTH = 73,
|
||||
parameter integer C_BPAYLOAD_WIDTH = 6,
|
||||
parameter integer C_ARPAYLOAD_WIDTH = 61,
|
||||
parameter integer C_RPAYLOAD_WIDTH = 69
|
||||
)
|
||||
(
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Port Declarations
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Slave Interface Write Address Ports
|
||||
input wire [C_AXI_ID_WIDTH-1:0] s_axi_awid,
|
||||
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
|
||||
input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,
|
||||
input wire [3-1:0] s_axi_awsize,
|
||||
input wire [2-1:0] s_axi_awburst,
|
||||
input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,
|
||||
input wire [4-1:0] s_axi_awcache,
|
||||
input wire [3-1:0] s_axi_awprot,
|
||||
input wire [4-1:0] s_axi_awregion,
|
||||
input wire [4-1:0] s_axi_awqos,
|
||||
input wire [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,
|
||||
|
||||
// Slave Interface Write Data Ports
|
||||
input wire [C_AXI_ID_WIDTH-1:0] s_axi_wid,
|
||||
input wire [C_AXI_DATA_WIDTH-1:0] s_axi_wdata,
|
||||
input wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
|
||||
input wire s_axi_wlast,
|
||||
input wire [C_AXI_WUSER_WIDTH-1:0] s_axi_wuser,
|
||||
|
||||
// Slave Interface Write Response Ports
|
||||
output wire [C_AXI_ID_WIDTH-1:0] s_axi_bid,
|
||||
output wire [2-1:0] s_axi_bresp,
|
||||
output wire [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,
|
||||
|
||||
// Slave Interface Read Address Ports
|
||||
input wire [C_AXI_ID_WIDTH-1:0] s_axi_arid,
|
||||
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
|
||||
input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,
|
||||
input wire [3-1:0] s_axi_arsize,
|
||||
input wire [2-1:0] s_axi_arburst,
|
||||
input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,
|
||||
input wire [4-1:0] s_axi_arcache,
|
||||
input wire [3-1:0] s_axi_arprot,
|
||||
input wire [4-1:0] s_axi_arregion,
|
||||
input wire [4-1:0] s_axi_arqos,
|
||||
input wire [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,
|
||||
|
||||
// Slave Interface Read Data Ports
|
||||
output wire [C_AXI_ID_WIDTH-1:0] s_axi_rid,
|
||||
output wire [C_AXI_DATA_WIDTH-1:0] s_axi_rdata,
|
||||
output wire [2-1:0] s_axi_rresp,
|
||||
output wire s_axi_rlast,
|
||||
output wire [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,
|
||||
|
||||
// payloads
|
||||
output wire [C_AWPAYLOAD_WIDTH-1:0] s_awpayload,
|
||||
output wire [C_WPAYLOAD_WIDTH-1:0] s_wpayload,
|
||||
input wire [C_BPAYLOAD_WIDTH-1:0] s_bpayload,
|
||||
output wire [C_ARPAYLOAD_WIDTH-1:0] s_arpayload,
|
||||
input wire [C_RPAYLOAD_WIDTH-1:0] s_rpayload
|
||||
);
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Functions
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
`include "axi_infrastructure_v1_1_0.vh"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Local parameters
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Wires/Reg declarations
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// BEGIN RTL
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// AXI4, AXI4LITE, AXI3 packing
|
||||
assign s_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH] = s_axi_awaddr;
|
||||
assign s_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH] = s_axi_awprot;
|
||||
|
||||
assign s_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH] = s_axi_wdata;
|
||||
assign s_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH] = s_axi_wstrb;
|
||||
|
||||
assign s_axi_bresp = s_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH];
|
||||
|
||||
assign s_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH] = s_axi_araddr;
|
||||
assign s_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH] = s_axi_arprot;
|
||||
|
||||
assign s_axi_rdata = s_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH];
|
||||
assign s_axi_rresp = s_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH];
|
||||
|
||||
generate
|
||||
if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing
|
||||
assign s_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] = s_axi_awsize;
|
||||
assign s_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH] = s_axi_awburst;
|
||||
assign s_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH] = s_axi_awcache;
|
||||
assign s_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] = s_axi_awlen;
|
||||
assign s_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] = s_axi_awlock;
|
||||
assign s_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] = s_axi_awid;
|
||||
assign s_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] = s_axi_awqos;
|
||||
|
||||
assign s_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] = s_axi_wlast;
|
||||
if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing
|
||||
assign s_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] = s_axi_wid;
|
||||
end
|
||||
else begin : gen_no_axi3_wid_packing
|
||||
end
|
||||
|
||||
assign s_axi_bid = s_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH];
|
||||
|
||||
assign s_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] = s_axi_arsize;
|
||||
assign s_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH] = s_axi_arburst;
|
||||
assign s_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH] = s_axi_arcache;
|
||||
assign s_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] = s_axi_arlen;
|
||||
assign s_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] = s_axi_arlock;
|
||||
assign s_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] = s_axi_arid;
|
||||
assign s_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] = s_axi_arqos;
|
||||
|
||||
assign s_axi_rlast = s_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH];
|
||||
assign s_axi_rid = s_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH];
|
||||
|
||||
if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals
|
||||
assign s_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH] = s_axi_awregion;
|
||||
assign s_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH] = s_axi_arregion;
|
||||
end
|
||||
else begin : gen_no_region_signals
|
||||
end
|
||||
if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals
|
||||
assign s_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH] = s_axi_awuser;
|
||||
assign s_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] = s_axi_wuser;
|
||||
assign s_axi_buser = s_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH];
|
||||
assign s_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH] = s_axi_aruser;
|
||||
assign s_axi_ruser = s_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH];
|
||||
end
|
||||
else begin : gen_no_user_signals
|
||||
assign s_axi_buser = 'b0;
|
||||
assign s_axi_ruser = 'b0;
|
||||
end
|
||||
end
|
||||
else begin : gen_axi4lite_packing
|
||||
assign s_axi_bid = 'b0;
|
||||
assign s_axi_buser = 'b0;
|
||||
|
||||
assign s_axi_rlast = 1'b1;
|
||||
assign s_axi_rid = 'b0;
|
||||
assign s_axi_ruser = 'b0;
|
||||
end
|
||||
endgenerate
|
||||
endmodule
|
||||
|
||||
`default_nettype wire
|
||||
|
||||
|
||||
// (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//-----------------------------------------------------------------------------
|
||||
// Description: SRL based FIFO for AXIS/AXI Channels.
|
||||
//--------------------------------------------------------------------------
|
||||
|
||||
|
||||
`timescale 1ps/1ps
|
||||
`default_nettype none
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings="yes" *)
|
||||
module axi_infrastructure_v1_1_0_axic_srl_fifo #(
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Parameter Definitions
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
parameter C_FAMILY = "virtex7",
|
||||
parameter integer C_PAYLOAD_WIDTH = 1,
|
||||
parameter integer C_FIFO_DEPTH = 16 // Range: 4-16.
|
||||
)
|
||||
(
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Port Declarations
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
input wire aclk, // Clock
|
||||
input wire aresetn, // Reset
|
||||
input wire [C_PAYLOAD_WIDTH-1:0] s_payload, // Input data
|
||||
input wire s_valid, // Input data valid
|
||||
output reg s_ready, // Input data ready
|
||||
output wire [C_PAYLOAD_WIDTH-1:0] m_payload, // Output data
|
||||
output reg m_valid, // Output data valid
|
||||
input wire m_ready // Output data ready
|
||||
);
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Functions
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// ceiling logb2
|
||||
function integer f_clogb2 (input integer size);
|
||||
integer s;
|
||||
begin
|
||||
s = size;
|
||||
s = s - 1;
|
||||
for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1)
|
||||
s = s >> 1;
|
||||
end
|
||||
endfunction // clogb2
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Local parameters
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
localparam integer LP_LOG_FIFO_DEPTH = f_clogb2(C_FIFO_DEPTH);
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Wires/Reg declarations
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
reg [LP_LOG_FIFO_DEPTH-1:0] fifo_index;
|
||||
wire [4-1:0] fifo_addr;
|
||||
wire push;
|
||||
wire pop ;
|
||||
reg areset_r1;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// BEGIN RTL
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
always @(posedge aclk) begin
|
||||
areset_r1 <= ~aresetn;
|
||||
end
|
||||
|
||||
always @(posedge aclk) begin
|
||||
if (~aresetn) begin
|
||||
fifo_index <= {LP_LOG_FIFO_DEPTH{1'b1}};
|
||||
end
|
||||
else begin
|
||||
fifo_index <= push & ~pop ? fifo_index + 1'b1 :
|
||||
~push & pop ? fifo_index - 1'b1 :
|
||||
fifo_index;
|
||||
end
|
||||
end
|
||||
|
||||
assign push = s_valid & s_ready;
|
||||
|
||||
always @(posedge aclk) begin
|
||||
if (~aresetn) begin
|
||||
s_ready <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
s_ready <= areset_r1 ? 1'b1 :
|
||||
push & ~pop && (fifo_index == (C_FIFO_DEPTH - 2'd2)) ? 1'b0 :
|
||||
~push & pop ? 1'b1 :
|
||||
s_ready;
|
||||
end
|
||||
end
|
||||
|
||||
assign pop = m_valid & m_ready;
|
||||
|
||||
always @(posedge aclk) begin
|
||||
if (~aresetn) begin
|
||||
m_valid <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
m_valid <= ~push & pop && (fifo_index == {LP_LOG_FIFO_DEPTH{1'b0}}) ? 1'b0 :
|
||||
push & ~pop ? 1'b1 :
|
||||
m_valid;
|
||||
end
|
||||
end
|
||||
|
||||
generate
|
||||
if (LP_LOG_FIFO_DEPTH < 4) begin : gen_pad_fifo_addr
|
||||
assign fifo_addr[0+:LP_LOG_FIFO_DEPTH] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];
|
||||
assign fifo_addr[LP_LOG_FIFO_DEPTH+:(4-LP_LOG_FIFO_DEPTH)] = {4-LP_LOG_FIFO_DEPTH{1'b0}};
|
||||
end
|
||||
else begin : gen_fifo_addr
|
||||
assign fifo_addr[LP_LOG_FIFO_DEPTH-1:0] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
||||
generate
|
||||
genvar i;
|
||||
for (i = 0; i < C_PAYLOAD_WIDTH; i = i + 1) begin : gen_data_bit
|
||||
SRL16E
|
||||
u_srl_fifo(
|
||||
.Q ( m_payload[i] ) ,
|
||||
.A0 ( fifo_addr[0] ) ,
|
||||
.A1 ( fifo_addr[1] ) ,
|
||||
.A2 ( fifo_addr[2] ) ,
|
||||
.A3 ( fifo_addr[3] ) ,
|
||||
.CE ( push ) ,
|
||||
.CLK ( aclk ) ,
|
||||
.D ( s_payload[i] )
|
||||
);
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
`default_nettype wire
|
||||
|
||||
|
||||
// (c) Copyright 2012 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//-----------------------------------------------------------------------------
|
||||
//
|
||||
// axi to vector
|
||||
// A generic module to merge all axi signals into one signal called payload.
|
||||
// This is strictly wires, so no clk, reset, aclken, valid/ready are required.
|
||||
//
|
||||
// Verilog-standard: Verilog 2001
|
||||
//--------------------------------------------------------------------------
|
||||
//
|
||||
|
||||
`timescale 1ps/1ps
|
||||
`default_nettype none
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings="yes" *)
|
||||
module axi_infrastructure_v1_1_0_vector2axi #
|
||||
(
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Parameter Definitions
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
parameter integer C_AXI_PROTOCOL = 0,
|
||||
parameter integer C_AXI_ID_WIDTH = 4,
|
||||
parameter integer C_AXI_ADDR_WIDTH = 32,
|
||||
parameter integer C_AXI_DATA_WIDTH = 32,
|
||||
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
|
||||
parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,
|
||||
parameter integer C_AXI_AWUSER_WIDTH = 1,
|
||||
parameter integer C_AXI_WUSER_WIDTH = 1,
|
||||
parameter integer C_AXI_BUSER_WIDTH = 1,
|
||||
parameter integer C_AXI_ARUSER_WIDTH = 1,
|
||||
parameter integer C_AXI_RUSER_WIDTH = 1,
|
||||
parameter integer C_AWPAYLOAD_WIDTH = 61,
|
||||
parameter integer C_WPAYLOAD_WIDTH = 73,
|
||||
parameter integer C_BPAYLOAD_WIDTH = 6,
|
||||
parameter integer C_ARPAYLOAD_WIDTH = 61,
|
||||
parameter integer C_RPAYLOAD_WIDTH = 69
|
||||
)
|
||||
(
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Port Declarations
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Slave Interface Write Address Ports
|
||||
output wire [C_AXI_ID_WIDTH-1:0] m_axi_awid,
|
||||
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
|
||||
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
|
||||
output wire [3-1:0] m_axi_awsize,
|
||||
output wire [2-1:0] m_axi_awburst,
|
||||
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
|
||||
output wire [4-1:0] m_axi_awcache,
|
||||
output wire [3-1:0] m_axi_awprot,
|
||||
output wire [4-1:0] m_axi_awregion,
|
||||
output wire [4-1:0] m_axi_awqos,
|
||||
output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
|
||||
|
||||
// Slave Interface Write Data Ports
|
||||
output wire [C_AXI_ID_WIDTH-1:0] m_axi_wid,
|
||||
output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
|
||||
output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
|
||||
output wire m_axi_wlast,
|
||||
output wire [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
|
||||
|
||||
// Slave Interface Write Response Ports
|
||||
input wire [C_AXI_ID_WIDTH-1:0] m_axi_bid,
|
||||
input wire [2-1:0] m_axi_bresp,
|
||||
input wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
|
||||
|
||||
// Slave Interface Read Address Ports
|
||||
output wire [C_AXI_ID_WIDTH-1:0] m_axi_arid,
|
||||
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
|
||||
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
|
||||
output wire [3-1:0] m_axi_arsize,
|
||||
output wire [2-1:0] m_axi_arburst,
|
||||
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
|
||||
output wire [4-1:0] m_axi_arcache,
|
||||
output wire [3-1:0] m_axi_arprot,
|
||||
output wire [4-1:0] m_axi_arregion,
|
||||
output wire [4-1:0] m_axi_arqos,
|
||||
output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
|
||||
|
||||
// Slave Interface Read Data Ports
|
||||
input wire [C_AXI_ID_WIDTH-1:0] m_axi_rid,
|
||||
input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
|
||||
input wire [2-1:0] m_axi_rresp,
|
||||
input wire m_axi_rlast,
|
||||
input wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
|
||||
|
||||
// payloads
|
||||
input wire [C_AWPAYLOAD_WIDTH-1:0] m_awpayload,
|
||||
input wire [C_WPAYLOAD_WIDTH-1:0] m_wpayload,
|
||||
output wire [C_BPAYLOAD_WIDTH-1:0] m_bpayload,
|
||||
input wire [C_ARPAYLOAD_WIDTH-1:0] m_arpayload,
|
||||
output wire [C_RPAYLOAD_WIDTH-1:0] m_rpayload
|
||||
);
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Functions
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
`include "axi_infrastructure_v1_1_0.vh"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Local parameters
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Wires/Reg declarations
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// BEGIN RTL
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// AXI4, AXI4LITE, AXI3 packing
|
||||
assign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];
|
||||
assign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];
|
||||
|
||||
assign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];
|
||||
assign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];
|
||||
|
||||
assign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;
|
||||
|
||||
assign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];
|
||||
assign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];
|
||||
|
||||
assign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;
|
||||
assign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;
|
||||
|
||||
generate
|
||||
if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing
|
||||
assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] ;
|
||||
assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];
|
||||
assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];
|
||||
assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] ;
|
||||
assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] ;
|
||||
assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] ;
|
||||
assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] ;
|
||||
|
||||
assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] ;
|
||||
if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing
|
||||
assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] ;
|
||||
end
|
||||
else begin : gen_no_axi3_wid_packing
|
||||
assign m_axi_wid = 1'b0;
|
||||
end
|
||||
|
||||
assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;
|
||||
|
||||
assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] ;
|
||||
assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];
|
||||
assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];
|
||||
assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] ;
|
||||
assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] ;
|
||||
assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] ;
|
||||
assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] ;
|
||||
|
||||
assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;
|
||||
assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid ;
|
||||
|
||||
if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals
|
||||
assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];
|
||||
assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];
|
||||
end
|
||||
else begin : gen_no_region_signals
|
||||
assign m_axi_awregion = 'b0;
|
||||
assign m_axi_arregion = 'b0;
|
||||
end
|
||||
if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals
|
||||
assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];
|
||||
assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] ;
|
||||
assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser ;
|
||||
assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];
|
||||
assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser ;
|
||||
end
|
||||
else begin : gen_no_user_signals
|
||||
assign m_axi_awuser = 'b0;
|
||||
assign m_axi_wuser = 'b0;
|
||||
assign m_axi_aruser = 'b0;
|
||||
end
|
||||
end
|
||||
else begin : gen_axi4lite_packing
|
||||
assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
|
||||
assign m_axi_awburst = 'b0;
|
||||
assign m_axi_awcache = 'b0;
|
||||
assign m_axi_awlen = 'b0;
|
||||
assign m_axi_awlock = 'b0;
|
||||
assign m_axi_awid = 'b0;
|
||||
assign m_axi_awqos = 'b0;
|
||||
|
||||
assign m_axi_wlast = 1'b1;
|
||||
assign m_axi_wid = 'b0;
|
||||
|
||||
|
||||
assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
|
||||
assign m_axi_arburst = 'b0;
|
||||
assign m_axi_arcache = 'b0;
|
||||
assign m_axi_arlen = 'b0;
|
||||
assign m_axi_arlock = 'b0;
|
||||
assign m_axi_arid = 'b0;
|
||||
assign m_axi_arqos = 'b0;
|
||||
|
||||
assign m_axi_awregion = 'b0;
|
||||
assign m_axi_arregion = 'b0;
|
||||
|
||||
assign m_axi_awuser = 'b0;
|
||||
assign m_axi_wuser = 'b0;
|
||||
assign m_axi_aruser = 'b0;
|
||||
end
|
||||
endgenerate
|
||||
endmodule
|
||||
|
||||
`default_nettype wire
|
||||
|
||||
|
||||
+1263
File diff suppressed because it is too large
Load Diff
+1412
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user