first commit after restructuring

2023-04-13 13:33:41 +08:00
commit 3c2cd0ba29
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+//Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+//--------------------------------------------------------------------------------
+//Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep  4 09:45:24 MDT 2019
+//Date        : Sun Mar 19 00:32:52 2023
+//Host        : JOSH-ASUS-Z690 running 64-bit major release  (build 9200)
+//Command     : generate_target system_bd_wrapper.bd
+//Design      : system_bd_wrapper
+//Purpose     : IP block netlist
+//--------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+module system_bd_wrapper
+   (clk_25MHz,
+    gpio_i,
+    gpio_o,
+    ps_clk_25M,
+    spi_active,
+    spi_cs,
+    spi_sclk,
+    spi_sdi,
+    spi_sdo,
+    spi_sdo_t,
+    spi_three_wire);
+  input clk_25MHz;
+  input [31:0]gpio_i;
+  output [31:0]gpio_o;
+  output ps_clk_25M;
+  output spi_active;
+  output [2:0]spi_cs;
+  output spi_sclk;
+  input [0:0]spi_sdi;
+  output spi_sdo;
+  output spi_sdo_t;
+  output spi_three_wire;
+
+  wire clk_25MHz;
+  wire [31:0]gpio_i;
+  wire [31:0]gpio_o;
+  wire ps_clk_25M;
+  wire spi_active;
+  wire [2:0]spi_cs;
+  wire spi_sclk;
+  wire [0:0]spi_sdi;
+  wire spi_sdo;
+  wire spi_sdo_t;
+  wire spi_three_wire;
+
+  system_bd system_bd_i
+       (.clk_25MHz(clk_25MHz),
+        .gpio_i(gpio_i),
+        .gpio_o(gpio_o),
+        .ps_clk_25M(ps_clk_25M),
+        .spi_active(spi_active),
+        .spi_cs(spi_cs),
+        .spi_sclk(spi_sclk),
+        .spi_sdi(spi_sdi),
+        .spi_sdo(spi_sdo),
+        .spi_sdo_t(spi_sdo_t),
+        .spi_three_wire(spi_three_wire));
+endmodule