first commit after restructuring

projects/dl814_k7/common_ipi-bd/basic_driver_bd/ip/system_bd_axi_gpio_0/sim/system_bd_axi_gpio_0.vhd

@@ -0,0 +1,207 @@
+-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
+-- IP Revision: 21
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+LIBRARY axi_gpio_v2_0_21;
+USE axi_gpio_v2_0_21.axi_gpio;
+
+ENTITY system_bd_axi_gpio_0 IS
+  PORT (
+    s_axi_aclk : IN STD_LOGIC;
+    s_axi_aresetn : IN STD_LOGIC;
+    s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
+    s_axi_awvalid : IN STD_LOGIC;
+    s_axi_awready : OUT STD_LOGIC;
+    s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+    s_axi_wvalid : IN STD_LOGIC;
+    s_axi_wready : OUT STD_LOGIC;
+    s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+    s_axi_bvalid : OUT STD_LOGIC;
+    s_axi_bready : IN STD_LOGIC;
+    s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
+    s_axi_arvalid : IN STD_LOGIC;
+    s_axi_arready : OUT STD_LOGIC;
+    s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+    s_axi_rvalid : OUT STD_LOGIC;
+    s_axi_rready : IN STD_LOGIC;
+    gpio_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
+  );
+END system_bd_axi_gpio_0;
+
+ARCHITECTURE system_bd_axi_gpio_0_arch OF system_bd_axi_gpio_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_bd_axi_gpio_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT axi_gpio IS
+    GENERIC (
+      C_FAMILY : STRING;
+      C_S_AXI_ADDR_WIDTH : INTEGER;
+      C_S_AXI_DATA_WIDTH : INTEGER;
+      C_GPIO_WIDTH : INTEGER;
+      C_GPIO2_WIDTH : INTEGER;
+      C_ALL_INPUTS : INTEGER;
+      C_ALL_INPUTS_2 : INTEGER;
+      C_ALL_OUTPUTS : INTEGER;
+      C_ALL_OUTPUTS_2 : INTEGER;
+      C_INTERRUPT_PRESENT : INTEGER;
+      C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
+      C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
+      C_IS_DUAL : INTEGER;
+      C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
+      C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
+    );
+    PORT (
+      s_axi_aclk : IN STD_LOGIC;
+      s_axi_aresetn : IN STD_LOGIC;
+      s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
+      s_axi_awvalid : IN STD_LOGIC;
+      s_axi_awready : OUT STD_LOGIC;
+      s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      s_axi_wvalid : IN STD_LOGIC;
+      s_axi_wready : OUT STD_LOGIC;
+      s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      s_axi_bvalid : OUT STD_LOGIC;
+      s_axi_bready : IN STD_LOGIC;
+      s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
+      s_axi_arvalid : IN STD_LOGIC;
+      s_axi_arready : OUT STD_LOGIC;
+      s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      s_axi_rvalid : OUT STD_LOGIC;
+      s_axi_rready : IN STD_LOGIC;
+      ip2intc_irpt : OUT STD_LOGIC;
+      gpio_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      gpio_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      gpio_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+    );
+  END COMPONENT axi_gpio;
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF gpio2_io_i: SIGNAL IS "XIL_INTERFACENAME GPIO2, BOARD.ASSOCIATED_PARAM GPIO2_BOARD_INTERFACE";
+  ATTRIBUTE X_INTERFACE_INFO OF gpio2_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO2 TRI_I";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF gpio_io_o: SIGNAL IS "XIL_INTERFACENAME GPIO, BOARD.ASSOCIATED_PARAM GPIO_BOARD_INTERFACE";
+  ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 25000000, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1" & 
+", RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME S_AXI_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aclk: SIGNAL IS "XIL_INTERFACENAME S_AXI_ACLK, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 25000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
+BEGIN
+  U0 : axi_gpio
+    GENERIC MAP (
+      C_FAMILY => "kintex7",
+      C_S_AXI_ADDR_WIDTH => 9,
+      C_S_AXI_DATA_WIDTH => 32,
+      C_GPIO_WIDTH => 32,
+      C_GPIO2_WIDTH => 32,
+      C_ALL_INPUTS => 0,
+      C_ALL_INPUTS_2 => 1,
+      C_ALL_OUTPUTS => 1,
+      C_ALL_OUTPUTS_2 => 0,
+      C_INTERRUPT_PRESENT => 0,
+      C_DOUT_DEFAULT => X"FFFFFFFF",
+      C_TRI_DEFAULT => X"FFFFFFFF",
+      C_IS_DUAL => 1,
+      C_DOUT_DEFAULT_2 => X"00000000",
+      C_TRI_DEFAULT_2 => X"FFFFFFFF"
+    )
+    PORT MAP (
+      s_axi_aclk => s_axi_aclk,
+      s_axi_aresetn => s_axi_aresetn,
+      s_axi_awaddr => s_axi_awaddr,
+      s_axi_awvalid => s_axi_awvalid,
+      s_axi_awready => s_axi_awready,
+      s_axi_wdata => s_axi_wdata,
+      s_axi_wstrb => s_axi_wstrb,
+      s_axi_wvalid => s_axi_wvalid,
+      s_axi_wready => s_axi_wready,
+      s_axi_bresp => s_axi_bresp,
+      s_axi_bvalid => s_axi_bvalid,
+      s_axi_bready => s_axi_bready,
+      s_axi_araddr => s_axi_araddr,
+      s_axi_arvalid => s_axi_arvalid,
+      s_axi_arready => s_axi_arready,
+      s_axi_rdata => s_axi_rdata,
+      s_axi_rresp => s_axi_rresp,
+      s_axi_rvalid => s_axi_rvalid,
+      s_axi_rready => s_axi_rready,
+      gpio_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
+      gpio_io_o => gpio_io_o,
+      gpio2_io_i => gpio2_io_i
+    );
+END system_bd_axi_gpio_0_arch;

projects/dl814_k7/common_ipi-bd/basic_driver_bd/ip/system_bd_axi_gpio_0/synth/system_bd_axi_gpio_0.vhd

@@ -0,0 +1,213 @@
+-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
+-- IP Revision: 21
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+LIBRARY axi_gpio_v2_0_21;
+USE axi_gpio_v2_0_21.axi_gpio;
+
+ENTITY system_bd_axi_gpio_0 IS
+  PORT (
+    s_axi_aclk : IN STD_LOGIC;
+    s_axi_aresetn : IN STD_LOGIC;
+    s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
+    s_axi_awvalid : IN STD_LOGIC;
+    s_axi_awready : OUT STD_LOGIC;
+    s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+    s_axi_wvalid : IN STD_LOGIC;
+    s_axi_wready : OUT STD_LOGIC;
+    s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+    s_axi_bvalid : OUT STD_LOGIC;
+    s_axi_bready : IN STD_LOGIC;
+    s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
+    s_axi_arvalid : IN STD_LOGIC;
+    s_axi_arready : OUT STD_LOGIC;
+    s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+    s_axi_rvalid : OUT STD_LOGIC;
+    s_axi_rready : IN STD_LOGIC;
+    gpio_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
+  );
+END system_bd_axi_gpio_0;
+
+ARCHITECTURE system_bd_axi_gpio_0_arch OF system_bd_axi_gpio_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_bd_axi_gpio_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT axi_gpio IS
+    GENERIC (
+      C_FAMILY : STRING;
+      C_S_AXI_ADDR_WIDTH : INTEGER;
+      C_S_AXI_DATA_WIDTH : INTEGER;
+      C_GPIO_WIDTH : INTEGER;
+      C_GPIO2_WIDTH : INTEGER;
+      C_ALL_INPUTS : INTEGER;
+      C_ALL_INPUTS_2 : INTEGER;
+      C_ALL_OUTPUTS : INTEGER;
+      C_ALL_OUTPUTS_2 : INTEGER;
+      C_INTERRUPT_PRESENT : INTEGER;
+      C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
+      C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
+      C_IS_DUAL : INTEGER;
+      C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
+      C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
+    );
+    PORT (
+      s_axi_aclk : IN STD_LOGIC;
+      s_axi_aresetn : IN STD_LOGIC;
+      s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
+      s_axi_awvalid : IN STD_LOGIC;
+      s_axi_awready : OUT STD_LOGIC;
+      s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      s_axi_wvalid : IN STD_LOGIC;
+      s_axi_wready : OUT STD_LOGIC;
+      s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      s_axi_bvalid : OUT STD_LOGIC;
+      s_axi_bready : IN STD_LOGIC;
+      s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
+      s_axi_arvalid : IN STD_LOGIC;
+      s_axi_arready : OUT STD_LOGIC;
+      s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      s_axi_rvalid : OUT STD_LOGIC;
+      s_axi_rready : IN STD_LOGIC;
+      ip2intc_irpt : OUT STD_LOGIC;
+      gpio_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      gpio_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      gpio_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+    );
+  END COMPONENT axi_gpio;
+  ATTRIBUTE X_CORE_INFO : STRING;
+  ATTRIBUTE X_CORE_INFO OF system_bd_axi_gpio_0_arch: ARCHITECTURE IS "axi_gpio,Vivado 2019.1.3";
+  ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
+  ATTRIBUTE CHECK_LICENSE_TYPE OF system_bd_axi_gpio_0_arch : ARCHITECTURE IS "system_bd_axi_gpio_0,axi_gpio,{}";
+  ATTRIBUTE CORE_GENERATION_INFO : STRING;
+  ATTRIBUTE CORE_GENERATION_INFO OF system_bd_axi_gpio_0_arch: ARCHITECTURE IS "system_bd_axi_gpio_0,axi_gpio,{x_ipProduct=Vivado 2019.1.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_gpio,x_ipVersion=2.0,x_ipCoreRevision=21,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=kintex7,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_GPIO_WIDTH=32,C_GPIO2_WIDTH=32,C_ALL_INPUTS=0,C_ALL_INPUTS_2=1,C_ALL_OUTPUTS=1,C_ALL_OUTPUTS_2=0,C_INTERRUPT_PRESENT=0,C_DOUT_DEFAULT=0xFFFFFFFF,C_TRI_DEFAULT=0xFFFFFFFF,C_IS_DUAL=1,C_DOUT_DEFAULT_2=0x00000000,C_TRI_DEFAULT_2=0xFFFFFFFF}";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF gpio2_io_i: SIGNAL IS "XIL_INTERFACENAME GPIO2, BOARD.ASSOCIATED_PARAM GPIO2_BOARD_INTERFACE";
+  ATTRIBUTE X_INTERFACE_INFO OF gpio2_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO2 TRI_I";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF gpio_io_o: SIGNAL IS "XIL_INTERFACENAME GPIO, BOARD.ASSOCIATED_PARAM GPIO_BOARD_INTERFACE";
+  ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 25000000, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1" & 
+", RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME S_AXI_ARESETN, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aclk: SIGNAL IS "XIL_INTERFACENAME S_AXI_ACLK, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 25000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
+BEGIN
+  U0 : axi_gpio
+    GENERIC MAP (
+      C_FAMILY => "kintex7",
+      C_S_AXI_ADDR_WIDTH => 9,
+      C_S_AXI_DATA_WIDTH => 32,
+      C_GPIO_WIDTH => 32,
+      C_GPIO2_WIDTH => 32,
+      C_ALL_INPUTS => 0,
+      C_ALL_INPUTS_2 => 1,
+      C_ALL_OUTPUTS => 1,
+      C_ALL_OUTPUTS_2 => 0,
+      C_INTERRUPT_PRESENT => 0,
+      C_DOUT_DEFAULT => X"FFFFFFFF",
+      C_TRI_DEFAULT => X"FFFFFFFF",
+      C_IS_DUAL => 1,
+      C_DOUT_DEFAULT_2 => X"00000000",
+      C_TRI_DEFAULT_2 => X"FFFFFFFF"
+    )
+    PORT MAP (
+      s_axi_aclk => s_axi_aclk,
+      s_axi_aresetn => s_axi_aresetn,
+      s_axi_awaddr => s_axi_awaddr,
+      s_axi_awvalid => s_axi_awvalid,
+      s_axi_awready => s_axi_awready,
+      s_axi_wdata => s_axi_wdata,
+      s_axi_wstrb => s_axi_wstrb,
+      s_axi_wvalid => s_axi_wvalid,
+      s_axi_wready => s_axi_wready,
+      s_axi_bresp => s_axi_bresp,
+      s_axi_bvalid => s_axi_bvalid,
+      s_axi_bready => s_axi_bready,
+      s_axi_araddr => s_axi_araddr,
+      s_axi_arvalid => s_axi_arvalid,
+      s_axi_arready => s_axi_arready,
+      s_axi_rdata => s_axi_rdata,
+      s_axi_rresp => s_axi_rresp,
+      s_axi_rvalid => s_axi_rvalid,
+      s_axi_rready => s_axi_rready,
+      gpio_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
+      gpio_io_o => gpio_io_o,
+      gpio2_io_i => gpio2_io_i
+    );
+END system_bd_axi_gpio_0_arch;

projects/dl814_k7/common_ipi-bd/basic_driver_bd/ip/system_bd_axi_gpio_0/system_bd_axi_gpio_0.xci

@@ -0,0 +1,142 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>system_bd_axi_gpio_0</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="axi_gpio" spirit:version="2.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.IP2INTC_IRQ.PortWidth">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN">/clk_wiz_25M_clk_out1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ">25000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PHASE">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.CLK_DOMAIN">/clk_wiz_25M_clk_out1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.FREQ_HZ">25000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.PHASE">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ARESETN.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ALL_INPUTS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ALL_INPUTS_2">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ALL_OUTPUTS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ALL_OUTPUTS_2">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_DEFAULT">0xFFFFFFFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_DEFAULT_2">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_GPIO2_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_GPIO_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERRUPT_PRESENT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IS_DUAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TRI_DEFAULT">0xFFFFFFFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TRI_DEFAULT_2">0xFFFFFFFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_ALL_INPUTS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_ALL_INPUTS_2">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_ALL_OUTPUTS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_ALL_OUTPUTS_2">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_DOUT_DEFAULT">0xFFFFFFFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_DOUT_DEFAULT_2">0x00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GPIO2_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GPIO_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_INTERRUPT_PRESENT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_IS_DUAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_TRI_DEFAULT">0xFFFFFFFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_TRI_DEFAULT_2">0xFFFFFFFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">system_bd_axi_gpio_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPIO2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.GPIO_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k410t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">21</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PHASE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.CLK_DOMAIN" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.FREQ_HZ" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.PHASE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_ALL_INPUTS_2" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_ALL_OUTPUTS" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_DOUT_DEFAULT" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_INTERRUPT_PRESENT" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_IS_DUAL" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>

projects/dl814_k7/common_ipi-bd/basic_driver_bd/ip/system_bd_axi_gpio_0/system_bd_axi_gpio_0.xdc

@@ -0,0 +1,48 @@
+# (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+
+set_false_path -to [get_pins -hier *cdc_to*/D]
+

projects/dl814_k7/common_ipi-bd/basic_driver_bd/ip/system_bd_axi_gpio_0/system_bd_axi_gpio_0_board.xdc

@@ -0,0 +1,2 @@
+#--------------------Physical Constraints-----------------
+

projects/dl814_k7/common_ipi-bd/basic_driver_bd/ip/system_bd_axi_gpio_0/system_bd_axi_gpio_0_ooc.xdc

@@ -0,0 +1,62 @@
+
+################################################################################
+# (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+
+################################################################################
+
+# This XDC is used only for OOC mode of synthesis, implementation
+# User should update the correct clock period before proceeding further
+# This constraints file contains default clock frequencies to be used during 
+# out-of-context flows such as OOC Synthesis and Hierarchical Designs. 
+# For best results the frequencies should be modified# to match the target 
+# frequencies. 
+
+
+ create_clock -name s_axi_clk -period 10 [get_ports s_axi_aclk]
+## set_property HD.CLK_SRC BUFGCTRL_X0Y0 [get_ports s_axi_aclk]
+
+################################################################################

projects/dl814_k7/common_ipi-bd/basic_driver_bd/ip/system_bd_axi_gpio_0/system_bd_axi_gpio_0_stub.v

@@ -0,0 +1,43 @@
+// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep  4 09:45:24 MDT 2019
+// Date        : Sat Mar 18 23:57:11 2023
+// Host        : JOSH-ASUS-Z690 running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode synth_stub -rename_top system_bd_axi_gpio_0 -prefix
+//               system_bd_axi_gpio_0_ system_bd_axi_gpio_0_stub.v
+// Design      : system_bd_axi_gpio_0
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7k410tffg900-2
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* x_core_info = "axi_gpio,Vivado 2019.1.3" *)
+module system_bd_axi_gpio_0(s_axi_aclk, s_axi_aresetn, s_axi_awaddr, 
+  s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready, 
+  s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready, 
+  s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, gpio_io_o, gpio2_io_i)
+/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,gpio_io_o[31:0],gpio2_io_i[31:0]" */;
+  input s_axi_aclk;
+  input s_axi_aresetn;
+  input [8:0]s_axi_awaddr;
+  input s_axi_awvalid;
+  output s_axi_awready;
+  input [31:0]s_axi_wdata;
+  input [3:0]s_axi_wstrb;
+  input s_axi_wvalid;
+  output s_axi_wready;
+  output [1:0]s_axi_bresp;
+  output s_axi_bvalid;
+  input s_axi_bready;
+  input [8:0]s_axi_araddr;
+  input s_axi_arvalid;
+  output s_axi_arready;
+  output [31:0]s_axi_rdata;
+  output [1:0]s_axi_rresp;
+  output s_axi_rvalid;
+  input s_axi_rready;
+  output [31:0]gpio_io_o;
+  input [31:0]gpio2_io_i;
+endmodule

projects/dl814_k7/common_ipi-bd/basic_driver_bd/ip/system_bd_axi_gpio_0/system_bd_axi_gpio_0_stub.vhdl

@@ -0,0 +1,50 @@
+-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep  4 09:45:24 MDT 2019
+-- Date        : Sat Mar 18 23:57:11 2023
+-- Host        : JOSH-ASUS-Z690 running 64-bit major release  (build 9200)
+-- Command     : write_vhdl -force -mode synth_stub -rename_top system_bd_axi_gpio_0 -prefix
+--               system_bd_axi_gpio_0_ system_bd_axi_gpio_0_stub.vhdl
+-- Design      : system_bd_axi_gpio_0
+-- Purpose     : Stub declaration of top-level module interface
+-- Device      : xc7k410tffg900-2
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity system_bd_axi_gpio_0 is
+  Port ( 
+    s_axi_aclk : in STD_LOGIC;
+    s_axi_aresetn : in STD_LOGIC;
+    s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
+    s_axi_awvalid : in STD_LOGIC;
+    s_axi_awready : out STD_LOGIC;
+    s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    s_axi_wvalid : in STD_LOGIC;
+    s_axi_wready : out STD_LOGIC;
+    s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    s_axi_bvalid : out STD_LOGIC;
+    s_axi_bready : in STD_LOGIC;
+    s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
+    s_axi_arvalid : in STD_LOGIC;
+    s_axi_arready : out STD_LOGIC;
+    s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    s_axi_rvalid : out STD_LOGIC;
+    s_axi_rready : in STD_LOGIC;
+    gpio_io_o : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    gpio2_io_i : in STD_LOGIC_VECTOR ( 31 downto 0 )
+  );
+
+end system_bd_axi_gpio_0;
+
+architecture stub of system_bd_axi_gpio_0 is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,gpio_io_o[31:0],gpio2_io_i[31:0]";
+attribute x_core_info : string;
+attribute x_core_info of stub : architecture is "axi_gpio,Vivado 2019.1.3";
+begin
+end;

projects/dl814_k7/common_ipi-bd/basic_driver_bd/ip/system_bd_axi_interconnect_0/system_bd_axi_interconnect_0.xci

@@ -0,0 +1,358 @@
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+  <spirit:library>xci</spirit:library>
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projects/dl814_k7/common_ipi-bd/basic_driver_bd/ip/system_bd_axi_spi_engine_0/sim/system_bd_axi_spi_engine_0.v

@@ -0,0 +1,245 @@
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: analog.com:user:axi_spi_engine:1.0
+// IP Revision: 1
+
+`timescale 1ns/1ps
+
+(* IP_DEFINITION_SOURCE = "package_project" *)
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module system_bd_axi_spi_engine_0 (
+  s_axi_aclk,
+  s_axi_aresetn,
+  s_axi_awvalid,
+  s_axi_awaddr,
+  s_axi_awready,
+  s_axi_awprot,
+  s_axi_wvalid,
+  s_axi_wdata,
+  s_axi_wstrb,
+  s_axi_wready,
+  s_axi_bvalid,
+  s_axi_bresp,
+  s_axi_bready,
+  s_axi_arvalid,
+  s_axi_araddr,
+  s_axi_arready,
+  s_axi_arprot,
+  s_axi_rvalid,
+  s_axi_rready,
+  s_axi_rresp,
+  s_axi_rdata,
+  irq,
+  spi_clk,
+  spi_resetn,
+  cmd_ready,
+  cmd_valid,
+  cmd_data,
+  sdo_data_ready,
+  sdo_data_valid,
+  sdo_data,
+  sdi_data_ready,
+  sdi_data_valid,
+  sdi_data,
+  sync_ready,
+  sync_valid,
+  sync_data
+);
+
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi_aclk, ASSOCIATED_BUSIF s_axi, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0, XIL_INTERFACENAME spi_engine_offload_ctrl0_s_axi_signal_clock, ASSOCIATED_BUSIF spi_engine_offload_ctrl0:s_axi, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 25000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 s_axi_aclk CLK, xilinx.com:signal:clock:1.0 spi_engine_offload_ctrl0_s_axi_signal_clock CLK" *)
+input wire s_axi_aclk;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0, XIL_INTERFACENAME spi_engine_offload_ctrl0_s_axi_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 s_axi_aresetn RST, xilinx.com:signal:reset:1.0 spi_engine_offload_ctrl0_s_axi_signal_reset RST" *)
+input wire s_axi_aresetn;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWVALID" *)
+input wire s_axi_awvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWADDR" *)
+input wire [15 : 0] s_axi_awaddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWREADY" *)
+output wire s_axi_awready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWPROT" *)
+input wire [2 : 0] s_axi_awprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WVALID" *)
+input wire s_axi_wvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WDATA" *)
+input wire [31 : 0] s_axi_wdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WSTRB" *)
+input wire [3 : 0] s_axi_wstrb;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WREADY" *)
+output wire s_axi_wready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BVALID" *)
+output wire s_axi_bvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BRESP" *)
+output wire [1 : 0] s_axi_bresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BREADY" *)
+input wire s_axi_bready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARVALID" *)
+input wire s_axi_arvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARADDR" *)
+input wire [15 : 0] s_axi_araddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARREADY" *)
+output wire s_axi_arready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARPROT" *)
+input wire [2 : 0] s_axi_arprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RVALID" *)
+output wire s_axi_rvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RREADY" *)
+input wire s_axi_rready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RRESP" *)
+output wire [1 : 0] s_axi_rresp;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 25000000, ID_WIDTH 0, ADDR_WIDTH 16, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS \
+1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RDATA" *)
+output wire [31 : 0] s_axi_rdata;
+output wire irq;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME spi_engine_ctrl_signal_clock, ASSOCIATED_BUSIF spi_engine_ctrl, ASSOCIATED_RESET spi_resetn, FREQ_HZ 25000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 spi_engine_ctrl_signal_clock CLK" *)
+input wire spi_clk;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME spi_engine_ctrl_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 spi_engine_ctrl_signal_reset RST" *)
+output wire spi_resetn;
+(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl CMD_READY" *)
+input wire cmd_ready;
+(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl CMD_VALID" *)
+output wire cmd_valid;
+(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl CMD_DATA" *)
+output wire [15 : 0] cmd_data;
+(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDO_READY" *)
+input wire sdo_data_ready;
+(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDO_VALID" *)
+output wire sdo_data_valid;
+(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDO_DATA" *)
+output wire [7 : 0] sdo_data;
+(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDI_READY" *)
+output wire sdi_data_ready;
+(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDI_VALID" *)
+input wire sdi_data_valid;
+(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDI_DATA" *)
+input wire [7 : 0] sdi_data;
+(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SYNC_READY" *)
+output wire sync_ready;
+(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SYNC_VALID" *)
+input wire sync_valid;
+(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SYNC_DATA" *)
+input wire [7 : 0] sync_data;
+
+  axi_spi_engine #(
+    .CMD_FIFO_ADDRESS_WIDTH(4),
+    .SYNC_FIFO_ADDRESS_WIDTH(4),
+    .SDO_FIFO_ADDRESS_WIDTH(5),
+    .SDI_FIFO_ADDRESS_WIDTH(5),
+    .MM_IF_TYPE(0),
+    .ASYNC_SPI_CLK(1'B0),
+    .NUM_OFFLOAD(0),
+    .OFFLOAD0_CMD_MEM_ADDRESS_WIDTH(4),
+    .OFFLOAD0_SDO_MEM_ADDRESS_WIDTH(4),
+    .ID(0),
+    .DATA_WIDTH(8),
+    .NUM_OF_SDI(1)
+  ) inst (
+    .s_axi_aclk(s_axi_aclk),
+    .s_axi_aresetn(s_axi_aresetn),
+    .s_axi_awvalid(s_axi_awvalid),
+    .s_axi_awaddr(s_axi_awaddr),
+    .s_axi_awready(s_axi_awready),
+    .s_axi_awprot(s_axi_awprot),
+    .s_axi_wvalid(s_axi_wvalid),
+    .s_axi_wdata(s_axi_wdata),
+    .s_axi_wstrb(s_axi_wstrb),
+    .s_axi_wready(s_axi_wready),
+    .s_axi_bvalid(s_axi_bvalid),
+    .s_axi_bresp(s_axi_bresp),
+    .s_axi_bready(s_axi_bready),
+    .s_axi_arvalid(s_axi_arvalid),
+    .s_axi_araddr(s_axi_araddr),
+    .s_axi_arready(s_axi_arready),
+    .s_axi_arprot(s_axi_arprot),
+    .s_axi_rvalid(s_axi_rvalid),
+    .s_axi_rready(s_axi_rready),
+    .s_axi_rresp(s_axi_rresp),
+    .s_axi_rdata(s_axi_rdata),
+    .up_clk(1'B0),
+    .up_rstn(1'B0),
+    .up_wreq(1'B0),
+    .up_waddr(14'B0),
+    .up_wdata(32'B0),
+    .up_wack(),
+    .up_rreq(1'B0),
+    .up_raddr(14'B0),
+    .up_rdata(),
+    .up_rack(),
+    .irq(irq),
+    .spi_clk(spi_clk),
+    .spi_resetn(spi_resetn),
+    .cmd_ready(cmd_ready),
+    .cmd_valid(cmd_valid),
+    .cmd_data(cmd_data),
+    .sdo_data_ready(sdo_data_ready),
+    .sdo_data_valid(sdo_data_valid),
+    .sdo_data(sdo_data),
+    .sdi_data_ready(sdi_data_ready),
+    .sdi_data_valid(sdi_data_valid),
+    .sdi_data(sdi_data),
+    .sync_ready(sync_ready),
+    .sync_valid(sync_valid),
+    .sync_data(sync_data),
+    .offload0_cmd_wr_en(),
+    .offload0_cmd_wr_data(),
+    .offload0_sdo_wr_en(),
+    .offload0_sdo_wr_data(),
+    .offload0_mem_reset(),
+    .offload0_enable(),
+    .offload0_enabled(1'B0),
+    .offload_sync_ready(),
+    .offload_sync_valid(1'B0),
+    .offload_sync_data(8'B0)
+  );
+endmodule

projects/dl814_k7/common_ipi-bd/basic_driver_bd/ip/system_bd_axi_spi_engine_0/synth/system_bd_axi_spi_engine_0.v

@@ -0,0 +1,245 @@
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: analog.com:user:axi_spi_engine:1.0
+// IP Revision: 1
+
+(* X_CORE_INFO = "axi_spi_engine,Vivado 2019.1.3" *)
+(* CHECK_LICENSE_TYPE = "system_bd_axi_spi_engine_0,axi_spi_engine,{}" *)
+(* IP_DEFINITION_SOURCE = "package_project" *)
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module system_bd_axi_spi_engine_0 (
+  s_axi_aclk,
+  s_axi_aresetn,
+  s_axi_awvalid,
+  s_axi_awaddr,
+  s_axi_awready,
+  s_axi_awprot,
+  s_axi_wvalid,
+  s_axi_wdata,
+  s_axi_wstrb,
+  s_axi_wready,
+  s_axi_bvalid,
+  s_axi_bresp,
+  s_axi_bready,
+  s_axi_arvalid,
+  s_axi_araddr,
+  s_axi_arready,
+  s_axi_arprot,
+  s_axi_rvalid,
+  s_axi_rready,
+  s_axi_rresp,
+  s_axi_rdata,
+  irq,
+  spi_clk,
+  spi_resetn,
+  cmd_ready,
+  cmd_valid,
+  cmd_data,
+  sdo_data_ready,
+  sdo_data_valid,
+  sdo_data,
+  sdi_data_ready,
+  sdi_data_valid,
+  sdi_data,
+  sync_ready,
+  sync_valid,
+  sync_data
+);
+
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi_aclk, ASSOCIATED_BUSIF s_axi, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0, XIL_INTERFACENAME spi_engine_offload_ctrl0_s_axi_signal_clock, ASSOCIATED_BUSIF spi_engine_offload_ctrl0:s_axi, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 25000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 s_axi_aclk CLK, xilinx.com:signal:clock:1.0 spi_engine_offload_ctrl0_s_axi_signal_clock CLK" *)
+input wire s_axi_aclk;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0, XIL_INTERFACENAME spi_engine_offload_ctrl0_s_axi_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 s_axi_aresetn RST, xilinx.com:signal:reset:1.0 spi_engine_offload_ctrl0_s_axi_signal_reset RST" *)
+input wire s_axi_aresetn;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWVALID" *)
+input wire s_axi_awvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWADDR" *)
+input wire [15 : 0] s_axi_awaddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWREADY" *)
+output wire s_axi_awready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWPROT" *)
+input wire [2 : 0] s_axi_awprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WVALID" *)
+input wire s_axi_wvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WDATA" *)
+input wire [31 : 0] s_axi_wdata;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WSTRB" *)
+input wire [3 : 0] s_axi_wstrb;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WREADY" *)
+output wire s_axi_wready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BVALID" *)
+output wire s_axi_bvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BRESP" *)
+output wire [1 : 0] s_axi_bresp;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BREADY" *)
+input wire s_axi_bready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARVALID" *)
+input wire s_axi_arvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARADDR" *)
+input wire [15 : 0] s_axi_araddr;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARREADY" *)
+output wire s_axi_arready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARPROT" *)
+input wire [2 : 0] s_axi_arprot;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RVALID" *)
+output wire s_axi_rvalid;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RREADY" *)
+input wire s_axi_rready;
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RRESP" *)
+output wire [1 : 0] s_axi_rresp;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 25000000, ID_WIDTH 0, ADDR_WIDTH 16, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS \
+1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RDATA" *)
+output wire [31 : 0] s_axi_rdata;
+output wire irq;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME spi_engine_ctrl_signal_clock, ASSOCIATED_BUSIF spi_engine_ctrl, ASSOCIATED_RESET spi_resetn, FREQ_HZ 25000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 spi_engine_ctrl_signal_clock CLK" *)
+input wire spi_clk;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME spi_engine_ctrl_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 spi_engine_ctrl_signal_reset RST" *)
+output wire spi_resetn;
+(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl CMD_READY" *)
+input wire cmd_ready;
+(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl CMD_VALID" *)
+output wire cmd_valid;
+(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl CMD_DATA" *)
+output wire [15 : 0] cmd_data;
+(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDO_READY" *)
+input wire sdo_data_ready;
+(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDO_VALID" *)
+output wire sdo_data_valid;
+(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDO_DATA" *)
+output wire [7 : 0] sdo_data;
+(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDI_READY" *)
+output wire sdi_data_ready;
+(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDI_VALID" *)
+input wire sdi_data_valid;
+(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDI_DATA" *)
+input wire [7 : 0] sdi_data;
+(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SYNC_READY" *)
+output wire sync_ready;
+(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SYNC_VALID" *)
+input wire sync_valid;
+(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SYNC_DATA" *)
+input wire [7 : 0] sync_data;
+
+  axi_spi_engine #(
+    .CMD_FIFO_ADDRESS_WIDTH(4),
+    .SYNC_FIFO_ADDRESS_WIDTH(4),
+    .SDO_FIFO_ADDRESS_WIDTH(5),
+    .SDI_FIFO_ADDRESS_WIDTH(5),
+    .MM_IF_TYPE(0),
+    .ASYNC_SPI_CLK(1'B0),
+    .NUM_OFFLOAD(0),
+    .OFFLOAD0_CMD_MEM_ADDRESS_WIDTH(4),
+    .OFFLOAD0_SDO_MEM_ADDRESS_WIDTH(4),
+    .ID(0),
+    .DATA_WIDTH(8),
+    .NUM_OF_SDI(1)
+  ) inst (
+    .s_axi_aclk(s_axi_aclk),
+    .s_axi_aresetn(s_axi_aresetn),
+    .s_axi_awvalid(s_axi_awvalid),
+    .s_axi_awaddr(s_axi_awaddr),
+    .s_axi_awready(s_axi_awready),
+    .s_axi_awprot(s_axi_awprot),
+    .s_axi_wvalid(s_axi_wvalid),
+    .s_axi_wdata(s_axi_wdata),
+    .s_axi_wstrb(s_axi_wstrb),
+    .s_axi_wready(s_axi_wready),
+    .s_axi_bvalid(s_axi_bvalid),
+    .s_axi_bresp(s_axi_bresp),
+    .s_axi_bready(s_axi_bready),
+    .s_axi_arvalid(s_axi_arvalid),
+    .s_axi_araddr(s_axi_araddr),
+    .s_axi_arready(s_axi_arready),
+    .s_axi_arprot(s_axi_arprot),
+    .s_axi_rvalid(s_axi_rvalid),
+    .s_axi_rready(s_axi_rready),
+    .s_axi_rresp(s_axi_rresp),
+    .s_axi_rdata(s_axi_rdata),
+    .up_clk(1'B0),
+    .up_rstn(1'B0),
+    .up_wreq(1'B0),
+    .up_waddr(14'B0),
+    .up_wdata(32'B0),
+    .up_wack(),
+    .up_rreq(1'B0),
+    .up_raddr(14'B0),
+    .up_rdata(),
+    .up_rack(),
+    .irq(irq),
+    .spi_clk(spi_clk),
+    .spi_resetn(spi_resetn),
+    .cmd_ready(cmd_ready),
+    .cmd_valid(cmd_valid),
+    .cmd_data(cmd_data),
+    .sdo_data_ready(sdo_data_ready),
+    .sdo_data_valid(sdo_data_valid),
+    .sdo_data(sdo_data),
+    .sdi_data_ready(sdi_data_ready),
+    .sdi_data_valid(sdi_data_valid),
+    .sdi_data(sdi_data),
+    .sync_ready(sync_ready),
+    .sync_valid(sync_valid),
+    .sync_data(sync_data),
+    .offload0_cmd_wr_en(),
+    .offload0_cmd_wr_data(),
+    .offload0_sdo_wr_en(),
+    .offload0_sdo_wr_data(),
+    .offload0_mem_reset(),
+    .offload0_enable(),
+    .offload0_enabled(1'B0),
+    .offload_sync_ready(),
+    .offload_sync_valid(1'B0),
+    .offload_sync_data(8'B0)
+  );
+endmodule

projects/dl814_k7/common_ipi-bd/basic_driver_bd/ip/system_bd_axi_spi_engine_0/system_bd_axi_spi_engine_0.xci

@@ -0,0 +1,147 @@
+<?xml version="1.0" encoding="UTF-8"?>
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+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>system_bd_axi_spi_engine_0</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="analog.com" spirit:library="user" spirit:name="axi_spi_engine" spirit:version="1.0"/>
+      <spirit:configurableElementValues>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SPI_ENGINE_CTRL_SIGNAL_CLOCK.PHASE">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SPI_ENGINE_CTRL_SIGNAL_RESET.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SPI_ENGINE_OFFLOAD_CTRL0_S_AXI_SIGNAL_CLOCK.CLK_DOMAIN">/clk_wiz_25M_clk_out1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ">25000000</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT">1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP">1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.INSERT_VIP">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PHASE">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.PHASE">0.000</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.ASYNC_SPI_CLK">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CMD_FIFO_ADDRESS_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DATA_WIDTH">8</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MM_IF_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.NUM_OFFLOAD">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.NUM_OF_SDI">1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.OFFLOAD0_SDO_MEM_ADDRESS_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SDI_FIFO_ADDRESS_WIDTH">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SDO_FIFO_ADDRESS_WIDTH">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SYNC_FIFO_ADDRESS_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.OFFLOAD0_CMD_MEM_ADDRESS_WIDTH">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.OFFLOAD0_SDO_MEM_ADDRESS_WIDTH">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ASYNC_SPI_CLK">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CMD_FIFO_ADDRESS_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">system_bd_axi_spi_engine_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MM_IF_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_OFFLOAD">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_OF_SDI">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OFFLOAD0_CMD_MEM_ADDRESS_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OFFLOAD0_SDO_MEM_ADDRESS_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SDI_FIFO_ADDRESS_WIDTH">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SDO_FIFO_ADDRESS_WIDTH">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SYNC_FIFO_ADDRESS_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k410t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SPI_ENGINE_CTRL_SIGNAL_CLOCK.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SPI_ENGINE_CTRL_SIGNAL_CLOCK.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SPI_ENGINE_CTRL_SIGNAL_CLOCK.PHASE" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SPI_ENGINE_OFFLOAD_CTRL0_S_AXI_SIGNAL_CLOCK.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SPI_ENGINE_OFFLOAD_CTRL0_S_AXI_SIGNAL_CLOCK.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SPI_ENGINE_OFFLOAD_CTRL0_S_AXI_SIGNAL_CLOCK.PHASE" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PHASE" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>

projects/dl814_k7/common_ipi-bd/basic_driver_bd/ip/system_bd_axi_spi_engine_0/system_bd_axi_spi_engine_0_constr.xdc

@@ -0,0 +1 @@
+

projects/dl814_k7/common_ipi-bd/basic_driver_bd/ip/system_bd_axi_spi_engine_0/system_bd_axi_spi_engine_0_stub.v

@@ -0,0 +1,60 @@
+// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep  4 09:45:24 MDT 2019
+// Date        : Sat Mar 18 23:57:11 2023
+// Host        : JOSH-ASUS-Z690 running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode synth_stub -rename_top system_bd_axi_spi_engine_0 -prefix
+//               system_bd_axi_spi_engine_0_ system_bd_axi_spi_engine_0_stub.v
+// Design      : system_bd_axi_spi_engine_0
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7k410tffg900-2
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* X_CORE_INFO = "axi_spi_engine,Vivado 2019.1.3" *)
+module system_bd_axi_spi_engine_0(s_axi_aclk, s_axi_aresetn, s_axi_awvalid, 
+  s_axi_awaddr, s_axi_awready, s_axi_awprot, s_axi_wvalid, s_axi_wdata, s_axi_wstrb, 
+  s_axi_wready, s_axi_bvalid, s_axi_bresp, s_axi_bready, s_axi_arvalid, s_axi_araddr, 
+  s_axi_arready, s_axi_arprot, s_axi_rvalid, s_axi_rready, s_axi_rresp, s_axi_rdata, irq, 
+  spi_clk, spi_resetn, cmd_ready, cmd_valid, cmd_data, sdo_data_ready, sdo_data_valid, sdo_data, 
+  sdi_data_ready, sdi_data_valid, sdi_data, sync_ready, sync_valid, sync_data)
+/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awvalid,s_axi_awaddr[15:0],s_axi_awready,s_axi_awprot[2:0],s_axi_wvalid,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wready,s_axi_bvalid,s_axi_bresp[1:0],s_axi_bready,s_axi_arvalid,s_axi_araddr[15:0],s_axi_arready,s_axi_arprot[2:0],s_axi_rvalid,s_axi_rready,s_axi_rresp[1:0],s_axi_rdata[31:0],irq,spi_clk,spi_resetn,cmd_ready,cmd_valid,cmd_data[15:0],sdo_data_ready,sdo_data_valid,sdo_data[7:0],sdi_data_ready,sdi_data_valid,sdi_data[7:0],sync_ready,sync_valid,sync_data[7:0]" */;
+  input s_axi_aclk;
+  input s_axi_aresetn;
+  input s_axi_awvalid;
+  input [15:0]s_axi_awaddr;
+  output s_axi_awready;
+  input [2:0]s_axi_awprot;
+  input s_axi_wvalid;
+  input [31:0]s_axi_wdata;
+  input [3:0]s_axi_wstrb;
+  output s_axi_wready;
+  output s_axi_bvalid;
+  output [1:0]s_axi_bresp;
+  input s_axi_bready;
+  input s_axi_arvalid;
+  input [15:0]s_axi_araddr;
+  output s_axi_arready;
+  input [2:0]s_axi_arprot;
+  output s_axi_rvalid;
+  input s_axi_rready;
+  output [1:0]s_axi_rresp;
+  output [31:0]s_axi_rdata;
+  output irq;
+  input spi_clk;
+  output spi_resetn;
+  input cmd_ready;
+  output cmd_valid;
+  output [15:0]cmd_data;
+  input sdo_data_ready;
+  output sdo_data_valid;
+  output [7:0]sdo_data;
+  output sdi_data_ready;
+  input sdi_data_valid;
+  input [7:0]sdi_data;
+  output sync_ready;
+  input sync_valid;
+  input [7:0]sync_data;
+endmodule

projects/dl814_k7/common_ipi-bd/basic_driver_bd/ip/system_bd_axi_spi_engine_0/system_bd_axi_spi_engine_0_stub.vhdl

@@ -0,0 +1,65 @@
+-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep  4 09:45:24 MDT 2019
+-- Date        : Sat Mar 18 23:57:11 2023
+-- Host        : JOSH-ASUS-Z690 running 64-bit major release  (build 9200)
+-- Command     : write_vhdl -force -mode synth_stub -rename_top system_bd_axi_spi_engine_0 -prefix
+--               system_bd_axi_spi_engine_0_ system_bd_axi_spi_engine_0_stub.vhdl
+-- Design      : system_bd_axi_spi_engine_0
+-- Purpose     : Stub declaration of top-level module interface
+-- Device      : xc7k410tffg900-2
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity system_bd_axi_spi_engine_0 is
+  Port ( 
+    s_axi_aclk : in STD_LOGIC;
+    s_axi_aresetn : in STD_LOGIC;
+    s_axi_awvalid : in STD_LOGIC;
+    s_axi_awaddr : in STD_LOGIC_VECTOR ( 15 downto 0 );
+    s_axi_awready : out STD_LOGIC;
+    s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
+    s_axi_wvalid : in STD_LOGIC;
+    s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    s_axi_wready : out STD_LOGIC;
+    s_axi_bvalid : out STD_LOGIC;
+    s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    s_axi_bready : in STD_LOGIC;
+    s_axi_arvalid : in STD_LOGIC;
+    s_axi_araddr : in STD_LOGIC_VECTOR ( 15 downto 0 );
+    s_axi_arready : out STD_LOGIC;
+    s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
+    s_axi_rvalid : out STD_LOGIC;
+    s_axi_rready : in STD_LOGIC;
+    s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    irq : out STD_LOGIC;
+    spi_clk : in STD_LOGIC;
+    spi_resetn : out STD_LOGIC;
+    cmd_ready : in STD_LOGIC;
+    cmd_valid : out STD_LOGIC;
+    cmd_data : out STD_LOGIC_VECTOR ( 15 downto 0 );
+    sdo_data_ready : in STD_LOGIC;
+    sdo_data_valid : out STD_LOGIC;
+    sdo_data : out STD_LOGIC_VECTOR ( 7 downto 0 );
+    sdi_data_ready : out STD_LOGIC;
+    sdi_data_valid : in STD_LOGIC;
+    sdi_data : in STD_LOGIC_VECTOR ( 7 downto 0 );
+    sync_ready : out STD_LOGIC;
+    sync_valid : in STD_LOGIC;
+    sync_data : in STD_LOGIC_VECTOR ( 7 downto 0 )
+  );
+
+end system_bd_axi_spi_engine_0;
+
+architecture stub of system_bd_axi_spi_engine_0 is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "s_axi_aclk,s_axi_aresetn,s_axi_awvalid,s_axi_awaddr[15:0],s_axi_awready,s_axi_awprot[2:0],s_axi_wvalid,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wready,s_axi_bvalid,s_axi_bresp[1:0],s_axi_bready,s_axi_arvalid,s_axi_araddr[15:0],s_axi_arready,s_axi_arprot[2:0],s_axi_rvalid,s_axi_rready,s_axi_rresp[1:0],s_axi_rdata[31:0],irq,spi_clk,spi_resetn,cmd_ready,cmd_valid,cmd_data[15:0],sdo_data_ready,sdo_data_valid,sdo_data[7:0],sdi_data_ready,sdi_data_valid,sdi_data[7:0],sync_ready,sync_valid,sync_data[7:0]";
+attribute X_CORE_INFO : string;
+attribute X_CORE_INFO of stub : architecture is "axi_spi_engine,Vivado 2019.1.3";
+begin
+end;

projects/dl814_k7/common_ipi-bd/basic_driver_bd/ip/system_bd_clk_wiz_25M_0/system_bd_clk_wiz_25M_0.v

@@ -0,0 +1,90 @@
+
+// file: system_bd_clk_wiz_25M_0.v
+// 
+// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+//----------------------------------------------------------------------------
+// User entered comments
+//----------------------------------------------------------------------------
+// None
+//
+//----------------------------------------------------------------------------
+//  Output     Output      Phase    Duty Cycle   Pk-to-Pk     Phase
+//   Clock     Freq (MHz)  (degrees)    (%)     Jitter (ps)  Error (ps)
+//----------------------------------------------------------------------------
+// clk_out1____25.000______0.000______50.0______401.466____245.713
+//
+//----------------------------------------------------------------------------
+// Input Clock   Freq (MHz)    Input Jitter (UI)
+//----------------------------------------------------------------------------
+// __primary______________25____________0.010
+
+`timescale 1ps/1ps
+
+(* CORE_GENERATION_INFO = "system_bd_clk_wiz_25M_0,clk_wiz_v6_0_3_0_0,{component_name=system_bd_clk_wiz_25M_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=40.000,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
+
+module system_bd_clk_wiz_25M_0 
+ (
+  // Clock out ports
+  output        clk_out1,
+  // Status and control signals
+  output        locked,
+ // Clock in ports
+  input         clk_in1
+ );
+
+  system_bd_clk_wiz_25M_0_clk_wiz inst
+  (
+  // Clock out ports  
+  .clk_out1(clk_out1),
+  // Status and control signals               
+  .locked(locked),
+ // Clock in ports
+  .clk_in1(clk_in1)
+  );
+
+endmodule

projects/dl814_k7/common_ipi-bd/basic_driver_bd/ip/system_bd_clk_wiz_25M_0/system_bd_clk_wiz_25M_0.xci

@@ -0,0 +1,692 @@
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+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>system_bd_clk_wiz_25M_0</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="clk_wiz" spirit:version="6.0"/>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.ASSOCIATED_RESET"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.CLK_DOMAIN">system_bd_clk_25MHz</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.FREQ_HZ">25000000</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.ASSOCIATED_BUSIF"/>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.CLK_DOMAIN">/clk_wiz_25M_clk_out1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_OUT_FREQ">25</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_1">0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_2">0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_ACTUAL_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_MATCHED_ROUTING">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_USED">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_1">0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_2">0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_ACTUAL_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_MATCHED_ROUTING">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_USED">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_1">0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_2">0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_ACTUAL_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_MATCHED_ROUTING">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_USED">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_1">0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_2">0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_ACTUAL_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_MATCHED_ROUTING">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_USED">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_1">0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_2">0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_ACTUAL_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_MATCHED_ROUTING">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_USED">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_MATCHED_ROUTING">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_USED">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUTPHY_MODE">VCO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_IN_SEL_PORT">clk_in_sel</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT1_PORT">clk_out1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT2_PORT">clk_out2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT3_PORT">clk_out3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT4_PORT">clk_out4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT5_PORT">clk_out5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT6_PORT">clk_out6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT7_PORT">clk_out7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_VALID_PORT">CLK_VALID</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLOCK_MGR_TYPE">NA</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DADDR_PORT">daddr</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DCLK_PORT">dclk</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEN_PORT">den</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_PORT">din</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVCLK">0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE1_AUTO">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE2_AUTO">0.25</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE3_AUTO">0.25</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE4_AUTO">0.25</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE5_AUTO">0.25</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE6_AUTO">0.25</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE7_AUTO">0.25</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_PORT">dout</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DRDY_PORT">drdy</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DWE_PORT">dwe</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_CLKOUTPHY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_CLOCK_MONITOR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_USER_CLOCK0">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_USER_CLOCK1">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_USER_CLOCK2">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_USER_CLOCK3">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_Enable_PLL0">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_Enable_PLL1">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FEEDBACK_SOURCE">FDBK_AUTO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FILTER_1">0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FILTER_2">0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_CDDC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW0">Input Clock   Freq (MHz)    Input Jitter (UI)</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW1">__primary______________25____________0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW2">no_secondary_input_clock </spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INPUT_CLK_STOPPED_PORT">input_clk_stopped</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_SELECTION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IN_FREQ_UNITS">Units_MHz</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_JITTER_SEL">No_Jitter</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOCKED_PORT">locked</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOCK_1">0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOCK_2">0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOCK_3">0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV1">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV2">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV3">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV4">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV5">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV6">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV7">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_MULT_F">36.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN1_PERIOD">40.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN2_PERIOD">10.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DIVIDE_F">36.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_CASCADE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLOCK_HOLD">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_COMPENSATION">ZHOLD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_NOTES">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_REF_JITTER1">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_REF_JITTER2">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_STARTUP_WAIT">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_OUT_CLKS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0A"> Output     Output      Phase    Duty Cycle   Pk-to-Pk     Phase</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0B">  Clock     Freq (MHz)  (degrees)    (%)     Jitter (ps)  Error (ps)</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW1">clk_out1____25.000______0.000______50.0______401.466____245.713</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW2">no_CLK_OUT2_output</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW3">no_CLK_OUT3_output</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW4">no_CLK_OUT4_output</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW5">no_CLK_OUT5_output</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW6">no_CLK_OUT6_output</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW7">no_CLK_OUT7_output</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERRIDE_MMCM">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERRIDE_PLL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PHASESHIFT_MODE">WAVEFORM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLATFORM">UNKNOWN</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLLBUFGCEDIV">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLLBUFGCEDIV1">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLLBUFGCEDIV2">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLLBUFGCEDIV3">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLLBUFGCEDIV4">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKFBOUT_MULT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKIN_PERIOD">1.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLK_FEEDBACK">CLKFBOUT</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_COMPENSATION">SYSTEM_SYNCHRONOUS</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_NOTES">No notes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_REF_JITTER">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_DOWN_PORT">power_down</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_REG">0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRECISION">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMARY_PORT">clk_in1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMITIVE">MMCM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMTYPE_SEL">AUTO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_FREQ">25</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_JITTER">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSCLK_PORT">psclk</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSDONE_PORT">psdone</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSEN_PORT">psen</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSINCDEC_PORT">psincdec</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REF_CLK_FREQ">100.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RESET_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RESET_PORT">reset</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_JITTER">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_PORT">clk_in2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MODE">CENTER_HIGH</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MOD_PERIOD">4000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MOD_TIME">0.004</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_STATUS_PORT">STATUS</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH">11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USER_CLK_FREQ0">100.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USER_CLK_FREQ1">100.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USER_CLK_FREQ2">100.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USER_CLK_FREQ3">100.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKFB_STOPPED">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT1_BAR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT2_BAR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT3_BAR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT4_BAR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLK_VALID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLOCK_SEQUENCING">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DYN_PHASE_SHIFT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DYN_RECONFIG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FAST_SIMULATION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FREEZE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FREQ_SYNTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_INCLK_STOPPED">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_INCLK_SWITCHOVER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_LOCKED">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MAX_I_JITTER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MIN_O_JITTER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MIN_POWER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_POWER_DOWN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_RESET">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SAFE_CLOCK_STARTUP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SPREAD_SPECTRUM">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_STATUS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_component_name">system_bd_clk_wiz_25M_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AUTO_PRIMITIVE">MMCM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_DRP">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CALC_DONE">empty</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCDONE_PORT">cddcdone</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCREQ_PORT">cddcreq</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_N_PORT">clkfb_in_n</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_PORT">clkfb_in</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_P_PORT">clkfb_in_p</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_SIGNALING">SINGLE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_N_PORT">clkfb_out_n</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_PORT">clkfb_out</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_P_PORT">clkfb_out_p</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_STOPPED_PORT">clkfb_stopped</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_JITTER_PS">400.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_UI_JITTER">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_JITTER_PS">100.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_UI_JITTER">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_JITTER">401.466</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_MATCHED_ROUTING">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR">245.713</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ">25</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_USED">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_JITTER">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_MATCHED_ROUTING">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_PHASE_ERROR">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_USED">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_JITTER">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_MATCHED_ROUTING">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_PHASE_ERROR">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_USED">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_JITTER">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_MATCHED_ROUTING">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_PHASE_ERROR">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_USED">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_JITTER">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_MATCHED_ROUTING">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_PHASE_ERROR">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_USED">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_JITTER">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_MATCHED_ROUTING">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_PHASE_ERROR">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_USED">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_JITTER">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_MATCHED_ROUTING">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_PHASE_ERROR">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_USED">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUTPHY_REQUESTED_FREQ">600.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN_SEL_PORT">clk_in_sel</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_PORT">clk_out1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_PORT">clk_out2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_PORT">clk_out3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_PORT">clk_out4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_PORT">clk_out5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_PORT">clk_out6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_PORT">clk_out7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_VALID_PORT">CLK_VALID</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLOCK_MGR_TYPE">auto</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">system_bd_clk_wiz_25M_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DADDR_PORT">daddr</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCLK_PORT">dclk</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DEN_PORT">den</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIN_PORT">din</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DOUT_PORT">dout</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DRDY_PORT">drdy</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DWE_PORT">dwe</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CDDC">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CLKOUTPHY">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CLOCK_MONITOR">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK0">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK1">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK2">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK3">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_PLL0">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_PLL1">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FEEDBACK_SOURCE">FDBK_AUTO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_CLK_STOPPED_PORT">input_clk_stopped</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_MODE">frequency</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_SELECTION">Enable_AXI</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_FREQ_UNITS">Units_MHz</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_JITTER_UNITS">Units_UI</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_OPTIONS">UI</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_SEL">No_Jitter</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LOCKED_PORT">locked</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F">36.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_USE_FINE_PS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN1_PERIOD">40.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN2_PERIOD">10.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F">36.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_USE_FINE_PS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_USE_FINE_PS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_USE_FINE_PS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_USE_FINE_PS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_CASCADE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_USE_FINE_PS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_USE_FINE_PS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_USE_FINE_PS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLOCK_HOLD">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_COMPENSATION">ZHOLD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_NOTES">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER1">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER2">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_STARTUP_WAIT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_OUT_CLKS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_MMCM">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_PLL">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PHASESHIFT_MODE">WAVEFORM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PHASE_DUTY_CONFIG">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLATFORM">UNKNOWN</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_MULT">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKIN_PERIOD">10.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLK_FEEDBACK">CLKFBOUT</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_COMPENSATION">SYSTEM_SYNCHRONOUS</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_NOTES">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_REF_JITTER">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.POWER_DOWN_PORT">power_down</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRECISION">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMARY_PORT">clk_in1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMITIVE">MMCM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMTYPE_SEL">mmcm_adv</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_FREQ">25</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_JITTER">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSCLK_PORT">psclk</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSDONE_PORT">psdone</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSEN_PORT">psen</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSINCDEC_PORT">psincdec</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REF_CLK_FREQ">100.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RELATIVE_INCLK">REL_PRIMARY</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_PORT">reset</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_TYPE">ACTIVE_HIGH</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_JITTER">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_PORT">clk_in2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MODE">CENTER_HIGH</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MOD_FREQ">250</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MOD_TIME">0.004</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.STATUS_PORT">STATUS</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SUMMARY_STRINGS">empty</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_CLK_FREQ0">100.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_CLK_FREQ1">100.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_CLK_FREQ2">100.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_CLK_FREQ3">100.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLKFB_STOPPED">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLK_VALID">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLOCK_SEQUENCING">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_PHASE_SHIFT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_RECONFIG">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREEZE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREQ_SYNTH">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_STOPPED">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_SWITCHOVER">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_LOCKED">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MAX_I_JITTER">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_O_JITTER">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_POWER">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_PHASE_ALIGNMENT">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_POWER_DOWN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_RESET">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SAFE_CLOCK_STARTUP">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SPREAD_SPECTRUM">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_STATUS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k410t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.ASSOCIATED_BUSIF" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.ASSOCIATED_RESET" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.FREQ_HZ" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.PHASE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.ASSOCIATED_BUSIF" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.ASSOCIATED_RESET" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.CLK_DOMAIN" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.FREQ_HZ" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.PHASE" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKIN1_JITTER_PS" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_JITTER" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKIN1_PERIOD" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKIN2_PERIOD" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PRIM_IN_FREQ" xilinx:valueSource="user" xilinx:valuePermission="bd_and_user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PRIM_SOURCE" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.USE_LOCKED" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.USE_RESET" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>

projects/dl814_k7/common_ipi-bd/basic_driver_bd/ip/system_bd_clk_wiz_25M_0/system_bd_clk_wiz_25M_0.xdc

@@ -0,0 +1,60 @@
+
+# file: system_bd_clk_wiz_25M_0.xdc
+# 
+# (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+# Input clock periods. These duplicate the values entered for the
+# input clocks. You can use these to time your system. If required
+# commented constraints can be used in the top level xdc 
+#----------------------------------------------------------------
+# Connect to input port when clock capable pin is selected for input
+create_clock -period 40.000 [get_ports clk_in1]
+set_input_jitter [get_clocks -of_objects [get_ports clk_in1]] 0.4
+
+
+set_property PHASESHIFT_MODE WAVEFORM [get_cells -hierarchical *adv*]

projects/dl814_k7/common_ipi-bd/basic_driver_bd/ip/system_bd_clk_wiz_25M_0/system_bd_clk_wiz_25M_0_board.xdc

@@ -0,0 +1,2 @@
+#--------------------Physical Constraints-----------------
+

projects/dl814_k7/common_ipi-bd/basic_driver_bd/ip/system_bd_clk_wiz_25M_0/system_bd_clk_wiz_25M_0_clk_wiz.v

@@ -0,0 +1,201 @@
+
+// file: system_bd_clk_wiz_25M_0.v
+// 
+// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+//----------------------------------------------------------------------------
+// User entered comments
+//----------------------------------------------------------------------------
+// None
+//
+//----------------------------------------------------------------------------
+//  Output     Output      Phase    Duty Cycle   Pk-to-Pk     Phase
+//   Clock     Freq (MHz)  (degrees)    (%)     Jitter (ps)  Error (ps)
+//----------------------------------------------------------------------------
+// clk_out1____25.000______0.000______50.0______401.466____245.713
+//
+//----------------------------------------------------------------------------
+// Input Clock   Freq (MHz)    Input Jitter (UI)
+//----------------------------------------------------------------------------
+// __primary______________25____________0.010
+
+`timescale 1ps/1ps
+
+module system_bd_clk_wiz_25M_0_clk_wiz 
+
+ (// Clock in ports
+  // Clock out ports
+  output        clk_out1,
+  // Status and control signals
+  output        locked,
+  input         clk_in1
+ );
+  // Input buffering
+  //------------------------------------
+wire clk_in1_system_bd_clk_wiz_25M_0;
+wire clk_in2_system_bd_clk_wiz_25M_0;
+  IBUF clkin1_ibufg
+   (.O (clk_in1_system_bd_clk_wiz_25M_0),
+    .I (clk_in1));
+
+
+
+
+  // Clocking PRIMITIVE
+  //------------------------------------
+
+  // Instantiation of the MMCM PRIMITIVE
+  //    * Unused inputs are tied off
+  //    * Unused outputs are labeled unused
+
+  wire        clk_out1_system_bd_clk_wiz_25M_0;
+  wire        clk_out2_system_bd_clk_wiz_25M_0;
+  wire        clk_out3_system_bd_clk_wiz_25M_0;
+  wire        clk_out4_system_bd_clk_wiz_25M_0;
+  wire        clk_out5_system_bd_clk_wiz_25M_0;
+  wire        clk_out6_system_bd_clk_wiz_25M_0;
+  wire        clk_out7_system_bd_clk_wiz_25M_0;
+
+  wire [15:0] do_unused;
+  wire        drdy_unused;
+  wire        psdone_unused;
+  wire        locked_int;
+  wire        clkfbout_system_bd_clk_wiz_25M_0;
+  wire        clkfbout_buf_system_bd_clk_wiz_25M_0;
+  wire        clkfboutb_unused;
+    wire clkout0b_unused;
+   wire clkout1_unused;
+   wire clkout1b_unused;
+   wire clkout2_unused;
+   wire clkout2b_unused;
+   wire clkout3_unused;
+   wire clkout3b_unused;
+   wire clkout4_unused;
+  wire        clkout5_unused;
+  wire        clkout6_unused;
+  wire        clkfbstopped_unused;
+  wire        clkinstopped_unused;
+
+  MMCME2_ADV
+  #(.BANDWIDTH            ("OPTIMIZED"),
+    .CLKOUT4_CASCADE      ("FALSE"),
+    .COMPENSATION         ("ZHOLD"),
+    .STARTUP_WAIT         ("FALSE"),
+    .DIVCLK_DIVIDE        (1),
+    .CLKFBOUT_MULT_F      (36.500),
+    .CLKFBOUT_PHASE       (0.000),
+    .CLKFBOUT_USE_FINE_PS ("FALSE"),
+    .CLKOUT0_DIVIDE_F     (36.500),
+    .CLKOUT0_PHASE        (0.000),
+    .CLKOUT0_DUTY_CYCLE   (0.500),
+    .CLKOUT0_USE_FINE_PS  ("FALSE"),
+    .CLKIN1_PERIOD        (40.000))
+  mmcm_adv_inst
+    // Output clocks
+   (
+    .CLKFBOUT            (clkfbout_system_bd_clk_wiz_25M_0),
+    .CLKFBOUTB           (clkfboutb_unused),
+    .CLKOUT0             (clk_out1_system_bd_clk_wiz_25M_0),
+    .CLKOUT0B            (clkout0b_unused),
+    .CLKOUT1             (clkout1_unused),
+    .CLKOUT1B            (clkout1b_unused),
+    .CLKOUT2             (clkout2_unused),
+    .CLKOUT2B            (clkout2b_unused),
+    .CLKOUT3             (clkout3_unused),
+    .CLKOUT3B            (clkout3b_unused),
+    .CLKOUT4             (clkout4_unused),
+    .CLKOUT5             (clkout5_unused),
+    .CLKOUT6             (clkout6_unused),
+     // Input clock control
+    .CLKFBIN             (clkfbout_buf_system_bd_clk_wiz_25M_0),
+    .CLKIN1              (clk_in1_system_bd_clk_wiz_25M_0),
+    .CLKIN2              (1'b0),
+     // Tied to always select the primary input clock
+    .CLKINSEL            (1'b1),
+    // Ports for dynamic reconfiguration
+    .DADDR               (7'h0),
+    .DCLK                (1'b0),
+    .DEN                 (1'b0),
+    .DI                  (16'h0),
+    .DO                  (do_unused),
+    .DRDY                (drdy_unused),
+    .DWE                 (1'b0),
+    // Ports for dynamic phase shift
+    .PSCLK               (1'b0),
+    .PSEN                (1'b0),
+    .PSINCDEC            (1'b0),
+    .PSDONE              (psdone_unused),
+    // Other control and status signals
+    .LOCKED              (locked_int),
+    .CLKINSTOPPED        (clkinstopped_unused),
+    .CLKFBSTOPPED        (clkfbstopped_unused),
+    .PWRDWN              (1'b0),
+    .RST                 (1'b0));
+
+  assign locked = locked_int;
+// Clock Monitor clock assigning
+//--------------------------------------
+ // Output buffering
+  //-----------------------------------
+
+  BUFG clkf_buf
+   (.O (clkfbout_buf_system_bd_clk_wiz_25M_0),
+    .I (clkfbout_system_bd_clk_wiz_25M_0));
+
+
+
+
+
+
+  BUFG clkout1_buf
+   (.O   (clk_out1),
+    .I   (clk_out1_system_bd_clk_wiz_25M_0));
+
+
+
+
+endmodule

projects/dl814_k7/common_ipi-bd/basic_driver_bd/ip/system_bd_clk_wiz_25M_0/system_bd_clk_wiz_25M_0_ooc.xdc

@@ -0,0 +1,58 @@
+
+# file: system_bd_clk_wiz_25M_0_ooc.xdc
+# 
+# (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+#################
+#DEFAULT CLOCK CONSTRAINTS
+
+############################################################
+# Clock Period Constraints                                 #
+############################################################
+#create_clock -period 40.000 [get_ports clk_in1]
+

projects/dl814_k7/common_ipi-bd/basic_driver_bd/ip/system_bd_clk_wiz_25M_0/system_bd_clk_wiz_25M_0_stub.v

@@ -0,0 +1,21 @@
+// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep  4 09:45:24 MDT 2019
+// Date        : Sat Mar 18 23:57:10 2023
+// Host        : JOSH-ASUS-Z690 running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode synth_stub -rename_top system_bd_clk_wiz_25M_0 -prefix
+//               system_bd_clk_wiz_25M_0_ system_bd_clk_wiz_25M_0_stub.v
+// Design      : system_bd_clk_wiz_25M_0
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7k410tffg900-2
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+module system_bd_clk_wiz_25M_0(clk_out1, locked, clk_in1)
+/* synthesis syn_black_box black_box_pad_pin="clk_out1,locked,clk_in1" */;
+  output clk_out1;
+  output locked;
+  input clk_in1;
+endmodule

projects/dl814_k7/common_ipi-bd/basic_driver_bd/ip/system_bd_clk_wiz_25M_0/system_bd_clk_wiz_25M_0_stub.vhdl

@@ -0,0 +1,30 @@
+-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep  4 09:45:24 MDT 2019
+-- Date        : Sat Mar 18 23:57:10 2023
+-- Host        : JOSH-ASUS-Z690 running 64-bit major release  (build 9200)
+-- Command     : write_vhdl -force -mode synth_stub -rename_top system_bd_clk_wiz_25M_0 -prefix
+--               system_bd_clk_wiz_25M_0_ system_bd_clk_wiz_25M_0_stub.vhdl
+-- Design      : system_bd_clk_wiz_25M_0
+-- Purpose     : Stub declaration of top-level module interface
+-- Device      : xc7k410tffg900-2
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity system_bd_clk_wiz_25M_0 is
+  Port ( 
+    clk_out1 : out STD_LOGIC;
+    locked : out STD_LOGIC;
+    clk_in1 : in STD_LOGIC
+  );
+
+end system_bd_clk_wiz_25M_0;
+
+architecture stub of system_bd_clk_wiz_25M_0 is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "clk_out1,locked,clk_in1";
+begin
+end;

projects/dl814_k7/common_ipi-bd/basic_driver_bd/ip/system_bd_dlmb_bram_if_cntlr_0/sim/system_bd_dlmb_bram_if_cntlr_0.vhd

@@ -0,0 +1,295 @@
+-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:lmb_bram_if_cntlr:4.0
+-- IP Revision: 16
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+LIBRARY lmb_bram_if_cntlr_v4_0_16;
+USE lmb_bram_if_cntlr_v4_0_16.lmb_bram_if_cntlr;
+
+ENTITY system_bd_dlmb_bram_if_cntlr_0 IS
+  PORT (
+    LMB_Clk : IN STD_LOGIC;
+    LMB_Rst : IN STD_LOGIC;
+    LMB_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
+    LMB_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
+    LMB_AddrStrobe : IN STD_LOGIC;
+    LMB_ReadStrobe : IN STD_LOGIC;
+    LMB_WriteStrobe : IN STD_LOGIC;
+    LMB_BE : IN STD_LOGIC_VECTOR(0 TO 3);
+    Sl_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
+    Sl_Ready : OUT STD_LOGIC;
+    Sl_Wait : OUT STD_LOGIC;
+    Sl_UE : OUT STD_LOGIC;
+    Sl_CE : OUT STD_LOGIC;
+    BRAM_Rst_A : OUT STD_LOGIC;
+    BRAM_Clk_A : OUT STD_LOGIC;
+    BRAM_Addr_A : OUT STD_LOGIC_VECTOR(0 TO 31);
+    BRAM_EN_A : OUT STD_LOGIC;
+    BRAM_WEN_A : OUT STD_LOGIC_VECTOR(0 TO 3);
+    BRAM_Dout_A : OUT STD_LOGIC_VECTOR(0 TO 31);
+    BRAM_Din_A : IN STD_LOGIC_VECTOR(0 TO 31)
+  );
+END system_bd_dlmb_bram_if_cntlr_0;
+
+ARCHITECTURE system_bd_dlmb_bram_if_cntlr_0_arch OF system_bd_dlmb_bram_if_cntlr_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_bd_dlmb_bram_if_cntlr_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT lmb_bram_if_cntlr IS
+    GENERIC (
+      C_FAMILY : STRING;
+      C_HIGHADDR : STD_LOGIC_VECTOR;
+      C_BASEADDR : STD_LOGIC_VECTOR;
+      C_NUM_LMB : INTEGER;
+      C_MASK : STD_LOGIC_VECTOR;
+      C_MASK1 : STD_LOGIC_VECTOR;
+      C_MASK2 : STD_LOGIC_VECTOR;
+      C_MASK3 : STD_LOGIC_VECTOR;
+      C_LMB_AWIDTH : INTEGER;
+      C_LMB_DWIDTH : INTEGER;
+      C_ECC : INTEGER;
+      C_INTERCONNECT : INTEGER;
+      C_FAULT_INJECT : INTEGER;
+      C_CE_FAILING_REGISTERS : INTEGER;
+      C_UE_FAILING_REGISTERS : INTEGER;
+      C_ECC_STATUS_REGISTERS : INTEGER;
+      C_ECC_ONOFF_REGISTER : INTEGER;
+      C_ECC_ONOFF_RESET_VALUE : INTEGER;
+      C_CE_COUNTER_WIDTH : INTEGER;
+      C_WRITE_ACCESS : INTEGER;
+      C_BRAM_AWIDTH : INTEGER;
+      C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
+      C_S_AXI_CTRL_DATA_WIDTH : INTEGER
+    );
+    PORT (
+      LMB_Clk : IN STD_LOGIC;
+      LMB_Rst : IN STD_LOGIC;
+      LMB_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
+      LMB_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
+      LMB_AddrStrobe : IN STD_LOGIC;
+      LMB_ReadStrobe : IN STD_LOGIC;
+      LMB_WriteStrobe : IN STD_LOGIC;
+      LMB_BE : IN STD_LOGIC_VECTOR(0 TO 3);
+      Sl_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
+      Sl_Ready : OUT STD_LOGIC;
+      Sl_Wait : OUT STD_LOGIC;
+      Sl_UE : OUT STD_LOGIC;
+      Sl_CE : OUT STD_LOGIC;
+      LMB1_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
+      LMB1_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
+      LMB1_AddrStrobe : IN STD_LOGIC;
+      LMB1_ReadStrobe : IN STD_LOGIC;
+      LMB1_WriteStrobe : IN STD_LOGIC;
+      LMB1_BE : IN STD_LOGIC_VECTOR(0 TO 3);
+      Sl1_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
+      Sl1_Ready : OUT STD_LOGIC;
+      Sl1_Wait : OUT STD_LOGIC;
+      Sl1_UE : OUT STD_LOGIC;
+      Sl1_CE : OUT STD_LOGIC;
+      LMB2_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
+      LMB2_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
+      LMB2_AddrStrobe : IN STD_LOGIC;
+      LMB2_ReadStrobe : IN STD_LOGIC;
+      LMB2_WriteStrobe : IN STD_LOGIC;
+      LMB2_BE : IN STD_LOGIC_VECTOR(0 TO 3);
+      Sl2_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
+      Sl2_Ready : OUT STD_LOGIC;
+      Sl2_Wait : OUT STD_LOGIC;
+      Sl2_UE : OUT STD_LOGIC;
+      Sl2_CE : OUT STD_LOGIC;
+      LMB3_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
+      LMB3_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
+      LMB3_AddrStrobe : IN STD_LOGIC;
+      LMB3_ReadStrobe : IN STD_LOGIC;
+      LMB3_WriteStrobe : IN STD_LOGIC;
+      LMB3_BE : IN STD_LOGIC_VECTOR(0 TO 3);
+      Sl3_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
+      Sl3_Ready : OUT STD_LOGIC;
+      Sl3_Wait : OUT STD_LOGIC;
+      Sl3_UE : OUT STD_LOGIC;
+      Sl3_CE : OUT STD_LOGIC;
+      BRAM_Rst_A : OUT STD_LOGIC;
+      BRAM_Clk_A : OUT STD_LOGIC;
+      BRAM_Addr_A : OUT STD_LOGIC_VECTOR(0 TO 31);
+      BRAM_EN_A : OUT STD_LOGIC;
+      BRAM_WEN_A : OUT STD_LOGIC_VECTOR(0 TO 3);
+      BRAM_Dout_A : OUT STD_LOGIC_VECTOR(0 TO 31);
+      BRAM_Din_A : IN STD_LOGIC_VECTOR(0 TO 31);
+      S_AXI_CTRL_ACLK : IN STD_LOGIC;
+      S_AXI_CTRL_ARESETN : IN STD_LOGIC;
+      S_AXI_CTRL_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      S_AXI_CTRL_AWVALID : IN STD_LOGIC;
+      S_AXI_CTRL_AWREADY : OUT STD_LOGIC;
+      S_AXI_CTRL_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      S_AXI_CTRL_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      S_AXI_CTRL_WVALID : IN STD_LOGIC;
+      S_AXI_CTRL_WREADY : OUT STD_LOGIC;
+      S_AXI_CTRL_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      S_AXI_CTRL_BVALID : OUT STD_LOGIC;
+      S_AXI_CTRL_BREADY : IN STD_LOGIC;
+      S_AXI_CTRL_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      S_AXI_CTRL_ARVALID : IN STD_LOGIC;
+      S_AXI_CTRL_ARREADY : OUT STD_LOGIC;
+      S_AXI_CTRL_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      S_AXI_CTRL_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      S_AXI_CTRL_RVALID : OUT STD_LOGIC;
+      S_AXI_CTRL_RREADY : IN STD_LOGIC;
+      UE : OUT STD_LOGIC;
+      CE : OUT STD_LOGIC;
+      Interrupt : OUT STD_LOGIC
+    );
+  END COMPONENT lmb_bram_if_cntlr;
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_INFO OF BRAM_Din_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT DOUT";
+  ATTRIBUTE X_INTERFACE_INFO OF BRAM_Dout_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT DIN";
+  ATTRIBUTE X_INTERFACE_INFO OF BRAM_WEN_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT WE";
+  ATTRIBUTE X_INTERFACE_INFO OF BRAM_EN_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT EN";
+  ATTRIBUTE X_INTERFACE_INFO OF BRAM_Addr_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT ADDR";
+  ATTRIBUTE X_INTERFACE_INFO OF BRAM_Clk_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT CLK";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF BRAM_Rst_A: SIGNAL IS "XIL_INTERFACENAME BRAM_PORT, MEM_SIZE 262144, MASTER_TYPE BRAM_CTRL, MEM_WIDTH 32, MEM_ECC NONE, READ_LATENCY 1";
+  ATTRIBUTE X_INTERFACE_INFO OF BRAM_Rst_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT RST";
+  ATTRIBUTE X_INTERFACE_INFO OF Sl_CE: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB CE";
+  ATTRIBUTE X_INTERFACE_INFO OF Sl_UE: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB UE";
+  ATTRIBUTE X_INTERFACE_INFO OF Sl_Wait: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB WAIT";
+  ATTRIBUTE X_INTERFACE_INFO OF Sl_Ready: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB READY";
+  ATTRIBUTE X_INTERFACE_INFO OF Sl_DBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB READDBUS";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_BE: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB BE";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB WRITESTROBE";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_ReadStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB READSTROBE";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_AddrStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB ADDRSTROBE";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteDBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB WRITEDBUS";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF LMB_ABus: SIGNAL IS "XIL_INTERFACENAME SLMB, ADDR_WIDTH 32, DATA_WIDTH 32, READ_WRITE_MODE READ_WRITE";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_ABus: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB ABUS";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF LMB_Rst: SIGNAL IS "XIL_INTERFACENAME RST.LMB_Rst, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_Rst: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.LMB_Rst RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF LMB_Clk: SIGNAL IS "XIL_INTERFACENAME CLK.LMB_Clk, ASSOCIATED_BUSIF SLMB:SLMB1:SLMB2:SLMB3, ASSOCIATED_RESET LMB_Rst, FREQ_HZ 25000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_Clk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK.LMB_Clk CLK";
+BEGIN
+  U0 : lmb_bram_if_cntlr
+    GENERIC MAP (
+      C_FAMILY => "kintex7",
+      C_HIGHADDR => X"000000000003FFFF",
+      C_BASEADDR => X"0000000000000000",
+      C_NUM_LMB => 1,
+      C_MASK => X"0000000040000000",
+      C_MASK1 => X"0000000000800000",
+      C_MASK2 => X"0000000000800000",
+      C_MASK3 => X"0000000000800000",
+      C_LMB_AWIDTH => 32,
+      C_LMB_DWIDTH => 32,
+      C_ECC => 0,
+      C_INTERCONNECT => 0,
+      C_FAULT_INJECT => 0,
+      C_CE_FAILING_REGISTERS => 0,
+      C_UE_FAILING_REGISTERS => 0,
+      C_ECC_STATUS_REGISTERS => 0,
+      C_ECC_ONOFF_REGISTER => 0,
+      C_ECC_ONOFF_RESET_VALUE => 1,
+      C_CE_COUNTER_WIDTH => 0,
+      C_WRITE_ACCESS => 2,
+      C_BRAM_AWIDTH => 32,
+      C_S_AXI_CTRL_ADDR_WIDTH => 32,
+      C_S_AXI_CTRL_DATA_WIDTH => 32
+    )
+    PORT MAP (
+      LMB_Clk => LMB_Clk,
+      LMB_Rst => LMB_Rst,
+      LMB_ABus => LMB_ABus,
+      LMB_WriteDBus => LMB_WriteDBus,
+      LMB_AddrStrobe => LMB_AddrStrobe,
+      LMB_ReadStrobe => LMB_ReadStrobe,
+      LMB_WriteStrobe => LMB_WriteStrobe,
+      LMB_BE => LMB_BE,
+      Sl_DBus => Sl_DBus,
+      Sl_Ready => Sl_Ready,
+      Sl_Wait => Sl_Wait,
+      Sl_UE => Sl_UE,
+      Sl_CE => Sl_CE,
+      LMB1_ABus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
+      LMB1_WriteDBus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
+      LMB1_AddrStrobe => '0',
+      LMB1_ReadStrobe => '0',
+      LMB1_WriteStrobe => '0',
+      LMB1_BE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
+      LMB2_ABus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
+      LMB2_WriteDBus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
+      LMB2_AddrStrobe => '0',
+      LMB2_ReadStrobe => '0',
+      LMB2_WriteStrobe => '0',
+      LMB2_BE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
+      LMB3_ABus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
+      LMB3_WriteDBus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
+      LMB3_AddrStrobe => '0',
+      LMB3_ReadStrobe => '0',
+      LMB3_WriteStrobe => '0',
+      LMB3_BE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
+      BRAM_Rst_A => BRAM_Rst_A,
+      BRAM_Clk_A => BRAM_Clk_A,
+      BRAM_Addr_A => BRAM_Addr_A,
+      BRAM_EN_A => BRAM_EN_A,
+      BRAM_WEN_A => BRAM_WEN_A,
+      BRAM_Dout_A => BRAM_Dout_A,
+      BRAM_Din_A => BRAM_Din_A,
+      S_AXI_CTRL_ACLK => '0',
+      S_AXI_CTRL_ARESETN => '0',
+      S_AXI_CTRL_AWADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
+      S_AXI_CTRL_AWVALID => '0',
+      S_AXI_CTRL_WDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
+      S_AXI_CTRL_WSTRB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
+      S_AXI_CTRL_WVALID => '0',
+      S_AXI_CTRL_BREADY => '0',
+      S_AXI_CTRL_ARADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
+      S_AXI_CTRL_ARVALID => '0',
+      S_AXI_CTRL_RREADY => '0'
+    );
+END system_bd_dlmb_bram_if_cntlr_0_arch;

projects/dl814_k7/common_ipi-bd/basic_driver_bd/ip/system_bd_dlmb_bram_if_cntlr_0/synth/system_bd_dlmb_bram_if_cntlr_0.vhd

@@ -0,0 +1,302 @@
+-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:lmb_bram_if_cntlr:4.0
+-- IP Revision: 16
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+LIBRARY lmb_bram_if_cntlr_v4_0_16;
+USE lmb_bram_if_cntlr_v4_0_16.lmb_bram_if_cntlr;
+
+ENTITY system_bd_dlmb_bram_if_cntlr_0 IS
+  PORT (
+    LMB_Clk : IN STD_LOGIC;
+    LMB_Rst : IN STD_LOGIC;
+    LMB_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
+    LMB_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
+    LMB_AddrStrobe : IN STD_LOGIC;
+    LMB_ReadStrobe : IN STD_LOGIC;
+    LMB_WriteStrobe : IN STD_LOGIC;
+    LMB_BE : IN STD_LOGIC_VECTOR(0 TO 3);
+    Sl_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
+    Sl_Ready : OUT STD_LOGIC;
+    Sl_Wait : OUT STD_LOGIC;
+    Sl_UE : OUT STD_LOGIC;
+    Sl_CE : OUT STD_LOGIC;
+    BRAM_Rst_A : OUT STD_LOGIC;
+    BRAM_Clk_A : OUT STD_LOGIC;
+    BRAM_Addr_A : OUT STD_LOGIC_VECTOR(0 TO 31);
+    BRAM_EN_A : OUT STD_LOGIC;
+    BRAM_WEN_A : OUT STD_LOGIC_VECTOR(0 TO 3);
+    BRAM_Dout_A : OUT STD_LOGIC_VECTOR(0 TO 31);
+    BRAM_Din_A : IN STD_LOGIC_VECTOR(0 TO 31)
+  );
+END system_bd_dlmb_bram_if_cntlr_0;
+
+ARCHITECTURE system_bd_dlmb_bram_if_cntlr_0_arch OF system_bd_dlmb_bram_if_cntlr_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_bd_dlmb_bram_if_cntlr_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT lmb_bram_if_cntlr IS
+    GENERIC (
+      C_FAMILY : STRING;
+      C_HIGHADDR : STD_LOGIC_VECTOR;
+      C_BASEADDR : STD_LOGIC_VECTOR;
+      C_NUM_LMB : INTEGER;
+      C_MASK : STD_LOGIC_VECTOR;
+      C_MASK1 : STD_LOGIC_VECTOR;
+      C_MASK2 : STD_LOGIC_VECTOR;
+      C_MASK3 : STD_LOGIC_VECTOR;
+      C_LMB_AWIDTH : INTEGER;
+      C_LMB_DWIDTH : INTEGER;
+      C_ECC : INTEGER;
+      C_INTERCONNECT : INTEGER;
+      C_FAULT_INJECT : INTEGER;
+      C_CE_FAILING_REGISTERS : INTEGER;
+      C_UE_FAILING_REGISTERS : INTEGER;
+      C_ECC_STATUS_REGISTERS : INTEGER;
+      C_ECC_ONOFF_REGISTER : INTEGER;
+      C_ECC_ONOFF_RESET_VALUE : INTEGER;
+      C_CE_COUNTER_WIDTH : INTEGER;
+      C_WRITE_ACCESS : INTEGER;
+      C_BRAM_AWIDTH : INTEGER;
+      C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
+      C_S_AXI_CTRL_DATA_WIDTH : INTEGER
+    );
+    PORT (
+      LMB_Clk : IN STD_LOGIC;
+      LMB_Rst : IN STD_LOGIC;
+      LMB_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
+      LMB_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
+      LMB_AddrStrobe : IN STD_LOGIC;
+      LMB_ReadStrobe : IN STD_LOGIC;
+      LMB_WriteStrobe : IN STD_LOGIC;
+      LMB_BE : IN STD_LOGIC_VECTOR(0 TO 3);
+      Sl_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
+      Sl_Ready : OUT STD_LOGIC;
+      Sl_Wait : OUT STD_LOGIC;
+      Sl_UE : OUT STD_LOGIC;
+      Sl_CE : OUT STD_LOGIC;
+      LMB1_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
+      LMB1_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
+      LMB1_AddrStrobe : IN STD_LOGIC;
+      LMB1_ReadStrobe : IN STD_LOGIC;
+      LMB1_WriteStrobe : IN STD_LOGIC;
+      LMB1_BE : IN STD_LOGIC_VECTOR(0 TO 3);
+      Sl1_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
+      Sl1_Ready : OUT STD_LOGIC;
+      Sl1_Wait : OUT STD_LOGIC;
+      Sl1_UE : OUT STD_LOGIC;
+      Sl1_CE : OUT STD_LOGIC;
+      LMB2_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
+      LMB2_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
+      LMB2_AddrStrobe : IN STD_LOGIC;
+      LMB2_ReadStrobe : IN STD_LOGIC;
+      LMB2_WriteStrobe : IN STD_LOGIC;
+      LMB2_BE : IN STD_LOGIC_VECTOR(0 TO 3);
+      Sl2_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
+      Sl2_Ready : OUT STD_LOGIC;
+      Sl2_Wait : OUT STD_LOGIC;
+      Sl2_UE : OUT STD_LOGIC;
+      Sl2_CE : OUT STD_LOGIC;
+      LMB3_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
+      LMB3_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
+      LMB3_AddrStrobe : IN STD_LOGIC;
+      LMB3_ReadStrobe : IN STD_LOGIC;
+      LMB3_WriteStrobe : IN STD_LOGIC;
+      LMB3_BE : IN STD_LOGIC_VECTOR(0 TO 3);
+      Sl3_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
+      Sl3_Ready : OUT STD_LOGIC;
+      Sl3_Wait : OUT STD_LOGIC;
+      Sl3_UE : OUT STD_LOGIC;
+      Sl3_CE : OUT STD_LOGIC;
+      BRAM_Rst_A : OUT STD_LOGIC;
+      BRAM_Clk_A : OUT STD_LOGIC;
+      BRAM_Addr_A : OUT STD_LOGIC_VECTOR(0 TO 31);
+      BRAM_EN_A : OUT STD_LOGIC;
+      BRAM_WEN_A : OUT STD_LOGIC_VECTOR(0 TO 3);
+      BRAM_Dout_A : OUT STD_LOGIC_VECTOR(0 TO 31);
+      BRAM_Din_A : IN STD_LOGIC_VECTOR(0 TO 31);
+      S_AXI_CTRL_ACLK : IN STD_LOGIC;
+      S_AXI_CTRL_ARESETN : IN STD_LOGIC;
+      S_AXI_CTRL_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      S_AXI_CTRL_AWVALID : IN STD_LOGIC;
+      S_AXI_CTRL_AWREADY : OUT STD_LOGIC;
+      S_AXI_CTRL_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      S_AXI_CTRL_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      S_AXI_CTRL_WVALID : IN STD_LOGIC;
+      S_AXI_CTRL_WREADY : OUT STD_LOGIC;
+      S_AXI_CTRL_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      S_AXI_CTRL_BVALID : OUT STD_LOGIC;
+      S_AXI_CTRL_BREADY : IN STD_LOGIC;
+      S_AXI_CTRL_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      S_AXI_CTRL_ARVALID : IN STD_LOGIC;
+      S_AXI_CTRL_ARREADY : OUT STD_LOGIC;
+      S_AXI_CTRL_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      S_AXI_CTRL_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      S_AXI_CTRL_RVALID : OUT STD_LOGIC;
+      S_AXI_CTRL_RREADY : IN STD_LOGIC;
+      UE : OUT STD_LOGIC;
+      CE : OUT STD_LOGIC;
+      Interrupt : OUT STD_LOGIC
+    );
+  END COMPONENT lmb_bram_if_cntlr;
+  ATTRIBUTE X_CORE_INFO : STRING;
+  ATTRIBUTE X_CORE_INFO OF system_bd_dlmb_bram_if_cntlr_0_arch: ARCHITECTURE IS "lmb_bram_if_cntlr,Vivado 2019.1.3";
+  ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
+  ATTRIBUTE CHECK_LICENSE_TYPE OF system_bd_dlmb_bram_if_cntlr_0_arch : ARCHITECTURE IS "system_bd_dlmb_bram_if_cntlr_0,lmb_bram_if_cntlr,{}";
+  ATTRIBUTE CORE_GENERATION_INFO : STRING;
+  ATTRIBUTE CORE_GENERATION_INFO OF system_bd_dlmb_bram_if_cntlr_0_arch: ARCHITECTURE IS "system_bd_dlmb_bram_if_cntlr_0,lmb_bram_if_cntlr,{x_ipProduct=Vivado 2019.1.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=lmb_bram_if_cntlr,x_ipVersion=4.0,x_ipCoreRevision=16,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=kintex7,C_HIGHADDR=0x000000000003FFFF,C_BASEADDR=0x0000000000000000,C_NUM_LMB=1,C_MASK=0x0000000040000000,C_MASK1=0x0000000000800000,C_MASK2=0x0000000000800000,C_MASK3=0x0000000000800000,C_LMB_AWIDTH=32,C_LMB_DWIDTH=32,C_ECC=0,C_INTERCONNECT=0,C_FAULT_INJECT=0,C_CE_FAIL" & 
+"ING_REGISTERS=0,C_UE_FAILING_REGISTERS=0,C_ECC_STATUS_REGISTERS=0,C_ECC_ONOFF_REGISTER=0,C_ECC_ONOFF_RESET_VALUE=1,C_CE_COUNTER_WIDTH=0,C_WRITE_ACCESS=2,C_BRAM_AWIDTH=32,C_S_AXI_CTRL_ADDR_WIDTH=32,C_S_AXI_CTRL_DATA_WIDTH=32}";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_INFO OF BRAM_Din_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT DOUT";
+  ATTRIBUTE X_INTERFACE_INFO OF BRAM_Dout_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT DIN";
+  ATTRIBUTE X_INTERFACE_INFO OF BRAM_WEN_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT WE";
+  ATTRIBUTE X_INTERFACE_INFO OF BRAM_EN_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT EN";
+  ATTRIBUTE X_INTERFACE_INFO OF BRAM_Addr_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT ADDR";
+  ATTRIBUTE X_INTERFACE_INFO OF BRAM_Clk_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT CLK";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF BRAM_Rst_A: SIGNAL IS "XIL_INTERFACENAME BRAM_PORT, MEM_SIZE 262144, MASTER_TYPE BRAM_CTRL, MEM_WIDTH 32, MEM_ECC NONE, READ_LATENCY 1";
+  ATTRIBUTE X_INTERFACE_INFO OF BRAM_Rst_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT RST";
+  ATTRIBUTE X_INTERFACE_INFO OF Sl_CE: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB CE";
+  ATTRIBUTE X_INTERFACE_INFO OF Sl_UE: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB UE";
+  ATTRIBUTE X_INTERFACE_INFO OF Sl_Wait: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB WAIT";
+  ATTRIBUTE X_INTERFACE_INFO OF Sl_Ready: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB READY";
+  ATTRIBUTE X_INTERFACE_INFO OF Sl_DBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB READDBUS";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_BE: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB BE";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB WRITESTROBE";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_ReadStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB READSTROBE";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_AddrStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB ADDRSTROBE";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteDBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB WRITEDBUS";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF LMB_ABus: SIGNAL IS "XIL_INTERFACENAME SLMB, ADDR_WIDTH 32, DATA_WIDTH 32, READ_WRITE_MODE READ_WRITE";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_ABus: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB ABUS";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF LMB_Rst: SIGNAL IS "XIL_INTERFACENAME RST.LMB_Rst, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_Rst: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.LMB_Rst RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF LMB_Clk: SIGNAL IS "XIL_INTERFACENAME CLK.LMB_Clk, ASSOCIATED_BUSIF SLMB:SLMB1:SLMB2:SLMB3, ASSOCIATED_RESET LMB_Rst, FREQ_HZ 25000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_Clk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK.LMB_Clk CLK";
+BEGIN
+  U0 : lmb_bram_if_cntlr
+    GENERIC MAP (
+      C_FAMILY => "kintex7",
+      C_HIGHADDR => X"000000000003FFFF",
+      C_BASEADDR => X"0000000000000000",
+      C_NUM_LMB => 1,
+      C_MASK => X"0000000040000000",
+      C_MASK1 => X"0000000000800000",
+      C_MASK2 => X"0000000000800000",
+      C_MASK3 => X"0000000000800000",
+      C_LMB_AWIDTH => 32,
+      C_LMB_DWIDTH => 32,
+      C_ECC => 0,
+      C_INTERCONNECT => 0,
+      C_FAULT_INJECT => 0,
+      C_CE_FAILING_REGISTERS => 0,
+      C_UE_FAILING_REGISTERS => 0,
+      C_ECC_STATUS_REGISTERS => 0,
+      C_ECC_ONOFF_REGISTER => 0,
+      C_ECC_ONOFF_RESET_VALUE => 1,
+      C_CE_COUNTER_WIDTH => 0,
+      C_WRITE_ACCESS => 2,
+      C_BRAM_AWIDTH => 32,
+      C_S_AXI_CTRL_ADDR_WIDTH => 32,
+      C_S_AXI_CTRL_DATA_WIDTH => 32
+    )
+    PORT MAP (
+      LMB_Clk => LMB_Clk,
+      LMB_Rst => LMB_Rst,
+      LMB_ABus => LMB_ABus,
+      LMB_WriteDBus => LMB_WriteDBus,
+      LMB_AddrStrobe => LMB_AddrStrobe,
+      LMB_ReadStrobe => LMB_ReadStrobe,
+      LMB_WriteStrobe => LMB_WriteStrobe,
+      LMB_BE => LMB_BE,
+      Sl_DBus => Sl_DBus,
+      Sl_Ready => Sl_Ready,
+      Sl_Wait => Sl_Wait,
+      Sl_UE => Sl_UE,
+      Sl_CE => Sl_CE,
+      LMB1_ABus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
+      LMB1_WriteDBus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
+      LMB1_AddrStrobe => '0',
+      LMB1_ReadStrobe => '0',
+      LMB1_WriteStrobe => '0',
+      LMB1_BE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
+      LMB2_ABus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
+      LMB2_WriteDBus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
+      LMB2_AddrStrobe => '0',
+      LMB2_ReadStrobe => '0',
+      LMB2_WriteStrobe => '0',
+      LMB2_BE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
+      LMB3_ABus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
+      LMB3_WriteDBus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
+      LMB3_AddrStrobe => '0',
+      LMB3_ReadStrobe => '0',
+      LMB3_WriteStrobe => '0',
+      LMB3_BE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
+      BRAM_Rst_A => BRAM_Rst_A,
+      BRAM_Clk_A => BRAM_Clk_A,
+      BRAM_Addr_A => BRAM_Addr_A,
+      BRAM_EN_A => BRAM_EN_A,
+      BRAM_WEN_A => BRAM_WEN_A,
+      BRAM_Dout_A => BRAM_Dout_A,
+      BRAM_Din_A => BRAM_Din_A,
+      S_AXI_CTRL_ACLK => '0',
+      S_AXI_CTRL_ARESETN => '0',
+      S_AXI_CTRL_AWADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
+      S_AXI_CTRL_AWVALID => '0',
+      S_AXI_CTRL_WDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
+      S_AXI_CTRL_WSTRB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
+      S_AXI_CTRL_WVALID => '0',
+      S_AXI_CTRL_BREADY => '0',
+      S_AXI_CTRL_ARADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
+      S_AXI_CTRL_ARVALID => '0',
+      S_AXI_CTRL_RREADY => '0'
+    );
+END system_bd_dlmb_bram_if_cntlr_0_arch;

projects/dl814_k7/common_ipi-bd/basic_driver_bd/ip/system_bd_dlmb_bram_if_cntlr_0/system_bd_dlmb_bram_if_cntlr_0.xci

@@ -0,0 +1,164 @@
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_MASK2">0x0000000000800000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_MASK3">0x0000000000800000</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k410t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.MEM_ECC" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.MEM_SIZE" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.MEM_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
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+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.READ_WRITE_MODE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.CLK_DOMAIN" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_HZ" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.PHASE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLMB.ADDR_WIDTH" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLMB.DATA_WIDTH" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_BASEADDR" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_ECC" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_HIGHADDR" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_AWIDTH" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_DWIDTH" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_MASK" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>

projects/dl814_k7/common_ipi-bd/basic_driver_bd/ip/system_bd_dlmb_bram_if_cntlr_0/system_bd_dlmb_bram_if_cntlr_0_ooc.xdc

@@ -0,0 +1,57 @@
+# (c) Copyright 2012-2023 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+# DO NOT MODIFY THIS FILE.
+# #########################################################
+#
+# This XDC is used only in OOC mode for synthesis, implementation
+#
+# #########################################################
+
+
+create_clock -period 40 -name LMB_Clk [get_ports LMB_Clk]
+
+

projects/dl814_k7/common_ipi-bd/basic_driver_bd/ip/system_bd_dlmb_bram_if_cntlr_0/system_bd_dlmb_bram_if_cntlr_0_stub.v

@@ -0,0 +1,41 @@
+// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep  4 09:45:24 MDT 2019
+// Date        : Sat Mar 18 23:57:09 2023
+// Host        : JOSH-ASUS-Z690 running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode synth_stub -rename_top system_bd_dlmb_bram_if_cntlr_0 -prefix
+//               system_bd_dlmb_bram_if_cntlr_0_ system_bd_dlmb_bram_if_cntlr_0_stub.v
+// Design      : system_bd_dlmb_bram_if_cntlr_0
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7k410tffg900-2
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* x_core_info = "lmb_bram_if_cntlr,Vivado 2019.1.3" *)
+module system_bd_dlmb_bram_if_cntlr_0(LMB_Clk, LMB_Rst, LMB_ABus, LMB_WriteDBus, 
+  LMB_AddrStrobe, LMB_ReadStrobe, LMB_WriteStrobe, LMB_BE, Sl_DBus, Sl_Ready, Sl_Wait, Sl_UE, 
+  Sl_CE, BRAM_Rst_A, BRAM_Clk_A, BRAM_Addr_A, BRAM_EN_A, BRAM_WEN_A, BRAM_Dout_A, BRAM_Din_A)
+/* synthesis syn_black_box black_box_pad_pin="LMB_Clk,LMB_Rst,LMB_ABus[0:31],LMB_WriteDBus[0:31],LMB_AddrStrobe,LMB_ReadStrobe,LMB_WriteStrobe,LMB_BE[0:3],Sl_DBus[0:31],Sl_Ready,Sl_Wait,Sl_UE,Sl_CE,BRAM_Rst_A,BRAM_Clk_A,BRAM_Addr_A[0:31],BRAM_EN_A,BRAM_WEN_A[0:3],BRAM_Dout_A[0:31],BRAM_Din_A[0:31]" */;
+  input LMB_Clk;
+  input LMB_Rst;
+  input [0:31]LMB_ABus;
+  input [0:31]LMB_WriteDBus;
+  input LMB_AddrStrobe;
+  input LMB_ReadStrobe;
+  input LMB_WriteStrobe;
+  input [0:3]LMB_BE;
+  output [0:31]Sl_DBus;
+  output Sl_Ready;
+  output Sl_Wait;
+  output Sl_UE;
+  output Sl_CE;
+  output BRAM_Rst_A;
+  output BRAM_Clk_A;
+  output [0:31]BRAM_Addr_A;
+  output BRAM_EN_A;
+  output [0:3]BRAM_WEN_A;
+  output [0:31]BRAM_Dout_A;
+  input [0:31]BRAM_Din_A;
+endmodule

projects/dl814_k7/common_ipi-bd/basic_driver_bd/ip/system_bd_dlmb_bram_if_cntlr_0/system_bd_dlmb_bram_if_cntlr_0_stub.vhdl

@@ -0,0 +1,49 @@
+-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep  4 09:45:24 MDT 2019
+-- Date        : Sat Mar 18 23:57:09 2023
+-- Host        : JOSH-ASUS-Z690 running 64-bit major release  (build 9200)
+-- Command     : write_vhdl -force -mode synth_stub -rename_top system_bd_dlmb_bram_if_cntlr_0 -prefix
+--               system_bd_dlmb_bram_if_cntlr_0_ system_bd_dlmb_bram_if_cntlr_0_stub.vhdl
+-- Design      : system_bd_dlmb_bram_if_cntlr_0
+-- Purpose     : Stub declaration of top-level module interface
+-- Device      : xc7k410tffg900-2
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity system_bd_dlmb_bram_if_cntlr_0 is
+  Port ( 
+    LMB_Clk : in STD_LOGIC;
+    LMB_Rst : in STD_LOGIC;
+    LMB_ABus : in STD_LOGIC_VECTOR ( 0 to 31 );
+    LMB_WriteDBus : in STD_LOGIC_VECTOR ( 0 to 31 );
+    LMB_AddrStrobe : in STD_LOGIC;
+    LMB_ReadStrobe : in STD_LOGIC;
+    LMB_WriteStrobe : in STD_LOGIC;
+    LMB_BE : in STD_LOGIC_VECTOR ( 0 to 3 );
+    Sl_DBus : out STD_LOGIC_VECTOR ( 0 to 31 );
+    Sl_Ready : out STD_LOGIC;
+    Sl_Wait : out STD_LOGIC;
+    Sl_UE : out STD_LOGIC;
+    Sl_CE : out STD_LOGIC;
+    BRAM_Rst_A : out STD_LOGIC;
+    BRAM_Clk_A : out STD_LOGIC;
+    BRAM_Addr_A : out STD_LOGIC_VECTOR ( 0 to 31 );
+    BRAM_EN_A : out STD_LOGIC;
+    BRAM_WEN_A : out STD_LOGIC_VECTOR ( 0 to 3 );
+    BRAM_Dout_A : out STD_LOGIC_VECTOR ( 0 to 31 );
+    BRAM_Din_A : in STD_LOGIC_VECTOR ( 0 to 31 )
+  );
+
+end system_bd_dlmb_bram_if_cntlr_0;
+
+architecture stub of system_bd_dlmb_bram_if_cntlr_0 is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "LMB_Clk,LMB_Rst,LMB_ABus[0:31],LMB_WriteDBus[0:31],LMB_AddrStrobe,LMB_ReadStrobe,LMB_WriteStrobe,LMB_BE[0:3],Sl_DBus[0:31],Sl_Ready,Sl_Wait,Sl_UE,Sl_CE,BRAM_Rst_A,BRAM_Clk_A,BRAM_Addr_A[0:31],BRAM_EN_A,BRAM_WEN_A[0:3],BRAM_Dout_A[0:31],BRAM_Din_A[0:31]";
+attribute x_core_info : string;
+attribute x_core_info of stub : architecture is "lmb_bram_if_cntlr,Vivado 2019.1.3";
+begin
+end;

projects/dl814_k7/common_ipi-bd/basic_driver_bd/ip/system_bd_dlmb_v10_0/sim/system_bd_dlmb_v10_0.vhd

@@ -0,0 +1,192 @@
+-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:lmb_v10:3.0
+-- IP Revision: 9
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+LIBRARY lmb_v10_v3_0_9;
+USE lmb_v10_v3_0_9.lmb_v10;
+
+ENTITY system_bd_dlmb_v10_0 IS
+  PORT (
+    LMB_Clk : IN STD_LOGIC;
+    SYS_Rst : IN STD_LOGIC;
+    LMB_Rst : OUT STD_LOGIC;
+    M_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
+    M_ReadStrobe : IN STD_LOGIC;
+    M_WriteStrobe : IN STD_LOGIC;
+    M_AddrStrobe : IN STD_LOGIC;
+    M_DBus : IN STD_LOGIC_VECTOR(0 TO 31);
+    M_BE : IN STD_LOGIC_VECTOR(0 TO 3);
+    Sl_DBus : IN STD_LOGIC_VECTOR(0 TO 31);
+    Sl_Ready : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    Sl_Wait : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    Sl_UE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    Sl_CE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    LMB_ABus : OUT STD_LOGIC_VECTOR(0 TO 31);
+    LMB_ReadStrobe : OUT STD_LOGIC;
+    LMB_WriteStrobe : OUT STD_LOGIC;
+    LMB_AddrStrobe : OUT STD_LOGIC;
+    LMB_ReadDBus : OUT STD_LOGIC_VECTOR(0 TO 31);
+    LMB_WriteDBus : OUT STD_LOGIC_VECTOR(0 TO 31);
+    LMB_Ready : OUT STD_LOGIC;
+    LMB_Wait : OUT STD_LOGIC;
+    LMB_UE : OUT STD_LOGIC;
+    LMB_CE : OUT STD_LOGIC;
+    LMB_BE : OUT STD_LOGIC_VECTOR(0 TO 3)
+  );
+END system_bd_dlmb_v10_0;
+
+ARCHITECTURE system_bd_dlmb_v10_0_arch OF system_bd_dlmb_v10_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_bd_dlmb_v10_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT lmb_v10 IS
+    GENERIC (
+      C_LMB_NUM_SLAVES : INTEGER;
+      C_LMB_DWIDTH : INTEGER;
+      C_LMB_AWIDTH : INTEGER;
+      C_EXT_RESET_HIGH : INTEGER
+    );
+    PORT (
+      LMB_Clk : IN STD_LOGIC;
+      SYS_Rst : IN STD_LOGIC;
+      LMB_Rst : OUT STD_LOGIC;
+      M_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
+      M_ReadStrobe : IN STD_LOGIC;
+      M_WriteStrobe : IN STD_LOGIC;
+      M_AddrStrobe : IN STD_LOGIC;
+      M_DBus : IN STD_LOGIC_VECTOR(0 TO 31);
+      M_BE : IN STD_LOGIC_VECTOR(0 TO 3);
+      Sl_DBus : IN STD_LOGIC_VECTOR(0 TO 31);
+      Sl_Ready : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      Sl_Wait : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      Sl_UE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      Sl_CE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      LMB_ABus : OUT STD_LOGIC_VECTOR(0 TO 31);
+      LMB_ReadStrobe : OUT STD_LOGIC;
+      LMB_WriteStrobe : OUT STD_LOGIC;
+      LMB_AddrStrobe : OUT STD_LOGIC;
+      LMB_ReadDBus : OUT STD_LOGIC_VECTOR(0 TO 31);
+      LMB_WriteDBus : OUT STD_LOGIC_VECTOR(0 TO 31);
+      LMB_Ready : OUT STD_LOGIC;
+      LMB_Wait : OUT STD_LOGIC;
+      LMB_UE : OUT STD_LOGIC;
+      LMB_CE : OUT STD_LOGIC;
+      LMB_BE : OUT STD_LOGIC_VECTOR(0 TO 3)
+    );
+  END COMPONENT lmb_v10;
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_BE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 BE";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_CE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M CE";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_UE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M UE";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_Wait: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M WAIT";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_Ready: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M READY";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteDBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 WRITEDBUS";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_ReadDBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M READDBUS";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_AddrStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 ADDRSTROBE";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 WRITESTROBE";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_ReadStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 READSTROBE";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_ABus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 ABUS";
+  ATTRIBUTE X_INTERFACE_INFO OF Sl_CE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 CE";
+  ATTRIBUTE X_INTERFACE_INFO OF Sl_UE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 UE";
+  ATTRIBUTE X_INTERFACE_INFO OF Sl_Wait: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 WAIT";
+  ATTRIBUTE X_INTERFACE_INFO OF Sl_Ready: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 READY";
+  ATTRIBUTE X_INTERFACE_INFO OF Sl_DBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 READDBUS";
+  ATTRIBUTE X_INTERFACE_INFO OF M_BE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M BE";
+  ATTRIBUTE X_INTERFACE_INFO OF M_DBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M WRITEDBUS";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AddrStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M ADDRSTROBE";
+  ATTRIBUTE X_INTERFACE_INFO OF M_WriteStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M WRITESTROBE";
+  ATTRIBUTE X_INTERFACE_INFO OF M_ReadStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M READSTROBE";
+  ATTRIBUTE X_INTERFACE_INFO OF M_ABus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M ABUS";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF LMB_Rst: SIGNAL IS "XIL_INTERFACENAME LMB_Sl_0, ADDR_WIDTH 32, DATA_WIDTH 32, READ_WRITE_MODE READ_WRITE, XIL_INTERFACENAME LMB_M, ADDR_WIDTH 32, DATA_WIDTH 32, READ_WRITE_MODE READ_WRITE";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_Rst: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 RST, xilinx.com:interface:lmb:1.0 LMB_M RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF SYS_Rst: SIGNAL IS "XIL_INTERFACENAME RST.SYS_Rst, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF SYS_Rst: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.SYS_Rst RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF LMB_Clk: SIGNAL IS "XIL_INTERFACENAME CLK.LMB_Clk, ASSOCIATED_BUSIF LMB_Sl_0:LMB_Sl_1:LMB_Sl_2:LMB_Sl_3:LMB_Sl_4:LMB_Sl_5:LMB_Sl_6:LMB_Sl_7:LMB_Sl_8:LMB_Sl_9:LMB_Sl_10:LMB_Sl_11:LMB_Sl_12:LMB_Sl_13:LMB_Sl_14:LMB_Sl_15:LMB_M, ASSOCIATED_RESET SYS_Rst, FREQ_HZ 25000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_Clk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK.LMB_Clk CLK";
+BEGIN
+  U0 : lmb_v10
+    GENERIC MAP (
+      C_LMB_NUM_SLAVES => 1,
+      C_LMB_DWIDTH => 32,
+      C_LMB_AWIDTH => 32,
+      C_EXT_RESET_HIGH => 1
+    )
+    PORT MAP (
+      LMB_Clk => LMB_Clk,
+      SYS_Rst => SYS_Rst,
+      LMB_Rst => LMB_Rst,
+      M_ABus => M_ABus,
+      M_ReadStrobe => M_ReadStrobe,
+      M_WriteStrobe => M_WriteStrobe,
+      M_AddrStrobe => M_AddrStrobe,
+      M_DBus => M_DBus,
+      M_BE => M_BE,
+      Sl_DBus => Sl_DBus,
+      Sl_Ready => Sl_Ready,
+      Sl_Wait => Sl_Wait,
+      Sl_UE => Sl_UE,
+      Sl_CE => Sl_CE,
+      LMB_ABus => LMB_ABus,
+      LMB_ReadStrobe => LMB_ReadStrobe,
+      LMB_WriteStrobe => LMB_WriteStrobe,
+      LMB_AddrStrobe => LMB_AddrStrobe,
+      LMB_ReadDBus => LMB_ReadDBus,
+      LMB_WriteDBus => LMB_WriteDBus,
+      LMB_Ready => LMB_Ready,
+      LMB_Wait => LMB_Wait,
+      LMB_UE => LMB_UE,
+      LMB_CE => LMB_CE,
+      LMB_BE => LMB_BE
+    );
+END system_bd_dlmb_v10_0_arch;

projects/dl814_k7/common_ipi-bd/basic_driver_bd/ip/system_bd_dlmb_v10_0/synth/system_bd_dlmb_v10_0.vhd

@@ -0,0 +1,198 @@
+-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:lmb_v10:3.0
+-- IP Revision: 9
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+LIBRARY lmb_v10_v3_0_9;
+USE lmb_v10_v3_0_9.lmb_v10;
+
+ENTITY system_bd_dlmb_v10_0 IS
+  PORT (
+    LMB_Clk : IN STD_LOGIC;
+    SYS_Rst : IN STD_LOGIC;
+    LMB_Rst : OUT STD_LOGIC;
+    M_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
+    M_ReadStrobe : IN STD_LOGIC;
+    M_WriteStrobe : IN STD_LOGIC;
+    M_AddrStrobe : IN STD_LOGIC;
+    M_DBus : IN STD_LOGIC_VECTOR(0 TO 31);
+    M_BE : IN STD_LOGIC_VECTOR(0 TO 3);
+    Sl_DBus : IN STD_LOGIC_VECTOR(0 TO 31);
+    Sl_Ready : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    Sl_Wait : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    Sl_UE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    Sl_CE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    LMB_ABus : OUT STD_LOGIC_VECTOR(0 TO 31);
+    LMB_ReadStrobe : OUT STD_LOGIC;
+    LMB_WriteStrobe : OUT STD_LOGIC;
+    LMB_AddrStrobe : OUT STD_LOGIC;
+    LMB_ReadDBus : OUT STD_LOGIC_VECTOR(0 TO 31);
+    LMB_WriteDBus : OUT STD_LOGIC_VECTOR(0 TO 31);
+    LMB_Ready : OUT STD_LOGIC;
+    LMB_Wait : OUT STD_LOGIC;
+    LMB_UE : OUT STD_LOGIC;
+    LMB_CE : OUT STD_LOGIC;
+    LMB_BE : OUT STD_LOGIC_VECTOR(0 TO 3)
+  );
+END system_bd_dlmb_v10_0;
+
+ARCHITECTURE system_bd_dlmb_v10_0_arch OF system_bd_dlmb_v10_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_bd_dlmb_v10_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT lmb_v10 IS
+    GENERIC (
+      C_LMB_NUM_SLAVES : INTEGER;
+      C_LMB_DWIDTH : INTEGER;
+      C_LMB_AWIDTH : INTEGER;
+      C_EXT_RESET_HIGH : INTEGER
+    );
+    PORT (
+      LMB_Clk : IN STD_LOGIC;
+      SYS_Rst : IN STD_LOGIC;
+      LMB_Rst : OUT STD_LOGIC;
+      M_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
+      M_ReadStrobe : IN STD_LOGIC;
+      M_WriteStrobe : IN STD_LOGIC;
+      M_AddrStrobe : IN STD_LOGIC;
+      M_DBus : IN STD_LOGIC_VECTOR(0 TO 31);
+      M_BE : IN STD_LOGIC_VECTOR(0 TO 3);
+      Sl_DBus : IN STD_LOGIC_VECTOR(0 TO 31);
+      Sl_Ready : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      Sl_Wait : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      Sl_UE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      Sl_CE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      LMB_ABus : OUT STD_LOGIC_VECTOR(0 TO 31);
+      LMB_ReadStrobe : OUT STD_LOGIC;
+      LMB_WriteStrobe : OUT STD_LOGIC;
+      LMB_AddrStrobe : OUT STD_LOGIC;
+      LMB_ReadDBus : OUT STD_LOGIC_VECTOR(0 TO 31);
+      LMB_WriteDBus : OUT STD_LOGIC_VECTOR(0 TO 31);
+      LMB_Ready : OUT STD_LOGIC;
+      LMB_Wait : OUT STD_LOGIC;
+      LMB_UE : OUT STD_LOGIC;
+      LMB_CE : OUT STD_LOGIC;
+      LMB_BE : OUT STD_LOGIC_VECTOR(0 TO 3)
+    );
+  END COMPONENT lmb_v10;
+  ATTRIBUTE X_CORE_INFO : STRING;
+  ATTRIBUTE X_CORE_INFO OF system_bd_dlmb_v10_0_arch: ARCHITECTURE IS "lmb_v10,Vivado 2019.1.3";
+  ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
+  ATTRIBUTE CHECK_LICENSE_TYPE OF system_bd_dlmb_v10_0_arch : ARCHITECTURE IS "system_bd_dlmb_v10_0,lmb_v10,{}";
+  ATTRIBUTE CORE_GENERATION_INFO : STRING;
+  ATTRIBUTE CORE_GENERATION_INFO OF system_bd_dlmb_v10_0_arch: ARCHITECTURE IS "system_bd_dlmb_v10_0,lmb_v10,{x_ipProduct=Vivado 2019.1.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=lmb_v10,x_ipVersion=3.0,x_ipCoreRevision=9,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_LMB_NUM_SLAVES=1,C_LMB_DWIDTH=32,C_LMB_AWIDTH=32,C_EXT_RESET_HIGH=1}";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_BE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 BE";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_CE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M CE";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_UE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M UE";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_Wait: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M WAIT";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_Ready: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M READY";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteDBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 WRITEDBUS";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_ReadDBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M READDBUS";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_AddrStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 ADDRSTROBE";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 WRITESTROBE";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_ReadStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 READSTROBE";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_ABus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 ABUS";
+  ATTRIBUTE X_INTERFACE_INFO OF Sl_CE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 CE";
+  ATTRIBUTE X_INTERFACE_INFO OF Sl_UE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 UE";
+  ATTRIBUTE X_INTERFACE_INFO OF Sl_Wait: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 WAIT";
+  ATTRIBUTE X_INTERFACE_INFO OF Sl_Ready: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 READY";
+  ATTRIBUTE X_INTERFACE_INFO OF Sl_DBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 READDBUS";
+  ATTRIBUTE X_INTERFACE_INFO OF M_BE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M BE";
+  ATTRIBUTE X_INTERFACE_INFO OF M_DBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M WRITEDBUS";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AddrStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M ADDRSTROBE";
+  ATTRIBUTE X_INTERFACE_INFO OF M_WriteStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M WRITESTROBE";
+  ATTRIBUTE X_INTERFACE_INFO OF M_ReadStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M READSTROBE";
+  ATTRIBUTE X_INTERFACE_INFO OF M_ABus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M ABUS";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF LMB_Rst: SIGNAL IS "XIL_INTERFACENAME LMB_Sl_0, ADDR_WIDTH 32, DATA_WIDTH 32, READ_WRITE_MODE READ_WRITE, XIL_INTERFACENAME LMB_M, ADDR_WIDTH 32, DATA_WIDTH 32, READ_WRITE_MODE READ_WRITE";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_Rst: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 RST, xilinx.com:interface:lmb:1.0 LMB_M RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF SYS_Rst: SIGNAL IS "XIL_INTERFACENAME RST.SYS_Rst, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF SYS_Rst: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.SYS_Rst RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF LMB_Clk: SIGNAL IS "XIL_INTERFACENAME CLK.LMB_Clk, ASSOCIATED_BUSIF LMB_Sl_0:LMB_Sl_1:LMB_Sl_2:LMB_Sl_3:LMB_Sl_4:LMB_Sl_5:LMB_Sl_6:LMB_Sl_7:LMB_Sl_8:LMB_Sl_9:LMB_Sl_10:LMB_Sl_11:LMB_Sl_12:LMB_Sl_13:LMB_Sl_14:LMB_Sl_15:LMB_M, ASSOCIATED_RESET SYS_Rst, FREQ_HZ 25000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_Clk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK.LMB_Clk CLK";
+BEGIN
+  U0 : lmb_v10
+    GENERIC MAP (
+      C_LMB_NUM_SLAVES => 1,
+      C_LMB_DWIDTH => 32,
+      C_LMB_AWIDTH => 32,
+      C_EXT_RESET_HIGH => 1
+    )
+    PORT MAP (
+      LMB_Clk => LMB_Clk,
+      SYS_Rst => SYS_Rst,
+      LMB_Rst => LMB_Rst,
+      M_ABus => M_ABus,
+      M_ReadStrobe => M_ReadStrobe,
+      M_WriteStrobe => M_WriteStrobe,
+      M_AddrStrobe => M_AddrStrobe,
+      M_DBus => M_DBus,
+      M_BE => M_BE,
+      Sl_DBus => Sl_DBus,
+      Sl_Ready => Sl_Ready,
+      Sl_Wait => Sl_Wait,
+      Sl_UE => Sl_UE,
+      Sl_CE => Sl_CE,
+      LMB_ABus => LMB_ABus,
+      LMB_ReadStrobe => LMB_ReadStrobe,
+      LMB_WriteStrobe => LMB_WriteStrobe,
+      LMB_AddrStrobe => LMB_AddrStrobe,
+      LMB_ReadDBus => LMB_ReadDBus,
+      LMB_WriteDBus => LMB_WriteDBus,
+      LMB_Ready => LMB_Ready,
+      LMB_Wait => LMB_Wait,
+      LMB_UE => LMB_UE,
+      LMB_CE => LMB_CE,
+      LMB_BE => LMB_BE
+    );
+END system_bd_dlmb_v10_0_arch;

projects/dl814_k7/common_ipi-bd/basic_driver_bd/ip/system_bd_dlmb_v10_0/system_bd_dlmb_v10_0.xci

@@ -0,0 +1,116 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>system_bd_dlmb_v10_0</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="lmb_v10" spirit:version="3.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.CLK_DOMAIN">/clk_wiz_25M_clk_out1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_HZ">25000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.PHASE">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_M.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_M.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_M.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_0.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_0.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_0.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_1.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_1.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_1.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_10.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_10.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_10.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_11.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_11.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_11.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_12.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_12.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_12.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_13.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_13.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_13.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_14.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_14.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_14.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_15.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_15.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_2.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_2.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_2.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_3.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_3.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_3.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_4.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_4.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_4.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_5.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_5.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_5.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_6.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_6.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_6.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_7.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_7.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_7.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_8.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_8.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_8.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_9.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_9.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_9.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST.SYS_RST.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EXT_RESET_HIGH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LMB_AWIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LMB_DWIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LMB_NUM_SLAVES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_EXT_RESET_HIGH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_LMB_AWIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_LMB_DWIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_LMB_NUM_SLAVES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">system_bd_dlmb_v10_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k410t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.CLK_DOMAIN" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_HZ" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.PHASE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_M.DATA_WIDTH" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_M.READ_WRITE_MODE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_0.ADDR_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_0.DATA_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_AWIDTH" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_DWIDTH" xilinx:valueSource="propagated"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>

projects/dl814_k7/common_ipi-bd/basic_driver_bd/ip/system_bd_dlmb_v10_0/system_bd_dlmb_v10_0.xdc

@@ -0,0 +1 @@
+set_false_path -through [get_ports "SYS_Rst"]

projects/dl814_k7/common_ipi-bd/basic_driver_bd/ip/system_bd_dlmb_v10_0/system_bd_dlmb_v10_0_ooc.xdc

@@ -0,0 +1,57 @@
+# (c) Copyright 2012-2023 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+# DO NOT MODIFY THIS FILE.
+# #########################################################
+#
+# This XDC is used only in OOC mode for synthesis, implementation
+#
+# #########################################################
+
+
+create_clock -period 40 -name LMB_Clk [get_ports LMB_Clk]
+
+

projects/dl814_k7/common_ipi-bd/basic_driver_bd/ip/system_bd_dlmb_v10_0/system_bd_dlmb_v10_0_stub.v

@@ -0,0 +1,47 @@
+// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep  4 09:45:24 MDT 2019
+// Date        : Sat Mar 18 23:57:10 2023
+// Host        : JOSH-ASUS-Z690 running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode synth_stub -rename_top system_bd_dlmb_v10_0 -prefix
+//               system_bd_dlmb_v10_0_ system_bd_dlmb_v10_0_stub.v
+// Design      : system_bd_dlmb_v10_0
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7k410tffg900-2
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* x_core_info = "lmb_v10,Vivado 2019.1.3" *)
+module system_bd_dlmb_v10_0(LMB_Clk, SYS_Rst, LMB_Rst, M_ABus, M_ReadStrobe, 
+  M_WriteStrobe, M_AddrStrobe, M_DBus, M_BE, Sl_DBus, Sl_Ready, Sl_Wait, Sl_UE, Sl_CE, LMB_ABus, 
+  LMB_ReadStrobe, LMB_WriteStrobe, LMB_AddrStrobe, LMB_ReadDBus, LMB_WriteDBus, LMB_Ready, 
+  LMB_Wait, LMB_UE, LMB_CE, LMB_BE)
+/* synthesis syn_black_box black_box_pad_pin="LMB_Clk,SYS_Rst,LMB_Rst,M_ABus[0:31],M_ReadStrobe,M_WriteStrobe,M_AddrStrobe,M_DBus[0:31],M_BE[0:3],Sl_DBus[0:31],Sl_Ready[0:0],Sl_Wait[0:0],Sl_UE[0:0],Sl_CE[0:0],LMB_ABus[0:31],LMB_ReadStrobe,LMB_WriteStrobe,LMB_AddrStrobe,LMB_ReadDBus[0:31],LMB_WriteDBus[0:31],LMB_Ready,LMB_Wait,LMB_UE,LMB_CE,LMB_BE[0:3]" */;
+  input LMB_Clk;
+  input SYS_Rst;
+  output LMB_Rst;
+  input [0:31]M_ABus;
+  input M_ReadStrobe;
+  input M_WriteStrobe;
+  input M_AddrStrobe;
+  input [0:31]M_DBus;
+  input [0:3]M_BE;
+  input [0:31]Sl_DBus;
+  input [0:0]Sl_Ready;
+  input [0:0]Sl_Wait;
+  input [0:0]Sl_UE;
+  input [0:0]Sl_CE;
+  output [0:31]LMB_ABus;
+  output LMB_ReadStrobe;
+  output LMB_WriteStrobe;
+  output LMB_AddrStrobe;
+  output [0:31]LMB_ReadDBus;
+  output [0:31]LMB_WriteDBus;
+  output LMB_Ready;
+  output LMB_Wait;
+  output LMB_UE;
+  output LMB_CE;
+  output [0:3]LMB_BE;
+endmodule

projects/dl814_k7/common_ipi-bd/basic_driver_bd/ip/system_bd_dlmb_v10_0/system_bd_dlmb_v10_0_stub.vhdl

@@ -0,0 +1,54 @@
+-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep  4 09:45:24 MDT 2019
+-- Date        : Sat Mar 18 23:57:10 2023
+-- Host        : JOSH-ASUS-Z690 running 64-bit major release  (build 9200)
+-- Command     : write_vhdl -force -mode synth_stub -rename_top system_bd_dlmb_v10_0 -prefix
+--               system_bd_dlmb_v10_0_ system_bd_dlmb_v10_0_stub.vhdl
+-- Design      : system_bd_dlmb_v10_0
+-- Purpose     : Stub declaration of top-level module interface
+-- Device      : xc7k410tffg900-2
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity system_bd_dlmb_v10_0 is
+  Port ( 
+    LMB_Clk : in STD_LOGIC;
+    SYS_Rst : in STD_LOGIC;
+    LMB_Rst : out STD_LOGIC;
+    M_ABus : in STD_LOGIC_VECTOR ( 0 to 31 );
+    M_ReadStrobe : in STD_LOGIC;
+    M_WriteStrobe : in STD_LOGIC;
+    M_AddrStrobe : in STD_LOGIC;
+    M_DBus : in STD_LOGIC_VECTOR ( 0 to 31 );
+    M_BE : in STD_LOGIC_VECTOR ( 0 to 3 );
+    Sl_DBus : in STD_LOGIC_VECTOR ( 0 to 31 );
+    Sl_Ready : in STD_LOGIC_VECTOR ( 0 to 0 );
+    Sl_Wait : in STD_LOGIC_VECTOR ( 0 to 0 );
+    Sl_UE : in STD_LOGIC_VECTOR ( 0 to 0 );
+    Sl_CE : in STD_LOGIC_VECTOR ( 0 to 0 );
+    LMB_ABus : out STD_LOGIC_VECTOR ( 0 to 31 );
+    LMB_ReadStrobe : out STD_LOGIC;
+    LMB_WriteStrobe : out STD_LOGIC;
+    LMB_AddrStrobe : out STD_LOGIC;
+    LMB_ReadDBus : out STD_LOGIC_VECTOR ( 0 to 31 );
+    LMB_WriteDBus : out STD_LOGIC_VECTOR ( 0 to 31 );
+    LMB_Ready : out STD_LOGIC;
+    LMB_Wait : out STD_LOGIC;
+    LMB_UE : out STD_LOGIC;
+    LMB_CE : out STD_LOGIC;
+    LMB_BE : out STD_LOGIC_VECTOR ( 0 to 3 )
+  );
+
+end system_bd_dlmb_v10_0;
+
+architecture stub of system_bd_dlmb_v10_0 is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "LMB_Clk,SYS_Rst,LMB_Rst,M_ABus[0:31],M_ReadStrobe,M_WriteStrobe,M_AddrStrobe,M_DBus[0:31],M_BE[0:3],Sl_DBus[0:31],Sl_Ready[0:0],Sl_Wait[0:0],Sl_UE[0:0],Sl_CE[0:0],LMB_ABus[0:31],LMB_ReadStrobe,LMB_WriteStrobe,LMB_AddrStrobe,LMB_ReadDBus[0:31],LMB_WriteDBus[0:31],LMB_Ready,LMB_Wait,LMB_UE,LMB_CE,LMB_BE[0:3]";
+attribute x_core_info : string;
+attribute x_core_info of stub : architecture is "lmb_v10,Vivado 2019.1.3";
+begin
+end;

projects/dl814_k7/common_ipi-bd/basic_driver_bd/ip/system_bd_ilmb_bram_if_cntlr_0/sim/system_bd_ilmb_bram_if_cntlr_0.vhd

@@ -0,0 +1,295 @@
+-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:lmb_bram_if_cntlr:4.0
+-- IP Revision: 16
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+LIBRARY lmb_bram_if_cntlr_v4_0_16;
+USE lmb_bram_if_cntlr_v4_0_16.lmb_bram_if_cntlr;
+
+ENTITY system_bd_ilmb_bram_if_cntlr_0 IS
+  PORT (
+    LMB_Clk : IN STD_LOGIC;
+    LMB_Rst : IN STD_LOGIC;
+    LMB_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
+    LMB_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
+    LMB_AddrStrobe : IN STD_LOGIC;
+    LMB_ReadStrobe : IN STD_LOGIC;
+    LMB_WriteStrobe : IN STD_LOGIC;
+    LMB_BE : IN STD_LOGIC_VECTOR(0 TO 3);
+    Sl_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
+    Sl_Ready : OUT STD_LOGIC;
+    Sl_Wait : OUT STD_LOGIC;
+    Sl_UE : OUT STD_LOGIC;
+    Sl_CE : OUT STD_LOGIC;
+    BRAM_Rst_A : OUT STD_LOGIC;
+    BRAM_Clk_A : OUT STD_LOGIC;
+    BRAM_Addr_A : OUT STD_LOGIC_VECTOR(0 TO 31);
+    BRAM_EN_A : OUT STD_LOGIC;
+    BRAM_WEN_A : OUT STD_LOGIC_VECTOR(0 TO 3);
+    BRAM_Dout_A : OUT STD_LOGIC_VECTOR(0 TO 31);
+    BRAM_Din_A : IN STD_LOGIC_VECTOR(0 TO 31)
+  );
+END system_bd_ilmb_bram_if_cntlr_0;
+
+ARCHITECTURE system_bd_ilmb_bram_if_cntlr_0_arch OF system_bd_ilmb_bram_if_cntlr_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_bd_ilmb_bram_if_cntlr_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT lmb_bram_if_cntlr IS
+    GENERIC (
+      C_FAMILY : STRING;
+      C_HIGHADDR : STD_LOGIC_VECTOR;
+      C_BASEADDR : STD_LOGIC_VECTOR;
+      C_NUM_LMB : INTEGER;
+      C_MASK : STD_LOGIC_VECTOR;
+      C_MASK1 : STD_LOGIC_VECTOR;
+      C_MASK2 : STD_LOGIC_VECTOR;
+      C_MASK3 : STD_LOGIC_VECTOR;
+      C_LMB_AWIDTH : INTEGER;
+      C_LMB_DWIDTH : INTEGER;
+      C_ECC : INTEGER;
+      C_INTERCONNECT : INTEGER;
+      C_FAULT_INJECT : INTEGER;
+      C_CE_FAILING_REGISTERS : INTEGER;
+      C_UE_FAILING_REGISTERS : INTEGER;
+      C_ECC_STATUS_REGISTERS : INTEGER;
+      C_ECC_ONOFF_REGISTER : INTEGER;
+      C_ECC_ONOFF_RESET_VALUE : INTEGER;
+      C_CE_COUNTER_WIDTH : INTEGER;
+      C_WRITE_ACCESS : INTEGER;
+      C_BRAM_AWIDTH : INTEGER;
+      C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
+      C_S_AXI_CTRL_DATA_WIDTH : INTEGER
+    );
+    PORT (
+      LMB_Clk : IN STD_LOGIC;
+      LMB_Rst : IN STD_LOGIC;
+      LMB_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
+      LMB_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
+      LMB_AddrStrobe : IN STD_LOGIC;
+      LMB_ReadStrobe : IN STD_LOGIC;
+      LMB_WriteStrobe : IN STD_LOGIC;
+      LMB_BE : IN STD_LOGIC_VECTOR(0 TO 3);
+      Sl_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
+      Sl_Ready : OUT STD_LOGIC;
+      Sl_Wait : OUT STD_LOGIC;
+      Sl_UE : OUT STD_LOGIC;
+      Sl_CE : OUT STD_LOGIC;
+      LMB1_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
+      LMB1_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
+      LMB1_AddrStrobe : IN STD_LOGIC;
+      LMB1_ReadStrobe : IN STD_LOGIC;
+      LMB1_WriteStrobe : IN STD_LOGIC;
+      LMB1_BE : IN STD_LOGIC_VECTOR(0 TO 3);
+      Sl1_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
+      Sl1_Ready : OUT STD_LOGIC;
+      Sl1_Wait : OUT STD_LOGIC;
+      Sl1_UE : OUT STD_LOGIC;
+      Sl1_CE : OUT STD_LOGIC;
+      LMB2_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
+      LMB2_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
+      LMB2_AddrStrobe : IN STD_LOGIC;
+      LMB2_ReadStrobe : IN STD_LOGIC;
+      LMB2_WriteStrobe : IN STD_LOGIC;
+      LMB2_BE : IN STD_LOGIC_VECTOR(0 TO 3);
+      Sl2_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
+      Sl2_Ready : OUT STD_LOGIC;
+      Sl2_Wait : OUT STD_LOGIC;
+      Sl2_UE : OUT STD_LOGIC;
+      Sl2_CE : OUT STD_LOGIC;
+      LMB3_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
+      LMB3_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
+      LMB3_AddrStrobe : IN STD_LOGIC;
+      LMB3_ReadStrobe : IN STD_LOGIC;
+      LMB3_WriteStrobe : IN STD_LOGIC;
+      LMB3_BE : IN STD_LOGIC_VECTOR(0 TO 3);
+      Sl3_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
+      Sl3_Ready : OUT STD_LOGIC;
+      Sl3_Wait : OUT STD_LOGIC;
+      Sl3_UE : OUT STD_LOGIC;
+      Sl3_CE : OUT STD_LOGIC;
+      BRAM_Rst_A : OUT STD_LOGIC;
+      BRAM_Clk_A : OUT STD_LOGIC;
+      BRAM_Addr_A : OUT STD_LOGIC_VECTOR(0 TO 31);
+      BRAM_EN_A : OUT STD_LOGIC;
+      BRAM_WEN_A : OUT STD_LOGIC_VECTOR(0 TO 3);
+      BRAM_Dout_A : OUT STD_LOGIC_VECTOR(0 TO 31);
+      BRAM_Din_A : IN STD_LOGIC_VECTOR(0 TO 31);
+      S_AXI_CTRL_ACLK : IN STD_LOGIC;
+      S_AXI_CTRL_ARESETN : IN STD_LOGIC;
+      S_AXI_CTRL_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      S_AXI_CTRL_AWVALID : IN STD_LOGIC;
+      S_AXI_CTRL_AWREADY : OUT STD_LOGIC;
+      S_AXI_CTRL_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      S_AXI_CTRL_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      S_AXI_CTRL_WVALID : IN STD_LOGIC;
+      S_AXI_CTRL_WREADY : OUT STD_LOGIC;
+      S_AXI_CTRL_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      S_AXI_CTRL_BVALID : OUT STD_LOGIC;
+      S_AXI_CTRL_BREADY : IN STD_LOGIC;
+      S_AXI_CTRL_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      S_AXI_CTRL_ARVALID : IN STD_LOGIC;
+      S_AXI_CTRL_ARREADY : OUT STD_LOGIC;
+      S_AXI_CTRL_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      S_AXI_CTRL_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      S_AXI_CTRL_RVALID : OUT STD_LOGIC;
+      S_AXI_CTRL_RREADY : IN STD_LOGIC;
+      UE : OUT STD_LOGIC;
+      CE : OUT STD_LOGIC;
+      Interrupt : OUT STD_LOGIC
+    );
+  END COMPONENT lmb_bram_if_cntlr;
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_INFO OF BRAM_Din_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT DOUT";
+  ATTRIBUTE X_INTERFACE_INFO OF BRAM_Dout_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT DIN";
+  ATTRIBUTE X_INTERFACE_INFO OF BRAM_WEN_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT WE";
+  ATTRIBUTE X_INTERFACE_INFO OF BRAM_EN_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT EN";
+  ATTRIBUTE X_INTERFACE_INFO OF BRAM_Addr_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT ADDR";
+  ATTRIBUTE X_INTERFACE_INFO OF BRAM_Clk_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT CLK";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF BRAM_Rst_A: SIGNAL IS "XIL_INTERFACENAME BRAM_PORT, MEM_SIZE 262144, MASTER_TYPE BRAM_CTRL, MEM_WIDTH 32, MEM_ECC NONE, READ_LATENCY 1";
+  ATTRIBUTE X_INTERFACE_INFO OF BRAM_Rst_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT RST";
+  ATTRIBUTE X_INTERFACE_INFO OF Sl_CE: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB CE";
+  ATTRIBUTE X_INTERFACE_INFO OF Sl_UE: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB UE";
+  ATTRIBUTE X_INTERFACE_INFO OF Sl_Wait: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB WAIT";
+  ATTRIBUTE X_INTERFACE_INFO OF Sl_Ready: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB READY";
+  ATTRIBUTE X_INTERFACE_INFO OF Sl_DBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB READDBUS";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_BE: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB BE";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB WRITESTROBE";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_ReadStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB READSTROBE";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_AddrStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB ADDRSTROBE";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteDBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB WRITEDBUS";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF LMB_ABus: SIGNAL IS "XIL_INTERFACENAME SLMB, ADDR_WIDTH 32, DATA_WIDTH 32, READ_WRITE_MODE READ_WRITE";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_ABus: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB ABUS";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF LMB_Rst: SIGNAL IS "XIL_INTERFACENAME RST.LMB_Rst, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_Rst: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.LMB_Rst RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF LMB_Clk: SIGNAL IS "XIL_INTERFACENAME CLK.LMB_Clk, ASSOCIATED_BUSIF SLMB:SLMB1:SLMB2:SLMB3, ASSOCIATED_RESET LMB_Rst, FREQ_HZ 25000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_Clk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK.LMB_Clk CLK";
+BEGIN
+  U0 : lmb_bram_if_cntlr
+    GENERIC MAP (
+      C_FAMILY => "kintex7",
+      C_HIGHADDR => X"000000000003FFFF",
+      C_BASEADDR => X"0000000000000000",
+      C_NUM_LMB => 1,
+      C_MASK => X"0000000000000000",
+      C_MASK1 => X"0000000000800000",
+      C_MASK2 => X"0000000000800000",
+      C_MASK3 => X"0000000000800000",
+      C_LMB_AWIDTH => 32,
+      C_LMB_DWIDTH => 32,
+      C_ECC => 0,
+      C_INTERCONNECT => 0,
+      C_FAULT_INJECT => 0,
+      C_CE_FAILING_REGISTERS => 0,
+      C_UE_FAILING_REGISTERS => 0,
+      C_ECC_STATUS_REGISTERS => 0,
+      C_ECC_ONOFF_REGISTER => 0,
+      C_ECC_ONOFF_RESET_VALUE => 1,
+      C_CE_COUNTER_WIDTH => 0,
+      C_WRITE_ACCESS => 2,
+      C_BRAM_AWIDTH => 32,
+      C_S_AXI_CTRL_ADDR_WIDTH => 32,
+      C_S_AXI_CTRL_DATA_WIDTH => 32
+    )
+    PORT MAP (
+      LMB_Clk => LMB_Clk,
+      LMB_Rst => LMB_Rst,
+      LMB_ABus => LMB_ABus,
+      LMB_WriteDBus => LMB_WriteDBus,
+      LMB_AddrStrobe => LMB_AddrStrobe,
+      LMB_ReadStrobe => LMB_ReadStrobe,
+      LMB_WriteStrobe => LMB_WriteStrobe,
+      LMB_BE => LMB_BE,
+      Sl_DBus => Sl_DBus,
+      Sl_Ready => Sl_Ready,
+      Sl_Wait => Sl_Wait,
+      Sl_UE => Sl_UE,
+      Sl_CE => Sl_CE,
+      LMB1_ABus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
+      LMB1_WriteDBus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
+      LMB1_AddrStrobe => '0',
+      LMB1_ReadStrobe => '0',
+      LMB1_WriteStrobe => '0',
+      LMB1_BE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
+      LMB2_ABus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
+      LMB2_WriteDBus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
+      LMB2_AddrStrobe => '0',
+      LMB2_ReadStrobe => '0',
+      LMB2_WriteStrobe => '0',
+      LMB2_BE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
+      LMB3_ABus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
+      LMB3_WriteDBus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
+      LMB3_AddrStrobe => '0',
+      LMB3_ReadStrobe => '0',
+      LMB3_WriteStrobe => '0',
+      LMB3_BE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
+      BRAM_Rst_A => BRAM_Rst_A,
+      BRAM_Clk_A => BRAM_Clk_A,
+      BRAM_Addr_A => BRAM_Addr_A,
+      BRAM_EN_A => BRAM_EN_A,
+      BRAM_WEN_A => BRAM_WEN_A,
+      BRAM_Dout_A => BRAM_Dout_A,
+      BRAM_Din_A => BRAM_Din_A,
+      S_AXI_CTRL_ACLK => '0',
+      S_AXI_CTRL_ARESETN => '0',
+      S_AXI_CTRL_AWADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
+      S_AXI_CTRL_AWVALID => '0',
+      S_AXI_CTRL_WDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
+      S_AXI_CTRL_WSTRB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
+      S_AXI_CTRL_WVALID => '0',
+      S_AXI_CTRL_BREADY => '0',
+      S_AXI_CTRL_ARADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
+      S_AXI_CTRL_ARVALID => '0',
+      S_AXI_CTRL_RREADY => '0'
+    );
+END system_bd_ilmb_bram_if_cntlr_0_arch;

projects/dl814_k7/common_ipi-bd/basic_driver_bd/ip/system_bd_ilmb_bram_if_cntlr_0/synth/system_bd_ilmb_bram_if_cntlr_0.vhd

@@ -0,0 +1,302 @@
+-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:lmb_bram_if_cntlr:4.0
+-- IP Revision: 16
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+LIBRARY lmb_bram_if_cntlr_v4_0_16;
+USE lmb_bram_if_cntlr_v4_0_16.lmb_bram_if_cntlr;
+
+ENTITY system_bd_ilmb_bram_if_cntlr_0 IS
+  PORT (
+    LMB_Clk : IN STD_LOGIC;
+    LMB_Rst : IN STD_LOGIC;
+    LMB_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
+    LMB_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
+    LMB_AddrStrobe : IN STD_LOGIC;
+    LMB_ReadStrobe : IN STD_LOGIC;
+    LMB_WriteStrobe : IN STD_LOGIC;
+    LMB_BE : IN STD_LOGIC_VECTOR(0 TO 3);
+    Sl_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
+    Sl_Ready : OUT STD_LOGIC;
+    Sl_Wait : OUT STD_LOGIC;
+    Sl_UE : OUT STD_LOGIC;
+    Sl_CE : OUT STD_LOGIC;
+    BRAM_Rst_A : OUT STD_LOGIC;
+    BRAM_Clk_A : OUT STD_LOGIC;
+    BRAM_Addr_A : OUT STD_LOGIC_VECTOR(0 TO 31);
+    BRAM_EN_A : OUT STD_LOGIC;
+    BRAM_WEN_A : OUT STD_LOGIC_VECTOR(0 TO 3);
+    BRAM_Dout_A : OUT STD_LOGIC_VECTOR(0 TO 31);
+    BRAM_Din_A : IN STD_LOGIC_VECTOR(0 TO 31)
+  );
+END system_bd_ilmb_bram_if_cntlr_0;
+
+ARCHITECTURE system_bd_ilmb_bram_if_cntlr_0_arch OF system_bd_ilmb_bram_if_cntlr_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_bd_ilmb_bram_if_cntlr_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT lmb_bram_if_cntlr IS
+    GENERIC (
+      C_FAMILY : STRING;
+      C_HIGHADDR : STD_LOGIC_VECTOR;
+      C_BASEADDR : STD_LOGIC_VECTOR;
+      C_NUM_LMB : INTEGER;
+      C_MASK : STD_LOGIC_VECTOR;
+      C_MASK1 : STD_LOGIC_VECTOR;
+      C_MASK2 : STD_LOGIC_VECTOR;
+      C_MASK3 : STD_LOGIC_VECTOR;
+      C_LMB_AWIDTH : INTEGER;
+      C_LMB_DWIDTH : INTEGER;
+      C_ECC : INTEGER;
+      C_INTERCONNECT : INTEGER;
+      C_FAULT_INJECT : INTEGER;
+      C_CE_FAILING_REGISTERS : INTEGER;
+      C_UE_FAILING_REGISTERS : INTEGER;
+      C_ECC_STATUS_REGISTERS : INTEGER;
+      C_ECC_ONOFF_REGISTER : INTEGER;
+      C_ECC_ONOFF_RESET_VALUE : INTEGER;
+      C_CE_COUNTER_WIDTH : INTEGER;
+      C_WRITE_ACCESS : INTEGER;
+      C_BRAM_AWIDTH : INTEGER;
+      C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
+      C_S_AXI_CTRL_DATA_WIDTH : INTEGER
+    );
+    PORT (
+      LMB_Clk : IN STD_LOGIC;
+      LMB_Rst : IN STD_LOGIC;
+      LMB_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
+      LMB_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
+      LMB_AddrStrobe : IN STD_LOGIC;
+      LMB_ReadStrobe : IN STD_LOGIC;
+      LMB_WriteStrobe : IN STD_LOGIC;
+      LMB_BE : IN STD_LOGIC_VECTOR(0 TO 3);
+      Sl_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
+      Sl_Ready : OUT STD_LOGIC;
+      Sl_Wait : OUT STD_LOGIC;
+      Sl_UE : OUT STD_LOGIC;
+      Sl_CE : OUT STD_LOGIC;
+      LMB1_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
+      LMB1_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
+      LMB1_AddrStrobe : IN STD_LOGIC;
+      LMB1_ReadStrobe : IN STD_LOGIC;
+      LMB1_WriteStrobe : IN STD_LOGIC;
+      LMB1_BE : IN STD_LOGIC_VECTOR(0 TO 3);
+      Sl1_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
+      Sl1_Ready : OUT STD_LOGIC;
+      Sl1_Wait : OUT STD_LOGIC;
+      Sl1_UE : OUT STD_LOGIC;
+      Sl1_CE : OUT STD_LOGIC;
+      LMB2_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
+      LMB2_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
+      LMB2_AddrStrobe : IN STD_LOGIC;
+      LMB2_ReadStrobe : IN STD_LOGIC;
+      LMB2_WriteStrobe : IN STD_LOGIC;
+      LMB2_BE : IN STD_LOGIC_VECTOR(0 TO 3);
+      Sl2_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
+      Sl2_Ready : OUT STD_LOGIC;
+      Sl2_Wait : OUT STD_LOGIC;
+      Sl2_UE : OUT STD_LOGIC;
+      Sl2_CE : OUT STD_LOGIC;
+      LMB3_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
+      LMB3_WriteDBus : IN STD_LOGIC_VECTOR(0 TO 31);
+      LMB3_AddrStrobe : IN STD_LOGIC;
+      LMB3_ReadStrobe : IN STD_LOGIC;
+      LMB3_WriteStrobe : IN STD_LOGIC;
+      LMB3_BE : IN STD_LOGIC_VECTOR(0 TO 3);
+      Sl3_DBus : OUT STD_LOGIC_VECTOR(0 TO 31);
+      Sl3_Ready : OUT STD_LOGIC;
+      Sl3_Wait : OUT STD_LOGIC;
+      Sl3_UE : OUT STD_LOGIC;
+      Sl3_CE : OUT STD_LOGIC;
+      BRAM_Rst_A : OUT STD_LOGIC;
+      BRAM_Clk_A : OUT STD_LOGIC;
+      BRAM_Addr_A : OUT STD_LOGIC_VECTOR(0 TO 31);
+      BRAM_EN_A : OUT STD_LOGIC;
+      BRAM_WEN_A : OUT STD_LOGIC_VECTOR(0 TO 3);
+      BRAM_Dout_A : OUT STD_LOGIC_VECTOR(0 TO 31);
+      BRAM_Din_A : IN STD_LOGIC_VECTOR(0 TO 31);
+      S_AXI_CTRL_ACLK : IN STD_LOGIC;
+      S_AXI_CTRL_ARESETN : IN STD_LOGIC;
+      S_AXI_CTRL_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      S_AXI_CTRL_AWVALID : IN STD_LOGIC;
+      S_AXI_CTRL_AWREADY : OUT STD_LOGIC;
+      S_AXI_CTRL_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      S_AXI_CTRL_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      S_AXI_CTRL_WVALID : IN STD_LOGIC;
+      S_AXI_CTRL_WREADY : OUT STD_LOGIC;
+      S_AXI_CTRL_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      S_AXI_CTRL_BVALID : OUT STD_LOGIC;
+      S_AXI_CTRL_BREADY : IN STD_LOGIC;
+      S_AXI_CTRL_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      S_AXI_CTRL_ARVALID : IN STD_LOGIC;
+      S_AXI_CTRL_ARREADY : OUT STD_LOGIC;
+      S_AXI_CTRL_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      S_AXI_CTRL_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      S_AXI_CTRL_RVALID : OUT STD_LOGIC;
+      S_AXI_CTRL_RREADY : IN STD_LOGIC;
+      UE : OUT STD_LOGIC;
+      CE : OUT STD_LOGIC;
+      Interrupt : OUT STD_LOGIC
+    );
+  END COMPONENT lmb_bram_if_cntlr;
+  ATTRIBUTE X_CORE_INFO : STRING;
+  ATTRIBUTE X_CORE_INFO OF system_bd_ilmb_bram_if_cntlr_0_arch: ARCHITECTURE IS "lmb_bram_if_cntlr,Vivado 2019.1.3";
+  ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
+  ATTRIBUTE CHECK_LICENSE_TYPE OF system_bd_ilmb_bram_if_cntlr_0_arch : ARCHITECTURE IS "system_bd_ilmb_bram_if_cntlr_0,lmb_bram_if_cntlr,{}";
+  ATTRIBUTE CORE_GENERATION_INFO : STRING;
+  ATTRIBUTE CORE_GENERATION_INFO OF system_bd_ilmb_bram_if_cntlr_0_arch: ARCHITECTURE IS "system_bd_ilmb_bram_if_cntlr_0,lmb_bram_if_cntlr,{x_ipProduct=Vivado 2019.1.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=lmb_bram_if_cntlr,x_ipVersion=4.0,x_ipCoreRevision=16,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=kintex7,C_HIGHADDR=0x000000000003FFFF,C_BASEADDR=0x0000000000000000,C_NUM_LMB=1,C_MASK=0x0000000000000000,C_MASK1=0x0000000000800000,C_MASK2=0x0000000000800000,C_MASK3=0x0000000000800000,C_LMB_AWIDTH=32,C_LMB_DWIDTH=32,C_ECC=0,C_INTERCONNECT=0,C_FAULT_INJECT=0,C_CE_FAIL" & 
+"ING_REGISTERS=0,C_UE_FAILING_REGISTERS=0,C_ECC_STATUS_REGISTERS=0,C_ECC_ONOFF_REGISTER=0,C_ECC_ONOFF_RESET_VALUE=1,C_CE_COUNTER_WIDTH=0,C_WRITE_ACCESS=2,C_BRAM_AWIDTH=32,C_S_AXI_CTRL_ADDR_WIDTH=32,C_S_AXI_CTRL_DATA_WIDTH=32}";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_INFO OF BRAM_Din_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT DOUT";
+  ATTRIBUTE X_INTERFACE_INFO OF BRAM_Dout_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT DIN";
+  ATTRIBUTE X_INTERFACE_INFO OF BRAM_WEN_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT WE";
+  ATTRIBUTE X_INTERFACE_INFO OF BRAM_EN_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT EN";
+  ATTRIBUTE X_INTERFACE_INFO OF BRAM_Addr_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT ADDR";
+  ATTRIBUTE X_INTERFACE_INFO OF BRAM_Clk_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT CLK";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF BRAM_Rst_A: SIGNAL IS "XIL_INTERFACENAME BRAM_PORT, MEM_SIZE 262144, MASTER_TYPE BRAM_CTRL, MEM_WIDTH 32, MEM_ECC NONE, READ_LATENCY 1";
+  ATTRIBUTE X_INTERFACE_INFO OF BRAM_Rst_A: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORT RST";
+  ATTRIBUTE X_INTERFACE_INFO OF Sl_CE: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB CE";
+  ATTRIBUTE X_INTERFACE_INFO OF Sl_UE: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB UE";
+  ATTRIBUTE X_INTERFACE_INFO OF Sl_Wait: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB WAIT";
+  ATTRIBUTE X_INTERFACE_INFO OF Sl_Ready: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB READY";
+  ATTRIBUTE X_INTERFACE_INFO OF Sl_DBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB READDBUS";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_BE: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB BE";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB WRITESTROBE";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_ReadStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB READSTROBE";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_AddrStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB ADDRSTROBE";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteDBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB WRITEDBUS";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF LMB_ABus: SIGNAL IS "XIL_INTERFACENAME SLMB, ADDR_WIDTH 32, DATA_WIDTH 32, READ_WRITE_MODE READ_WRITE";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_ABus: SIGNAL IS "xilinx.com:interface:lmb:1.0 SLMB ABUS";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF LMB_Rst: SIGNAL IS "XIL_INTERFACENAME RST.LMB_Rst, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_Rst: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.LMB_Rst RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF LMB_Clk: SIGNAL IS "XIL_INTERFACENAME CLK.LMB_Clk, ASSOCIATED_BUSIF SLMB:SLMB1:SLMB2:SLMB3, ASSOCIATED_RESET LMB_Rst, FREQ_HZ 25000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_Clk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK.LMB_Clk CLK";
+BEGIN
+  U0 : lmb_bram_if_cntlr
+    GENERIC MAP (
+      C_FAMILY => "kintex7",
+      C_HIGHADDR => X"000000000003FFFF",
+      C_BASEADDR => X"0000000000000000",
+      C_NUM_LMB => 1,
+      C_MASK => X"0000000000000000",
+      C_MASK1 => X"0000000000800000",
+      C_MASK2 => X"0000000000800000",
+      C_MASK3 => X"0000000000800000",
+      C_LMB_AWIDTH => 32,
+      C_LMB_DWIDTH => 32,
+      C_ECC => 0,
+      C_INTERCONNECT => 0,
+      C_FAULT_INJECT => 0,
+      C_CE_FAILING_REGISTERS => 0,
+      C_UE_FAILING_REGISTERS => 0,
+      C_ECC_STATUS_REGISTERS => 0,
+      C_ECC_ONOFF_REGISTER => 0,
+      C_ECC_ONOFF_RESET_VALUE => 1,
+      C_CE_COUNTER_WIDTH => 0,
+      C_WRITE_ACCESS => 2,
+      C_BRAM_AWIDTH => 32,
+      C_S_AXI_CTRL_ADDR_WIDTH => 32,
+      C_S_AXI_CTRL_DATA_WIDTH => 32
+    )
+    PORT MAP (
+      LMB_Clk => LMB_Clk,
+      LMB_Rst => LMB_Rst,
+      LMB_ABus => LMB_ABus,
+      LMB_WriteDBus => LMB_WriteDBus,
+      LMB_AddrStrobe => LMB_AddrStrobe,
+      LMB_ReadStrobe => LMB_ReadStrobe,
+      LMB_WriteStrobe => LMB_WriteStrobe,
+      LMB_BE => LMB_BE,
+      Sl_DBus => Sl_DBus,
+      Sl_Ready => Sl_Ready,
+      Sl_Wait => Sl_Wait,
+      Sl_UE => Sl_UE,
+      Sl_CE => Sl_CE,
+      LMB1_ABus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
+      LMB1_WriteDBus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
+      LMB1_AddrStrobe => '0',
+      LMB1_ReadStrobe => '0',
+      LMB1_WriteStrobe => '0',
+      LMB1_BE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
+      LMB2_ABus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
+      LMB2_WriteDBus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
+      LMB2_AddrStrobe => '0',
+      LMB2_ReadStrobe => '0',
+      LMB2_WriteStrobe => '0',
+      LMB2_BE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
+      LMB3_ABus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
+      LMB3_WriteDBus => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
+      LMB3_AddrStrobe => '0',
+      LMB3_ReadStrobe => '0',
+      LMB3_WriteStrobe => '0',
+      LMB3_BE => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
+      BRAM_Rst_A => BRAM_Rst_A,
+      BRAM_Clk_A => BRAM_Clk_A,
+      BRAM_Addr_A => BRAM_Addr_A,
+      BRAM_EN_A => BRAM_EN_A,
+      BRAM_WEN_A => BRAM_WEN_A,
+      BRAM_Dout_A => BRAM_Dout_A,
+      BRAM_Din_A => BRAM_Din_A,
+      S_AXI_CTRL_ACLK => '0',
+      S_AXI_CTRL_ARESETN => '0',
+      S_AXI_CTRL_AWADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
+      S_AXI_CTRL_AWVALID => '0',
+      S_AXI_CTRL_WDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
+      S_AXI_CTRL_WSTRB => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
+      S_AXI_CTRL_WVALID => '0',
+      S_AXI_CTRL_BREADY => '0',
+      S_AXI_CTRL_ARADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
+      S_AXI_CTRL_ARVALID => '0',
+      S_AXI_CTRL_RREADY => '0'
+    );
+END system_bd_ilmb_bram_if_cntlr_0_arch;

projects/dl814_k7/common_ipi-bd/basic_driver_bd/ip/system_bd_ilmb_bram_if_cntlr_0/system_bd_ilmb_bram_if_cntlr_0.xci

@@ -0,0 +1,164 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>system_bd_ilmb_bram_if_cntlr_0</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="lmb_bram_if_cntlr" spirit:version="4.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.MEM_ECC">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.MEM_SIZE">262144</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.MEM_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.READ_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.READ_WRITE_MODE"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.CLK_DOMAIN">/clk_wiz_25M_clk_out1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_HZ">25000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.PHASE">0.0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.CLK_DOMAIN"/>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_CTRL.WUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_BASEADDR">0x0000000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_BRAM_AWIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CE_COUNTER_WIDTH">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ECC_ONOFF_REGISTER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ECC_ONOFF_RESET_VALUE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ECC_STATUS_REGISTERS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAULT_INJECT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HIGHADDR">0x000000000003FFFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERCONNECT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LMB_AWIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LMB_DWIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MASK">0x0000000000000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MASK1">0x0000000000800000</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_UE_FAILING_REGISTERS">0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_ECC_ONOFF_REGISTER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_ECC_ONOFF_RESET_VALUE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_ECC_STATUS_REGISTERS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_FAULT_INJECT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_HIGHADDR">0x000000000003FFFF</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_MASK3">0x0000000000800000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_LMB">1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S_AXI_CTRL_ADDR_WIDTH">32</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_S_AXI_CTRL_PROTOCOL">AXI4LITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_UE_FAILING_REGISTERS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_WRITE_ACCESS">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">system_bd_ilmb_bram_if_cntlr_0</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
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+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORT.MEM_ECC" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
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+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SLMB.DATA_WIDTH" xilinx:valuePermission="bd"/>
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+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_ECC" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_HIGHADDR" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
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+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_DWIDTH" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_MASK" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>

projects/dl814_k7/common_ipi-bd/basic_driver_bd/ip/system_bd_ilmb_bram_if_cntlr_0/system_bd_ilmb_bram_if_cntlr_0_ooc.xdc

@@ -0,0 +1,57 @@
+# (c) Copyright 2012-2023 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+# DO NOT MODIFY THIS FILE.
+# #########################################################
+#
+# This XDC is used only in OOC mode for synthesis, implementation
+#
+# #########################################################
+
+
+create_clock -period 40 -name LMB_Clk [get_ports LMB_Clk]
+
+

projects/dl814_k7/common_ipi-bd/basic_driver_bd/ip/system_bd_ilmb_bram_if_cntlr_0/system_bd_ilmb_bram_if_cntlr_0_stub.v

@@ -0,0 +1,41 @@
+// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep  4 09:45:24 MDT 2019
+// Date        : Sat Mar 18 23:57:10 2023
+// Host        : JOSH-ASUS-Z690 running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode synth_stub -rename_top system_bd_ilmb_bram_if_cntlr_0 -prefix
+//               system_bd_ilmb_bram_if_cntlr_0_ system_bd_ilmb_bram_if_cntlr_0_stub.v
+// Design      : system_bd_ilmb_bram_if_cntlr_0
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7k410tffg900-2
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* x_core_info = "lmb_bram_if_cntlr,Vivado 2019.1.3" *)
+module system_bd_ilmb_bram_if_cntlr_0(LMB_Clk, LMB_Rst, LMB_ABus, LMB_WriteDBus, 
+  LMB_AddrStrobe, LMB_ReadStrobe, LMB_WriteStrobe, LMB_BE, Sl_DBus, Sl_Ready, Sl_Wait, Sl_UE, 
+  Sl_CE, BRAM_Rst_A, BRAM_Clk_A, BRAM_Addr_A, BRAM_EN_A, BRAM_WEN_A, BRAM_Dout_A, BRAM_Din_A)
+/* synthesis syn_black_box black_box_pad_pin="LMB_Clk,LMB_Rst,LMB_ABus[0:31],LMB_WriteDBus[0:31],LMB_AddrStrobe,LMB_ReadStrobe,LMB_WriteStrobe,LMB_BE[0:3],Sl_DBus[0:31],Sl_Ready,Sl_Wait,Sl_UE,Sl_CE,BRAM_Rst_A,BRAM_Clk_A,BRAM_Addr_A[0:31],BRAM_EN_A,BRAM_WEN_A[0:3],BRAM_Dout_A[0:31],BRAM_Din_A[0:31]" */;
+  input LMB_Clk;
+  input LMB_Rst;
+  input [0:31]LMB_ABus;
+  input [0:31]LMB_WriteDBus;
+  input LMB_AddrStrobe;
+  input LMB_ReadStrobe;
+  input LMB_WriteStrobe;
+  input [0:3]LMB_BE;
+  output [0:31]Sl_DBus;
+  output Sl_Ready;
+  output Sl_Wait;
+  output Sl_UE;
+  output Sl_CE;
+  output BRAM_Rst_A;
+  output BRAM_Clk_A;
+  output [0:31]BRAM_Addr_A;
+  output BRAM_EN_A;
+  output [0:3]BRAM_WEN_A;
+  output [0:31]BRAM_Dout_A;
+  input [0:31]BRAM_Din_A;
+endmodule

projects/dl814_k7/common_ipi-bd/basic_driver_bd/ip/system_bd_ilmb_bram_if_cntlr_0/system_bd_ilmb_bram_if_cntlr_0_stub.vhdl

@@ -0,0 +1,49 @@
+-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep  4 09:45:24 MDT 2019
+-- Date        : Sat Mar 18 23:57:10 2023
+-- Host        : JOSH-ASUS-Z690 running 64-bit major release  (build 9200)
+-- Command     : write_vhdl -force -mode synth_stub -rename_top system_bd_ilmb_bram_if_cntlr_0 -prefix
+--               system_bd_ilmb_bram_if_cntlr_0_ system_bd_ilmb_bram_if_cntlr_0_stub.vhdl
+-- Design      : system_bd_ilmb_bram_if_cntlr_0
+-- Purpose     : Stub declaration of top-level module interface
+-- Device      : xc7k410tffg900-2
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity system_bd_ilmb_bram_if_cntlr_0 is
+  Port ( 
+    LMB_Clk : in STD_LOGIC;
+    LMB_Rst : in STD_LOGIC;
+    LMB_ABus : in STD_LOGIC_VECTOR ( 0 to 31 );
+    LMB_WriteDBus : in STD_LOGIC_VECTOR ( 0 to 31 );
+    LMB_AddrStrobe : in STD_LOGIC;
+    LMB_ReadStrobe : in STD_LOGIC;
+    LMB_WriteStrobe : in STD_LOGIC;
+    LMB_BE : in STD_LOGIC_VECTOR ( 0 to 3 );
+    Sl_DBus : out STD_LOGIC_VECTOR ( 0 to 31 );
+    Sl_Ready : out STD_LOGIC;
+    Sl_Wait : out STD_LOGIC;
+    Sl_UE : out STD_LOGIC;
+    Sl_CE : out STD_LOGIC;
+    BRAM_Rst_A : out STD_LOGIC;
+    BRAM_Clk_A : out STD_LOGIC;
+    BRAM_Addr_A : out STD_LOGIC_VECTOR ( 0 to 31 );
+    BRAM_EN_A : out STD_LOGIC;
+    BRAM_WEN_A : out STD_LOGIC_VECTOR ( 0 to 3 );
+    BRAM_Dout_A : out STD_LOGIC_VECTOR ( 0 to 31 );
+    BRAM_Din_A : in STD_LOGIC_VECTOR ( 0 to 31 )
+  );
+
+end system_bd_ilmb_bram_if_cntlr_0;
+
+architecture stub of system_bd_ilmb_bram_if_cntlr_0 is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "LMB_Clk,LMB_Rst,LMB_ABus[0:31],LMB_WriteDBus[0:31],LMB_AddrStrobe,LMB_ReadStrobe,LMB_WriteStrobe,LMB_BE[0:3],Sl_DBus[0:31],Sl_Ready,Sl_Wait,Sl_UE,Sl_CE,BRAM_Rst_A,BRAM_Clk_A,BRAM_Addr_A[0:31],BRAM_EN_A,BRAM_WEN_A[0:3],BRAM_Dout_A[0:31],BRAM_Din_A[0:31]";
+attribute x_core_info : string;
+attribute x_core_info of stub : architecture is "lmb_bram_if_cntlr,Vivado 2019.1.3";
+begin
+end;

projects/dl814_k7/common_ipi-bd/basic_driver_bd/ip/system_bd_ilmb_v10_0/sim/system_bd_ilmb_v10_0.vhd

@@ -0,0 +1,192 @@
+-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:lmb_v10:3.0
+-- IP Revision: 9
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+LIBRARY lmb_v10_v3_0_9;
+USE lmb_v10_v3_0_9.lmb_v10;
+
+ENTITY system_bd_ilmb_v10_0 IS
+  PORT (
+    LMB_Clk : IN STD_LOGIC;
+    SYS_Rst : IN STD_LOGIC;
+    LMB_Rst : OUT STD_LOGIC;
+    M_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
+    M_ReadStrobe : IN STD_LOGIC;
+    M_WriteStrobe : IN STD_LOGIC;
+    M_AddrStrobe : IN STD_LOGIC;
+    M_DBus : IN STD_LOGIC_VECTOR(0 TO 31);
+    M_BE : IN STD_LOGIC_VECTOR(0 TO 3);
+    Sl_DBus : IN STD_LOGIC_VECTOR(0 TO 31);
+    Sl_Ready : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    Sl_Wait : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    Sl_UE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    Sl_CE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    LMB_ABus : OUT STD_LOGIC_VECTOR(0 TO 31);
+    LMB_ReadStrobe : OUT STD_LOGIC;
+    LMB_WriteStrobe : OUT STD_LOGIC;
+    LMB_AddrStrobe : OUT STD_LOGIC;
+    LMB_ReadDBus : OUT STD_LOGIC_VECTOR(0 TO 31);
+    LMB_WriteDBus : OUT STD_LOGIC_VECTOR(0 TO 31);
+    LMB_Ready : OUT STD_LOGIC;
+    LMB_Wait : OUT STD_LOGIC;
+    LMB_UE : OUT STD_LOGIC;
+    LMB_CE : OUT STD_LOGIC;
+    LMB_BE : OUT STD_LOGIC_VECTOR(0 TO 3)
+  );
+END system_bd_ilmb_v10_0;
+
+ARCHITECTURE system_bd_ilmb_v10_0_arch OF system_bd_ilmb_v10_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_bd_ilmb_v10_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT lmb_v10 IS
+    GENERIC (
+      C_LMB_NUM_SLAVES : INTEGER;
+      C_LMB_DWIDTH : INTEGER;
+      C_LMB_AWIDTH : INTEGER;
+      C_EXT_RESET_HIGH : INTEGER
+    );
+    PORT (
+      LMB_Clk : IN STD_LOGIC;
+      SYS_Rst : IN STD_LOGIC;
+      LMB_Rst : OUT STD_LOGIC;
+      M_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
+      M_ReadStrobe : IN STD_LOGIC;
+      M_WriteStrobe : IN STD_LOGIC;
+      M_AddrStrobe : IN STD_LOGIC;
+      M_DBus : IN STD_LOGIC_VECTOR(0 TO 31);
+      M_BE : IN STD_LOGIC_VECTOR(0 TO 3);
+      Sl_DBus : IN STD_LOGIC_VECTOR(0 TO 31);
+      Sl_Ready : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      Sl_Wait : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      Sl_UE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      Sl_CE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      LMB_ABus : OUT STD_LOGIC_VECTOR(0 TO 31);
+      LMB_ReadStrobe : OUT STD_LOGIC;
+      LMB_WriteStrobe : OUT STD_LOGIC;
+      LMB_AddrStrobe : OUT STD_LOGIC;
+      LMB_ReadDBus : OUT STD_LOGIC_VECTOR(0 TO 31);
+      LMB_WriteDBus : OUT STD_LOGIC_VECTOR(0 TO 31);
+      LMB_Ready : OUT STD_LOGIC;
+      LMB_Wait : OUT STD_LOGIC;
+      LMB_UE : OUT STD_LOGIC;
+      LMB_CE : OUT STD_LOGIC;
+      LMB_BE : OUT STD_LOGIC_VECTOR(0 TO 3)
+    );
+  END COMPONENT lmb_v10;
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_BE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 BE";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_CE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M CE";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_UE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M UE";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_Wait: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M WAIT";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_Ready: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M READY";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteDBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 WRITEDBUS";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_ReadDBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M READDBUS";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_AddrStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 ADDRSTROBE";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 WRITESTROBE";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_ReadStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 READSTROBE";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_ABus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 ABUS";
+  ATTRIBUTE X_INTERFACE_INFO OF Sl_CE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 CE";
+  ATTRIBUTE X_INTERFACE_INFO OF Sl_UE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 UE";
+  ATTRIBUTE X_INTERFACE_INFO OF Sl_Wait: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 WAIT";
+  ATTRIBUTE X_INTERFACE_INFO OF Sl_Ready: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 READY";
+  ATTRIBUTE X_INTERFACE_INFO OF Sl_DBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 READDBUS";
+  ATTRIBUTE X_INTERFACE_INFO OF M_BE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M BE";
+  ATTRIBUTE X_INTERFACE_INFO OF M_DBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M WRITEDBUS";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AddrStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M ADDRSTROBE";
+  ATTRIBUTE X_INTERFACE_INFO OF M_WriteStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M WRITESTROBE";
+  ATTRIBUTE X_INTERFACE_INFO OF M_ReadStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M READSTROBE";
+  ATTRIBUTE X_INTERFACE_INFO OF M_ABus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M ABUS";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF LMB_Rst: SIGNAL IS "XIL_INTERFACENAME LMB_Sl_0, ADDR_WIDTH 32, DATA_WIDTH 32, READ_WRITE_MODE READ_WRITE, XIL_INTERFACENAME LMB_M, ADDR_WIDTH 32, DATA_WIDTH 32, READ_WRITE_MODE READ_ONLY";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_Rst: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 RST, xilinx.com:interface:lmb:1.0 LMB_M RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF SYS_Rst: SIGNAL IS "XIL_INTERFACENAME RST.SYS_Rst, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF SYS_Rst: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.SYS_Rst RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF LMB_Clk: SIGNAL IS "XIL_INTERFACENAME CLK.LMB_Clk, ASSOCIATED_BUSIF LMB_Sl_0:LMB_Sl_1:LMB_Sl_2:LMB_Sl_3:LMB_Sl_4:LMB_Sl_5:LMB_Sl_6:LMB_Sl_7:LMB_Sl_8:LMB_Sl_9:LMB_Sl_10:LMB_Sl_11:LMB_Sl_12:LMB_Sl_13:LMB_Sl_14:LMB_Sl_15:LMB_M, ASSOCIATED_RESET SYS_Rst, FREQ_HZ 25000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_Clk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK.LMB_Clk CLK";
+BEGIN
+  U0 : lmb_v10
+    GENERIC MAP (
+      C_LMB_NUM_SLAVES => 1,
+      C_LMB_DWIDTH => 32,
+      C_LMB_AWIDTH => 32,
+      C_EXT_RESET_HIGH => 1
+    )
+    PORT MAP (
+      LMB_Clk => LMB_Clk,
+      SYS_Rst => SYS_Rst,
+      LMB_Rst => LMB_Rst,
+      M_ABus => M_ABus,
+      M_ReadStrobe => M_ReadStrobe,
+      M_WriteStrobe => M_WriteStrobe,
+      M_AddrStrobe => M_AddrStrobe,
+      M_DBus => M_DBus,
+      M_BE => M_BE,
+      Sl_DBus => Sl_DBus,
+      Sl_Ready => Sl_Ready,
+      Sl_Wait => Sl_Wait,
+      Sl_UE => Sl_UE,
+      Sl_CE => Sl_CE,
+      LMB_ABus => LMB_ABus,
+      LMB_ReadStrobe => LMB_ReadStrobe,
+      LMB_WriteStrobe => LMB_WriteStrobe,
+      LMB_AddrStrobe => LMB_AddrStrobe,
+      LMB_ReadDBus => LMB_ReadDBus,
+      LMB_WriteDBus => LMB_WriteDBus,
+      LMB_Ready => LMB_Ready,
+      LMB_Wait => LMB_Wait,
+      LMB_UE => LMB_UE,
+      LMB_CE => LMB_CE,
+      LMB_BE => LMB_BE
+    );
+END system_bd_ilmb_v10_0_arch;

projects/dl814_k7/common_ipi-bd/basic_driver_bd/ip/system_bd_ilmb_v10_0/synth/system_bd_ilmb_v10_0.vhd

@@ -0,0 +1,198 @@
+-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:lmb_v10:3.0
+-- IP Revision: 9
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+LIBRARY lmb_v10_v3_0_9;
+USE lmb_v10_v3_0_9.lmb_v10;
+
+ENTITY system_bd_ilmb_v10_0 IS
+  PORT (
+    LMB_Clk : IN STD_LOGIC;
+    SYS_Rst : IN STD_LOGIC;
+    LMB_Rst : OUT STD_LOGIC;
+    M_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
+    M_ReadStrobe : IN STD_LOGIC;
+    M_WriteStrobe : IN STD_LOGIC;
+    M_AddrStrobe : IN STD_LOGIC;
+    M_DBus : IN STD_LOGIC_VECTOR(0 TO 31);
+    M_BE : IN STD_LOGIC_VECTOR(0 TO 3);
+    Sl_DBus : IN STD_LOGIC_VECTOR(0 TO 31);
+    Sl_Ready : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    Sl_Wait : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    Sl_UE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    Sl_CE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    LMB_ABus : OUT STD_LOGIC_VECTOR(0 TO 31);
+    LMB_ReadStrobe : OUT STD_LOGIC;
+    LMB_WriteStrobe : OUT STD_LOGIC;
+    LMB_AddrStrobe : OUT STD_LOGIC;
+    LMB_ReadDBus : OUT STD_LOGIC_VECTOR(0 TO 31);
+    LMB_WriteDBus : OUT STD_LOGIC_VECTOR(0 TO 31);
+    LMB_Ready : OUT STD_LOGIC;
+    LMB_Wait : OUT STD_LOGIC;
+    LMB_UE : OUT STD_LOGIC;
+    LMB_CE : OUT STD_LOGIC;
+    LMB_BE : OUT STD_LOGIC_VECTOR(0 TO 3)
+  );
+END system_bd_ilmb_v10_0;
+
+ARCHITECTURE system_bd_ilmb_v10_0_arch OF system_bd_ilmb_v10_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_bd_ilmb_v10_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT lmb_v10 IS
+    GENERIC (
+      C_LMB_NUM_SLAVES : INTEGER;
+      C_LMB_DWIDTH : INTEGER;
+      C_LMB_AWIDTH : INTEGER;
+      C_EXT_RESET_HIGH : INTEGER
+    );
+    PORT (
+      LMB_Clk : IN STD_LOGIC;
+      SYS_Rst : IN STD_LOGIC;
+      LMB_Rst : OUT STD_LOGIC;
+      M_ABus : IN STD_LOGIC_VECTOR(0 TO 31);
+      M_ReadStrobe : IN STD_LOGIC;
+      M_WriteStrobe : IN STD_LOGIC;
+      M_AddrStrobe : IN STD_LOGIC;
+      M_DBus : IN STD_LOGIC_VECTOR(0 TO 31);
+      M_BE : IN STD_LOGIC_VECTOR(0 TO 3);
+      Sl_DBus : IN STD_LOGIC_VECTOR(0 TO 31);
+      Sl_Ready : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      Sl_Wait : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      Sl_UE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      Sl_CE : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      LMB_ABus : OUT STD_LOGIC_VECTOR(0 TO 31);
+      LMB_ReadStrobe : OUT STD_LOGIC;
+      LMB_WriteStrobe : OUT STD_LOGIC;
+      LMB_AddrStrobe : OUT STD_LOGIC;
+      LMB_ReadDBus : OUT STD_LOGIC_VECTOR(0 TO 31);
+      LMB_WriteDBus : OUT STD_LOGIC_VECTOR(0 TO 31);
+      LMB_Ready : OUT STD_LOGIC;
+      LMB_Wait : OUT STD_LOGIC;
+      LMB_UE : OUT STD_LOGIC;
+      LMB_CE : OUT STD_LOGIC;
+      LMB_BE : OUT STD_LOGIC_VECTOR(0 TO 3)
+    );
+  END COMPONENT lmb_v10;
+  ATTRIBUTE X_CORE_INFO : STRING;
+  ATTRIBUTE X_CORE_INFO OF system_bd_ilmb_v10_0_arch: ARCHITECTURE IS "lmb_v10,Vivado 2019.1.3";
+  ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
+  ATTRIBUTE CHECK_LICENSE_TYPE OF system_bd_ilmb_v10_0_arch : ARCHITECTURE IS "system_bd_ilmb_v10_0,lmb_v10,{}";
+  ATTRIBUTE CORE_GENERATION_INFO : STRING;
+  ATTRIBUTE CORE_GENERATION_INFO OF system_bd_ilmb_v10_0_arch: ARCHITECTURE IS "system_bd_ilmb_v10_0,lmb_v10,{x_ipProduct=Vivado 2019.1.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=lmb_v10,x_ipVersion=3.0,x_ipCoreRevision=9,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_LMB_NUM_SLAVES=1,C_LMB_DWIDTH=32,C_LMB_AWIDTH=32,C_EXT_RESET_HIGH=1}";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_BE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 BE";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_CE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M CE";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_UE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M UE";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_Wait: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M WAIT";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_Ready: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M READY";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteDBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 WRITEDBUS";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_ReadDBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M READDBUS";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_AddrStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 ADDRSTROBE";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_WriteStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 WRITESTROBE";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_ReadStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 READSTROBE";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_ABus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 ABUS";
+  ATTRIBUTE X_INTERFACE_INFO OF Sl_CE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 CE";
+  ATTRIBUTE X_INTERFACE_INFO OF Sl_UE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 UE";
+  ATTRIBUTE X_INTERFACE_INFO OF Sl_Wait: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 WAIT";
+  ATTRIBUTE X_INTERFACE_INFO OF Sl_Ready: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 READY";
+  ATTRIBUTE X_INTERFACE_INFO OF Sl_DBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 READDBUS";
+  ATTRIBUTE X_INTERFACE_INFO OF M_BE: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M BE";
+  ATTRIBUTE X_INTERFACE_INFO OF M_DBus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M WRITEDBUS";
+  ATTRIBUTE X_INTERFACE_INFO OF M_AddrStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M ADDRSTROBE";
+  ATTRIBUTE X_INTERFACE_INFO OF M_WriteStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M WRITESTROBE";
+  ATTRIBUTE X_INTERFACE_INFO OF M_ReadStrobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M READSTROBE";
+  ATTRIBUTE X_INTERFACE_INFO OF M_ABus: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_M ABUS";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF LMB_Rst: SIGNAL IS "XIL_INTERFACENAME LMB_Sl_0, ADDR_WIDTH 32, DATA_WIDTH 32, READ_WRITE_MODE READ_WRITE, XIL_INTERFACENAME LMB_M, ADDR_WIDTH 32, DATA_WIDTH 32, READ_WRITE_MODE READ_ONLY";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_Rst: SIGNAL IS "xilinx.com:interface:lmb:1.0 LMB_Sl_0 RST, xilinx.com:interface:lmb:1.0 LMB_M RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF SYS_Rst: SIGNAL IS "XIL_INTERFACENAME RST.SYS_Rst, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF SYS_Rst: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.SYS_Rst RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF LMB_Clk: SIGNAL IS "XIL_INTERFACENAME CLK.LMB_Clk, ASSOCIATED_BUSIF LMB_Sl_0:LMB_Sl_1:LMB_Sl_2:LMB_Sl_3:LMB_Sl_4:LMB_Sl_5:LMB_Sl_6:LMB_Sl_7:LMB_Sl_8:LMB_Sl_9:LMB_Sl_10:LMB_Sl_11:LMB_Sl_12:LMB_Sl_13:LMB_Sl_14:LMB_Sl_15:LMB_M, ASSOCIATED_RESET SYS_Rst, FREQ_HZ 25000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_25M_clk_out1, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF LMB_Clk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK.LMB_Clk CLK";
+BEGIN
+  U0 : lmb_v10
+    GENERIC MAP (
+      C_LMB_NUM_SLAVES => 1,
+      C_LMB_DWIDTH => 32,
+      C_LMB_AWIDTH => 32,
+      C_EXT_RESET_HIGH => 1
+    )
+    PORT MAP (
+      LMB_Clk => LMB_Clk,
+      SYS_Rst => SYS_Rst,
+      LMB_Rst => LMB_Rst,
+      M_ABus => M_ABus,
+      M_ReadStrobe => M_ReadStrobe,
+      M_WriteStrobe => M_WriteStrobe,
+      M_AddrStrobe => M_AddrStrobe,
+      M_DBus => M_DBus,
+      M_BE => M_BE,
+      Sl_DBus => Sl_DBus,
+      Sl_Ready => Sl_Ready,
+      Sl_Wait => Sl_Wait,
+      Sl_UE => Sl_UE,
+      Sl_CE => Sl_CE,
+      LMB_ABus => LMB_ABus,
+      LMB_ReadStrobe => LMB_ReadStrobe,
+      LMB_WriteStrobe => LMB_WriteStrobe,
+      LMB_AddrStrobe => LMB_AddrStrobe,
+      LMB_ReadDBus => LMB_ReadDBus,
+      LMB_WriteDBus => LMB_WriteDBus,
+      LMB_Ready => LMB_Ready,
+      LMB_Wait => LMB_Wait,
+      LMB_UE => LMB_UE,
+      LMB_CE => LMB_CE,
+      LMB_BE => LMB_BE
+    );
+END system_bd_ilmb_v10_0_arch;

projects/dl814_k7/common_ipi-bd/basic_driver_bd/ip/system_bd_ilmb_v10_0/system_bd_ilmb_v10_0.xci

@@ -0,0 +1,116 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>system_bd_ilmb_v10_0</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="lmb_v10" spirit:version="3.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.CLK_DOMAIN">/clk_wiz_25M_clk_out1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_HZ">25000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.PHASE">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_M.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_M.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_M.READ_WRITE_MODE">READ_ONLY</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_0.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_0.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_0.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_1.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_1.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_1.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_10.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_10.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_10.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_11.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_11.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_11.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_12.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_12.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_12.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_13.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_13.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_13.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_14.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_14.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_14.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_15.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_15.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_15.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_2.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_2.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_2.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_3.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_3.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_3.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_4.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_4.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_4.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_5.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_5.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_5.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_6.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_6.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_6.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_7.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_7.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_7.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_8.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_8.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_8.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_9.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_9.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.LMB_SL_9.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST.SYS_RST.INSERT_VIP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EXT_RESET_HIGH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LMB_AWIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LMB_DWIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LMB_NUM_SLAVES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_EXT_RESET_HIGH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_LMB_AWIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_LMB_DWIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_LMB_NUM_SLAVES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">system_bd_ilmb_v10_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k410t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.CLK_DOMAIN" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.FREQ_HZ" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.LMB_CLK.PHASE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_M.DATA_WIDTH" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_M.READ_WRITE_MODE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_0.ADDR_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.LMB_SL_0.DATA_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_AWIDTH" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LMB_DWIDTH" xilinx:valueSource="propagated"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>

projects/dl814_k7/common_ipi-bd/basic_driver_bd/ip/system_bd_ilmb_v10_0/system_bd_ilmb_v10_0.xdc

@@ -0,0 +1 @@
+set_false_path -through [get_ports "SYS_Rst"]

projects/dl814_k7/common_ipi-bd/basic_driver_bd/ip/system_bd_ilmb_v10_0/system_bd_ilmb_v10_0_ooc.xdc

@@ -0,0 +1,57 @@
+# (c) Copyright 2012-2023 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+# DO NOT MODIFY THIS FILE.
+# #########################################################
+#
+# This XDC is used only in OOC mode for synthesis, implementation
+#
+# #########################################################
+
+
+create_clock -period 40 -name LMB_Clk [get_ports LMB_Clk]
+
+

projects/dl814_k7/common_ipi-bd/basic_driver_bd/ip/system_bd_ilmb_v10_0/system_bd_ilmb_v10_0_stub.v

@@ -0,0 +1,47 @@
+// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep  4 09:45:24 MDT 2019
+// Date        : Sat Mar 18 23:57:10 2023
+// Host        : JOSH-ASUS-Z690 running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode synth_stub -rename_top system_bd_ilmb_v10_0 -prefix
+//               system_bd_ilmb_v10_0_ system_bd_dlmb_v10_0_stub.v
+// Design      : system_bd_dlmb_v10_0
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7k410tffg900-2
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* x_core_info = "lmb_v10,Vivado 2019.1.3" *)
+module system_bd_ilmb_v10_0(LMB_Clk, SYS_Rst, LMB_Rst, M_ABus, M_ReadStrobe, 
+  M_WriteStrobe, M_AddrStrobe, M_DBus, M_BE, Sl_DBus, Sl_Ready, Sl_Wait, Sl_UE, Sl_CE, LMB_ABus, 
+  LMB_ReadStrobe, LMB_WriteStrobe, LMB_AddrStrobe, LMB_ReadDBus, LMB_WriteDBus, LMB_Ready, 
+  LMB_Wait, LMB_UE, LMB_CE, LMB_BE)
+/* synthesis syn_black_box black_box_pad_pin="LMB_Clk,SYS_Rst,LMB_Rst,M_ABus[0:31],M_ReadStrobe,M_WriteStrobe,M_AddrStrobe,M_DBus[0:31],M_BE[0:3],Sl_DBus[0:31],Sl_Ready[0:0],Sl_Wait[0:0],Sl_UE[0:0],Sl_CE[0:0],LMB_ABus[0:31],LMB_ReadStrobe,LMB_WriteStrobe,LMB_AddrStrobe,LMB_ReadDBus[0:31],LMB_WriteDBus[0:31],LMB_Ready,LMB_Wait,LMB_UE,LMB_CE,LMB_BE[0:3]" */;
+  input LMB_Clk;
+  input SYS_Rst;
+  output LMB_Rst;
+  input [0:31]M_ABus;
+  input M_ReadStrobe;
+  input M_WriteStrobe;
+  input M_AddrStrobe;
+  input [0:31]M_DBus;
+  input [0:3]M_BE;
+  input [0:31]Sl_DBus;
+  input [0:0]Sl_Ready;
+  input [0:0]Sl_Wait;
+  input [0:0]Sl_UE;
+  input [0:0]Sl_CE;
+  output [0:31]LMB_ABus;
+  output LMB_ReadStrobe;
+  output LMB_WriteStrobe;
+  output LMB_AddrStrobe;
+  output [0:31]LMB_ReadDBus;
+  output [0:31]LMB_WriteDBus;
+  output LMB_Ready;
+  output LMB_Wait;
+  output LMB_UE;
+  output LMB_CE;
+  output [0:3]LMB_BE;
+endmodule

projects/dl814_k7/common_ipi-bd/basic_driver_bd/ip/system_bd_ilmb_v10_0/system_bd_ilmb_v10_0_stub.vhdl

@@ -0,0 +1,54 @@
+-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep  4 09:45:24 MDT 2019
+-- Date        : Sat Mar 18 23:57:10 2023
+-- Host        : JOSH-ASUS-Z690 running 64-bit major release  (build 9200)
+-- Command     : write_vhdl -force -mode synth_stub -rename_top system_bd_ilmb_v10_0 -prefix
+--               system_bd_ilmb_v10_0_ system_bd_dlmb_v10_0_stub.vhdl
+-- Design      : system_bd_dlmb_v10_0
+-- Purpose     : Stub declaration of top-level module interface
+-- Device      : xc7k410tffg900-2
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity system_bd_ilmb_v10_0 is
+  Port ( 
+    LMB_Clk : in STD_LOGIC;
+    SYS_Rst : in STD_LOGIC;
+    LMB_Rst : out STD_LOGIC;
+    M_ABus : in STD_LOGIC_VECTOR ( 0 to 31 );
+    M_ReadStrobe : in STD_LOGIC;
+    M_WriteStrobe : in STD_LOGIC;
+    M_AddrStrobe : in STD_LOGIC;
+    M_DBus : in STD_LOGIC_VECTOR ( 0 to 31 );
+    M_BE : in STD_LOGIC_VECTOR ( 0 to 3 );
+    Sl_DBus : in STD_LOGIC_VECTOR ( 0 to 31 );
+    Sl_Ready : in STD_LOGIC_VECTOR ( 0 to 0 );
+    Sl_Wait : in STD_LOGIC_VECTOR ( 0 to 0 );
+    Sl_UE : in STD_LOGIC_VECTOR ( 0 to 0 );
+    Sl_CE : in STD_LOGIC_VECTOR ( 0 to 0 );
+    LMB_ABus : out STD_LOGIC_VECTOR ( 0 to 31 );
+    LMB_ReadStrobe : out STD_LOGIC;
+    LMB_WriteStrobe : out STD_LOGIC;
+    LMB_AddrStrobe : out STD_LOGIC;
+    LMB_ReadDBus : out STD_LOGIC_VECTOR ( 0 to 31 );
+    LMB_WriteDBus : out STD_LOGIC_VECTOR ( 0 to 31 );
+    LMB_Ready : out STD_LOGIC;
+    LMB_Wait : out STD_LOGIC;
+    LMB_UE : out STD_LOGIC;
+    LMB_CE : out STD_LOGIC;
+    LMB_BE : out STD_LOGIC_VECTOR ( 0 to 3 )
+  );
+
+end system_bd_ilmb_v10_0;
+
+architecture stub of system_bd_ilmb_v10_0 is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "LMB_Clk,SYS_Rst,LMB_Rst,M_ABus[0:31],M_ReadStrobe,M_WriteStrobe,M_AddrStrobe,M_DBus[0:31],M_BE[0:3],Sl_DBus[0:31],Sl_Ready[0:0],Sl_Wait[0:0],Sl_UE[0:0],Sl_CE[0:0],LMB_ABus[0:31],LMB_ReadStrobe,LMB_WriteStrobe,LMB_AddrStrobe,LMB_ReadDBus[0:31],LMB_WriteDBus[0:31],LMB_Ready,LMB_Wait,LMB_UE,LMB_CE,LMB_BE[0:3]";
+attribute x_core_info : string;
+attribute x_core_info of stub : architecture is "lmb_v10,Vivado 2019.1.3";
+begin
+end;

projects/dl814_k7/common_ipi-bd/basic_driver_bd/ip/system_bd_lmb_bram_0/sim/system_bd_lmb_bram_0.v

@@ -0,0 +1,249 @@
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
+// IP Revision: 3
+
+`timescale 1ns/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module system_bd_lmb_bram_0 (
+  clka,
+  rsta,
+  ena,
+  wea,
+  addra,
+  dina,
+  douta,
+  clkb,
+  rstb,
+  enb,
+  web,
+  addrb,
+  dinb,
+  doutb,
+  rsta_busy,
+  rstb_busy
+);
+
+(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
+input wire clka;
+(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA RST" *)
+input wire rsta;
+(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *)
+input wire ena;
+(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *)
+input wire [3 : 0] wea;
+(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
+input wire [31 : 0] addra;
+(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *)
+input wire [31 : 0] dina;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 262144, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE BRAM_CTRL, READ_WRITE_MODE READ_WRITE, READ_LATENCY 1" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
+output wire [31 : 0] douta;
+(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK" *)
+input wire clkb;
+(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB RST" *)
+input wire rstb;
+(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB EN" *)
+input wire enb;
+(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB WE" *)
+input wire [3 : 0] web;
+(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR" *)
+input wire [31 : 0] addrb;
+(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN" *)
+input wire [31 : 0] dinb;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME BRAM_PORTB, MEM_SIZE 262144, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE BRAM_CTRL, READ_WRITE_MODE READ_WRITE, READ_LATENCY 1" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT" *)
+output wire [31 : 0] doutb;
+output wire rsta_busy;
+output wire rstb_busy;
+
+  blk_mem_gen_v8_4_3 #(
+    .C_FAMILY("kintex7"),
+    .C_XDEVICEFAMILY("kintex7"),
+    .C_ELABORATION_DIR("./"),
+    .C_INTERFACE_TYPE(0),
+    .C_AXI_TYPE(1),
+    .C_AXI_SLAVE_TYPE(0),
+    .C_USE_BRAM_BLOCK(1),
+    .C_ENABLE_32BIT_ADDRESS(1),
+    .C_CTRL_ECC_ALGO("NONE"),
+    .C_HAS_AXI_ID(0),
+    .C_AXI_ID_WIDTH(4),
+    .C_MEM_TYPE(2),
+    .C_BYTE_SIZE(8),
+    .C_ALGORITHM(1),
+    .C_PRIM_TYPE(1),
+    .C_LOAD_INIT_FILE(0),
+    .C_INIT_FILE_NAME("no_coe_file_loaded"),
+    .C_INIT_FILE("system_bd_lmb_bram_0.mem"),
+    .C_USE_DEFAULT_DATA(0),
+    .C_DEFAULT_DATA("0"),
+    .C_HAS_RSTA(1),
+    .C_RST_PRIORITY_A("CE"),
+    .C_RSTRAM_A(0),
+    .C_INITA_VAL("0"),
+    .C_HAS_ENA(1),
+    .C_HAS_REGCEA(0),
+    .C_USE_BYTE_WEA(1),
+    .C_WEA_WIDTH(4),
+    .C_WRITE_MODE_A("WRITE_FIRST"),
+    .C_WRITE_WIDTH_A(32),
+    .C_READ_WIDTH_A(32),
+    .C_WRITE_DEPTH_A(65536),
+    .C_READ_DEPTH_A(65536),
+    .C_ADDRA_WIDTH(32),
+    .C_HAS_RSTB(1),
+    .C_RST_PRIORITY_B("CE"),
+    .C_RSTRAM_B(0),
+    .C_INITB_VAL("0"),
+    .C_HAS_ENB(1),
+    .C_HAS_REGCEB(0),
+    .C_USE_BYTE_WEB(1),
+    .C_WEB_WIDTH(4),
+    .C_WRITE_MODE_B("WRITE_FIRST"),
+    .C_WRITE_WIDTH_B(32),
+    .C_READ_WIDTH_B(32),
+    .C_WRITE_DEPTH_B(65536),
+    .C_READ_DEPTH_B(65536),
+    .C_ADDRB_WIDTH(32),
+    .C_HAS_MEM_OUTPUT_REGS_A(0),
+    .C_HAS_MEM_OUTPUT_REGS_B(0),
+    .C_HAS_MUX_OUTPUT_REGS_A(0),
+    .C_HAS_MUX_OUTPUT_REGS_B(0),
+    .C_MUX_PIPELINE_STAGES(0),
+    .C_HAS_SOFTECC_INPUT_REGS_A(0),
+    .C_HAS_SOFTECC_OUTPUT_REGS_B(0),
+    .C_USE_SOFTECC(0),
+    .C_USE_ECC(0),
+    .C_EN_ECC_PIPE(0),
+    .C_READ_LATENCY_A(1),
+    .C_READ_LATENCY_B(1),
+    .C_HAS_INJECTERR(0),
+    .C_SIM_COLLISION_CHECK("ALL"),
+    .C_COMMON_CLK(0),
+    .C_DISABLE_WARN_BHV_COLL(0),
+    .C_EN_SLEEP_PIN(0),
+    .C_USE_URAM(0),
+    .C_EN_RDADDRA_CHG(0),
+    .C_EN_RDADDRB_CHG(0),
+    .C_EN_DEEPSLEEP_PIN(0),
+    .C_EN_SHUTDOWN_PIN(0),
+    .C_EN_SAFETY_CKT(1),
+    .C_DISABLE_WARN_BHV_RANGE(0),
+    .C_COUNT_36K_BRAM("64"),
+    .C_COUNT_18K_BRAM("0"),
+    .C_EST_POWER_SUMMARY("Estimated Power for IP     :     20.388004 mW")
+  ) inst (
+    .clka(clka),
+    .rsta(rsta),
+    .ena(ena),
+    .regcea(1'D0),
+    .wea(wea),
+    .addra(addra),
+    .dina(dina),
+    .douta(douta),
+    .clkb(clkb),
+    .rstb(rstb),
+    .enb(enb),
+    .regceb(1'D0),
+    .web(web),
+    .addrb(addrb),
+    .dinb(dinb),
+    .doutb(doutb),
+    .injectsbiterr(1'D0),
+    .injectdbiterr(1'D0),
+    .eccpipece(1'D0),
+    .sbiterr(),
+    .dbiterr(),
+    .rdaddrecc(),
+    .sleep(1'D0),
+    .deepsleep(1'D0),
+    .shutdown(1'D0),
+    .rsta_busy(rsta_busy),
+    .rstb_busy(rstb_busy),
+    .s_aclk(1'H0),
+    .s_aresetn(1'D0),
+    .s_axi_awid(4'B0),
+    .s_axi_awaddr(32'B0),
+    .s_axi_awlen(8'B0),
+    .s_axi_awsize(3'B0),
+    .s_axi_awburst(2'B0),
+    .s_axi_awvalid(1'D0),
+    .s_axi_awready(),
+    .s_axi_wdata(32'B0),
+    .s_axi_wstrb(4'B0),
+    .s_axi_wlast(1'D0),
+    .s_axi_wvalid(1'D0),
+    .s_axi_wready(),
+    .s_axi_bid(),
+    .s_axi_bresp(),
+    .s_axi_bvalid(),
+    .s_axi_bready(1'D0),
+    .s_axi_arid(4'B0),
+    .s_axi_araddr(32'B0),
+    .s_axi_arlen(8'B0),
+    .s_axi_arsize(3'B0),
+    .s_axi_arburst(2'B0),
+    .s_axi_arvalid(1'D0),
+    .s_axi_arready(),
+    .s_axi_rid(),
+    .s_axi_rdata(),
+    .s_axi_rresp(),
+    .s_axi_rlast(),
+    .s_axi_rvalid(),
+    .s_axi_rready(1'D0),
+    .s_axi_injectsbiterr(1'D0),
+    .s_axi_injectdbiterr(1'D0),
+    .s_axi_sbiterr(),
+    .s_axi_dbiterr(),
+    .s_axi_rdaddrecc()
+  );
+endmodule

projects/dl814_k7/common_ipi-bd/basic_driver_bd/ip/system_bd_lmb_bram_0/synth/system_bd_lmb_bram_0.vhd

@@ -0,0 +1,381 @@
+-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
+-- IP Revision: 3
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+LIBRARY blk_mem_gen_v8_4_3;
+USE blk_mem_gen_v8_4_3.blk_mem_gen_v8_4_3;
+
+ENTITY system_bd_lmb_bram_0 IS
+  PORT (
+    clka : IN STD_LOGIC;
+    rsta : IN STD_LOGIC;
+    ena : IN STD_LOGIC;
+    wea : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+    addra : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    clkb : IN STD_LOGIC;
+    rstb : IN STD_LOGIC;
+    enb : IN STD_LOGIC;
+    web : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+    addrb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    rsta_busy : OUT STD_LOGIC;
+    rstb_busy : OUT STD_LOGIC
+  );
+END system_bd_lmb_bram_0;
+
+ARCHITECTURE system_bd_lmb_bram_0_arch OF system_bd_lmb_bram_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_bd_lmb_bram_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT blk_mem_gen_v8_4_3 IS
+    GENERIC (
+      C_FAMILY : STRING;
+      C_XDEVICEFAMILY : STRING;
+      C_ELABORATION_DIR : STRING;
+      C_INTERFACE_TYPE : INTEGER;
+      C_AXI_TYPE : INTEGER;
+      C_AXI_SLAVE_TYPE : INTEGER;
+      C_USE_BRAM_BLOCK : INTEGER;
+      C_ENABLE_32BIT_ADDRESS : INTEGER;
+      C_CTRL_ECC_ALGO : STRING;
+      C_HAS_AXI_ID : INTEGER;
+      C_AXI_ID_WIDTH : INTEGER;
+      C_MEM_TYPE : INTEGER;
+      C_BYTE_SIZE : INTEGER;
+      C_ALGORITHM : INTEGER;
+      C_PRIM_TYPE : INTEGER;
+      C_LOAD_INIT_FILE : INTEGER;
+      C_INIT_FILE_NAME : STRING;
+      C_INIT_FILE : STRING;
+      C_USE_DEFAULT_DATA : INTEGER;
+      C_DEFAULT_DATA : STRING;
+      C_HAS_RSTA : INTEGER;
+      C_RST_PRIORITY_A : STRING;
+      C_RSTRAM_A : INTEGER;
+      C_INITA_VAL : STRING;
+      C_HAS_ENA : INTEGER;
+      C_HAS_REGCEA : INTEGER;
+      C_USE_BYTE_WEA : INTEGER;
+      C_WEA_WIDTH : INTEGER;
+      C_WRITE_MODE_A : STRING;
+      C_WRITE_WIDTH_A : INTEGER;
+      C_READ_WIDTH_A : INTEGER;
+      C_WRITE_DEPTH_A : INTEGER;
+      C_READ_DEPTH_A : INTEGER;
+      C_ADDRA_WIDTH : INTEGER;
+      C_HAS_RSTB : INTEGER;
+      C_RST_PRIORITY_B : STRING;
+      C_RSTRAM_B : INTEGER;
+      C_INITB_VAL : STRING;
+      C_HAS_ENB : INTEGER;
+      C_HAS_REGCEB : INTEGER;
+      C_USE_BYTE_WEB : INTEGER;
+      C_WEB_WIDTH : INTEGER;
+      C_WRITE_MODE_B : STRING;
+      C_WRITE_WIDTH_B : INTEGER;
+      C_READ_WIDTH_B : INTEGER;
+      C_WRITE_DEPTH_B : INTEGER;
+      C_READ_DEPTH_B : INTEGER;
+      C_ADDRB_WIDTH : INTEGER;
+      C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
+      C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
+      C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
+      C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
+      C_MUX_PIPELINE_STAGES : INTEGER;
+      C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
+      C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
+      C_USE_SOFTECC : INTEGER;
+      C_USE_ECC : INTEGER;
+      C_EN_ECC_PIPE : INTEGER;
+      C_READ_LATENCY_A : INTEGER;
+      C_READ_LATENCY_B : INTEGER;
+      C_HAS_INJECTERR : INTEGER;
+      C_SIM_COLLISION_CHECK : STRING;
+      C_COMMON_CLK : INTEGER;
+      C_DISABLE_WARN_BHV_COLL : INTEGER;
+      C_EN_SLEEP_PIN : INTEGER;
+      C_USE_URAM : INTEGER;
+      C_EN_RDADDRA_CHG : INTEGER;
+      C_EN_RDADDRB_CHG : INTEGER;
+      C_EN_DEEPSLEEP_PIN : INTEGER;
+      C_EN_SHUTDOWN_PIN : INTEGER;
+      C_EN_SAFETY_CKT : INTEGER;
+      C_DISABLE_WARN_BHV_RANGE : INTEGER;
+      C_COUNT_36K_BRAM : STRING;
+      C_COUNT_18K_BRAM : STRING;
+      C_EST_POWER_SUMMARY : STRING
+    );
+    PORT (
+      clka : IN STD_LOGIC;
+      rsta : IN STD_LOGIC;
+      ena : IN STD_LOGIC;
+      regcea : IN STD_LOGIC;
+      wea : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      addra : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      clkb : IN STD_LOGIC;
+      rstb : IN STD_LOGIC;
+      enb : IN STD_LOGIC;
+      regceb : IN STD_LOGIC;
+      web : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      addrb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      injectsbiterr : IN STD_LOGIC;
+      injectdbiterr : IN STD_LOGIC;
+      eccpipece : IN STD_LOGIC;
+      sbiterr : OUT STD_LOGIC;
+      dbiterr : OUT STD_LOGIC;
+      rdaddrecc : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      sleep : IN STD_LOGIC;
+      deepsleep : IN STD_LOGIC;
+      shutdown : IN STD_LOGIC;
+      rsta_busy : OUT STD_LOGIC;
+      rstb_busy : OUT STD_LOGIC;
+      s_aclk : IN STD_LOGIC;
+      s_aresetn : IN STD_LOGIC;
+      s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+      s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+      s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+      s_axi_awvalid : IN STD_LOGIC;
+      s_axi_awready : OUT STD_LOGIC;
+      s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      s_axi_wlast : IN STD_LOGIC;
+      s_axi_wvalid : IN STD_LOGIC;
+      s_axi_wready : OUT STD_LOGIC;
+      s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+      s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      s_axi_bvalid : OUT STD_LOGIC;
+      s_axi_bready : IN STD_LOGIC;
+      s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+      s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+      s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+      s_axi_arvalid : IN STD_LOGIC;
+      s_axi_arready : OUT STD_LOGIC;
+      s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+      s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      s_axi_rlast : OUT STD_LOGIC;
+      s_axi_rvalid : OUT STD_LOGIC;
+      s_axi_rready : IN STD_LOGIC;
+      s_axi_injectsbiterr : IN STD_LOGIC;
+      s_axi_injectdbiterr : IN STD_LOGIC;
+      s_axi_sbiterr : OUT STD_LOGIC;
+      s_axi_dbiterr : OUT STD_LOGIC;
+      s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+    );
+  END COMPONENT blk_mem_gen_v8_4_3;
+  ATTRIBUTE X_CORE_INFO : STRING;
+  ATTRIBUTE X_CORE_INFO OF system_bd_lmb_bram_0_arch: ARCHITECTURE IS "blk_mem_gen_v8_4_3,Vivado 2019.1.3";
+  ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
+  ATTRIBUTE CHECK_LICENSE_TYPE OF system_bd_lmb_bram_0_arch : ARCHITECTURE IS "system_bd_lmb_bram_0,blk_mem_gen_v8_4_3,{}";
+  ATTRIBUTE CORE_GENERATION_INFO : STRING;
+  ATTRIBUTE CORE_GENERATION_INFO OF system_bd_lmb_bram_0_arch: ARCHITECTURE IS "system_bd_lmb_bram_0,blk_mem_gen_v8_4_3,{x_ipProduct=Vivado 2019.1.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.4,x_ipCoreRevision=3,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=kintex7,C_XDEVICEFAMILY=kintex7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=1,C_ENABLE_32BIT_ADDRESS=1,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=2,C_BYTE_SIZE=8,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE" & 
+"_NAME=no_coe_file_loaded,C_INIT_FILE=system_bd_lmb_bram_0.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=1,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=1,C_WEA_WIDTH=4,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=32,C_READ_WIDTH_A=32,C_WRITE_DEPTH_A=65536,C_READ_DEPTH_A=65536,C_ADDRA_WIDTH=32,C_HAS_RSTB=1,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=1,C_HAS_REGCEB=0,C_USE_BYTE_WEB=1,C_WEB_WIDTH=4,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH" & 
+"_B=32,C_READ_WIDTH_B=32,C_WRITE_DEPTH_B=65536,C_READ_DEPTH_B=65536,C_ADDRB_WIDTH=32,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_READ_LATENCY_A=1,C_READ_LATENCY_B=1,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_" & 
+"CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=1,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=64,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP     _     20.388004 mW}";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
+  ATTRIBUTE X_INTERFACE_INFO OF dinb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN";
+  ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
+  ATTRIBUTE X_INTERFACE_INFO OF web: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB WE";
+  ATTRIBUTE X_INTERFACE_INFO OF enb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
+  ATTRIBUTE X_INTERFACE_INFO OF rstb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF clkb: SIGNAL IS "XIL_INTERFACENAME BRAM_PORTB, MEM_SIZE 262144, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE BRAM_CTRL, READ_WRITE_MODE READ_WRITE, READ_LATENCY 1";
+  ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
+  ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
+  ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
+  ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
+  ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
+  ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
+  ATTRIBUTE X_INTERFACE_INFO OF rsta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA RST";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF clka: SIGNAL IS "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 262144, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE BRAM_CTRL, READ_WRITE_MODE READ_WRITE, READ_LATENCY 1";
+  ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
+BEGIN
+  U0 : blk_mem_gen_v8_4_3
+    GENERIC MAP (
+      C_FAMILY => "kintex7",
+      C_XDEVICEFAMILY => "kintex7",
+      C_ELABORATION_DIR => "./",
+      C_INTERFACE_TYPE => 0,
+      C_AXI_TYPE => 1,
+      C_AXI_SLAVE_TYPE => 0,
+      C_USE_BRAM_BLOCK => 1,
+      C_ENABLE_32BIT_ADDRESS => 1,
+      C_CTRL_ECC_ALGO => "NONE",
+      C_HAS_AXI_ID => 0,
+      C_AXI_ID_WIDTH => 4,
+      C_MEM_TYPE => 2,
+      C_BYTE_SIZE => 8,
+      C_ALGORITHM => 1,
+      C_PRIM_TYPE => 1,
+      C_LOAD_INIT_FILE => 0,
+      C_INIT_FILE_NAME => "no_coe_file_loaded",
+      C_INIT_FILE => "system_bd_lmb_bram_0.mem",
+      C_USE_DEFAULT_DATA => 0,
+      C_DEFAULT_DATA => "0",
+      C_HAS_RSTA => 1,
+      C_RST_PRIORITY_A => "CE",
+      C_RSTRAM_A => 0,
+      C_INITA_VAL => "0",
+      C_HAS_ENA => 1,
+      C_HAS_REGCEA => 0,
+      C_USE_BYTE_WEA => 1,
+      C_WEA_WIDTH => 4,
+      C_WRITE_MODE_A => "WRITE_FIRST",
+      C_WRITE_WIDTH_A => 32,
+      C_READ_WIDTH_A => 32,
+      C_WRITE_DEPTH_A => 65536,
+      C_READ_DEPTH_A => 65536,
+      C_ADDRA_WIDTH => 32,
+      C_HAS_RSTB => 1,
+      C_RST_PRIORITY_B => "CE",
+      C_RSTRAM_B => 0,
+      C_INITB_VAL => "0",
+      C_HAS_ENB => 1,
+      C_HAS_REGCEB => 0,
+      C_USE_BYTE_WEB => 1,
+      C_WEB_WIDTH => 4,
+      C_WRITE_MODE_B => "WRITE_FIRST",
+      C_WRITE_WIDTH_B => 32,
+      C_READ_WIDTH_B => 32,
+      C_WRITE_DEPTH_B => 65536,
+      C_READ_DEPTH_B => 65536,
+      C_ADDRB_WIDTH => 32,
+      C_HAS_MEM_OUTPUT_REGS_A => 0,
+      C_HAS_MEM_OUTPUT_REGS_B => 0,
+      C_HAS_MUX_OUTPUT_REGS_A => 0,
+      C_HAS_MUX_OUTPUT_REGS_B => 0,
+      C_MUX_PIPELINE_STAGES => 0,
+      C_HAS_SOFTECC_INPUT_REGS_A => 0,
+      C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
+      C_USE_SOFTECC => 0,
+      C_USE_ECC => 0,
+      C_EN_ECC_PIPE => 0,
+      C_READ_LATENCY_A => 1,
+      C_READ_LATENCY_B => 1,
+      C_HAS_INJECTERR => 0,
+      C_SIM_COLLISION_CHECK => "ALL",
+      C_COMMON_CLK => 0,
+      C_DISABLE_WARN_BHV_COLL => 0,
+      C_EN_SLEEP_PIN => 0,
+      C_USE_URAM => 0,
+      C_EN_RDADDRA_CHG => 0,
+      C_EN_RDADDRB_CHG => 0,
+      C_EN_DEEPSLEEP_PIN => 0,
+      C_EN_SHUTDOWN_PIN => 0,
+      C_EN_SAFETY_CKT => 1,
+      C_DISABLE_WARN_BHV_RANGE => 0,
+      C_COUNT_36K_BRAM => "64",
+      C_COUNT_18K_BRAM => "0",
+      C_EST_POWER_SUMMARY => "Estimated Power for IP     :     20.388004 mW"
+    )
+    PORT MAP (
+      clka => clka,
+      rsta => rsta,
+      ena => ena,
+      regcea => '0',
+      wea => wea,
+      addra => addra,
+      dina => dina,
+      douta => douta,
+      clkb => clkb,
+      rstb => rstb,
+      enb => enb,
+      regceb => '0',
+      web => web,
+      addrb => addrb,
+      dinb => dinb,
+      doutb => doutb,
+      injectsbiterr => '0',
+      injectdbiterr => '0',
+      eccpipece => '0',
+      sleep => '0',
+      deepsleep => '0',
+      shutdown => '0',
+      rsta_busy => rsta_busy,
+      rstb_busy => rstb_busy,
+      s_aclk => '0',
+      s_aresetn => '0',
+      s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
+      s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
+      s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
+      s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
+      s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
+      s_axi_awvalid => '0',
+      s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
+      s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
+      s_axi_wlast => '0',
+      s_axi_wvalid => '0',
+      s_axi_bready => '0',
+      s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
+      s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
+      s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
+      s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
+      s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
+      s_axi_arvalid => '0',
+      s_axi_rready => '0',
+      s_axi_injectsbiterr => '0',
+      s_axi_injectdbiterr => '0'
+    );
+END system_bd_lmb_bram_0_arch;

projects/dl814_k7/common_ipi-bd/basic_driver_bd/ip/system_bd_lmb_bram_0/system_bd_lmb_bram_0.xci

@@ -0,0 +1,292 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>system_bd_lmb_bram_0</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="blk_mem_gen" spirit:version="8.4"/>
+      <spirit:configurableElementValues>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ADDR_WIDTH">32</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.CLK_DOMAIN"/>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.DATA_WIDTH">32</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BURST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_CACHE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_LOCK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_PROT">1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PROTOCOL">AXI4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.SUPPORTS_NARROW_BURST">1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MASTER_TYPE">BRAM_CTRL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_ECC">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_SIZE">262144</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.READ_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MASTER_TYPE">BRAM_CTRL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_ECC">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_SIZE">262144</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_WIDTH">32</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RSTA">1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_WIDTH_B">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RSTRAM_A">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RSTRAM_B">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RST_PRIORITY_A">CE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RST_PRIORITY_B">CE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SIM_COLLISION_CHECK">ALL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_BRAM_BLOCK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_BYTE_WEA">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_BYTE_WEB">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_DATA">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SOFTECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_URAM">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WEA_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WEB_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_DEPTH_A">65536</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_DEPTH_B">65536</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_MODE_A">WRITE_FIRST</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_MODE_B">WRITE_FIRST</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_WIDTH_A">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_WIDTH_B">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XDEVICEFAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_ID_Width">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_Slave_Type">Memory_Slave</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_Type">AXI4_Full</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Additional_Inputs_for_Power_Estimation">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Algorithm">Minimum_Area</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Assume_Synchronous_Clk">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Byte_Size">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CTRL_ECC_ALGO">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coe_File">no_coe_file_loaded</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Collision_Warnings">ALL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">system_bd_lmb_bram_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Collision_Warnings">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Out_of_Range_Warnings">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ECC">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_DEEPSLEEP_PIN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_ECC_PIPE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SAFETY_CKT">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SHUTDOWN_PIN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SLEEP_PIN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_32bit_Address">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_A">Use_ENA_Pin</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_B">Use_ENB_Pin</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Error_Injection_Type">Single_Bit_Error_Injection</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fill_Remaining_Memory_Locations">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Interface_Type">Native</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Load_Init_File">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MEM_FILE">system_bd_lmb_bram_0.mem</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Memory_Type">True_Dual_Port_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Operating_Mode_A">WRITE_FIRST</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Operating_Mode_B">WRITE_FIRST</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Reset_Value_A">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Reset_Value_B">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_type_to_Implement">BRAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Pipeline_Stages">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Clock">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Enable_Rate">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Write_Rate">50</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Clock">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Enable_Rate">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Write_Rate">50</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Primitive">8kx2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RD_ADDR_CHNG_A">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RD_ADDR_CHNG_B">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_LATENCY_A">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_LATENCY_B">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Width_A">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Width_B">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Core">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortB_Output_of_Memory_Core">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortB_Output_of_Memory_Primitives">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Remaining_Memory_Locations">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Memory_Latch_A">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Memory_Latch_B">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Priority_A">CE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Priority_B">CE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">SYNC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_AXI_ID">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Byte_Write_Enable">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Error_Injection_Pins">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_REGCEA_Pin">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_REGCEB_Pin">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_RSTA_Pin">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_RSTB_Pin">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Depth_A">65536</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Width_A">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Width_B">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecctype">No_ECC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.register_porta_input_of_softecc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.register_portb_output_of_softecc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.softecc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_bram_block">BRAM_Controller</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k410t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">3</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MASTER_TYPE" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_ECC" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_SIZE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_WIDTH" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.READ_LATENCY" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.READ_WRITE_MODE" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MASTER_TYPE" xilinx:valueSource="user" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_ECC" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_SIZE" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_WIDTH" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.READ_LATENCY" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.READ_WRITE_MODE" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CTRL_ECC_ALGO" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MEM_FILE" xilinx:valueSource="ip_propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Memory_Type" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.READ_LATENCY_A" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.READ_LATENCY_B" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_A" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_B" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Depth_A" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_A" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_B" xilinx:valueSource="propagated"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.use_bram_block" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>

projects/dl814_k7/common_ipi-bd/basic_driver_bd/ip/system_bd_lmb_bram_0/system_bd_lmb_bram_0_ooc.xdc

@@ -0,0 +1,58 @@
+################################################################################
+#
+# (c) Copyright 2002 - 2013 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+################################################################################
+
+# Core Period Constraint. This constraint can be modified, and is
+# valid as long as it is met after place and route.
+create_clock -name "TS_CLKA" -period 20.0 [ get_ports clka ]
+    set_property HD.CLK_SRC BUFGCTRL_X0Y0 [ get_ports clka ]
+  
+create_clock -name "TS_CLKB" -period 20.0 [ get_ports clkb ]
+    set_property HD.CLK_SRC BUFGCTRL_X0Y1 [ get_ports clkb ]
+################################################################################

projects/dl814_k7/common_ipi-bd/basic_driver_bd/ip/system_bd_lmb_bram_0/system_bd_lmb_bram_0_stub.v

@@ -0,0 +1,36 @@
+// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep  4 09:45:24 MDT 2019
+// Date        : Sat Mar 18 23:58:03 2023
+// Host        : JOSH-ASUS-Z690 running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode synth_stub -rename_top system_bd_lmb_bram_0 -prefix
+//               system_bd_lmb_bram_0_ system_bd_lmb_bram_0_stub.v
+// Design      : system_bd_lmb_bram_0
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7k410tffg900-2
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* x_core_info = "blk_mem_gen_v8_4_3,Vivado 2019.1.3" *)
+module system_bd_lmb_bram_0(clka, rsta, ena, wea, addra, dina, douta, clkb, rstb, enb, 
+  web, addrb, dinb, doutb, rsta_busy, rstb_busy)
+/* synthesis syn_black_box black_box_pad_pin="clka,rsta,ena,wea[3:0],addra[31:0],dina[31:0],douta[31:0],clkb,rstb,enb,web[3:0],addrb[31:0],dinb[31:0],doutb[31:0],rsta_busy,rstb_busy" */;
+  input clka;
+  input rsta;
+  input ena;
+  input [3:0]wea;
+  input [31:0]addra;
+  input [31:0]dina;
+  output [31:0]douta;
+  input clkb;
+  input rstb;
+  input enb;
+  input [3:0]web;
+  input [31:0]addrb;
+  input [31:0]dinb;
+  output [31:0]doutb;
+  output rsta_busy;
+  output rstb_busy;
+endmodule

projects/dl814_k7/common_ipi-bd/basic_driver_bd/ip/system_bd_lmb_bram_0/system_bd_lmb_bram_0_stub.vhdl

@@ -0,0 +1,45 @@
+-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep  4 09:45:24 MDT 2019
+-- Date        : Sat Mar 18 23:58:03 2023
+-- Host        : JOSH-ASUS-Z690 running 64-bit major release  (build 9200)
+-- Command     : write_vhdl -force -mode synth_stub -rename_top system_bd_lmb_bram_0 -prefix
+--               system_bd_lmb_bram_0_ system_bd_lmb_bram_0_stub.vhdl
+-- Design      : system_bd_lmb_bram_0
+-- Purpose     : Stub declaration of top-level module interface
+-- Device      : xc7k410tffg900-2
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity system_bd_lmb_bram_0 is
+  Port ( 
+    clka : in STD_LOGIC;
+    rsta : in STD_LOGIC;
+    ena : in STD_LOGIC;
+    wea : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    addra : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    clkb : in STD_LOGIC;
+    rstb : in STD_LOGIC;
+    enb : in STD_LOGIC;
+    web : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    addrb : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    doutb : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    rsta_busy : out STD_LOGIC;
+    rstb_busy : out STD_LOGIC
+  );
+
+end system_bd_lmb_bram_0;
+
+architecture stub of system_bd_lmb_bram_0 is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "clka,rsta,ena,wea[3:0],addra[31:0],dina[31:0],douta[31:0],clkb,rstb,enb,web[3:0],addrb[31:0],dinb[31:0],doutb[31:0],rsta_busy,rstb_busy";
+attribute x_core_info : string;
+attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_3,Vivado 2019.1.3";
+begin
+end;

projects/dl814_k7/common_ipi-bd/basic_driver_bd/ip/system_bd_mdm_0/system_bd_mdm_0.xdc

@@ -0,0 +1,173 @@
+# file: system_bd_mdm_0.xdc
+# (c) Copyright 2013-2018 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+
+create_clock -period 33.333 [get_pins {Use*.BSCAN*/*/DRCK}]
+create_clock -period 33.333 [get_pins {Use*.BSCAN*/*/UPDATE}]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins "Use*.BSCAN*/*/DRCK"]]
+set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins "Use*.BSCAN*/*/UPDATE"]]
+set_false_path -through [get_pins "Use*.BSCAN*/*/CAPTURE"]
+set_false_path -through [get_pins "Use*.BSCAN*/*/SEL"]
+set_false_path -through [get_pins "Use*.BSCAN*/*/SHIFT"]
+set_false_path -through [get_pins "Use*.BSCAN*/*/TDI"]
+set_clock_groups -logically_exclusive  -group [get_clocks -of_objects [get_pins "Use*.BSCAN*/*/DRCK"]] -group [get_clocks -of_objects [get_pins "Use*.BSCAN*/*/UPDATE"]]
+
+create_waiver -internal -quiet -user mdm -tags 12436 -type CDC -id CDC-10 -description "Debug protocol ensures stable signals" \
+  -from [get_pins -quiet MDM_Core_I1/JTAG_CONTROL_I/Debug_SYS_Rst_i_reg/C] -to *PIN
+
+# Waivers for serial debug interface
+create_waiver -internal -quiet -user mdm -tags 12436 -type CDC -id CDC-1 -description "Debug protocol ensures stable signals" \
+  -from *PIN -to [get_pins -quiet MDM_Core_I1/JTAG_CONTROL_I/Use_Serial_Unified_Completion.completion*reg*/*]
+create_waiver -internal -quiet -user mdm -tags 12436 -type CDC -id CDC-1 -description "Debug protocol ensures stable signals" \
+  -from *PIN -to [get_pins -quiet MDM_Core_I1/JTAG_CONTROL_I/Use_Serial_Unified_Completion.count_reg*/*]
+create_waiver -internal -quiet -user mdm -tags 12436 -type CDC -id CDC-1 -description "Debug protocol ensures stable signals" \
+  -from *PIN -to [get_pins -quiet MDM_Core_I1/JTAG_CONTROL_I/Use_Serial_Unified_Completion.mb_data_overrun_reg/D]
+create_waiver -internal -quiet -user mdm -tags 12436 -type CDC -id CDC-1 -description "Debug protocol ensures stable signals" \
+  -from *PIN -to [get_pins -quiet MDM_Core_I1/JTAG_CONTROL_I/Use_Serial_Unified_Completion.mb_instr_error_reg/D]
+create_waiver -internal -quiet -user mdm -tags 12436 -type CDC -id CDC-1 -description "Debug protocol ensures stable signals" \
+  -from *PIN -to [get_pins -quiet MDM_Core_I1/JTAG_CONTROL_I/Use_Serial_Unified_Completion.mb_instr_overrun_reg/D]
+create_waiver -internal -quiet -user mdm -tags 12436 -type CDC -id CDC-1 -description "Debug protocol ensures stable signals" \
+  -from *PIN -to [get_pins -quiet MDM_Core_I1/JTAG_CONTROL_I/Use_Serial_Unified_Completion.sample*_reg*/*]
+create_waiver -internal -quiet -user mdm -tags 12436 -type CDC -id CDC-1 -description "Debug protocol ensures stable signals" \
+  -from *PIN -to [get_pins -quiet MDM_Core_I1/JTAG_CONTROL_I/Use_Serial_Unified_Completion.clear_overrun_reg*/D]
+create_waiver -internal -quiet -user mdm -tags 12436 -type CDC -id CDC-13 -description "Debug protocol ensures stable signals" \
+  -from [get_pins -quiet MDM_Core_I1/JTAG_CONTROL_I/Use_Serial_Unified_Completion.completion_block_reg/C] -to *PIN
+create_waiver -internal -quiet -user mdm -tags 12436 -type CDC -id CDC-15 -description "Debug protocol ensures stable signals" \
+  -from *PIN -to [get_pins -quiet MDM_Core_I1/JTAG_CONTROL_I/Use_Serial_Unified_Completion.completion*reg*/*]
+create_waiver -internal -quiet -user mdm -tags 12436 -type CDC -id CDC-15 -description "Debug protocol ensures stable signals" \
+  -from *PIN -to [get_pins -quiet MDM_Core_I1/JTAG_CONTROL_I/Use_Serial_Unified_Completion.count_reg*/*]
+
+# Waivers for BSCAN
+create_waiver -internal -quiet -user mdm -tags 12436 -type CDC -id CDC-1 -description "Debug protocol ensures stable signals" \
+  -from *PIN -to [get_pins -quiet MDM_Core_I1/Use_BSCAN.TDI_Shifter_reg\[*\]/CE]
+create_waiver -internal -quiet -user mdm -tags 12436 -type CDC -id CDC-1 -description "Debug protocol ensures stable signals" \
+  -from *PIN -to [get_pins -quiet MDM_Core_I1/JTAG_CONTROL_I/sel_n_reg/*]
+create_waiver -internal -quiet -user mdm -tags 12436 -type CDC -id CDC-1 -description "Debug protocol ensures stable signals" \
+  -from *PIN -to [get_pins -quiet MDM_Core_I1/JTAG_CONTROL_I/shift_Count_reg\[*\]/D]
+create_waiver -internal -quiet -user mdm -tags 12436 -type CDC -id CDC-1 -description "Debug protocol ensures stable signals" \
+  -from *PIN -to [get_pins -quiet MDM_Core_I1/JTAG_CONTROL_I/tdi_shifter_reg\[*\]/*]
+create_waiver -internal -quiet -user mdm -tags 12436 -type CDC -id CDC-1 -description "Debug protocol ensures stable signals" \
+  -from *PIN -to [get_pins -quiet MDM_Core_I1/JTAG_CONTROL_I/command_1_reg\[*\]/CE]
+create_waiver -internal -quiet -user mdm -tags 12436 -type CDC -id CDC-1 -description "Debug protocol ensures stable signals" \
+  -from *PIN -to [get_pins -quiet MDM_Core_I1/JTAG_CONTROL_I/Debug_Rst_i_reg/CE]
+create_waiver -internal -quiet -user mdm -tags 12436 -type CDC -id CDC-1 -description "Debug protocol ensures stable signals" \
+  -from *PIN -to [get_pins -quiet MDM_Core_I1/JTAG_CONTROL_I/Debug_SYS_Rst_i_reg/CE]
+create_waiver -internal -quiet -user mdm -tags 12436 -type CDC -id CDC-1 -description "Debug protocol ensures stable signals" \
+  -from *PIN -to [get_pins -quiet MDM_Core_I1/JTAG_CONTROL_I/Ext_NM_BRK_i_reg/CE]
+create_waiver -internal -quiet -user mdm -tags 12436 -type CDC -id CDC-1 -description "Debug protocol ensures stable signals" \
+  -from *PIN -to [get_pins -quiet MDM_Core_I1/JTAG_CONTROL_I/*Which_MB_Reg_reg\[*\]/CE]
+create_waiver -internal -quiet -user mdm -tags 12436 -type CDC -id CDC-1 -description "Debug protocol ensures stable signals" \
+  -from *PIN -to [get_pins -quiet MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.command_reg\[*\]/CE]
+create_waiver -internal -quiet -user mdm -tags 12436 -type CDC -id CDC-1 -description "Debug protocol ensures stable signals" \
+  -from *PIN -to [get_pins -quiet MDM_Core_I1/JTAG_CONTROL_I/completion_ctrl_reg\[0\]/D]
+create_waiver -internal -quiet -user mdm -tags 12436 -type CDC -id CDC-1 -description "Debug protocol ensures stable signals" \
+  -from [get_pins -quiet MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Using_FPGA.Native/C] -to *PIN
+create_waiver -internal -quiet -user mdm -tags 12436 -type CDC -id CDC-1 -description "Debug protocol ensures stable signals" \
+  -from [get_pins -quiet MDM_Core_I1/JTAG_CONTROL_I/tdi_shifter_reg\[*\]/C] -to *PIN
+create_waiver -internal -quiet -user mdm -tags 12436 -type CDC -id CDC-1 -description "Debug protocol ensures stable signals" \
+  -from *PIN -to [get_pins -quiet MDM_Core_I1/Use_BSCAN.Config_Reg_reg*/D]
+create_waiver -internal -quiet -user mdm -tags 12436 -type CDC -id CDC-1 -description "Debug protocol ensures stable signals" \
+  -from *PIN -to [get_pins -quiet MDM_Core_I1/Use_BSCAN.TDI_Shifter_reg\[*\]/D]
+create_waiver -internal -quiet -user mdm -tags 12436 -type CDC -id CDC-1 -description "Debug protocol ensures stable signals" \
+  -from *PIN -to [get_pins -quiet MDM_Core_I1/JTAG_CONTROL_I/set_Ext_BRK_reg/CE]
+create_waiver -internal -quiet -user mdm -tags 12436 -type CDC -id CDC-2 -description "Debug protocol ensures stable signals" \
+  -from *PIN -to [get_pins -quiet MDM_Core_I1/Use_BSCAN.PORT_Selector*_reg\[*\]/CE]
+create_waiver -internal -quiet -user mdm -tags 12436 -type CDC -id CDC-2 -description "Debug protocol ensures stable signals" \
+  -from *PIN -to [get_pins -quiet MDM_Core_I1/Use_BSCAN.Config_Reg_reg\[*\]/D]
+create_waiver -internal -quiet -user mdm -tags 12436 -type CDC -id CDC-2 -description "Debug protocol ensures stable signals" \
+  -from *PIN -to [get_pins -quiet MDM_Core_I1/Use_BSCAN.Config_Reg_reg*/D]
+create_waiver -internal -quiet -user mdm -tags 12436 -type CDC -id CDC-4 -description "Debug protocol ensures stable signals" \
+  -from *PIN -to [get_pins -quiet MDM_Core_I1/Use_BSCAN.PORT_Selector_reg\[*\]/D]
+create_waiver -internal -quiet -user mdm -tags 12436 -type CDC -id CDC-7 -description "Debug protocol ensures stable signals" \
+  -from *PIN -to [get_pins -quiet MDM_Core_I1/JTAG_CONTROL_I/sel_n_reg/PRE]
+create_waiver -internal -quiet -user mdm -tags 12436 -type CDC -id CDC-7 -description "Debug protocol ensures stable signals" \
+  -from *PIN -to [get_pins -quiet MDM_Core_I1/Use_BSCAN.Config_Reg_reg\[*\]/*]
+create_waiver -internal -quiet -user mdm -tags 12436 -type CDC -id CDC-7 -description "Debug protocol ensures stable signals" \
+  -from *PIN -to [get_pins -quiet MDM_Core_I1/Use_BSCAN.TDI_Shifter_reg\[*\]/*]
+create_waiver -internal -quiet -user mdm -tags 12436 -type CDC -id CDC-7 -description "Debug protocol ensures stable signals" \
+  -from *PIN -to [get_pins -quiet MDM_Core_I1/Use_BSCAN.FDC_I/*/*]
+create_waiver -internal -quiet -user mdm -tags 12436 -type CDC -id CDC-7 -description "Debug protocol ensures stable signals" \
+  -from [get_pins -quiet MDM_Core_I1/JTAG_CONTROL_I/sel_n_reg/C] -to *PIN
+create_waiver -internal -quiet -user mdm -tags 12436 -type CDC -id CDC-8 -description "Debug protocol ensures stable signals" \
+  -from *PIN -to [get_pins -quiet MDM_Core_I1/Use_BSCAN.Config_Reg_reg*/CLR]
+create_waiver -internal -quiet -user mdm -tags 12436 -type CDC -id CDC-10 -description "Debug protocol ensures stable signals" \
+  -from *PIN -to [get_pins -quiet MDM_Core_I1/Use_BSCAN.PORT_Selector*_reg\[*\]/*]
+create_waiver -internal -quiet -user mdm -tags 12436 -type CDC -id CDC-10 -description "Debug protocol ensures stable signals" \
+  -from *PIN -to [get_pins -quiet MDM_Core_I1/Use_BSCAN.Config_Reg_reg*/D]
+create_waiver -internal -quiet -user mdm -tags 12436 -type CDC -id CDC-10 -description "Debug protocol ensures stable signals" \
+  -from *PIN -to [get_pins -quiet MDM_Core_I1/Use_BSCAN.Config_Reg_reg*/CLR]
+create_waiver -internal -quiet -user mdm -tags 12436 -type CDC -id CDC-11 -description "Debug protocol ensures stable signals" \
+  -from *PIN -to [get_pins -quiet MDM_Core_I1/Use_BSCAN.Config_Reg_reg*/*]
+create_waiver -internal -quiet -user mdm -tags 12436 -type CDC -id CDC-11 -description "Debug protocol ensures stable signals" \
+  -from *PIN -to [get_pins -quiet MDM_Core_I1/Use_BSCAN.PORT_Selector*_reg\[*\]/*]
+create_waiver -internal -quiet -user mdm -tags 12436 -type CDC -id CDC-13 -description "Debug protocol ensures stable signals" \
+  -from *PIN -to [get_pins -quiet Use_E2.BSCAN_I/Use_E2.BSCANE2_I/TDO]
+create_waiver -internal -quiet -user mdm -tags 12436 -type CDC -id CDC-13 -description "Debug protocol ensures stable signals" \
+  -from [get_pins -quiet Use_E2.BSCAN_I/Use_E2.BSCANE2_I/INTERNAL_TDI] -to *PIN
+create_waiver -internal -quiet -user mdm -tags 12436 -type CDC -id CDC-13 -description "Debug protocol ensures stable signals" \
+  -from *PIN -to [get_pins -quiet MDM_Core_I1/Use_BSCAN.Config_Reg_reg*/D]
+create_waiver -internal -quiet -user mdm -tags 12436 -type CDC -id CDC-13 -description "Debug protocol ensures stable signals" \
+  -from [get_pins -quiet MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Using_FPGA.Native/C] -to *PIN
+create_waiver -internal -quiet -user mdm -tags 12436 -type CDC -id CDC-13 -description "Debug protocol ensures stable signals" \
+  -from [get_pins -quiet MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.command_reg\[*\]/C] -to *PIN
+create_waiver -internal -quiet -user mdm -tags 12436 -type CDC -id CDC-15 -description "Debug protocol ensures stable signals" \
+  -from *PIN -to [get_pins -quiet MDM_Core_I1/JTAG_CONTROL_I/command_1_reg\[*\]/D]
+create_waiver -internal -quiet -user mdm -tags 12436 -type CDC -id CDC-15 -description "Debug protocol ensures stable signals" \
+  -from *PIN -to [get_pins -quiet MDM_Core_I1/JTAG_CONTROL_I/Debug_Rst_i_reg/D]
+create_waiver -internal -quiet -user mdm -tags 12436 -type CDC -id CDC-15 -description "Debug protocol ensures stable signals" \
+  -from *PIN -to [get_pins -quiet MDM_Core_I1/JTAG_CONTROL_I/Debug_SYS_Rst_i_reg/D]
+create_waiver -internal -quiet -user mdm -tags 12436 -type CDC -id CDC-15 -description "Debug protocol ensures stable signals" \
+  -from *PIN -to [get_pins -quiet MDM_Core_I1/JTAG_CONTROL_I/Ext_NM_BRK_i_reg/D]
+create_waiver -internal -quiet -user mdm -tags 12436 -type CDC -id CDC-15 -description "Debug protocol ensures stable signals" \
+  -from *PIN -to [get_pins -quiet MDM_Core_I1/JTAG_CONTROL_I/*Which_MB_Reg_reg\[*\]/D]
+create_waiver -internal -quiet -user mdm -tags 12436 -type CDC -id CDC-15 -description "Debug protocol ensures stable signals" \
+  -from [get_pins -quiet MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.FDC_I/Using_FPGA.Native/C] -to *PIN
+create_waiver -internal -quiet -user mdm -tags 12436 -type CDC -id CDC-15 -description "Debug protocol ensures stable signals" \
+  -from *PIN -to [get_pins -quiet MDM_Core_I1/Use_BSCAN.PORT_Selector*_reg\[*\]/*]
+create_waiver -internal -quiet -user mdm -tags 12436 -type CDC -id CDC-15 -description "Debug protocol ensures stable signals" \
+  -from *PIN -to [get_pins -quiet MDM_Core_I1/JTAG_CONTROL_I/set_Ext_BRK_reg/D]
+create_waiver -internal -quiet -user mdm -tags 12436 -type CDC -id CDC-15 -description "Debug protocol ensures stable signals" \
+  -from *PIN -to [get_pins -quiet MDM_Core_I1/JTAG_CONTROL_I/Use_BSCAN.command_reg\[*\]/D]

projects/dl814_k7/common_ipi-bd/basic_driver_bd/ip/system_bd_mdm_0/system_bd_mdm_0_ooc_trace.xdc

@@ -0,0 +1,6 @@
+# This constraints file contains default clock frequencies to be used during 
+# out-of-context flows such as OOC Synthesis and Hierarchical Designs. For 
+# best results the frequencies should be modified to match the target 
+# frequencies. This constraints file is not used in normal top-down 
+# synthesis (the default flow of Vivado)
+

projects/dl814_k7/common_ipi-bd/basic_driver_bd/ip/system_bd_mdm_0/system_bd_mdm_0_stub.v

@@ -0,0 +1,30 @@
+// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep  4 09:45:24 MDT 2019
+// Date        : Sat Mar 18 23:57:15 2023
+// Host        : JOSH-ASUS-Z690 running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode synth_stub -rename_top system_bd_mdm_0 -prefix
+//               system_bd_mdm_0_ system_bd_mdm_0_stub.v
+// Design      : system_bd_mdm_0
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7k410tffg900-2
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* x_core_info = "MDM,Vivado 2019.1.3" *)
+module system_bd_mdm_0(Debug_SYS_Rst, Dbg_Clk_0, Dbg_TDI_0, Dbg_TDO_0, 
+  Dbg_Reg_En_0, Dbg_Capture_0, Dbg_Shift_0, Dbg_Update_0, Dbg_Rst_0, Dbg_Disable_0)
+/* synthesis syn_black_box black_box_pad_pin="Debug_SYS_Rst,Dbg_Clk_0,Dbg_TDI_0,Dbg_TDO_0,Dbg_Reg_En_0[0:7],Dbg_Capture_0,Dbg_Shift_0,Dbg_Update_0,Dbg_Rst_0,Dbg_Disable_0" */;
+  output Debug_SYS_Rst;
+  output Dbg_Clk_0;
+  output Dbg_TDI_0;
+  input Dbg_TDO_0;
+  output [0:7]Dbg_Reg_En_0;
+  output Dbg_Capture_0;
+  output Dbg_Shift_0;
+  output Dbg_Update_0;
+  output Dbg_Rst_0;
+  output Dbg_Disable_0;
+endmodule

projects/dl814_k7/common_ipi-bd/basic_driver_bd/ip/system_bd_mdm_0/system_bd_mdm_0_stub.vhdl

@@ -0,0 +1,39 @@
+-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep  4 09:45:24 MDT 2019
+-- Date        : Sat Mar 18 23:57:15 2023
+-- Host        : JOSH-ASUS-Z690 running 64-bit major release  (build 9200)
+-- Command     : write_vhdl -force -mode synth_stub -rename_top system_bd_mdm_0 -prefix
+--               system_bd_mdm_0_ system_bd_mdm_0_stub.vhdl
+-- Design      : system_bd_mdm_0
+-- Purpose     : Stub declaration of top-level module interface
+-- Device      : xc7k410tffg900-2
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity system_bd_mdm_0 is
+  Port ( 
+    Debug_SYS_Rst : out STD_LOGIC;
+    Dbg_Clk_0 : out STD_LOGIC;
+    Dbg_TDI_0 : out STD_LOGIC;
+    Dbg_TDO_0 : in STD_LOGIC;
+    Dbg_Reg_En_0 : out STD_LOGIC_VECTOR ( 0 to 7 );
+    Dbg_Capture_0 : out STD_LOGIC;
+    Dbg_Shift_0 : out STD_LOGIC;
+    Dbg_Update_0 : out STD_LOGIC;
+    Dbg_Rst_0 : out STD_LOGIC;
+    Dbg_Disable_0 : out STD_LOGIC
+  );
+
+end system_bd_mdm_0;
+
+architecture stub of system_bd_mdm_0 is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "Debug_SYS_Rst,Dbg_Clk_0,Dbg_TDI_0,Dbg_TDO_0,Dbg_Reg_En_0[0:7],Dbg_Capture_0,Dbg_Shift_0,Dbg_Update_0,Dbg_Rst_0,Dbg_Disable_0";
+attribute x_core_info : string;
+attribute x_core_info of stub : architecture is "MDM,Vivado 2019.1.3";
+begin
+end;