Archived
first commit after restructuring
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################################################################################
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########################### Single Project Specific ############################
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################################################################################
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# ------------------------------------------------------------------------------
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# ------------------------------ Vivado Specific -------------------------------
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# ------------------------------------------------------------------------------
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# exclude everything in project directory
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project/**
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# include hardware manager projects and sources
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# 1. include `.hw` directory
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# 2. include everything in `.hw` directory
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!project/*.hw/
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!project/*.hw/**
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# include design run results
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# 1. include `*.runs` directory
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# 2. exclude everything in `.runs` directory
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# 3. include `.impl_*` directory
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# 4. include `*.bit` file in `.impl_*` directory
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# 5. include `*.ltx` file in `.impl_*` directory
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!/project/*.runs/
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/project/*.runs/**
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!/project/*.runs/impl_*/
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!/project/*.runs/impl_*/*.bit
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!/project/*.runs/impl_*/*.ltx
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# ------------------------------------------------------------------------------
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# -------------------------------- SDK Specific --------------------------------
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# ------------------------------------------------------------------------------
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# include sdk directory and everything in it
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!/project/*.sdk/
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!/project/*.sdk/**
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/project/*.sdk/**.log
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||||
# exclude some obscure hidden SDK folders
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||||
/project/*.sdk/.metadata/
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/project/*.sdk/.sdk/
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/project/*.sdk/RemoteSystemsTempFiles/
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/project/*.sdk/webtalk/
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# hw_platform: exclude the entire hw_platform folder, as everything can be
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||||
# generated from the .hdf file. Make sure to include the bitstream in the .hdf
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# file when exporting from Vivado!
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||||
/project/*.sdk/*_hw_platform_*/
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||||
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# BSP: only keep `.cproject`, `.project`, `.sdkproject`, `.system.mss` and
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# Makefile, ps lib files are regenerated automatically
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/project/*.sdk/*_bsp/*
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!/project/*.sdk/*_bsp/*.cproject
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||||
!/project/*.sdk/*_bsp/*.project
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||||
!/project/*.sdk/*_bsp/*.sdkproject
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||||
!/project/*.sdk/*_bsp/system.mss
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||||
!/project/*.sdk/*_bsp/Makefile
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||||
|
||||
# Application: ignored file patterns, exclude Debug & Release folders
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/project/*.sdk/**/*.o
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/project/*.sdk/**/*.d
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/project/*.sdk/**/*.a
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/project/*.sdk/*/Debug/
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/project/*.sdk/*/Release/
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||||
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||||
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||||
################################################################################
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||||
# ############################ Multi Project Specific ############################
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||||
# ################################################################################
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||||
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||||
# # ------------------------------------------------------------------------------
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||||
# # ------------------------------ Vivado Specific -------------------------------
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||||
# # ------------------------------------------------------------------------------
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||||
|
||||
# # exclude everything in project directory expect for top level directory
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||||
# project/**
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||||
# !/project/*/
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||||
|
||||
# # include hardware manager projects and sources
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||||
# # 1. include `.hw` directory
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||||
# # 2. include everything in `.hw` directory
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||||
# !project/*/*.hw/
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# !project/*/*.hw/**
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||||
|
||||
# # include design run results
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||||
# # 1. include `*.runs` directory
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||||
# # 2. exclude everything in `.runs` directory
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||||
# # 3. include `.impl_*` directory
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||||
# # 4. include `*.bit` file in `.impl_*` directory
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# # 5. include `*.ltx` file in `.impl_*` directory
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||||
# !/project/*/*.runs/
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# /project/*/*.runs/**
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# !/project/*/*.runs/impl_*/
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# !/project/*/*.runs/impl_*/*.bit
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# !/project/*/*.runs/impl_*/*.ltx
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||||
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||||
# # ------------------------------------------------------------------------------
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||||
# # -------------------------------- SDK Specific --------------------------------
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||||
# # ------------------------------------------------------------------------------
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||||
|
||||
# # include sdk directory and everything in it
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||||
# !/project/*/*.sdk/
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||||
# !/project/*/*.sdk/**
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||||
# /project/*/*.sdk/**.log
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||||
|
||||
# # exclude some obscure hidden SDK folders
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||||
# /project/*/*.sdk/.metadata/
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# /project/*/*.sdk/.sdk/
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||||
# /project/*/*.sdk/RemoteSystemsTempFiles/
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||||
# /project/*/*.sdk/webtalk/
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||||
|
||||
# # hw_platform: exclude the entire hw_platform folder, as everything can be
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||||
# # generated from the .hdf file. Make sure to include the bitstream in the .hdf
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||||
# # file when exporting from Vivado!
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||||
# /project/*/*.sdk/*_hw_platform_*/
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||||
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||||
# # BSP: only keep `.cproject`, `.project`, `.sdkproject`, `.system.mss` and
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||||
# # Makefile, ps lib files are regenerated automatically
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||||
# /project/*/*.sdk/*_bsp/*
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# !/project/*/*.sdk/*_bsp/*.cproject
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# !/project/*/*.sdk/*_bsp/*.project
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# !/project/*/*.sdk/*_bsp/*.sdkproject
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# !/project/*/*.sdk/*_bsp/system.mss
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||||
# !/project/*/*.sdk/*_bsp/Makefile
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||||
|
||||
# # Application: ignored file patterns, exclude Debug & Release folders
|
||||
# /project/*/*.sdk/**/*.o
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||||
# /project/*/*.sdk/**/*.d
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||||
# /project/*/*.sdk/**/*.a
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# /project/*/*.sdk/*/Debug/
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# /project/*/*.sdk/*/Release/
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@@ -0,0 +1,220 @@
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# smq7k410t_b9361
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## Timing Assertions Section
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## Physical Constraints Section
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# Clocks
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set_property -dict {PACKAGE_PIN L25 IOSTANDARD LVCMOS33} [get_ports clk_25m ] ;# CLK_25M
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set_property -dict {PACKAGE_PIN F20 IOSTANDARD LVDS_25 } [get_ports clk_250m_p ] ;# CLK_250M_P
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set_property -dict {PACKAGE_PIN D26 IOSTANDARD LVCMOS18} [get_ports ad9361_1_buffer_clk ] ;# B9361_1_CLK_OUT
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set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS18} [get_ports ad9361_2_buffer_clk ] ;# B9361_2_CLK_OUT
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# HMC7044-1 Interface
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set_property -dict {PACKAGE_PIN J23 IOSTANDARD LVCMOS33} [get_ports ad9516_spi_clk ] ;# GM4526C_SPI_SCLK
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set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS33} [get_ports ad9516_spi_csn ] ;# GM4526C_SPI_CSB
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set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVCMOS33} [get_ports ad9516_spi_mosi ] ;# GM4526C_SPI_SDIO
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set_property -dict {PACKAGE_PIN K23 IOSTANDARD LVCMOS33} [get_ports ad9516_spi_miso ] ;# GM4526C_SPI_SDO
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set_property -dict {PACKAGE_PIN L23 IOSTANDARD LVCMOS33} [get_ports ad9516_refmon ] ;# GM4526C_REFMON
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set_property -dict {PACKAGE_PIN K24 IOSTANDARD LVCMOS33} [get_ports ad9516_ld ] ;# GM4526C_LD
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set_property -dict {PACKAGE_PIN J24 IOSTANDARD LVCMOS33} [get_ports ad9516_status ] ;# GM4526C_STATUS
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set_property -dict {PACKAGE_PIN K21 IOSTANDARD LVCMOS33} [get_ports ad9516_pd_b ] ;# GM4526C_PDB
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set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS33} [get_ports ad9516_reset_b ] ;# GM4526C_RESETB
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set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVCMOS33} [get_ports ad9516_sync_b ] ;# GM4526C_SYNCB
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# AD9361-1 Interface
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set_property -dict {PACKAGE_PIN D27 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data_clk ] ;# B9361_1_DATA_CLK
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set_property -dict {PACKAGE_PIN B27 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_frame ] ;# B9361_1_RX_FRAME
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set_property -dict {PACKAGE_PIN A23 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[0] ] ;# B9361_1_P0_00_TX0_N
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set_property -dict {PACKAGE_PIN B23 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[1] ] ;# B9361_1_P0_01_TX0_P
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set_property -dict {PACKAGE_PIN D23 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[2] ] ;# B9361_1_P0_02_TX1_N
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set_property -dict {PACKAGE_PIN E23 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[3] ] ;# B9361_1_P0_03_TX1_P
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set_property -dict {PACKAGE_PIN D24 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[4] ] ;# B9361_1_P0_04_TX2_N
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set_property -dict {PACKAGE_PIN E24 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[5] ] ;# B9361_1_P0_05_TX2_P
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set_property -dict {PACKAGE_PIN E25 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[6] ] ;# B9361_1_P0_06_TX3_N
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set_property -dict {PACKAGE_PIN F25 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[7] ] ;# B9361_1_P0_07_TX3_P
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set_property -dict {PACKAGE_PIN E26 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[8] ] ;# B9361_1_P0_08_TX4_N
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set_property -dict {PACKAGE_PIN F26 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[9] ] ;# B9361_1_P0_09_TX4_P
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set_property -dict {PACKAGE_PIN G24 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[10] ] ;# B9361_1_P0_10_TX5_N
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set_property -dict {PACKAGE_PIN G23 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[11] ] ;# B9361_1_P0_11_TX5_P
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set_property -dict {PACKAGE_PIN E28 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_fb_clk ] ;# B9361_1_FB_CLK
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set_property -dict {PACKAGE_PIN G27 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_frame ] ;# B9361_1_TX_FRAME
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set_property -dict {PACKAGE_PIN E30 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[0] ] ;# B9361_1_P1_00_RX0_N
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set_property -dict {PACKAGE_PIN E29 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[1] ] ;# B9361_1_P1_01_RX0_P
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set_property -dict {PACKAGE_PIN C30 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[2] ] ;# B9361_1_P1_02_RX1_N
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set_property -dict {PACKAGE_PIN D29 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[3] ] ;# B9361_1_P1_03_RX1_P
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set_property -dict {PACKAGE_PIN A30 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[4] ] ;# B9361_1_P1_04_RX2_N
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set_property -dict {PACKAGE_PIN B30 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[5] ] ;# B9361_1_P1_05_RX2_P
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set_property -dict {PACKAGE_PIN B29 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[6] ] ;# B9361_1_P1_06_RX3_N
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set_property -dict {PACKAGE_PIN C29 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[7] ] ;# B9361_1_P1_07_RX3_P
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set_property -dict {PACKAGE_PIN F28 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[8] ] ;# B9361_1_P1_08_RX4_N
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set_property -dict {PACKAGE_PIN G28 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[9] ] ;# B9361_1_P1_09_RX4_P
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set_property -dict {PACKAGE_PIN H25 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[10] ] ;# B9361_1_P1_10_RX5_N
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set_property -dict {PACKAGE_PIN H24 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[11] ] ;# B9361_1_P1_11_RX5_P
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set_property -dict {PACKAGE_PIN H20 IOSTANDARD LVCMOS18} [get_ports ad9361_1_spi_clk ] ;# B9361_1_SPI_CLK
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set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS18} [get_ports ad9361_1_spi_csn ] ;# B9361_1_SPI_ENB
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set_property -dict {PACKAGE_PIN G20 IOSTANDARD LVCMOS18} [get_ports ad9361_1_spi_mosi ] ;# B9361_1_SPI_DI
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set_property -dict {PACKAGE_PIN G19 IOSTANDARD LVCMOS18} [get_ports ad9361_1_spi_miso ] ;# B9361_1_SPI_DO
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set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS18} [get_ports ad9361_1_reset_b ] ;# B9361_1_RESETB
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set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVCMOS18} [get_ports ad9361_1_en_agc ] ;# B9361_1_EN_AGC
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set_property -dict {PACKAGE_PIN H17 IOSTANDARD LVCMOS18} [get_ports ad9361_1_enable ] ;# B9361_1_ENABLE
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set_property -dict {PACKAGE_PIN A27 IOSTANDARD LVCMOS18} [get_ports ad9361_1_txnrx ] ;# B9361_1_TXNRX
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set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_in[0] ] ;# B9361_1_CTRL_IN0
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set_property -dict {PACKAGE_PIN H19 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_in[1] ] ;# B9361_1_CTRL_IN1
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set_property -dict {PACKAGE_PIN J19 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_in[2] ] ;# B9361_1_CTRL_IN2
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set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_in[3] ] ;# B9361_1_CTRL_IN3
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set_property -dict {PACKAGE_PIN H21 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[0] ] ;# B9361_1_CTRL_OUT0
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set_property -dict {PACKAGE_PIN K20 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[1] ] ;# B9361_1_CTRL_OUT1
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set_property -dict {PACKAGE_PIN H22 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[2] ] ;# B9361_1_CTRL_OUT2
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set_property -dict {PACKAGE_PIN G22 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[3] ] ;# B9361_1_CTRL_OUT3
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set_property -dict {PACKAGE_PIN C21 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[4] ] ;# B9361_1_CTRL_OUT4
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set_property -dict {PACKAGE_PIN F22 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[5] ] ;# B9361_1_CTRL_OUT5
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set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[6] ] ;# B9361_1_CTRL_OUT6
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set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[7] ] ;# B9361_1_CTRL_OUT7
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set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVCMOS18} [get_ports ad9361_sync ] ;# B9361_SYNC
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# AD9361-2 Interface
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set_property -dict {PACKAGE_PIN D12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data_clk ] ;# B9361_2_DATA_CLK
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set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_frame ] ;# B9361_2_RX_FRAME
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set_property -dict {PACKAGE_PIN L13 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[0] ] ;# B9361_2_P0_00_TX0_N
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set_property -dict {PACKAGE_PIN L12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[1] ] ;# B9361_2_P0_01_TX0_P
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set_property -dict {PACKAGE_PIN K11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[2] ] ;# B9361_2_P0_02_TX1_N
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set_property -dict {PACKAGE_PIN L11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[3] ] ;# B9361_2_P0_03_TX1_P
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||||
set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[4] ] ;# B9361_2_P0_04_TX2_N
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||||
set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[5] ] ;# B9361_2_P0_05_TX2_P
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||||
set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[6] ] ;# B9361_2_P0_06_TX3_N
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||||
set_property -dict {PACKAGE_PIN K14 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[7] ] ;# B9361_2_P0_07_TX3_P
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||||
set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[8] ] ;# B9361_2_P0_08_TX4_N
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||||
set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[9] ] ;# B9361_2_P0_09_TX4_P
|
||||
set_property -dict {PACKAGE_PIN K16 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[10] ] ;# B9361_2_P0_10_TX5_N
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||||
set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[11] ] ;# B9361_2_P0_11_TX5_P
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||||
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||||
set_property -dict {PACKAGE_PIN F12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_fb_clk ] ;# B9361_2_FB_CLK
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||||
set_property -dict {PACKAGE_PIN D14 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_frame ] ;# B9361_2_TX_FRAME
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||||
set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[0] ] ;# B9361_2_P1_00_RX0_N
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||||
set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[1] ] ;# B9361_2_P1_01_RX0_P
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||||
set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[2] ] ;# B9361_2_P1_02_RX1_N
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||||
set_property -dict {PACKAGE_PIN E14 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[3] ] ;# B9361_2_P1_03_RX1_P
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||||
set_property -dict {PACKAGE_PIN B12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[4] ] ;# B9361_2_P1_04_RX2_N
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||||
set_property -dict {PACKAGE_PIN C12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[5] ] ;# B9361_2_P1_05_RX2_P
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||||
set_property -dict {PACKAGE_PIN A12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[6] ] ;# B9361_2_P1_06_RX3_N
|
||||
set_property -dict {PACKAGE_PIN A11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[7] ] ;# B9361_2_P1_07_RX3_P
|
||||
set_property -dict {PACKAGE_PIN C11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[8] ] ;# B9361_2_P1_08_RX4_N
|
||||
set_property -dict {PACKAGE_PIN D11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[9] ] ;# B9361_2_P1_09_RX4_P
|
||||
set_property -dict {PACKAGE_PIN E11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[10] ] ;# B9361_2_P1_10_RX5_N
|
||||
set_property -dict {PACKAGE_PIN F11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[11] ] ;# B9361_2_P1_11_RX5_P
|
||||
|
||||
set_property -dict {PACKAGE_PIN C16 IOSTANDARD LVCMOS18} [get_ports ad9361_2_spi_clk ] ;# B9361_2_SPI_CLK
|
||||
set_property -dict {PACKAGE_PIN D16 IOSTANDARD LVCMOS18} [get_ports ad9361_2_spi_csn ] ;# B9361_2_SPI_ENB
|
||||
set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS18} [get_ports ad9361_2_spi_mosi ] ;# B9361_2_SPI_DI
|
||||
set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS18} [get_ports ad9361_2_spi_miso ] ;# B9361_2_SPI_DO
|
||||
|
||||
set_property -dict {PACKAGE_PIN G18 IOSTANDARD LVCMOS18} [get_ports ad9361_2_reset_b ] ;# B9361_2_RESETB
|
||||
set_property -dict {PACKAGE_PIN D19 IOSTANDARD LVCMOS18} [get_ports ad9361_2_en_agc ] ;# B9361_2_EN_AGC
|
||||
set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS18} [get_ports ad9361_2_enable ] ;# B9361_2_ENABLE
|
||||
set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS18} [get_ports ad9361_2_txnrx ] ;# B9361_2_TXNRX
|
||||
|
||||
set_property -dict {PACKAGE_PIN C20 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_in[0] ] ;# B9361_2_CTRL_IN0
|
||||
set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_in[1] ] ;# B9361_2_CTRL_IN1
|
||||
set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_in[2] ] ;# B9361_2_CTRL_IN2
|
||||
set_property -dict {PACKAGE_PIN F17 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_in[3] ] ;# B9361_2_CTRL_IN3
|
||||
|
||||
set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[0] ] ;# B9361_2_CTRL_OUT0
|
||||
set_property -dict {PACKAGE_PIN A20 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[1] ] ;# B9361_2_CTRL_OUT1
|
||||
set_property -dict {PACKAGE_PIN B18 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[2] ] ;# B9361_2_CTRL_OUT2
|
||||
set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[3] ] ;# B9361_2_CTRL_OUT3
|
||||
set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[4] ] ;# B9361_2_CTRL_OUT4
|
||||
set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[5] ] ;# B9361_2_CTRL_OUT5
|
||||
set_property -dict {PACKAGE_PIN A21 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[6] ] ;# B9361_2_CTRL_OUT6
|
||||
set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[7] ] ;# B9361_2_CTRL_OUT7
|
||||
|
||||
# Phased-Array Control
|
||||
set_property -dict {PACKAGE_PIN T26 IOSTANDARD LVTTL } [get_ports ant_cin ] ;# ANT_CIN0
|
||||
set_property -dict {PACKAGE_PIN T25 IOSTANDARD LVTTL } [get_ports ant_din0 ] ;# ANT_DIN0
|
||||
set_property -dict {PACKAGE_PIN U25 IOSTANDARD LVTTL } [get_ports ant_din1 ] ;# ANT_DIN1
|
||||
set_property -dict {PACKAGE_PIN U27 IOSTANDARD LVTTL } [get_ports ant_cout ] ;# ANT_COUT0
|
||||
set_property -dict {PACKAGE_PIN U29 IOSTANDARD LVTTL } [get_ports ant_dout0 ] ;# ANT_DOUT0
|
||||
set_property -dict {PACKAGE_PIN U30 IOSTANDARD LVTTL } [get_ports ant_dout1 ] ;# ANT_DOUT1
|
||||
set_property -dict {PACKAGE_PIN V26 IOSTANDARD LVTTL } [get_ports ant_tr ] ;# ANT_TR_IN
|
||||
set_property -dict {PACKAGE_PIN V27 IOSTANDARD LVTTL } [get_ports ant_dary ] ;# ANT_DARY_IN
|
||||
|
||||
# RF Synthesizer Control
|
||||
set_property -dict {PACKAGE_PIN AK29 IOSTANDARD LVTTL } [get_ports rf_standby ] ;# RF_STANDBY
|
||||
set_property -dict {PACKAGE_PIN AJ28 IOSTANDARD LVTTL } [get_ports rf_sw_pll ] ;# RF_SW_PLL
|
||||
set_property -dict {PACKAGE_PIN AK30 IOSTANDARD LVTTL } [get_ports rf_t ] ;# RF_T
|
||||
set_property -dict {PACKAGE_PIN AG29 IOSTANDARD LVTTL } [get_ports rf_r ] ;# RF_R
|
||||
set_property -dict {PACKAGE_PIN AB25 IOSTANDARD LVTTL } [get_ports rf_sw_bpf ] ;# RF_SW_BPF
|
||||
set_property -dict {PACKAGE_PIN AE28 IOSTANDARD LVTTL } [get_ports rf_sclk1 ] ;# RF_SCLK1
|
||||
set_property -dict {PACKAGE_PIN AA26 IOSTANDARD LVTTL } [get_ports rf_sdio1 ] ;# RF_SDIO1
|
||||
set_property -dict {PACKAGE_PIN AE30 IOSTANDARD LVTTL } [get_ports rf_cs1 ] ;# RF_CS1
|
||||
set_property -dict {PACKAGE_PIN AH29 IOSTANDARD LVTTL } [get_ports rf_ld1 ] ;# RF_LD1
|
||||
set_property -dict {PACKAGE_PIN AD28 IOSTANDARD LVTTL } [get_ports rf_sclk2 ] ;# RF_SCLK2
|
||||
set_property -dict {PACKAGE_PIN AD27 IOSTANDARD LVTTL } [get_ports rf_sdio2 ] ;# RF_SDIO2
|
||||
set_property -dict {PACKAGE_PIN AB27 IOSTANDARD LVTTL } [get_ports rf_cs2 ] ;# RF_CS2
|
||||
set_property -dict {PACKAGE_PIN AC27 IOSTANDARD LVTTL } [get_ports rf_ld2 ] ;# RF_LD2
|
||||
set_property -dict {PACKAGE_PIN AC30 IOSTANDARD LVTTL } [get_ports rf_sclk3 ] ;# RF_SCLK3
|
||||
set_property -dict {PACKAGE_PIN AE29 IOSTANDARD LVTTL } [get_ports rf_sdio3 ] ;# RF_SDIO3
|
||||
set_property -dict {PACKAGE_PIN AB28 IOSTANDARD LVTTL } [get_ports rf_cs3 ] ;# RF_CS3
|
||||
set_property -dict {PACKAGE_PIN AD29 IOSTANDARD LVTTL } [get_ports rf_ld3 ] ;# RF_LD3
|
||||
set_property -dict {PACKAGE_PIN AB30 IOSTANDARD LVTTL } [get_ports rf_tmgc_16 ] ;# RF_TMGC_16
|
||||
set_property -dict {PACKAGE_PIN AC29 IOSTANDARD LVTTL } [get_ports rf_tmgc_8 ] ;# RF_TMGC_8
|
||||
set_property -dict {PACKAGE_PIN AA27 IOSTANDARD LVTTL } [get_ports rf_tmgc_4 ] ;# RF_TMGC_4
|
||||
set_property -dict {PACKAGE_PIN AB29 IOSTANDARD LVTTL } [get_ports rf_tmgc_2 ] ;# RF_TMGC_2
|
||||
set_property -dict {PACKAGE_PIN AA30 IOSTANDARD LVTTL } [get_ports rf_tmgc_1 ] ;# RF_TMGC_1
|
||||
set_property -dict {PACKAGE_PIN AA28 IOSTANDARD LVTTL } [get_ports rf_rmgc_16 ] ;# RF_RMGC_16
|
||||
set_property -dict {PACKAGE_PIN Y28 IOSTANDARD LVTTL } [get_ports rf_rmgc_8 ] ;# RF_RMGC_8
|
||||
set_property -dict {PACKAGE_PIN Y29 IOSTANDARD LVTTL } [get_ports rf_rmgc_4 ] ;# RF_RMGC_4
|
||||
set_property -dict {PACKAGE_PIN Y30 IOSTANDARD LVTTL } [get_ports rf_rmgc_2 ] ;# RF_RMGC_2
|
||||
set_property -dict {PACKAGE_PIN Y26 IOSTANDARD LVTTL } [get_ports rf_rmgc_1 ] ;# RF_RMGC_1
|
||||
set_property -dict {PACKAGE_PIN W28 IOSTANDARD LVTTL } [get_ports rf_enable ] ;# RF_ENABLE
|
||||
set_property -dict {PACKAGE_PIN AA25 IOSTANDARD LVTTL } [get_ports rf_sc ] ;# RF_SC
|
||||
set_property -dict {PACKAGE_PIN W29 IOSTANDARD LVTTL } [get_ports rf_sd ] ;# RF_SD
|
||||
set_property -dict {PACKAGE_PIN Y25 IOSTANDARD LVTTL } [get_ports rf_endsyn ] ;# RF_END_SYN
|
||||
set_property -dict {PACKAGE_PIN W27 IOSTANDARD LVTTL } [get_ports rf_sdout ] ;# RF_SDOUT
|
||||
set_property -dict {PACKAGE_PIN AF28 IOSTANDARD LVTTL } [get_ports rf_dq_wd ] ;# RF_DQ_WD
|
||||
set_property -dict {PACKAGE_PIN AF30 IOSTANDARD LVTTL } [get_ports rf_sw_rx ] ;# RF_SW_RX
|
||||
|
||||
# LVDS for Time Synchronization
|
||||
set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVCMOS33} [get_ports lvds_in_1 ] ;# LVDS_IN1
|
||||
set_property -dict {PACKAGE_PIN L20 IOSTANDARD LVCMOS33} [get_ports lvds_out_1 ] ;# LVDS_OUT1
|
||||
|
||||
set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS33} [get_ports lvds_in_2 ] ;# LVDS_IN2
|
||||
set_property -dict {PACKAGE_PIN J29 IOSTANDARD LVCMOS33} [get_ports lvds_out_2 ] ;# LVDS_OUT2
|
||||
|
||||
# Debug IO
|
||||
set_property -dict {PACKAGE_PIN U22 IOSTANDARD LVCMOS33} [get_ports uart1_txd ] ;# UART_1_TXD
|
||||
set_property -dict {PACKAGE_PIN V19 IOSTANDARD LVCMOS33} [get_ports uart1_rxd ] ;# UART_1_RXD
|
||||
set_property -dict {PACKAGE_PIN U23 IOSTANDARD LVCMOS33} [get_ports uart2_txd ] ;# UART_2_TXD
|
||||
set_property -dict {PACKAGE_PIN V20 IOSTANDARD LVCMOS33} [get_ports uart2_rxd ] ;# UART_2_RXD
|
||||
set_property -dict {PACKAGE_PIN U24 IOSTANDARD LVCMOS33} [get_ports uart3_txd ] ;# UART_3_TXD
|
||||
set_property -dict {PACKAGE_PIN V21 IOSTANDARD LVCMOS33} [get_ports uart3_rxd ] ;# UART_3_RXD
|
||||
|
||||
set_property -dict {PACKAGE_PIN V25 IOSTANDARD LVCMOS33} [get_ports debug_io_1 ] ;# DEBUG_IO_1
|
||||
set_property -dict {PACKAGE_PIN W21 IOSTANDARD LVCMOS33} [get_ports debug_io_2 ] ;# DEBUG_IO_2
|
||||
set_property -dict {PACKAGE_PIN W26 IOSTANDARD LVCMOS33} [get_ports debug_io_3 ] ;# DEBUG_IO_3
|
||||
set_property -dict {PACKAGE_PIN V22 IOSTANDARD LVCMOS33} [get_ports debug_io_4 ] ;# DEBUG_IO_4
|
||||
set_property -dict {PACKAGE_PIN V24 IOSTANDARD LVCMOS33} [get_ports debug_io_5 ] ;# DEBUG_IO_5
|
||||
set_property -dict {PACKAGE_PIN W22 IOSTANDARD LVCMOS33} [get_ports debug_io_6 ] ;# DEBUG_IO_6
|
||||
set_property -dict {PACKAGE_PIN W24 IOSTANDARD LVCMOS33} [get_ports debug_io_7 ] ;# DEBUG_IO_7
|
||||
set_property -dict {PACKAGE_PIN W23 IOSTANDARD LVCMOS33} [get_ports debug_io_8 ] ;# DEBUG_IO_8
|
||||
|
||||
set_property -dict {PACKAGE_PIN Y23 IOSTANDARD LVDS_25 } [get_ports debug_io_00_p ] ;# DEBUG_IO_00_P
|
||||
set_property -dict {PACKAGE_PIN Y21 IOSTANDARD LVDS_25 } [get_ports debug_io_01_p ] ;# DEBUG_IO_01_P
|
||||
set_property -dict {PACKAGE_PIN AA20 IOSTANDARD LVDS_25 } [get_ports debug_io_02_p ] ;# DEBUG_IO_02_P
|
||||
set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVDS_25 } [get_ports debug_io_03_p ] ;# DEBUG_IO_03_P
|
||||
set_property -dict {PACKAGE_PIN AC20 IOSTANDARD LVDS_25 } [get_ports debug_io_04_p ] ;# DEBUG_IO_04_P
|
||||
set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVDS_25 } [get_ports debug_io_05_p ] ;# DEBUG_IO_05_P
|
||||
set_property -dict {PACKAGE_PIN AC22 IOSTANDARD LVDS_25 } [get_ports debug_io_06_p ] ;# DEBUG_IO_06_P
|
||||
set_property -dict {PACKAGE_PIN AB22 IOSTANDARD LVDS_25 } [get_ports debug_io_07_p ] ;# DEBUG_IO_07_P
|
||||
set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVDS_25 } [get_ports debug_io_08_p ] ;# DEBUG_IO_08_P
|
||||
|
||||
# FLASH
|
||||
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
|
||||
set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]
|
||||
set_property CONFIG_MODE SPIx4 [current_design]
|
||||
@@ -0,0 +1,4 @@
|
||||
set_false_path -from [get_pins {u_system_bd_wrapper/system_bd_i/axi_gpio/U0/gpio_core_1/Dual.gpio_Data_Out_reg[8]/C}] -to [get_pins u_rx_pre_process/u_ad9361_phase_cal/ad9361_recal_d1_reg/D]
|
||||
set_false_path -from [get_pins {u_system_bd_wrapper/system_bd_i/axi_gpio/U0/gpio_core_1/Dual.gpio_Data_Out_reg[10]/C}] -to [get_pins u_rx_pre_process/u_ad9361_phase_cal/ad9361_1_cal_start_d1_reg/D]
|
||||
#set_false_path -from [get_pins {u_system_bd_wrapper/system_bd_i/axi_gpio/U0/gpio_core_1/Dual.gpio_Data_Out_reg[7]/C}] -to [get_pins u_tx_pre_process/ad9361_tx_switch_d1_reg/D]
|
||||
set_false_path -from [get_pins {u_system_bd_wrapper/system_bd_i/axi_gpio/U0/gpio_core_1/Dual.gpio_Data_Out_reg[9]/C}] -to [get_pins u_rx_pre_process/u_ad9361_phase_cal/ad9361_2_cal_start_d1_reg/D]
|
||||
Binary file not shown.
Binary file not shown.
@@ -0,0 +1 @@
|
||||
The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.
|
||||
+70
@@ -0,0 +1,70 @@
|
||||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
|
||||
// IP Revision: 3
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
COSLUT_10_16bit your_instance_name (
|
||||
.clka(clka), // input wire clka
|
||||
.addra(addra), // input wire [12 : 0] addra
|
||||
.douta(douta), // output wire [17 : 0] douta
|
||||
.clkb(clkb), // input wire clkb
|
||||
.addrb(addrb), // input wire [12 : 0] addrb
|
||||
.doutb(doutb) // output wire [17 : 0] doutb
|
||||
);
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
// You must compile the wrapper file COSLUT_10_16bit.v when simulating
|
||||
// the core, COSLUT_10_16bit. When compiling the wrapper file, be sure to
|
||||
// reference the Verilog simulation library.
|
||||
|
||||
+85
@@ -0,0 +1,85 @@
|
||||
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
|
||||
-- IP Revision: 3
|
||||
|
||||
-- The following code must appear in the VHDL architecture header.
|
||||
|
||||
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
|
||||
COMPONENT COSLUT_10_16bit
|
||||
PORT (
|
||||
clka : IN STD_LOGIC;
|
||||
addra : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
|
||||
douta : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
|
||||
clkb : IN STD_LOGIC;
|
||||
addrb : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
|
||||
doutb : OUT STD_LOGIC_VECTOR(17 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
||||
|
||||
-- The following code must appear in the VHDL architecture
|
||||
-- body. Substitute your own instance name and net names.
|
||||
|
||||
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
|
||||
your_instance_name : COSLUT_10_16bit
|
||||
PORT MAP (
|
||||
clka => clka,
|
||||
addra => addra,
|
||||
douta => douta,
|
||||
clkb => clkb,
|
||||
addrb => addrb,
|
||||
doutb => doutb
|
||||
);
|
||||
-- INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
-- You must compile the wrapper file COSLUT_10_16bit.vhd when simulating
|
||||
-- the core, COSLUT_10_16bit. When compiling the wrapper file, be sure to
|
||||
-- reference the VHDL simulation library.
|
||||
|
||||
LFS
BIN
Binary file not shown.
projects/dl814_k7/dl814_k7_beam/ip/ip_user_files/ip/COSLUT_10_16bit/COSLUT_10_16bit_sim_netlist.vhdl
LFS
BIN
Binary file not shown.
+25
@@ -0,0 +1,25 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Sun Mar 26 00:23:32 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/COSLUT_10_16bit_stub.v
|
||||
// Design : COSLUT_10_16bit
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "blk_mem_gen_v8_4_3,Vivado 2019.1.3" *)
|
||||
module COSLUT_10_16bit(clka, addra, douta, clkb, addrb, doutb)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clka,addra[12:0],douta[17:0],clkb,addrb[12:0],doutb[17:0]" */;
|
||||
input clka;
|
||||
input [12:0]addra;
|
||||
output [17:0]douta;
|
||||
input clkb;
|
||||
input [12:0]addrb;
|
||||
output [17:0]doutb;
|
||||
endmodule
|
||||
+35
@@ -0,0 +1,35 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Sun Mar 26 00:23:32 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ip/managed_ip_project/managed_ip_project.runs/COSLUT_10_16bit_synth_1/COSLUT_10_16bit_stub.vhdl
|
||||
-- Design : COSLUT_10_16bit
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity COSLUT_10_16bit is
|
||||
Port (
|
||||
clka : in STD_LOGIC;
|
||||
addra : in STD_LOGIC_VECTOR ( 12 downto 0 );
|
||||
douta : out STD_LOGIC_VECTOR ( 17 downto 0 );
|
||||
clkb : in STD_LOGIC;
|
||||
addrb : in STD_LOGIC_VECTOR ( 12 downto 0 );
|
||||
doutb : out STD_LOGIC_VECTOR ( 17 downto 0 )
|
||||
);
|
||||
|
||||
end COSLUT_10_16bit;
|
||||
|
||||
architecture stub of COSLUT_10_16bit is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clka,addra[12:0],douta[17:0],clkb,addrb[12:0],doutb[17:0]";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_3,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
+221
@@ -0,0 +1,221 @@
|
||||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
|
||||
// IP Revision: 3
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module COSLUT_10_16bit (
|
||||
clka,
|
||||
addra,
|
||||
douta,
|
||||
clkb,
|
||||
addrb,
|
||||
doutb
|
||||
);
|
||||
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
|
||||
input wire clka;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
|
||||
input wire [12 : 0] addra;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
|
||||
output wire [17 : 0] douta;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK" *)
|
||||
input wire clkb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR" *)
|
||||
input wire [12 : 0] addrb;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME BRAM_PORTB, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT" *)
|
||||
output wire [17 : 0] doutb;
|
||||
|
||||
blk_mem_gen_v8_4_3 #(
|
||||
.C_FAMILY("kintex7"),
|
||||
.C_XDEVICEFAMILY("kintex7"),
|
||||
.C_ELABORATION_DIR("./"),
|
||||
.C_INTERFACE_TYPE(0),
|
||||
.C_AXI_TYPE(1),
|
||||
.C_AXI_SLAVE_TYPE(0),
|
||||
.C_USE_BRAM_BLOCK(0),
|
||||
.C_ENABLE_32BIT_ADDRESS(0),
|
||||
.C_CTRL_ECC_ALGO("NONE"),
|
||||
.C_HAS_AXI_ID(0),
|
||||
.C_AXI_ID_WIDTH(4),
|
||||
.C_MEM_TYPE(4),
|
||||
.C_BYTE_SIZE(9),
|
||||
.C_ALGORITHM(1),
|
||||
.C_PRIM_TYPE(1),
|
||||
.C_LOAD_INIT_FILE(1),
|
||||
.C_INIT_FILE_NAME("COSLUT_10_16bit.mif"),
|
||||
.C_INIT_FILE("COSLUT_10_16bit.mem"),
|
||||
.C_USE_DEFAULT_DATA(0),
|
||||
.C_DEFAULT_DATA("0"),
|
||||
.C_HAS_RSTA(0),
|
||||
.C_RST_PRIORITY_A("CE"),
|
||||
.C_RSTRAM_A(0),
|
||||
.C_INITA_VAL("0"),
|
||||
.C_HAS_ENA(0),
|
||||
.C_HAS_REGCEA(0),
|
||||
.C_USE_BYTE_WEA(0),
|
||||
.C_WEA_WIDTH(1),
|
||||
.C_WRITE_MODE_A("WRITE_FIRST"),
|
||||
.C_WRITE_WIDTH_A(18),
|
||||
.C_READ_WIDTH_A(18),
|
||||
.C_WRITE_DEPTH_A(8192),
|
||||
.C_READ_DEPTH_A(8192),
|
||||
.C_ADDRA_WIDTH(13),
|
||||
.C_HAS_RSTB(0),
|
||||
.C_RST_PRIORITY_B("CE"),
|
||||
.C_RSTRAM_B(0),
|
||||
.C_INITB_VAL("0"),
|
||||
.C_HAS_ENB(0),
|
||||
.C_HAS_REGCEB(0),
|
||||
.C_USE_BYTE_WEB(0),
|
||||
.C_WEB_WIDTH(1),
|
||||
.C_WRITE_MODE_B("WRITE_FIRST"),
|
||||
.C_WRITE_WIDTH_B(18),
|
||||
.C_READ_WIDTH_B(18),
|
||||
.C_WRITE_DEPTH_B(8192),
|
||||
.C_READ_DEPTH_B(8192),
|
||||
.C_ADDRB_WIDTH(13),
|
||||
.C_HAS_MEM_OUTPUT_REGS_A(1),
|
||||
.C_HAS_MEM_OUTPUT_REGS_B(1),
|
||||
.C_HAS_MUX_OUTPUT_REGS_A(1),
|
||||
.C_HAS_MUX_OUTPUT_REGS_B(1),
|
||||
.C_MUX_PIPELINE_STAGES(0),
|
||||
.C_HAS_SOFTECC_INPUT_REGS_A(0),
|
||||
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
|
||||
.C_USE_SOFTECC(0),
|
||||
.C_USE_ECC(0),
|
||||
.C_EN_ECC_PIPE(0),
|
||||
.C_READ_LATENCY_A(1),
|
||||
.C_READ_LATENCY_B(1),
|
||||
.C_HAS_INJECTERR(0),
|
||||
.C_SIM_COLLISION_CHECK("ALL"),
|
||||
.C_COMMON_CLK(0),
|
||||
.C_DISABLE_WARN_BHV_COLL(0),
|
||||
.C_EN_SLEEP_PIN(0),
|
||||
.C_USE_URAM(0),
|
||||
.C_EN_RDADDRA_CHG(0),
|
||||
.C_EN_RDADDRB_CHG(0),
|
||||
.C_EN_DEEPSLEEP_PIN(0),
|
||||
.C_EN_SHUTDOWN_PIN(0),
|
||||
.C_EN_SAFETY_CKT(0),
|
||||
.C_DISABLE_WARN_BHV_RANGE(0),
|
||||
.C_COUNT_36K_BRAM("4"),
|
||||
.C_COUNT_18K_BRAM("0"),
|
||||
.C_EST_POWER_SUMMARY("Estimated Power for IP : 9.414399 mW")
|
||||
) inst (
|
||||
.clka(clka),
|
||||
.rsta(1'D0),
|
||||
.ena(1'D0),
|
||||
.regcea(1'D0),
|
||||
.wea(1'B0),
|
||||
.addra(addra),
|
||||
.dina(18'B0),
|
||||
.douta(douta),
|
||||
.clkb(clkb),
|
||||
.rstb(1'D0),
|
||||
.enb(1'D0),
|
||||
.regceb(1'D0),
|
||||
.web(1'B0),
|
||||
.addrb(addrb),
|
||||
.dinb(18'B0),
|
||||
.doutb(doutb),
|
||||
.injectsbiterr(1'D0),
|
||||
.injectdbiterr(1'D0),
|
||||
.eccpipece(1'D0),
|
||||
.sbiterr(),
|
||||
.dbiterr(),
|
||||
.rdaddrecc(),
|
||||
.sleep(1'D0),
|
||||
.deepsleep(1'D0),
|
||||
.shutdown(1'D0),
|
||||
.rsta_busy(),
|
||||
.rstb_busy(),
|
||||
.s_aclk(1'H0),
|
||||
.s_aresetn(1'D0),
|
||||
.s_axi_awid(4'B0),
|
||||
.s_axi_awaddr(32'B0),
|
||||
.s_axi_awlen(8'B0),
|
||||
.s_axi_awsize(3'B0),
|
||||
.s_axi_awburst(2'B0),
|
||||
.s_axi_awvalid(1'D0),
|
||||
.s_axi_awready(),
|
||||
.s_axi_wdata(18'B0),
|
||||
.s_axi_wstrb(1'B0),
|
||||
.s_axi_wlast(1'D0),
|
||||
.s_axi_wvalid(1'D0),
|
||||
.s_axi_wready(),
|
||||
.s_axi_bid(),
|
||||
.s_axi_bresp(),
|
||||
.s_axi_bvalid(),
|
||||
.s_axi_bready(1'D0),
|
||||
.s_axi_arid(4'B0),
|
||||
.s_axi_araddr(32'B0),
|
||||
.s_axi_arlen(8'B0),
|
||||
.s_axi_arsize(3'B0),
|
||||
.s_axi_arburst(2'B0),
|
||||
.s_axi_arvalid(1'D0),
|
||||
.s_axi_arready(),
|
||||
.s_axi_rid(),
|
||||
.s_axi_rdata(),
|
||||
.s_axi_rresp(),
|
||||
.s_axi_rlast(),
|
||||
.s_axi_rvalid(),
|
||||
.s_axi_rready(1'D0),
|
||||
.s_axi_injectsbiterr(1'D0),
|
||||
.s_axi_injectdbiterr(1'D0),
|
||||
.s_axi_sbiterr(),
|
||||
.s_axi_dbiterr(),
|
||||
.s_axi_rdaddrecc()
|
||||
);
|
||||
endmodule
|
||||
@@ -0,0 +1,70 @@
|
||||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
// IP VLNV: xilinx.com:ip:fir_compiler:7.2
|
||||
// IP Revision: 12
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
GaussFir_12m your_instance_name (
|
||||
.aclk(aclk), // input wire aclk
|
||||
.s_axis_data_tvalid(s_axis_data_tvalid), // input wire s_axis_data_tvalid
|
||||
.s_axis_data_tready(s_axis_data_tready), // output wire s_axis_data_tready
|
||||
.s_axis_data_tdata(s_axis_data_tdata), // input wire [7 : 0] s_axis_data_tdata
|
||||
.m_axis_data_tvalid(m_axis_data_tvalid), // output wire m_axis_data_tvalid
|
||||
.m_axis_data_tdata(m_axis_data_tdata) // output wire [15 : 0] m_axis_data_tdata
|
||||
);
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
// You must compile the wrapper file GaussFir_12m.v when simulating
|
||||
// the core, GaussFir_12m. When compiling the wrapper file, be sure to
|
||||
// reference the Verilog simulation library.
|
||||
|
||||
@@ -0,0 +1,85 @@
|
||||
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:fir_compiler:7.2
|
||||
-- IP Revision: 12
|
||||
|
||||
-- The following code must appear in the VHDL architecture header.
|
||||
|
||||
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
|
||||
COMPONENT GaussFir_12m
|
||||
PORT (
|
||||
aclk : IN STD_LOGIC;
|
||||
s_axis_data_tvalid : IN STD_LOGIC;
|
||||
s_axis_data_tready : OUT STD_LOGIC;
|
||||
s_axis_data_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axis_data_tvalid : OUT STD_LOGIC;
|
||||
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
||||
|
||||
-- The following code must appear in the VHDL architecture
|
||||
-- body. Substitute your own instance name and net names.
|
||||
|
||||
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
|
||||
your_instance_name : GaussFir_12m
|
||||
PORT MAP (
|
||||
aclk => aclk,
|
||||
s_axis_data_tvalid => s_axis_data_tvalid,
|
||||
s_axis_data_tready => s_axis_data_tready,
|
||||
s_axis_data_tdata => s_axis_data_tdata,
|
||||
m_axis_data_tvalid => m_axis_data_tvalid,
|
||||
m_axis_data_tdata => m_axis_data_tdata
|
||||
);
|
||||
-- INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
-- You must compile the wrapper file GaussFir_12m.vhd when simulating
|
||||
-- the core, GaussFir_12m. When compiling the wrapper file, be sure to
|
||||
-- reference the VHDL simulation library.
|
||||
|
||||
BIN
Binary file not shown.
BIN
Binary file not shown.
@@ -0,0 +1,26 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Sun Mar 26 00:22:49 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/GaussFir_12m_stub.v
|
||||
// Design : GaussFir_12m
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "fir_compiler_v7_2_12,Vivado 2019.1.3" *)
|
||||
module GaussFir_12m(aclk, s_axis_data_tvalid, s_axis_data_tready,
|
||||
s_axis_data_tdata, m_axis_data_tvalid, m_axis_data_tdata)
|
||||
/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[7:0],m_axis_data_tvalid,m_axis_data_tdata[15:0]" */;
|
||||
input aclk;
|
||||
input s_axis_data_tvalid;
|
||||
output s_axis_data_tready;
|
||||
input [7:0]s_axis_data_tdata;
|
||||
output m_axis_data_tvalid;
|
||||
output [15:0]m_axis_data_tdata;
|
||||
endmodule
|
||||
+35
@@ -0,0 +1,35 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Sun Mar 26 00:22:49 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ip/managed_ip_project/managed_ip_project.runs/GaussFir_12m_synth_1/GaussFir_12m_stub.vhdl
|
||||
-- Design : GaussFir_12m
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity GaussFir_12m is
|
||||
Port (
|
||||
aclk : in STD_LOGIC;
|
||||
s_axis_data_tvalid : in STD_LOGIC;
|
||||
s_axis_data_tready : out STD_LOGIC;
|
||||
s_axis_data_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
m_axis_data_tvalid : out STD_LOGIC;
|
||||
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 )
|
||||
);
|
||||
|
||||
end GaussFir_12m;
|
||||
|
||||
architecture stub of GaussFir_12m is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[7:0],m_axis_data_tvalid,m_axis_data_tdata[15:0]";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "fir_compiler_v7_2_12,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
+261
@@ -0,0 +1,261 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- (c) Copyright 2011 - 2013 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--------------------------------------------------------------------------------
|
||||
-- Description:
|
||||
-- This is an example testbench for the FIR Compiler IP core.
|
||||
-- The testbench has been generated by Vivado to accompany the IP core
|
||||
-- instance you have generated.
|
||||
--
|
||||
-- This testbench is for demonstration purposes only. See note below for
|
||||
-- instructions on how to use it with your core.
|
||||
--
|
||||
-- See the FIR Compiler product guide for further information
|
||||
-- about this core.
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Using this testbench
|
||||
--
|
||||
-- This testbench instantiates your generated FIR Compiler core
|
||||
-- instance named "GaussFir_12m".
|
||||
--
|
||||
-- Use Vivado's Run Simulation flow to run this testbench. See the Vivado
|
||||
-- documentation for details.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity tb_GaussFir_12m is
|
||||
end tb_GaussFir_12m;
|
||||
|
||||
architecture tb of tb_GaussFir_12m is
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Timing constants
|
||||
-----------------------------------------------------------------------
|
||||
constant CLOCK_PERIOD : time := 100 ns;
|
||||
constant T_HOLD : time := 10 ns;
|
||||
constant T_STROBE : time := CLOCK_PERIOD - (1 ns);
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- DUT signals
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
-- General signals
|
||||
signal aclk : std_logic := '0'; -- the master clock
|
||||
|
||||
-- Data slave channel signals
|
||||
signal s_axis_data_tvalid : std_logic := '0'; -- payload is valid
|
||||
signal s_axis_data_tready : std_logic := '1'; -- slave is ready
|
||||
signal s_axis_data_tdata : std_logic_vector(7 downto 0) := (others => '0'); -- data payload
|
||||
|
||||
-- Data master channel signals
|
||||
signal m_axis_data_tvalid : std_logic := '0'; -- payload is valid
|
||||
signal m_axis_data_tdata : std_logic_vector(15 downto 0) := (others => '0'); -- data payload
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Aliases for AXI channel TDATA and TUSER fields
|
||||
-- These are a convenience for viewing data in a simulator waveform viewer.
|
||||
-- If using ModelSim or Questa, add "-voptargs=+acc=n" to the vsim command
|
||||
-- to prevent the simulator optimizing away these signals.
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
-- Data slave channel alias signals
|
||||
signal s_axis_data_tdata_data : std_logic_vector(1 downto 0) := (others => '0');
|
||||
|
||||
-- Data master channel alias signals
|
||||
signal m_axis_data_tdata_data : std_logic_vector(14 downto 0) := (others => '0');
|
||||
|
||||
|
||||
begin
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Instantiate the DUT
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
dut : entity work.GaussFir_12m
|
||||
port map (
|
||||
aclk => aclk,
|
||||
s_axis_data_tvalid => s_axis_data_tvalid,
|
||||
s_axis_data_tready => s_axis_data_tready,
|
||||
s_axis_data_tdata => s_axis_data_tdata,
|
||||
m_axis_data_tvalid => m_axis_data_tvalid,
|
||||
m_axis_data_tdata => m_axis_data_tdata
|
||||
);
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Generate clock
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
clock_gen : process
|
||||
begin
|
||||
aclk <= '0';
|
||||
wait for CLOCK_PERIOD;
|
||||
loop
|
||||
aclk <= '0';
|
||||
wait for CLOCK_PERIOD/2;
|
||||
aclk <= '1';
|
||||
wait for CLOCK_PERIOD/2;
|
||||
end loop;
|
||||
end process clock_gen;
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Generate inputs
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
stimuli : process
|
||||
|
||||
-- Procedure to drive a number of input samples with specific data
|
||||
-- data is the data value to drive on the tdata signal
|
||||
-- samples is the number of zero-data input samples to drive
|
||||
procedure drive_data ( data : std_logic_vector(7 downto 0);
|
||||
samples : natural := 1 ) is
|
||||
variable ip_count : integer := 0;
|
||||
begin
|
||||
ip_count := 0;
|
||||
loop
|
||||
s_axis_data_tvalid <= '1';
|
||||
s_axis_data_tdata <= data;
|
||||
loop
|
||||
wait until rising_edge(aclk);
|
||||
exit when s_axis_data_tready = '1';
|
||||
end loop;
|
||||
ip_count := ip_count + 1;
|
||||
wait for T_HOLD;
|
||||
-- Input rate is 1 input each 4 clock cycles: drive valid inputs at this rate
|
||||
s_axis_data_tvalid <= '0';
|
||||
wait for CLOCK_PERIOD * 3;
|
||||
exit when ip_count >= samples;
|
||||
end loop;
|
||||
end procedure drive_data;
|
||||
|
||||
-- Procedure to drive a number of zero-data input samples
|
||||
-- samples is the number of zero-data input samples to drive
|
||||
procedure drive_zeros ( samples : natural := 1 ) is
|
||||
begin
|
||||
drive_data((others => '0'), samples);
|
||||
end procedure drive_zeros;
|
||||
|
||||
-- Procedure to drive an impulse and let the impulse response emerge on the data master channel
|
||||
-- samples is the number of input samples to drive; default is enough for impulse response output to emerge
|
||||
procedure drive_impulse ( samples : natural := 27 ) is
|
||||
variable impulse : std_logic_vector(7 downto 0);
|
||||
begin
|
||||
impulse := (others => '0'); -- initialize unused bits to zero
|
||||
impulse(1 downto 0) := "01";
|
||||
drive_data(impulse);
|
||||
if samples > 1 then
|
||||
drive_zeros(samples-1);
|
||||
end if;
|
||||
end procedure drive_impulse;
|
||||
|
||||
begin
|
||||
|
||||
-- Drive inputs T_HOLD time after rising edge of clock
|
||||
wait until rising_edge(aclk);
|
||||
wait for T_HOLD;
|
||||
|
||||
-- Drive a single impulse and let the impulse response emerge
|
||||
drive_impulse;
|
||||
|
||||
-- Drive another impulse, during which demonstrate use and effect of AXI handshaking signals
|
||||
drive_impulse(2); -- start of impulse; data is now zero
|
||||
s_axis_data_tvalid <= '0';
|
||||
wait for CLOCK_PERIOD * 20; -- provide no data for 5 input samples worth
|
||||
drive_zeros(2); -- 2 normal input samples
|
||||
s_axis_data_tvalid <= '1';
|
||||
wait for CLOCK_PERIOD * 20; -- provide data as fast as the core can accept it for 5 input samples worth
|
||||
drive_zeros(18); -- back to normal operation
|
||||
|
||||
-- End of test
|
||||
report "Not a real failure. Simulation finished successfully. Test completed successfully" severity failure;
|
||||
wait;
|
||||
|
||||
end process stimuli;
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Check outputs
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
check_outputs : process
|
||||
variable check_ok : boolean := true;
|
||||
begin
|
||||
|
||||
-- Check outputs T_STROBE time after rising edge of clock
|
||||
wait until rising_edge(aclk);
|
||||
wait for T_STROBE;
|
||||
|
||||
-- Do not check the output payload values, as this requires the behavioral model
|
||||
-- which would make this demonstration testbench unwieldy.
|
||||
-- Instead, check the protocol of the master DATA channel:
|
||||
-- check that the payload is valid (not X) when TVALID is high
|
||||
|
||||
if m_axis_data_tvalid = '1' then
|
||||
if is_x(m_axis_data_tdata) then
|
||||
report "ERROR: m_axis_data_tdata is invalid when m_axis_data_tvalid is high" severity error;
|
||||
check_ok := false;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
|
||||
assert check_ok
|
||||
report "ERROR: terminating test with failures." severity failure;
|
||||
|
||||
end process check_outputs;
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Assign TDATA / TUSER fields to aliases, for easy simulator waveform viewing
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
-- Data slave channel alias signals
|
||||
s_axis_data_tdata_data <= s_axis_data_tdata(1 downto 0);
|
||||
|
||||
-- Data master channel alias signals: update these only when they are valid
|
||||
m_axis_data_tdata_data <= m_axis_data_tdata(14 downto 0) when m_axis_data_tvalid = '1';
|
||||
|
||||
end tb;
|
||||
+281
@@ -0,0 +1,281 @@
|
||||
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:fir_compiler:7.2
|
||||
-- IP Revision: 12
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY fir_compiler_v7_2_12;
|
||||
USE fir_compiler_v7_2_12.fir_compiler_v7_2_12;
|
||||
|
||||
ENTITY GaussFir_12m IS
|
||||
PORT (
|
||||
aclk : IN STD_LOGIC;
|
||||
s_axis_data_tvalid : IN STD_LOGIC;
|
||||
s_axis_data_tready : OUT STD_LOGIC;
|
||||
s_axis_data_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axis_data_tvalid : OUT STD_LOGIC;
|
||||
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
|
||||
);
|
||||
END GaussFir_12m;
|
||||
|
||||
ARCHITECTURE GaussFir_12m_arch OF GaussFir_12m IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF GaussFir_12m_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT fir_compiler_v7_2_12 IS
|
||||
GENERIC (
|
||||
C_XDEVICEFAMILY : STRING;
|
||||
C_ELABORATION_DIR : STRING;
|
||||
C_COMPONENT_NAME : STRING;
|
||||
C_COEF_FILE : STRING;
|
||||
C_COEF_FILE_LINES : INTEGER;
|
||||
C_FILTER_TYPE : INTEGER;
|
||||
C_INTERP_RATE : INTEGER;
|
||||
C_DECIM_RATE : INTEGER;
|
||||
C_ZERO_PACKING_FACTOR : INTEGER;
|
||||
C_SYMMETRY : INTEGER;
|
||||
C_NUM_FILTS : INTEGER;
|
||||
C_NUM_TAPS : INTEGER;
|
||||
C_NUM_CHANNELS : INTEGER;
|
||||
C_CHANNEL_PATTERN : STRING;
|
||||
C_ROUND_MODE : INTEGER;
|
||||
C_COEF_RELOAD : INTEGER;
|
||||
C_NUM_RELOAD_SLOTS : INTEGER;
|
||||
C_COL_MODE : INTEGER;
|
||||
C_COL_PIPE_LEN : INTEGER;
|
||||
C_COL_CONFIG : STRING;
|
||||
C_OPTIMIZATION : INTEGER;
|
||||
C_DATA_PATH_WIDTHS : STRING;
|
||||
C_DATA_IP_PATH_WIDTHS : STRING;
|
||||
C_DATA_PX_PATH_WIDTHS : STRING;
|
||||
C_DATA_WIDTH : INTEGER;
|
||||
C_COEF_PATH_WIDTHS : STRING;
|
||||
C_COEF_WIDTH : INTEGER;
|
||||
C_DATA_PATH_SRC : STRING;
|
||||
C_COEF_PATH_SRC : STRING;
|
||||
C_PX_PATH_SRC : STRING;
|
||||
C_DATA_PATH_SIGN : STRING;
|
||||
C_COEF_PATH_SIGN : STRING;
|
||||
C_ACCUM_PATH_WIDTHS : STRING;
|
||||
C_OUTPUT_WIDTH : INTEGER;
|
||||
C_OUTPUT_PATH_WIDTHS : STRING;
|
||||
C_ACCUM_OP_PATH_WIDTHS : STRING;
|
||||
C_EXT_MULT_CNFG : STRING;
|
||||
C_DATA_PATH_PSAMP_SRC : STRING;
|
||||
C_OP_PATH_PSAMP_SRC : STRING;
|
||||
C_NUM_MADDS : INTEGER;
|
||||
C_OPT_MADDS : STRING;
|
||||
C_OVERSAMPLING_RATE : INTEGER;
|
||||
C_INPUT_RATE : INTEGER;
|
||||
C_OUTPUT_RATE : INTEGER;
|
||||
C_DATA_MEMTYPE : INTEGER;
|
||||
C_COEF_MEMTYPE : INTEGER;
|
||||
C_IPBUFF_MEMTYPE : INTEGER;
|
||||
C_OPBUFF_MEMTYPE : INTEGER;
|
||||
C_DATAPATH_MEMTYPE : INTEGER;
|
||||
C_MEM_ARRANGEMENT : INTEGER;
|
||||
C_DATA_MEM_PACKING : INTEGER;
|
||||
C_COEF_MEM_PACKING : INTEGER;
|
||||
C_FILTS_PACKED : INTEGER;
|
||||
C_LATENCY : INTEGER;
|
||||
C_HAS_ARESETn : INTEGER;
|
||||
C_HAS_ACLKEN : INTEGER;
|
||||
C_DATA_HAS_TLAST : INTEGER;
|
||||
C_S_DATA_HAS_FIFO : INTEGER;
|
||||
C_S_DATA_HAS_TUSER : INTEGER;
|
||||
C_S_DATA_TDATA_WIDTH : INTEGER;
|
||||
C_S_DATA_TUSER_WIDTH : INTEGER;
|
||||
C_M_DATA_HAS_TREADY : INTEGER;
|
||||
C_M_DATA_HAS_TUSER : INTEGER;
|
||||
C_M_DATA_TDATA_WIDTH : INTEGER;
|
||||
C_M_DATA_TUSER_WIDTH : INTEGER;
|
||||
C_HAS_CONFIG_CHANNEL : INTEGER;
|
||||
C_CONFIG_SYNC_MODE : INTEGER;
|
||||
C_CONFIG_PACKET_SIZE : INTEGER;
|
||||
C_CONFIG_TDATA_WIDTH : INTEGER;
|
||||
C_RELOAD_TDATA_WIDTH : INTEGER
|
||||
);
|
||||
PORT (
|
||||
aresetn : IN STD_LOGIC;
|
||||
aclk : IN STD_LOGIC;
|
||||
aclken : IN STD_LOGIC;
|
||||
s_axis_data_tvalid : IN STD_LOGIC;
|
||||
s_axis_data_tready : OUT STD_LOGIC;
|
||||
s_axis_data_tlast : IN STD_LOGIC;
|
||||
s_axis_data_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axis_data_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
s_axis_config_tvalid : IN STD_LOGIC;
|
||||
s_axis_config_tready : OUT STD_LOGIC;
|
||||
s_axis_config_tlast : IN STD_LOGIC;
|
||||
s_axis_config_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axis_reload_tvalid : IN STD_LOGIC;
|
||||
s_axis_reload_tready : OUT STD_LOGIC;
|
||||
s_axis_reload_tlast : IN STD_LOGIC;
|
||||
s_axis_reload_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
m_axis_data_tvalid : OUT STD_LOGIC;
|
||||
m_axis_data_tready : IN STD_LOGIC;
|
||||
m_axis_data_tlast : OUT STD_LOGIC;
|
||||
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
event_s_data_tlast_missing : OUT STD_LOGIC;
|
||||
event_s_data_tlast_unexpected : OUT STD_LOGIC;
|
||||
event_s_data_chanid_incorrect : OUT STD_LOGIC;
|
||||
event_s_config_tlast_missing : OUT STD_LOGIC;
|
||||
event_s_config_tlast_unexpected : OUT STD_LOGIC;
|
||||
event_s_reload_tlast_missing : OUT STD_LOGIC;
|
||||
event_s_reload_tlast_unexpected : OUT STD_LOGIC
|
||||
);
|
||||
END COMPONENT fir_compiler_v7_2_12;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axis_data_tvalid: SIGNAL IS "XIL_INTERFACENAME M_AXIS_DATA, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TREADY";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_data_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_DATA, TDATA_NUM_BYTES 1, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF aclk: SIGNAL IS "XIL_INTERFACENAME aclk_intf, ASSOCIATED_BUSIF S_AXIS_CONFIG:M_AXIS_DATA:S_AXIS_DATA:S_AXIS_RELOAD, ASSOCIATED_RESET aresetn, ASSOCIATED_CLKEN aclken, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
|
||||
BEGIN
|
||||
U0 : fir_compiler_v7_2_12
|
||||
GENERIC MAP (
|
||||
C_XDEVICEFAMILY => "kintex7",
|
||||
C_ELABORATION_DIR => "./",
|
||||
C_COMPONENT_NAME => "GaussFir_12m",
|
||||
C_COEF_FILE => "GaussFir_12m.mif",
|
||||
C_COEF_FILE_LINES => 20,
|
||||
C_FILTER_TYPE => 2,
|
||||
C_INTERP_RATE => 4,
|
||||
C_DECIM_RATE => 1,
|
||||
C_ZERO_PACKING_FACTOR => 1,
|
||||
C_SYMMETRY => 0,
|
||||
C_NUM_FILTS => 1,
|
||||
C_NUM_TAPS => 17,
|
||||
C_NUM_CHANNELS => 1,
|
||||
C_CHANNEL_PATTERN => "fixed",
|
||||
C_ROUND_MODE => 0,
|
||||
C_COEF_RELOAD => 0,
|
||||
C_NUM_RELOAD_SLOTS => 1,
|
||||
C_COL_MODE => 1,
|
||||
C_COL_PIPE_LEN => 4,
|
||||
C_COL_CONFIG => "5",
|
||||
C_OPTIMIZATION => 0,
|
||||
C_DATA_PATH_WIDTHS => "2",
|
||||
C_DATA_IP_PATH_WIDTHS => "2",
|
||||
C_DATA_PX_PATH_WIDTHS => "2",
|
||||
C_DATA_WIDTH => 2,
|
||||
C_COEF_PATH_WIDTHS => "14",
|
||||
C_COEF_WIDTH => 14,
|
||||
C_DATA_PATH_SRC => "0",
|
||||
C_COEF_PATH_SRC => "0",
|
||||
C_PX_PATH_SRC => "0",
|
||||
C_DATA_PATH_SIGN => "0",
|
||||
C_COEF_PATH_SIGN => "1",
|
||||
C_ACCUM_PATH_WIDTHS => "15",
|
||||
C_OUTPUT_WIDTH => 15,
|
||||
C_OUTPUT_PATH_WIDTHS => "15",
|
||||
C_ACCUM_OP_PATH_WIDTHS => "15",
|
||||
C_EXT_MULT_CNFG => "none",
|
||||
C_DATA_PATH_PSAMP_SRC => "0",
|
||||
C_OP_PATH_PSAMP_SRC => "0",
|
||||
C_NUM_MADDS => 5,
|
||||
C_OPT_MADDS => "none",
|
||||
C_OVERSAMPLING_RATE => 1,
|
||||
C_INPUT_RATE => 4,
|
||||
C_OUTPUT_RATE => 1,
|
||||
C_DATA_MEMTYPE => 0,
|
||||
C_COEF_MEMTYPE => 2,
|
||||
C_IPBUFF_MEMTYPE => 0,
|
||||
C_OPBUFF_MEMTYPE => 0,
|
||||
C_DATAPATH_MEMTYPE => 0,
|
||||
C_MEM_ARRANGEMENT => 2,
|
||||
C_DATA_MEM_PACKING => 0,
|
||||
C_COEF_MEM_PACKING => 0,
|
||||
C_FILTS_PACKED => 0,
|
||||
C_LATENCY => 11,
|
||||
C_HAS_ARESETn => 0,
|
||||
C_HAS_ACLKEN => 0,
|
||||
C_DATA_HAS_TLAST => 0,
|
||||
C_S_DATA_HAS_FIFO => 0,
|
||||
C_S_DATA_HAS_TUSER => 0,
|
||||
C_S_DATA_TDATA_WIDTH => 8,
|
||||
C_S_DATA_TUSER_WIDTH => 1,
|
||||
C_M_DATA_HAS_TREADY => 0,
|
||||
C_M_DATA_HAS_TUSER => 0,
|
||||
C_M_DATA_TDATA_WIDTH => 16,
|
||||
C_M_DATA_TUSER_WIDTH => 1,
|
||||
C_HAS_CONFIG_CHANNEL => 0,
|
||||
C_CONFIG_SYNC_MODE => 0,
|
||||
C_CONFIG_PACKET_SIZE => 0,
|
||||
C_CONFIG_TDATA_WIDTH => 1,
|
||||
C_RELOAD_TDATA_WIDTH => 1
|
||||
)
|
||||
PORT MAP (
|
||||
aresetn => '1',
|
||||
aclk => aclk,
|
||||
aclken => '1',
|
||||
s_axis_data_tvalid => s_axis_data_tvalid,
|
||||
s_axis_data_tready => s_axis_data_tready,
|
||||
s_axis_data_tlast => '0',
|
||||
s_axis_data_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
s_axis_data_tdata => s_axis_data_tdata,
|
||||
s_axis_config_tvalid => '0',
|
||||
s_axis_config_tlast => '0',
|
||||
s_axis_config_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
s_axis_reload_tvalid => '0',
|
||||
s_axis_reload_tlast => '0',
|
||||
s_axis_reload_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
m_axis_data_tvalid => m_axis_data_tvalid,
|
||||
m_axis_data_tready => '1',
|
||||
m_axis_data_tdata => m_axis_data_tdata
|
||||
);
|
||||
END GaussFir_12m_arch;
|
||||
@@ -0,0 +1,70 @@
|
||||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
// IP VLNV: xilinx.com:ip:fir_compiler:7.2
|
||||
// IP Revision: 12
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
GaussFir_1mp5 your_instance_name (
|
||||
.aclk(aclk), // input wire aclk
|
||||
.s_axis_data_tvalid(s_axis_data_tvalid), // input wire s_axis_data_tvalid
|
||||
.s_axis_data_tready(s_axis_data_tready), // output wire s_axis_data_tready
|
||||
.s_axis_data_tdata(s_axis_data_tdata), // input wire [7 : 0] s_axis_data_tdata
|
||||
.m_axis_data_tvalid(m_axis_data_tvalid), // output wire m_axis_data_tvalid
|
||||
.m_axis_data_tdata(m_axis_data_tdata) // output wire [15 : 0] m_axis_data_tdata
|
||||
);
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
// You must compile the wrapper file GaussFir_1mp5.v when simulating
|
||||
// the core, GaussFir_1mp5. When compiling the wrapper file, be sure to
|
||||
// reference the Verilog simulation library.
|
||||
|
||||
@@ -0,0 +1,85 @@
|
||||
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:fir_compiler:7.2
|
||||
-- IP Revision: 12
|
||||
|
||||
-- The following code must appear in the VHDL architecture header.
|
||||
|
||||
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
|
||||
COMPONENT GaussFir_1mp5
|
||||
PORT (
|
||||
aclk : IN STD_LOGIC;
|
||||
s_axis_data_tvalid : IN STD_LOGIC;
|
||||
s_axis_data_tready : OUT STD_LOGIC;
|
||||
s_axis_data_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axis_data_tvalid : OUT STD_LOGIC;
|
||||
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
||||
|
||||
-- The following code must appear in the VHDL architecture
|
||||
-- body. Substitute your own instance name and net names.
|
||||
|
||||
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
|
||||
your_instance_name : GaussFir_1mp5
|
||||
PORT MAP (
|
||||
aclk => aclk,
|
||||
s_axis_data_tvalid => s_axis_data_tvalid,
|
||||
s_axis_data_tready => s_axis_data_tready,
|
||||
s_axis_data_tdata => s_axis_data_tdata,
|
||||
m_axis_data_tvalid => m_axis_data_tvalid,
|
||||
m_axis_data_tdata => m_axis_data_tdata
|
||||
);
|
||||
-- INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
-- You must compile the wrapper file GaussFir_1mp5.vhd when simulating
|
||||
-- the core, GaussFir_1mp5. When compiling the wrapper file, be sure to
|
||||
-- reference the VHDL simulation library.
|
||||
|
||||
BIN
Binary file not shown.
LFS
BIN
Binary file not shown.
+26
@@ -0,0 +1,26 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Sun Mar 26 00:22:49 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/GaussFir_1mp5_stub.v
|
||||
// Design : GaussFir_1mp5
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "fir_compiler_v7_2_12,Vivado 2019.1.3" *)
|
||||
module GaussFir_1mp5(aclk, s_axis_data_tvalid, s_axis_data_tready,
|
||||
s_axis_data_tdata, m_axis_data_tvalid, m_axis_data_tdata)
|
||||
/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[7:0],m_axis_data_tvalid,m_axis_data_tdata[15:0]" */;
|
||||
input aclk;
|
||||
input s_axis_data_tvalid;
|
||||
output s_axis_data_tready;
|
||||
input [7:0]s_axis_data_tdata;
|
||||
output m_axis_data_tvalid;
|
||||
output [15:0]m_axis_data_tdata;
|
||||
endmodule
|
||||
+35
@@ -0,0 +1,35 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Sun Mar 26 00:22:49 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ip/managed_ip_project/managed_ip_project.runs/GaussFir_1mp5_synth_1/GaussFir_1mp5_stub.vhdl
|
||||
-- Design : GaussFir_1mp5
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity GaussFir_1mp5 is
|
||||
Port (
|
||||
aclk : in STD_LOGIC;
|
||||
s_axis_data_tvalid : in STD_LOGIC;
|
||||
s_axis_data_tready : out STD_LOGIC;
|
||||
s_axis_data_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
m_axis_data_tvalid : out STD_LOGIC;
|
||||
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 )
|
||||
);
|
||||
|
||||
end GaussFir_1mp5;
|
||||
|
||||
architecture stub of GaussFir_1mp5 is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[7:0],m_axis_data_tvalid,m_axis_data_tdata[15:0]";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "fir_compiler_v7_2_12,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
+261
@@ -0,0 +1,261 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- (c) Copyright 2011 - 2013 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--------------------------------------------------------------------------------
|
||||
-- Description:
|
||||
-- This is an example testbench for the FIR Compiler IP core.
|
||||
-- The testbench has been generated by Vivado to accompany the IP core
|
||||
-- instance you have generated.
|
||||
--
|
||||
-- This testbench is for demonstration purposes only. See note below for
|
||||
-- instructions on how to use it with your core.
|
||||
--
|
||||
-- See the FIR Compiler product guide for further information
|
||||
-- about this core.
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Using this testbench
|
||||
--
|
||||
-- This testbench instantiates your generated FIR Compiler core
|
||||
-- instance named "GaussFir_1mp5".
|
||||
--
|
||||
-- Use Vivado's Run Simulation flow to run this testbench. See the Vivado
|
||||
-- documentation for details.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity tb_GaussFir_1mp5 is
|
||||
end tb_GaussFir_1mp5;
|
||||
|
||||
architecture tb of tb_GaussFir_1mp5 is
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Timing constants
|
||||
-----------------------------------------------------------------------
|
||||
constant CLOCK_PERIOD : time := 100 ns;
|
||||
constant T_HOLD : time := 10 ns;
|
||||
constant T_STROBE : time := CLOCK_PERIOD - (1 ns);
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- DUT signals
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
-- General signals
|
||||
signal aclk : std_logic := '0'; -- the master clock
|
||||
|
||||
-- Data slave channel signals
|
||||
signal s_axis_data_tvalid : std_logic := '0'; -- payload is valid
|
||||
signal s_axis_data_tready : std_logic := '1'; -- slave is ready
|
||||
signal s_axis_data_tdata : std_logic_vector(7 downto 0) := (others => '0'); -- data payload
|
||||
|
||||
-- Data master channel signals
|
||||
signal m_axis_data_tvalid : std_logic := '0'; -- payload is valid
|
||||
signal m_axis_data_tdata : std_logic_vector(15 downto 0) := (others => '0'); -- data payload
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Aliases for AXI channel TDATA and TUSER fields
|
||||
-- These are a convenience for viewing data in a simulator waveform viewer.
|
||||
-- If using ModelSim or Questa, add "-voptargs=+acc=n" to the vsim command
|
||||
-- to prevent the simulator optimizing away these signals.
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
-- Data slave channel alias signals
|
||||
signal s_axis_data_tdata_data : std_logic_vector(1 downto 0) := (others => '0');
|
||||
|
||||
-- Data master channel alias signals
|
||||
signal m_axis_data_tdata_data : std_logic_vector(12 downto 0) := (others => '0');
|
||||
|
||||
|
||||
begin
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Instantiate the DUT
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
dut : entity work.GaussFir_1mp5
|
||||
port map (
|
||||
aclk => aclk,
|
||||
s_axis_data_tvalid => s_axis_data_tvalid,
|
||||
s_axis_data_tready => s_axis_data_tready,
|
||||
s_axis_data_tdata => s_axis_data_tdata,
|
||||
m_axis_data_tvalid => m_axis_data_tvalid,
|
||||
m_axis_data_tdata => m_axis_data_tdata
|
||||
);
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Generate clock
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
clock_gen : process
|
||||
begin
|
||||
aclk <= '0';
|
||||
wait for CLOCK_PERIOD;
|
||||
loop
|
||||
aclk <= '0';
|
||||
wait for CLOCK_PERIOD/2;
|
||||
aclk <= '1';
|
||||
wait for CLOCK_PERIOD/2;
|
||||
end loop;
|
||||
end process clock_gen;
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Generate inputs
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
stimuli : process
|
||||
|
||||
-- Procedure to drive a number of input samples with specific data
|
||||
-- data is the data value to drive on the tdata signal
|
||||
-- samples is the number of zero-data input samples to drive
|
||||
procedure drive_data ( data : std_logic_vector(7 downto 0);
|
||||
samples : natural := 1 ) is
|
||||
variable ip_count : integer := 0;
|
||||
begin
|
||||
ip_count := 0;
|
||||
loop
|
||||
s_axis_data_tvalid <= '1';
|
||||
s_axis_data_tdata <= data;
|
||||
loop
|
||||
wait until rising_edge(aclk);
|
||||
exit when s_axis_data_tready = '1';
|
||||
end loop;
|
||||
ip_count := ip_count + 1;
|
||||
wait for T_HOLD;
|
||||
-- Input rate is 1 input each 32 clock cycles: drive valid inputs at this rate
|
||||
s_axis_data_tvalid <= '0';
|
||||
wait for CLOCK_PERIOD * 31;
|
||||
exit when ip_count >= samples;
|
||||
end loop;
|
||||
end procedure drive_data;
|
||||
|
||||
-- Procedure to drive a number of zero-data input samples
|
||||
-- samples is the number of zero-data input samples to drive
|
||||
procedure drive_zeros ( samples : natural := 1 ) is
|
||||
begin
|
||||
drive_data((others => '0'), samples);
|
||||
end procedure drive_zeros;
|
||||
|
||||
-- Procedure to drive an impulse and let the impulse response emerge on the data master channel
|
||||
-- samples is the number of input samples to drive; default is enough for impulse response output to emerge
|
||||
procedure drive_impulse ( samples : natural := 165 ) is
|
||||
variable impulse : std_logic_vector(7 downto 0);
|
||||
begin
|
||||
impulse := (others => '0'); -- initialize unused bits to zero
|
||||
impulse(1 downto 0) := "01";
|
||||
drive_data(impulse);
|
||||
if samples > 1 then
|
||||
drive_zeros(samples-1);
|
||||
end if;
|
||||
end procedure drive_impulse;
|
||||
|
||||
begin
|
||||
|
||||
-- Drive inputs T_HOLD time after rising edge of clock
|
||||
wait until rising_edge(aclk);
|
||||
wait for T_HOLD;
|
||||
|
||||
-- Drive a single impulse and let the impulse response emerge
|
||||
drive_impulse;
|
||||
|
||||
-- Drive another impulse, during which demonstrate use and effect of AXI handshaking signals
|
||||
drive_impulse(2); -- start of impulse; data is now zero
|
||||
s_axis_data_tvalid <= '0';
|
||||
wait for CLOCK_PERIOD * 160; -- provide no data for 5 input samples worth
|
||||
drive_zeros(2); -- 2 normal input samples
|
||||
s_axis_data_tvalid <= '1';
|
||||
wait for CLOCK_PERIOD * 160; -- provide data as fast as the core can accept it for 5 input samples worth
|
||||
drive_zeros(156); -- back to normal operation
|
||||
|
||||
-- End of test
|
||||
report "Not a real failure. Simulation finished successfully. Test completed successfully" severity failure;
|
||||
wait;
|
||||
|
||||
end process stimuli;
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Check outputs
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
check_outputs : process
|
||||
variable check_ok : boolean := true;
|
||||
begin
|
||||
|
||||
-- Check outputs T_STROBE time after rising edge of clock
|
||||
wait until rising_edge(aclk);
|
||||
wait for T_STROBE;
|
||||
|
||||
-- Do not check the output payload values, as this requires the behavioral model
|
||||
-- which would make this demonstration testbench unwieldy.
|
||||
-- Instead, check the protocol of the master DATA channel:
|
||||
-- check that the payload is valid (not X) when TVALID is high
|
||||
|
||||
if m_axis_data_tvalid = '1' then
|
||||
if is_x(m_axis_data_tdata) then
|
||||
report "ERROR: m_axis_data_tdata is invalid when m_axis_data_tvalid is high" severity error;
|
||||
check_ok := false;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
|
||||
assert check_ok
|
||||
report "ERROR: terminating test with failures." severity failure;
|
||||
|
||||
end process check_outputs;
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Assign TDATA / TUSER fields to aliases, for easy simulator waveform viewing
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
-- Data slave channel alias signals
|
||||
s_axis_data_tdata_data <= s_axis_data_tdata(1 downto 0);
|
||||
|
||||
-- Data master channel alias signals: update these only when they are valid
|
||||
m_axis_data_tdata_data <= m_axis_data_tdata(12 downto 0) when m_axis_data_tvalid = '1';
|
||||
|
||||
end tb;
|
||||
+281
@@ -0,0 +1,281 @@
|
||||
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:fir_compiler:7.2
|
||||
-- IP Revision: 12
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY fir_compiler_v7_2_12;
|
||||
USE fir_compiler_v7_2_12.fir_compiler_v7_2_12;
|
||||
|
||||
ENTITY GaussFir_1mp5 IS
|
||||
PORT (
|
||||
aclk : IN STD_LOGIC;
|
||||
s_axis_data_tvalid : IN STD_LOGIC;
|
||||
s_axis_data_tready : OUT STD_LOGIC;
|
||||
s_axis_data_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axis_data_tvalid : OUT STD_LOGIC;
|
||||
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
|
||||
);
|
||||
END GaussFir_1mp5;
|
||||
|
||||
ARCHITECTURE GaussFir_1mp5_arch OF GaussFir_1mp5 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF GaussFir_1mp5_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT fir_compiler_v7_2_12 IS
|
||||
GENERIC (
|
||||
C_XDEVICEFAMILY : STRING;
|
||||
C_ELABORATION_DIR : STRING;
|
||||
C_COMPONENT_NAME : STRING;
|
||||
C_COEF_FILE : STRING;
|
||||
C_COEF_FILE_LINES : INTEGER;
|
||||
C_FILTER_TYPE : INTEGER;
|
||||
C_INTERP_RATE : INTEGER;
|
||||
C_DECIM_RATE : INTEGER;
|
||||
C_ZERO_PACKING_FACTOR : INTEGER;
|
||||
C_SYMMETRY : INTEGER;
|
||||
C_NUM_FILTS : INTEGER;
|
||||
C_NUM_TAPS : INTEGER;
|
||||
C_NUM_CHANNELS : INTEGER;
|
||||
C_CHANNEL_PATTERN : STRING;
|
||||
C_ROUND_MODE : INTEGER;
|
||||
C_COEF_RELOAD : INTEGER;
|
||||
C_NUM_RELOAD_SLOTS : INTEGER;
|
||||
C_COL_MODE : INTEGER;
|
||||
C_COL_PIPE_LEN : INTEGER;
|
||||
C_COL_CONFIG : STRING;
|
||||
C_OPTIMIZATION : INTEGER;
|
||||
C_DATA_PATH_WIDTHS : STRING;
|
||||
C_DATA_IP_PATH_WIDTHS : STRING;
|
||||
C_DATA_PX_PATH_WIDTHS : STRING;
|
||||
C_DATA_WIDTH : INTEGER;
|
||||
C_COEF_PATH_WIDTHS : STRING;
|
||||
C_COEF_WIDTH : INTEGER;
|
||||
C_DATA_PATH_SRC : STRING;
|
||||
C_COEF_PATH_SRC : STRING;
|
||||
C_PX_PATH_SRC : STRING;
|
||||
C_DATA_PATH_SIGN : STRING;
|
||||
C_COEF_PATH_SIGN : STRING;
|
||||
C_ACCUM_PATH_WIDTHS : STRING;
|
||||
C_OUTPUT_WIDTH : INTEGER;
|
||||
C_OUTPUT_PATH_WIDTHS : STRING;
|
||||
C_ACCUM_OP_PATH_WIDTHS : STRING;
|
||||
C_EXT_MULT_CNFG : STRING;
|
||||
C_DATA_PATH_PSAMP_SRC : STRING;
|
||||
C_OP_PATH_PSAMP_SRC : STRING;
|
||||
C_NUM_MADDS : INTEGER;
|
||||
C_OPT_MADDS : STRING;
|
||||
C_OVERSAMPLING_RATE : INTEGER;
|
||||
C_INPUT_RATE : INTEGER;
|
||||
C_OUTPUT_RATE : INTEGER;
|
||||
C_DATA_MEMTYPE : INTEGER;
|
||||
C_COEF_MEMTYPE : INTEGER;
|
||||
C_IPBUFF_MEMTYPE : INTEGER;
|
||||
C_OPBUFF_MEMTYPE : INTEGER;
|
||||
C_DATAPATH_MEMTYPE : INTEGER;
|
||||
C_MEM_ARRANGEMENT : INTEGER;
|
||||
C_DATA_MEM_PACKING : INTEGER;
|
||||
C_COEF_MEM_PACKING : INTEGER;
|
||||
C_FILTS_PACKED : INTEGER;
|
||||
C_LATENCY : INTEGER;
|
||||
C_HAS_ARESETn : INTEGER;
|
||||
C_HAS_ACLKEN : INTEGER;
|
||||
C_DATA_HAS_TLAST : INTEGER;
|
||||
C_S_DATA_HAS_FIFO : INTEGER;
|
||||
C_S_DATA_HAS_TUSER : INTEGER;
|
||||
C_S_DATA_TDATA_WIDTH : INTEGER;
|
||||
C_S_DATA_TUSER_WIDTH : INTEGER;
|
||||
C_M_DATA_HAS_TREADY : INTEGER;
|
||||
C_M_DATA_HAS_TUSER : INTEGER;
|
||||
C_M_DATA_TDATA_WIDTH : INTEGER;
|
||||
C_M_DATA_TUSER_WIDTH : INTEGER;
|
||||
C_HAS_CONFIG_CHANNEL : INTEGER;
|
||||
C_CONFIG_SYNC_MODE : INTEGER;
|
||||
C_CONFIG_PACKET_SIZE : INTEGER;
|
||||
C_CONFIG_TDATA_WIDTH : INTEGER;
|
||||
C_RELOAD_TDATA_WIDTH : INTEGER
|
||||
);
|
||||
PORT (
|
||||
aresetn : IN STD_LOGIC;
|
||||
aclk : IN STD_LOGIC;
|
||||
aclken : IN STD_LOGIC;
|
||||
s_axis_data_tvalid : IN STD_LOGIC;
|
||||
s_axis_data_tready : OUT STD_LOGIC;
|
||||
s_axis_data_tlast : IN STD_LOGIC;
|
||||
s_axis_data_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axis_data_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
s_axis_config_tvalid : IN STD_LOGIC;
|
||||
s_axis_config_tready : OUT STD_LOGIC;
|
||||
s_axis_config_tlast : IN STD_LOGIC;
|
||||
s_axis_config_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axis_reload_tvalid : IN STD_LOGIC;
|
||||
s_axis_reload_tready : OUT STD_LOGIC;
|
||||
s_axis_reload_tlast : IN STD_LOGIC;
|
||||
s_axis_reload_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
m_axis_data_tvalid : OUT STD_LOGIC;
|
||||
m_axis_data_tready : IN STD_LOGIC;
|
||||
m_axis_data_tlast : OUT STD_LOGIC;
|
||||
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
event_s_data_tlast_missing : OUT STD_LOGIC;
|
||||
event_s_data_tlast_unexpected : OUT STD_LOGIC;
|
||||
event_s_data_chanid_incorrect : OUT STD_LOGIC;
|
||||
event_s_config_tlast_missing : OUT STD_LOGIC;
|
||||
event_s_config_tlast_unexpected : OUT STD_LOGIC;
|
||||
event_s_reload_tlast_missing : OUT STD_LOGIC;
|
||||
event_s_reload_tlast_unexpected : OUT STD_LOGIC
|
||||
);
|
||||
END COMPONENT fir_compiler_v7_2_12;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axis_data_tvalid: SIGNAL IS "XIL_INTERFACENAME M_AXIS_DATA, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TDATA";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TREADY";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_data_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_DATA, TDATA_NUM_BYTES 1, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF aclk: SIGNAL IS "XIL_INTERFACENAME aclk_intf, ASSOCIATED_BUSIF S_AXIS_CONFIG:M_AXIS_DATA:S_AXIS_DATA:S_AXIS_RELOAD, ASSOCIATED_RESET aresetn, ASSOCIATED_CLKEN aclken, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
|
||||
BEGIN
|
||||
U0 : fir_compiler_v7_2_12
|
||||
GENERIC MAP (
|
||||
C_XDEVICEFAMILY => "kintex7",
|
||||
C_ELABORATION_DIR => "./",
|
||||
C_COMPONENT_NAME => "GaussFir_1mp5",
|
||||
C_COEF_FILE => "GaussFir_1mp5.mif",
|
||||
C_COEF_FILE_LINES => 160,
|
||||
C_FILTER_TYPE => 2,
|
||||
C_INTERP_RATE => 32,
|
||||
C_DECIM_RATE => 1,
|
||||
C_ZERO_PACKING_FACTOR => 1,
|
||||
C_SYMMETRY => 0,
|
||||
C_NUM_FILTS => 1,
|
||||
C_NUM_TAPS => 129,
|
||||
C_NUM_CHANNELS => 1,
|
||||
C_CHANNEL_PATTERN => "fixed",
|
||||
C_ROUND_MODE => 0,
|
||||
C_COEF_RELOAD => 0,
|
||||
C_NUM_RELOAD_SLOTS => 1,
|
||||
C_COL_MODE => 1,
|
||||
C_COL_PIPE_LEN => 4,
|
||||
C_COL_CONFIG => "5",
|
||||
C_OPTIMIZATION => 0,
|
||||
C_DATA_PATH_WIDTHS => "2",
|
||||
C_DATA_IP_PATH_WIDTHS => "2",
|
||||
C_DATA_PX_PATH_WIDTHS => "2",
|
||||
C_DATA_WIDTH => 2,
|
||||
C_COEF_PATH_WIDTHS => "14",
|
||||
C_COEF_WIDTH => 14,
|
||||
C_DATA_PATH_SRC => "0",
|
||||
C_COEF_PATH_SRC => "0",
|
||||
C_PX_PATH_SRC => "0",
|
||||
C_DATA_PATH_SIGN => "0",
|
||||
C_COEF_PATH_SIGN => "1",
|
||||
C_ACCUM_PATH_WIDTHS => "13",
|
||||
C_OUTPUT_WIDTH => 13,
|
||||
C_OUTPUT_PATH_WIDTHS => "13",
|
||||
C_ACCUM_OP_PATH_WIDTHS => "13",
|
||||
C_EXT_MULT_CNFG => "none",
|
||||
C_DATA_PATH_PSAMP_SRC => "0",
|
||||
C_OP_PATH_PSAMP_SRC => "0",
|
||||
C_NUM_MADDS => 5,
|
||||
C_OPT_MADDS => "none",
|
||||
C_OVERSAMPLING_RATE => 1,
|
||||
C_INPUT_RATE => 32,
|
||||
C_OUTPUT_RATE => 1,
|
||||
C_DATA_MEMTYPE => 0,
|
||||
C_COEF_MEMTYPE => 2,
|
||||
C_IPBUFF_MEMTYPE => 0,
|
||||
C_OPBUFF_MEMTYPE => 0,
|
||||
C_DATAPATH_MEMTYPE => 0,
|
||||
C_MEM_ARRANGEMENT => 2,
|
||||
C_DATA_MEM_PACKING => 0,
|
||||
C_COEF_MEM_PACKING => 0,
|
||||
C_FILTS_PACKED => 0,
|
||||
C_LATENCY => 11,
|
||||
C_HAS_ARESETn => 0,
|
||||
C_HAS_ACLKEN => 0,
|
||||
C_DATA_HAS_TLAST => 0,
|
||||
C_S_DATA_HAS_FIFO => 0,
|
||||
C_S_DATA_HAS_TUSER => 0,
|
||||
C_S_DATA_TDATA_WIDTH => 8,
|
||||
C_S_DATA_TUSER_WIDTH => 1,
|
||||
C_M_DATA_HAS_TREADY => 0,
|
||||
C_M_DATA_HAS_TUSER => 0,
|
||||
C_M_DATA_TDATA_WIDTH => 16,
|
||||
C_M_DATA_TUSER_WIDTH => 1,
|
||||
C_HAS_CONFIG_CHANNEL => 0,
|
||||
C_CONFIG_SYNC_MODE => 0,
|
||||
C_CONFIG_PACKET_SIZE => 0,
|
||||
C_CONFIG_TDATA_WIDTH => 1,
|
||||
C_RELOAD_TDATA_WIDTH => 1
|
||||
)
|
||||
PORT MAP (
|
||||
aresetn => '1',
|
||||
aclk => aclk,
|
||||
aclken => '1',
|
||||
s_axis_data_tvalid => s_axis_data_tvalid,
|
||||
s_axis_data_tready => s_axis_data_tready,
|
||||
s_axis_data_tlast => '0',
|
||||
s_axis_data_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
s_axis_data_tdata => s_axis_data_tdata,
|
||||
s_axis_config_tvalid => '0',
|
||||
s_axis_config_tlast => '0',
|
||||
s_axis_config_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
s_axis_reload_tvalid => '0',
|
||||
s_axis_reload_tlast => '0',
|
||||
s_axis_reload_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
m_axis_data_tvalid => m_axis_data_tvalid,
|
||||
m_axis_data_tready => '1',
|
||||
m_axis_data_tdata => m_axis_data_tdata
|
||||
);
|
||||
END GaussFir_1mp5_arch;
|
||||
@@ -0,0 +1,68 @@
|
||||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
|
||||
// IP Revision: 3
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
data_1p5m your_instance_name (
|
||||
.clka(clka), // input wire clka
|
||||
.ena(ena), // input wire ena
|
||||
.addra(addra), // input wire [10 : 0] addra
|
||||
.douta(douta) // output wire [0 : 0] douta
|
||||
);
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
// You must compile the wrapper file data_1p5m.v when simulating
|
||||
// the core, data_1p5m. When compiling the wrapper file, be sure to
|
||||
// reference the Verilog simulation library.
|
||||
|
||||
@@ -0,0 +1,81 @@
|
||||
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
|
||||
-- IP Revision: 3
|
||||
|
||||
-- The following code must appear in the VHDL architecture header.
|
||||
|
||||
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
|
||||
COMPONENT data_1p5m
|
||||
PORT (
|
||||
clka : IN STD_LOGIC;
|
||||
ena : IN STD_LOGIC;
|
||||
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
|
||||
douta : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
||||
|
||||
-- The following code must appear in the VHDL architecture
|
||||
-- body. Substitute your own instance name and net names.
|
||||
|
||||
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
|
||||
your_instance_name : data_1p5m
|
||||
PORT MAP (
|
||||
clka => clka,
|
||||
ena => ena,
|
||||
addra => addra,
|
||||
douta => douta
|
||||
);
|
||||
-- INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
-- You must compile the wrapper file data_1p5m.vhd when simulating
|
||||
-- the core, data_1p5m. When compiling the wrapper file, be sure to
|
||||
-- reference the VHDL simulation library.
|
||||
|
||||
BIN
Binary file not shown.
BIN
Binary file not shown.
@@ -0,0 +1,23 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Sun Mar 26 00:23:29 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/data_1p5m_stub.v
|
||||
// Design : data_1p5m
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "blk_mem_gen_v8_4_3,Vivado 2019.1.3" *)
|
||||
module data_1p5m(clka, ena, addra, douta)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clka,ena,addra[10:0],douta[0:0]" */;
|
||||
input clka;
|
||||
input ena;
|
||||
input [10:0]addra;
|
||||
output [0:0]douta;
|
||||
endmodule
|
||||
@@ -0,0 +1,33 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Sun Mar 26 00:23:29 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ip/managed_ip_project/managed_ip_project.runs/data_1p5m_synth_1/data_1p5m_stub.vhdl
|
||||
-- Design : data_1p5m
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity data_1p5m is
|
||||
Port (
|
||||
clka : in STD_LOGIC;
|
||||
ena : in STD_LOGIC;
|
||||
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
|
||||
douta : out STD_LOGIC_VECTOR ( 0 to 0 )
|
||||
);
|
||||
|
||||
end data_1p5m;
|
||||
|
||||
architecture stub of data_1p5m is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clka,ena,addra[10:0],douta[0:0]";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_3,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
@@ -0,0 +1,214 @@
|
||||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
|
||||
// IP Revision: 3
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module data_1p5m (
|
||||
clka,
|
||||
ena,
|
||||
addra,
|
||||
douta
|
||||
);
|
||||
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
|
||||
input wire clka;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *)
|
||||
input wire ena;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
|
||||
input wire [10 : 0] addra;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
|
||||
output wire [0 : 0] douta;
|
||||
|
||||
blk_mem_gen_v8_4_3 #(
|
||||
.C_FAMILY("kintex7"),
|
||||
.C_XDEVICEFAMILY("kintex7"),
|
||||
.C_ELABORATION_DIR("./"),
|
||||
.C_INTERFACE_TYPE(0),
|
||||
.C_AXI_TYPE(1),
|
||||
.C_AXI_SLAVE_TYPE(0),
|
||||
.C_USE_BRAM_BLOCK(0),
|
||||
.C_ENABLE_32BIT_ADDRESS(0),
|
||||
.C_CTRL_ECC_ALGO("NONE"),
|
||||
.C_HAS_AXI_ID(0),
|
||||
.C_AXI_ID_WIDTH(4),
|
||||
.C_MEM_TYPE(3),
|
||||
.C_BYTE_SIZE(9),
|
||||
.C_ALGORITHM(1),
|
||||
.C_PRIM_TYPE(1),
|
||||
.C_LOAD_INIT_FILE(1),
|
||||
.C_INIT_FILE_NAME("data_1p5m.mif"),
|
||||
.C_INIT_FILE("data_1p5m.mem"),
|
||||
.C_USE_DEFAULT_DATA(0),
|
||||
.C_DEFAULT_DATA("0"),
|
||||
.C_HAS_RSTA(0),
|
||||
.C_RST_PRIORITY_A("CE"),
|
||||
.C_RSTRAM_A(0),
|
||||
.C_INITA_VAL("0"),
|
||||
.C_HAS_ENA(1),
|
||||
.C_HAS_REGCEA(0),
|
||||
.C_USE_BYTE_WEA(0),
|
||||
.C_WEA_WIDTH(1),
|
||||
.C_WRITE_MODE_A("WRITE_FIRST"),
|
||||
.C_WRITE_WIDTH_A(1),
|
||||
.C_READ_WIDTH_A(1),
|
||||
.C_WRITE_DEPTH_A(2048),
|
||||
.C_READ_DEPTH_A(2048),
|
||||
.C_ADDRA_WIDTH(11),
|
||||
.C_HAS_RSTB(0),
|
||||
.C_RST_PRIORITY_B("CE"),
|
||||
.C_RSTRAM_B(0),
|
||||
.C_INITB_VAL("0"),
|
||||
.C_HAS_ENB(0),
|
||||
.C_HAS_REGCEB(0),
|
||||
.C_USE_BYTE_WEB(0),
|
||||
.C_WEB_WIDTH(1),
|
||||
.C_WRITE_MODE_B("WRITE_FIRST"),
|
||||
.C_WRITE_WIDTH_B(1),
|
||||
.C_READ_WIDTH_B(1),
|
||||
.C_WRITE_DEPTH_B(2048),
|
||||
.C_READ_DEPTH_B(2048),
|
||||
.C_ADDRB_WIDTH(11),
|
||||
.C_HAS_MEM_OUTPUT_REGS_A(1),
|
||||
.C_HAS_MEM_OUTPUT_REGS_B(0),
|
||||
.C_HAS_MUX_OUTPUT_REGS_A(1),
|
||||
.C_HAS_MUX_OUTPUT_REGS_B(0),
|
||||
.C_MUX_PIPELINE_STAGES(0),
|
||||
.C_HAS_SOFTECC_INPUT_REGS_A(0),
|
||||
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
|
||||
.C_USE_SOFTECC(0),
|
||||
.C_USE_ECC(0),
|
||||
.C_EN_ECC_PIPE(0),
|
||||
.C_READ_LATENCY_A(1),
|
||||
.C_READ_LATENCY_B(1),
|
||||
.C_HAS_INJECTERR(0),
|
||||
.C_SIM_COLLISION_CHECK("ALL"),
|
||||
.C_COMMON_CLK(0),
|
||||
.C_DISABLE_WARN_BHV_COLL(0),
|
||||
.C_EN_SLEEP_PIN(0),
|
||||
.C_USE_URAM(0),
|
||||
.C_EN_RDADDRA_CHG(0),
|
||||
.C_EN_RDADDRB_CHG(0),
|
||||
.C_EN_DEEPSLEEP_PIN(0),
|
||||
.C_EN_SHUTDOWN_PIN(0),
|
||||
.C_EN_SAFETY_CKT(0),
|
||||
.C_DISABLE_WARN_BHV_RANGE(0),
|
||||
.C_COUNT_36K_BRAM("0"),
|
||||
.C_COUNT_18K_BRAM("1"),
|
||||
.C_EST_POWER_SUMMARY("Estimated Power for IP : 0.990811 mW")
|
||||
) inst (
|
||||
.clka(clka),
|
||||
.rsta(1'D0),
|
||||
.ena(ena),
|
||||
.regcea(1'D0),
|
||||
.wea(1'B0),
|
||||
.addra(addra),
|
||||
.dina(1'B0),
|
||||
.douta(douta),
|
||||
.clkb(1'D0),
|
||||
.rstb(1'D0),
|
||||
.enb(1'D0),
|
||||
.regceb(1'D0),
|
||||
.web(1'B0),
|
||||
.addrb(11'B0),
|
||||
.dinb(1'B0),
|
||||
.doutb(),
|
||||
.injectsbiterr(1'D0),
|
||||
.injectdbiterr(1'D0),
|
||||
.eccpipece(1'D0),
|
||||
.sbiterr(),
|
||||
.dbiterr(),
|
||||
.rdaddrecc(),
|
||||
.sleep(1'D0),
|
||||
.deepsleep(1'D0),
|
||||
.shutdown(1'D0),
|
||||
.rsta_busy(),
|
||||
.rstb_busy(),
|
||||
.s_aclk(1'H0),
|
||||
.s_aresetn(1'D0),
|
||||
.s_axi_awid(4'B0),
|
||||
.s_axi_awaddr(32'B0),
|
||||
.s_axi_awlen(8'B0),
|
||||
.s_axi_awsize(3'B0),
|
||||
.s_axi_awburst(2'B0),
|
||||
.s_axi_awvalid(1'D0),
|
||||
.s_axi_awready(),
|
||||
.s_axi_wdata(1'B0),
|
||||
.s_axi_wstrb(1'B0),
|
||||
.s_axi_wlast(1'D0),
|
||||
.s_axi_wvalid(1'D0),
|
||||
.s_axi_wready(),
|
||||
.s_axi_bid(),
|
||||
.s_axi_bresp(),
|
||||
.s_axi_bvalid(),
|
||||
.s_axi_bready(1'D0),
|
||||
.s_axi_arid(4'B0),
|
||||
.s_axi_araddr(32'B0),
|
||||
.s_axi_arlen(8'B0),
|
||||
.s_axi_arsize(3'B0),
|
||||
.s_axi_arburst(2'B0),
|
||||
.s_axi_arvalid(1'D0),
|
||||
.s_axi_arready(),
|
||||
.s_axi_rid(),
|
||||
.s_axi_rdata(),
|
||||
.s_axi_rresp(),
|
||||
.s_axi_rlast(),
|
||||
.s_axi_rvalid(),
|
||||
.s_axi_rready(1'D0),
|
||||
.s_axi_injectsbiterr(1'D0),
|
||||
.s_axi_injectdbiterr(1'D0),
|
||||
.s_axi_sbiterr(),
|
||||
.s_axi_dbiterr(),
|
||||
.s_axi_rdaddrecc()
|
||||
);
|
||||
endmodule
|
||||
@@ -0,0 +1,83 @@
|
||||
// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
|
||||
ila_cal your_instance_name (
|
||||
.clk(clk), // input wire clk
|
||||
|
||||
|
||||
.probe0(probe0), // input wire [0:0] probe0
|
||||
.probe1(probe1), // input wire [0:0] probe1
|
||||
.probe2(probe2), // input wire [0:0] probe2
|
||||
.probe3(probe3), // input wire [0:0] probe3
|
||||
.probe4(probe4), // input wire [0:0] probe4
|
||||
.probe5(probe5), // input wire [0:0] probe5
|
||||
.probe6(probe6), // input wire [1:0] probe6
|
||||
.probe7(probe7), // input wire [11:0] probe7
|
||||
.probe8(probe8), // input wire [11:0] probe8
|
||||
.probe9(probe9), // input wire [11:0] probe9
|
||||
.probe10(probe10), // input wire [11:0] probe10
|
||||
.probe11(probe11), // input wire [11:0] probe11
|
||||
.probe12(probe12), // input wire [11:0] probe12
|
||||
.probe13(probe13), // input wire [11:0] probe13
|
||||
.probe14(probe14) // input wire [11:0] probe14
|
||||
);
|
||||
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
// You must compile the wrapper file ila_cal when simulating
|
||||
// the core, ila_cal. When compiling the wrapper file, be sure to
|
||||
// reference the Verilog simulation library.
|
||||
|
||||
|
||||
Binary file not shown.
BIN
Binary file not shown.
@@ -0,0 +1,36 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Sun Mar 26 00:24:39 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ip/managed_ip_project/managed_ip_project.runs/ila_cal_synth_1/ila_cal_stub.v
|
||||
// Design : ila_cal
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "ila,Vivado 2019.1.3" *)
|
||||
module ila_cal(clk, probe0, probe1, probe2, probe3, probe4, probe5,
|
||||
probe6, probe7, probe8, probe9, probe10, probe11, probe12, probe13, probe14)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[0:0],probe1[0:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[1:0],probe7[11:0],probe8[11:0],probe9[11:0],probe10[11:0],probe11[11:0],probe12[11:0],probe13[11:0],probe14[11:0]" */;
|
||||
input clk;
|
||||
input [0:0]probe0;
|
||||
input [0:0]probe1;
|
||||
input [0:0]probe2;
|
||||
input [0:0]probe3;
|
||||
input [0:0]probe4;
|
||||
input [0:0]probe5;
|
||||
input [1:0]probe6;
|
||||
input [11:0]probe7;
|
||||
input [11:0]probe8;
|
||||
input [11:0]probe9;
|
||||
input [11:0]probe10;
|
||||
input [11:0]probe11;
|
||||
input [11:0]probe12;
|
||||
input [11:0]probe13;
|
||||
input [11:0]probe14;
|
||||
endmodule
|
||||
@@ -0,0 +1,45 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Sun Mar 26 00:24:39 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ip/managed_ip_project/managed_ip_project.runs/ila_cal_synth_1/ila_cal_stub.vhdl
|
||||
-- Design : ila_cal
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity ila_cal is
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
probe0 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe1 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe2 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe3 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe4 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe5 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe6 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe7 : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe8 : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe9 : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe10 : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe11 : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe12 : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe13 : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe14 : in STD_LOGIC_VECTOR ( 11 downto 0 )
|
||||
);
|
||||
|
||||
end ila_cal;
|
||||
|
||||
architecture stub of ila_cal is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe0[0:0],probe1[0:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[1:0],probe7[11:0],probe8[11:0],probe9[11:0],probe10[11:0],probe11[11:0],probe12[11:0],probe13[11:0],probe14[11:0]";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
@@ -0,0 +1,90 @@
|
||||
// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
`timescale 1ns / 1ps
|
||||
module ila_cal (
|
||||
clk,
|
||||
|
||||
|
||||
probe0,
|
||||
probe1,
|
||||
probe2,
|
||||
probe3,
|
||||
probe4,
|
||||
probe5,
|
||||
probe6,
|
||||
probe7,
|
||||
probe8,
|
||||
probe9,
|
||||
probe10,
|
||||
probe11,
|
||||
probe12,
|
||||
probe13,
|
||||
probe14
|
||||
);
|
||||
|
||||
input clk;
|
||||
|
||||
|
||||
input [0 : 0] probe0;
|
||||
input [0 : 0] probe1;
|
||||
input [0 : 0] probe2;
|
||||
input [0 : 0] probe3;
|
||||
input [0 : 0] probe4;
|
||||
input [0 : 0] probe5;
|
||||
input [1 : 0] probe6;
|
||||
input [11 : 0] probe7;
|
||||
input [11 : 0] probe8;
|
||||
input [11 : 0] probe9;
|
||||
input [11 : 0] probe10;
|
||||
input [11 : 0] probe11;
|
||||
input [11 : 0] probe12;
|
||||
input [11 : 0] probe13;
|
||||
input [11 : 0] probe14;
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,72 @@
|
||||
// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
|
||||
ila_rx_pre your_instance_name (
|
||||
.clk(clk), // input wire clk
|
||||
|
||||
|
||||
.probe0(probe0), // input wire [0:0] probe0
|
||||
.probe1(probe1), // input wire [0:0] probe1
|
||||
.probe2(probe2), // input wire [0:0] probe2
|
||||
.probe3(probe3) // input wire [0:0] probe3
|
||||
);
|
||||
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
// You must compile the wrapper file ila_rx_pre when simulating
|
||||
// the core, ila_rx_pre. When compiling the wrapper file, be sure to
|
||||
// reference the Verilog simulation library.
|
||||
|
||||
|
||||
BIN
Binary file not shown.
BIN
Binary file not shown.
@@ -0,0 +1,24 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Sun Mar 26 00:24:02 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ip/managed_ip_project/managed_ip_project.runs/ila_rx_pre_synth_1/ila_rx_pre_stub.v
|
||||
// Design : ila_rx_pre
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "ila,Vivado 2019.1.3" *)
|
||||
module ila_rx_pre(clk, probe0, probe1, probe2, probe3)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[0:0],probe1[0:0],probe2[0:0],probe3[0:0]" */;
|
||||
input clk;
|
||||
input [0:0]probe0;
|
||||
input [0:0]probe1;
|
||||
input [0:0]probe2;
|
||||
input [0:0]probe3;
|
||||
endmodule
|
||||
@@ -0,0 +1,34 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Sun Mar 26 00:24:02 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ip/managed_ip_project/managed_ip_project.runs/ila_rx_pre_synth_1/ila_rx_pre_stub.vhdl
|
||||
-- Design : ila_rx_pre
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity ila_rx_pre is
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
probe0 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe1 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe2 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe3 : in STD_LOGIC_VECTOR ( 0 to 0 )
|
||||
);
|
||||
|
||||
end ila_rx_pre;
|
||||
|
||||
architecture stub of ila_rx_pre is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe0[0:0],probe1[0:0],probe2[0:0],probe3[0:0]";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
@@ -0,0 +1,68 @@
|
||||
// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
`timescale 1ns / 1ps
|
||||
module ila_rx_pre (
|
||||
clk,
|
||||
|
||||
|
||||
probe0,
|
||||
probe1,
|
||||
probe2,
|
||||
probe3
|
||||
);
|
||||
|
||||
input clk;
|
||||
|
||||
|
||||
input [0 : 0] probe0;
|
||||
input [0 : 0] probe1;
|
||||
input [0 : 0] probe2;
|
||||
input [0 : 0] probe3;
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,62 @@
|
||||
// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
`timescale 1ns / 1ps
|
||||
module vio_cal (
|
||||
clk,
|
||||
probe_in0,probe_in1,probe_in2
|
||||
|
||||
);
|
||||
|
||||
input clk;
|
||||
input [4 : 0] probe_in0;
|
||||
input [15 : 0] probe_in1;
|
||||
input [15 : 0] probe_in2;
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,68 @@
|
||||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
// IP VLNV: xilinx.com:ip:vio:3.0
|
||||
// IP Revision: 20
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
vio_cal your_instance_name (
|
||||
.clk(clk), // input wire clk
|
||||
.probe_in0(probe_in0), // input wire [4 : 0] probe_in0
|
||||
.probe_in1(probe_in1), // input wire [15 : 0] probe_in1
|
||||
.probe_in2(probe_in2) // input wire [15 : 0] probe_in2
|
||||
);
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
// You must compile the wrapper file vio_cal.v when simulating
|
||||
// the core, vio_cal. When compiling the wrapper file, be sure to
|
||||
// reference the Verilog simulation library.
|
||||
|
||||
@@ -0,0 +1,81 @@
|
||||
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:vio:3.0
|
||||
-- IP Revision: 20
|
||||
|
||||
-- The following code must appear in the VHDL architecture header.
|
||||
|
||||
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
|
||||
COMPONENT vio_cal
|
||||
PORT (
|
||||
clk : IN STD_LOGIC;
|
||||
probe_in0 : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
|
||||
probe_in1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
probe_in2 : IN STD_LOGIC_VECTOR(15 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
||||
|
||||
-- The following code must appear in the VHDL architecture
|
||||
-- body. Substitute your own instance name and net names.
|
||||
|
||||
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
|
||||
your_instance_name : vio_cal
|
||||
PORT MAP (
|
||||
clk => clk,
|
||||
probe_in0 => probe_in0,
|
||||
probe_in1 => probe_in1,
|
||||
probe_in2 => probe_in2
|
||||
);
|
||||
-- INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
-- You must compile the wrapper file vio_cal.vhd when simulating
|
||||
-- the core, vio_cal. When compiling the wrapper file, be sure to
|
||||
-- reference the VHDL simulation library.
|
||||
|
||||
Binary file not shown.
BIN
Binary file not shown.
@@ -0,0 +1,23 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Sun Mar 26 00:23:24 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ip/managed_ip_project/managed_ip_project.runs/vio_cal_synth_1/vio_cal_stub.v
|
||||
// Design : vio_cal
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "vio,Vivado 2019.1.3" *)
|
||||
module vio_cal(clk, probe_in0, probe_in1, probe_in2)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[4:0],probe_in1[15:0],probe_in2[15:0]" */;
|
||||
input clk;
|
||||
input [4:0]probe_in0;
|
||||
input [15:0]probe_in1;
|
||||
input [15:0]probe_in2;
|
||||
endmodule
|
||||
@@ -0,0 +1,33 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Sun Mar 26 00:23:24 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ip/managed_ip_project/managed_ip_project.runs/vio_cal_synth_1/vio_cal_stub.vhdl
|
||||
-- Design : vio_cal
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity vio_cal is
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
probe_in0 : in STD_LOGIC_VECTOR ( 4 downto 0 );
|
||||
probe_in1 : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe_in2 : in STD_LOGIC_VECTOR ( 15 downto 0 )
|
||||
);
|
||||
|
||||
end vio_cal;
|
||||
|
||||
architecture stub of vio_cal is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[4:0],probe_in1[15:0],probe_in2[15:0]";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
@@ -0,0 +1,61 @@
|
||||
// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
`timescale 1ns / 1ps
|
||||
module vio_clk_ld_rd (
|
||||
clk,
|
||||
probe_in0,probe_in1
|
||||
|
||||
);
|
||||
|
||||
input clk;
|
||||
input [0 : 0] probe_in0;
|
||||
input [0 : 0] probe_in1;
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,67 @@
|
||||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
// IP VLNV: xilinx.com:ip:vio:3.0
|
||||
// IP Revision: 20
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
vio_clk_ld_rd your_instance_name (
|
||||
.clk(clk), // input wire clk
|
||||
.probe_in0(probe_in0), // input wire [0 : 0] probe_in0
|
||||
.probe_in1(probe_in1) // input wire [0 : 0] probe_in1
|
||||
);
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
// You must compile the wrapper file vio_clk_ld_rd.v when simulating
|
||||
// the core, vio_clk_ld_rd. When compiling the wrapper file, be sure to
|
||||
// reference the Verilog simulation library.
|
||||
|
||||
@@ -0,0 +1,79 @@
|
||||
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:vio:3.0
|
||||
-- IP Revision: 20
|
||||
|
||||
-- The following code must appear in the VHDL architecture header.
|
||||
|
||||
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
|
||||
COMPONENT vio_clk_ld_rd
|
||||
PORT (
|
||||
clk : IN STD_LOGIC;
|
||||
probe_in0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe_in1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
||||
|
||||
-- The following code must appear in the VHDL architecture
|
||||
-- body. Substitute your own instance name and net names.
|
||||
|
||||
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
|
||||
your_instance_name : vio_clk_ld_rd
|
||||
PORT MAP (
|
||||
clk => clk,
|
||||
probe_in0 => probe_in0,
|
||||
probe_in1 => probe_in1
|
||||
);
|
||||
-- INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
-- You must compile the wrapper file vio_clk_ld_rd.vhd when simulating
|
||||
-- the core, vio_clk_ld_rd. When compiling the wrapper file, be sure to
|
||||
-- reference the VHDL simulation library.
|
||||
|
||||
BIN
Binary file not shown.
LFS
BIN
Binary file not shown.
+22
@@ -0,0 +1,22 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Sun Mar 26 00:23:25 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ip/managed_ip_project/managed_ip_project.runs/vio_clk_ld_rd_synth_1/vio_clk_ld_rd_stub.v
|
||||
// Design : vio_clk_ld_rd
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "vio,Vivado 2019.1.3" *)
|
||||
module vio_clk_ld_rd(clk, probe_in0, probe_in1)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[0:0],probe_in1[0:0]" */;
|
||||
input clk;
|
||||
input [0:0]probe_in0;
|
||||
input [0:0]probe_in1;
|
||||
endmodule
|
||||
+32
@@ -0,0 +1,32 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Sun Mar 26 00:23:25 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ip/managed_ip_project/managed_ip_project.runs/vio_clk_ld_rd_synth_1/vio_clk_ld_rd_stub.vhdl
|
||||
-- Design : vio_clk_ld_rd
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity vio_clk_ld_rd is
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
probe_in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_in1 : in STD_LOGIC_VECTOR ( 0 to 0 )
|
||||
);
|
||||
|
||||
end vio_clk_ld_rd;
|
||||
|
||||
architecture stub of vio_clk_ld_rd is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[0:0],probe_in1[0:0]";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
+68
@@ -0,0 +1,68 @@
|
||||
// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
`timescale 1ns / 1ps
|
||||
module vio_manual_ctrl (
|
||||
clk,
|
||||
|
||||
probe_out0,
|
||||
probe_out1,
|
||||
probe_out2,
|
||||
probe_out3,
|
||||
probe_out4
|
||||
);
|
||||
|
||||
input clk;
|
||||
|
||||
output reg [2 : 0] probe_out0 = 'h2 ;
|
||||
output reg [0 : 0] probe_out1 = 'h0 ;
|
||||
output reg [31 : 0] probe_out2 = 'h00000000 ;
|
||||
output reg [1 : 0] probe_out3 = 'h3 ;
|
||||
output reg [3 : 0] probe_out4 = 'h0 ;
|
||||
|
||||
|
||||
endmodule
|
||||
+70
@@ -0,0 +1,70 @@
|
||||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
// IP VLNV: xilinx.com:ip:vio:3.0
|
||||
// IP Revision: 20
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
vio_manual_ctrl your_instance_name (
|
||||
.clk(clk), // input wire clk
|
||||
.probe_out0(probe_out0), // output wire [2 : 0] probe_out0
|
||||
.probe_out1(probe_out1), // output wire [0 : 0] probe_out1
|
||||
.probe_out2(probe_out2), // output wire [31 : 0] probe_out2
|
||||
.probe_out3(probe_out3), // output wire [1 : 0] probe_out3
|
||||
.probe_out4(probe_out4) // output wire [3 : 0] probe_out4
|
||||
);
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
// You must compile the wrapper file vio_manual_ctrl.v when simulating
|
||||
// the core, vio_manual_ctrl. When compiling the wrapper file, be sure to
|
||||
// reference the Verilog simulation library.
|
||||
|
||||
+85
@@ -0,0 +1,85 @@
|
||||
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:vio:3.0
|
||||
-- IP Revision: 20
|
||||
|
||||
-- The following code must appear in the VHDL architecture header.
|
||||
|
||||
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
|
||||
COMPONENT vio_manual_ctrl
|
||||
PORT (
|
||||
clk : IN STD_LOGIC;
|
||||
probe_out0 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
probe_out1 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe_out2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
probe_out3 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe_out4 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
||||
|
||||
-- The following code must appear in the VHDL architecture
|
||||
-- body. Substitute your own instance name and net names.
|
||||
|
||||
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
|
||||
your_instance_name : vio_manual_ctrl
|
||||
PORT MAP (
|
||||
clk => clk,
|
||||
probe_out0 => probe_out0,
|
||||
probe_out1 => probe_out1,
|
||||
probe_out2 => probe_out2,
|
||||
probe_out3 => probe_out3,
|
||||
probe_out4 => probe_out4
|
||||
);
|
||||
-- INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
-- You must compile the wrapper file vio_manual_ctrl.vhd when simulating
|
||||
-- the core, vio_manual_ctrl. When compiling the wrapper file, be sure to
|
||||
-- reference the VHDL simulation library.
|
||||
|
||||
LFS
BIN
Binary file not shown.
projects/dl814_k7/dl814_k7_beam/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_sim_netlist.vhdl
LFS
BIN
Binary file not shown.
+26
@@ -0,0 +1,26 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Sun Mar 26 00:30:24 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.v
|
||||
// Design : vio_manual_ctrl
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "vio,Vivado 2019.1.3" *)
|
||||
module vio_manual_ctrl(clk, probe_out0, probe_out1, probe_out2,
|
||||
probe_out3, probe_out4)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk,probe_out0[2:0],probe_out1[0:0],probe_out2[31:0],probe_out3[1:0],probe_out4[3:0]" */;
|
||||
input clk;
|
||||
output [2:0]probe_out0;
|
||||
output [0:0]probe_out1;
|
||||
output [31:0]probe_out2;
|
||||
output [1:0]probe_out3;
|
||||
output [3:0]probe_out4;
|
||||
endmodule
|
||||
+35
@@ -0,0 +1,35 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Sun Mar 26 00:30:24 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.vhdl
|
||||
-- Design : vio_manual_ctrl
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity vio_manual_ctrl is
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
probe_out0 : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out2 : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe_out3 : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe_out4 : out STD_LOGIC_VECTOR ( 3 downto 0 )
|
||||
);
|
||||
|
||||
end vio_manual_ctrl;
|
||||
|
||||
architecture stub of vio_manual_ctrl is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe_out0[2:0],probe_out1[0:0],probe_out2[31:0],probe_out3[1:0],probe_out4[3:0]";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
@@ -0,0 +1,74 @@
|
||||
// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
`timescale 1ns / 1ps
|
||||
module vio_weight (
|
||||
clk,
|
||||
|
||||
probe_out0,
|
||||
probe_out1,
|
||||
probe_out2,
|
||||
probe_out3,
|
||||
probe_out4,
|
||||
probe_out5,
|
||||
probe_out6,
|
||||
probe_out7
|
||||
);
|
||||
|
||||
input clk;
|
||||
|
||||
output reg [15 : 0] probe_out0 = 'h594a ;
|
||||
output reg [15 : 0] probe_out1 = 'h4c42 ;
|
||||
output reg [15 : 0] probe_out2 = 'h4c49 ;
|
||||
output reg [15 : 0] probe_out3 = 'h5945 ;
|
||||
output reg [15 : 0] probe_out4 = 'ha44a ;
|
||||
output reg [15 : 0] probe_out5 = 'h9e85 ;
|
||||
output reg [15 : 0] probe_out6 = 'h617b ;
|
||||
output reg [15 : 0] probe_out7 = 'h5bb6 ;
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,73 @@
|
||||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
// IP VLNV: xilinx.com:ip:vio:3.0
|
||||
// IP Revision: 20
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
vio_weight your_instance_name (
|
||||
.clk(clk), // input wire clk
|
||||
.probe_out0(probe_out0), // output wire [15 : 0] probe_out0
|
||||
.probe_out1(probe_out1), // output wire [15 : 0] probe_out1
|
||||
.probe_out2(probe_out2), // output wire [15 : 0] probe_out2
|
||||
.probe_out3(probe_out3), // output wire [15 : 0] probe_out3
|
||||
.probe_out4(probe_out4), // output wire [15 : 0] probe_out4
|
||||
.probe_out5(probe_out5), // output wire [15 : 0] probe_out5
|
||||
.probe_out6(probe_out6), // output wire [15 : 0] probe_out6
|
||||
.probe_out7(probe_out7) // output wire [15 : 0] probe_out7
|
||||
);
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
// You must compile the wrapper file vio_weight.v when simulating
|
||||
// the core, vio_weight. When compiling the wrapper file, be sure to
|
||||
// reference the Verilog simulation library.
|
||||
|
||||
@@ -0,0 +1,91 @@
|
||||
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:vio:3.0
|
||||
-- IP Revision: 20
|
||||
|
||||
-- The following code must appear in the VHDL architecture header.
|
||||
|
||||
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
|
||||
COMPONENT vio_weight
|
||||
PORT (
|
||||
clk : IN STD_LOGIC;
|
||||
probe_out0 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
probe_out1 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
probe_out2 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
probe_out3 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
probe_out4 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
probe_out5 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
probe_out6 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
probe_out7 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
||||
|
||||
-- The following code must appear in the VHDL architecture
|
||||
-- body. Substitute your own instance name and net names.
|
||||
|
||||
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
|
||||
your_instance_name : vio_weight
|
||||
PORT MAP (
|
||||
clk => clk,
|
||||
probe_out0 => probe_out0,
|
||||
probe_out1 => probe_out1,
|
||||
probe_out2 => probe_out2,
|
||||
probe_out3 => probe_out3,
|
||||
probe_out4 => probe_out4,
|
||||
probe_out5 => probe_out5,
|
||||
probe_out6 => probe_out6,
|
||||
probe_out7 => probe_out7
|
||||
);
|
||||
-- INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
-- You must compile the wrapper file vio_weight.vhd when simulating
|
||||
-- the core, vio_weight. When compiling the wrapper file, be sure to
|
||||
-- reference the VHDL simulation library.
|
||||
|
||||
BIN
Binary file not shown.
BIN
Binary file not shown.
@@ -0,0 +1,29 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Sun Mar 26 00:23:34 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ip/managed_ip_project/managed_ip_project.runs/vio_weight_synth_1/vio_weight_stub.v
|
||||
// Design : vio_weight
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "vio,Vivado 2019.1.3" *)
|
||||
module vio_weight(clk, probe_out0, probe_out1, probe_out2,
|
||||
probe_out3, probe_out4, probe_out5, probe_out6, probe_out7)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk,probe_out0[15:0],probe_out1[15:0],probe_out2[15:0],probe_out3[15:0],probe_out4[15:0],probe_out5[15:0],probe_out6[15:0],probe_out7[15:0]" */;
|
||||
input clk;
|
||||
output [15:0]probe_out0;
|
||||
output [15:0]probe_out1;
|
||||
output [15:0]probe_out2;
|
||||
output [15:0]probe_out3;
|
||||
output [15:0]probe_out4;
|
||||
output [15:0]probe_out5;
|
||||
output [15:0]probe_out6;
|
||||
output [15:0]probe_out7;
|
||||
endmodule
|
||||
@@ -0,0 +1,38 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Sun Mar 26 00:23:34 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/datalink_814/dl814_k7_beam/ip/managed_ip_project/managed_ip_project.runs/vio_weight_synth_1/vio_weight_stub.vhdl
|
||||
-- Design : vio_weight
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity vio_weight is
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
probe_out0 : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe_out1 : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe_out2 : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe_out3 : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe_out4 : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe_out5 : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe_out6 : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe_out7 : out STD_LOGIC_VECTOR ( 15 downto 0 )
|
||||
);
|
||||
|
||||
end vio_weight;
|
||||
|
||||
architecture stub of vio_weight is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe_out0[15:0],probe_out1[15:0],probe_out2[15:0],probe_out3[15:0],probe_out4[15:0],probe_out5[15:0],probe_out6[15:0],probe_out7[15:0]";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
+3821
File diff suppressed because it is too large
Load Diff
+55945
File diff suppressed because it is too large
Load Diff
+2392
File diff suppressed because it is too large
Load Diff
+4522
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
+20
@@ -0,0 +1,20 @@
|
||||
Radix=10;
|
||||
Coefficient_Width=16;
|
||||
CoefData=
|
||||
3
|
||||
19
|
||||
97
|
||||
366
|
||||
1052
|
||||
2321
|
||||
3999
|
||||
5485
|
||||
6082
|
||||
5485
|
||||
3999
|
||||
2321
|
||||
1052
|
||||
366
|
||||
97
|
||||
19
|
||||
3
|
||||
@@ -0,0 +1,20 @@
|
||||
00000003 0 0 0 0 0 0
|
||||
00000013 0 0 0 0 1 0
|
||||
00000061 0 0 0 0 2 0
|
||||
0000016e 0 0 0 0 3 0
|
||||
0000041c 0 1 0 0 4 0
|
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|
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00000000 0 4 0 0 17 0
|
||||
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|
||||
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|
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@@ -0,0 +1,160 @@
|
||||
00000000 0 0 0 0 0 0
|
||||
00000000 0 0 0 0 1 0
|
||||
00000001 0 0 0 0 2 0
|
||||
00000001 0 0 0 0 3 0
|
||||
00000001 0 0 0 0 4 0
|
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00000001 0 0 0 0 5 0
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|
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|
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|
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|
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|
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|
||||
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|
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|
||||
00000008 0 3 0 0 114 0
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
00000002 0 3 0 0 120 0
|
||||
00000002 0 3 0 0 121 0
|
||||
00000002 0 3 0 0 122 0
|
||||
00000001 0 3 0 0 123 0
|
||||
00000001 0 3 0 0 124 0
|
||||
00000001 0 3 0 0 125 0
|
||||
00000001 0 3 0 0 126 0
|
||||
00000000 0 3 0 0 127 0
|
||||
00000000 0 4 0 0 128 0
|
||||
00000000 0 4 0 0 129 0
|
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|
||||
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|
||||
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|
||||
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|
||||
00000000 0 4 0 0 134 0
|
||||
00000000 0 4 0 0 135 0
|
||||
00000000 0 4 0 0 136 0
|
||||
00000000 0 4 0 0 137 0
|
||||
00000000 0 4 0 0 138 0
|
||||
00000000 0 4 0 0 139 0
|
||||
00000000 0 4 0 0 140 0
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
00000000 0 4 0 0 157 0
|
||||
00000000 0 4 0 0 158 0
|
||||
00000000 0 4 0 0 159 0
|
||||
+132
@@ -0,0 +1,132 @@
|
||||
Radix=10;
|
||||
Coefficient_Width=16;
|
||||
CoefData=
|
||||
0
|
||||
0
|
||||
1
|
||||
1
|
||||
1
|
||||
1
|
||||
2
|
||||
2
|
||||
2
|
||||
3
|
||||
4
|
||||
5
|
||||
6
|
||||
7
|
||||
8
|
||||
10
|
||||
12
|
||||
14
|
||||
17
|
||||
21
|
||||
24
|
||||
29
|
||||
34
|
||||
39
|
||||
46
|
||||
53
|
||||
61
|
||||
70
|
||||
80
|
||||
91
|
||||
104
|
||||
117
|
||||
132
|
||||
147
|
||||
164
|
||||
182
|
||||
202
|
||||
222
|
||||
244
|
||||
267
|
||||
290
|
||||
315
|
||||
340
|
||||
366
|
||||
392
|
||||
419
|
||||
446
|
||||
473
|
||||
500
|
||||
526
|
||||
552
|
||||
577
|
||||
602
|
||||
625
|
||||
647
|
||||
667
|
||||
686
|
||||
702
|
||||
717
|
||||
730
|
||||
741
|
||||
749
|
||||
755
|
||||
759
|
||||
760
|
||||
759
|
||||
755
|
||||
749
|
||||
741
|
||||
730
|
||||
717
|
||||
702
|
||||
686
|
||||
667
|
||||
647
|
||||
625
|
||||
602
|
||||
577
|
||||
552
|
||||
526
|
||||
500
|
||||
473
|
||||
446
|
||||
419
|
||||
392
|
||||
366
|
||||
340
|
||||
315
|
||||
290
|
||||
267
|
||||
244
|
||||
222
|
||||
202
|
||||
182
|
||||
164
|
||||
147
|
||||
132
|
||||
117
|
||||
104
|
||||
91
|
||||
80
|
||||
70
|
||||
61
|
||||
53
|
||||
46
|
||||
39
|
||||
34
|
||||
29
|
||||
24
|
||||
21
|
||||
17
|
||||
14
|
||||
12
|
||||
10
|
||||
8
|
||||
7
|
||||
6
|
||||
5
|
||||
4
|
||||
3
|
||||
2
|
||||
2
|
||||
2
|
||||
1
|
||||
1
|
||||
1
|
||||
1
|
||||
0
|
||||
0
|
||||
+8194
File diff suppressed because it is too large
Load Diff
+2051
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
+83
@@ -0,0 +1,83 @@
|
||||
################################################################################
|
||||
# Vivado (TM) v2019.1.3 (64-bit)
|
||||
#
|
||||
# README.txt: Please read the sections below to understand the steps required
|
||||
# to simulate the design for a simulator, the directory structure
|
||||
# and the generated exported files.
|
||||
#
|
||||
################################################################################
|
||||
|
||||
1. Simulate Design
|
||||
|
||||
To simulate design, cd to the simulator directory and execute the script.
|
||||
|
||||
For example:-
|
||||
|
||||
% cd questa
|
||||
% ./top.sh
|
||||
|
||||
The export simulation flow requires the Xilinx pre-compiled simulation library
|
||||
components for the target simulator. These components are referred using the
|
||||
'-lib_map_path' switch. If this switch is specified, then the export simulation
|
||||
will automatically set this library path in the generated script and update,
|
||||
copy the simulator setup file(s) in the exported directory.
|
||||
|
||||
If '-lib_map_path' is not specified, then the pre-compiled simulation library
|
||||
information will not be included in the exported scripts and that may cause
|
||||
simulation errors when running this script. Alternatively, you can provide the
|
||||
library information using this switch while executing the generated script.
|
||||
|
||||
For example:-
|
||||
|
||||
% ./top.sh -lib_map_path /design/questa/clibs
|
||||
|
||||
Please refer to the generated script header 'Prerequisite' section for more details.
|
||||
|
||||
2. Directory Structure
|
||||
|
||||
By default, if the -directory switch is not specified, export_simulation will
|
||||
create the following directory structure:-
|
||||
|
||||
<current_working_directory>/export_sim/<simulator>
|
||||
|
||||
For example, if the current working directory is /tmp/test, export_simulation
|
||||
will create the following directory path:-
|
||||
|
||||
/tmp/test/export_sim/questa
|
||||
|
||||
If -directory switch is specified, export_simulation will create a simulator
|
||||
sub-directory under the specified directory path.
|
||||
|
||||
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
|
||||
command will create the following directory:-
|
||||
|
||||
/tmp/test/my_test_area/func_sim/questa
|
||||
|
||||
By default, if -simulator is not specified, export_simulation will create a
|
||||
simulator sub-directory for each simulator and export the files for each simulator
|
||||
in this sub-directory respectively.
|
||||
|
||||
IMPORTANT: Please note that the simulation library path must be specified manually
|
||||
in the generated script for the respective simulator. Please refer to the generated
|
||||
script header 'Prerequisite' section for more details.
|
||||
|
||||
3. Exported script and files
|
||||
|
||||
Export simulation will create the driver shell script, setup files and copy the
|
||||
design sources in the output directory path.
|
||||
|
||||
By default, when the -script_name switch is not specified, export_simulation will
|
||||
create the following script name:-
|
||||
|
||||
<simulation_top>.sh (Unix)
|
||||
When exporting the files for an IP using the -of_objects switch, export_simulation
|
||||
will create the following script name:-
|
||||
|
||||
<ip-name>.sh (Unix)
|
||||
Export simulation will create the setup files for the target simulator specified
|
||||
with the -simulator switch.
|
||||
|
||||
For example, if the target simulator is "ies", export_simulation will create the
|
||||
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
|
||||
file.
|
||||
|
||||
+8192
File diff suppressed because it is too large
Load Diff
+152
@@ -0,0 +1,152 @@
|
||||
#!/bin/bash -f
|
||||
#*********************************************************************************************************
|
||||
# Vivado (TM) v2019.1.3 (64-bit)
|
||||
#
|
||||
# Filename : COSLUT_10_16bit.sh
|
||||
# Simulator : Aldec Active-HDL Simulator
|
||||
# Description : Simulation script for compiling, elaborating and verifying the project source files.
|
||||
# The script will automatically create the design libraries sub-directories in the run
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Thu Apr 13 10:57:34 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
# usage: COSLUT_10_16bit.sh [-help]
|
||||
# usage: COSLUT_10_16bit.sh [-lib_map_path]
|
||||
# usage: COSLUT_10_16bit.sh [-noclean_files]
|
||||
# usage: COSLUT_10_16bit.sh [-reset_run]
|
||||
#
|
||||
# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
|
||||
# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
|
||||
# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
|
||||
# that points to these libraries and rerun export_simulation. For more information about this switch please
|
||||
# type 'export_simulation -help' in the Tcl shell.
|
||||
#
|
||||
# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
|
||||
# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
|
||||
# executing this script. Please type 'COSLUT_10_16bit.sh -help' for more information.
|
||||
#
|
||||
# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
|
||||
#
|
||||
#*********************************************************************************************************
|
||||
|
||||
|
||||
# Script info
|
||||
echo -e "COSLUT_10_16bit.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
|
||||
|
||||
# Main steps
|
||||
run()
|
||||
{
|
||||
check_args $# $1
|
||||
setup $1 $2
|
||||
compile
|
||||
simulate
|
||||
}
|
||||
|
||||
# RUN_STEP: <compile>
|
||||
compile()
|
||||
{
|
||||
# Compile design files
|
||||
source compile.do 2>&1 | tee -a compile.log
|
||||
|
||||
}
|
||||
|
||||
# RUN_STEP: <simulate>
|
||||
simulate()
|
||||
{
|
||||
runvsimsa -l simulate.log -do "do {simulate.do}"
|
||||
}
|
||||
|
||||
# STEP: setup
|
||||
setup()
|
||||
{
|
||||
case $1 in
|
||||
"-lib_map_path" )
|
||||
if [[ ($2 == "") ]]; then
|
||||
echo -e "ERROR: Simulation library directory path not specified (type \"./COSLUT_10_16bit.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
map_setup_file $2
|
||||
;;
|
||||
"-reset_run" )
|
||||
reset_run
|
||||
echo -e "INFO: Simulation run files deleted.\n"
|
||||
exit 0
|
||||
;;
|
||||
"-noclean_files" )
|
||||
# do not remove previous data
|
||||
;;
|
||||
* )
|
||||
map_setup_file $2
|
||||
esac
|
||||
|
||||
# Add any setup/initialization commands here:-
|
||||
|
||||
# <user specific commands>
|
||||
|
||||
}
|
||||
|
||||
# Map library.cfg file
|
||||
map_setup_file()
|
||||
{
|
||||
file="library.cfg"
|
||||
lib_map_path=""
|
||||
if [[ ($1 != "") ]]; then
|
||||
lib_map_path="$1"
|
||||
fi
|
||||
if [[ ($lib_map_path != "") ]]; then
|
||||
src_file="$lib_map_path/$file"
|
||||
if [[ -e $src_file ]]; then
|
||||
vmap -link $lib_map_path
|
||||
fi
|
||||
fi
|
||||
}
|
||||
|
||||
# Delete generated data from the previous run
|
||||
reset_run()
|
||||
{
|
||||
files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl)
|
||||
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
|
||||
file="${files_to_remove[i]}"
|
||||
if [[ -e $file ]]; then
|
||||
rm -rf $file
|
||||
fi
|
||||
done
|
||||
}
|
||||
|
||||
# Check command line arguments
|
||||
check_args()
|
||||
{
|
||||
if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
|
||||
echo -e "ERROR: Unknown option specified '$2' (type \"./COSLUT_10_16bit.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
|
||||
if [[ ($2 == "-help" || $2 == "-h") ]]; then
|
||||
usage
|
||||
fi
|
||||
}
|
||||
|
||||
# Script usage
|
||||
usage()
|
||||
{
|
||||
msg="Usage: COSLUT_10_16bit.sh [-help]\n\
|
||||
Usage: COSLUT_10_16bit.sh [-lib_map_path]\n\
|
||||
Usage: COSLUT_10_16bit.sh [-reset_run]\n\
|
||||
Usage: COSLUT_10_16bit.sh [-noclean_files]\n\n\
|
||||
[-help] -- Print help information for this script\n\n\
|
||||
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
|
||||
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
|
||||
[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
|
||||
from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
|
||||
-noclean_files switch.\n\n\
|
||||
[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
|
||||
echo -e $msg
|
||||
exit 1
|
||||
}
|
||||
|
||||
# Launch script
|
||||
run $1 $2
|
||||
+49
@@ -0,0 +1,49 @@
|
||||
################################################################################
|
||||
# Vivado (TM) v2019.1.3 (64-bit)
|
||||
#
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Thu Apr 13 10:57:34 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
1. How to run the generated simulation script:-
|
||||
|
||||
From the shell prompt in the current directory, issue the following command:-
|
||||
|
||||
./COSLUT_10_16bit.sh
|
||||
|
||||
This command will launch the 'compile', 'elaborate' and 'simulate' functions
|
||||
implemented in the script file for the 3-step flow. These functions are called
|
||||
from the main 'run' function in the script file.
|
||||
|
||||
The 'run' function first executes the 'setup' function, the purpose of which is to
|
||||
create simulator specific setup files, create design library mappings and library
|
||||
directories and copy 'glbl.v' from the Vivado software install location into the
|
||||
current directory.
|
||||
|
||||
The 'setup' function is also used for removing the simulator generated data in
|
||||
order to reset the current directory to the original state when export_simulation
|
||||
was launched from Vivado. This generated data can be removed by specifying the
|
||||
'-reset_run' switch to the './COSLUT_10_16bit.sh' script.
|
||||
|
||||
./COSLUT_10_16bit.sh -reset_run
|
||||
|
||||
To keep the generated data from the previous run but regenerate the setup files and
|
||||
library directories, use the '-noclean_files' switch.
|
||||
|
||||
./COSLUT_10_16bit.sh -noclean_files
|
||||
|
||||
For more information on the script, please type './COSLUT_10_16bit.sh -help'.
|
||||
|
||||
2. Additional design information files:-
|
||||
|
||||
export_simulation generates following additional file that can be used for fetching
|
||||
the design files information or for integrating with external custom scripts.
|
||||
|
||||
Name : file_info.txt
|
||||
Purpose: This file contains detail design file information based on the compile order
|
||||
when export_simulation was executed from Vivado. The file contains information
|
||||
about the file type, name, whether it is part of the IP, associated library
|
||||
and the file path information.
|
||||
+27
@@ -0,0 +1,27 @@
|
||||
vlib work
|
||||
vlib activehdl
|
||||
|
||||
vlib activehdl/xil_defaultlib
|
||||
vlib activehdl/xpm
|
||||
vlib activehdl/blk_mem_gen_v8_4_3
|
||||
|
||||
vmap xil_defaultlib activehdl/xil_defaultlib
|
||||
vmap xpm activehdl/xpm
|
||||
vmap blk_mem_gen_v8_4_3 activehdl/blk_mem_gen_v8_4_3
|
||||
|
||||
vlog -work xil_defaultlib -sv2k12 \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
|
||||
vcom -work xpm -93 \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
|
||||
vlog -work blk_mem_gen_v8_4_3 -v2k5 \
|
||||
"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
|
||||
|
||||
vlog -work xil_defaultlib -v2k5 \
|
||||
"../../../ip/COSLUT_10_16bit/sim/COSLUT_10_16bit.v" \
|
||||
|
||||
vlog -work xil_defaultlib \
|
||||
"glbl.v"
|
||||
|
||||
+8194
File diff suppressed because it is too large
Load Diff
+6
@@ -0,0 +1,6 @@
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
||||
blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
|
||||
COSLUT_10_16bit.v,verilog,xil_defaultlib,../../../ip/COSLUT_10_16bit/sim/COSLUT_10_16bit.v,
|
||||
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||
+71
@@ -0,0 +1,71 @@
|
||||
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
+17
@@ -0,0 +1,17 @@
|
||||
onbreak {quit -force}
|
||||
onerror {quit -force}
|
||||
|
||||
asim -t 1ps +access +r +m+COSLUT_10_16bit -L xil_defaultlib -L xpm -L blk_mem_gen_v8_4_3 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.COSLUT_10_16bit xil_defaultlib.glbl
|
||||
|
||||
do {wave.do}
|
||||
|
||||
view wave
|
||||
view structure
|
||||
|
||||
do {COSLUT_10_16bit.udo}
|
||||
|
||||
run -all
|
||||
|
||||
endsim
|
||||
|
||||
quit -force
|
||||
+2
@@ -0,0 +1,2 @@
|
||||
add wave *
|
||||
add wave /glbl/GSR
|
||||
+8192
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Reference in New Issue
Block a user