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first commit after restructuring
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The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.
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+99
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|
||||
// file: ad9361_clk_gen_cmos_1t1r.v
|
||||
//
|
||||
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// User entered comments
|
||||
//----------------------------------------------------------------------------
|
||||
// None
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Output Output Phase Duty Cycle Pk-to-Pk Phase
|
||||
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
|
||||
//----------------------------------------------------------------------------
|
||||
// clk_out1____48.000______0.000______50.0______176.382____161.578
|
||||
// clk_out2____96.000______0.000______50.0______148.620____161.578
|
||||
// clk_out3___144.000______0.000______50.0______137.385____161.578
|
||||
// clk_out4___192.000______0.000______50.0______131.258____161.578
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Input Clock Freq (MHz) Input Jitter (UI)
|
||||
//----------------------------------------------------------------------------
|
||||
// __primary______________48____________0.010
|
||||
|
||||
`timescale 1ps/1ps
|
||||
|
||||
(* CORE_GENERATION_INFO = "ad9361_clk_gen_cmos_1t1r,clk_wiz_v6_0_3_0_0,{component_name=ad9361_clk_gen_cmos_1t1r,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=4,clkin1_period=20.833,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
|
||||
|
||||
module ad9361_clk_gen_cmos_1t1r
|
||||
(
|
||||
// Clock out ports
|
||||
output clk_out1,
|
||||
output clk_out2,
|
||||
output clk_out3,
|
||||
output clk_out4,
|
||||
// Status and control signals
|
||||
output locked,
|
||||
// Clock in ports
|
||||
input clk_in1
|
||||
);
|
||||
|
||||
ad9361_clk_gen_cmos_1t1r_clk_wiz inst
|
||||
(
|
||||
// Clock out ports
|
||||
.clk_out1(clk_out1),
|
||||
.clk_out2(clk_out2),
|
||||
.clk_out3(clk_out3),
|
||||
.clk_out4(clk_out4),
|
||||
// Status and control signals
|
||||
.locked(locked),
|
||||
// Clock in ports
|
||||
.clk_in1(clk_in1)
|
||||
);
|
||||
|
||||
endmodule
|
||||
+85
@@ -0,0 +1,85 @@
|
||||
|
||||
//
|
||||
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// User entered comments
|
||||
//----------------------------------------------------------------------------
|
||||
// None
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Output Output Phase Duty Cycle Pk-to-Pk Phase
|
||||
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
|
||||
//----------------------------------------------------------------------------
|
||||
// clk_out1____48.000______0.000______50.0______176.382____161.578
|
||||
// clk_out2____96.000______0.000______50.0______148.620____161.578
|
||||
// clk_out3___144.000______0.000______50.0______137.385____161.578
|
||||
// clk_out4___192.000______0.000______50.0______131.258____161.578
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Input Clock Freq (MHz) Input Jitter (UI)
|
||||
//----------------------------------------------------------------------------
|
||||
// __primary______________48____________0.010
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
|
||||
ad9361_clk_gen_cmos_1t1r instance_name
|
||||
(
|
||||
// Clock out ports
|
||||
.clk_out1(clk_out1), // output clk_out1
|
||||
.clk_out2(clk_out2), // output clk_out2
|
||||
.clk_out3(clk_out3), // output clk_out3
|
||||
.clk_out4(clk_out4), // output clk_out4
|
||||
// Status and control signals
|
||||
.locked(locked), // output locked
|
||||
// Clock in ports
|
||||
.clk_in1(clk_in1)); // input clk_in1
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
+228
@@ -0,0 +1,228 @@
|
||||
|
||||
// file: ad9361_clk_gen_cmos_1t1r.v
|
||||
//
|
||||
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// User entered comments
|
||||
//----------------------------------------------------------------------------
|
||||
// None
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Output Output Phase Duty Cycle Pk-to-Pk Phase
|
||||
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
|
||||
//----------------------------------------------------------------------------
|
||||
// clk_out1____48.000______0.000______50.0______176.382____161.578
|
||||
// clk_out2____96.000______0.000______50.0______148.620____161.578
|
||||
// clk_out3___144.000______0.000______50.0______137.385____161.578
|
||||
// clk_out4___192.000______0.000______50.0______131.258____161.578
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Input Clock Freq (MHz) Input Jitter (UI)
|
||||
//----------------------------------------------------------------------------
|
||||
// __primary______________48____________0.010
|
||||
|
||||
`timescale 1ps/1ps
|
||||
|
||||
module ad9361_clk_gen_cmos_1t1r_clk_wiz
|
||||
|
||||
(// Clock in ports
|
||||
// Clock out ports
|
||||
output clk_out1,
|
||||
output clk_out2,
|
||||
output clk_out3,
|
||||
output clk_out4,
|
||||
// Status and control signals
|
||||
output locked,
|
||||
input clk_in1
|
||||
);
|
||||
// Input buffering
|
||||
//------------------------------------
|
||||
wire clk_in1_ad9361_clk_gen_cmos_1t1r;
|
||||
wire clk_in2_ad9361_clk_gen_cmos_1t1r;
|
||||
IBUF clkin1_ibufg
|
||||
(.O (clk_in1_ad9361_clk_gen_cmos_1t1r),
|
||||
.I (clk_in1));
|
||||
|
||||
|
||||
|
||||
|
||||
// Clocking PRIMITIVE
|
||||
//------------------------------------
|
||||
|
||||
// Instantiation of the MMCM PRIMITIVE
|
||||
// * Unused inputs are tied off
|
||||
// * Unused outputs are labeled unused
|
||||
|
||||
wire clk_out1_ad9361_clk_gen_cmos_1t1r;
|
||||
wire clk_out2_ad9361_clk_gen_cmos_1t1r;
|
||||
wire clk_out3_ad9361_clk_gen_cmos_1t1r;
|
||||
wire clk_out4_ad9361_clk_gen_cmos_1t1r;
|
||||
wire clk_out5_ad9361_clk_gen_cmos_1t1r;
|
||||
wire clk_out6_ad9361_clk_gen_cmos_1t1r;
|
||||
wire clk_out7_ad9361_clk_gen_cmos_1t1r;
|
||||
|
||||
wire [15:0] do_unused;
|
||||
wire drdy_unused;
|
||||
wire psdone_unused;
|
||||
wire locked_int;
|
||||
wire clkfbout_ad9361_clk_gen_cmos_1t1r;
|
||||
wire clkfbout_buf_ad9361_clk_gen_cmos_1t1r;
|
||||
wire clkfboutb_unused;
|
||||
wire clkout0b_unused;
|
||||
wire clkout1b_unused;
|
||||
wire clkout2b_unused;
|
||||
wire clkout3b_unused;
|
||||
wire clkout4_unused;
|
||||
wire clkout5_unused;
|
||||
wire clkout6_unused;
|
||||
wire clkfbstopped_unused;
|
||||
wire clkinstopped_unused;
|
||||
|
||||
MMCME2_ADV
|
||||
#(.BANDWIDTH ("OPTIMIZED"),
|
||||
.CLKOUT4_CASCADE ("FALSE"),
|
||||
.COMPENSATION ("ZHOLD"),
|
||||
.STARTUP_WAIT ("FALSE"),
|
||||
.DIVCLK_DIVIDE (1),
|
||||
.CLKFBOUT_MULT_F (24.000),
|
||||
.CLKFBOUT_PHASE (0.000),
|
||||
.CLKFBOUT_USE_FINE_PS ("FALSE"),
|
||||
.CLKOUT0_DIVIDE_F (24.000),
|
||||
.CLKOUT0_PHASE (0.000),
|
||||
.CLKOUT0_DUTY_CYCLE (0.500),
|
||||
.CLKOUT0_USE_FINE_PS ("FALSE"),
|
||||
.CLKOUT1_DIVIDE (12),
|
||||
.CLKOUT1_PHASE (0.000),
|
||||
.CLKOUT1_DUTY_CYCLE (0.500),
|
||||
.CLKOUT1_USE_FINE_PS ("FALSE"),
|
||||
.CLKOUT2_DIVIDE (8),
|
||||
.CLKOUT2_PHASE (0.000),
|
||||
.CLKOUT2_DUTY_CYCLE (0.500),
|
||||
.CLKOUT2_USE_FINE_PS ("FALSE"),
|
||||
.CLKOUT3_DIVIDE (6),
|
||||
.CLKOUT3_PHASE (0.000),
|
||||
.CLKOUT3_DUTY_CYCLE (0.500),
|
||||
.CLKOUT3_USE_FINE_PS ("FALSE"),
|
||||
.CLKIN1_PERIOD (20.833))
|
||||
mmcm_adv_inst
|
||||
// Output clocks
|
||||
(
|
||||
.CLKFBOUT (clkfbout_ad9361_clk_gen_cmos_1t1r),
|
||||
.CLKFBOUTB (clkfboutb_unused),
|
||||
.CLKOUT0 (clk_out1_ad9361_clk_gen_cmos_1t1r),
|
||||
.CLKOUT0B (clkout0b_unused),
|
||||
.CLKOUT1 (clk_out2_ad9361_clk_gen_cmos_1t1r),
|
||||
.CLKOUT1B (clkout1b_unused),
|
||||
.CLKOUT2 (clk_out3_ad9361_clk_gen_cmos_1t1r),
|
||||
.CLKOUT2B (clkout2b_unused),
|
||||
.CLKOUT3 (clk_out4_ad9361_clk_gen_cmos_1t1r),
|
||||
.CLKOUT3B (clkout3b_unused),
|
||||
.CLKOUT4 (clkout4_unused),
|
||||
.CLKOUT5 (clkout5_unused),
|
||||
.CLKOUT6 (clkout6_unused),
|
||||
// Input clock control
|
||||
.CLKFBIN (clkfbout_buf_ad9361_clk_gen_cmos_1t1r),
|
||||
.CLKIN1 (clk_in1_ad9361_clk_gen_cmos_1t1r),
|
||||
.CLKIN2 (1'b0),
|
||||
// Tied to always select the primary input clock
|
||||
.CLKINSEL (1'b1),
|
||||
// Ports for dynamic reconfiguration
|
||||
.DADDR (7'h0),
|
||||
.DCLK (1'b0),
|
||||
.DEN (1'b0),
|
||||
.DI (16'h0),
|
||||
.DO (do_unused),
|
||||
.DRDY (drdy_unused),
|
||||
.DWE (1'b0),
|
||||
// Ports for dynamic phase shift
|
||||
.PSCLK (1'b0),
|
||||
.PSEN (1'b0),
|
||||
.PSINCDEC (1'b0),
|
||||
.PSDONE (psdone_unused),
|
||||
// Other control and status signals
|
||||
.LOCKED (locked_int),
|
||||
.CLKINSTOPPED (clkinstopped_unused),
|
||||
.CLKFBSTOPPED (clkfbstopped_unused),
|
||||
.PWRDWN (1'b0),
|
||||
.RST (1'b0));
|
||||
|
||||
assign locked = locked_int;
|
||||
// Clock Monitor clock assigning
|
||||
//--------------------------------------
|
||||
// Output buffering
|
||||
//-----------------------------------
|
||||
|
||||
BUFG clkf_buf
|
||||
(.O (clkfbout_buf_ad9361_clk_gen_cmos_1t1r),
|
||||
.I (clkfbout_ad9361_clk_gen_cmos_1t1r));
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
BUFG clkout1_buf
|
||||
(.O (clk_out1),
|
||||
.I (clk_out1_ad9361_clk_gen_cmos_1t1r));
|
||||
|
||||
|
||||
BUFG clkout2_buf
|
||||
(.O (clk_out2),
|
||||
.I (clk_out2_ad9361_clk_gen_cmos_1t1r));
|
||||
|
||||
BUFG clkout3_buf
|
||||
(.O (clk_out3),
|
||||
.I (clk_out3_ad9361_clk_gen_cmos_1t1r));
|
||||
|
||||
BUFG clkout4_buf
|
||||
(.O (clk_out4),
|
||||
.I (clk_out4_ad9361_clk_gen_cmos_1t1r));
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
BIN
Binary file not shown.
BIN
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+25
@@ -0,0 +1,25 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Thu Apr 13 11:09:35 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/duifei/common_ip/managed_ip_project/managed_ip_project.runs/ad9361_clk_gen_cmos_1t1r_synth_1/ad9361_clk_gen_cmos_1t1r_stub.v
|
||||
// Design : ad9361_clk_gen_cmos_1t1r
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z100ffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
module ad9361_clk_gen_cmos_1t1r(clk_out1, clk_out2, clk_out3, clk_out4, locked,
|
||||
clk_in1)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk_out1,clk_out2,clk_out3,clk_out4,locked,clk_in1" */;
|
||||
output clk_out1;
|
||||
output clk_out2;
|
||||
output clk_out3;
|
||||
output clk_out4;
|
||||
output locked;
|
||||
input clk_in1;
|
||||
endmodule
|
||||
+33
@@ -0,0 +1,33 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Thu Apr 13 11:09:35 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/duifei/common_ip/managed_ip_project/managed_ip_project.runs/ad9361_clk_gen_cmos_1t1r_synth_1/ad9361_clk_gen_cmos_1t1r_stub.vhdl
|
||||
-- Design : ad9361_clk_gen_cmos_1t1r
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z100ffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity ad9361_clk_gen_cmos_1t1r is
|
||||
Port (
|
||||
clk_out1 : out STD_LOGIC;
|
||||
clk_out2 : out STD_LOGIC;
|
||||
clk_out3 : out STD_LOGIC;
|
||||
clk_out4 : out STD_LOGIC;
|
||||
locked : out STD_LOGIC;
|
||||
clk_in1 : in STD_LOGIC
|
||||
);
|
||||
|
||||
end ad9361_clk_gen_cmos_1t1r;
|
||||
|
||||
architecture stub of ad9361_clk_gen_cmos_1t1r is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk_out1,clk_out2,clk_out3,clk_out4,locked,clk_in1";
|
||||
begin
|
||||
end;
|
||||
+99
@@ -0,0 +1,99 @@
|
||||
|
||||
// file: ad9361_clk_gen_cmos_2t2r.v
|
||||
//
|
||||
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// User entered comments
|
||||
//----------------------------------------------------------------------------
|
||||
// None
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Output Output Phase Duty Cycle Pk-to-Pk Phase
|
||||
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
|
||||
//----------------------------------------------------------------------------
|
||||
// clk_out1____48.000______0.000______50.0______139.139_____89.958
|
||||
// clk_out2____96.000______0.000______50.0______120.859_____89.958
|
||||
// clk_out3___144.000______0.000______50.0______112.241_____89.958
|
||||
// clk_out4___192.000______0.000______50.0______106.524_____89.958
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Input Clock Freq (MHz) Input Jitter (UI)
|
||||
//----------------------------------------------------------------------------
|
||||
// __primary______________96____________0.010
|
||||
|
||||
`timescale 1ps/1ps
|
||||
|
||||
(* CORE_GENERATION_INFO = "ad9361_clk_gen_cmos_2t2r,clk_wiz_v6_0_3_0_0,{component_name=ad9361_clk_gen_cmos_2t2r,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=4,clkin1_period=10.417,clkin2_period=10.000,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
|
||||
|
||||
module ad9361_clk_gen_cmos_2t2r
|
||||
(
|
||||
// Clock out ports
|
||||
output clk_out1,
|
||||
output clk_out2,
|
||||
output clk_out3,
|
||||
output clk_out4,
|
||||
// Status and control signals
|
||||
output locked,
|
||||
// Clock in ports
|
||||
input clk_in1
|
||||
);
|
||||
|
||||
ad9361_clk_gen_cmos_2t2r_clk_wiz inst
|
||||
(
|
||||
// Clock out ports
|
||||
.clk_out1(clk_out1),
|
||||
.clk_out2(clk_out2),
|
||||
.clk_out3(clk_out3),
|
||||
.clk_out4(clk_out4),
|
||||
// Status and control signals
|
||||
.locked(locked),
|
||||
// Clock in ports
|
||||
.clk_in1(clk_in1)
|
||||
);
|
||||
|
||||
endmodule
|
||||
+85
@@ -0,0 +1,85 @@
|
||||
|
||||
//
|
||||
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// User entered comments
|
||||
//----------------------------------------------------------------------------
|
||||
// None
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Output Output Phase Duty Cycle Pk-to-Pk Phase
|
||||
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
|
||||
//----------------------------------------------------------------------------
|
||||
// clk_out1____48.000______0.000______50.0______139.139_____89.958
|
||||
// clk_out2____96.000______0.000______50.0______120.859_____89.958
|
||||
// clk_out3___144.000______0.000______50.0______112.241_____89.958
|
||||
// clk_out4___192.000______0.000______50.0______106.524_____89.958
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Input Clock Freq (MHz) Input Jitter (UI)
|
||||
//----------------------------------------------------------------------------
|
||||
// __primary______________96____________0.010
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
|
||||
ad9361_clk_gen_cmos_2t2r instance_name
|
||||
(
|
||||
// Clock out ports
|
||||
.clk_out1(clk_out1), // output clk_out1
|
||||
.clk_out2(clk_out2), // output clk_out2
|
||||
.clk_out3(clk_out3), // output clk_out3
|
||||
.clk_out4(clk_out4), // output clk_out4
|
||||
// Status and control signals
|
||||
.locked(locked), // output locked
|
||||
// Clock in ports
|
||||
.clk_in1(clk_in1)); // input clk_in1
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
+228
@@ -0,0 +1,228 @@
|
||||
|
||||
// file: ad9361_clk_gen_cmos_2t2r.v
|
||||
//
|
||||
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// User entered comments
|
||||
//----------------------------------------------------------------------------
|
||||
// None
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Output Output Phase Duty Cycle Pk-to-Pk Phase
|
||||
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
|
||||
//----------------------------------------------------------------------------
|
||||
// clk_out1____48.000______0.000______50.0______139.139_____89.958
|
||||
// clk_out2____96.000______0.000______50.0______120.859_____89.958
|
||||
// clk_out3___144.000______0.000______50.0______112.241_____89.958
|
||||
// clk_out4___192.000______0.000______50.0______106.524_____89.958
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Input Clock Freq (MHz) Input Jitter (UI)
|
||||
//----------------------------------------------------------------------------
|
||||
// __primary______________96____________0.010
|
||||
|
||||
`timescale 1ps/1ps
|
||||
|
||||
module ad9361_clk_gen_cmos_2t2r_clk_wiz
|
||||
|
||||
(// Clock in ports
|
||||
// Clock out ports
|
||||
output clk_out1,
|
||||
output clk_out2,
|
||||
output clk_out3,
|
||||
output clk_out4,
|
||||
// Status and control signals
|
||||
output locked,
|
||||
input clk_in1
|
||||
);
|
||||
// Input buffering
|
||||
//------------------------------------
|
||||
wire clk_in1_ad9361_clk_gen_cmos_2t2r;
|
||||
wire clk_in2_ad9361_clk_gen_cmos_2t2r;
|
||||
IBUF clkin1_ibufg
|
||||
(.O (clk_in1_ad9361_clk_gen_cmos_2t2r),
|
||||
.I (clk_in1));
|
||||
|
||||
|
||||
|
||||
|
||||
// Clocking PRIMITIVE
|
||||
//------------------------------------
|
||||
|
||||
// Instantiation of the MMCM PRIMITIVE
|
||||
// * Unused inputs are tied off
|
||||
// * Unused outputs are labeled unused
|
||||
|
||||
wire clk_out1_ad9361_clk_gen_cmos_2t2r;
|
||||
wire clk_out2_ad9361_clk_gen_cmos_2t2r;
|
||||
wire clk_out3_ad9361_clk_gen_cmos_2t2r;
|
||||
wire clk_out4_ad9361_clk_gen_cmos_2t2r;
|
||||
wire clk_out5_ad9361_clk_gen_cmos_2t2r;
|
||||
wire clk_out6_ad9361_clk_gen_cmos_2t2r;
|
||||
wire clk_out7_ad9361_clk_gen_cmos_2t2r;
|
||||
|
||||
wire [15:0] do_unused;
|
||||
wire drdy_unused;
|
||||
wire psdone_unused;
|
||||
wire locked_int;
|
||||
wire clkfbout_ad9361_clk_gen_cmos_2t2r;
|
||||
wire clkfbout_buf_ad9361_clk_gen_cmos_2t2r;
|
||||
wire clkfboutb_unused;
|
||||
wire clkout0b_unused;
|
||||
wire clkout1b_unused;
|
||||
wire clkout2b_unused;
|
||||
wire clkout3b_unused;
|
||||
wire clkout4_unused;
|
||||
wire clkout5_unused;
|
||||
wire clkout6_unused;
|
||||
wire clkfbstopped_unused;
|
||||
wire clkinstopped_unused;
|
||||
|
||||
MMCME2_ADV
|
||||
#(.BANDWIDTH ("OPTIMIZED"),
|
||||
.CLKOUT4_CASCADE ("FALSE"),
|
||||
.COMPENSATION ("ZHOLD"),
|
||||
.STARTUP_WAIT ("FALSE"),
|
||||
.DIVCLK_DIVIDE (1),
|
||||
.CLKFBOUT_MULT_F (12.000),
|
||||
.CLKFBOUT_PHASE (0.000),
|
||||
.CLKFBOUT_USE_FINE_PS ("FALSE"),
|
||||
.CLKOUT0_DIVIDE_F (24.000),
|
||||
.CLKOUT0_PHASE (0.000),
|
||||
.CLKOUT0_DUTY_CYCLE (0.500),
|
||||
.CLKOUT0_USE_FINE_PS ("FALSE"),
|
||||
.CLKOUT1_DIVIDE (12),
|
||||
.CLKOUT1_PHASE (0.000),
|
||||
.CLKOUT1_DUTY_CYCLE (0.500),
|
||||
.CLKOUT1_USE_FINE_PS ("FALSE"),
|
||||
.CLKOUT2_DIVIDE (8),
|
||||
.CLKOUT2_PHASE (0.000),
|
||||
.CLKOUT2_DUTY_CYCLE (0.500),
|
||||
.CLKOUT2_USE_FINE_PS ("FALSE"),
|
||||
.CLKOUT3_DIVIDE (6),
|
||||
.CLKOUT3_PHASE (0.000),
|
||||
.CLKOUT3_DUTY_CYCLE (0.500),
|
||||
.CLKOUT3_USE_FINE_PS ("FALSE"),
|
||||
.CLKIN1_PERIOD (10.417))
|
||||
mmcm_adv_inst
|
||||
// Output clocks
|
||||
(
|
||||
.CLKFBOUT (clkfbout_ad9361_clk_gen_cmos_2t2r),
|
||||
.CLKFBOUTB (clkfboutb_unused),
|
||||
.CLKOUT0 (clk_out1_ad9361_clk_gen_cmos_2t2r),
|
||||
.CLKOUT0B (clkout0b_unused),
|
||||
.CLKOUT1 (clk_out2_ad9361_clk_gen_cmos_2t2r),
|
||||
.CLKOUT1B (clkout1b_unused),
|
||||
.CLKOUT2 (clk_out3_ad9361_clk_gen_cmos_2t2r),
|
||||
.CLKOUT2B (clkout2b_unused),
|
||||
.CLKOUT3 (clk_out4_ad9361_clk_gen_cmos_2t2r),
|
||||
.CLKOUT3B (clkout3b_unused),
|
||||
.CLKOUT4 (clkout4_unused),
|
||||
.CLKOUT5 (clkout5_unused),
|
||||
.CLKOUT6 (clkout6_unused),
|
||||
// Input clock control
|
||||
.CLKFBIN (clkfbout_buf_ad9361_clk_gen_cmos_2t2r),
|
||||
.CLKIN1 (clk_in1_ad9361_clk_gen_cmos_2t2r),
|
||||
.CLKIN2 (1'b0),
|
||||
// Tied to always select the primary input clock
|
||||
.CLKINSEL (1'b1),
|
||||
// Ports for dynamic reconfiguration
|
||||
.DADDR (7'h0),
|
||||
.DCLK (1'b0),
|
||||
.DEN (1'b0),
|
||||
.DI (16'h0),
|
||||
.DO (do_unused),
|
||||
.DRDY (drdy_unused),
|
||||
.DWE (1'b0),
|
||||
// Ports for dynamic phase shift
|
||||
.PSCLK (1'b0),
|
||||
.PSEN (1'b0),
|
||||
.PSINCDEC (1'b0),
|
||||
.PSDONE (psdone_unused),
|
||||
// Other control and status signals
|
||||
.LOCKED (locked_int),
|
||||
.CLKINSTOPPED (clkinstopped_unused),
|
||||
.CLKFBSTOPPED (clkfbstopped_unused),
|
||||
.PWRDWN (1'b0),
|
||||
.RST (1'b0));
|
||||
|
||||
assign locked = locked_int;
|
||||
// Clock Monitor clock assigning
|
||||
//--------------------------------------
|
||||
// Output buffering
|
||||
//-----------------------------------
|
||||
|
||||
BUFG clkf_buf
|
||||
(.O (clkfbout_buf_ad9361_clk_gen_cmos_2t2r),
|
||||
.I (clkfbout_ad9361_clk_gen_cmos_2t2r));
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
BUFG clkout1_buf
|
||||
(.O (clk_out1),
|
||||
.I (clk_out1_ad9361_clk_gen_cmos_2t2r));
|
||||
|
||||
|
||||
BUFG clkout2_buf
|
||||
(.O (clk_out2),
|
||||
.I (clk_out2_ad9361_clk_gen_cmos_2t2r));
|
||||
|
||||
BUFG clkout3_buf
|
||||
(.O (clk_out3),
|
||||
.I (clk_out3_ad9361_clk_gen_cmos_2t2r));
|
||||
|
||||
BUFG clkout4_buf
|
||||
(.O (clk_out4),
|
||||
.I (clk_out4_ad9361_clk_gen_cmos_2t2r));
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
BIN
Binary file not shown.
BIN
Binary file not shown.
+25
@@ -0,0 +1,25 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Thu Apr 13 11:09:34 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/duifei/common_ip/managed_ip_project/managed_ip_project.runs/ad9361_clk_gen_cmos_2t2r_synth_1/ad9361_clk_gen_cmos_2t2r_stub.v
|
||||
// Design : ad9361_clk_gen_cmos_2t2r
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z100ffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
module ad9361_clk_gen_cmos_2t2r(clk_out1, clk_out2, clk_out3, clk_out4, locked,
|
||||
clk_in1)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk_out1,clk_out2,clk_out3,clk_out4,locked,clk_in1" */;
|
||||
output clk_out1;
|
||||
output clk_out2;
|
||||
output clk_out3;
|
||||
output clk_out4;
|
||||
output locked;
|
||||
input clk_in1;
|
||||
endmodule
|
||||
+33
@@ -0,0 +1,33 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Thu Apr 13 11:09:34 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/duifei/common_ip/managed_ip_project/managed_ip_project.runs/ad9361_clk_gen_cmos_2t2r_synth_1/ad9361_clk_gen_cmos_2t2r_stub.vhdl
|
||||
-- Design : ad9361_clk_gen_cmos_2t2r
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z100ffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity ad9361_clk_gen_cmos_2t2r is
|
||||
Port (
|
||||
clk_out1 : out STD_LOGIC;
|
||||
clk_out2 : out STD_LOGIC;
|
||||
clk_out3 : out STD_LOGIC;
|
||||
clk_out4 : out STD_LOGIC;
|
||||
locked : out STD_LOGIC;
|
||||
clk_in1 : in STD_LOGIC
|
||||
);
|
||||
|
||||
end ad9361_clk_gen_cmos_2t2r;
|
||||
|
||||
architecture stub of ad9361_clk_gen_cmos_2t2r is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk_out1,clk_out2,clk_out3,clk_out4,locked,clk_in1";
|
||||
begin
|
||||
end;
|
||||
+101
@@ -0,0 +1,101 @@
|
||||
|
||||
// file: ad9361_clk_gen_lvds_2t2r.v
|
||||
//
|
||||
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// User entered comments
|
||||
//----------------------------------------------------------------------------
|
||||
// None
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Output Output Phase Duty Cycle Pk-to-Pk Phase
|
||||
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
|
||||
//----------------------------------------------------------------------------
|
||||
// clk_out1____48.000______0.000______50.0______125.124_____84.729
|
||||
// clk_out2____96.000______0.000______50.0______109.078_____84.729
|
||||
// clk_out3___144.000______0.000______50.0______100.899_____84.729
|
||||
// clk_out4___192.000______0.000______50.0_______95.477_____84.729
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Input Clock Freq (MHz) Input Jitter (UI)
|
||||
//----------------------------------------------------------------------------
|
||||
// __primary_____________192____________0.010
|
||||
|
||||
`timescale 1ps/1ps
|
||||
|
||||
(* CORE_GENERATION_INFO = "ad9361_clk_gen_lvds_2t2r,clk_wiz_v6_0_3_0_0,{component_name=ad9361_clk_gen_lvds_2t2r,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=4,clkin1_period=5.208,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
|
||||
|
||||
module ad9361_clk_gen_lvds_2t2r
|
||||
(
|
||||
// Clock out ports
|
||||
output clk_out1,
|
||||
output clk_out2,
|
||||
output clk_out3,
|
||||
output clk_out4,
|
||||
// Status and control signals
|
||||
output locked,
|
||||
// Clock in ports
|
||||
input clk_in1_p,
|
||||
input clk_in1_n
|
||||
);
|
||||
|
||||
ad9361_clk_gen_lvds_2t2r_clk_wiz inst
|
||||
(
|
||||
// Clock out ports
|
||||
.clk_out1(clk_out1),
|
||||
.clk_out2(clk_out2),
|
||||
.clk_out3(clk_out3),
|
||||
.clk_out4(clk_out4),
|
||||
// Status and control signals
|
||||
.locked(locked),
|
||||
// Clock in ports
|
||||
.clk_in1_p(clk_in1_p),
|
||||
.clk_in1_n(clk_in1_n)
|
||||
);
|
||||
|
||||
endmodule
|
||||
+86
@@ -0,0 +1,86 @@
|
||||
|
||||
//
|
||||
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// User entered comments
|
||||
//----------------------------------------------------------------------------
|
||||
// None
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Output Output Phase Duty Cycle Pk-to-Pk Phase
|
||||
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
|
||||
//----------------------------------------------------------------------------
|
||||
// clk_out1____48.000______0.000______50.0______125.124_____84.729
|
||||
// clk_out2____96.000______0.000______50.0______109.078_____84.729
|
||||
// clk_out3___144.000______0.000______50.0______100.899_____84.729
|
||||
// clk_out4___192.000______0.000______50.0_______95.477_____84.729
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Input Clock Freq (MHz) Input Jitter (UI)
|
||||
//----------------------------------------------------------------------------
|
||||
// __primary_____________192____________0.010
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
|
||||
ad9361_clk_gen_lvds_2t2r instance_name
|
||||
(
|
||||
// Clock out ports
|
||||
.clk_out1(clk_out1), // output clk_out1
|
||||
.clk_out2(clk_out2), // output clk_out2
|
||||
.clk_out3(clk_out3), // output clk_out3
|
||||
.clk_out4(clk_out4), // output clk_out4
|
||||
// Status and control signals
|
||||
.locked(locked), // output locked
|
||||
// Clock in ports
|
||||
.clk_in1_p(clk_in1_p), // input clk_in1_p
|
||||
.clk_in1_n(clk_in1_n)); // input clk_in1_n
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
+230
@@ -0,0 +1,230 @@
|
||||
|
||||
// file: ad9361_clk_gen_lvds_2t2r.v
|
||||
//
|
||||
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// User entered comments
|
||||
//----------------------------------------------------------------------------
|
||||
// None
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Output Output Phase Duty Cycle Pk-to-Pk Phase
|
||||
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
|
||||
//----------------------------------------------------------------------------
|
||||
// clk_out1____48.000______0.000______50.0______125.124_____84.729
|
||||
// clk_out2____96.000______0.000______50.0______109.078_____84.729
|
||||
// clk_out3___144.000______0.000______50.0______100.899_____84.729
|
||||
// clk_out4___192.000______0.000______50.0_______95.477_____84.729
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Input Clock Freq (MHz) Input Jitter (UI)
|
||||
//----------------------------------------------------------------------------
|
||||
// __primary_____________192____________0.010
|
||||
|
||||
`timescale 1ps/1ps
|
||||
|
||||
module ad9361_clk_gen_lvds_2t2r_clk_wiz
|
||||
|
||||
(// Clock in ports
|
||||
// Clock out ports
|
||||
output clk_out1,
|
||||
output clk_out2,
|
||||
output clk_out3,
|
||||
output clk_out4,
|
||||
// Status and control signals
|
||||
output locked,
|
||||
input clk_in1_p,
|
||||
input clk_in1_n
|
||||
);
|
||||
// Input buffering
|
||||
//------------------------------------
|
||||
wire clk_in1_ad9361_clk_gen_lvds_2t2r;
|
||||
wire clk_in2_ad9361_clk_gen_lvds_2t2r;
|
||||
IBUFDS clkin1_ibufgds
|
||||
(.O (clk_in1_ad9361_clk_gen_lvds_2t2r),
|
||||
.I (clk_in1_p),
|
||||
.IB (clk_in1_n));
|
||||
|
||||
|
||||
|
||||
|
||||
// Clocking PRIMITIVE
|
||||
//------------------------------------
|
||||
|
||||
// Instantiation of the MMCM PRIMITIVE
|
||||
// * Unused inputs are tied off
|
||||
// * Unused outputs are labeled unused
|
||||
|
||||
wire clk_out1_ad9361_clk_gen_lvds_2t2r;
|
||||
wire clk_out2_ad9361_clk_gen_lvds_2t2r;
|
||||
wire clk_out3_ad9361_clk_gen_lvds_2t2r;
|
||||
wire clk_out4_ad9361_clk_gen_lvds_2t2r;
|
||||
wire clk_out5_ad9361_clk_gen_lvds_2t2r;
|
||||
wire clk_out6_ad9361_clk_gen_lvds_2t2r;
|
||||
wire clk_out7_ad9361_clk_gen_lvds_2t2r;
|
||||
|
||||
wire [15:0] do_unused;
|
||||
wire drdy_unused;
|
||||
wire psdone_unused;
|
||||
wire locked_int;
|
||||
wire clkfbout_ad9361_clk_gen_lvds_2t2r;
|
||||
wire clkfbout_buf_ad9361_clk_gen_lvds_2t2r;
|
||||
wire clkfboutb_unused;
|
||||
wire clkout0b_unused;
|
||||
wire clkout1b_unused;
|
||||
wire clkout2b_unused;
|
||||
wire clkout3b_unused;
|
||||
wire clkout4_unused;
|
||||
wire clkout5_unused;
|
||||
wire clkout6_unused;
|
||||
wire clkfbstopped_unused;
|
||||
wire clkinstopped_unused;
|
||||
|
||||
MMCME2_ADV
|
||||
#(.BANDWIDTH ("OPTIMIZED"),
|
||||
.CLKOUT4_CASCADE ("FALSE"),
|
||||
.COMPENSATION ("ZHOLD"),
|
||||
.STARTUP_WAIT ("FALSE"),
|
||||
.DIVCLK_DIVIDE (1),
|
||||
.CLKFBOUT_MULT_F (6.000),
|
||||
.CLKFBOUT_PHASE (0.000),
|
||||
.CLKFBOUT_USE_FINE_PS ("FALSE"),
|
||||
.CLKOUT0_DIVIDE_F (24.000),
|
||||
.CLKOUT0_PHASE (0.000),
|
||||
.CLKOUT0_DUTY_CYCLE (0.500),
|
||||
.CLKOUT0_USE_FINE_PS ("FALSE"),
|
||||
.CLKOUT1_DIVIDE (12),
|
||||
.CLKOUT1_PHASE (0.000),
|
||||
.CLKOUT1_DUTY_CYCLE (0.500),
|
||||
.CLKOUT1_USE_FINE_PS ("FALSE"),
|
||||
.CLKOUT2_DIVIDE (8),
|
||||
.CLKOUT2_PHASE (0.000),
|
||||
.CLKOUT2_DUTY_CYCLE (0.500),
|
||||
.CLKOUT2_USE_FINE_PS ("FALSE"),
|
||||
.CLKOUT3_DIVIDE (6),
|
||||
.CLKOUT3_PHASE (0.000),
|
||||
.CLKOUT3_DUTY_CYCLE (0.500),
|
||||
.CLKOUT3_USE_FINE_PS ("FALSE"),
|
||||
.CLKIN1_PERIOD (5.208))
|
||||
mmcm_adv_inst
|
||||
// Output clocks
|
||||
(
|
||||
.CLKFBOUT (clkfbout_ad9361_clk_gen_lvds_2t2r),
|
||||
.CLKFBOUTB (clkfboutb_unused),
|
||||
.CLKOUT0 (clk_out1_ad9361_clk_gen_lvds_2t2r),
|
||||
.CLKOUT0B (clkout0b_unused),
|
||||
.CLKOUT1 (clk_out2_ad9361_clk_gen_lvds_2t2r),
|
||||
.CLKOUT1B (clkout1b_unused),
|
||||
.CLKOUT2 (clk_out3_ad9361_clk_gen_lvds_2t2r),
|
||||
.CLKOUT2B (clkout2b_unused),
|
||||
.CLKOUT3 (clk_out4_ad9361_clk_gen_lvds_2t2r),
|
||||
.CLKOUT3B (clkout3b_unused),
|
||||
.CLKOUT4 (clkout4_unused),
|
||||
.CLKOUT5 (clkout5_unused),
|
||||
.CLKOUT6 (clkout6_unused),
|
||||
// Input clock control
|
||||
.CLKFBIN (clkfbout_buf_ad9361_clk_gen_lvds_2t2r),
|
||||
.CLKIN1 (clk_in1_ad9361_clk_gen_lvds_2t2r),
|
||||
.CLKIN2 (1'b0),
|
||||
// Tied to always select the primary input clock
|
||||
.CLKINSEL (1'b1),
|
||||
// Ports for dynamic reconfiguration
|
||||
.DADDR (7'h0),
|
||||
.DCLK (1'b0),
|
||||
.DEN (1'b0),
|
||||
.DI (16'h0),
|
||||
.DO (do_unused),
|
||||
.DRDY (drdy_unused),
|
||||
.DWE (1'b0),
|
||||
// Ports for dynamic phase shift
|
||||
.PSCLK (1'b0),
|
||||
.PSEN (1'b0),
|
||||
.PSINCDEC (1'b0),
|
||||
.PSDONE (psdone_unused),
|
||||
// Other control and status signals
|
||||
.LOCKED (locked_int),
|
||||
.CLKINSTOPPED (clkinstopped_unused),
|
||||
.CLKFBSTOPPED (clkfbstopped_unused),
|
||||
.PWRDWN (1'b0),
|
||||
.RST (1'b0));
|
||||
|
||||
assign locked = locked_int;
|
||||
// Clock Monitor clock assigning
|
||||
//--------------------------------------
|
||||
// Output buffering
|
||||
//-----------------------------------
|
||||
|
||||
BUFG clkf_buf
|
||||
(.O (clkfbout_buf_ad9361_clk_gen_lvds_2t2r),
|
||||
.I (clkfbout_ad9361_clk_gen_lvds_2t2r));
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
BUFG clkout1_buf
|
||||
(.O (clk_out1),
|
||||
.I (clk_out1_ad9361_clk_gen_lvds_2t2r));
|
||||
|
||||
|
||||
BUFG clkout2_buf
|
||||
(.O (clk_out2),
|
||||
.I (clk_out2_ad9361_clk_gen_lvds_2t2r));
|
||||
|
||||
BUFG clkout3_buf
|
||||
(.O (clk_out3),
|
||||
.I (clk_out3_ad9361_clk_gen_lvds_2t2r));
|
||||
|
||||
BUFG clkout4_buf
|
||||
(.O (clk_out4),
|
||||
.I (clk_out4_ad9361_clk_gen_lvds_2t2r));
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
BIN
Binary file not shown.
BIN
Binary file not shown.
+26
@@ -0,0 +1,26 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Thu Apr 13 11:09:34 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/duifei/common_ip/managed_ip_project/managed_ip_project.runs/ad9361_clk_gen_lvds_2t2r_synth_1/ad9361_clk_gen_lvds_2t2r_stub.v
|
||||
// Design : ad9361_clk_gen_lvds_2t2r
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z100ffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
module ad9361_clk_gen_lvds_2t2r(clk_out1, clk_out2, clk_out3, clk_out4, locked,
|
||||
clk_in1_p, clk_in1_n)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk_out1,clk_out2,clk_out3,clk_out4,locked,clk_in1_p,clk_in1_n" */;
|
||||
output clk_out1;
|
||||
output clk_out2;
|
||||
output clk_out3;
|
||||
output clk_out4;
|
||||
output locked;
|
||||
input clk_in1_p;
|
||||
input clk_in1_n;
|
||||
endmodule
|
||||
+34
@@ -0,0 +1,34 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Thu Apr 13 11:09:34 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/duifei/common_ip/managed_ip_project/managed_ip_project.runs/ad9361_clk_gen_lvds_2t2r_synth_1/ad9361_clk_gen_lvds_2t2r_stub.vhdl
|
||||
-- Design : ad9361_clk_gen_lvds_2t2r
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z100ffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity ad9361_clk_gen_lvds_2t2r is
|
||||
Port (
|
||||
clk_out1 : out STD_LOGIC;
|
||||
clk_out2 : out STD_LOGIC;
|
||||
clk_out3 : out STD_LOGIC;
|
||||
clk_out4 : out STD_LOGIC;
|
||||
locked : out STD_LOGIC;
|
||||
clk_in1_p : in STD_LOGIC;
|
||||
clk_in1_n : in STD_LOGIC
|
||||
);
|
||||
|
||||
end ad9361_clk_gen_lvds_2t2r;
|
||||
|
||||
architecture stub of ad9361_clk_gen_lvds_2t2r is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk_out1,clk_out2,clk_out3,clk_out4,locked,clk_in1_p,clk_in1_n";
|
||||
begin
|
||||
end;
|
||||
@@ -0,0 +1,92 @@
|
||||
|
||||
// file: ant_clk_gen_stg1.v
|
||||
//
|
||||
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// User entered comments
|
||||
//----------------------------------------------------------------------------
|
||||
// None
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Output Output Phase Duty Cycle Pk-to-Pk Phase
|
||||
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
|
||||
//----------------------------------------------------------------------------
|
||||
// clk_out1____96.000______0.000______50.0______168.397____161.614
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Input Clock Freq (MHz) Input Jitter (UI)
|
||||
//----------------------------------------------------------------------------
|
||||
// __primary_____________250____________0.010
|
||||
|
||||
`timescale 1ps/1ps
|
||||
|
||||
(* CORE_GENERATION_INFO = "ant_clk_gen_stg1,clk_wiz_v6_0_3_0_0,{component_name=ant_clk_gen_stg1,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=4.000,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
|
||||
|
||||
module ant_clk_gen_stg1
|
||||
(
|
||||
// Clock out ports
|
||||
output clk_out1,
|
||||
// Status and control signals
|
||||
output locked,
|
||||
// Clock in ports
|
||||
input clk_in1_p,
|
||||
input clk_in1_n
|
||||
);
|
||||
|
||||
ant_clk_gen_stg1_clk_wiz inst
|
||||
(
|
||||
// Clock out ports
|
||||
.clk_out1(clk_out1),
|
||||
// Status and control signals
|
||||
.locked(locked),
|
||||
// Clock in ports
|
||||
.clk_in1_p(clk_in1_p),
|
||||
.clk_in1_n(clk_in1_n)
|
||||
);
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,80 @@
|
||||
|
||||
//
|
||||
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// User entered comments
|
||||
//----------------------------------------------------------------------------
|
||||
// None
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Output Output Phase Duty Cycle Pk-to-Pk Phase
|
||||
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
|
||||
//----------------------------------------------------------------------------
|
||||
// clk_out1____96.000______0.000______50.0______168.397____161.614
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Input Clock Freq (MHz) Input Jitter (UI)
|
||||
//----------------------------------------------------------------------------
|
||||
// __primary_____________250____________0.010
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
|
||||
ant_clk_gen_stg1 instance_name
|
||||
(
|
||||
// Clock out ports
|
||||
.clk_out1(clk_out1), // output clk_out1
|
||||
// Status and control signals
|
||||
.locked(locked), // output locked
|
||||
// Clock in ports
|
||||
.clk_in1_p(clk_in1_p), // input clk_in1_p
|
||||
.clk_in1_n(clk_in1_n)); // input clk_in1_n
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
+203
@@ -0,0 +1,203 @@
|
||||
|
||||
// file: ant_clk_gen_stg1.v
|
||||
//
|
||||
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// User entered comments
|
||||
//----------------------------------------------------------------------------
|
||||
// None
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Output Output Phase Duty Cycle Pk-to-Pk Phase
|
||||
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
|
||||
//----------------------------------------------------------------------------
|
||||
// clk_out1____96.000______0.000______50.0______168.397____161.614
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Input Clock Freq (MHz) Input Jitter (UI)
|
||||
//----------------------------------------------------------------------------
|
||||
// __primary_____________250____________0.010
|
||||
|
||||
`timescale 1ps/1ps
|
||||
|
||||
module ant_clk_gen_stg1_clk_wiz
|
||||
|
||||
(// Clock in ports
|
||||
// Clock out ports
|
||||
output clk_out1,
|
||||
// Status and control signals
|
||||
output locked,
|
||||
input clk_in1_p,
|
||||
input clk_in1_n
|
||||
);
|
||||
// Input buffering
|
||||
//------------------------------------
|
||||
wire clk_in1_ant_clk_gen_stg1;
|
||||
wire clk_in2_ant_clk_gen_stg1;
|
||||
IBUFDS clkin1_ibufgds
|
||||
(.O (clk_in1_ant_clk_gen_stg1),
|
||||
.I (clk_in1_p),
|
||||
.IB (clk_in1_n));
|
||||
|
||||
|
||||
|
||||
|
||||
// Clocking PRIMITIVE
|
||||
//------------------------------------
|
||||
|
||||
// Instantiation of the MMCM PRIMITIVE
|
||||
// * Unused inputs are tied off
|
||||
// * Unused outputs are labeled unused
|
||||
|
||||
wire clk_out1_ant_clk_gen_stg1;
|
||||
wire clk_out2_ant_clk_gen_stg1;
|
||||
wire clk_out3_ant_clk_gen_stg1;
|
||||
wire clk_out4_ant_clk_gen_stg1;
|
||||
wire clk_out5_ant_clk_gen_stg1;
|
||||
wire clk_out6_ant_clk_gen_stg1;
|
||||
wire clk_out7_ant_clk_gen_stg1;
|
||||
|
||||
wire [15:0] do_unused;
|
||||
wire drdy_unused;
|
||||
wire psdone_unused;
|
||||
wire locked_int;
|
||||
wire clkfbout_ant_clk_gen_stg1;
|
||||
wire clkfbout_buf_ant_clk_gen_stg1;
|
||||
wire clkfboutb_unused;
|
||||
wire clkout0b_unused;
|
||||
wire clkout1_unused;
|
||||
wire clkout1b_unused;
|
||||
wire clkout2_unused;
|
||||
wire clkout2b_unused;
|
||||
wire clkout3_unused;
|
||||
wire clkout3b_unused;
|
||||
wire clkout4_unused;
|
||||
wire clkout5_unused;
|
||||
wire clkout6_unused;
|
||||
wire clkfbstopped_unused;
|
||||
wire clkinstopped_unused;
|
||||
|
||||
MMCME2_ADV
|
||||
#(.BANDWIDTH ("OPTIMIZED"),
|
||||
.CLKOUT4_CASCADE ("FALSE"),
|
||||
.COMPENSATION ("ZHOLD"),
|
||||
.STARTUP_WAIT ("FALSE"),
|
||||
.DIVCLK_DIVIDE (5),
|
||||
.CLKFBOUT_MULT_F (18.000),
|
||||
.CLKFBOUT_PHASE (0.000),
|
||||
.CLKFBOUT_USE_FINE_PS ("FALSE"),
|
||||
.CLKOUT0_DIVIDE_F (9.375),
|
||||
.CLKOUT0_PHASE (0.000),
|
||||
.CLKOUT0_DUTY_CYCLE (0.500),
|
||||
.CLKOUT0_USE_FINE_PS ("FALSE"),
|
||||
.CLKIN1_PERIOD (4.000))
|
||||
mmcm_adv_inst
|
||||
// Output clocks
|
||||
(
|
||||
.CLKFBOUT (clkfbout_ant_clk_gen_stg1),
|
||||
.CLKFBOUTB (clkfboutb_unused),
|
||||
.CLKOUT0 (clk_out1_ant_clk_gen_stg1),
|
||||
.CLKOUT0B (clkout0b_unused),
|
||||
.CLKOUT1 (clkout1_unused),
|
||||
.CLKOUT1B (clkout1b_unused),
|
||||
.CLKOUT2 (clkout2_unused),
|
||||
.CLKOUT2B (clkout2b_unused),
|
||||
.CLKOUT3 (clkout3_unused),
|
||||
.CLKOUT3B (clkout3b_unused),
|
||||
.CLKOUT4 (clkout4_unused),
|
||||
.CLKOUT5 (clkout5_unused),
|
||||
.CLKOUT6 (clkout6_unused),
|
||||
// Input clock control
|
||||
.CLKFBIN (clkfbout_buf_ant_clk_gen_stg1),
|
||||
.CLKIN1 (clk_in1_ant_clk_gen_stg1),
|
||||
.CLKIN2 (1'b0),
|
||||
// Tied to always select the primary input clock
|
||||
.CLKINSEL (1'b1),
|
||||
// Ports for dynamic reconfiguration
|
||||
.DADDR (7'h0),
|
||||
.DCLK (1'b0),
|
||||
.DEN (1'b0),
|
||||
.DI (16'h0),
|
||||
.DO (do_unused),
|
||||
.DRDY (drdy_unused),
|
||||
.DWE (1'b0),
|
||||
// Ports for dynamic phase shift
|
||||
.PSCLK (1'b0),
|
||||
.PSEN (1'b0),
|
||||
.PSINCDEC (1'b0),
|
||||
.PSDONE (psdone_unused),
|
||||
// Other control and status signals
|
||||
.LOCKED (locked_int),
|
||||
.CLKINSTOPPED (clkinstopped_unused),
|
||||
.CLKFBSTOPPED (clkfbstopped_unused),
|
||||
.PWRDWN (1'b0),
|
||||
.RST (1'b0));
|
||||
|
||||
assign locked = locked_int;
|
||||
// Clock Monitor clock assigning
|
||||
//--------------------------------------
|
||||
// Output buffering
|
||||
//-----------------------------------
|
||||
|
||||
BUFG clkf_buf
|
||||
(.O (clkfbout_buf_ant_clk_gen_stg1),
|
||||
.I (clkfbout_ant_clk_gen_stg1));
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
BUFG clkout1_buf
|
||||
(.O (clk_out1),
|
||||
.I (clk_out1_ant_clk_gen_stg1));
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
BIN
Binary file not shown.
BIN
Binary file not shown.
@@ -0,0 +1,22 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Thu Apr 13 11:09:37 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/duifei/common_ip/managed_ip_project/managed_ip_project.runs/ant_clk_gen_stg1_synth_1/ant_clk_gen_stg1_stub.v
|
||||
// Design : ant_clk_gen_stg1
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z100ffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
module ant_clk_gen_stg1(clk_out1, locked, clk_in1_p, clk_in1_n)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk_out1,locked,clk_in1_p,clk_in1_n" */;
|
||||
output clk_out1;
|
||||
output locked;
|
||||
input clk_in1_p;
|
||||
input clk_in1_n;
|
||||
endmodule
|
||||
+31
@@ -0,0 +1,31 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Thu Apr 13 11:09:37 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/duifei/common_ip/managed_ip_project/managed_ip_project.runs/ant_clk_gen_stg1_synth_1/ant_clk_gen_stg1_stub.vhdl
|
||||
-- Design : ant_clk_gen_stg1
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z100ffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity ant_clk_gen_stg1 is
|
||||
Port (
|
||||
clk_out1 : out STD_LOGIC;
|
||||
locked : out STD_LOGIC;
|
||||
clk_in1_p : in STD_LOGIC;
|
||||
clk_in1_n : in STD_LOGIC
|
||||
);
|
||||
|
||||
end ant_clk_gen_stg1;
|
||||
|
||||
architecture stub of ant_clk_gen_stg1 is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk_out1,locked,clk_in1_p,clk_in1_n";
|
||||
begin
|
||||
end;
|
||||
@@ -0,0 +1,99 @@
|
||||
|
||||
// file: ant_clk_gen_stg2.v
|
||||
//
|
||||
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// User entered comments
|
||||
//----------------------------------------------------------------------------
|
||||
// None
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Output Output Phase Duty Cycle Pk-to-Pk Phase
|
||||
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
|
||||
//----------------------------------------------------------------------------
|
||||
// clk_out1____96.000______0.000______50.0______136.435____101.715
|
||||
// clk_out2____48.000______0.000______50.0______158.351____101.715
|
||||
// clk_out3____32.000______0.000______50.0______172.426____101.715
|
||||
// clk_out4____19.200______0.000______50.0______190.665____101.715
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Input Clock Freq (MHz) Input Jitter (UI)
|
||||
//----------------------------------------------------------------------------
|
||||
// __primary______________96____________0.010
|
||||
|
||||
`timescale 1ps/1ps
|
||||
|
||||
(* CORE_GENERATION_INFO = "ant_clk_gen_stg2,clk_wiz_v6_0_3_0_0,{component_name=ant_clk_gen_stg2,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=4,clkin1_period=10.417,clkin2_period=10.000,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
|
||||
|
||||
module ant_clk_gen_stg2
|
||||
(
|
||||
// Clock out ports
|
||||
output clk_out1,
|
||||
output clk_out2,
|
||||
output clk_out3,
|
||||
output clk_out4,
|
||||
// Status and control signals
|
||||
output locked,
|
||||
// Clock in ports
|
||||
input clk_in1
|
||||
);
|
||||
|
||||
ant_clk_gen_stg2_clk_wiz inst
|
||||
(
|
||||
// Clock out ports
|
||||
.clk_out1(clk_out1),
|
||||
.clk_out2(clk_out2),
|
||||
.clk_out3(clk_out3),
|
||||
.clk_out4(clk_out4),
|
||||
// Status and control signals
|
||||
.locked(locked),
|
||||
// Clock in ports
|
||||
.clk_in1(clk_in1)
|
||||
);
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,85 @@
|
||||
|
||||
//
|
||||
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// User entered comments
|
||||
//----------------------------------------------------------------------------
|
||||
// None
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Output Output Phase Duty Cycle Pk-to-Pk Phase
|
||||
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
|
||||
//----------------------------------------------------------------------------
|
||||
// clk_out1____96.000______0.000______50.0______136.435____101.715
|
||||
// clk_out2____48.000______0.000______50.0______158.351____101.715
|
||||
// clk_out3____32.000______0.000______50.0______172.426____101.715
|
||||
// clk_out4____19.200______0.000______50.0______190.665____101.715
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Input Clock Freq (MHz) Input Jitter (UI)
|
||||
//----------------------------------------------------------------------------
|
||||
// __primary______________96____________0.010
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
|
||||
ant_clk_gen_stg2 instance_name
|
||||
(
|
||||
// Clock out ports
|
||||
.clk_out1(clk_out1), // output clk_out1
|
||||
.clk_out2(clk_out2), // output clk_out2
|
||||
.clk_out3(clk_out3), // output clk_out3
|
||||
.clk_out4(clk_out4), // output clk_out4
|
||||
// Status and control signals
|
||||
.locked(locked), // output locked
|
||||
// Clock in ports
|
||||
.clk_in1(clk_in1)); // input clk_in1
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
+228
@@ -0,0 +1,228 @@
|
||||
|
||||
// file: ant_clk_gen_stg2.v
|
||||
//
|
||||
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// User entered comments
|
||||
//----------------------------------------------------------------------------
|
||||
// None
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Output Output Phase Duty Cycle Pk-to-Pk Phase
|
||||
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
|
||||
//----------------------------------------------------------------------------
|
||||
// clk_out1____96.000______0.000______50.0______136.435____101.715
|
||||
// clk_out2____48.000______0.000______50.0______158.351____101.715
|
||||
// clk_out3____32.000______0.000______50.0______172.426____101.715
|
||||
// clk_out4____19.200______0.000______50.0______190.665____101.715
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// Input Clock Freq (MHz) Input Jitter (UI)
|
||||
//----------------------------------------------------------------------------
|
||||
// __primary______________96____________0.010
|
||||
|
||||
`timescale 1ps/1ps
|
||||
|
||||
module ant_clk_gen_stg2_clk_wiz
|
||||
|
||||
(// Clock in ports
|
||||
// Clock out ports
|
||||
output clk_out1,
|
||||
output clk_out2,
|
||||
output clk_out3,
|
||||
output clk_out4,
|
||||
// Status and control signals
|
||||
output locked,
|
||||
input clk_in1
|
||||
);
|
||||
// Input buffering
|
||||
//------------------------------------
|
||||
wire clk_in1_ant_clk_gen_stg2;
|
||||
wire clk_in2_ant_clk_gen_stg2;
|
||||
BUFG clkin1_bufg
|
||||
(.O (clk_in1_ant_clk_gen_stg2),
|
||||
.I (clk_in1));
|
||||
|
||||
|
||||
|
||||
|
||||
// Clocking PRIMITIVE
|
||||
//------------------------------------
|
||||
|
||||
// Instantiation of the MMCM PRIMITIVE
|
||||
// * Unused inputs are tied off
|
||||
// * Unused outputs are labeled unused
|
||||
|
||||
wire clk_out1_ant_clk_gen_stg2;
|
||||
wire clk_out2_ant_clk_gen_stg2;
|
||||
wire clk_out3_ant_clk_gen_stg2;
|
||||
wire clk_out4_ant_clk_gen_stg2;
|
||||
wire clk_out5_ant_clk_gen_stg2;
|
||||
wire clk_out6_ant_clk_gen_stg2;
|
||||
wire clk_out7_ant_clk_gen_stg2;
|
||||
|
||||
wire [15:0] do_unused;
|
||||
wire drdy_unused;
|
||||
wire psdone_unused;
|
||||
wire locked_int;
|
||||
wire clkfbout_ant_clk_gen_stg2;
|
||||
wire clkfbout_buf_ant_clk_gen_stg2;
|
||||
wire clkfboutb_unused;
|
||||
wire clkout0b_unused;
|
||||
wire clkout1b_unused;
|
||||
wire clkout2b_unused;
|
||||
wire clkout3b_unused;
|
||||
wire clkout4_unused;
|
||||
wire clkout5_unused;
|
||||
wire clkout6_unused;
|
||||
wire clkfbstopped_unused;
|
||||
wire clkinstopped_unused;
|
||||
|
||||
MMCME2_ADV
|
||||
#(.BANDWIDTH ("OPTIMIZED"),
|
||||
.CLKOUT4_CASCADE ("FALSE"),
|
||||
.COMPENSATION ("ZHOLD"),
|
||||
.STARTUP_WAIT ("FALSE"),
|
||||
.DIVCLK_DIVIDE (1),
|
||||
.CLKFBOUT_MULT_F (10.000),
|
||||
.CLKFBOUT_PHASE (0.000),
|
||||
.CLKFBOUT_USE_FINE_PS ("FALSE"),
|
||||
.CLKOUT0_DIVIDE_F (10.000),
|
||||
.CLKOUT0_PHASE (0.000),
|
||||
.CLKOUT0_DUTY_CYCLE (0.500),
|
||||
.CLKOUT0_USE_FINE_PS ("FALSE"),
|
||||
.CLKOUT1_DIVIDE (20),
|
||||
.CLKOUT1_PHASE (0.000),
|
||||
.CLKOUT1_DUTY_CYCLE (0.500),
|
||||
.CLKOUT1_USE_FINE_PS ("FALSE"),
|
||||
.CLKOUT2_DIVIDE (30),
|
||||
.CLKOUT2_PHASE (0.000),
|
||||
.CLKOUT2_DUTY_CYCLE (0.500),
|
||||
.CLKOUT2_USE_FINE_PS ("FALSE"),
|
||||
.CLKOUT3_DIVIDE (50),
|
||||
.CLKOUT3_PHASE (0.000),
|
||||
.CLKOUT3_DUTY_CYCLE (0.500),
|
||||
.CLKOUT3_USE_FINE_PS ("FALSE"),
|
||||
.CLKIN1_PERIOD (10.417))
|
||||
mmcm_adv_inst
|
||||
// Output clocks
|
||||
(
|
||||
.CLKFBOUT (clkfbout_ant_clk_gen_stg2),
|
||||
.CLKFBOUTB (clkfboutb_unused),
|
||||
.CLKOUT0 (clk_out1_ant_clk_gen_stg2),
|
||||
.CLKOUT0B (clkout0b_unused),
|
||||
.CLKOUT1 (clk_out2_ant_clk_gen_stg2),
|
||||
.CLKOUT1B (clkout1b_unused),
|
||||
.CLKOUT2 (clk_out3_ant_clk_gen_stg2),
|
||||
.CLKOUT2B (clkout2b_unused),
|
||||
.CLKOUT3 (clk_out4_ant_clk_gen_stg2),
|
||||
.CLKOUT3B (clkout3b_unused),
|
||||
.CLKOUT4 (clkout4_unused),
|
||||
.CLKOUT5 (clkout5_unused),
|
||||
.CLKOUT6 (clkout6_unused),
|
||||
// Input clock control
|
||||
.CLKFBIN (clkfbout_buf_ant_clk_gen_stg2),
|
||||
.CLKIN1 (clk_in1_ant_clk_gen_stg2),
|
||||
.CLKIN2 (1'b0),
|
||||
// Tied to always select the primary input clock
|
||||
.CLKINSEL (1'b1),
|
||||
// Ports for dynamic reconfiguration
|
||||
.DADDR (7'h0),
|
||||
.DCLK (1'b0),
|
||||
.DEN (1'b0),
|
||||
.DI (16'h0),
|
||||
.DO (do_unused),
|
||||
.DRDY (drdy_unused),
|
||||
.DWE (1'b0),
|
||||
// Ports for dynamic phase shift
|
||||
.PSCLK (1'b0),
|
||||
.PSEN (1'b0),
|
||||
.PSINCDEC (1'b0),
|
||||
.PSDONE (psdone_unused),
|
||||
// Other control and status signals
|
||||
.LOCKED (locked_int),
|
||||
.CLKINSTOPPED (clkinstopped_unused),
|
||||
.CLKFBSTOPPED (clkfbstopped_unused),
|
||||
.PWRDWN (1'b0),
|
||||
.RST (1'b0));
|
||||
|
||||
assign locked = locked_int;
|
||||
// Clock Monitor clock assigning
|
||||
//--------------------------------------
|
||||
// Output buffering
|
||||
//-----------------------------------
|
||||
|
||||
BUFG clkf_buf
|
||||
(.O (clkfbout_buf_ant_clk_gen_stg2),
|
||||
.I (clkfbout_ant_clk_gen_stg2));
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
BUFG clkout1_buf
|
||||
(.O (clk_out1),
|
||||
.I (clk_out1_ant_clk_gen_stg2));
|
||||
|
||||
|
||||
BUFG clkout2_buf
|
||||
(.O (clk_out2),
|
||||
.I (clk_out2_ant_clk_gen_stg2));
|
||||
|
||||
BUFG clkout3_buf
|
||||
(.O (clk_out3),
|
||||
.I (clk_out3_ant_clk_gen_stg2));
|
||||
|
||||
BUFG clkout4_buf
|
||||
(.O (clk_out4),
|
||||
.I (clk_out4_ant_clk_gen_stg2));
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
BIN
Binary file not shown.
BIN
Binary file not shown.
@@ -0,0 +1,25 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Thu Apr 13 11:09:39 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/duifei/common_ip/managed_ip_project/managed_ip_project.runs/ant_clk_gen_stg2_synth_1/ant_clk_gen_stg2_stub.v
|
||||
// Design : ant_clk_gen_stg2
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z100ffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
module ant_clk_gen_stg2(clk_out1, clk_out2, clk_out3, clk_out4, locked,
|
||||
clk_in1)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk_out1,clk_out2,clk_out3,clk_out4,locked,clk_in1" */;
|
||||
output clk_out1;
|
||||
output clk_out2;
|
||||
output clk_out3;
|
||||
output clk_out4;
|
||||
output locked;
|
||||
input clk_in1;
|
||||
endmodule
|
||||
+33
@@ -0,0 +1,33 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Thu Apr 13 11:09:39 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/duifei/common_ip/managed_ip_project/managed_ip_project.runs/ant_clk_gen_stg2_synth_1/ant_clk_gen_stg2_stub.vhdl
|
||||
-- Design : ant_clk_gen_stg2
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z100ffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity ant_clk_gen_stg2 is
|
||||
Port (
|
||||
clk_out1 : out STD_LOGIC;
|
||||
clk_out2 : out STD_LOGIC;
|
||||
clk_out3 : out STD_LOGIC;
|
||||
clk_out4 : out STD_LOGIC;
|
||||
locked : out STD_LOGIC;
|
||||
clk_in1 : in STD_LOGIC
|
||||
);
|
||||
|
||||
end ant_clk_gen_stg2;
|
||||
|
||||
architecture stub of ant_clk_gen_stg2 is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk_out1,clk_out2,clk_out3,clk_out4,locked,clk_in1";
|
||||
begin
|
||||
end;
|
||||
@@ -0,0 +1,73 @@
|
||||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
// IP VLNV: xilinx.com:ip:fifo_generator:13.2
|
||||
// IP Revision: 4
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
fifo_AntCtrl your_instance_name (
|
||||
.rst(rst), // input wire rst
|
||||
.wr_clk(wr_clk), // input wire wr_clk
|
||||
.rd_clk(rd_clk), // input wire rd_clk
|
||||
.din(din), // input wire [3 : 0] din
|
||||
.wr_en(wr_en), // input wire wr_en
|
||||
.rd_en(rd_en), // input wire rd_en
|
||||
.dout(dout), // output wire [3 : 0] dout
|
||||
.full(full), // output wire full
|
||||
.empty(empty) // output wire empty
|
||||
);
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
// You must compile the wrapper file fifo_AntCtrl.v when simulating
|
||||
// the core, fifo_AntCtrl. When compiling the wrapper file, be sure to
|
||||
// reference the Verilog simulation library.
|
||||
|
||||
@@ -0,0 +1,91 @@
|
||||
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:fifo_generator:13.2
|
||||
-- IP Revision: 4
|
||||
|
||||
-- The following code must appear in the VHDL architecture header.
|
||||
|
||||
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
|
||||
COMPONENT fifo_AntCtrl
|
||||
PORT (
|
||||
rst : IN STD_LOGIC;
|
||||
wr_clk : IN STD_LOGIC;
|
||||
rd_clk : IN STD_LOGIC;
|
||||
din : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
wr_en : IN STD_LOGIC;
|
||||
rd_en : IN STD_LOGIC;
|
||||
dout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
full : OUT STD_LOGIC;
|
||||
empty : OUT STD_LOGIC
|
||||
);
|
||||
END COMPONENT;
|
||||
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
||||
|
||||
-- The following code must appear in the VHDL architecture
|
||||
-- body. Substitute your own instance name and net names.
|
||||
|
||||
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
|
||||
your_instance_name : fifo_AntCtrl
|
||||
PORT MAP (
|
||||
rst => rst,
|
||||
wr_clk => wr_clk,
|
||||
rd_clk => rd_clk,
|
||||
din => din,
|
||||
wr_en => wr_en,
|
||||
rd_en => rd_en,
|
||||
dout => dout,
|
||||
full => full,
|
||||
empty => empty
|
||||
);
|
||||
-- INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
-- You must compile the wrapper file fifo_AntCtrl.vhd when simulating
|
||||
-- the core, fifo_AntCtrl. When compiling the wrapper file, be sure to
|
||||
-- reference the VHDL simulation library.
|
||||
|
||||
BIN
Binary file not shown.
BIN
Binary file not shown.
@@ -0,0 +1,29 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Thu Mar 30 16:42:56 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/fifo_AntCtrl_stub.v
|
||||
// Design : fifo_AntCtrl
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z100ffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "fifo_generator_v13_2_4,Vivado 2019.1.3" *)
|
||||
module fifo_AntCtrl(rst, wr_clk, rd_clk, din, wr_en, rd_en, dout, full,
|
||||
empty)
|
||||
/* synthesis syn_black_box black_box_pad_pin="rst,wr_clk,rd_clk,din[3:0],wr_en,rd_en,dout[3:0],full,empty" */;
|
||||
input rst;
|
||||
input wr_clk;
|
||||
input rd_clk;
|
||||
input [3:0]din;
|
||||
input wr_en;
|
||||
input rd_en;
|
||||
output [3:0]dout;
|
||||
output full;
|
||||
output empty;
|
||||
endmodule
|
||||
@@ -0,0 +1,38 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Thu Mar 30 16:42:56 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/fifo_AntCtrl_stub.vhdl
|
||||
-- Design : fifo_AntCtrl
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z100ffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity fifo_AntCtrl is
|
||||
Port (
|
||||
rst : in STD_LOGIC;
|
||||
wr_clk : in STD_LOGIC;
|
||||
rd_clk : in STD_LOGIC;
|
||||
din : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
wr_en : in STD_LOGIC;
|
||||
rd_en : in STD_LOGIC;
|
||||
dout : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
full : out STD_LOGIC;
|
||||
empty : out STD_LOGIC
|
||||
);
|
||||
|
||||
end fifo_AntCtrl;
|
||||
|
||||
architecture stub of fifo_AntCtrl is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "rst,wr_clk,rd_clk,din[3:0],wr_en,rd_en,dout[3:0],full,empty";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "fifo_generator_v13_2_4,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
@@ -0,0 +1,524 @@
|
||||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:fifo_generator:13.2
|
||||
// IP Revision: 4
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module fifo_AntCtrl (
|
||||
rst,
|
||||
wr_clk,
|
||||
rd_clk,
|
||||
din,
|
||||
wr_en,
|
||||
rd_en,
|
||||
dout,
|
||||
full,
|
||||
empty
|
||||
);
|
||||
|
||||
input wire rst;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME write_clk, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 write_clk CLK" *)
|
||||
input wire wr_clk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME read_clk, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 read_clk CLK" *)
|
||||
input wire rd_clk;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA" *)
|
||||
input wire [3 : 0] din;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN" *)
|
||||
input wire wr_en;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN" *)
|
||||
input wire rd_en;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA" *)
|
||||
output wire [3 : 0] dout;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL" *)
|
||||
output wire full;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY" *)
|
||||
output wire empty;
|
||||
|
||||
fifo_generator_v13_2_4 #(
|
||||
.C_COMMON_CLOCK(0),
|
||||
.C_SELECT_XPM(0),
|
||||
.C_COUNT_TYPE(0),
|
||||
.C_DATA_COUNT_WIDTH(10),
|
||||
.C_DEFAULT_VALUE("BlankString"),
|
||||
.C_DIN_WIDTH(4),
|
||||
.C_DOUT_RST_VAL("0"),
|
||||
.C_DOUT_WIDTH(4),
|
||||
.C_ENABLE_RLOCS(0),
|
||||
.C_FAMILY("zynq"),
|
||||
.C_FULL_FLAGS_RST_VAL(1),
|
||||
.C_HAS_ALMOST_EMPTY(0),
|
||||
.C_HAS_ALMOST_FULL(0),
|
||||
.C_HAS_BACKUP(0),
|
||||
.C_HAS_DATA_COUNT(0),
|
||||
.C_HAS_INT_CLK(0),
|
||||
.C_HAS_MEMINIT_FILE(0),
|
||||
.C_HAS_OVERFLOW(0),
|
||||
.C_HAS_RD_DATA_COUNT(0),
|
||||
.C_HAS_RD_RST(0),
|
||||
.C_HAS_RST(1),
|
||||
.C_HAS_SRST(0),
|
||||
.C_HAS_UNDERFLOW(0),
|
||||
.C_HAS_VALID(0),
|
||||
.C_HAS_WR_ACK(0),
|
||||
.C_HAS_WR_DATA_COUNT(0),
|
||||
.C_HAS_WR_RST(0),
|
||||
.C_IMPLEMENTATION_TYPE(2),
|
||||
.C_INIT_WR_PNTR_VAL(0),
|
||||
.C_MEMORY_TYPE(2),
|
||||
.C_MIF_FILE_NAME("BlankString"),
|
||||
.C_OPTIMIZATION_MODE(0),
|
||||
.C_OVERFLOW_LOW(0),
|
||||
.C_PRELOAD_LATENCY(1),
|
||||
.C_PRELOAD_REGS(0),
|
||||
.C_PRIM_FIFO_TYPE("1kx18"),
|
||||
.C_PROG_EMPTY_THRESH_ASSERT_VAL(2),
|
||||
.C_PROG_EMPTY_THRESH_NEGATE_VAL(3),
|
||||
.C_PROG_EMPTY_TYPE(0),
|
||||
.C_PROG_FULL_THRESH_ASSERT_VAL(1021),
|
||||
.C_PROG_FULL_THRESH_NEGATE_VAL(1020),
|
||||
.C_PROG_FULL_TYPE(0),
|
||||
.C_RD_DATA_COUNT_WIDTH(10),
|
||||
.C_RD_DEPTH(1024),
|
||||
.C_RD_FREQ(1),
|
||||
.C_RD_PNTR_WIDTH(10),
|
||||
.C_UNDERFLOW_LOW(0),
|
||||
.C_USE_DOUT_RST(1),
|
||||
.C_USE_ECC(0),
|
||||
.C_USE_EMBEDDED_REG(0),
|
||||
.C_USE_PIPELINE_REG(0),
|
||||
.C_POWER_SAVING_MODE(0),
|
||||
.C_USE_FIFO16_FLAGS(0),
|
||||
.C_USE_FWFT_DATA_COUNT(0),
|
||||
.C_VALID_LOW(0),
|
||||
.C_WR_ACK_LOW(0),
|
||||
.C_WR_DATA_COUNT_WIDTH(10),
|
||||
.C_WR_DEPTH(1024),
|
||||
.C_WR_FREQ(1),
|
||||
.C_WR_PNTR_WIDTH(10),
|
||||
.C_WR_RESPONSE_LATENCY(1),
|
||||
.C_MSGON_VAL(1),
|
||||
.C_ENABLE_RST_SYNC(1),
|
||||
.C_EN_SAFETY_CKT(0),
|
||||
.C_ERROR_INJECTION_TYPE(0),
|
||||
.C_SYNCHRONIZER_STAGE(2),
|
||||
.C_INTERFACE_TYPE(0),
|
||||
.C_AXI_TYPE(1),
|
||||
.C_HAS_AXI_WR_CHANNEL(1),
|
||||
.C_HAS_AXI_RD_CHANNEL(1),
|
||||
.C_HAS_SLAVE_CE(0),
|
||||
.C_HAS_MASTER_CE(0),
|
||||
.C_ADD_NGC_CONSTRAINT(0),
|
||||
.C_USE_COMMON_OVERFLOW(0),
|
||||
.C_USE_COMMON_UNDERFLOW(0),
|
||||
.C_USE_DEFAULT_SETTINGS(0),
|
||||
.C_AXI_ID_WIDTH(1),
|
||||
.C_AXI_ADDR_WIDTH(32),
|
||||
.C_AXI_DATA_WIDTH(64),
|
||||
.C_AXI_LEN_WIDTH(8),
|
||||
.C_AXI_LOCK_WIDTH(1),
|
||||
.C_HAS_AXI_ID(0),
|
||||
.C_HAS_AXI_AWUSER(0),
|
||||
.C_HAS_AXI_WUSER(0),
|
||||
.C_HAS_AXI_BUSER(0),
|
||||
.C_HAS_AXI_ARUSER(0),
|
||||
.C_HAS_AXI_RUSER(0),
|
||||
.C_AXI_ARUSER_WIDTH(1),
|
||||
.C_AXI_AWUSER_WIDTH(1),
|
||||
.C_AXI_WUSER_WIDTH(1),
|
||||
.C_AXI_BUSER_WIDTH(1),
|
||||
.C_AXI_RUSER_WIDTH(1),
|
||||
.C_HAS_AXIS_TDATA(1),
|
||||
.C_HAS_AXIS_TID(0),
|
||||
.C_HAS_AXIS_TDEST(0),
|
||||
.C_HAS_AXIS_TUSER(1),
|
||||
.C_HAS_AXIS_TREADY(1),
|
||||
.C_HAS_AXIS_TLAST(0),
|
||||
.C_HAS_AXIS_TSTRB(0),
|
||||
.C_HAS_AXIS_TKEEP(0),
|
||||
.C_AXIS_TDATA_WIDTH(8),
|
||||
.C_AXIS_TID_WIDTH(1),
|
||||
.C_AXIS_TDEST_WIDTH(1),
|
||||
.C_AXIS_TUSER_WIDTH(4),
|
||||
.C_AXIS_TSTRB_WIDTH(1),
|
||||
.C_AXIS_TKEEP_WIDTH(1),
|
||||
.C_WACH_TYPE(0),
|
||||
.C_WDCH_TYPE(0),
|
||||
.C_WRCH_TYPE(0),
|
||||
.C_RACH_TYPE(0),
|
||||
.C_RDCH_TYPE(0),
|
||||
.C_AXIS_TYPE(0),
|
||||
.C_IMPLEMENTATION_TYPE_WACH(1),
|
||||
.C_IMPLEMENTATION_TYPE_WDCH(1),
|
||||
.C_IMPLEMENTATION_TYPE_WRCH(1),
|
||||
.C_IMPLEMENTATION_TYPE_RACH(1),
|
||||
.C_IMPLEMENTATION_TYPE_RDCH(1),
|
||||
.C_IMPLEMENTATION_TYPE_AXIS(1),
|
||||
.C_APPLICATION_TYPE_WACH(0),
|
||||
.C_APPLICATION_TYPE_WDCH(0),
|
||||
.C_APPLICATION_TYPE_WRCH(0),
|
||||
.C_APPLICATION_TYPE_RACH(0),
|
||||
.C_APPLICATION_TYPE_RDCH(0),
|
||||
.C_APPLICATION_TYPE_AXIS(0),
|
||||
.C_PRIM_FIFO_TYPE_WACH("512x36"),
|
||||
.C_PRIM_FIFO_TYPE_WDCH("1kx36"),
|
||||
.C_PRIM_FIFO_TYPE_WRCH("512x36"),
|
||||
.C_PRIM_FIFO_TYPE_RACH("512x36"),
|
||||
.C_PRIM_FIFO_TYPE_RDCH("1kx36"),
|
||||
.C_PRIM_FIFO_TYPE_AXIS("1kx18"),
|
||||
.C_USE_ECC_WACH(0),
|
||||
.C_USE_ECC_WDCH(0),
|
||||
.C_USE_ECC_WRCH(0),
|
||||
.C_USE_ECC_RACH(0),
|
||||
.C_USE_ECC_RDCH(0),
|
||||
.C_USE_ECC_AXIS(0),
|
||||
.C_ERROR_INJECTION_TYPE_WACH(0),
|
||||
.C_ERROR_INJECTION_TYPE_WDCH(0),
|
||||
.C_ERROR_INJECTION_TYPE_WRCH(0),
|
||||
.C_ERROR_INJECTION_TYPE_RACH(0),
|
||||
.C_ERROR_INJECTION_TYPE_RDCH(0),
|
||||
.C_ERROR_INJECTION_TYPE_AXIS(0),
|
||||
.C_DIN_WIDTH_WACH(1),
|
||||
.C_DIN_WIDTH_WDCH(64),
|
||||
.C_DIN_WIDTH_WRCH(2),
|
||||
.C_DIN_WIDTH_RACH(32),
|
||||
.C_DIN_WIDTH_RDCH(64),
|
||||
.C_DIN_WIDTH_AXIS(1),
|
||||
.C_WR_DEPTH_WACH(16),
|
||||
.C_WR_DEPTH_WDCH(1024),
|
||||
.C_WR_DEPTH_WRCH(16),
|
||||
.C_WR_DEPTH_RACH(16),
|
||||
.C_WR_DEPTH_RDCH(1024),
|
||||
.C_WR_DEPTH_AXIS(1024),
|
||||
.C_WR_PNTR_WIDTH_WACH(4),
|
||||
.C_WR_PNTR_WIDTH_WDCH(10),
|
||||
.C_WR_PNTR_WIDTH_WRCH(4),
|
||||
.C_WR_PNTR_WIDTH_RACH(4),
|
||||
.C_WR_PNTR_WIDTH_RDCH(10),
|
||||
.C_WR_PNTR_WIDTH_AXIS(10),
|
||||
.C_HAS_DATA_COUNTS_WACH(0),
|
||||
.C_HAS_DATA_COUNTS_WDCH(0),
|
||||
.C_HAS_DATA_COUNTS_WRCH(0),
|
||||
.C_HAS_DATA_COUNTS_RACH(0),
|
||||
.C_HAS_DATA_COUNTS_RDCH(0),
|
||||
.C_HAS_DATA_COUNTS_AXIS(0),
|
||||
.C_HAS_PROG_FLAGS_WACH(0),
|
||||
.C_HAS_PROG_FLAGS_WDCH(0),
|
||||
.C_HAS_PROG_FLAGS_WRCH(0),
|
||||
.C_HAS_PROG_FLAGS_RACH(0),
|
||||
.C_HAS_PROG_FLAGS_RDCH(0),
|
||||
.C_HAS_PROG_FLAGS_AXIS(0),
|
||||
.C_PROG_FULL_TYPE_WACH(0),
|
||||
.C_PROG_FULL_TYPE_WDCH(0),
|
||||
.C_PROG_FULL_TYPE_WRCH(0),
|
||||
.C_PROG_FULL_TYPE_RACH(0),
|
||||
.C_PROG_FULL_TYPE_RDCH(0),
|
||||
.C_PROG_FULL_TYPE_AXIS(0),
|
||||
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
|
||||
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
|
||||
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
|
||||
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
|
||||
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
|
||||
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
|
||||
.C_PROG_EMPTY_TYPE_WACH(0),
|
||||
.C_PROG_EMPTY_TYPE_WDCH(0),
|
||||
.C_PROG_EMPTY_TYPE_WRCH(0),
|
||||
.C_PROG_EMPTY_TYPE_RACH(0),
|
||||
.C_PROG_EMPTY_TYPE_RDCH(0),
|
||||
.C_PROG_EMPTY_TYPE_AXIS(0),
|
||||
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
|
||||
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
|
||||
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
|
||||
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
|
||||
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
|
||||
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
|
||||
.C_REG_SLICE_MODE_WACH(0),
|
||||
.C_REG_SLICE_MODE_WDCH(0),
|
||||
.C_REG_SLICE_MODE_WRCH(0),
|
||||
.C_REG_SLICE_MODE_RACH(0),
|
||||
.C_REG_SLICE_MODE_RDCH(0),
|
||||
.C_REG_SLICE_MODE_AXIS(0)
|
||||
) inst (
|
||||
.backup(1'D0),
|
||||
.backup_marker(1'D0),
|
||||
.clk(1'D0),
|
||||
.rst(rst),
|
||||
.srst(1'D0),
|
||||
.wr_clk(wr_clk),
|
||||
.wr_rst(1'D0),
|
||||
.rd_clk(rd_clk),
|
||||
.rd_rst(1'D0),
|
||||
.din(din),
|
||||
.wr_en(wr_en),
|
||||
.rd_en(rd_en),
|
||||
.prog_empty_thresh(10'B0),
|
||||
.prog_empty_thresh_assert(10'B0),
|
||||
.prog_empty_thresh_negate(10'B0),
|
||||
.prog_full_thresh(10'B0),
|
||||
.prog_full_thresh_assert(10'B0),
|
||||
.prog_full_thresh_negate(10'B0),
|
||||
.int_clk(1'D0),
|
||||
.injectdbiterr(1'D0),
|
||||
.injectsbiterr(1'D0),
|
||||
.sleep(1'D0),
|
||||
.dout(dout),
|
||||
.full(full),
|
||||
.almost_full(),
|
||||
.wr_ack(),
|
||||
.overflow(),
|
||||
.empty(empty),
|
||||
.almost_empty(),
|
||||
.valid(),
|
||||
.underflow(),
|
||||
.data_count(),
|
||||
.rd_data_count(),
|
||||
.wr_data_count(),
|
||||
.prog_full(),
|
||||
.prog_empty(),
|
||||
.sbiterr(),
|
||||
.dbiterr(),
|
||||
.wr_rst_busy(),
|
||||
.rd_rst_busy(),
|
||||
.m_aclk(1'D0),
|
||||
.s_aclk(1'D0),
|
||||
.s_aresetn(1'D0),
|
||||
.m_aclk_en(1'D0),
|
||||
.s_aclk_en(1'D0),
|
||||
.s_axi_awid(1'B0),
|
||||
.s_axi_awaddr(32'B0),
|
||||
.s_axi_awlen(8'B0),
|
||||
.s_axi_awsize(3'B0),
|
||||
.s_axi_awburst(2'B0),
|
||||
.s_axi_awlock(1'B0),
|
||||
.s_axi_awcache(4'B0),
|
||||
.s_axi_awprot(3'B0),
|
||||
.s_axi_awqos(4'B0),
|
||||
.s_axi_awregion(4'B0),
|
||||
.s_axi_awuser(1'B0),
|
||||
.s_axi_awvalid(1'D0),
|
||||
.s_axi_awready(),
|
||||
.s_axi_wid(1'B0),
|
||||
.s_axi_wdata(64'B0),
|
||||
.s_axi_wstrb(8'B0),
|
||||
.s_axi_wlast(1'D0),
|
||||
.s_axi_wuser(1'B0),
|
||||
.s_axi_wvalid(1'D0),
|
||||
.s_axi_wready(),
|
||||
.s_axi_bid(),
|
||||
.s_axi_bresp(),
|
||||
.s_axi_buser(),
|
||||
.s_axi_bvalid(),
|
||||
.s_axi_bready(1'D0),
|
||||
.m_axi_awid(),
|
||||
.m_axi_awaddr(),
|
||||
.m_axi_awlen(),
|
||||
.m_axi_awsize(),
|
||||
.m_axi_awburst(),
|
||||
.m_axi_awlock(),
|
||||
.m_axi_awcache(),
|
||||
.m_axi_awprot(),
|
||||
.m_axi_awqos(),
|
||||
.m_axi_awregion(),
|
||||
.m_axi_awuser(),
|
||||
.m_axi_awvalid(),
|
||||
.m_axi_awready(1'D0),
|
||||
.m_axi_wid(),
|
||||
.m_axi_wdata(),
|
||||
.m_axi_wstrb(),
|
||||
.m_axi_wlast(),
|
||||
.m_axi_wuser(),
|
||||
.m_axi_wvalid(),
|
||||
.m_axi_wready(1'D0),
|
||||
.m_axi_bid(1'B0),
|
||||
.m_axi_bresp(2'B0),
|
||||
.m_axi_buser(1'B0),
|
||||
.m_axi_bvalid(1'D0),
|
||||
.m_axi_bready(),
|
||||
.s_axi_arid(1'B0),
|
||||
.s_axi_araddr(32'B0),
|
||||
.s_axi_arlen(8'B0),
|
||||
.s_axi_arsize(3'B0),
|
||||
.s_axi_arburst(2'B0),
|
||||
.s_axi_arlock(1'B0),
|
||||
.s_axi_arcache(4'B0),
|
||||
.s_axi_arprot(3'B0),
|
||||
.s_axi_arqos(4'B0),
|
||||
.s_axi_arregion(4'B0),
|
||||
.s_axi_aruser(1'B0),
|
||||
.s_axi_arvalid(1'D0),
|
||||
.s_axi_arready(),
|
||||
.s_axi_rid(),
|
||||
.s_axi_rdata(),
|
||||
.s_axi_rresp(),
|
||||
.s_axi_rlast(),
|
||||
.s_axi_ruser(),
|
||||
.s_axi_rvalid(),
|
||||
.s_axi_rready(1'D0),
|
||||
.m_axi_arid(),
|
||||
.m_axi_araddr(),
|
||||
.m_axi_arlen(),
|
||||
.m_axi_arsize(),
|
||||
.m_axi_arburst(),
|
||||
.m_axi_arlock(),
|
||||
.m_axi_arcache(),
|
||||
.m_axi_arprot(),
|
||||
.m_axi_arqos(),
|
||||
.m_axi_arregion(),
|
||||
.m_axi_aruser(),
|
||||
.m_axi_arvalid(),
|
||||
.m_axi_arready(1'D0),
|
||||
.m_axi_rid(1'B0),
|
||||
.m_axi_rdata(64'B0),
|
||||
.m_axi_rresp(2'B0),
|
||||
.m_axi_rlast(1'D0),
|
||||
.m_axi_ruser(1'B0),
|
||||
.m_axi_rvalid(1'D0),
|
||||
.m_axi_rready(),
|
||||
.s_axis_tvalid(1'D0),
|
||||
.s_axis_tready(),
|
||||
.s_axis_tdata(8'B0),
|
||||
.s_axis_tstrb(1'B0),
|
||||
.s_axis_tkeep(1'B0),
|
||||
.s_axis_tlast(1'D0),
|
||||
.s_axis_tid(1'B0),
|
||||
.s_axis_tdest(1'B0),
|
||||
.s_axis_tuser(4'B0),
|
||||
.m_axis_tvalid(),
|
||||
.m_axis_tready(1'D0),
|
||||
.m_axis_tdata(),
|
||||
.m_axis_tstrb(),
|
||||
.m_axis_tkeep(),
|
||||
.m_axis_tlast(),
|
||||
.m_axis_tid(),
|
||||
.m_axis_tdest(),
|
||||
.m_axis_tuser(),
|
||||
.axi_aw_injectsbiterr(1'D0),
|
||||
.axi_aw_injectdbiterr(1'D0),
|
||||
.axi_aw_prog_full_thresh(4'B0),
|
||||
.axi_aw_prog_empty_thresh(4'B0),
|
||||
.axi_aw_data_count(),
|
||||
.axi_aw_wr_data_count(),
|
||||
.axi_aw_rd_data_count(),
|
||||
.axi_aw_sbiterr(),
|
||||
.axi_aw_dbiterr(),
|
||||
.axi_aw_overflow(),
|
||||
.axi_aw_underflow(),
|
||||
.axi_aw_prog_full(),
|
||||
.axi_aw_prog_empty(),
|
||||
.axi_w_injectsbiterr(1'D0),
|
||||
.axi_w_injectdbiterr(1'D0),
|
||||
.axi_w_prog_full_thresh(10'B0),
|
||||
.axi_w_prog_empty_thresh(10'B0),
|
||||
.axi_w_data_count(),
|
||||
.axi_w_wr_data_count(),
|
||||
.axi_w_rd_data_count(),
|
||||
.axi_w_sbiterr(),
|
||||
.axi_w_dbiterr(),
|
||||
.axi_w_overflow(),
|
||||
.axi_w_underflow(),
|
||||
.axi_w_prog_full(),
|
||||
.axi_w_prog_empty(),
|
||||
.axi_b_injectsbiterr(1'D0),
|
||||
.axi_b_injectdbiterr(1'D0),
|
||||
.axi_b_prog_full_thresh(4'B0),
|
||||
.axi_b_prog_empty_thresh(4'B0),
|
||||
.axi_b_data_count(),
|
||||
.axi_b_wr_data_count(),
|
||||
.axi_b_rd_data_count(),
|
||||
.axi_b_sbiterr(),
|
||||
.axi_b_dbiterr(),
|
||||
.axi_b_overflow(),
|
||||
.axi_b_underflow(),
|
||||
.axi_b_prog_full(),
|
||||
.axi_b_prog_empty(),
|
||||
.axi_ar_injectsbiterr(1'D0),
|
||||
.axi_ar_injectdbiterr(1'D0),
|
||||
.axi_ar_prog_full_thresh(4'B0),
|
||||
.axi_ar_prog_empty_thresh(4'B0),
|
||||
.axi_ar_data_count(),
|
||||
.axi_ar_wr_data_count(),
|
||||
.axi_ar_rd_data_count(),
|
||||
.axi_ar_sbiterr(),
|
||||
.axi_ar_dbiterr(),
|
||||
.axi_ar_overflow(),
|
||||
.axi_ar_underflow(),
|
||||
.axi_ar_prog_full(),
|
||||
.axi_ar_prog_empty(),
|
||||
.axi_r_injectsbiterr(1'D0),
|
||||
.axi_r_injectdbiterr(1'D0),
|
||||
.axi_r_prog_full_thresh(10'B0),
|
||||
.axi_r_prog_empty_thresh(10'B0),
|
||||
.axi_r_data_count(),
|
||||
.axi_r_wr_data_count(),
|
||||
.axi_r_rd_data_count(),
|
||||
.axi_r_sbiterr(),
|
||||
.axi_r_dbiterr(),
|
||||
.axi_r_overflow(),
|
||||
.axi_r_underflow(),
|
||||
.axi_r_prog_full(),
|
||||
.axi_r_prog_empty(),
|
||||
.axis_injectsbiterr(1'D0),
|
||||
.axis_injectdbiterr(1'D0),
|
||||
.axis_prog_full_thresh(10'B0),
|
||||
.axis_prog_empty_thresh(10'B0),
|
||||
.axis_data_count(),
|
||||
.axis_wr_data_count(),
|
||||
.axis_rd_data_count(),
|
||||
.axis_sbiterr(),
|
||||
.axis_dbiterr(),
|
||||
.axis_overflow(),
|
||||
.axis_underflow(),
|
||||
.axis_prog_full(),
|
||||
.axis_prog_empty()
|
||||
);
|
||||
endmodule
|
||||
@@ -0,0 +1,70 @@
|
||||
// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
|
||||
ila_2x12x1024 your_instance_name (
|
||||
.clk(clk), // input wire clk
|
||||
|
||||
|
||||
.probe0(probe0), // input wire [11:0] probe0
|
||||
.probe1(probe1) // input wire [11:0] probe1
|
||||
);
|
||||
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
// You must compile the wrapper file ila_2x12x1024 when simulating
|
||||
// the core, ila_2x12x1024. When compiling the wrapper file, be sure to
|
||||
// reference the Verilog simulation library.
|
||||
|
||||
|
||||
BIN
Binary file not shown.
BIN
Binary file not shown.
@@ -0,0 +1,22 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Thu Apr 13 11:10:35 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/duifei/common_ip/managed_ip_project/managed_ip_project.runs/ila_2x12x1024_synth_1/ila_2x12x1024_stub.v
|
||||
// Design : ila_2x12x1024
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z100ffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "ila,Vivado 2019.1.3" *)
|
||||
module ila_2x12x1024(clk, probe0, probe1)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[11:0],probe1[11:0]" */;
|
||||
input clk;
|
||||
input [11:0]probe0;
|
||||
input [11:0]probe1;
|
||||
endmodule
|
||||
@@ -0,0 +1,32 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Thu Apr 13 11:10:35 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/duifei/common_ip/managed_ip_project/managed_ip_project.runs/ila_2x12x1024_synth_1/ila_2x12x1024_stub.vhdl
|
||||
-- Design : ila_2x12x1024
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z100ffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity ila_2x12x1024 is
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
probe0 : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe1 : in STD_LOGIC_VECTOR ( 11 downto 0 )
|
||||
);
|
||||
|
||||
end ila_2x12x1024;
|
||||
|
||||
architecture stub of ila_2x12x1024 is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe0[11:0],probe1[11:0]";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
@@ -0,0 +1,64 @@
|
||||
// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
`timescale 1ns / 1ps
|
||||
module ila_2x12x1024 (
|
||||
clk,
|
||||
|
||||
|
||||
probe0,
|
||||
probe1
|
||||
);
|
||||
|
||||
input clk;
|
||||
|
||||
|
||||
input [11 : 0] probe0;
|
||||
input [11 : 0] probe1;
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,70 @@
|
||||
// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
|
||||
ila_2x12x131072 your_instance_name (
|
||||
.clk(clk), // input wire clk
|
||||
|
||||
|
||||
.probe0(probe0), // input wire [11:0] probe0
|
||||
.probe1(probe1) // input wire [11:0] probe1
|
||||
);
|
||||
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
// You must compile the wrapper file ila_2x12x131072 when simulating
|
||||
// the core, ila_2x12x131072. When compiling the wrapper file, be sure to
|
||||
// reference the Verilog simulation library.
|
||||
|
||||
|
||||
BIN
Binary file not shown.
BIN
Binary file not shown.
@@ -0,0 +1,22 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Thu Apr 13 11:11:04 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/duifei/common_ip/managed_ip_project/managed_ip_project.runs/ila_2x12x131072_synth_1/ila_2x12x131072_stub.v
|
||||
// Design : ila_2x12x131072
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z100ffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "ila,Vivado 2019.1.3" *)
|
||||
module ila_2x12x131072(clk, probe0, probe1)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[11:0],probe1[11:0]" */;
|
||||
input clk;
|
||||
input [11:0]probe0;
|
||||
input [11:0]probe1;
|
||||
endmodule
|
||||
@@ -0,0 +1,32 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Thu Apr 13 11:11:04 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/duifei/common_ip/managed_ip_project/managed_ip_project.runs/ila_2x12x131072_synth_1/ila_2x12x131072_stub.vhdl
|
||||
-- Design : ila_2x12x131072
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z100ffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity ila_2x12x131072 is
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
probe0 : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe1 : in STD_LOGIC_VECTOR ( 11 downto 0 )
|
||||
);
|
||||
|
||||
end ila_2x12x131072;
|
||||
|
||||
architecture stub of ila_2x12x131072 is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe0[11:0],probe1[11:0]";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
@@ -0,0 +1,64 @@
|
||||
// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
`timescale 1ns / 1ps
|
||||
module ila_2x12x131072 (
|
||||
clk,
|
||||
|
||||
|
||||
probe0,
|
||||
probe1
|
||||
);
|
||||
|
||||
input clk;
|
||||
|
||||
|
||||
input [11 : 0] probe0;
|
||||
input [11 : 0] probe1;
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,72 @@
|
||||
// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
|
||||
ila_4x12x131072 your_instance_name (
|
||||
.clk(clk), // input wire clk
|
||||
|
||||
|
||||
.probe0(probe0), // input wire [11:0] probe0
|
||||
.probe1(probe1), // input wire [11:0] probe1
|
||||
.probe2(probe2), // input wire [11:0] probe2
|
||||
.probe3(probe3) // input wire [11:0] probe3
|
||||
);
|
||||
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
// You must compile the wrapper file ila_4x12x131072 when simulating
|
||||
// the core, ila_4x12x131072. When compiling the wrapper file, be sure to
|
||||
// reference the Verilog simulation library.
|
||||
|
||||
|
||||
BIN
Binary file not shown.
BIN
Binary file not shown.
@@ -0,0 +1,24 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Thu Apr 13 11:11:27 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/duifei/common_ip/managed_ip_project/managed_ip_project.runs/ila_4x12x131072_synth_1/ila_4x12x131072_stub.v
|
||||
// Design : ila_4x12x131072
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z100ffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "ila,Vivado 2019.1.3" *)
|
||||
module ila_4x12x131072(clk, probe0, probe1, probe2, probe3)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[11:0],probe1[11:0],probe2[11:0],probe3[11:0]" */;
|
||||
input clk;
|
||||
input [11:0]probe0;
|
||||
input [11:0]probe1;
|
||||
input [11:0]probe2;
|
||||
input [11:0]probe3;
|
||||
endmodule
|
||||
@@ -0,0 +1,34 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Thu Apr 13 11:11:27 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/duifei/common_ip/managed_ip_project/managed_ip_project.runs/ila_4x12x131072_synth_1/ila_4x12x131072_stub.vhdl
|
||||
-- Design : ila_4x12x131072
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z100ffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity ila_4x12x131072 is
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
probe0 : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe1 : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe2 : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe3 : in STD_LOGIC_VECTOR ( 11 downto 0 )
|
||||
);
|
||||
|
||||
end ila_4x12x131072;
|
||||
|
||||
architecture stub of ila_4x12x131072 is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe0[11:0],probe1[11:0],probe2[11:0],probe3[11:0]";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
@@ -0,0 +1,68 @@
|
||||
// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
`timescale 1ns / 1ps
|
||||
module ila_4x12x131072 (
|
||||
clk,
|
||||
|
||||
|
||||
probe0,
|
||||
probe1,
|
||||
probe2,
|
||||
probe3
|
||||
);
|
||||
|
||||
input clk;
|
||||
|
||||
|
||||
input [11 : 0] probe0;
|
||||
input [11 : 0] probe1;
|
||||
input [11 : 0] probe2;
|
||||
input [11 : 0] probe3;
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,76 @@
|
||||
// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
|
||||
ila_8x12x131072 your_instance_name (
|
||||
.clk(clk), // input wire clk
|
||||
|
||||
|
||||
.probe0(probe0), // input wire [11:0] probe0
|
||||
.probe1(probe1), // input wire [11:0] probe1
|
||||
.probe2(probe2), // input wire [11:0] probe2
|
||||
.probe3(probe3), // input wire [11:0] probe3
|
||||
.probe4(probe4), // input wire [11:0] probe4
|
||||
.probe5(probe5), // input wire [11:0] probe5
|
||||
.probe6(probe6), // input wire [11:0] probe6
|
||||
.probe7(probe7) // input wire [11:0] probe7
|
||||
);
|
||||
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
// You must compile the wrapper file ila_8x12x131072 when simulating
|
||||
// the core, ila_8x12x131072. When compiling the wrapper file, be sure to
|
||||
// reference the Verilog simulation library.
|
||||
|
||||
|
||||
BIN
Binary file not shown.
BIN
Binary file not shown.
@@ -0,0 +1,29 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Thu Apr 13 11:12:13 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/duifei/common_ip/managed_ip_project/managed_ip_project.runs/ila_8x12x131072_synth_1/ila_8x12x131072_stub.v
|
||||
// Design : ila_8x12x131072
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z100ffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "ila,Vivado 2019.1.3" *)
|
||||
module ila_8x12x131072(clk, probe0, probe1, probe2, probe3, probe4, probe5,
|
||||
probe6, probe7)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[11:0],probe1[11:0],probe2[11:0],probe3[11:0],probe4[11:0],probe5[11:0],probe6[11:0],probe7[11:0]" */;
|
||||
input clk;
|
||||
input [11:0]probe0;
|
||||
input [11:0]probe1;
|
||||
input [11:0]probe2;
|
||||
input [11:0]probe3;
|
||||
input [11:0]probe4;
|
||||
input [11:0]probe5;
|
||||
input [11:0]probe6;
|
||||
input [11:0]probe7;
|
||||
endmodule
|
||||
@@ -0,0 +1,38 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Thu Apr 13 11:12:13 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/duifei/common_ip/managed_ip_project/managed_ip_project.runs/ila_8x12x131072_synth_1/ila_8x12x131072_stub.vhdl
|
||||
-- Design : ila_8x12x131072
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z100ffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity ila_8x12x131072 is
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
probe0 : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe1 : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe2 : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe3 : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe4 : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe5 : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe6 : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe7 : in STD_LOGIC_VECTOR ( 11 downto 0 )
|
||||
);
|
||||
|
||||
end ila_8x12x131072;
|
||||
|
||||
architecture stub of ila_8x12x131072 is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe0[11:0],probe1[11:0],probe2[11:0],probe3[11:0],probe4[11:0],probe5[11:0],probe6[11:0],probe7[11:0]";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
@@ -0,0 +1,76 @@
|
||||
// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
`timescale 1ns / 1ps
|
||||
module ila_8x12x131072 (
|
||||
clk,
|
||||
|
||||
|
||||
probe0,
|
||||
probe1,
|
||||
probe2,
|
||||
probe3,
|
||||
probe4,
|
||||
probe5,
|
||||
probe6,
|
||||
probe7
|
||||
);
|
||||
|
||||
input clk;
|
||||
|
||||
|
||||
input [11 : 0] probe0;
|
||||
input [11 : 0] probe1;
|
||||
input [11 : 0] probe2;
|
||||
input [11 : 0] probe3;
|
||||
input [11 : 0] probe4;
|
||||
input [11 : 0] probe5;
|
||||
input [11 : 0] probe6;
|
||||
input [11 : 0] probe7;
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,81 @@
|
||||
// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
|
||||
ila_AntCtrl your_instance_name (
|
||||
.clk(clk), // input wire clk
|
||||
|
||||
|
||||
.probe0(probe0), // input wire [0:0] probe0
|
||||
.probe1(probe1), // input wire [0:0] probe1
|
||||
.probe2(probe2), // input wire [0:0] probe2
|
||||
.probe3(probe3), // input wire [0:0] probe3
|
||||
.probe4(probe4), // input wire [0:0] probe4
|
||||
.probe5(probe5), // input wire [0:0] probe5
|
||||
.probe6(probe6), // input wire [1:0] probe6
|
||||
.probe7(probe7), // input wire [7:0] probe7
|
||||
.probe8(probe8), // input wire [7:0] probe8
|
||||
.probe9(probe9), // input wire [7:0] probe9
|
||||
.probe10(probe10), // input wire [7:0] probe10
|
||||
.probe11(probe11), // input wire [31:0] probe11
|
||||
.probe12(probe12) // input wire [95:0] probe12
|
||||
);
|
||||
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
// You must compile the wrapper file ila_AntCtrl when simulating
|
||||
// the core, ila_AntCtrl. When compiling the wrapper file, be sure to
|
||||
// reference the Verilog simulation library.
|
||||
|
||||
|
||||
Binary file not shown.
BIN
Binary file not shown.
@@ -0,0 +1,34 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Thu Mar 30 16:43:51 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ip/managed_ip_project/managed_ip_project.runs/ila_AntCtrl_synth_1/ila_AntCtrl_stub.v
|
||||
// Design : ila_AntCtrl
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z100ffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "ila,Vivado 2019.1.3" *)
|
||||
module ila_AntCtrl(clk, probe0, probe1, probe2, probe3, probe4, probe5,
|
||||
probe6, probe7, probe8, probe9, probe10, probe11, probe12)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[0:0],probe1[0:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[1:0],probe7[7:0],probe8[7:0],probe9[7:0],probe10[7:0],probe11[31:0],probe12[95:0]" */;
|
||||
input clk;
|
||||
input [0:0]probe0;
|
||||
input [0:0]probe1;
|
||||
input [0:0]probe2;
|
||||
input [0:0]probe3;
|
||||
input [0:0]probe4;
|
||||
input [0:0]probe5;
|
||||
input [1:0]probe6;
|
||||
input [7:0]probe7;
|
||||
input [7:0]probe8;
|
||||
input [7:0]probe9;
|
||||
input [7:0]probe10;
|
||||
input [31:0]probe11;
|
||||
input [95:0]probe12;
|
||||
endmodule
|
||||
@@ -0,0 +1,43 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Thu Mar 30 16:43:51 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ip/managed_ip_project/managed_ip_project.runs/ila_AntCtrl_synth_1/ila_AntCtrl_stub.vhdl
|
||||
-- Design : ila_AntCtrl
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z100ffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity ila_AntCtrl is
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
probe0 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe1 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe2 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe3 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe4 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe5 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe6 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe7 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe8 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe9 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe10 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe11 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe12 : in STD_LOGIC_VECTOR ( 95 downto 0 )
|
||||
);
|
||||
|
||||
end ila_AntCtrl;
|
||||
|
||||
architecture stub of ila_AntCtrl is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe0[0:0],probe1[0:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[1:0],probe7[7:0],probe8[7:0],probe9[7:0],probe10[7:0],probe11[31:0],probe12[95:0]";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
@@ -0,0 +1,86 @@
|
||||
// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
`timescale 1ns / 1ps
|
||||
module ila_AntCtrl (
|
||||
clk,
|
||||
|
||||
|
||||
probe0,
|
||||
probe1,
|
||||
probe2,
|
||||
probe3,
|
||||
probe4,
|
||||
probe5,
|
||||
probe6,
|
||||
probe7,
|
||||
probe8,
|
||||
probe9,
|
||||
probe10,
|
||||
probe11,
|
||||
probe12
|
||||
);
|
||||
|
||||
input clk;
|
||||
|
||||
|
||||
input [0 : 0] probe0;
|
||||
input [0 : 0] probe1;
|
||||
input [0 : 0] probe2;
|
||||
input [0 : 0] probe3;
|
||||
input [0 : 0] probe4;
|
||||
input [0 : 0] probe5;
|
||||
input [1 : 0] probe6;
|
||||
input [7 : 0] probe7;
|
||||
input [7 : 0] probe8;
|
||||
input [7 : 0] probe9;
|
||||
input [7 : 0] probe10;
|
||||
input [31 : 0] probe11;
|
||||
input [95 : 0] probe12;
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,118 @@
|
||||
// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
|
||||
ila_rfcontrl your_instance_name (
|
||||
.clk(clk), // input wire clk
|
||||
|
||||
|
||||
.probe0(probe0), // input wire [0:0] probe0
|
||||
.probe1(probe1), // input wire [0:0] probe1
|
||||
.probe2(probe2), // input wire [0:0] probe2
|
||||
.probe3(probe3), // input wire [0:0] probe3
|
||||
.probe4(probe4), // input wire [0:0] probe4
|
||||
.probe5(probe5), // input wire [0:0] probe5
|
||||
.probe6(probe6), // input wire [0:0] probe6
|
||||
.probe7(probe7), // input wire [0:0] probe7
|
||||
.probe8(probe8), // input wire [0:0] probe8
|
||||
.probe9(probe9), // input wire [0:0] probe9
|
||||
.probe10(probe10), // input wire [0:0] probe10
|
||||
.probe11(probe11), // input wire [0:0] probe11
|
||||
.probe12(probe12), // input wire [0:0] probe12
|
||||
.probe13(probe13), // input wire [0:0] probe13
|
||||
.probe14(probe14), // input wire [0:0] probe14
|
||||
.probe15(probe15), // input wire [0:0] probe15
|
||||
.probe16(probe16), // input wire [0:0] probe16
|
||||
.probe17(probe17), // input wire [0:0] probe17
|
||||
.probe18(probe18), // input wire [0:0] probe18
|
||||
.probe19(probe19), // input wire [0:0] probe19
|
||||
.probe20(probe20), // input wire [0:0] probe20
|
||||
.probe21(probe21), // input wire [0:0] probe21
|
||||
.probe22(probe22), // input wire [0:0] probe22
|
||||
.probe23(probe23), // input wire [0:0] probe23
|
||||
.probe24(probe24), // input wire [0:0] probe24
|
||||
.probe25(probe25), // input wire [0:0] probe25
|
||||
.probe26(probe26), // input wire [0:0] probe26
|
||||
.probe27(probe27), // input wire [0:0] probe27
|
||||
.probe28(probe28), // input wire [0:0] probe28
|
||||
.probe29(probe29), // input wire [0:0] probe29
|
||||
.probe30(probe30), // input wire [0:0] probe30
|
||||
.probe31(probe31), // input wire [0:0] probe31
|
||||
.probe32(probe32), // input wire [0:0] probe32
|
||||
.probe33(probe33), // input wire [0:0] probe33
|
||||
.probe34(probe34), // input wire [0:0] probe34
|
||||
.probe35(probe35), // input wire [0:0] probe35
|
||||
.probe36(probe36), // input wire [0:0] probe36
|
||||
.probe37(probe37), // input wire [0:0] probe37
|
||||
.probe38(probe38), // input wire [0:0] probe38
|
||||
.probe39(probe39), // input wire [1:0] probe39
|
||||
.probe40(probe40), // input wire [7:0] probe40
|
||||
.probe41(probe41), // input wire [7:0] probe41
|
||||
.probe42(probe42), // input wire [7:0] probe42
|
||||
.probe43(probe43), // input wire [7:0] probe43
|
||||
.probe44(probe44), // input wire [3:0] probe44
|
||||
.probe45(probe45), // input wire [3:0] probe45
|
||||
.probe46(probe46), // input wire [3:0] probe46
|
||||
.probe47(probe47), // input wire [3:0] probe47
|
||||
.probe48(probe48), // input wire [31:0] probe48
|
||||
.probe49(probe49) // input wire [95:0] probe49
|
||||
);
|
||||
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
// You must compile the wrapper file ila_rfcontrl when simulating
|
||||
// the core, ila_rfcontrl. When compiling the wrapper file, be sure to
|
||||
// reference the Verilog simulation library.
|
||||
|
||||
|
||||
BIN
Binary file not shown.
BIN
Binary file not shown.
@@ -0,0 +1,74 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Thu Mar 30 16:44:02 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ip/managed_ip_project/managed_ip_project.runs/ila_rfcontrl_synth_1/ila_rfcontrl_stub.v
|
||||
// Design : ila_rfcontrl
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z100ffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "ila,Vivado 2019.1.3" *)
|
||||
module ila_rfcontrl(clk, probe0, probe1, probe2, probe3, probe4, probe5,
|
||||
probe6, probe7, probe8, probe9, probe10, probe11, probe12, probe13, probe14, probe15, probe16, probe17,
|
||||
probe18, probe19, probe20, probe21, probe22, probe23, probe24, probe25, probe26, probe27, probe28,
|
||||
probe29, probe30, probe31, probe32, probe33, probe34, probe35, probe36, probe37, probe38, probe39,
|
||||
probe40, probe41, probe42, probe43, probe44, probe45, probe46, probe47, probe48, probe49)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[0:0],probe1[0:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[0:0],probe8[0:0],probe9[0:0],probe10[0:0],probe11[0:0],probe12[0:0],probe13[0:0],probe14[0:0],probe15[0:0],probe16[0:0],probe17[0:0],probe18[0:0],probe19[0:0],probe20[0:0],probe21[0:0],probe22[0:0],probe23[0:0],probe24[0:0],probe25[0:0],probe26[0:0],probe27[0:0],probe28[0:0],probe29[0:0],probe30[0:0],probe31[0:0],probe32[0:0],probe33[0:0],probe34[0:0],probe35[0:0],probe36[0:0],probe37[0:0],probe38[0:0],probe39[1:0],probe40[7:0],probe41[7:0],probe42[7:0],probe43[7:0],probe44[3:0],probe45[3:0],probe46[3:0],probe47[3:0],probe48[31:0],probe49[95:0]" */;
|
||||
input clk;
|
||||
input [0:0]probe0;
|
||||
input [0:0]probe1;
|
||||
input [0:0]probe2;
|
||||
input [0:0]probe3;
|
||||
input [0:0]probe4;
|
||||
input [0:0]probe5;
|
||||
input [0:0]probe6;
|
||||
input [0:0]probe7;
|
||||
input [0:0]probe8;
|
||||
input [0:0]probe9;
|
||||
input [0:0]probe10;
|
||||
input [0:0]probe11;
|
||||
input [0:0]probe12;
|
||||
input [0:0]probe13;
|
||||
input [0:0]probe14;
|
||||
input [0:0]probe15;
|
||||
input [0:0]probe16;
|
||||
input [0:0]probe17;
|
||||
input [0:0]probe18;
|
||||
input [0:0]probe19;
|
||||
input [0:0]probe20;
|
||||
input [0:0]probe21;
|
||||
input [0:0]probe22;
|
||||
input [0:0]probe23;
|
||||
input [0:0]probe24;
|
||||
input [0:0]probe25;
|
||||
input [0:0]probe26;
|
||||
input [0:0]probe27;
|
||||
input [0:0]probe28;
|
||||
input [0:0]probe29;
|
||||
input [0:0]probe30;
|
||||
input [0:0]probe31;
|
||||
input [0:0]probe32;
|
||||
input [0:0]probe33;
|
||||
input [0:0]probe34;
|
||||
input [0:0]probe35;
|
||||
input [0:0]probe36;
|
||||
input [0:0]probe37;
|
||||
input [0:0]probe38;
|
||||
input [1:0]probe39;
|
||||
input [7:0]probe40;
|
||||
input [7:0]probe41;
|
||||
input [7:0]probe42;
|
||||
input [7:0]probe43;
|
||||
input [3:0]probe44;
|
||||
input [3:0]probe45;
|
||||
input [3:0]probe46;
|
||||
input [3:0]probe47;
|
||||
input [31:0]probe48;
|
||||
input [95:0]probe49;
|
||||
endmodule
|
||||
@@ -0,0 +1,80 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Thu Mar 30 16:44:02 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ip/managed_ip_project/managed_ip_project.runs/ila_rfcontrl_synth_1/ila_rfcontrl_stub.vhdl
|
||||
-- Design : ila_rfcontrl
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z100ffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity ila_rfcontrl is
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
probe0 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe1 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe2 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe3 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe4 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe5 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe6 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe7 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe8 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe9 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe10 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe11 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe12 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe13 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe14 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe15 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe16 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe17 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe18 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe19 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe20 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe21 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe22 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe23 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe24 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe25 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe26 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe27 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe28 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe29 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe30 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe31 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe32 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe33 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe34 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe35 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe36 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe37 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe38 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe39 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe40 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe41 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe42 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe43 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe44 : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
probe45 : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
probe46 : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
probe47 : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
probe48 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe49 : in STD_LOGIC_VECTOR ( 95 downto 0 )
|
||||
);
|
||||
|
||||
end ila_rfcontrl;
|
||||
|
||||
architecture stub of ila_rfcontrl is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe0[0:0],probe1[0:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[0:0],probe8[0:0],probe9[0:0],probe10[0:0],probe11[0:0],probe12[0:0],probe13[0:0],probe14[0:0],probe15[0:0],probe16[0:0],probe17[0:0],probe18[0:0],probe19[0:0],probe20[0:0],probe21[0:0],probe22[0:0],probe23[0:0],probe24[0:0],probe25[0:0],probe26[0:0],probe27[0:0],probe28[0:0],probe29[0:0],probe30[0:0],probe31[0:0],probe32[0:0],probe33[0:0],probe34[0:0],probe35[0:0],probe36[0:0],probe37[0:0],probe38[0:0],probe39[1:0],probe40[7:0],probe41[7:0],probe42[7:0],probe43[7:0],probe44[3:0],probe45[3:0],probe46[3:0],probe47[3:0],probe48[31:0],probe49[95:0]";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
@@ -0,0 +1,160 @@
|
||||
// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
`timescale 1ns / 1ps
|
||||
module ila_rfcontrl (
|
||||
clk,
|
||||
|
||||
|
||||
probe0,
|
||||
probe1,
|
||||
probe2,
|
||||
probe3,
|
||||
probe4,
|
||||
probe5,
|
||||
probe6,
|
||||
probe7,
|
||||
probe8,
|
||||
probe9,
|
||||
probe10,
|
||||
probe11,
|
||||
probe12,
|
||||
probe13,
|
||||
probe14,
|
||||
probe15,
|
||||
probe16,
|
||||
probe17,
|
||||
probe18,
|
||||
probe19,
|
||||
probe20,
|
||||
probe21,
|
||||
probe22,
|
||||
probe23,
|
||||
probe24,
|
||||
probe25,
|
||||
probe26,
|
||||
probe27,
|
||||
probe28,
|
||||
probe29,
|
||||
probe30,
|
||||
probe31,
|
||||
probe32,
|
||||
probe33,
|
||||
probe34,
|
||||
probe35,
|
||||
probe36,
|
||||
probe37,
|
||||
probe38,
|
||||
probe39,
|
||||
probe40,
|
||||
probe41,
|
||||
probe42,
|
||||
probe43,
|
||||
probe44,
|
||||
probe45,
|
||||
probe46,
|
||||
probe47,
|
||||
probe48,
|
||||
probe49
|
||||
);
|
||||
|
||||
input clk;
|
||||
|
||||
|
||||
input [0 : 0] probe0;
|
||||
input [0 : 0] probe1;
|
||||
input [0 : 0] probe2;
|
||||
input [0 : 0] probe3;
|
||||
input [0 : 0] probe4;
|
||||
input [0 : 0] probe5;
|
||||
input [0 : 0] probe6;
|
||||
input [0 : 0] probe7;
|
||||
input [0 : 0] probe8;
|
||||
input [0 : 0] probe9;
|
||||
input [0 : 0] probe10;
|
||||
input [0 : 0] probe11;
|
||||
input [0 : 0] probe12;
|
||||
input [0 : 0] probe13;
|
||||
input [0 : 0] probe14;
|
||||
input [0 : 0] probe15;
|
||||
input [0 : 0] probe16;
|
||||
input [0 : 0] probe17;
|
||||
input [0 : 0] probe18;
|
||||
input [0 : 0] probe19;
|
||||
input [0 : 0] probe20;
|
||||
input [0 : 0] probe21;
|
||||
input [0 : 0] probe22;
|
||||
input [0 : 0] probe23;
|
||||
input [0 : 0] probe24;
|
||||
input [0 : 0] probe25;
|
||||
input [0 : 0] probe26;
|
||||
input [0 : 0] probe27;
|
||||
input [0 : 0] probe28;
|
||||
input [0 : 0] probe29;
|
||||
input [0 : 0] probe30;
|
||||
input [0 : 0] probe31;
|
||||
input [0 : 0] probe32;
|
||||
input [0 : 0] probe33;
|
||||
input [0 : 0] probe34;
|
||||
input [0 : 0] probe35;
|
||||
input [0 : 0] probe36;
|
||||
input [0 : 0] probe37;
|
||||
input [0 : 0] probe38;
|
||||
input [1 : 0] probe39;
|
||||
input [7 : 0] probe40;
|
||||
input [7 : 0] probe41;
|
||||
input [7 : 0] probe42;
|
||||
input [7 : 0] probe43;
|
||||
input [3 : 0] probe44;
|
||||
input [3 : 0] probe45;
|
||||
input [3 : 0] probe46;
|
||||
input [3 : 0] probe47;
|
||||
input [31 : 0] probe48;
|
||||
input [95 : 0] probe49;
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,65 @@
|
||||
// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
`timescale 1ns / 1ps
|
||||
module vio_ant_rd (
|
||||
clk,
|
||||
probe_in0,probe_in1,probe_in2,probe_in3,probe_in4,probe_in5
|
||||
|
||||
);
|
||||
|
||||
input clk;
|
||||
input [7 : 0] probe_in0;
|
||||
input [7 : 0] probe_in1;
|
||||
input [7 : 0] probe_in2;
|
||||
input [7 : 0] probe_in3;
|
||||
input [31 : 0] probe_in4;
|
||||
input [95 : 0] probe_in5;
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,71 @@
|
||||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
// IP VLNV: xilinx.com:ip:vio:3.0
|
||||
// IP Revision: 20
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
vio_ant_rd your_instance_name (
|
||||
.clk(clk), // input wire clk
|
||||
.probe_in0(probe_in0), // input wire [7 : 0] probe_in0
|
||||
.probe_in1(probe_in1), // input wire [7 : 0] probe_in1
|
||||
.probe_in2(probe_in2), // input wire [7 : 0] probe_in2
|
||||
.probe_in3(probe_in3), // input wire [7 : 0] probe_in3
|
||||
.probe_in4(probe_in4), // input wire [31 : 0] probe_in4
|
||||
.probe_in5(probe_in5) // input wire [95 : 0] probe_in5
|
||||
);
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
// You must compile the wrapper file vio_ant_rd.v when simulating
|
||||
// the core, vio_ant_rd. When compiling the wrapper file, be sure to
|
||||
// reference the Verilog simulation library.
|
||||
|
||||
@@ -0,0 +1,87 @@
|
||||
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:vio:3.0
|
||||
-- IP Revision: 20
|
||||
|
||||
-- The following code must appear in the VHDL architecture header.
|
||||
|
||||
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
|
||||
COMPONENT vio_ant_rd
|
||||
PORT (
|
||||
clk : IN STD_LOGIC;
|
||||
probe_in0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
probe_in1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
probe_in2 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
probe_in3 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
probe_in4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
probe_in5 : IN STD_LOGIC_VECTOR(95 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
||||
|
||||
-- The following code must appear in the VHDL architecture
|
||||
-- body. Substitute your own instance name and net names.
|
||||
|
||||
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
|
||||
your_instance_name : vio_ant_rd
|
||||
PORT MAP (
|
||||
clk => clk,
|
||||
probe_in0 => probe_in0,
|
||||
probe_in1 => probe_in1,
|
||||
probe_in2 => probe_in2,
|
||||
probe_in3 => probe_in3,
|
||||
probe_in4 => probe_in4,
|
||||
probe_in5 => probe_in5
|
||||
);
|
||||
-- INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
-- You must compile the wrapper file vio_ant_rd.vhd when simulating
|
||||
-- the core, vio_ant_rd. When compiling the wrapper file, be sure to
|
||||
-- reference the VHDL simulation library.
|
||||
|
||||
Binary file not shown.
Binary file not shown.
@@ -0,0 +1,27 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Thu Mar 30 16:42:43 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ip/managed_ip_project/managed_ip_project.runs/vio_ant_rd_synth_1/vio_ant_rd_stub.v
|
||||
// Design : vio_ant_rd
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z100ffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "vio,Vivado 2019.1.3" *)
|
||||
module vio_ant_rd(clk, probe_in0, probe_in1, probe_in2, probe_in3,
|
||||
probe_in4, probe_in5)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[7:0],probe_in1[7:0],probe_in2[7:0],probe_in3[7:0],probe_in4[31:0],probe_in5[95:0]" */;
|
||||
input clk;
|
||||
input [7:0]probe_in0;
|
||||
input [7:0]probe_in1;
|
||||
input [7:0]probe_in2;
|
||||
input [7:0]probe_in3;
|
||||
input [31:0]probe_in4;
|
||||
input [95:0]probe_in5;
|
||||
endmodule
|
||||
@@ -0,0 +1,36 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Thu Mar 30 16:42:43 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ip/managed_ip_project/managed_ip_project.runs/vio_ant_rd_synth_1/vio_ant_rd_stub.vhdl
|
||||
-- Design : vio_ant_rd
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z100ffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity vio_ant_rd is
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
probe_in0 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe_in1 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe_in2 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe_in3 : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe_in4 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe_in5 : in STD_LOGIC_VECTOR ( 95 downto 0 )
|
||||
);
|
||||
|
||||
end vio_ant_rd;
|
||||
|
||||
architecture stub of vio_ant_rd is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[7:0],probe_in1[7:0],probe_in2[7:0],probe_in3[7:0],probe_in4[31:0],probe_in5[95:0]";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
@@ -0,0 +1,66 @@
|
||||
// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
`timescale 1ns / 1ps
|
||||
module vio_ant_test (
|
||||
clk,
|
||||
|
||||
probe_out0,
|
||||
probe_out1,
|
||||
probe_out2,
|
||||
probe_out3
|
||||
);
|
||||
|
||||
input clk;
|
||||
|
||||
output reg [0 : 0] probe_out0 = 'h0 ;
|
||||
output reg [0 : 0] probe_out1 = 'h0 ;
|
||||
output reg [0 : 0] probe_out2 = 'h1 ;
|
||||
output reg [15 : 0] probe_out3 = 'h2580 ;
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,69 @@
|
||||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
// IP VLNV: xilinx.com:ip:vio:3.0
|
||||
// IP Revision: 20
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
vio_ant_test your_instance_name (
|
||||
.clk(clk), // input wire clk
|
||||
.probe_out0(probe_out0), // output wire [0 : 0] probe_out0
|
||||
.probe_out1(probe_out1), // output wire [0 : 0] probe_out1
|
||||
.probe_out2(probe_out2), // output wire [0 : 0] probe_out2
|
||||
.probe_out3(probe_out3) // output wire [15 : 0] probe_out3
|
||||
);
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
// You must compile the wrapper file vio_ant_test.v when simulating
|
||||
// the core, vio_ant_test. When compiling the wrapper file, be sure to
|
||||
// reference the Verilog simulation library.
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user