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first commit after restructuring
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// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
|
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// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
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||||
// DO NOT MODIFY THIS FILE.
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||||
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// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
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// IP Revision: 19
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`timescale 1ns/1ps
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(* DowngradeIPIdentifiedWarnings = "yes" *)
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module system_bd_auto_pc_0 (
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aclk,
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aresetn,
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s_axi_awid,
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s_axi_awaddr,
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s_axi_awlen,
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s_axi_awsize,
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s_axi_awburst,
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s_axi_awlock,
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s_axi_awcache,
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s_axi_awprot,
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s_axi_awqos,
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s_axi_awvalid,
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s_axi_awready,
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s_axi_wid,
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s_axi_wdata,
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s_axi_wstrb,
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s_axi_wlast,
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s_axi_wvalid,
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s_axi_wready,
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s_axi_bid,
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s_axi_bresp,
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s_axi_bvalid,
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s_axi_bready,
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s_axi_arid,
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s_axi_araddr,
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s_axi_arlen,
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s_axi_arsize,
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s_axi_arburst,
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s_axi_arlock,
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s_axi_arcache,
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s_axi_arprot,
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s_axi_arqos,
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s_axi_arvalid,
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s_axi_arready,
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s_axi_rid,
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s_axi_rdata,
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s_axi_rresp,
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s_axi_rlast,
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s_axi_rvalid,
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s_axi_rready,
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m_axi_awaddr,
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m_axi_awprot,
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m_axi_awvalid,
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m_axi_awready,
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m_axi_wdata,
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m_axi_wstrb,
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m_axi_wvalid,
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m_axi_wready,
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m_axi_bresp,
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m_axi_bvalid,
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m_axi_bready,
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m_axi_araddr,
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m_axi_arprot,
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m_axi_arvalid,
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m_axi_arready,
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m_axi_rdata,
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m_axi_rresp,
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m_axi_rvalid,
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m_axi_rready
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);
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(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN system_bd_ps_system_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, INSERT_VIP 0" *)
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(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
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input wire aclk;
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(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
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(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
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input wire aresetn;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
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input wire [11 : 0] s_axi_awid;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
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input wire [31 : 0] s_axi_awaddr;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
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input wire [3 : 0] s_axi_awlen;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
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input wire [2 : 0] s_axi_awsize;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
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input wire [1 : 0] s_axi_awburst;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
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input wire [1 : 0] s_axi_awlock;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
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input wire [3 : 0] s_axi_awcache;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
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input wire [2 : 0] s_axi_awprot;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
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input wire [3 : 0] s_axi_awqos;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
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input wire s_axi_awvalid;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
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output wire s_axi_awready;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *)
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input wire [11 : 0] s_axi_wid;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
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input wire [31 : 0] s_axi_wdata;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
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input wire [3 : 0] s_axi_wstrb;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
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input wire s_axi_wlast;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
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input wire s_axi_wvalid;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
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output wire s_axi_wready;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
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output wire [11 : 0] s_axi_bid;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
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output wire [1 : 0] s_axi_bresp;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
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output wire s_axi_bvalid;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
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input wire s_axi_bready;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
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input wire [11 : 0] s_axi_arid;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
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input wire [31 : 0] s_axi_araddr;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
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input wire [3 : 0] s_axi_arlen;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
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input wire [2 : 0] s_axi_arsize;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
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input wire [1 : 0] s_axi_arburst;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
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input wire [1 : 0] s_axi_arlock;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
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input wire [3 : 0] s_axi_arcache;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
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input wire [2 : 0] s_axi_arprot;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
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input wire [3 : 0] s_axi_arqos;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
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input wire s_axi_arvalid;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
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output wire s_axi_arready;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
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output wire [11 : 0] s_axi_rid;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
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output wire [31 : 0] s_axi_rdata;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
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output wire [1 : 0] s_axi_rresp;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
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output wire s_axi_rlast;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
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output wire s_axi_rvalid;
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(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 50000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN system_bd_ps_system_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRIT\
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E_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
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input wire s_axi_rready;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
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output wire [31 : 0] m_axi_awaddr;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
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output wire [2 : 0] m_axi_awprot;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
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output wire m_axi_awvalid;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
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input wire m_axi_awready;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
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output wire [31 : 0] m_axi_wdata;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
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output wire [3 : 0] m_axi_wstrb;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
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output wire m_axi_wvalid;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
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input wire m_axi_wready;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
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input wire [1 : 0] m_axi_bresp;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
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input wire m_axi_bvalid;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
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output wire m_axi_bready;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
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output wire [31 : 0] m_axi_araddr;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
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output wire [2 : 0] m_axi_arprot;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
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output wire m_axi_arvalid;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
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input wire m_axi_arready;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
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input wire [31 : 0] m_axi_rdata;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
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input wire [1 : 0] m_axi_rresp;
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(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
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input wire m_axi_rvalid;
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||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 50000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN system_bd_ps_system_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WR\
|
||||
ITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
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||||
output wire m_axi_rready;
|
||||
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||||
axi_protocol_converter_v2_1_19_axi_protocol_converter #(
|
||||
.C_FAMILY("zynq"),
|
||||
.C_M_AXI_PROTOCOL(2),
|
||||
.C_S_AXI_PROTOCOL(1),
|
||||
.C_IGNORE_ID(0),
|
||||
.C_AXI_ID_WIDTH(12),
|
||||
.C_AXI_ADDR_WIDTH(32),
|
||||
.C_AXI_DATA_WIDTH(32),
|
||||
.C_AXI_SUPPORTS_WRITE(1),
|
||||
.C_AXI_SUPPORTS_READ(1),
|
||||
.C_AXI_SUPPORTS_USER_SIGNALS(0),
|
||||
.C_AXI_AWUSER_WIDTH(1),
|
||||
.C_AXI_ARUSER_WIDTH(1),
|
||||
.C_AXI_WUSER_WIDTH(1),
|
||||
.C_AXI_RUSER_WIDTH(1),
|
||||
.C_AXI_BUSER_WIDTH(1),
|
||||
.C_TRANSLATION_MODE(2)
|
||||
) inst (
|
||||
.aclk(aclk),
|
||||
.aresetn(aresetn),
|
||||
.s_axi_awid(s_axi_awid),
|
||||
.s_axi_awaddr(s_axi_awaddr),
|
||||
.s_axi_awlen(s_axi_awlen),
|
||||
.s_axi_awsize(s_axi_awsize),
|
||||
.s_axi_awburst(s_axi_awburst),
|
||||
.s_axi_awlock(s_axi_awlock),
|
||||
.s_axi_awcache(s_axi_awcache),
|
||||
.s_axi_awprot(s_axi_awprot),
|
||||
.s_axi_awregion(4'H0),
|
||||
.s_axi_awqos(s_axi_awqos),
|
||||
.s_axi_awuser(1'H0),
|
||||
.s_axi_awvalid(s_axi_awvalid),
|
||||
.s_axi_awready(s_axi_awready),
|
||||
.s_axi_wid(s_axi_wid),
|
||||
.s_axi_wdata(s_axi_wdata),
|
||||
.s_axi_wstrb(s_axi_wstrb),
|
||||
.s_axi_wlast(s_axi_wlast),
|
||||
.s_axi_wuser(1'H0),
|
||||
.s_axi_wvalid(s_axi_wvalid),
|
||||
.s_axi_wready(s_axi_wready),
|
||||
.s_axi_bid(s_axi_bid),
|
||||
.s_axi_bresp(s_axi_bresp),
|
||||
.s_axi_buser(),
|
||||
.s_axi_bvalid(s_axi_bvalid),
|
||||
.s_axi_bready(s_axi_bready),
|
||||
.s_axi_arid(s_axi_arid),
|
||||
.s_axi_araddr(s_axi_araddr),
|
||||
.s_axi_arlen(s_axi_arlen),
|
||||
.s_axi_arsize(s_axi_arsize),
|
||||
.s_axi_arburst(s_axi_arburst),
|
||||
.s_axi_arlock(s_axi_arlock),
|
||||
.s_axi_arcache(s_axi_arcache),
|
||||
.s_axi_arprot(s_axi_arprot),
|
||||
.s_axi_arregion(4'H0),
|
||||
.s_axi_arqos(s_axi_arqos),
|
||||
.s_axi_aruser(1'H0),
|
||||
.s_axi_arvalid(s_axi_arvalid),
|
||||
.s_axi_arready(s_axi_arready),
|
||||
.s_axi_rid(s_axi_rid),
|
||||
.s_axi_rdata(s_axi_rdata),
|
||||
.s_axi_rresp(s_axi_rresp),
|
||||
.s_axi_rlast(s_axi_rlast),
|
||||
.s_axi_ruser(),
|
||||
.s_axi_rvalid(s_axi_rvalid),
|
||||
.s_axi_rready(s_axi_rready),
|
||||
.m_axi_awid(),
|
||||
.m_axi_awaddr(m_axi_awaddr),
|
||||
.m_axi_awlen(),
|
||||
.m_axi_awsize(),
|
||||
.m_axi_awburst(),
|
||||
.m_axi_awlock(),
|
||||
.m_axi_awcache(),
|
||||
.m_axi_awprot(m_axi_awprot),
|
||||
.m_axi_awregion(),
|
||||
.m_axi_awqos(),
|
||||
.m_axi_awuser(),
|
||||
.m_axi_awvalid(m_axi_awvalid),
|
||||
.m_axi_awready(m_axi_awready),
|
||||
.m_axi_wid(),
|
||||
.m_axi_wdata(m_axi_wdata),
|
||||
.m_axi_wstrb(m_axi_wstrb),
|
||||
.m_axi_wlast(),
|
||||
.m_axi_wuser(),
|
||||
.m_axi_wvalid(m_axi_wvalid),
|
||||
.m_axi_wready(m_axi_wready),
|
||||
.m_axi_bid(12'H000),
|
||||
.m_axi_bresp(m_axi_bresp),
|
||||
.m_axi_buser(1'H0),
|
||||
.m_axi_bvalid(m_axi_bvalid),
|
||||
.m_axi_bready(m_axi_bready),
|
||||
.m_axi_arid(),
|
||||
.m_axi_araddr(m_axi_araddr),
|
||||
.m_axi_arlen(),
|
||||
.m_axi_arsize(),
|
||||
.m_axi_arburst(),
|
||||
.m_axi_arlock(),
|
||||
.m_axi_arcache(),
|
||||
.m_axi_arprot(m_axi_arprot),
|
||||
.m_axi_arregion(),
|
||||
.m_axi_arqos(),
|
||||
.m_axi_aruser(),
|
||||
.m_axi_arvalid(m_axi_arvalid),
|
||||
.m_axi_arready(m_axi_arready),
|
||||
.m_axi_rid(12'H000),
|
||||
.m_axi_rdata(m_axi_rdata),
|
||||
.m_axi_rresp(m_axi_rresp),
|
||||
.m_axi_rlast(1'H1),
|
||||
.m_axi_ruser(1'H0),
|
||||
.m_axi_rvalid(m_axi_rvalid),
|
||||
.m_axi_rready(m_axi_rready)
|
||||
);
|
||||
endmodule
|
||||
+356
@@ -0,0 +1,356 @@
|
||||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
|
||||
// IP Revision: 19
|
||||
|
||||
(* X_CORE_INFO = "axi_protocol_converter_v2_1_19_axi_protocol_converter,Vivado 2019.1.3" *)
|
||||
(* CHECK_LICENSE_TYPE = "system_bd_auto_pc_0,axi_protocol_converter_v2_1_19_axi_protocol_converter,{}" *)
|
||||
(* CORE_GENERATION_INFO = "system_bd_auto_pc_0,axi_protocol_converter_v2_1_19_axi_protocol_converter,{x_ipProduct=Vivado 2019.1.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_protocol_converter,x_ipVersion=2.1,x_ipCoreRevision=19,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_M_AXI_PROTOCOL=2,C_S_AXI_PROTOCOL=1,C_IGNORE_ID=0,C_AXI_ID_WIDTH=12,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WU\
|
||||
SER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_TRANSLATION_MODE=2}" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module system_bd_auto_pc_0 (
|
||||
aclk,
|
||||
aresetn,
|
||||
s_axi_awid,
|
||||
s_axi_awaddr,
|
||||
s_axi_awlen,
|
||||
s_axi_awsize,
|
||||
s_axi_awburst,
|
||||
s_axi_awlock,
|
||||
s_axi_awcache,
|
||||
s_axi_awprot,
|
||||
s_axi_awqos,
|
||||
s_axi_awvalid,
|
||||
s_axi_awready,
|
||||
s_axi_wid,
|
||||
s_axi_wdata,
|
||||
s_axi_wstrb,
|
||||
s_axi_wlast,
|
||||
s_axi_wvalid,
|
||||
s_axi_wready,
|
||||
s_axi_bid,
|
||||
s_axi_bresp,
|
||||
s_axi_bvalid,
|
||||
s_axi_bready,
|
||||
s_axi_arid,
|
||||
s_axi_araddr,
|
||||
s_axi_arlen,
|
||||
s_axi_arsize,
|
||||
s_axi_arburst,
|
||||
s_axi_arlock,
|
||||
s_axi_arcache,
|
||||
s_axi_arprot,
|
||||
s_axi_arqos,
|
||||
s_axi_arvalid,
|
||||
s_axi_arready,
|
||||
s_axi_rid,
|
||||
s_axi_rdata,
|
||||
s_axi_rresp,
|
||||
s_axi_rlast,
|
||||
s_axi_rvalid,
|
||||
s_axi_rready,
|
||||
m_axi_awaddr,
|
||||
m_axi_awprot,
|
||||
m_axi_awvalid,
|
||||
m_axi_awready,
|
||||
m_axi_wdata,
|
||||
m_axi_wstrb,
|
||||
m_axi_wvalid,
|
||||
m_axi_wready,
|
||||
m_axi_bresp,
|
||||
m_axi_bvalid,
|
||||
m_axi_bready,
|
||||
m_axi_araddr,
|
||||
m_axi_arprot,
|
||||
m_axi_arvalid,
|
||||
m_axi_arready,
|
||||
m_axi_rdata,
|
||||
m_axi_rresp,
|
||||
m_axi_rvalid,
|
||||
m_axi_rready
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN system_bd_ps_system_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
|
||||
input wire aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, INSERT_VIP 0, TYPE INTERCONNECT" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
|
||||
input wire aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
|
||||
input wire [11 : 0] s_axi_awid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
|
||||
input wire [31 : 0] s_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
|
||||
input wire [3 : 0] s_axi_awlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
|
||||
input wire [2 : 0] s_axi_awsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
|
||||
input wire [1 : 0] s_axi_awburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
|
||||
input wire [1 : 0] s_axi_awlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
|
||||
input wire [3 : 0] s_axi_awcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
|
||||
input wire [2 : 0] s_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
|
||||
input wire [3 : 0] s_axi_awqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
|
||||
input wire s_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
|
||||
output wire s_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *)
|
||||
input wire [11 : 0] s_axi_wid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
|
||||
input wire [31 : 0] s_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
|
||||
input wire [3 : 0] s_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
|
||||
input wire s_axi_wlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
|
||||
input wire s_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
|
||||
output wire s_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
|
||||
output wire [11 : 0] s_axi_bid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
|
||||
output wire [1 : 0] s_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
|
||||
output wire s_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
|
||||
input wire s_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
|
||||
input wire [11 : 0] s_axi_arid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
|
||||
input wire [31 : 0] s_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
|
||||
input wire [3 : 0] s_axi_arlen;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
|
||||
input wire [2 : 0] s_axi_arsize;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
|
||||
input wire [1 : 0] s_axi_arburst;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
|
||||
input wire [1 : 0] s_axi_arlock;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
|
||||
input wire [3 : 0] s_axi_arcache;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
|
||||
input wire [2 : 0] s_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
|
||||
input wire [3 : 0] s_axi_arqos;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
|
||||
input wire s_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
|
||||
output wire s_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
|
||||
output wire [11 : 0] s_axi_rid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
|
||||
output wire [31 : 0] s_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
|
||||
output wire [1 : 0] s_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
|
||||
output wire s_axi_rlast;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
|
||||
output wire s_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 50000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN system_bd_ps_system_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRIT\
|
||||
E_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
|
||||
input wire s_axi_rready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
|
||||
output wire [31 : 0] m_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
|
||||
output wire [2 : 0] m_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
|
||||
output wire m_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
|
||||
input wire m_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
|
||||
output wire [31 : 0] m_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
|
||||
output wire [3 : 0] m_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
|
||||
output wire m_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
|
||||
input wire m_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
|
||||
input wire [1 : 0] m_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
|
||||
input wire m_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
|
||||
output wire m_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
|
||||
output wire [31 : 0] m_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
|
||||
output wire [2 : 0] m_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
|
||||
output wire m_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
|
||||
input wire m_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
|
||||
input wire [31 : 0] m_axi_rdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
|
||||
input wire [1 : 0] m_axi_rresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
|
||||
input wire m_axi_rvalid;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 50000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN system_bd_ps_system_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WR\
|
||||
ITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
|
||||
output wire m_axi_rready;
|
||||
|
||||
axi_protocol_converter_v2_1_19_axi_protocol_converter #(
|
||||
.C_FAMILY("zynq"),
|
||||
.C_M_AXI_PROTOCOL(2),
|
||||
.C_S_AXI_PROTOCOL(1),
|
||||
.C_IGNORE_ID(0),
|
||||
.C_AXI_ID_WIDTH(12),
|
||||
.C_AXI_ADDR_WIDTH(32),
|
||||
.C_AXI_DATA_WIDTH(32),
|
||||
.C_AXI_SUPPORTS_WRITE(1),
|
||||
.C_AXI_SUPPORTS_READ(1),
|
||||
.C_AXI_SUPPORTS_USER_SIGNALS(0),
|
||||
.C_AXI_AWUSER_WIDTH(1),
|
||||
.C_AXI_ARUSER_WIDTH(1),
|
||||
.C_AXI_WUSER_WIDTH(1),
|
||||
.C_AXI_RUSER_WIDTH(1),
|
||||
.C_AXI_BUSER_WIDTH(1),
|
||||
.C_TRANSLATION_MODE(2)
|
||||
) inst (
|
||||
.aclk(aclk),
|
||||
.aresetn(aresetn),
|
||||
.s_axi_awid(s_axi_awid),
|
||||
.s_axi_awaddr(s_axi_awaddr),
|
||||
.s_axi_awlen(s_axi_awlen),
|
||||
.s_axi_awsize(s_axi_awsize),
|
||||
.s_axi_awburst(s_axi_awburst),
|
||||
.s_axi_awlock(s_axi_awlock),
|
||||
.s_axi_awcache(s_axi_awcache),
|
||||
.s_axi_awprot(s_axi_awprot),
|
||||
.s_axi_awregion(4'H0),
|
||||
.s_axi_awqos(s_axi_awqos),
|
||||
.s_axi_awuser(1'H0),
|
||||
.s_axi_awvalid(s_axi_awvalid),
|
||||
.s_axi_awready(s_axi_awready),
|
||||
.s_axi_wid(s_axi_wid),
|
||||
.s_axi_wdata(s_axi_wdata),
|
||||
.s_axi_wstrb(s_axi_wstrb),
|
||||
.s_axi_wlast(s_axi_wlast),
|
||||
.s_axi_wuser(1'H0),
|
||||
.s_axi_wvalid(s_axi_wvalid),
|
||||
.s_axi_wready(s_axi_wready),
|
||||
.s_axi_bid(s_axi_bid),
|
||||
.s_axi_bresp(s_axi_bresp),
|
||||
.s_axi_buser(),
|
||||
.s_axi_bvalid(s_axi_bvalid),
|
||||
.s_axi_bready(s_axi_bready),
|
||||
.s_axi_arid(s_axi_arid),
|
||||
.s_axi_araddr(s_axi_araddr),
|
||||
.s_axi_arlen(s_axi_arlen),
|
||||
.s_axi_arsize(s_axi_arsize),
|
||||
.s_axi_arburst(s_axi_arburst),
|
||||
.s_axi_arlock(s_axi_arlock),
|
||||
.s_axi_arcache(s_axi_arcache),
|
||||
.s_axi_arprot(s_axi_arprot),
|
||||
.s_axi_arregion(4'H0),
|
||||
.s_axi_arqos(s_axi_arqos),
|
||||
.s_axi_aruser(1'H0),
|
||||
.s_axi_arvalid(s_axi_arvalid),
|
||||
.s_axi_arready(s_axi_arready),
|
||||
.s_axi_rid(s_axi_rid),
|
||||
.s_axi_rdata(s_axi_rdata),
|
||||
.s_axi_rresp(s_axi_rresp),
|
||||
.s_axi_rlast(s_axi_rlast),
|
||||
.s_axi_ruser(),
|
||||
.s_axi_rvalid(s_axi_rvalid),
|
||||
.s_axi_rready(s_axi_rready),
|
||||
.m_axi_awid(),
|
||||
.m_axi_awaddr(m_axi_awaddr),
|
||||
.m_axi_awlen(),
|
||||
.m_axi_awsize(),
|
||||
.m_axi_awburst(),
|
||||
.m_axi_awlock(),
|
||||
.m_axi_awcache(),
|
||||
.m_axi_awprot(m_axi_awprot),
|
||||
.m_axi_awregion(),
|
||||
.m_axi_awqos(),
|
||||
.m_axi_awuser(),
|
||||
.m_axi_awvalid(m_axi_awvalid),
|
||||
.m_axi_awready(m_axi_awready),
|
||||
.m_axi_wid(),
|
||||
.m_axi_wdata(m_axi_wdata),
|
||||
.m_axi_wstrb(m_axi_wstrb),
|
||||
.m_axi_wlast(),
|
||||
.m_axi_wuser(),
|
||||
.m_axi_wvalid(m_axi_wvalid),
|
||||
.m_axi_wready(m_axi_wready),
|
||||
.m_axi_bid(12'H000),
|
||||
.m_axi_bresp(m_axi_bresp),
|
||||
.m_axi_buser(1'H0),
|
||||
.m_axi_bvalid(m_axi_bvalid),
|
||||
.m_axi_bready(m_axi_bready),
|
||||
.m_axi_arid(),
|
||||
.m_axi_araddr(m_axi_araddr),
|
||||
.m_axi_arlen(),
|
||||
.m_axi_arsize(),
|
||||
.m_axi_arburst(),
|
||||
.m_axi_arlock(),
|
||||
.m_axi_arcache(),
|
||||
.m_axi_arprot(m_axi_arprot),
|
||||
.m_axi_arregion(),
|
||||
.m_axi_arqos(),
|
||||
.m_axi_aruser(),
|
||||
.m_axi_arvalid(m_axi_arvalid),
|
||||
.m_axi_arready(m_axi_arready),
|
||||
.m_axi_rid(12'H000),
|
||||
.m_axi_rdata(m_axi_rdata),
|
||||
.m_axi_rresp(m_axi_rresp),
|
||||
.m_axi_rlast(1'H1),
|
||||
.m_axi_ruser(1'H0),
|
||||
.m_axi_rvalid(m_axi_rvalid),
|
||||
.m_axi_rready(m_axi_rready)
|
||||
);
|
||||
endmodule
|
||||
BIN
Binary file not shown.
+213
@@ -0,0 +1,213 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>xci</spirit:library>
|
||||
<spirit:name>unknown</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>system_bd_auto_pc_0</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="axi_protocol_converter" spirit:version="2.1"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF">S_AXI:M_AXI</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET">ARESETN</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN">system_bd_ps_system_0_FCLK_CLK0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_HZ">50000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN">system_bd_ps_system_0_FCLK_CLK0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ">50000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_OUTSTANDING">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_THREADS">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_OUTSTANDING">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_THREADS">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST.TYPE">INTERCONNECT</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN">system_bd_ps_system_0_FCLK_CLK0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ">50000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH">12</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL">AXI3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ADDR_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ARUSER_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_AWUSER_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_BUSER_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_DATA_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">12</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_RUSER_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_SUPPORTS_READ">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_SUPPORTS_USER_SIGNALS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_SUPPORTS_WRITE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_WUSER_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">zynq</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IGNORE_ID">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXI_PROTOCOL">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_PROTOCOL">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TRANSLATION_MODE">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDR_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">system_bd_auto_pc_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">12</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MI_PROTOCOL">AXI4LITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SI_PROTOCOL">AXI3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TRANSLATION_MODE">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z100</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">19</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1.3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:componentInstanceExtensions>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_BUSIF" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.ASSOCIATED_RESET" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLK.PHASE" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ID_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.MAX_BURST_LENGTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_READ_THREADS" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.NUM_WRITE_THREADS" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.READ_WRITE_MODE" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.RST.POLARITY" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION" xilinx:valueSource="auto" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE" xilinx:valueSource="auto_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ADDR_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ARUSER_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.AWUSER_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.BUSER_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.DATA_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ID_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MI_PROTOCOL" xilinx:valueSource="user" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.READ_WRITE_MODE" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.RUSER_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.SI_PROTOCOL" xilinx:valueSource="user" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.WUSER_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:componentInstanceExtensions>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
+4342
File diff suppressed because it is too large
Load Diff
+57
@@ -0,0 +1,57 @@
|
||||
# (c) Copyright 2012-2023 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
# DO NOT MODIFY THIS FILE.
|
||||
# #########################################################
|
||||
#
|
||||
# This XDC is used only in OOC mode for synthesis, implementation
|
||||
#
|
||||
# #########################################################
|
||||
|
||||
|
||||
create_clock -period 20 -name aclk [get_ports aclk]
|
||||
|
||||
|
||||
BIN
Binary file not shown.
BIN
Binary file not shown.
+87
@@ -0,0 +1,87 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Thu Mar 30 16:05:42 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ipi-bds/system_bd/ip/system_bd_auto_pc_0/system_bd_auto_pc_0_stub.v
|
||||
// Design : system_bd_auto_pc_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z100ffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "axi_protocol_converter_v2_1_19_axi_protocol_converter,Vivado 2019.1.3" *)
|
||||
module system_bd_auto_pc_0(aclk, aresetn, s_axi_awid, s_axi_awaddr,
|
||||
s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot,
|
||||
s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wid, s_axi_wdata, s_axi_wstrb, s_axi_wlast,
|
||||
s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_arid,
|
||||
s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache,
|
||||
s_axi_arprot, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp,
|
||||
s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awaddr, m_axi_awprot, m_axi_awvalid,
|
||||
m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wvalid, m_axi_wready, m_axi_bresp,
|
||||
m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arprot, m_axi_arvalid, m_axi_arready,
|
||||
m_axi_rdata, m_axi_rresp, m_axi_rvalid, m_axi_rready)
|
||||
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[3:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[1:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wid[11:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[3:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[1:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr[31:0],m_axi_awprot[2:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wvalid,m_axi_wready,m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_araddr[31:0],m_axi_arprot[2:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rvalid,m_axi_rready" */;
|
||||
input aclk;
|
||||
input aresetn;
|
||||
input [11:0]s_axi_awid;
|
||||
input [31:0]s_axi_awaddr;
|
||||
input [3:0]s_axi_awlen;
|
||||
input [2:0]s_axi_awsize;
|
||||
input [1:0]s_axi_awburst;
|
||||
input [1:0]s_axi_awlock;
|
||||
input [3:0]s_axi_awcache;
|
||||
input [2:0]s_axi_awprot;
|
||||
input [3:0]s_axi_awqos;
|
||||
input s_axi_awvalid;
|
||||
output s_axi_awready;
|
||||
input [11:0]s_axi_wid;
|
||||
input [31:0]s_axi_wdata;
|
||||
input [3:0]s_axi_wstrb;
|
||||
input s_axi_wlast;
|
||||
input s_axi_wvalid;
|
||||
output s_axi_wready;
|
||||
output [11:0]s_axi_bid;
|
||||
output [1:0]s_axi_bresp;
|
||||
output s_axi_bvalid;
|
||||
input s_axi_bready;
|
||||
input [11:0]s_axi_arid;
|
||||
input [31:0]s_axi_araddr;
|
||||
input [3:0]s_axi_arlen;
|
||||
input [2:0]s_axi_arsize;
|
||||
input [1:0]s_axi_arburst;
|
||||
input [1:0]s_axi_arlock;
|
||||
input [3:0]s_axi_arcache;
|
||||
input [2:0]s_axi_arprot;
|
||||
input [3:0]s_axi_arqos;
|
||||
input s_axi_arvalid;
|
||||
output s_axi_arready;
|
||||
output [11:0]s_axi_rid;
|
||||
output [31:0]s_axi_rdata;
|
||||
output [1:0]s_axi_rresp;
|
||||
output s_axi_rlast;
|
||||
output s_axi_rvalid;
|
||||
input s_axi_rready;
|
||||
output [31:0]m_axi_awaddr;
|
||||
output [2:0]m_axi_awprot;
|
||||
output m_axi_awvalid;
|
||||
input m_axi_awready;
|
||||
output [31:0]m_axi_wdata;
|
||||
output [3:0]m_axi_wstrb;
|
||||
output m_axi_wvalid;
|
||||
input m_axi_wready;
|
||||
input [1:0]m_axi_bresp;
|
||||
input m_axi_bvalid;
|
||||
output m_axi_bready;
|
||||
output [31:0]m_axi_araddr;
|
||||
output [2:0]m_axi_arprot;
|
||||
output m_axi_arvalid;
|
||||
input m_axi_arready;
|
||||
input [31:0]m_axi_rdata;
|
||||
input [1:0]m_axi_rresp;
|
||||
input m_axi_rvalid;
|
||||
output m_axi_rready;
|
||||
endmodule
|
||||
+88
@@ -0,0 +1,88 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Thu Mar 30 16:05:42 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ipi-bds/system_bd/ip/system_bd_auto_pc_0/system_bd_auto_pc_0_stub.vhdl
|
||||
-- Design : system_bd_auto_pc_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z100ffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity system_bd_auto_pc_0 is
|
||||
Port (
|
||||
aclk : in STD_LOGIC;
|
||||
aresetn : in STD_LOGIC;
|
||||
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_awvalid : in STD_LOGIC;
|
||||
s_axi_awready : out STD_LOGIC;
|
||||
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_wlast : in STD_LOGIC;
|
||||
s_axi_wvalid : in STD_LOGIC;
|
||||
s_axi_wready : out STD_LOGIC;
|
||||
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_bvalid : out STD_LOGIC;
|
||||
s_axi_bready : in STD_LOGIC;
|
||||
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_arvalid : in STD_LOGIC;
|
||||
s_axi_arready : out STD_LOGIC;
|
||||
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_rlast : out STD_LOGIC;
|
||||
s_axi_rvalid : out STD_LOGIC;
|
||||
s_axi_rready : in STD_LOGIC;
|
||||
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
m_axi_awvalid : out STD_LOGIC;
|
||||
m_axi_awready : in STD_LOGIC;
|
||||
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
m_axi_wvalid : out STD_LOGIC;
|
||||
m_axi_wready : in STD_LOGIC;
|
||||
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
m_axi_bvalid : in STD_LOGIC;
|
||||
m_axi_bready : out STD_LOGIC;
|
||||
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
m_axi_arvalid : out STD_LOGIC;
|
||||
m_axi_arready : in STD_LOGIC;
|
||||
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
m_axi_rvalid : in STD_LOGIC;
|
||||
m_axi_rready : out STD_LOGIC
|
||||
);
|
||||
|
||||
end system_bd_auto_pc_0;
|
||||
|
||||
architecture stub of system_bd_auto_pc_0 is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "aclk,aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[3:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[1:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wid[11:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[3:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[1:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr[31:0],m_axi_awprot[2:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wvalid,m_axi_wready,m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_araddr[31:0],m_axi_arprot[2:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rvalid,m_axi_rready";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "axi_protocol_converter_v2_1_19_axi_protocol_converter,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
+358
@@ -0,0 +1,358 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
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|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>xci</spirit:library>
|
||||
<spirit:name>unknown</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>system_bd_axi_interconnect_0</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="axi_interconnect" spirit:version="2.1"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">system_bd_axi_interconnect_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_ADVANCED_OPTIONS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_PROTOCOL_CHECKERS">0</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S15_HAS_DATA_FIFO">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.S15_HAS_REGSLICE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.STRATEGY">0</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SYNCHRONIZATION_STAGES">3</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.XBAR_DATA_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z100</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator_AppCore</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">20</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1.3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:componentInstanceExtensions>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.NUM_MI" xilinx:valueSource="user"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:componentInstanceExtensions>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
+1642
File diff suppressed because it is too large
Load Diff
+245
@@ -0,0 +1,245 @@
|
||||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: analog.com:user:axi_spi_engine:1.0
|
||||
// IP Revision: 1
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* IP_DEFINITION_SOURCE = "package_project" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module system_bd_axi_spi_engine_0 (
|
||||
s_axi_aclk,
|
||||
s_axi_aresetn,
|
||||
s_axi_awvalid,
|
||||
s_axi_awaddr,
|
||||
s_axi_awready,
|
||||
s_axi_awprot,
|
||||
s_axi_wvalid,
|
||||
s_axi_wdata,
|
||||
s_axi_wstrb,
|
||||
s_axi_wready,
|
||||
s_axi_bvalid,
|
||||
s_axi_bresp,
|
||||
s_axi_bready,
|
||||
s_axi_arvalid,
|
||||
s_axi_araddr,
|
||||
s_axi_arready,
|
||||
s_axi_arprot,
|
||||
s_axi_rvalid,
|
||||
s_axi_rready,
|
||||
s_axi_rresp,
|
||||
s_axi_rdata,
|
||||
irq,
|
||||
spi_clk,
|
||||
spi_resetn,
|
||||
cmd_ready,
|
||||
cmd_valid,
|
||||
cmd_data,
|
||||
sdo_data_ready,
|
||||
sdo_data_valid,
|
||||
sdo_data,
|
||||
sdi_data_ready,
|
||||
sdi_data_valid,
|
||||
sdi_data,
|
||||
sync_ready,
|
||||
sync_valid,
|
||||
sync_data
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi_aclk, ASSOCIATED_BUSIF s_axi, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0, XIL_INTERFACENAME spi_engine_offload_ctrl0_s_axi_signal_clock, ASSOCIATED_BUSIF spi_engine_offload_ctrl0:s_axi, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN system_bd_ps_system_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 s_axi_aclk CLK, xilinx.com:signal:clock:1.0 spi_engine_offload_ctrl0_s_axi_signal_clock CLK" *)
|
||||
input wire s_axi_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0, XIL_INTERFACENAME spi_engine_offload_ctrl0_s_axi_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 s_axi_aresetn RST, xilinx.com:signal:reset:1.0 spi_engine_offload_ctrl0_s_axi_signal_reset RST" *)
|
||||
input wire s_axi_aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWVALID" *)
|
||||
input wire s_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWADDR" *)
|
||||
input wire [15 : 0] s_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWREADY" *)
|
||||
output wire s_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWPROT" *)
|
||||
input wire [2 : 0] s_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WVALID" *)
|
||||
input wire s_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WDATA" *)
|
||||
input wire [31 : 0] s_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WSTRB" *)
|
||||
input wire [3 : 0] s_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WREADY" *)
|
||||
output wire s_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BVALID" *)
|
||||
output wire s_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BRESP" *)
|
||||
output wire [1 : 0] s_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BREADY" *)
|
||||
input wire s_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARVALID" *)
|
||||
input wire s_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARADDR" *)
|
||||
input wire [15 : 0] s_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARREADY" *)
|
||||
output wire s_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARPROT" *)
|
||||
input wire [2 : 0] s_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RVALID" *)
|
||||
output wire s_axi_rvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RREADY" *)
|
||||
input wire s_axi_rready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RRESP" *)
|
||||
output wire [1 : 0] s_axi_rresp;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 50000000, ID_WIDTH 0, ADDR_WIDTH 16, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN system_bd_ps_system_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WR\
|
||||
ITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RDATA" *)
|
||||
output wire [31 : 0] s_axi_rdata;
|
||||
output wire irq;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME spi_engine_ctrl_signal_clock, ASSOCIATED_BUSIF spi_engine_ctrl, ASSOCIATED_RESET spi_resetn, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN system_bd_ps_system_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 spi_engine_ctrl_signal_clock CLK" *)
|
||||
input wire spi_clk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME spi_engine_ctrl_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 spi_engine_ctrl_signal_reset RST" *)
|
||||
output wire spi_resetn;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl CMD_READY" *)
|
||||
input wire cmd_ready;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl CMD_VALID" *)
|
||||
output wire cmd_valid;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl CMD_DATA" *)
|
||||
output wire [15 : 0] cmd_data;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDO_READY" *)
|
||||
input wire sdo_data_ready;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDO_VALID" *)
|
||||
output wire sdo_data_valid;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDO_DATA" *)
|
||||
output wire [7 : 0] sdo_data;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDI_READY" *)
|
||||
output wire sdi_data_ready;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDI_VALID" *)
|
||||
input wire sdi_data_valid;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDI_DATA" *)
|
||||
input wire [7 : 0] sdi_data;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SYNC_READY" *)
|
||||
output wire sync_ready;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SYNC_VALID" *)
|
||||
input wire sync_valid;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SYNC_DATA" *)
|
||||
input wire [7 : 0] sync_data;
|
||||
|
||||
axi_spi_engine #(
|
||||
.CMD_FIFO_ADDRESS_WIDTH(4),
|
||||
.SYNC_FIFO_ADDRESS_WIDTH(4),
|
||||
.SDO_FIFO_ADDRESS_WIDTH(5),
|
||||
.SDI_FIFO_ADDRESS_WIDTH(5),
|
||||
.MM_IF_TYPE(0),
|
||||
.ASYNC_SPI_CLK(1'B0),
|
||||
.NUM_OFFLOAD(0),
|
||||
.OFFLOAD0_CMD_MEM_ADDRESS_WIDTH(4),
|
||||
.OFFLOAD0_SDO_MEM_ADDRESS_WIDTH(4),
|
||||
.ID(0),
|
||||
.DATA_WIDTH(8),
|
||||
.NUM_OF_SDI(1)
|
||||
) inst (
|
||||
.s_axi_aclk(s_axi_aclk),
|
||||
.s_axi_aresetn(s_axi_aresetn),
|
||||
.s_axi_awvalid(s_axi_awvalid),
|
||||
.s_axi_awaddr(s_axi_awaddr),
|
||||
.s_axi_awready(s_axi_awready),
|
||||
.s_axi_awprot(s_axi_awprot),
|
||||
.s_axi_wvalid(s_axi_wvalid),
|
||||
.s_axi_wdata(s_axi_wdata),
|
||||
.s_axi_wstrb(s_axi_wstrb),
|
||||
.s_axi_wready(s_axi_wready),
|
||||
.s_axi_bvalid(s_axi_bvalid),
|
||||
.s_axi_bresp(s_axi_bresp),
|
||||
.s_axi_bready(s_axi_bready),
|
||||
.s_axi_arvalid(s_axi_arvalid),
|
||||
.s_axi_araddr(s_axi_araddr),
|
||||
.s_axi_arready(s_axi_arready),
|
||||
.s_axi_arprot(s_axi_arprot),
|
||||
.s_axi_rvalid(s_axi_rvalid),
|
||||
.s_axi_rready(s_axi_rready),
|
||||
.s_axi_rresp(s_axi_rresp),
|
||||
.s_axi_rdata(s_axi_rdata),
|
||||
.up_clk(1'B0),
|
||||
.up_rstn(1'B0),
|
||||
.up_wreq(1'B0),
|
||||
.up_waddr(14'B0),
|
||||
.up_wdata(32'B0),
|
||||
.up_wack(),
|
||||
.up_rreq(1'B0),
|
||||
.up_raddr(14'B0),
|
||||
.up_rdata(),
|
||||
.up_rack(),
|
||||
.irq(irq),
|
||||
.spi_clk(spi_clk),
|
||||
.spi_resetn(spi_resetn),
|
||||
.cmd_ready(cmd_ready),
|
||||
.cmd_valid(cmd_valid),
|
||||
.cmd_data(cmd_data),
|
||||
.sdo_data_ready(sdo_data_ready),
|
||||
.sdo_data_valid(sdo_data_valid),
|
||||
.sdo_data(sdo_data),
|
||||
.sdi_data_ready(sdi_data_ready),
|
||||
.sdi_data_valid(sdi_data_valid),
|
||||
.sdi_data(sdi_data),
|
||||
.sync_ready(sync_ready),
|
||||
.sync_valid(sync_valid),
|
||||
.sync_data(sync_data),
|
||||
.offload0_cmd_wr_en(),
|
||||
.offload0_cmd_wr_data(),
|
||||
.offload0_sdo_wr_en(),
|
||||
.offload0_sdo_wr_data(),
|
||||
.offload0_mem_reset(),
|
||||
.offload0_enable(),
|
||||
.offload0_enabled(1'B0),
|
||||
.offload_sync_ready(),
|
||||
.offload_sync_valid(1'B0),
|
||||
.offload_sync_data(8'B0)
|
||||
);
|
||||
endmodule
|
||||
+245
@@ -0,0 +1,245 @@
|
||||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: analog.com:user:axi_spi_engine:1.0
|
||||
// IP Revision: 1
|
||||
|
||||
(* X_CORE_INFO = "axi_spi_engine,Vivado 2019.1.3" *)
|
||||
(* CHECK_LICENSE_TYPE = "system_bd_axi_spi_engine_0,axi_spi_engine,{}" *)
|
||||
(* IP_DEFINITION_SOURCE = "package_project" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module system_bd_axi_spi_engine_0 (
|
||||
s_axi_aclk,
|
||||
s_axi_aresetn,
|
||||
s_axi_awvalid,
|
||||
s_axi_awaddr,
|
||||
s_axi_awready,
|
||||
s_axi_awprot,
|
||||
s_axi_wvalid,
|
||||
s_axi_wdata,
|
||||
s_axi_wstrb,
|
||||
s_axi_wready,
|
||||
s_axi_bvalid,
|
||||
s_axi_bresp,
|
||||
s_axi_bready,
|
||||
s_axi_arvalid,
|
||||
s_axi_araddr,
|
||||
s_axi_arready,
|
||||
s_axi_arprot,
|
||||
s_axi_rvalid,
|
||||
s_axi_rready,
|
||||
s_axi_rresp,
|
||||
s_axi_rdata,
|
||||
irq,
|
||||
spi_clk,
|
||||
spi_resetn,
|
||||
cmd_ready,
|
||||
cmd_valid,
|
||||
cmd_data,
|
||||
sdo_data_ready,
|
||||
sdo_data_valid,
|
||||
sdo_data,
|
||||
sdi_data_ready,
|
||||
sdi_data_valid,
|
||||
sdi_data,
|
||||
sync_ready,
|
||||
sync_valid,
|
||||
sync_data
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi_aclk, ASSOCIATED_BUSIF s_axi, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0, XIL_INTERFACENAME spi_engine_offload_ctrl0_s_axi_signal_clock, ASSOCIATED_BUSIF spi_engine_offload_ctrl0:s_axi, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN system_bd_ps_system_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 s_axi_aclk CLK, xilinx.com:signal:clock:1.0 spi_engine_offload_ctrl0_s_axi_signal_clock CLK" *)
|
||||
input wire s_axi_aclk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0, XIL_INTERFACENAME spi_engine_offload_ctrl0_s_axi_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 s_axi_aresetn RST, xilinx.com:signal:reset:1.0 spi_engine_offload_ctrl0_s_axi_signal_reset RST" *)
|
||||
input wire s_axi_aresetn;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWVALID" *)
|
||||
input wire s_axi_awvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWADDR" *)
|
||||
input wire [15 : 0] s_axi_awaddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWREADY" *)
|
||||
output wire s_axi_awready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi AWPROT" *)
|
||||
input wire [2 : 0] s_axi_awprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WVALID" *)
|
||||
input wire s_axi_wvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WDATA" *)
|
||||
input wire [31 : 0] s_axi_wdata;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WSTRB" *)
|
||||
input wire [3 : 0] s_axi_wstrb;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi WREADY" *)
|
||||
output wire s_axi_wready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BVALID" *)
|
||||
output wire s_axi_bvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BRESP" *)
|
||||
output wire [1 : 0] s_axi_bresp;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi BREADY" *)
|
||||
input wire s_axi_bready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARVALID" *)
|
||||
input wire s_axi_arvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARADDR" *)
|
||||
input wire [15 : 0] s_axi_araddr;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARREADY" *)
|
||||
output wire s_axi_arready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi ARPROT" *)
|
||||
input wire [2 : 0] s_axi_arprot;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RVALID" *)
|
||||
output wire s_axi_rvalid;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RREADY" *)
|
||||
input wire s_axi_rready;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RRESP" *)
|
||||
output wire [1 : 0] s_axi_rresp;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME s_axi, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 50000000, ID_WIDTH 0, ADDR_WIDTH 16, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN system_bd_ps_system_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WR\
|
||||
ITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi RDATA" *)
|
||||
output wire [31 : 0] s_axi_rdata;
|
||||
output wire irq;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME spi_engine_ctrl_signal_clock, ASSOCIATED_BUSIF spi_engine_ctrl, ASSOCIATED_RESET spi_resetn, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN system_bd_ps_system_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 spi_engine_ctrl_signal_clock CLK" *)
|
||||
input wire spi_clk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME spi_engine_ctrl_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 spi_engine_ctrl_signal_reset RST" *)
|
||||
output wire spi_resetn;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl CMD_READY" *)
|
||||
input wire cmd_ready;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl CMD_VALID" *)
|
||||
output wire cmd_valid;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl CMD_DATA" *)
|
||||
output wire [15 : 0] cmd_data;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDO_READY" *)
|
||||
input wire sdo_data_ready;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDO_VALID" *)
|
||||
output wire sdo_data_valid;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDO_DATA" *)
|
||||
output wire [7 : 0] sdo_data;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDI_READY" *)
|
||||
output wire sdi_data_ready;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDI_VALID" *)
|
||||
input wire sdi_data_valid;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SDI_DATA" *)
|
||||
input wire [7 : 0] sdi_data;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SYNC_READY" *)
|
||||
output wire sync_ready;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SYNC_VALID" *)
|
||||
input wire sync_valid;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 spi_engine_ctrl SYNC_DATA" *)
|
||||
input wire [7 : 0] sync_data;
|
||||
|
||||
axi_spi_engine #(
|
||||
.CMD_FIFO_ADDRESS_WIDTH(4),
|
||||
.SYNC_FIFO_ADDRESS_WIDTH(4),
|
||||
.SDO_FIFO_ADDRESS_WIDTH(5),
|
||||
.SDI_FIFO_ADDRESS_WIDTH(5),
|
||||
.MM_IF_TYPE(0),
|
||||
.ASYNC_SPI_CLK(1'B0),
|
||||
.NUM_OFFLOAD(0),
|
||||
.OFFLOAD0_CMD_MEM_ADDRESS_WIDTH(4),
|
||||
.OFFLOAD0_SDO_MEM_ADDRESS_WIDTH(4),
|
||||
.ID(0),
|
||||
.DATA_WIDTH(8),
|
||||
.NUM_OF_SDI(1)
|
||||
) inst (
|
||||
.s_axi_aclk(s_axi_aclk),
|
||||
.s_axi_aresetn(s_axi_aresetn),
|
||||
.s_axi_awvalid(s_axi_awvalid),
|
||||
.s_axi_awaddr(s_axi_awaddr),
|
||||
.s_axi_awready(s_axi_awready),
|
||||
.s_axi_awprot(s_axi_awprot),
|
||||
.s_axi_wvalid(s_axi_wvalid),
|
||||
.s_axi_wdata(s_axi_wdata),
|
||||
.s_axi_wstrb(s_axi_wstrb),
|
||||
.s_axi_wready(s_axi_wready),
|
||||
.s_axi_bvalid(s_axi_bvalid),
|
||||
.s_axi_bresp(s_axi_bresp),
|
||||
.s_axi_bready(s_axi_bready),
|
||||
.s_axi_arvalid(s_axi_arvalid),
|
||||
.s_axi_araddr(s_axi_araddr),
|
||||
.s_axi_arready(s_axi_arready),
|
||||
.s_axi_arprot(s_axi_arprot),
|
||||
.s_axi_rvalid(s_axi_rvalid),
|
||||
.s_axi_rready(s_axi_rready),
|
||||
.s_axi_rresp(s_axi_rresp),
|
||||
.s_axi_rdata(s_axi_rdata),
|
||||
.up_clk(1'B0),
|
||||
.up_rstn(1'B0),
|
||||
.up_wreq(1'B0),
|
||||
.up_waddr(14'B0),
|
||||
.up_wdata(32'B0),
|
||||
.up_wack(),
|
||||
.up_rreq(1'B0),
|
||||
.up_raddr(14'B0),
|
||||
.up_rdata(),
|
||||
.up_rack(),
|
||||
.irq(irq),
|
||||
.spi_clk(spi_clk),
|
||||
.spi_resetn(spi_resetn),
|
||||
.cmd_ready(cmd_ready),
|
||||
.cmd_valid(cmd_valid),
|
||||
.cmd_data(cmd_data),
|
||||
.sdo_data_ready(sdo_data_ready),
|
||||
.sdo_data_valid(sdo_data_valid),
|
||||
.sdo_data(sdo_data),
|
||||
.sdi_data_ready(sdi_data_ready),
|
||||
.sdi_data_valid(sdi_data_valid),
|
||||
.sdi_data(sdi_data),
|
||||
.sync_ready(sync_ready),
|
||||
.sync_valid(sync_valid),
|
||||
.sync_data(sync_data),
|
||||
.offload0_cmd_wr_en(),
|
||||
.offload0_cmd_wr_data(),
|
||||
.offload0_sdo_wr_en(),
|
||||
.offload0_sdo_wr_data(),
|
||||
.offload0_mem_reset(),
|
||||
.offload0_enable(),
|
||||
.offload0_enabled(1'B0),
|
||||
.offload_sync_ready(),
|
||||
.offload_sync_valid(1'B0),
|
||||
.offload_sync_data(8'B0)
|
||||
);
|
||||
endmodule
|
||||
BIN
Binary file not shown.
+148
@@ -0,0 +1,148 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>xci</spirit:library>
|
||||
<spirit:name>unknown</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>system_bd_axi_spi_engine_0</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="analog.com" spirit:library="user" spirit:name="axi_spi_engine" spirit:version="1.0"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SPI_ENGINE_CTRL_SIGNAL_CLOCK.CLK_DOMAIN">system_bd_ps_system_0_FCLK_CLK0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SPI_ENGINE_CTRL_SIGNAL_CLOCK.FREQ_HZ">50000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SPI_ENGINE_CTRL_SIGNAL_CLOCK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SPI_ENGINE_CTRL_SIGNAL_CLOCK.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SPI_ENGINE_CTRL_SIGNAL_RESET.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SPI_ENGINE_OFFLOAD_CTRL0_S_AXI_SIGNAL_CLOCK.CLK_DOMAIN">system_bd_ps_system_0_FCLK_CLK0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SPI_ENGINE_OFFLOAD_CTRL0_S_AXI_SIGNAL_CLOCK.FREQ_HZ">50000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SPI_ENGINE_OFFLOAD_CTRL0_S_AXI_SIGNAL_CLOCK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SPI_ENGINE_OFFLOAD_CTRL0_S_AXI_SIGNAL_CLOCK.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SPI_ENGINE_OFFLOAD_CTRL0_S_AXI_SIGNAL_RESET.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN">system_bd_ps_system_0_FCLK_CLK0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ">50000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ARESETN.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.ASYNC_SPI_CLK">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.CMD_FIFO_ADDRESS_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DATA_WIDTH">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.ID">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.MM_IF_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.NUM_OFFLOAD">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.NUM_OF_SDI">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.OFFLOAD0_CMD_MEM_ADDRESS_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.OFFLOAD0_SDO_MEM_ADDRESS_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SDI_FIFO_ADDRESS_WIDTH">5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SDO_FIFO_ADDRESS_WIDTH">5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SYNC_FIFO_ADDRESS_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.OFFLOAD0_CMD_MEM_ADDRESS_WIDTH">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_ENABLEMENT.OFFLOAD0_SDO_MEM_ADDRESS_WIDTH">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ASYNC_SPI_CLK">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CMD_FIFO_ADDRESS_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">system_bd_axi_spi_engine_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MM_IF_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_OFFLOAD">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_OF_SDI">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OFFLOAD0_CMD_MEM_ADDRESS_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OFFLOAD0_SDO_MEM_ADDRESS_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SDI_FIFO_ADDRESS_WIDTH">5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SDO_FIFO_ADDRESS_WIDTH">5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SYNC_FIFO_ADDRESS_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z100</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1.3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:componentInstanceExtensions>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SPI_ENGINE_CTRL_SIGNAL_CLOCK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SPI_ENGINE_CTRL_SIGNAL_CLOCK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SPI_ENGINE_OFFLOAD_CTRL0_S_AXI_SIGNAL_CLOCK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SPI_ENGINE_OFFLOAD_CTRL0_S_AXI_SIGNAL_CLOCK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.BUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ID_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.MAX_BURST_LENGTH" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_OUTSTANDING" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_READ_THREADS" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_OUTSTANDING" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.NUM_WRITE_THREADS" xilinx:valueSource="constant_prop" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.READ_WRITE_MODE" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.RUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST" xilinx:valueSource="auto" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.WUSER_WIDTH" xilinx:valueSource="constant" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.DATA_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.NUM_OF_SDI" xilinx:valueSource="user"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:componentInstanceExtensions>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
+2692
File diff suppressed because it is too large
Load Diff
+1
@@ -0,0 +1 @@
|
||||
|
||||
BIN
Binary file not shown.
BIN
Binary file not shown.
+60
@@ -0,0 +1,60 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Thu Mar 30 16:05:23 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ipi-bds/system_bd/ip/system_bd_axi_spi_engine_0/system_bd_axi_spi_engine_0_stub.v
|
||||
// Design : system_bd_axi_spi_engine_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z100ffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "axi_spi_engine,Vivado 2019.1.3" *)
|
||||
module system_bd_axi_spi_engine_0(s_axi_aclk, s_axi_aresetn, s_axi_awvalid,
|
||||
s_axi_awaddr, s_axi_awready, s_axi_awprot, s_axi_wvalid, s_axi_wdata, s_axi_wstrb,
|
||||
s_axi_wready, s_axi_bvalid, s_axi_bresp, s_axi_bready, s_axi_arvalid, s_axi_araddr,
|
||||
s_axi_arready, s_axi_arprot, s_axi_rvalid, s_axi_rready, s_axi_rresp, s_axi_rdata, irq,
|
||||
spi_clk, spi_resetn, cmd_ready, cmd_valid, cmd_data, sdo_data_ready, sdo_data_valid, sdo_data,
|
||||
sdi_data_ready, sdi_data_valid, sdi_data, sync_ready, sync_valid, sync_data)
|
||||
/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awvalid,s_axi_awaddr[15:0],s_axi_awready,s_axi_awprot[2:0],s_axi_wvalid,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wready,s_axi_bvalid,s_axi_bresp[1:0],s_axi_bready,s_axi_arvalid,s_axi_araddr[15:0],s_axi_arready,s_axi_arprot[2:0],s_axi_rvalid,s_axi_rready,s_axi_rresp[1:0],s_axi_rdata[31:0],irq,spi_clk,spi_resetn,cmd_ready,cmd_valid,cmd_data[15:0],sdo_data_ready,sdo_data_valid,sdo_data[7:0],sdi_data_ready,sdi_data_valid,sdi_data[7:0],sync_ready,sync_valid,sync_data[7:0]" */;
|
||||
input s_axi_aclk;
|
||||
input s_axi_aresetn;
|
||||
input s_axi_awvalid;
|
||||
input [15:0]s_axi_awaddr;
|
||||
output s_axi_awready;
|
||||
input [2:0]s_axi_awprot;
|
||||
input s_axi_wvalid;
|
||||
input [31:0]s_axi_wdata;
|
||||
input [3:0]s_axi_wstrb;
|
||||
output s_axi_wready;
|
||||
output s_axi_bvalid;
|
||||
output [1:0]s_axi_bresp;
|
||||
input s_axi_bready;
|
||||
input s_axi_arvalid;
|
||||
input [15:0]s_axi_araddr;
|
||||
output s_axi_arready;
|
||||
input [2:0]s_axi_arprot;
|
||||
output s_axi_rvalid;
|
||||
input s_axi_rready;
|
||||
output [1:0]s_axi_rresp;
|
||||
output [31:0]s_axi_rdata;
|
||||
output irq;
|
||||
input spi_clk;
|
||||
output spi_resetn;
|
||||
input cmd_ready;
|
||||
output cmd_valid;
|
||||
output [15:0]cmd_data;
|
||||
input sdo_data_ready;
|
||||
output sdo_data_valid;
|
||||
output [7:0]sdo_data;
|
||||
output sdi_data_ready;
|
||||
input sdi_data_valid;
|
||||
input [7:0]sdi_data;
|
||||
output sync_ready;
|
||||
input sync_valid;
|
||||
input [7:0]sync_data;
|
||||
endmodule
|
||||
+65
@@ -0,0 +1,65 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Thu Mar 30 16:05:23 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ipi-bds/system_bd/ip/system_bd_axi_spi_engine_0/system_bd_axi_spi_engine_0_stub.vhdl
|
||||
-- Design : system_bd_axi_spi_engine_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z100ffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity system_bd_axi_spi_engine_0 is
|
||||
Port (
|
||||
s_axi_aclk : in STD_LOGIC;
|
||||
s_axi_aresetn : in STD_LOGIC;
|
||||
s_axi_awvalid : in STD_LOGIC;
|
||||
s_axi_awaddr : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
s_axi_awready : out STD_LOGIC;
|
||||
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
s_axi_wvalid : in STD_LOGIC;
|
||||
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_wready : out STD_LOGIC;
|
||||
s_axi_bvalid : out STD_LOGIC;
|
||||
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_bready : in STD_LOGIC;
|
||||
s_axi_arvalid : in STD_LOGIC;
|
||||
s_axi_araddr : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
s_axi_arready : out STD_LOGIC;
|
||||
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
s_axi_rvalid : out STD_LOGIC;
|
||||
s_axi_rready : in STD_LOGIC;
|
||||
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
irq : out STD_LOGIC;
|
||||
spi_clk : in STD_LOGIC;
|
||||
spi_resetn : out STD_LOGIC;
|
||||
cmd_ready : in STD_LOGIC;
|
||||
cmd_valid : out STD_LOGIC;
|
||||
cmd_data : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
sdo_data_ready : in STD_LOGIC;
|
||||
sdo_data_valid : out STD_LOGIC;
|
||||
sdo_data : out STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
sdi_data_ready : out STD_LOGIC;
|
||||
sdi_data_valid : in STD_LOGIC;
|
||||
sdi_data : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
sync_ready : out STD_LOGIC;
|
||||
sync_valid : in STD_LOGIC;
|
||||
sync_data : in STD_LOGIC_VECTOR ( 7 downto 0 )
|
||||
);
|
||||
|
||||
end system_bd_axi_spi_engine_0;
|
||||
|
||||
architecture stub of system_bd_axi_spi_engine_0 is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "s_axi_aclk,s_axi_aresetn,s_axi_awvalid,s_axi_awaddr[15:0],s_axi_awready,s_axi_awprot[2:0],s_axi_wvalid,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wready,s_axi_bvalid,s_axi_bresp[1:0],s_axi_bready,s_axi_arvalid,s_axi_araddr[15:0],s_axi_arready,s_axi_arprot[2:0],s_axi_rvalid,s_axi_rready,s_axi_rresp[1:0],s_axi_rdata[31:0],irq,spi_clk,spi_resetn,cmd_ready,cmd_valid,cmd_data[15:0],sdo_data_ready,sdo_data_valid,sdo_data[7:0],sdi_data_ready,sdi_data_valid,sdi_data[7:0],sync_ready,sync_valid,sync_data[7:0]";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "axi_spi_engine,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
+3934
File diff suppressed because it is too large
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,139 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2018 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
******************************************************************************/
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file ps7_init.h
|
||||
*
|
||||
* This file can be included in FSBL code
|
||||
* to get prototype of ps7_init() function
|
||||
* and error codes
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
//typedef unsigned int u32;
|
||||
|
||||
|
||||
/** do we need to make this name more unique ? **/
|
||||
//extern u32 ps7_init_data[];
|
||||
extern unsigned long * ps7_ddr_init_data;
|
||||
extern unsigned long * ps7_mio_init_data;
|
||||
extern unsigned long * ps7_pll_init_data;
|
||||
extern unsigned long * ps7_clock_init_data;
|
||||
extern unsigned long * ps7_peripherals_init_data;
|
||||
|
||||
|
||||
|
||||
#define OPCODE_EXIT 0U
|
||||
#define OPCODE_CLEAR 1U
|
||||
#define OPCODE_WRITE 2U
|
||||
#define OPCODE_MASKWRITE 3U
|
||||
#define OPCODE_MASKPOLL 4U
|
||||
#define OPCODE_MASKDELAY 5U
|
||||
#define NEW_PS7_ERR_CODE 1
|
||||
|
||||
/* Encode number of arguments in last nibble */
|
||||
#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
|
||||
#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
|
||||
#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
|
||||
#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
|
||||
#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
|
||||
#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
|
||||
|
||||
/* Returns codes of PS7_Init */
|
||||
#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
|
||||
#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
|
||||
#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
|
||||
#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
|
||||
#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
|
||||
#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
|
||||
|
||||
|
||||
/* Silicon Versions */
|
||||
#define PCW_SILICON_VERSION_1 0
|
||||
#define PCW_SILICON_VERSION_2 1
|
||||
#define PCW_SILICON_VERSION_3 2
|
||||
|
||||
/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
|
||||
#define PS7_POST_CONFIG
|
||||
|
||||
/* Freq of all peripherals */
|
||||
|
||||
#define APU_FREQ 666666687
|
||||
#define DDR_FREQ 533333374
|
||||
#define DCI_FREQ 10158730
|
||||
#define QSPI_FREQ 200000000
|
||||
#define SMC_FREQ 10000000
|
||||
#define ENET0_FREQ 10000000
|
||||
#define ENET1_FREQ 10000000
|
||||
#define USB0_FREQ 60000000
|
||||
#define USB1_FREQ 60000000
|
||||
#define SDIO_FREQ 10000000
|
||||
#define UART_FREQ 10000000
|
||||
#define SPI_FREQ 10000000
|
||||
#define I2C_FREQ 111111115
|
||||
#define WDT_FREQ 111111115
|
||||
#define TTC_FREQ 50000000
|
||||
#define CAN_FREQ 10000000
|
||||
#define PCAP_FREQ 200000000
|
||||
#define TPIU_FREQ 200000000
|
||||
#define FPGA0_FREQ 50000000
|
||||
#define FPGA1_FREQ 200000000
|
||||
#define FPGA2_FREQ 10000000
|
||||
#define FPGA3_FREQ 10000000
|
||||
|
||||
|
||||
/* For delay calculation using global registers*/
|
||||
#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
|
||||
#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
|
||||
#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
|
||||
#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
|
||||
|
||||
int ps7_config( unsigned long*);
|
||||
int ps7_init();
|
||||
int ps7_post_config();
|
||||
int ps7_debug();
|
||||
char* getPS7MessageInfo(unsigned key);
|
||||
|
||||
void perf_start_clock(void);
|
||||
void perf_disable_clock(void);
|
||||
void perf_reset_clock(void);
|
||||
void perf_reset_and_start_timer();
|
||||
int get_number_of_cycles_for_delay(unsigned int delay);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
+133130
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,790 @@
|
||||
proc ps7_pll_init_data_3_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000110 0x003FFFF0 0x000FA220
|
||||
mask_write 0XF8000100 0x0007F000 0x00028000
|
||||
mask_write 0XF8000100 0x00000010 0x00000010
|
||||
mask_write 0XF8000100 0x00000001 0x00000001
|
||||
mask_write 0XF8000100 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000001
|
||||
mask_write 0XF8000100 0x00000010 0x00000000
|
||||
mask_write 0XF8000120 0x1F003F30 0x1F000200
|
||||
mask_write 0XF8000114 0x003FFFF0 0x0012C220
|
||||
mask_write 0XF8000104 0x0007F000 0x00020000
|
||||
mask_write 0XF8000104 0x00000010 0x00000010
|
||||
mask_write 0XF8000104 0x00000001 0x00000001
|
||||
mask_write 0XF8000104 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000002
|
||||
mask_write 0XF8000104 0x00000010 0x00000000
|
||||
mask_write 0XF8000124 0xFFF00003 0x0C200003
|
||||
mask_write 0XF8000118 0x003FFFF0 0x000FA240
|
||||
mask_write 0XF8000108 0x0007F000 0x00036000
|
||||
mask_write 0XF8000108 0x00000010 0x00000010
|
||||
mask_write 0XF8000108 0x00000001 0x00000001
|
||||
mask_write 0XF8000108 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000004
|
||||
mask_write 0XF8000108 0x00000010 0x00000000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_clock_init_data_3_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000128 0x03F03F01 0x00700F01
|
||||
mask_write 0XF800014C 0x00003F31 0x00000901
|
||||
mask_write 0XF8000168 0x00003F31 0x00000901
|
||||
mask_write 0XF8000170 0x03F03F30 0x00600600
|
||||
mask_write 0XF8000180 0x03F03F30 0x00300300
|
||||
mask_write 0XF80001C4 0x00000001 0x00000001
|
||||
mask_write 0XF800012C 0x01FFCCCD 0x01CC000D
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_ddr_init_data_3_0 {} {
|
||||
mask_write 0XF8006000 0x0001FFFF 0x00000084
|
||||
mask_write 0XF8006004 0x0007FFFF 0x00001082
|
||||
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
|
||||
mask_write 0XF800600C 0x03FFFFFF 0x02001001
|
||||
mask_write 0XF8006010 0x03FFFFFF 0x00014001
|
||||
mask_write 0XF8006014 0x001FFFFF 0x0004285B
|
||||
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
|
||||
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
|
||||
mask_write 0XF8006020 0x7FDFFFFC 0x270872D0
|
||||
mask_write 0XF8006024 0x0FFFFFC3 0x00000000
|
||||
mask_write 0XF8006028 0x00003FFF 0x00002007
|
||||
mask_write 0XF800602C 0xFFFFFFFF 0x00000008
|
||||
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
|
||||
mask_write 0XF8006034 0x13FF3FFF 0x000116D4
|
||||
mask_write 0XF8006038 0x00000003 0x00000000
|
||||
mask_write 0XF800603C 0x000FFFFF 0x00000666
|
||||
mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
|
||||
mask_write 0XF8006044 0x0FFFFFFF 0x0F555555
|
||||
mask_write 0XF8006048 0x0003F03F 0x0003C008
|
||||
mask_write 0XF8006050 0xFF0F8FFF 0x77010800
|
||||
mask_write 0XF8006058 0x00010000 0x00000000
|
||||
mask_write 0XF800605C 0x0000FFFF 0x00005003
|
||||
mask_write 0XF8006060 0x000017FF 0x0000003E
|
||||
mask_write 0XF8006064 0x00021FE0 0x00020000
|
||||
mask_write 0XF8006068 0x03FFFFFF 0x00284141
|
||||
mask_write 0XF800606C 0x0000FFFF 0x00001610
|
||||
mask_write 0XF8006078 0x03FFFFFF 0x00466111
|
||||
mask_write 0XF800607C 0x000FFFFF 0x00032222
|
||||
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
|
||||
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
|
||||
mask_write 0XF80060AC 0x000001FF 0x000001FE
|
||||
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
|
||||
mask_write 0XF80060B4 0x00000200 0x00000200
|
||||
mask_write 0XF80060B8 0x01FFFFFF 0x00200066
|
||||
mask_write 0XF80060C4 0x00000003 0x00000000
|
||||
mask_write 0XF80060C8 0x000000FF 0x00000000
|
||||
mask_write 0XF80060DC 0x00000001 0x00000000
|
||||
mask_write 0XF80060F0 0x0000FFFF 0x00000000
|
||||
mask_write 0XF80060F4 0x0000000F 0x00000008
|
||||
mask_write 0XF8006114 0x000000FF 0x00000000
|
||||
mask_write 0XF8006118 0x7FFFFFCF 0x40000001
|
||||
mask_write 0XF800611C 0x7FFFFFCF 0x40000001
|
||||
mask_write 0XF8006120 0x7FFFFFCF 0x40000000
|
||||
mask_write 0XF8006124 0x7FFFFFCF 0x40000000
|
||||
mask_write 0XF800612C 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006130 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006134 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006138 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006140 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006144 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006148 0x000FFFFF 0x00000035
|
||||
mask_write 0XF800614C 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006154 0x000FFFFF 0x00000080
|
||||
mask_write 0XF8006158 0x000FFFFF 0x00000080
|
||||
mask_write 0XF800615C 0x000FFFFF 0x00000080
|
||||
mask_write 0XF8006160 0x000FFFFF 0x00000080
|
||||
mask_write 0XF8006168 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF800616C 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF8006170 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF8006174 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF800617C 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006180 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006184 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006188 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006190 0x6FFFFEFE 0x00040080
|
||||
mask_write 0XF8006194 0x000FFFFF 0x0001FC82
|
||||
mask_write 0XF8006204 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF8006208 0x000703FF 0x000003FF
|
||||
mask_write 0XF800620C 0x000703FF 0x000003FF
|
||||
mask_write 0XF8006210 0x000703FF 0x000003FF
|
||||
mask_write 0XF8006214 0x000703FF 0x000003FF
|
||||
mask_write 0XF8006218 0x000F03FF 0x000003FF
|
||||
mask_write 0XF800621C 0x000F03FF 0x000003FF
|
||||
mask_write 0XF8006220 0x000F03FF 0x000003FF
|
||||
mask_write 0XF8006224 0x000F03FF 0x000003FF
|
||||
mask_write 0XF80062A8 0x00000FF5 0x00000000
|
||||
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF80062B0 0x003FFFFF 0x00005125
|
||||
mask_write 0XF80062B4 0x0003FFFF 0x000012A8
|
||||
mask_poll 0XF8000B74 0x00002000
|
||||
mask_write 0XF8006000 0x0001FFFF 0x00000085
|
||||
mask_poll 0XF8006054 0x00000007
|
||||
}
|
||||
proc ps7_mio_init_data_3_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000B40 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B44 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B48 0x00000FFF 0x00000672
|
||||
mask_write 0XF8000B4C 0x00000FFF 0x00000800
|
||||
mask_write 0XF8000B50 0x00000FFF 0x00000674
|
||||
mask_write 0XF8000B54 0x00000FFF 0x00000800
|
||||
mask_write 0XF8000B58 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
|
||||
mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B6C 0x00007FFF 0x00000220
|
||||
mask_write 0XF8000B70 0x00000001 0x00000001
|
||||
mask_write 0XF8000B70 0x00000021 0x00000020
|
||||
mask_write 0XF8000B70 0x07FEFFFF 0x00000823
|
||||
mask_write 0XF8000700 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000704 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000708 0x00003FFF 0x00000202
|
||||
mask_write 0XF800070C 0x00003FFF 0x00000202
|
||||
mask_write 0XF8000710 0x00003FFF 0x00000202
|
||||
mask_write 0XF8000714 0x00003FFF 0x00000202
|
||||
mask_write 0XF8000718 0x00003FFF 0x00000202
|
||||
mask_write 0XF800071C 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000720 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000724 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000728 0x00003FFF 0x00000200
|
||||
mask_write 0XF800072C 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000730 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000734 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000738 0x00003FFF 0x00000200
|
||||
mask_write 0XF800073C 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000740 0x00003FFF 0x00001200
|
||||
mask_write 0XF8000744 0x00003FFF 0x00001200
|
||||
mask_write 0XF8000748 0x00003FFF 0x00001200
|
||||
mask_write 0XF800074C 0x00003FFF 0x00001200
|
||||
mask_write 0XF8000750 0x00003FFF 0x00001200
|
||||
mask_write 0XF8000754 0x00003FFF 0x00001200
|
||||
mask_write 0XF8000758 0x00003FFF 0x00001200
|
||||
mask_write 0XF800075C 0x00003FFF 0x00001200
|
||||
mask_write 0XF8000760 0x00003FFF 0x00001200
|
||||
mask_write 0XF8000764 0x00003FFF 0x00001200
|
||||
mask_write 0XF8000768 0x00003FFF 0x00001200
|
||||
mask_write 0XF800076C 0x00003FFF 0x00001200
|
||||
mask_write 0XF8000770 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000774 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000778 0x00003FFF 0x00000200
|
||||
mask_write 0XF800077C 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000780 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000784 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000788 0x00003FFF 0x00000200
|
||||
mask_write 0XF800078C 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000790 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000794 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000798 0x00003FFF 0x00000200
|
||||
mask_write 0XF800079C 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007A0 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007A4 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007A8 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007AC 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007B0 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007B4 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007B8 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007BC 0x00003FFF 0x00001200
|
||||
mask_write 0XF80007C0 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007C4 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007C8 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007CC 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007D0 0x00003FFF 0x00001200
|
||||
mask_write 0XF80007D4 0x00003FFF 0x00001200
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_peripherals_init_data_3_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000B48 0x00000180 0x00000180
|
||||
mask_write 0XF8000B4C 0x00000180 0x00000000
|
||||
mask_write 0XF8000B50 0x00000180 0x00000180
|
||||
mask_write 0XF8000B54 0x00000180 0x00000000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
mask_write 0XE000D000 0x00080000 0x00080000
|
||||
mask_write 0XF8007000 0x20000000 0x00000000
|
||||
}
|
||||
proc ps7_post_config_3_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000900 0x0000000F 0x0000000F
|
||||
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_debug_3_0 {} {
|
||||
mwr -force 0XF8898FB0 0xC5ACCE55
|
||||
mwr -force 0XF8899FB0 0xC5ACCE55
|
||||
mwr -force 0XF8809FB0 0xC5ACCE55
|
||||
}
|
||||
proc ps7_pll_init_data_2_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000110 0x003FFFF0 0x000FA220
|
||||
mask_write 0XF8000100 0x0007F000 0x00028000
|
||||
mask_write 0XF8000100 0x00000010 0x00000010
|
||||
mask_write 0XF8000100 0x00000001 0x00000001
|
||||
mask_write 0XF8000100 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000001
|
||||
mask_write 0XF8000100 0x00000010 0x00000000
|
||||
mask_write 0XF8000120 0x1F003F30 0x1F000200
|
||||
mask_write 0XF8000114 0x003FFFF0 0x0012C220
|
||||
mask_write 0XF8000104 0x0007F000 0x00020000
|
||||
mask_write 0XF8000104 0x00000010 0x00000010
|
||||
mask_write 0XF8000104 0x00000001 0x00000001
|
||||
mask_write 0XF8000104 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000002
|
||||
mask_write 0XF8000104 0x00000010 0x00000000
|
||||
mask_write 0XF8000124 0xFFF00003 0x0C200003
|
||||
mask_write 0XF8000118 0x003FFFF0 0x000FA240
|
||||
mask_write 0XF8000108 0x0007F000 0x00036000
|
||||
mask_write 0XF8000108 0x00000010 0x00000010
|
||||
mask_write 0XF8000108 0x00000001 0x00000001
|
||||
mask_write 0XF8000108 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000004
|
||||
mask_write 0XF8000108 0x00000010 0x00000000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_clock_init_data_2_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000128 0x03F03F01 0x00700F01
|
||||
mask_write 0XF800014C 0x00003F31 0x00000901
|
||||
mask_write 0XF8000168 0x00003F31 0x00000901
|
||||
mask_write 0XF8000170 0x03F03F30 0x00600600
|
||||
mask_write 0XF8000180 0x03F03F30 0x00300300
|
||||
mask_write 0XF80001C4 0x00000001 0x00000001
|
||||
mask_write 0XF800012C 0x01FFCCCD 0x01CC000D
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_ddr_init_data_2_0 {} {
|
||||
mask_write 0XF8006000 0x0001FFFF 0x00000084
|
||||
mask_write 0XF8006004 0x1FFFFFFF 0x00081082
|
||||
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
|
||||
mask_write 0XF800600C 0x03FFFFFF 0x02001001
|
||||
mask_write 0XF8006010 0x03FFFFFF 0x00014001
|
||||
mask_write 0XF8006014 0x001FFFFF 0x0004285B
|
||||
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
|
||||
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
|
||||
mask_write 0XF8006020 0xFFFFFFFC 0x272872D0
|
||||
mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
|
||||
mask_write 0XF8006028 0x00003FFF 0x00002007
|
||||
mask_write 0XF800602C 0xFFFFFFFF 0x00000008
|
||||
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
|
||||
mask_write 0XF8006034 0x13FF3FFF 0x000116D4
|
||||
mask_write 0XF8006038 0x00001FC3 0x00000000
|
||||
mask_write 0XF800603C 0x000FFFFF 0x00000666
|
||||
mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
|
||||
mask_write 0XF8006044 0x0FFFFFFF 0x0F555555
|
||||
mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
|
||||
mask_write 0XF8006050 0xFF0F8FFF 0x77010800
|
||||
mask_write 0XF8006058 0x0001FFFF 0x00000101
|
||||
mask_write 0XF800605C 0x0000FFFF 0x00005003
|
||||
mask_write 0XF8006060 0x000017FF 0x0000003E
|
||||
mask_write 0XF8006064 0x00021FE0 0x00020000
|
||||
mask_write 0XF8006068 0x03FFFFFF 0x00284141
|
||||
mask_write 0XF800606C 0x0000FFFF 0x00001610
|
||||
mask_write 0XF8006078 0x03FFFFFF 0x00466111
|
||||
mask_write 0XF800607C 0x000FFFFF 0x00032222
|
||||
mask_write 0XF80060A0 0x00FFFFFF 0x00008000
|
||||
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
|
||||
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
|
||||
mask_write 0XF80060AC 0x000001FF 0x000001FE
|
||||
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
|
||||
mask_write 0XF80060B4 0x000007FF 0x00000200
|
||||
mask_write 0XF80060B8 0x01FFFFFF 0x00200066
|
||||
mask_write 0XF80060C4 0x00000003 0x00000000
|
||||
mask_write 0XF80060C8 0x000000FF 0x00000000
|
||||
mask_write 0XF80060DC 0x00000001 0x00000000
|
||||
mask_write 0XF80060F0 0x0000FFFF 0x00000000
|
||||
mask_write 0XF80060F4 0x0000000F 0x00000008
|
||||
mask_write 0XF8006114 0x000000FF 0x00000000
|
||||
mask_write 0XF8006118 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF800611C 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF8006120 0x7FFFFFFF 0x40000000
|
||||
mask_write 0XF8006124 0x7FFFFFFF 0x40000000
|
||||
mask_write 0XF800612C 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006130 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006134 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006138 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006140 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006144 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006148 0x000FFFFF 0x00000035
|
||||
mask_write 0XF800614C 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006154 0x000FFFFF 0x00000080
|
||||
mask_write 0XF8006158 0x000FFFFF 0x00000080
|
||||
mask_write 0XF800615C 0x000FFFFF 0x00000080
|
||||
mask_write 0XF8006160 0x000FFFFF 0x00000080
|
||||
mask_write 0XF8006168 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF800616C 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF8006170 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF8006174 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF800617C 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006180 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006184 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006188 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006190 0xFFFFFFFF 0x10040080
|
||||
mask_write 0XF8006194 0x000FFFFF 0x0001FC82
|
||||
mask_write 0XF8006204 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF8006208 0x000F03FF 0x000803FF
|
||||
mask_write 0XF800620C 0x000F03FF 0x000803FF
|
||||
mask_write 0XF8006210 0x000F03FF 0x000803FF
|
||||
mask_write 0XF8006214 0x000F03FF 0x000803FF
|
||||
mask_write 0XF8006218 0x000F03FF 0x000003FF
|
||||
mask_write 0XF800621C 0x000F03FF 0x000003FF
|
||||
mask_write 0XF8006220 0x000F03FF 0x000003FF
|
||||
mask_write 0XF8006224 0x000F03FF 0x000003FF
|
||||
mask_write 0XF80062A8 0x00000FF7 0x00000000
|
||||
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF80062B0 0x003FFFFF 0x00005125
|
||||
mask_write 0XF80062B4 0x0003FFFF 0x000012A8
|
||||
mask_poll 0XF8000B74 0x00002000
|
||||
mask_write 0XF8006000 0x0001FFFF 0x00000085
|
||||
mask_poll 0XF8006054 0x00000007
|
||||
}
|
||||
proc ps7_mio_init_data_2_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000B40 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B44 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B48 0x00000FFF 0x00000672
|
||||
mask_write 0XF8000B4C 0x00000FFF 0x00000800
|
||||
mask_write 0XF8000B50 0x00000FFF 0x00000674
|
||||
mask_write 0XF8000B54 0x00000FFF 0x00000800
|
||||
mask_write 0XF8000B58 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
|
||||
mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B6C 0x00007FFF 0x00000220
|
||||
mask_write 0XF8000B70 0x00000021 0x00000021
|
||||
mask_write 0XF8000B70 0x00000021 0x00000020
|
||||
mask_write 0XF8000B70 0x07FFFFFF 0x00000823
|
||||
mask_write 0XF8000700 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000704 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000708 0x00003FFF 0x00000202
|
||||
mask_write 0XF800070C 0x00003FFF 0x00000202
|
||||
mask_write 0XF8000710 0x00003FFF 0x00000202
|
||||
mask_write 0XF8000714 0x00003FFF 0x00000202
|
||||
mask_write 0XF8000718 0x00003FFF 0x00000202
|
||||
mask_write 0XF800071C 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000720 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000724 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000728 0x00003FFF 0x00000200
|
||||
mask_write 0XF800072C 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000730 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000734 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000738 0x00003FFF 0x00000200
|
||||
mask_write 0XF800073C 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000740 0x00003FFF 0x00001200
|
||||
mask_write 0XF8000744 0x00003FFF 0x00001200
|
||||
mask_write 0XF8000748 0x00003FFF 0x00001200
|
||||
mask_write 0XF800074C 0x00003FFF 0x00001200
|
||||
mask_write 0XF8000750 0x00003FFF 0x00001200
|
||||
mask_write 0XF8000754 0x00003FFF 0x00001200
|
||||
mask_write 0XF8000758 0x00003FFF 0x00001200
|
||||
mask_write 0XF800075C 0x00003FFF 0x00001200
|
||||
mask_write 0XF8000760 0x00003FFF 0x00001200
|
||||
mask_write 0XF8000764 0x00003FFF 0x00001200
|
||||
mask_write 0XF8000768 0x00003FFF 0x00001200
|
||||
mask_write 0XF800076C 0x00003FFF 0x00001200
|
||||
mask_write 0XF8000770 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000774 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000778 0x00003FFF 0x00000200
|
||||
mask_write 0XF800077C 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000780 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000784 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000788 0x00003FFF 0x00000200
|
||||
mask_write 0XF800078C 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000790 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000794 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000798 0x00003FFF 0x00000200
|
||||
mask_write 0XF800079C 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007A0 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007A4 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007A8 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007AC 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007B0 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007B4 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007B8 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007BC 0x00003FFF 0x00001200
|
||||
mask_write 0XF80007C0 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007C4 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007C8 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007CC 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007D0 0x00003FFF 0x00001200
|
||||
mask_write 0XF80007D4 0x00003FFF 0x00001200
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_peripherals_init_data_2_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000B48 0x00000180 0x00000180
|
||||
mask_write 0XF8000B4C 0x00000180 0x00000000
|
||||
mask_write 0XF8000B50 0x00000180 0x00000180
|
||||
mask_write 0XF8000B54 0x00000180 0x00000000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
mask_write 0XE000D000 0x00080000 0x00080000
|
||||
mask_write 0XF8007000 0x20000000 0x00000000
|
||||
}
|
||||
proc ps7_post_config_2_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000900 0x0000000F 0x0000000F
|
||||
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_debug_2_0 {} {
|
||||
mwr -force 0XF8898FB0 0xC5ACCE55
|
||||
mwr -force 0XF8899FB0 0xC5ACCE55
|
||||
mwr -force 0XF8809FB0 0xC5ACCE55
|
||||
}
|
||||
proc ps7_pll_init_data_1_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000110 0x003FFFF0 0x000FA220
|
||||
mask_write 0XF8000100 0x0007F000 0x00028000
|
||||
mask_write 0XF8000100 0x00000010 0x00000010
|
||||
mask_write 0XF8000100 0x00000001 0x00000001
|
||||
mask_write 0XF8000100 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000001
|
||||
mask_write 0XF8000100 0x00000010 0x00000000
|
||||
mask_write 0XF8000120 0x1F003F30 0x1F000200
|
||||
mask_write 0XF8000114 0x003FFFF0 0x0012C220
|
||||
mask_write 0XF8000104 0x0007F000 0x00020000
|
||||
mask_write 0XF8000104 0x00000010 0x00000010
|
||||
mask_write 0XF8000104 0x00000001 0x00000001
|
||||
mask_write 0XF8000104 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000002
|
||||
mask_write 0XF8000104 0x00000010 0x00000000
|
||||
mask_write 0XF8000124 0xFFF00003 0x0C200003
|
||||
mask_write 0XF8000118 0x003FFFF0 0x000FA240
|
||||
mask_write 0XF8000108 0x0007F000 0x00036000
|
||||
mask_write 0XF8000108 0x00000010 0x00000010
|
||||
mask_write 0XF8000108 0x00000001 0x00000001
|
||||
mask_write 0XF8000108 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000004
|
||||
mask_write 0XF8000108 0x00000010 0x00000000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_clock_init_data_1_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000128 0x03F03F01 0x00700F01
|
||||
mask_write 0XF800014C 0x00003F31 0x00000901
|
||||
mask_write 0XF8000168 0x00003F31 0x00000901
|
||||
mask_write 0XF8000170 0x03F03F30 0x00600600
|
||||
mask_write 0XF8000180 0x03F03F30 0x00300300
|
||||
mask_write 0XF80001C4 0x00000001 0x00000001
|
||||
mask_write 0XF800012C 0x01FFCCCD 0x01CC000D
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_ddr_init_data_1_0 {} {
|
||||
mask_write 0XF8006000 0x0001FFFF 0x00000084
|
||||
mask_write 0XF8006004 0x1FFFFFFF 0x00081082
|
||||
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
|
||||
mask_write 0XF800600C 0x03FFFFFF 0x02001001
|
||||
mask_write 0XF8006010 0x03FFFFFF 0x00014001
|
||||
mask_write 0XF8006014 0x001FFFFF 0x0004285B
|
||||
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
|
||||
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
|
||||
mask_write 0XF8006020 0xFFFFFFFC 0x272872D0
|
||||
mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
|
||||
mask_write 0XF8006028 0x00003FFF 0x00002007
|
||||
mask_write 0XF800602C 0xFFFFFFFF 0x00000008
|
||||
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
|
||||
mask_write 0XF8006034 0x13FF3FFF 0x000116D4
|
||||
mask_write 0XF8006038 0x00001FC3 0x00000000
|
||||
mask_write 0XF800603C 0x000FFFFF 0x00000666
|
||||
mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
|
||||
mask_write 0XF8006044 0x0FFFFFFF 0x0F555555
|
||||
mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
|
||||
mask_write 0XF8006050 0xFF0F8FFF 0x77010800
|
||||
mask_write 0XF8006058 0x0001FFFF 0x00000101
|
||||
mask_write 0XF800605C 0x0000FFFF 0x00005003
|
||||
mask_write 0XF8006060 0x000017FF 0x0000003E
|
||||
mask_write 0XF8006064 0x00021FE0 0x00020000
|
||||
mask_write 0XF8006068 0x03FFFFFF 0x00284141
|
||||
mask_write 0XF800606C 0x0000FFFF 0x00001610
|
||||
mask_write 0XF80060A0 0x00FFFFFF 0x00008000
|
||||
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
|
||||
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
|
||||
mask_write 0XF80060AC 0x000001FF 0x000001FE
|
||||
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
|
||||
mask_write 0XF80060B4 0x000007FF 0x00000200
|
||||
mask_write 0XF80060B8 0x01FFFFFF 0x00200066
|
||||
mask_write 0XF80060C4 0x00000003 0x00000000
|
||||
mask_write 0XF80060C8 0x000000FF 0x00000000
|
||||
mask_write 0XF80060DC 0x00000001 0x00000000
|
||||
mask_write 0XF80060F0 0x0000FFFF 0x00000000
|
||||
mask_write 0XF80060F4 0x0000000F 0x00000008
|
||||
mask_write 0XF8006114 0x000000FF 0x00000000
|
||||
mask_write 0XF8006118 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF800611C 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF8006120 0x7FFFFFFF 0x40000000
|
||||
mask_write 0XF8006124 0x7FFFFFFF 0x40000000
|
||||
mask_write 0XF800612C 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006130 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006134 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006138 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006140 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006144 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006148 0x000FFFFF 0x00000035
|
||||
mask_write 0XF800614C 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006154 0x000FFFFF 0x00000080
|
||||
mask_write 0XF8006158 0x000FFFFF 0x00000080
|
||||
mask_write 0XF800615C 0x000FFFFF 0x00000080
|
||||
mask_write 0XF8006160 0x000FFFFF 0x00000080
|
||||
mask_write 0XF8006168 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF800616C 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF8006170 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF8006174 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF800617C 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006180 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006184 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006188 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006190 0xFFFFFFFF 0x10040080
|
||||
mask_write 0XF8006194 0x000FFFFF 0x0001FC82
|
||||
mask_write 0XF8006204 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF8006208 0x000F03FF 0x000803FF
|
||||
mask_write 0XF800620C 0x000F03FF 0x000803FF
|
||||
mask_write 0XF8006210 0x000F03FF 0x000803FF
|
||||
mask_write 0XF8006214 0x000F03FF 0x000803FF
|
||||
mask_write 0XF8006218 0x000F03FF 0x000003FF
|
||||
mask_write 0XF800621C 0x000F03FF 0x000003FF
|
||||
mask_write 0XF8006220 0x000F03FF 0x000003FF
|
||||
mask_write 0XF8006224 0x000F03FF 0x000003FF
|
||||
mask_write 0XF80062A8 0x00000FF7 0x00000000
|
||||
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF80062B0 0x003FFFFF 0x00005125
|
||||
mask_write 0XF80062B4 0x0003FFFF 0x000012A8
|
||||
mask_poll 0XF8000B74 0x00002000
|
||||
mask_write 0XF8006000 0x0001FFFF 0x00000085
|
||||
mask_poll 0XF8006054 0x00000007
|
||||
}
|
||||
proc ps7_mio_init_data_1_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000B40 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B44 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B48 0x00000FFF 0x00000672
|
||||
mask_write 0XF8000B4C 0x00000FFF 0x00000800
|
||||
mask_write 0XF8000B50 0x00000FFF 0x00000674
|
||||
mask_write 0XF8000B54 0x00000FFF 0x00000800
|
||||
mask_write 0XF8000B58 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
|
||||
mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B6C 0x000073FF 0x00000220
|
||||
mask_write 0XF8000B70 0x00000021 0x00000021
|
||||
mask_write 0XF8000B70 0x00000021 0x00000020
|
||||
mask_write 0XF8000B70 0x07FFFFFF 0x00000823
|
||||
mask_write 0XF8000700 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000704 0x00003FFF 0x00001202
|
||||
mask_write 0XF8000708 0x00003FFF 0x00000202
|
||||
mask_write 0XF800070C 0x00003FFF 0x00000202
|
||||
mask_write 0XF8000710 0x00003FFF 0x00000202
|
||||
mask_write 0XF8000714 0x00003FFF 0x00000202
|
||||
mask_write 0XF8000718 0x00003FFF 0x00000202
|
||||
mask_write 0XF800071C 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000720 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000724 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000728 0x00003FFF 0x00000200
|
||||
mask_write 0XF800072C 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000730 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000734 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000738 0x00003FFF 0x00000200
|
||||
mask_write 0XF800073C 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000740 0x00003FFF 0x00001200
|
||||
mask_write 0XF8000744 0x00003FFF 0x00001200
|
||||
mask_write 0XF8000748 0x00003FFF 0x00001200
|
||||
mask_write 0XF800074C 0x00003FFF 0x00001200
|
||||
mask_write 0XF8000750 0x00003FFF 0x00001200
|
||||
mask_write 0XF8000754 0x00003FFF 0x00001200
|
||||
mask_write 0XF8000758 0x00003FFF 0x00001200
|
||||
mask_write 0XF800075C 0x00003FFF 0x00001200
|
||||
mask_write 0XF8000760 0x00003FFF 0x00001200
|
||||
mask_write 0XF8000764 0x00003FFF 0x00001200
|
||||
mask_write 0XF8000768 0x00003FFF 0x00001200
|
||||
mask_write 0XF800076C 0x00003FFF 0x00001200
|
||||
mask_write 0XF8000770 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000774 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000778 0x00003FFF 0x00000200
|
||||
mask_write 0XF800077C 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000780 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000784 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000788 0x00003FFF 0x00000200
|
||||
mask_write 0XF800078C 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000790 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000794 0x00003FFF 0x00000200
|
||||
mask_write 0XF8000798 0x00003FFF 0x00000200
|
||||
mask_write 0XF800079C 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007A0 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007A4 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007A8 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007AC 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007B0 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007B4 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007B8 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007BC 0x00003FFF 0x00001200
|
||||
mask_write 0XF80007C0 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007C4 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007C8 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007CC 0x00003FFF 0x00000200
|
||||
mask_write 0XF80007D0 0x00003FFF 0x00001200
|
||||
mask_write 0XF80007D4 0x00003FFF 0x00001200
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_peripherals_init_data_1_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000B48 0x00000180 0x00000180
|
||||
mask_write 0XF8000B4C 0x00000180 0x00000000
|
||||
mask_write 0XF8000B50 0x00000180 0x00000180
|
||||
mask_write 0XF8000B54 0x00000180 0x00000000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
mask_write 0XE000D000 0x00080000 0x00080000
|
||||
mask_write 0XF8007000 0x20000000 0x00000000
|
||||
}
|
||||
proc ps7_post_config_1_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000900 0x0000000F 0x0000000F
|
||||
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_debug_1_0 {} {
|
||||
mwr -force 0XF8898FB0 0xC5ACCE55
|
||||
mwr -force 0XF8899FB0 0xC5ACCE55
|
||||
mwr -force 0XF8809FB0 0xC5ACCE55
|
||||
}
|
||||
set PCW_SILICON_VER_1_0 "0x0"
|
||||
set PCW_SILICON_VER_2_0 "0x1"
|
||||
set PCW_SILICON_VER_3_0 "0x2"
|
||||
set APU_FREQ 666666666
|
||||
|
||||
|
||||
|
||||
proc mask_poll { addr mask } {
|
||||
set count 1
|
||||
set curval "0x[string range [mrd $addr] end-8 end]"
|
||||
set maskedval [expr {$curval & $mask}]
|
||||
while { $maskedval == 0 } {
|
||||
set curval "0x[string range [mrd $addr] end-8 end]"
|
||||
set maskedval [expr {$curval & $mask}]
|
||||
set count [ expr { $count + 1 } ]
|
||||
if { $count == 100000000 } {
|
||||
puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask"
|
||||
break
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
proc mask_delay { addr val } {
|
||||
set delay [ get_number_of_cycles_for_delay $val ]
|
||||
perf_reset_and_start_timer
|
||||
set curval "0x[string range [mrd $addr] end-8 end]"
|
||||
set maskedval [expr {$curval < $delay}]
|
||||
while { $maskedval == 1 } {
|
||||
set curval "0x[string range [mrd $addr] end-8 end]"
|
||||
set maskedval [expr {$curval < $delay}]
|
||||
}
|
||||
perf_reset_clock
|
||||
}
|
||||
|
||||
proc ps_version { } {
|
||||
set si_ver "0x[string range [mrd 0xF8007080] end-8 end]"
|
||||
set mask_sil_ver "0x[expr {$si_ver >> 28}]"
|
||||
return $mask_sil_ver;
|
||||
}
|
||||
|
||||
proc ps7_post_config {} {
|
||||
set saved_mode [configparams force-mem-accesses]
|
||||
configparams force-mem-accesses 1
|
||||
|
||||
variable PCW_SILICON_VER_1_0
|
||||
variable PCW_SILICON_VER_2_0
|
||||
variable PCW_SILICON_VER_3_0
|
||||
set sil_ver [ps_version]
|
||||
|
||||
if { $sil_ver == $PCW_SILICON_VER_1_0} {
|
||||
ps7_post_config_1_0
|
||||
} elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
|
||||
ps7_post_config_2_0
|
||||
} else {
|
||||
ps7_post_config_3_0
|
||||
}
|
||||
configparams force-mem-accesses $saved_mode
|
||||
}
|
||||
|
||||
proc ps7_debug {} {
|
||||
variable PCW_SILICON_VER_1_0
|
||||
variable PCW_SILICON_VER_2_0
|
||||
variable PCW_SILICON_VER_3_0
|
||||
set sil_ver [ps_version]
|
||||
|
||||
if { $sil_ver == $PCW_SILICON_VER_1_0} {
|
||||
ps7_debug_1_0
|
||||
} elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
|
||||
ps7_debug_2_0
|
||||
} else {
|
||||
ps7_debug_3_0
|
||||
}
|
||||
}
|
||||
proc ps7_init {} {
|
||||
variable PCW_SILICON_VER_1_0
|
||||
variable PCW_SILICON_VER_2_0
|
||||
variable PCW_SILICON_VER_3_0
|
||||
set sil_ver [ps_version]
|
||||
if { $sil_ver == $PCW_SILICON_VER_1_0} {
|
||||
ps7_mio_init_data_1_0
|
||||
ps7_pll_init_data_1_0
|
||||
ps7_clock_init_data_1_0
|
||||
ps7_ddr_init_data_1_0
|
||||
ps7_peripherals_init_data_1_0
|
||||
#puts "PCW Silicon Version : 1.0"
|
||||
} elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
|
||||
ps7_mio_init_data_2_0
|
||||
ps7_pll_init_data_2_0
|
||||
ps7_clock_init_data_2_0
|
||||
ps7_ddr_init_data_2_0
|
||||
ps7_peripherals_init_data_2_0
|
||||
#puts "PCW Silicon Version : 2.0"
|
||||
} else {
|
||||
ps7_mio_init_data_3_0
|
||||
ps7_pll_init_data_3_0
|
||||
ps7_clock_init_data_3_0
|
||||
ps7_ddr_init_data_3_0
|
||||
ps7_peripherals_init_data_3_0
|
||||
#puts "PCW Silicon Version : 3.0"
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
# For delay calculation using global timer
|
||||
|
||||
# start timer
|
||||
proc perf_start_clock { } {
|
||||
|
||||
#writing SCU_GLOBAL_TIMER_CONTROL register
|
||||
|
||||
mask_write 0xF8F00208 0x00000109 0x00000009
|
||||
}
|
||||
|
||||
# stop timer and reset timer count regs
|
||||
proc perf_reset_clock { } {
|
||||
perf_disable_clock
|
||||
mask_write 0xF8F00200 0xFFFFFFFF 0x00000000
|
||||
mask_write 0xF8F00204 0xFFFFFFFF 0x00000000
|
||||
}
|
||||
|
||||
# Compute mask for given delay in miliseconds
|
||||
proc get_number_of_cycles_for_delay { delay } {
|
||||
|
||||
# GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
|
||||
variable APU_FREQ
|
||||
return [ expr ($delay * $APU_FREQ /(2 * 1000))]
|
||||
}
|
||||
|
||||
|
||||
# stop timer
|
||||
proc perf_disable_clock {} {
|
||||
mask_write 0xF8F00208 0xFFFFFFFF 0x00000000
|
||||
}
|
||||
|
||||
proc perf_reset_and_start_timer {} {
|
||||
perf_reset_clock
|
||||
perf_start_clock
|
||||
}
|
||||
|
||||
|
||||
+11831
File diff suppressed because it is too large
Load Diff
+131
@@ -0,0 +1,131 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2018 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, see <http://www.gnu.org/licenses/>
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file ps7_init_gpl.h
|
||||
*
|
||||
* This file can be included in FSBL code
|
||||
* to get prototype of ps7_init() function
|
||||
* and error codes
|
||||
*
|
||||
*****************************************************************************/
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
//typedef unsigned int u32;
|
||||
|
||||
|
||||
/** do we need to make this name more unique ? **/
|
||||
//extern u32 ps7_init_data[];
|
||||
extern unsigned long * ps7_ddr_init_data;
|
||||
extern unsigned long * ps7_mio_init_data;
|
||||
extern unsigned long * ps7_pll_init_data;
|
||||
extern unsigned long * ps7_clock_init_data;
|
||||
extern unsigned long * ps7_peripherals_init_data;
|
||||
|
||||
|
||||
|
||||
#define OPCODE_EXIT 0U
|
||||
#define OPCODE_CLEAR 1U
|
||||
#define OPCODE_WRITE 2U
|
||||
#define OPCODE_MASKWRITE 3U
|
||||
#define OPCODE_MASKPOLL 4U
|
||||
#define OPCODE_MASKDELAY 5U
|
||||
#define NEW_PS7_ERR_CODE 1
|
||||
|
||||
/* Encode number of arguments in last nibble */
|
||||
#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
|
||||
#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
|
||||
#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
|
||||
#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
|
||||
#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
|
||||
#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
|
||||
|
||||
/* Returns codes of PS7_Init */
|
||||
#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
|
||||
#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
|
||||
#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
|
||||
#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
|
||||
#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
|
||||
#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
|
||||
|
||||
|
||||
/* Silicon Versions */
|
||||
#define PCW_SILICON_VERSION_1 0
|
||||
#define PCW_SILICON_VERSION_2 1
|
||||
#define PCW_SILICON_VERSION_3 2
|
||||
|
||||
/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
|
||||
#define PS7_POST_CONFIG
|
||||
|
||||
/* Freq of all peripherals */
|
||||
|
||||
#define APU_FREQ 666666687
|
||||
#define DDR_FREQ 533333374
|
||||
#define DCI_FREQ 10158730
|
||||
#define QSPI_FREQ 200000000
|
||||
#define SMC_FREQ 10000000
|
||||
#define ENET0_FREQ 10000000
|
||||
#define ENET1_FREQ 10000000
|
||||
#define USB0_FREQ 60000000
|
||||
#define USB1_FREQ 60000000
|
||||
#define SDIO_FREQ 10000000
|
||||
#define UART_FREQ 10000000
|
||||
#define SPI_FREQ 10000000
|
||||
#define I2C_FREQ 111111115
|
||||
#define WDT_FREQ 111111115
|
||||
#define TTC_FREQ 50000000
|
||||
#define CAN_FREQ 10000000
|
||||
#define PCAP_FREQ 200000000
|
||||
#define TPIU_FREQ 200000000
|
||||
#define FPGA0_FREQ 50000000
|
||||
#define FPGA1_FREQ 200000000
|
||||
#define FPGA2_FREQ 10000000
|
||||
#define FPGA3_FREQ 10000000
|
||||
|
||||
|
||||
/* For delay calculation using global registers*/
|
||||
#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
|
||||
#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
|
||||
#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
|
||||
#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
|
||||
|
||||
int ps7_config( unsigned long*);
|
||||
int ps7_init();
|
||||
int ps7_post_config();
|
||||
int ps7_debug();
|
||||
char* getPS7MessageInfo(unsigned key);
|
||||
|
||||
void perf_start_clock(void);
|
||||
void perf_disable_clock(void);
|
||||
void perf_reset_clock(void);
|
||||
void perf_reset_and_start_timer();
|
||||
int get_number_of_cycles_for_delay(unsigned int delay);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
+643
@@ -0,0 +1,643 @@
|
||||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<!DOCTYPE designInfo PUBLIC "designInfo" "designInfo.dtd" >
|
||||
<designInfo version="1.0" >
|
||||
<MODULE IP_TYPE="SOC" MOD_CLASS="CONFIGURABLE" MODTYPE="processing_system7" >
|
||||
<PARAMETERS >
|
||||
<PARAMETER NAME="PCW_APU_CLK_RATIO_ENABLE" VALUE="6:2:1" />
|
||||
<PARAMETER NAME="PCW_APU_PERIPHERAL_FREQMHZ" VALUE="666.666666" />
|
||||
<PARAMETER NAME="PCW_ARMPLL_CTRL_FBDIV" VALUE="40" />
|
||||
<PARAMETER NAME="PCW_CAN0_CAN0_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_CAN0_GRP_CLK_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_CAN0_GRP_CLK_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_CAN0_PERIPHERAL_CLKSRC" VALUE="External" />
|
||||
<PARAMETER NAME="PCW_CAN0_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_CAN0_PERIPHERAL_FREQMHZ" VALUE="" />
|
||||
<PARAMETER NAME="PCW_CAN1_CAN1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_CAN1_GRP_CLK_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_CAN1_GRP_CLK_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_CAN1_PERIPHERAL_CLKSRC" VALUE="External" />
|
||||
<PARAMETER NAME="PCW_CAN1_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_CAN1_PERIPHERAL_FREQMHZ" VALUE="" />
|
||||
<PARAMETER NAME="PCW_CAN_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_CAN_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_CAN_PERIPHERAL_DIVISOR1" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_CAN_PERIPHERAL_FREQMHZ" VALUE="100" />
|
||||
<PARAMETER NAME="PCW_CPU_CPU_PLL_FREQMHZ" VALUE="1333.333" />
|
||||
<PARAMETER NAME="PCW_CPU_PERIPHERAL_CLKSRC" VALUE="ARM PLL" />
|
||||
<PARAMETER NAME="PCW_CPU_PERIPHERAL_DIVISOR0" VALUE="2" />
|
||||
<PARAMETER NAME="PCW_CRYSTAL_PERIPHERAL_FREQMHZ" VALUE="33.333333" />
|
||||
<PARAMETER NAME="PCW_DCI_PERIPHERAL_CLKSRC" VALUE="DDR PLL" />
|
||||
<PARAMETER NAME="PCW_DCI_PERIPHERAL_DIVISOR0" VALUE="15" />
|
||||
<PARAMETER NAME="PCW_DCI_PERIPHERAL_DIVISOR1" VALUE="7" />
|
||||
<PARAMETER NAME="PCW_DCI_PERIPHERAL_FREQMHZ" VALUE="10.159" />
|
||||
<PARAMETER NAME="PCW_DDRPLL_CTRL_FBDIV" VALUE="32" />
|
||||
<PARAMETER NAME="PCW_DDR_DDR_PLL_FREQMHZ" VALUE="1066.667" />
|
||||
<PARAMETER NAME="PCW_DDR_HPRLPR_QUEUE_PARTITION" VALUE="HPR(0)/LPR(32)" />
|
||||
<PARAMETER NAME="PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL" VALUE="15" />
|
||||
<PARAMETER NAME="PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL" VALUE="2" />
|
||||
<PARAMETER NAME="PCW_DDR_PERIPHERAL_CLKSRC" VALUE="DDR PLL" />
|
||||
<PARAMETER NAME="PCW_DDR_PERIPHERAL_DIVISOR0" VALUE="2" />
|
||||
<PARAMETER NAME="PCW_DDR_PORT0_HPR_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PORT1_HPR_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PORT2_HPR_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PORT3_HPR_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_0" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_1" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_2" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PRIORITY_READPORT_3" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_0" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_1" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_2" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_PRIORITY_WRITEPORT_3" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL" VALUE="2" />
|
||||
<PARAMETER NAME="PCW_DUAL_PARALLEL_QSPI_DATA_MODE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_DUAL_STACK_QSPI_DATA_MODE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET0_ENET0_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET0_GRP_MDIO_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET0_GRP_MDIO_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET0_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_ENET0_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_ENET0_PERIPHERAL_DIVISOR1" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_ENET0_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_ENET0_PERIPHERAL_FREQMHZ" VALUE="1000 Mbps" />
|
||||
<PARAMETER NAME="PCW_ENET0_RESET_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET0_RESET_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET1_ENET1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET1_GRP_MDIO_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET1_GRP_MDIO_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET1_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_ENET1_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_ENET1_PERIPHERAL_DIVISOR1" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_ENET1_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_ENET1_PERIPHERAL_FREQMHZ" VALUE="1000 Mbps" />
|
||||
<PARAMETER NAME="PCW_ENET1_RESET_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET1_RESET_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET_RESET_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_ENET_RESET_POLARITY" VALUE="Active Low" />
|
||||
<PARAMETER NAME="PCW_ENET_RESET_SELECT" VALUE="" />
|
||||
<PARAMETER NAME="PCW_EN_4K_TIMER" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_EN_CLK0_PORT" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_EN_CLK1_PORT" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_EN_CLK2_PORT" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_EN_CLK3_PORT" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_FCLK0_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_FCLK0_PERIPHERAL_DIVISOR0" VALUE="6" />
|
||||
<PARAMETER NAME="PCW_FCLK0_PERIPHERAL_DIVISOR1" VALUE="6" />
|
||||
<PARAMETER NAME="PCW_FCLK1_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_FCLK1_PERIPHERAL_DIVISOR0" VALUE="3" />
|
||||
<PARAMETER NAME="PCW_FCLK1_PERIPHERAL_DIVISOR1" VALUE="3" />
|
||||
<PARAMETER NAME="PCW_FCLK2_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_FCLK2_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_FCLK2_PERIPHERAL_DIVISOR1" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_FCLK3_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_FCLK3_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_FCLK3_PERIPHERAL_DIVISOR1" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_FCLK_CLK0_BUF" VALUE="TRUE" />
|
||||
<PARAMETER NAME="PCW_FCLK_CLK1_BUF" VALUE="FALSE" />
|
||||
<PARAMETER NAME="PCW_FCLK_CLK2_BUF" VALUE="FALSE" />
|
||||
<PARAMETER NAME="PCW_FCLK_CLK3_BUF" VALUE="FALSE" />
|
||||
<PARAMETER NAME="PCW_FPGA0_PERIPHERAL_FREQMHZ" VALUE="50" />
|
||||
<PARAMETER NAME="PCW_FPGA1_PERIPHERAL_FREQMHZ" VALUE="200" />
|
||||
<PARAMETER NAME="PCW_FPGA2_PERIPHERAL_FREQMHZ" VALUE="50" />
|
||||
<PARAMETER NAME="PCW_FPGA3_PERIPHERAL_FREQMHZ" VALUE="50" />
|
||||
<PARAMETER NAME="PCW_FTM_CTI_IN0" VALUE="" />
|
||||
<PARAMETER NAME="PCW_FTM_CTI_IN1" VALUE="" />
|
||||
<PARAMETER NAME="PCW_FTM_CTI_IN2" VALUE="" />
|
||||
<PARAMETER NAME="PCW_FTM_CTI_IN3" VALUE="" />
|
||||
<PARAMETER NAME="PCW_FTM_CTI_OUT0" VALUE="" />
|
||||
<PARAMETER NAME="PCW_FTM_CTI_OUT1" VALUE="" />
|
||||
<PARAMETER NAME="PCW_FTM_CTI_OUT2" VALUE="" />
|
||||
<PARAMETER NAME="PCW_FTM_CTI_OUT3" VALUE="" />
|
||||
<PARAMETER NAME="PCW_GPIO_EMIO_GPIO_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_GPIO_EMIO_GPIO_IO" VALUE="48" />
|
||||
<PARAMETER NAME="PCW_GPIO_MIO_GPIO_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_GPIO_MIO_GPIO_IO" VALUE="MIO" />
|
||||
<PARAMETER NAME="PCW_GPIO_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_I2C0_GRP_INT_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_I2C0_GRP_INT_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_I2C0_I2C0_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_I2C0_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_I2C0_RESET_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_I2C0_RESET_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_I2C1_GRP_INT_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_I2C1_GRP_INT_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_I2C1_I2C1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_I2C1_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_I2C1_RESET_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_I2C1_RESET_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_I2C_RESET_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_I2C_RESET_POLARITY" VALUE="Active Low" />
|
||||
<PARAMETER NAME="PCW_I2C_RESET_SELECT" VALUE="" />
|
||||
<PARAMETER NAME="PCW_IOPLL_CTRL_FBDIV" VALUE="54" />
|
||||
<PARAMETER NAME="PCW_IO_IO_PLL_FREQMHZ" VALUE="1800.000" />
|
||||
<PARAMETER NAME="PCW_IRQ_F2P_MODE" VALUE="DIRECT" />
|
||||
<PARAMETER NAME="PCW_MIO_0_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_0_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_0_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_0_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_10_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_10_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_10_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_10_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_11_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_11_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_11_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_11_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_12_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_12_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_12_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_12_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_13_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_13_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_13_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_13_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_14_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_14_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_14_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_14_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_15_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_15_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_15_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_15_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_16_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_16_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_16_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_16_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_17_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_17_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_17_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_17_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_18_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_18_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_18_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_18_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_19_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_19_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_19_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_19_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_1_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_1_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_1_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_1_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_20_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_20_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_20_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_20_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_21_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_21_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_21_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_21_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_22_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_22_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_22_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_22_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_23_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_23_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_23_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_23_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_24_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_24_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_24_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_24_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_25_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_25_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_25_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_25_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_26_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_26_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_26_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_26_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_27_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_27_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_27_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_27_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_28_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_28_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_28_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_28_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_29_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_29_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_29_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_29_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_2_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_2_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_2_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_2_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_30_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_30_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_30_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_30_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_31_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_31_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_31_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_31_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_32_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_32_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_32_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_32_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_33_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_33_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_33_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_33_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_34_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_34_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_34_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_34_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_35_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_35_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_35_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_35_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_36_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_36_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_36_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_36_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_37_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_37_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_37_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_37_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_38_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_38_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_38_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_38_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_39_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_39_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_39_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_39_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_3_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_3_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_3_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_3_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_40_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_40_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_40_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_40_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_41_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_41_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_41_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_41_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_42_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_42_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_42_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_42_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_43_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_43_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_43_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_43_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_44_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_44_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_44_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_44_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_45_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_45_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_45_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_45_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_46_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_46_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_46_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_46_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_47_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_47_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_47_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_47_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_48_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_48_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_48_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_48_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_49_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_49_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_49_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_49_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_4_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_4_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_4_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_4_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_50_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_50_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_50_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_50_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_51_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_51_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_51_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_51_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_52_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_52_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_52_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_52_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_53_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_53_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_53_PULLUP" VALUE="enabled" />
|
||||
<PARAMETER NAME="PCW_MIO_53_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_5_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_5_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_5_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_5_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_6_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_6_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_6_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_6_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_7_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_7_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_7_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_7_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_8_DIRECTION" VALUE="out" />
|
||||
<PARAMETER NAME="PCW_MIO_8_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_8_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_8_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_MIO_9_DIRECTION" VALUE="inout" />
|
||||
<PARAMETER NAME="PCW_MIO_9_IOTYPE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_MIO_9_PULLUP" VALUE="disabled" />
|
||||
<PARAMETER NAME="PCW_MIO_9_SLEW" VALUE="slow" />
|
||||
<PARAMETER NAME="PCW_NAND_CYCLES_T_AR" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NAND_CYCLES_T_CLR" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NAND_CYCLES_T_RC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NAND_CYCLES_T_REA" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NAND_CYCLES_T_RR" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NAND_CYCLES_T_WC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NAND_CYCLES_T_WP" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NAND_GRP_D8_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NAND_GRP_D8_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NAND_NAND_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NAND_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_NOR_CS0_T_CEOE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_CS0_T_PC" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_CS0_T_RC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NOR_CS0_T_TR" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_CS0_T_WC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NOR_CS0_T_WP" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_CS0_WE_TIME" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_NOR_CS1_T_CEOE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_CS1_T_PC" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_CS1_T_RC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NOR_CS1_T_TR" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_CS1_T_WC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NOR_CS1_T_WP" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_CS1_WE_TIME" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_A25_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_A25_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_CS0_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_CS0_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_CS1_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_CS1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_SRAM_CS0_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_SRAM_CS0_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_SRAM_CS1_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_SRAM_CS1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_SRAM_INT_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_GRP_SRAM_INT_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_NOR_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_NOR_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_CEOE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_PC" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_RC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_TR" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_WC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS0_T_WP" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS0_WE_TIME" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_CEOE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_PC" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_RC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_TR" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_WC" VALUE="11" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS1_T_WP" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_NOR_SRAM_CS1_WE_TIME" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_OVERRIDE_BASIC_CLOCK" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_PCAP_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_PCAP_PERIPHERAL_DIVISOR0" VALUE="9" />
|
||||
<PARAMETER NAME="PCW_PCAP_PERIPHERAL_FREQMHZ" VALUE="200" />
|
||||
<PARAMETER NAME="PCW_PJTAG_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_PJTAG_PJTAG_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_PLL_BYPASSMODE_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_PRESET_BANK0_VOLTAGE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_PRESET_BANK1_VOLTAGE" VALUE="LVCMOS 1.8V" />
|
||||
<PARAMETER NAME="PCW_QSPI_GRP_FBCLK_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_QSPI_GRP_FBCLK_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_QSPI_GRP_IO1_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_QSPI_GRP_IO1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_QSPI_GRP_SINGLE_SS_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_QSPI_GRP_SINGLE_SS_IO" VALUE="MIO 1 .. 6" />
|
||||
<PARAMETER NAME="PCW_QSPI_GRP_SS1_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_QSPI_GRP_SS1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_QSPI_INTERNAL_HIGHADDRESS" VALUE="0xFCFFFFFF" />
|
||||
<PARAMETER NAME="PCW_QSPI_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_QSPI_PERIPHERAL_DIVISOR0" VALUE="9" />
|
||||
<PARAMETER NAME="PCW_QSPI_PERIPHERAL_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_QSPI_PERIPHERAL_FREQMHZ" VALUE="200" />
|
||||
<PARAMETER NAME="PCW_QSPI_QSPI_IO" VALUE="MIO 1 .. 6" />
|
||||
<PARAMETER NAME="PCW_SD0_GRP_CD_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD0_GRP_CD_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD0_GRP_POW_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD0_GRP_POW_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD0_GRP_WP_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD0_GRP_WP_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD0_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_SD0_SD0_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD1_GRP_CD_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD1_GRP_CD_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD1_GRP_POW_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD1_GRP_POW_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD1_GRP_WP_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD1_GRP_WP_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SD1_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_SD1_SD1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SDIO_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_SDIO_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_SDIO_PERIPHERAL_FREQMHZ" VALUE="100" />
|
||||
<PARAMETER NAME="PCW_SINGLE_QSPI_DATA_MODE" VALUE="x4" />
|
||||
<PARAMETER NAME="PCW_SMC_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_SMC_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_SMC_PERIPHERAL_FREQMHZ" VALUE="100" />
|
||||
<PARAMETER NAME="PCW_SPI0_GRP_SS0_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI0_GRP_SS0_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI0_GRP_SS1_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI0_GRP_SS1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI0_GRP_SS2_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI0_GRP_SS2_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI0_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_SPI0_SPI0_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI1_GRP_SS0_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI1_GRP_SS0_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI1_GRP_SS1_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI1_GRP_SS1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI1_GRP_SS2_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI1_GRP_SS2_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI1_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_SPI1_SPI1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_SPI_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_SPI_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_SPI_PERIPHERAL_FREQMHZ" VALUE="166.666666" />
|
||||
<PARAMETER NAME="PCW_S_AXI_HP0_DATA_WIDTH" VALUE="64" />
|
||||
<PARAMETER NAME="PCW_S_AXI_HP1_DATA_WIDTH" VALUE="64" />
|
||||
<PARAMETER NAME="PCW_S_AXI_HP2_DATA_WIDTH" VALUE="64" />
|
||||
<PARAMETER NAME="PCW_S_AXI_HP3_DATA_WIDTH" VALUE="64" />
|
||||
<PARAMETER NAME="PCW_TPIU_PERIPHERAL_CLKSRC" VALUE="External" />
|
||||
<PARAMETER NAME="PCW_TPIU_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_TPIU_PERIPHERAL_FREQMHZ" VALUE="200" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_16BIT_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_16BIT_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_2BIT_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_2BIT_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_32BIT_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_32BIT_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_4BIT_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_4BIT_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_8BIT_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_GRP_8BIT_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TRACE_INTERNAL_WIDTH" VALUE="2" />
|
||||
<PARAMETER NAME="PCW_TRACE_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_TRACE_TRACE_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TTC0_CLK0_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
|
||||
<PARAMETER NAME="PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
|
||||
<PARAMETER NAME="PCW_TTC0_CLK1_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
|
||||
<PARAMETER NAME="PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
|
||||
<PARAMETER NAME="PCW_TTC0_CLK2_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
|
||||
<PARAMETER NAME="PCW_TTC0_CLK2_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
|
||||
<PARAMETER NAME="PCW_TTC0_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_TTC0_TTC0_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TTC1_CLK0_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
|
||||
<PARAMETER NAME="PCW_TTC1_CLK0_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
|
||||
<PARAMETER NAME="PCW_TTC1_CLK1_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
|
||||
<PARAMETER NAME="PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
|
||||
<PARAMETER NAME="PCW_TTC1_CLK2_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
|
||||
<PARAMETER NAME="PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
|
||||
<PARAMETER NAME="PCW_TTC1_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_TTC1_TTC1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_TTC_PERIPHERAL_FREQMHZ" VALUE="50" />
|
||||
<PARAMETER NAME="PCW_UART0_BAUD_RATE" VALUE="115200" />
|
||||
<PARAMETER NAME="PCW_UART0_GRP_FULL_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_UART0_GRP_FULL_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_UART0_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UART0_UART0_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_UART1_BAUD_RATE" VALUE="115200" />
|
||||
<PARAMETER NAME="PCW_UART1_GRP_FULL_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_UART1_GRP_FULL_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_UART1_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UART1_UART1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_UART_PERIPHERAL_CLKSRC" VALUE="IO PLL" />
|
||||
<PARAMETER NAME="PCW_UART_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_UART_PERIPHERAL_FREQMHZ" VALUE="100" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_ADV_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_AL" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_BANK_ADDR_COUNT" VALUE="3" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_BL" VALUE="8" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY0" VALUE="0.25" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY1" VALUE="0.25" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY2" VALUE="0.25" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_BOARD_DELAY3" VALUE="0.25" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_BUS_WIDTH" VALUE="16 Bit" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CL" VALUE="7" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH" VALUE="80.0515" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH" VALUE="80.0515" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH" VALUE="80.0515" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH" VALUE="80.0515" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CLOCK_STOP_EN" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_COL_ADDR_COUNT" VALUE="10" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_CWL" VALUE="6" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DEVICE_CAPACITY" VALUE="4096 MBits" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_0_LENGTH_MM" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH" VALUE="133.8645" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_1_LENGTH_MM" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH" VALUE="119.997" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_2_LENGTH_MM" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH" VALUE="121.146" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_3_LENGTH_MM" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH" VALUE="90.125" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0" VALUE="0.0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1" VALUE="0.0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2" VALUE="0.0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3" VALUE="0.0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_0_LENGTH_MM" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH" VALUE="111.7605" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_1_LENGTH_MM" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH" VALUE="123.5525" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_2_LENGTH_MM" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH" VALUE="120.714" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_3_LENGTH_MM" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH" VALUE="100.836" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY" VALUE="160" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_DRAM_WIDTH" VALUE="16 Bits" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_ECC" VALUE="Disabled" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_ENABLE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_FREQ_MHZ" VALUE="533.333333" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_HIGH_TEMP" VALUE="Normal (0-85)" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_MEMORY_TYPE" VALUE="DDR 3" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_PARTNO" VALUE="MT41J256M16 RE-125" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_ROW_ADDR_COUNT" VALUE="15" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_SPEED_BIN" VALUE="DDR3_1066F" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_TRAIN_DATA_EYE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_TRAIN_READ_GATE" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_T_FAW" VALUE="40.0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_T_RAS_MIN" VALUE="35.0" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_T_RC" VALUE="48.91" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_T_RCD" VALUE="7" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_T_RP" VALUE="7" />
|
||||
<PARAMETER NAME="PCW_UIPARAM_DDR_USE_INTERNAL_VREF" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USB0_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USB0_PERIPHERAL_FREQMHZ" VALUE="60" />
|
||||
<PARAMETER NAME="PCW_USB0_RESET_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_USB0_RESET_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_USB0_USB0_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_USB1_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USB1_PERIPHERAL_FREQMHZ" VALUE="60" />
|
||||
<PARAMETER NAME="PCW_USB1_RESET_ENABLE" VALUE="" />
|
||||
<PARAMETER NAME="PCW_USB1_RESET_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_USB1_USB1_IO" VALUE="" />
|
||||
<PARAMETER NAME="PCW_USB_RESET_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USB_RESET_POLARITY" VALUE="Active Low" />
|
||||
<PARAMETER NAME="PCW_USB_RESET_SELECT" VALUE="" />
|
||||
<PARAMETER NAME="PCW_USE_AXI_NONSECURE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USE_CROSS_TRIGGER" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USE_M_AXI_GP0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_USE_M_AXI_GP1" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USE_S_AXI_ACP" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USE_S_AXI_GP0" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USE_S_AXI_GP1" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USE_S_AXI_HP0" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USE_S_AXI_HP1" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USE_S_AXI_HP2" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_USE_S_AXI_HP3" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_WDT_PERIPHERAL_CLKSRC" VALUE="CPU_1X" />
|
||||
<PARAMETER NAME="PCW_WDT_PERIPHERAL_DIVISOR0" VALUE="1" />
|
||||
<PARAMETER NAME="PCW_WDT_PERIPHERAL_ENABLE" VALUE="0" />
|
||||
<PARAMETER NAME="PCW_WDT_PERIPHERAL_FREQMHZ" VALUE="133.333333" />
|
||||
<PARAMETER NAME="PCW_WDT_WDT_IO" VALUE="" />
|
||||
</PARAMETERS>
|
||||
<BUSINTERFACES >
|
||||
<BUSINTERFACE NAME="M_AXI_GP0" TYPE="MASTER" WIDTH="32" PARAMTOENABLE="PCW_USE_M_AXI_GP0" VALUE="1" />
|
||||
<BUSINTERFACE NAME="M_AXI_GP1" TYPE="MASTER" WIDTH="32" PARAMTOENABLE="PCW_USE_M_AXI_GP1" VALUE="0" />
|
||||
<BUSINTERFACE NAME="S_AXI_GP0" TYPE="TARGET" WIDTH="32" PARAMTOENABLE="PCW_USE_S_AXI_GP0" VALUE="0" />
|
||||
<BUSINTERFACE NAME="S_AXI_GP0" TYPE="TARGET" WIDTH="32" PARAMTOENABLE="PCW_USE_S_AXI_GP1" VALUE="0" />
|
||||
<BUSINTERFACE NAME="S_AXI_HP0" TYPE="TARGET" WIDTH="64" PARAMTOENABLE="PCW_USE_S_AXI_HP0" VALUE="0" />
|
||||
<BUSINTERFACE NAME="S_AXI_HP1" TYPE="TARGET" WIDTH="64" PARAMTOENABLE="PCW_USE_S_AXI_HP1" VALUE="0" />
|
||||
<BUSINTERFACE NAME="S_AXI_HP2" TYPE="TARGET" WIDTH="64" PARAMTOENABLE="PCW_USE_S_AXI_HP2" VALUE="0" />
|
||||
<BUSINTERFACE NAME="S_AXI_HP3" TYPE="TARGET" WIDTH="64" PARAMTOENABLE="PCW_USE_S_AXI_HP1" VALUE="0" />
|
||||
</BUSINTERFACES>
|
||||
<CLOCKOUTS >
|
||||
<CLOCKOUT NAME="FCLK_CLK0" FREQUENCY="50.000000" />
|
||||
<CLOCKOUT NAME="FCLK_CLK1" FREQUENCY="200.000000" />
|
||||
<CLOCKOUT NAME="FCLK_CLK2" FREQUENCY="10.000000" />
|
||||
<CLOCKOUT NAME="FCLK_CLK3" FREQUENCY="10.000000" />
|
||||
</CLOCKOUTS>
|
||||
</MODULE>
|
||||
</designInfo>
|
||||
Binary file not shown.
Binary file not shown.
BIN
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BIN
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+1153
File diff suppressed because it is too large
Load Diff
+588
@@ -0,0 +1,588 @@
|
||||
|
||||
|
||||
|
||||
// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:processing_system7_vip:1.0
|
||||
// IP Revision: 1
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
module system_bd_ps_system_0 (
|
||||
GPIO_I,
|
||||
GPIO_O,
|
||||
GPIO_T,
|
||||
M_AXI_GP0_ARVALID,
|
||||
M_AXI_GP0_AWVALID,
|
||||
M_AXI_GP0_BREADY,
|
||||
M_AXI_GP0_RREADY,
|
||||
M_AXI_GP0_WLAST,
|
||||
M_AXI_GP0_WVALID,
|
||||
M_AXI_GP0_ARID,
|
||||
M_AXI_GP0_AWID,
|
||||
M_AXI_GP0_WID,
|
||||
M_AXI_GP0_ARBURST,
|
||||
M_AXI_GP0_ARLOCK,
|
||||
M_AXI_GP0_ARSIZE,
|
||||
M_AXI_GP0_AWBURST,
|
||||
M_AXI_GP0_AWLOCK,
|
||||
M_AXI_GP0_AWSIZE,
|
||||
M_AXI_GP0_ARPROT,
|
||||
M_AXI_GP0_AWPROT,
|
||||
M_AXI_GP0_ARADDR,
|
||||
M_AXI_GP0_AWADDR,
|
||||
M_AXI_GP0_WDATA,
|
||||
M_AXI_GP0_ARCACHE,
|
||||
M_AXI_GP0_ARLEN,
|
||||
M_AXI_GP0_ARQOS,
|
||||
M_AXI_GP0_AWCACHE,
|
||||
M_AXI_GP0_AWLEN,
|
||||
M_AXI_GP0_AWQOS,
|
||||
M_AXI_GP0_WSTRB,
|
||||
M_AXI_GP0_ACLK,
|
||||
M_AXI_GP0_ARREADY,
|
||||
M_AXI_GP0_AWREADY,
|
||||
M_AXI_GP0_BVALID,
|
||||
M_AXI_GP0_RLAST,
|
||||
M_AXI_GP0_RVALID,
|
||||
M_AXI_GP0_WREADY,
|
||||
M_AXI_GP0_BID,
|
||||
M_AXI_GP0_RID,
|
||||
M_AXI_GP0_BRESP,
|
||||
M_AXI_GP0_RRESP,
|
||||
M_AXI_GP0_RDATA,
|
||||
IRQ_F2P,
|
||||
FCLK_CLK0,
|
||||
FCLK_CLK1,
|
||||
FCLK_RESET0_N,
|
||||
MIO,
|
||||
DDR_CAS_n,
|
||||
DDR_CKE,
|
||||
DDR_Clk_n,
|
||||
DDR_Clk,
|
||||
DDR_CS_n,
|
||||
DDR_DRSTB,
|
||||
DDR_ODT,
|
||||
DDR_RAS_n,
|
||||
DDR_WEB,
|
||||
DDR_BankAddr,
|
||||
DDR_Addr,
|
||||
DDR_VRN,
|
||||
DDR_VRP,
|
||||
DDR_DM,
|
||||
DDR_DQ,
|
||||
DDR_DQS_n,
|
||||
DDR_DQS,
|
||||
PS_SRSTB,
|
||||
PS_CLK,
|
||||
PS_PORB
|
||||
);
|
||||
input [47 : 0] GPIO_I;
|
||||
output [47 : 0] GPIO_O;
|
||||
output [47 : 0] GPIO_T;
|
||||
output M_AXI_GP0_ARVALID;
|
||||
output M_AXI_GP0_AWVALID;
|
||||
output M_AXI_GP0_BREADY;
|
||||
output M_AXI_GP0_RREADY;
|
||||
output M_AXI_GP0_WLAST;
|
||||
output M_AXI_GP0_WVALID;
|
||||
output [11 : 0] M_AXI_GP0_ARID;
|
||||
output [11 : 0] M_AXI_GP0_AWID;
|
||||
output [11 : 0] M_AXI_GP0_WID;
|
||||
output [1 : 0] M_AXI_GP0_ARBURST;
|
||||
output [1 : 0] M_AXI_GP0_ARLOCK;
|
||||
output [2 : 0] M_AXI_GP0_ARSIZE;
|
||||
output [1 : 0] M_AXI_GP0_AWBURST;
|
||||
output [1 : 0] M_AXI_GP0_AWLOCK;
|
||||
output [2 : 0] M_AXI_GP0_AWSIZE;
|
||||
output [2 : 0] M_AXI_GP0_ARPROT;
|
||||
output [2 : 0] M_AXI_GP0_AWPROT;
|
||||
output [31 : 0] M_AXI_GP0_ARADDR;
|
||||
output [31 : 0] M_AXI_GP0_AWADDR;
|
||||
output [31 : 0] M_AXI_GP0_WDATA;
|
||||
output [3 : 0] M_AXI_GP0_ARCACHE;
|
||||
output [3 : 0] M_AXI_GP0_ARLEN;
|
||||
output [3 : 0] M_AXI_GP0_ARQOS;
|
||||
output [3 : 0] M_AXI_GP0_AWCACHE;
|
||||
output [3 : 0] M_AXI_GP0_AWLEN;
|
||||
output [3 : 0] M_AXI_GP0_AWQOS;
|
||||
output [3 : 0] M_AXI_GP0_WSTRB;
|
||||
input M_AXI_GP0_ACLK;
|
||||
input M_AXI_GP0_ARREADY;
|
||||
input M_AXI_GP0_AWREADY;
|
||||
input M_AXI_GP0_BVALID;
|
||||
input M_AXI_GP0_RLAST;
|
||||
input M_AXI_GP0_RVALID;
|
||||
input M_AXI_GP0_WREADY;
|
||||
input [11 : 0] M_AXI_GP0_BID;
|
||||
input [11 : 0] M_AXI_GP0_RID;
|
||||
input [1 : 0] M_AXI_GP0_BRESP;
|
||||
input [1 : 0] M_AXI_GP0_RRESP;
|
||||
input [31 : 0] M_AXI_GP0_RDATA;
|
||||
input [0 : 0] IRQ_F2P;
|
||||
output FCLK_CLK0;
|
||||
output FCLK_CLK1;
|
||||
output FCLK_RESET0_N;
|
||||
input [53 : 0] MIO;
|
||||
input DDR_CAS_n;
|
||||
input DDR_CKE;
|
||||
input DDR_Clk_n;
|
||||
input DDR_Clk;
|
||||
input DDR_CS_n;
|
||||
input DDR_DRSTB;
|
||||
input DDR_ODT;
|
||||
input DDR_RAS_n;
|
||||
input DDR_WEB;
|
||||
input [2 : 0] DDR_BankAddr;
|
||||
input [14 : 0] DDR_Addr;
|
||||
input DDR_VRN;
|
||||
input DDR_VRP;
|
||||
input [3 : 0] DDR_DM;
|
||||
input [31 : 0] DDR_DQ;
|
||||
input [3 : 0] DDR_DQS_n;
|
||||
input [3 : 0] DDR_DQS;
|
||||
input PS_SRSTB;
|
||||
input PS_CLK;
|
||||
input PS_PORB;
|
||||
|
||||
processing_system7_vip_v1_0_7 #(
|
||||
.C_USE_M_AXI_GP0(1),
|
||||
.C_USE_M_AXI_GP1(0),
|
||||
.C_USE_S_AXI_ACP(0),
|
||||
.C_USE_S_AXI_GP0(0),
|
||||
.C_USE_S_AXI_GP1(0),
|
||||
.C_USE_S_AXI_HP0(0),
|
||||
.C_USE_S_AXI_HP1(0),
|
||||
.C_USE_S_AXI_HP2(0),
|
||||
.C_USE_S_AXI_HP3(0),
|
||||
.C_S_AXI_HP0_DATA_WIDTH(64),
|
||||
.C_S_AXI_HP1_DATA_WIDTH(64),
|
||||
.C_S_AXI_HP2_DATA_WIDTH(64),
|
||||
.C_S_AXI_HP3_DATA_WIDTH(64),
|
||||
.C_HIGH_OCM_EN(0),
|
||||
.C_FCLK_CLK0_FREQ(50.0),
|
||||
.C_FCLK_CLK1_FREQ(200.0),
|
||||
.C_FCLK_CLK2_FREQ(10.0),
|
||||
.C_FCLK_CLK3_FREQ(10.0),
|
||||
.C_M_AXI_GP0_ENABLE_STATIC_REMAP(0),
|
||||
.C_M_AXI_GP1_ENABLE_STATIC_REMAP(0),
|
||||
.C_M_AXI_GP0_THREAD_ID_WIDTH (12),
|
||||
.C_M_AXI_GP1_THREAD_ID_WIDTH (12)
|
||||
) inst (
|
||||
.M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
|
||||
.M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
|
||||
.M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
|
||||
.M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
|
||||
.M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
|
||||
.M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
|
||||
.M_AXI_GP0_ARID(M_AXI_GP0_ARID),
|
||||
.M_AXI_GP0_AWID(M_AXI_GP0_AWID),
|
||||
.M_AXI_GP0_WID(M_AXI_GP0_WID),
|
||||
.M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
|
||||
.M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
|
||||
.M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
|
||||
.M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
|
||||
.M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
|
||||
.M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
|
||||
.M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
|
||||
.M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
|
||||
.M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
|
||||
.M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
|
||||
.M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
|
||||
.M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
|
||||
.M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
|
||||
.M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
|
||||
.M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
|
||||
.M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
|
||||
.M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
|
||||
.M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
|
||||
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
|
||||
.M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
|
||||
.M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
|
||||
.M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
|
||||
.M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
|
||||
.M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
|
||||
.M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
|
||||
.M_AXI_GP0_BID(M_AXI_GP0_BID),
|
||||
.M_AXI_GP0_RID(M_AXI_GP0_RID),
|
||||
.M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
|
||||
.M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
|
||||
.M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
|
||||
.M_AXI_GP1_ARVALID(),
|
||||
.M_AXI_GP1_AWVALID(),
|
||||
.M_AXI_GP1_BREADY(),
|
||||
.M_AXI_GP1_RREADY(),
|
||||
.M_AXI_GP1_WLAST(),
|
||||
.M_AXI_GP1_WVALID(),
|
||||
.M_AXI_GP1_ARID(),
|
||||
.M_AXI_GP1_AWID(),
|
||||
.M_AXI_GP1_WID(),
|
||||
.M_AXI_GP1_ARBURST(),
|
||||
.M_AXI_GP1_ARLOCK(),
|
||||
.M_AXI_GP1_ARSIZE(),
|
||||
.M_AXI_GP1_AWBURST(),
|
||||
.M_AXI_GP1_AWLOCK(),
|
||||
.M_AXI_GP1_AWSIZE(),
|
||||
.M_AXI_GP1_ARPROT(),
|
||||
.M_AXI_GP1_AWPROT(),
|
||||
.M_AXI_GP1_ARADDR(),
|
||||
.M_AXI_GP1_AWADDR(),
|
||||
.M_AXI_GP1_WDATA(),
|
||||
.M_AXI_GP1_ARCACHE(),
|
||||
.M_AXI_GP1_ARLEN(),
|
||||
.M_AXI_GP1_ARQOS(),
|
||||
.M_AXI_GP1_AWCACHE(),
|
||||
.M_AXI_GP1_AWLEN(),
|
||||
.M_AXI_GP1_AWQOS(),
|
||||
.M_AXI_GP1_WSTRB(),
|
||||
.M_AXI_GP1_ACLK(1'B0),
|
||||
.M_AXI_GP1_ARREADY(1'B0),
|
||||
.M_AXI_GP1_AWREADY(1'B0),
|
||||
.M_AXI_GP1_BVALID(1'B0),
|
||||
.M_AXI_GP1_RLAST(1'B0),
|
||||
.M_AXI_GP1_RVALID(1'B0),
|
||||
.M_AXI_GP1_WREADY(1'B0),
|
||||
.M_AXI_GP1_BID(12'B0),
|
||||
.M_AXI_GP1_RID(12'B0),
|
||||
.M_AXI_GP1_BRESP(2'B0),
|
||||
.M_AXI_GP1_RRESP(2'B0),
|
||||
.M_AXI_GP1_RDATA(32'B0),
|
||||
.S_AXI_GP0_ARREADY(),
|
||||
.S_AXI_GP0_AWREADY(),
|
||||
.S_AXI_GP0_BVALID(),
|
||||
.S_AXI_GP0_RLAST(),
|
||||
.S_AXI_GP0_RVALID(),
|
||||
.S_AXI_GP0_WREADY(),
|
||||
.S_AXI_GP0_BRESP(),
|
||||
.S_AXI_GP0_RRESP(),
|
||||
.S_AXI_GP0_RDATA(),
|
||||
.S_AXI_GP0_BID(),
|
||||
.S_AXI_GP0_RID(),
|
||||
.S_AXI_GP0_ACLK(1'B0),
|
||||
.S_AXI_GP0_ARVALID(1'B0),
|
||||
.S_AXI_GP0_AWVALID(1'B0),
|
||||
.S_AXI_GP0_BREADY(1'B0),
|
||||
.S_AXI_GP0_RREADY(1'B0),
|
||||
.S_AXI_GP0_WLAST(1'B0),
|
||||
.S_AXI_GP0_WVALID(1'B0),
|
||||
.S_AXI_GP0_ARBURST(2'B0),
|
||||
.S_AXI_GP0_ARLOCK(2'B0),
|
||||
.S_AXI_GP0_ARSIZE(3'B0),
|
||||
.S_AXI_GP0_AWBURST(2'B0),
|
||||
.S_AXI_GP0_AWLOCK(2'B0),
|
||||
.S_AXI_GP0_AWSIZE(3'B0),
|
||||
.S_AXI_GP0_ARPROT(3'B0),
|
||||
.S_AXI_GP0_AWPROT(3'B0),
|
||||
.S_AXI_GP0_ARADDR(32'B0),
|
||||
.S_AXI_GP0_AWADDR(32'B0),
|
||||
.S_AXI_GP0_WDATA(32'B0),
|
||||
.S_AXI_GP0_ARCACHE(4'B0),
|
||||
.S_AXI_GP0_ARLEN(4'B0),
|
||||
.S_AXI_GP0_ARQOS(4'B0),
|
||||
.S_AXI_GP0_AWCACHE(4'B0),
|
||||
.S_AXI_GP0_AWLEN(4'B0),
|
||||
.S_AXI_GP0_AWQOS(4'B0),
|
||||
.S_AXI_GP0_WSTRB(4'B0),
|
||||
.S_AXI_GP0_ARID(6'B0),
|
||||
.S_AXI_GP0_AWID(6'B0),
|
||||
.S_AXI_GP0_WID(6'B0),
|
||||
.S_AXI_GP1_ARREADY(),
|
||||
.S_AXI_GP1_AWREADY(),
|
||||
.S_AXI_GP1_BVALID(),
|
||||
.S_AXI_GP1_RLAST(),
|
||||
.S_AXI_GP1_RVALID(),
|
||||
.S_AXI_GP1_WREADY(),
|
||||
.S_AXI_GP1_BRESP(),
|
||||
.S_AXI_GP1_RRESP(),
|
||||
.S_AXI_GP1_RDATA(),
|
||||
.S_AXI_GP1_BID(),
|
||||
.S_AXI_GP1_RID(),
|
||||
.S_AXI_GP1_ACLK(1'B0),
|
||||
.S_AXI_GP1_ARVALID(1'B0),
|
||||
.S_AXI_GP1_AWVALID(1'B0),
|
||||
.S_AXI_GP1_BREADY(1'B0),
|
||||
.S_AXI_GP1_RREADY(1'B0),
|
||||
.S_AXI_GP1_WLAST(1'B0),
|
||||
.S_AXI_GP1_WVALID(1'B0),
|
||||
.S_AXI_GP1_ARBURST(2'B0),
|
||||
.S_AXI_GP1_ARLOCK(2'B0),
|
||||
.S_AXI_GP1_ARSIZE(3'B0),
|
||||
.S_AXI_GP1_AWBURST(2'B0),
|
||||
.S_AXI_GP1_AWLOCK(2'B0),
|
||||
.S_AXI_GP1_AWSIZE(3'B0),
|
||||
.S_AXI_GP1_ARPROT(3'B0),
|
||||
.S_AXI_GP1_AWPROT(3'B0),
|
||||
.S_AXI_GP1_ARADDR(32'B0),
|
||||
.S_AXI_GP1_AWADDR(32'B0),
|
||||
.S_AXI_GP1_WDATA(32'B0),
|
||||
.S_AXI_GP1_ARCACHE(4'B0),
|
||||
.S_AXI_GP1_ARLEN(4'B0),
|
||||
.S_AXI_GP1_ARQOS(4'B0),
|
||||
.S_AXI_GP1_AWCACHE(4'B0),
|
||||
.S_AXI_GP1_AWLEN(4'B0),
|
||||
.S_AXI_GP1_AWQOS(4'B0),
|
||||
.S_AXI_GP1_WSTRB(4'B0),
|
||||
.S_AXI_GP1_ARID(6'B0),
|
||||
.S_AXI_GP1_AWID(6'B0),
|
||||
.S_AXI_GP1_WID(6'B0),
|
||||
.S_AXI_ACP_ARREADY(),
|
||||
.S_AXI_ACP_AWREADY(),
|
||||
.S_AXI_ACP_BVALID(),
|
||||
.S_AXI_ACP_RLAST(),
|
||||
.S_AXI_ACP_RVALID(),
|
||||
.S_AXI_ACP_WREADY(),
|
||||
.S_AXI_ACP_BRESP(),
|
||||
.S_AXI_ACP_RRESP(),
|
||||
.S_AXI_ACP_BID(),
|
||||
.S_AXI_ACP_RID(),
|
||||
.S_AXI_ACP_RDATA(),
|
||||
.S_AXI_ACP_ACLK(1'B0),
|
||||
.S_AXI_ACP_ARVALID(1'B0),
|
||||
.S_AXI_ACP_AWVALID(1'B0),
|
||||
.S_AXI_ACP_BREADY(1'B0),
|
||||
.S_AXI_ACP_RREADY(1'B0),
|
||||
.S_AXI_ACP_WLAST(1'B0),
|
||||
.S_AXI_ACP_WVALID(1'B0),
|
||||
.S_AXI_ACP_ARID(3'B0),
|
||||
.S_AXI_ACP_ARPROT(3'B0),
|
||||
.S_AXI_ACP_AWID(3'B0),
|
||||
.S_AXI_ACP_AWPROT(3'B0),
|
||||
.S_AXI_ACP_WID(3'B0),
|
||||
.S_AXI_ACP_ARADDR(32'B0),
|
||||
.S_AXI_ACP_AWADDR(32'B0),
|
||||
.S_AXI_ACP_ARCACHE(4'B0),
|
||||
.S_AXI_ACP_ARLEN(4'B0),
|
||||
.S_AXI_ACP_ARQOS(4'B0),
|
||||
.S_AXI_ACP_AWCACHE(4'B0),
|
||||
.S_AXI_ACP_AWLEN(4'B0),
|
||||
.S_AXI_ACP_AWQOS(4'B0),
|
||||
.S_AXI_ACP_ARBURST(2'B0),
|
||||
.S_AXI_ACP_ARLOCK(2'B0),
|
||||
.S_AXI_ACP_ARSIZE(3'B0),
|
||||
.S_AXI_ACP_AWBURST(2'B0),
|
||||
.S_AXI_ACP_AWLOCK(2'B0),
|
||||
.S_AXI_ACP_AWSIZE(3'B0),
|
||||
.S_AXI_ACP_ARUSER(5'B0),
|
||||
.S_AXI_ACP_AWUSER(5'B0),
|
||||
.S_AXI_ACP_WDATA(64'B0),
|
||||
.S_AXI_ACP_WSTRB(8'B0),
|
||||
.S_AXI_HP0_ARREADY(),
|
||||
.S_AXI_HP0_AWREADY(),
|
||||
.S_AXI_HP0_BVALID(),
|
||||
.S_AXI_HP0_RLAST(),
|
||||
.S_AXI_HP0_RVALID(),
|
||||
.S_AXI_HP0_WREADY(),
|
||||
.S_AXI_HP0_BRESP(),
|
||||
.S_AXI_HP0_RRESP(),
|
||||
.S_AXI_HP0_BID(),
|
||||
.S_AXI_HP0_RID(),
|
||||
.S_AXI_HP0_RDATA(),
|
||||
.S_AXI_HP0_ACLK(1'B0),
|
||||
.S_AXI_HP0_ARVALID(1'B0),
|
||||
.S_AXI_HP0_AWVALID(1'B0),
|
||||
.S_AXI_HP0_BREADY(1'B0),
|
||||
.S_AXI_HP0_RREADY(1'B0),
|
||||
.S_AXI_HP0_WLAST(1'B0),
|
||||
.S_AXI_HP0_WVALID(1'B0),
|
||||
.S_AXI_HP0_ARBURST(2'B0),
|
||||
.S_AXI_HP0_ARLOCK(2'B0),
|
||||
.S_AXI_HP0_ARSIZE(3'B0),
|
||||
.S_AXI_HP0_AWBURST(2'B0),
|
||||
.S_AXI_HP0_AWLOCK(2'B0),
|
||||
.S_AXI_HP0_AWSIZE(3'B0),
|
||||
.S_AXI_HP0_ARPROT(3'B0),
|
||||
.S_AXI_HP0_AWPROT(3'B0),
|
||||
.S_AXI_HP0_ARADDR(32'B0),
|
||||
.S_AXI_HP0_AWADDR(32'B0),
|
||||
.S_AXI_HP0_ARCACHE(4'B0),
|
||||
.S_AXI_HP0_ARLEN(4'B0),
|
||||
.S_AXI_HP0_ARQOS(4'B0),
|
||||
.S_AXI_HP0_AWCACHE(4'B0),
|
||||
.S_AXI_HP0_AWLEN(4'B0),
|
||||
.S_AXI_HP0_AWQOS(4'B0),
|
||||
.S_AXI_HP0_ARID(6'B0),
|
||||
.S_AXI_HP0_AWID(6'B0),
|
||||
.S_AXI_HP0_WID(6'B0),
|
||||
.S_AXI_HP0_WDATA(64'B0),
|
||||
.S_AXI_HP0_WSTRB(8'B0),
|
||||
.S_AXI_HP1_ARREADY(),
|
||||
.S_AXI_HP1_AWREADY(),
|
||||
.S_AXI_HP1_BVALID(),
|
||||
.S_AXI_HP1_RLAST(),
|
||||
.S_AXI_HP1_RVALID(),
|
||||
.S_AXI_HP1_WREADY(),
|
||||
.S_AXI_HP1_BRESP(),
|
||||
.S_AXI_HP1_RRESP(),
|
||||
.S_AXI_HP1_BID(),
|
||||
.S_AXI_HP1_RID(),
|
||||
.S_AXI_HP1_RDATA(),
|
||||
.S_AXI_HP1_ACLK(1'B0),
|
||||
.S_AXI_HP1_ARVALID(1'B0),
|
||||
.S_AXI_HP1_AWVALID(1'B0),
|
||||
.S_AXI_HP1_BREADY(1'B0),
|
||||
.S_AXI_HP1_RREADY(1'B0),
|
||||
.S_AXI_HP1_WLAST(1'B0),
|
||||
.S_AXI_HP1_WVALID(1'B0),
|
||||
.S_AXI_HP1_ARBURST(2'B0),
|
||||
.S_AXI_HP1_ARLOCK(2'B0),
|
||||
.S_AXI_HP1_ARSIZE(3'B0),
|
||||
.S_AXI_HP1_AWBURST(2'B0),
|
||||
.S_AXI_HP1_AWLOCK(2'B0),
|
||||
.S_AXI_HP1_AWSIZE(3'B0),
|
||||
.S_AXI_HP1_ARPROT(3'B0),
|
||||
.S_AXI_HP1_AWPROT(3'B0),
|
||||
.S_AXI_HP1_ARADDR(32'B0),
|
||||
.S_AXI_HP1_AWADDR(32'B0),
|
||||
.S_AXI_HP1_ARCACHE(4'B0),
|
||||
.S_AXI_HP1_ARLEN(4'B0),
|
||||
.S_AXI_HP1_ARQOS(4'B0),
|
||||
.S_AXI_HP1_AWCACHE(4'B0),
|
||||
.S_AXI_HP1_AWLEN(4'B0),
|
||||
.S_AXI_HP1_AWQOS(4'B0),
|
||||
.S_AXI_HP1_ARID(6'B0),
|
||||
.S_AXI_HP1_AWID(6'B0),
|
||||
.S_AXI_HP1_WID(6'B0),
|
||||
.S_AXI_HP1_WDATA(64'B0),
|
||||
.S_AXI_HP1_WSTRB(8'B0),
|
||||
.S_AXI_HP2_ARREADY(),
|
||||
.S_AXI_HP2_AWREADY(),
|
||||
.S_AXI_HP2_BVALID(),
|
||||
.S_AXI_HP2_RLAST(),
|
||||
.S_AXI_HP2_RVALID(),
|
||||
.S_AXI_HP2_WREADY(),
|
||||
.S_AXI_HP2_BRESP(),
|
||||
.S_AXI_HP2_RRESP(),
|
||||
.S_AXI_HP2_BID(),
|
||||
.S_AXI_HP2_RID(),
|
||||
.S_AXI_HP2_RDATA(),
|
||||
.S_AXI_HP2_ACLK(1'B0),
|
||||
.S_AXI_HP2_ARVALID(1'B0),
|
||||
.S_AXI_HP2_AWVALID(1'B0),
|
||||
.S_AXI_HP2_BREADY(1'B0),
|
||||
.S_AXI_HP2_RREADY(1'B0),
|
||||
.S_AXI_HP2_WLAST(1'B0),
|
||||
.S_AXI_HP2_WVALID(1'B0),
|
||||
.S_AXI_HP2_ARBURST(2'B0),
|
||||
.S_AXI_HP2_ARLOCK(2'B0),
|
||||
.S_AXI_HP2_ARSIZE(3'B0),
|
||||
.S_AXI_HP2_AWBURST(2'B0),
|
||||
.S_AXI_HP2_AWLOCK(2'B0),
|
||||
.S_AXI_HP2_AWSIZE(3'B0),
|
||||
.S_AXI_HP2_ARPROT(3'B0),
|
||||
.S_AXI_HP2_AWPROT(3'B0),
|
||||
.S_AXI_HP2_ARADDR(32'B0),
|
||||
.S_AXI_HP2_AWADDR(32'B0),
|
||||
.S_AXI_HP2_ARCACHE(4'B0),
|
||||
.S_AXI_HP2_ARLEN(4'B0),
|
||||
.S_AXI_HP2_ARQOS(4'B0),
|
||||
.S_AXI_HP2_AWCACHE(4'B0),
|
||||
.S_AXI_HP2_AWLEN(4'B0),
|
||||
.S_AXI_HP2_AWQOS(4'B0),
|
||||
.S_AXI_HP2_ARID(6'B0),
|
||||
.S_AXI_HP2_AWID(6'B0),
|
||||
.S_AXI_HP2_WID(6'B0),
|
||||
.S_AXI_HP2_WDATA(64'B0),
|
||||
.S_AXI_HP2_WSTRB(8'B0),
|
||||
.S_AXI_HP3_ARREADY(),
|
||||
.S_AXI_HP3_AWREADY(),
|
||||
.S_AXI_HP3_BVALID(),
|
||||
.S_AXI_HP3_RLAST(),
|
||||
.S_AXI_HP3_RVALID(),
|
||||
.S_AXI_HP3_WREADY(),
|
||||
.S_AXI_HP3_BRESP(),
|
||||
.S_AXI_HP3_RRESP(),
|
||||
.S_AXI_HP3_BID(),
|
||||
.S_AXI_HP3_RID(),
|
||||
.S_AXI_HP3_RDATA(),
|
||||
.S_AXI_HP3_ACLK(1'B0),
|
||||
.S_AXI_HP3_ARVALID(1'B0),
|
||||
.S_AXI_HP3_AWVALID(1'B0),
|
||||
.S_AXI_HP3_BREADY(1'B0),
|
||||
.S_AXI_HP3_RREADY(1'B0),
|
||||
.S_AXI_HP3_WLAST(1'B0),
|
||||
.S_AXI_HP3_WVALID(1'B0),
|
||||
.S_AXI_HP3_ARBURST(2'B0),
|
||||
.S_AXI_HP3_ARLOCK(2'B0),
|
||||
.S_AXI_HP3_ARSIZE(3'B0),
|
||||
.S_AXI_HP3_AWBURST(2'B0),
|
||||
.S_AXI_HP3_AWLOCK(2'B0),
|
||||
.S_AXI_HP3_AWSIZE(3'B0),
|
||||
.S_AXI_HP3_ARPROT(3'B0),
|
||||
.S_AXI_HP3_AWPROT(3'B0),
|
||||
.S_AXI_HP3_ARADDR(32'B0),
|
||||
.S_AXI_HP3_AWADDR(32'B0),
|
||||
.S_AXI_HP3_ARCACHE(4'B0),
|
||||
.S_AXI_HP3_ARLEN(4'B0),
|
||||
.S_AXI_HP3_ARQOS(4'B0),
|
||||
.S_AXI_HP3_AWCACHE(4'B0),
|
||||
.S_AXI_HP3_AWLEN(4'B0),
|
||||
.S_AXI_HP3_AWQOS(4'B0),
|
||||
.S_AXI_HP3_ARID(6'B0),
|
||||
.S_AXI_HP3_AWID(6'B0),
|
||||
.S_AXI_HP3_WID(6'B0),
|
||||
.S_AXI_HP3_WDATA(64'B0),
|
||||
.S_AXI_HP3_WSTRB(8'B0),
|
||||
.FCLK_CLK0(FCLK_CLK0),
|
||||
|
||||
.FCLK_CLK1(FCLK_CLK1),
|
||||
|
||||
.FCLK_CLK2(),
|
||||
|
||||
.FCLK_CLK3(),
|
||||
.FCLK_RESET0_N(FCLK_RESET0_N),
|
||||
.FCLK_RESET1_N(),
|
||||
.FCLK_RESET2_N(),
|
||||
.FCLK_RESET3_N(),
|
||||
.IRQ_F2P(IRQ_F2P),
|
||||
.PS_SRSTB(PS_SRSTB),
|
||||
.PS_CLK(PS_CLK),
|
||||
.PS_PORB(PS_PORB)
|
||||
);
|
||||
endmodule
|
||||
+1005
File diff suppressed because it is too large
Load Diff
LFS
BIN
Binary file not shown.
+1885
File diff suppressed because it is too large
Load Diff
+695
@@ -0,0 +1,695 @@
|
||||
############################################################################
|
||||
##
|
||||
## Xilinx, Inc. 2006 www.xilinx.com
|
||||
############################################################################
|
||||
## File name : ps7_constraints.xdc
|
||||
##
|
||||
## Details : Constraints file
|
||||
## FPGA family: zynq
|
||||
## FPGA: xc7z100ffg900-2
|
||||
## Device Size: xc7z100
|
||||
## Package: ffg900
|
||||
## Speedgrade: -2
|
||||
##
|
||||
##
|
||||
############################################################################
|
||||
############################################################################
|
||||
############################################################################
|
||||
# Clock constraints #
|
||||
############################################################################
|
||||
create_clock -name clk_fpga_0 -period "20" [get_pins "PS7_i/FCLKCLK[0]"]
|
||||
set_input_jitter clk_fpga_0 0.6
|
||||
#The clocks are asynchronous, user should constrain them appropriately.#
|
||||
create_clock -name clk_fpga_1 -period "5" [get_pins "PS7_i/FCLKCLK[1]"]
|
||||
set_input_jitter clk_fpga_1 0.15
|
||||
#The clocks are asynchronous, user should constrain them appropriately.#
|
||||
|
||||
|
||||
############################################################################
|
||||
# I/O STANDARDS and Location Constraints #
|
||||
############################################################################
|
||||
|
||||
# GPIO / gpio[53] / MIO[53]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[53]"]
|
||||
set_property PACKAGE_PIN "C18" [get_ports "MIO[53]"]
|
||||
set_property slew "slow" [get_ports "MIO[53]"]
|
||||
set_property drive "8" [get_ports "MIO[53]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[53]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[53]"]
|
||||
# GPIO / gpio[52] / MIO[52]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[52]"]
|
||||
set_property PACKAGE_PIN "D19" [get_ports "MIO[52]"]
|
||||
set_property slew "slow" [get_ports "MIO[52]"]
|
||||
set_property drive "8" [get_ports "MIO[52]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[52]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[52]"]
|
||||
# GPIO / gpio[51] / MIO[51]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[51]"]
|
||||
set_property PACKAGE_PIN "F19" [get_ports "MIO[51]"]
|
||||
set_property slew "slow" [get_ports "MIO[51]"]
|
||||
set_property drive "8" [get_ports "MIO[51]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[51]"]
|
||||
# GPIO / gpio[50] / MIO[50]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[50]"]
|
||||
set_property PACKAGE_PIN "A19" [get_ports "MIO[50]"]
|
||||
set_property slew "slow" [get_ports "MIO[50]"]
|
||||
set_property drive "8" [get_ports "MIO[50]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[50]"]
|
||||
# GPIO / gpio[49] / MIO[49]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[49]"]
|
||||
set_property PACKAGE_PIN "D18" [get_ports "MIO[49]"]
|
||||
set_property slew "slow" [get_ports "MIO[49]"]
|
||||
set_property drive "8" [get_ports "MIO[49]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[49]"]
|
||||
# GPIO / gpio[48] / MIO[48]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[48]"]
|
||||
set_property PACKAGE_PIN "C19" [get_ports "MIO[48]"]
|
||||
set_property slew "slow" [get_ports "MIO[48]"]
|
||||
set_property drive "8" [get_ports "MIO[48]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[48]"]
|
||||
# GPIO / gpio[47] / MIO[47]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[47]"]
|
||||
set_property PACKAGE_PIN "A18" [get_ports "MIO[47]"]
|
||||
set_property slew "slow" [get_ports "MIO[47]"]
|
||||
set_property drive "8" [get_ports "MIO[47]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[47]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[47]"]
|
||||
# GPIO / gpio[46] / MIO[46]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[46]"]
|
||||
set_property PACKAGE_PIN "F20" [get_ports "MIO[46]"]
|
||||
set_property slew "slow" [get_ports "MIO[46]"]
|
||||
set_property drive "8" [get_ports "MIO[46]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[46]"]
|
||||
# GPIO / gpio[45] / MIO[45]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[45]"]
|
||||
set_property PACKAGE_PIN "H18" [get_ports "MIO[45]"]
|
||||
set_property slew "slow" [get_ports "MIO[45]"]
|
||||
set_property drive "8" [get_ports "MIO[45]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[45]"]
|
||||
# GPIO / gpio[44] / MIO[44]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[44]"]
|
||||
set_property PACKAGE_PIN "E20" [get_ports "MIO[44]"]
|
||||
set_property slew "slow" [get_ports "MIO[44]"]
|
||||
set_property drive "8" [get_ports "MIO[44]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[44]"]
|
||||
# GPIO / gpio[43] / MIO[43]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[43]"]
|
||||
set_property PACKAGE_PIN "E18" [get_ports "MIO[43]"]
|
||||
set_property slew "slow" [get_ports "MIO[43]"]
|
||||
set_property drive "8" [get_ports "MIO[43]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[43]"]
|
||||
# GPIO / gpio[42] / MIO[42]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[42]"]
|
||||
set_property PACKAGE_PIN "D20" [get_ports "MIO[42]"]
|
||||
set_property slew "slow" [get_ports "MIO[42]"]
|
||||
set_property drive "8" [get_ports "MIO[42]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[42]"]
|
||||
# GPIO / gpio[41] / MIO[41]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[41]"]
|
||||
set_property PACKAGE_PIN "J18" [get_ports "MIO[41]"]
|
||||
set_property slew "slow" [get_ports "MIO[41]"]
|
||||
set_property drive "8" [get_ports "MIO[41]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[41]"]
|
||||
# GPIO / gpio[40] / MIO[40]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[40]"]
|
||||
set_property PACKAGE_PIN "B20" [get_ports "MIO[40]"]
|
||||
set_property slew "slow" [get_ports "MIO[40]"]
|
||||
set_property drive "8" [get_ports "MIO[40]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[40]"]
|
||||
# GPIO / gpio[39] / MIO[39]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[39]"]
|
||||
set_property PACKAGE_PIN "F18" [get_ports "MIO[39]"]
|
||||
set_property slew "slow" [get_ports "MIO[39]"]
|
||||
set_property drive "8" [get_ports "MIO[39]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[39]"]
|
||||
# GPIO / gpio[38] / MIO[38]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[38]"]
|
||||
set_property PACKAGE_PIN "A20" [get_ports "MIO[38]"]
|
||||
set_property slew "slow" [get_ports "MIO[38]"]
|
||||
set_property drive "8" [get_ports "MIO[38]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[38]"]
|
||||
# GPIO / gpio[37] / MIO[37]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[37]"]
|
||||
set_property PACKAGE_PIN "B21" [get_ports "MIO[37]"]
|
||||
set_property slew "slow" [get_ports "MIO[37]"]
|
||||
set_property drive "8" [get_ports "MIO[37]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[37]"]
|
||||
# GPIO / gpio[36] / MIO[36]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[36]"]
|
||||
set_property PACKAGE_PIN "H17" [get_ports "MIO[36]"]
|
||||
set_property slew "slow" [get_ports "MIO[36]"]
|
||||
set_property drive "8" [get_ports "MIO[36]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[36]"]
|
||||
# GPIO / gpio[35] / MIO[35]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[35]"]
|
||||
set_property PACKAGE_PIN "G21" [get_ports "MIO[35]"]
|
||||
set_property slew "slow" [get_ports "MIO[35]"]
|
||||
set_property drive "8" [get_ports "MIO[35]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[35]"]
|
||||
# GPIO / gpio[34] / MIO[34]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[34]"]
|
||||
set_property PACKAGE_PIN "K18" [get_ports "MIO[34]"]
|
||||
set_property slew "slow" [get_ports "MIO[34]"]
|
||||
set_property drive "8" [get_ports "MIO[34]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[34]"]
|
||||
# GPIO / gpio[33] / MIO[33]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[33]"]
|
||||
set_property PACKAGE_PIN "G22" [get_ports "MIO[33]"]
|
||||
set_property slew "slow" [get_ports "MIO[33]"]
|
||||
set_property drive "8" [get_ports "MIO[33]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[33]"]
|
||||
# GPIO / gpio[32] / MIO[32]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[32]"]
|
||||
set_property PACKAGE_PIN "K17" [get_ports "MIO[32]"]
|
||||
set_property slew "slow" [get_ports "MIO[32]"]
|
||||
set_property drive "8" [get_ports "MIO[32]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[32]"]
|
||||
# GPIO / gpio[31] / MIO[31]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[31]"]
|
||||
set_property PACKAGE_PIN "H21" [get_ports "MIO[31]"]
|
||||
set_property slew "slow" [get_ports "MIO[31]"]
|
||||
set_property drive "8" [get_ports "MIO[31]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[31]"]
|
||||
# GPIO / gpio[30] / MIO[30]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[30]"]
|
||||
set_property PACKAGE_PIN "L18" [get_ports "MIO[30]"]
|
||||
set_property slew "slow" [get_ports "MIO[30]"]
|
||||
set_property drive "8" [get_ports "MIO[30]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[30]"]
|
||||
# GPIO / gpio[29] / MIO[29]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[29]"]
|
||||
set_property PACKAGE_PIN "H22" [get_ports "MIO[29]"]
|
||||
set_property slew "slow" [get_ports "MIO[29]"]
|
||||
set_property drive "8" [get_ports "MIO[29]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[29]"]
|
||||
# GPIO / gpio[28] / MIO[28]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[28]"]
|
||||
set_property PACKAGE_PIN "L17" [get_ports "MIO[28]"]
|
||||
set_property slew "slow" [get_ports "MIO[28]"]
|
||||
set_property drive "8" [get_ports "MIO[28]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[28]"]
|
||||
# GPIO / gpio[27] / MIO[27]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[27]"]
|
||||
set_property PACKAGE_PIN "G20" [get_ports "MIO[27]"]
|
||||
set_property slew "slow" [get_ports "MIO[27]"]
|
||||
set_property drive "8" [get_ports "MIO[27]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[27]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[27]"]
|
||||
# GPIO / gpio[26] / MIO[26]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[26]"]
|
||||
set_property PACKAGE_PIN "M17" [get_ports "MIO[26]"]
|
||||
set_property slew "slow" [get_ports "MIO[26]"]
|
||||
set_property drive "8" [get_ports "MIO[26]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[26]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[26]"]
|
||||
# GPIO / gpio[25] / MIO[25]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[25]"]
|
||||
set_property PACKAGE_PIN "G19" [get_ports "MIO[25]"]
|
||||
set_property slew "slow" [get_ports "MIO[25]"]
|
||||
set_property drive "8" [get_ports "MIO[25]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[25]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[25]"]
|
||||
# GPIO / gpio[24] / MIO[24]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[24]"]
|
||||
set_property PACKAGE_PIN "M19" [get_ports "MIO[24]"]
|
||||
set_property slew "slow" [get_ports "MIO[24]"]
|
||||
set_property drive "8" [get_ports "MIO[24]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[24]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[24]"]
|
||||
# GPIO / gpio[23] / MIO[23]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[23]"]
|
||||
set_property PACKAGE_PIN "J21" [get_ports "MIO[23]"]
|
||||
set_property slew "slow" [get_ports "MIO[23]"]
|
||||
set_property drive "8" [get_ports "MIO[23]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[23]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[23]"]
|
||||
# GPIO / gpio[22] / MIO[22]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[22]"]
|
||||
set_property PACKAGE_PIN "L20" [get_ports "MIO[22]"]
|
||||
set_property slew "slow" [get_ports "MIO[22]"]
|
||||
set_property drive "8" [get_ports "MIO[22]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[22]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[22]"]
|
||||
# GPIO / gpio[21] / MIO[21]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[21]"]
|
||||
set_property PACKAGE_PIN "J19" [get_ports "MIO[21]"]
|
||||
set_property slew "slow" [get_ports "MIO[21]"]
|
||||
set_property drive "8" [get_ports "MIO[21]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[21]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[21]"]
|
||||
# GPIO / gpio[20] / MIO[20]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[20]"]
|
||||
set_property PACKAGE_PIN "M20" [get_ports "MIO[20]"]
|
||||
set_property slew "slow" [get_ports "MIO[20]"]
|
||||
set_property drive "8" [get_ports "MIO[20]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[20]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[20]"]
|
||||
# GPIO / gpio[19] / MIO[19]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[19]"]
|
||||
set_property PACKAGE_PIN "J20" [get_ports "MIO[19]"]
|
||||
set_property slew "slow" [get_ports "MIO[19]"]
|
||||
set_property drive "8" [get_ports "MIO[19]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[19]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[19]"]
|
||||
# GPIO / gpio[18] / MIO[18]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[18]"]
|
||||
set_property PACKAGE_PIN "K20" [get_ports "MIO[18]"]
|
||||
set_property slew "slow" [get_ports "MIO[18]"]
|
||||
set_property drive "8" [get_ports "MIO[18]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[18]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[18]"]
|
||||
# GPIO / gpio[17] / MIO[17]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[17]"]
|
||||
set_property PACKAGE_PIN "K21" [get_ports "MIO[17]"]
|
||||
set_property slew "slow" [get_ports "MIO[17]"]
|
||||
set_property drive "8" [get_ports "MIO[17]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[17]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[17]"]
|
||||
# GPIO / gpio[16] / MIO[16]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[16]"]
|
||||
set_property PACKAGE_PIN "L19" [get_ports "MIO[16]"]
|
||||
set_property slew "slow" [get_ports "MIO[16]"]
|
||||
set_property drive "8" [get_ports "MIO[16]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[16]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[16]"]
|
||||
# GPIO / gpio[15] / MIO[15]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[15]"]
|
||||
set_property PACKAGE_PIN "C22" [get_ports "MIO[15]"]
|
||||
set_property slew "slow" [get_ports "MIO[15]"]
|
||||
set_property drive "8" [get_ports "MIO[15]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[15]"]
|
||||
# GPIO / gpio[14] / MIO[14]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[14]"]
|
||||
set_property PACKAGE_PIN "B22" [get_ports "MIO[14]"]
|
||||
set_property slew "slow" [get_ports "MIO[14]"]
|
||||
set_property drive "8" [get_ports "MIO[14]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[14]"]
|
||||
# GPIO / gpio[13] / MIO[13]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[13]"]
|
||||
set_property PACKAGE_PIN "F22" [get_ports "MIO[13]"]
|
||||
set_property slew "slow" [get_ports "MIO[13]"]
|
||||
set_property drive "8" [get_ports "MIO[13]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[13]"]
|
||||
# GPIO / gpio[12] / MIO[12]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[12]"]
|
||||
set_property PACKAGE_PIN "E21" [get_ports "MIO[12]"]
|
||||
set_property slew "slow" [get_ports "MIO[12]"]
|
||||
set_property drive "8" [get_ports "MIO[12]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[12]"]
|
||||
# GPIO / gpio[11] / MIO[11]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[11]"]
|
||||
set_property PACKAGE_PIN "A23" [get_ports "MIO[11]"]
|
||||
set_property slew "slow" [get_ports "MIO[11]"]
|
||||
set_property drive "8" [get_ports "MIO[11]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[11]"]
|
||||
# GPIO / gpio[10] / MIO[10]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[10]"]
|
||||
set_property PACKAGE_PIN "E22" [get_ports "MIO[10]"]
|
||||
set_property slew "slow" [get_ports "MIO[10]"]
|
||||
set_property drive "8" [get_ports "MIO[10]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[10]"]
|
||||
# GPIO / gpio[9] / MIO[9]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[9]"]
|
||||
set_property PACKAGE_PIN "A24" [get_ports "MIO[9]"]
|
||||
set_property slew "slow" [get_ports "MIO[9]"]
|
||||
set_property drive "8" [get_ports "MIO[9]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[9]"]
|
||||
# GPIO / gpio[8] / MIO[8]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[8]"]
|
||||
set_property PACKAGE_PIN "C21" [get_ports "MIO[8]"]
|
||||
set_property slew "slow" [get_ports "MIO[8]"]
|
||||
set_property drive "8" [get_ports "MIO[8]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[8]"]
|
||||
# GPIO / gpio[7] / MIO[7]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[7]"]
|
||||
set_property PACKAGE_PIN "B24" [get_ports "MIO[7]"]
|
||||
set_property slew "slow" [get_ports "MIO[7]"]
|
||||
set_property drive "8" [get_ports "MIO[7]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[7]"]
|
||||
# Quad SPI Flash / qspi0_sclk / MIO[6]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[6]"]
|
||||
set_property PACKAGE_PIN "D24" [get_ports "MIO[6]"]
|
||||
set_property slew "slow" [get_ports "MIO[6]"]
|
||||
set_property drive "8" [get_ports "MIO[6]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[6]"]
|
||||
# Quad SPI Flash / qspi0_io[3]/HOLD_B / MIO[5]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[5]"]
|
||||
set_property PACKAGE_PIN "C24" [get_ports "MIO[5]"]
|
||||
set_property slew "slow" [get_ports "MIO[5]"]
|
||||
set_property drive "8" [get_ports "MIO[5]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[5]"]
|
||||
# Quad SPI Flash / qspi0_io[2] / MIO[4]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[4]"]
|
||||
set_property PACKAGE_PIN "E23" [get_ports "MIO[4]"]
|
||||
set_property slew "slow" [get_ports "MIO[4]"]
|
||||
set_property drive "8" [get_ports "MIO[4]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[4]"]
|
||||
# Quad SPI Flash / qspi0_io[1] / MIO[3]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[3]"]
|
||||
set_property PACKAGE_PIN "C23" [get_ports "MIO[3]"]
|
||||
set_property slew "slow" [get_ports "MIO[3]"]
|
||||
set_property drive "8" [get_ports "MIO[3]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[3]"]
|
||||
# Quad SPI Flash / qspi0_io[0] / MIO[2]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[2]"]
|
||||
set_property PACKAGE_PIN "F23" [get_ports "MIO[2]"]
|
||||
set_property slew "slow" [get_ports "MIO[2]"]
|
||||
set_property drive "8" [get_ports "MIO[2]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[2]"]
|
||||
# Quad SPI Flash / qspi0_ss_b / MIO[1]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[1]"]
|
||||
set_property PACKAGE_PIN "D23" [get_ports "MIO[1]"]
|
||||
set_property slew "slow" [get_ports "MIO[1]"]
|
||||
set_property drive "8" [get_ports "MIO[1]"]
|
||||
set_property pullup "TRUE" [get_ports "MIO[1]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "MIO[1]"]
|
||||
# GPIO / gpio[0] / MIO[0]
|
||||
set_property iostandard "LVCMOS18" [get_ports "MIO[0]"]
|
||||
set_property PACKAGE_PIN "F24" [get_ports "MIO[0]"]
|
||||
set_property slew "slow" [get_ports "MIO[0]"]
|
||||
set_property drive "8" [get_ports "MIO[0]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "MIO[0]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_VRP"]
|
||||
set_property PACKAGE_PIN "M21" [get_ports "DDR_VRP"]
|
||||
set_property slew "FAST" [get_ports "DDR_VRP"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_VRP"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_VRN"]
|
||||
set_property PACKAGE_PIN "N21" [get_ports "DDR_VRN"]
|
||||
set_property slew "FAST" [get_ports "DDR_VRN"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_VRN"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_WEB"]
|
||||
set_property PACKAGE_PIN "N23" [get_ports "DDR_WEB"]
|
||||
set_property slew "SLOW" [get_ports "DDR_WEB"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_WEB"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_RAS_n"]
|
||||
set_property PACKAGE_PIN "N24" [get_ports "DDR_RAS_n"]
|
||||
set_property slew "SLOW" [get_ports "DDR_RAS_n"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_RAS_n"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_ODT"]
|
||||
set_property PACKAGE_PIN "L23" [get_ports "DDR_ODT"]
|
||||
set_property slew "SLOW" [get_ports "DDR_ODT"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_ODT"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_DRSTB"]
|
||||
set_property PACKAGE_PIN "F25" [get_ports "DDR_DRSTB"]
|
||||
set_property slew "FAST" [get_ports "DDR_DRSTB"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DRSTB"]
|
||||
set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS[3]"]
|
||||
set_property PACKAGE_PIN "L28" [get_ports "DDR_DQS[3]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQS[3]"]
|
||||
set_property pullup "TRUE" [get_ports "DDR_DQS[3]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[3]"]
|
||||
set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS[2]"]
|
||||
set_property PACKAGE_PIN "G29" [get_ports "DDR_DQS[2]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQS[2]"]
|
||||
set_property pullup "TRUE" [get_ports "DDR_DQS[2]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[2]"]
|
||||
set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS[1]"]
|
||||
set_property PACKAGE_PIN "C29" [get_ports "DDR_DQS[1]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQS[1]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[1]"]
|
||||
set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS[0]"]
|
||||
set_property PACKAGE_PIN "C26" [get_ports "DDR_DQS[0]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQS[0]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS[0]"]
|
||||
set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS_n[3]"]
|
||||
set_property PACKAGE_PIN "L29" [get_ports "DDR_DQS_n[3]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQS_n[3]"]
|
||||
set_property pullup "TRUE" [get_ports "DDR_DQS_n[3]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[3]"]
|
||||
set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS_n[2]"]
|
||||
set_property PACKAGE_PIN "F29" [get_ports "DDR_DQS_n[2]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQS_n[2]"]
|
||||
set_property pullup "TRUE" [get_ports "DDR_DQS_n[2]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[2]"]
|
||||
set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS_n[1]"]
|
||||
set_property PACKAGE_PIN "B29" [get_ports "DDR_DQS_n[1]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQS_n[1]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[1]"]
|
||||
set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS_n[0]"]
|
||||
set_property PACKAGE_PIN "B26" [get_ports "DDR_DQS_n[0]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQS_n[0]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQS_n[0]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[9]"]
|
||||
set_property PACKAGE_PIN "A27" [get_ports "DDR_DQ[9]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[9]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[9]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[8]"]
|
||||
set_property PACKAGE_PIN "A29" [get_ports "DDR_DQ[8]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[8]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[8]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[7]"]
|
||||
set_property PACKAGE_PIN "E27" [get_ports "DDR_DQ[7]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[7]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[7]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[6]"]
|
||||
set_property PACKAGE_PIN "D26" [get_ports "DDR_DQ[6]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[6]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[6]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[5]"]
|
||||
set_property PACKAGE_PIN "E26" [get_ports "DDR_DQ[5]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[5]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[5]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[4]"]
|
||||
set_property PACKAGE_PIN "B25" [get_ports "DDR_DQ[4]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[4]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[4]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[3]"]
|
||||
set_property PACKAGE_PIN "D25" [get_ports "DDR_DQ[3]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[3]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[3]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[31]"]
|
||||
set_property PACKAGE_PIN "M30" [get_ports "DDR_DQ[31]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[31]"]
|
||||
set_property pullup "TRUE" [get_ports "DDR_DQ[31]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[31]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[30]"]
|
||||
set_property PACKAGE_PIN "L30" [get_ports "DDR_DQ[30]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[30]"]
|
||||
set_property pullup "TRUE" [get_ports "DDR_DQ[30]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[30]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[2]"]
|
||||
set_property PACKAGE_PIN "B27" [get_ports "DDR_DQ[2]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[2]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[2]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[29]"]
|
||||
set_property PACKAGE_PIN "M29" [get_ports "DDR_DQ[29]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[29]"]
|
||||
set_property pullup "TRUE" [get_ports "DDR_DQ[29]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[29]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[28]"]
|
||||
set_property PACKAGE_PIN "K30" [get_ports "DDR_DQ[28]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[28]"]
|
||||
set_property pullup "TRUE" [get_ports "DDR_DQ[28]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[28]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[27]"]
|
||||
set_property PACKAGE_PIN "J28" [get_ports "DDR_DQ[27]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[27]"]
|
||||
set_property pullup "TRUE" [get_ports "DDR_DQ[27]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[27]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[26]"]
|
||||
set_property PACKAGE_PIN "J30" [get_ports "DDR_DQ[26]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[26]"]
|
||||
set_property pullup "TRUE" [get_ports "DDR_DQ[26]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[26]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[25]"]
|
||||
set_property PACKAGE_PIN "K27" [get_ports "DDR_DQ[25]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[25]"]
|
||||
set_property pullup "TRUE" [get_ports "DDR_DQ[25]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[25]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[24]"]
|
||||
set_property PACKAGE_PIN "J29" [get_ports "DDR_DQ[24]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[24]"]
|
||||
set_property pullup "TRUE" [get_ports "DDR_DQ[24]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[24]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[23]"]
|
||||
set_property PACKAGE_PIN "F30" [get_ports "DDR_DQ[23]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[23]"]
|
||||
set_property pullup "TRUE" [get_ports "DDR_DQ[23]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[23]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[22]"]
|
||||
set_property PACKAGE_PIN "G30" [get_ports "DDR_DQ[22]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[22]"]
|
||||
set_property pullup "TRUE" [get_ports "DDR_DQ[22]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[22]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[21]"]
|
||||
set_property PACKAGE_PIN "F28" [get_ports "DDR_DQ[21]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[21]"]
|
||||
set_property pullup "TRUE" [get_ports "DDR_DQ[21]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[21]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[20]"]
|
||||
set_property PACKAGE_PIN "E30" [get_ports "DDR_DQ[20]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[20]"]
|
||||
set_property pullup "TRUE" [get_ports "DDR_DQ[20]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[20]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[1]"]
|
||||
set_property PACKAGE_PIN "E25" [get_ports "DDR_DQ[1]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[1]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[1]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[19]"]
|
||||
set_property PACKAGE_PIN "E28" [get_ports "DDR_DQ[19]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[19]"]
|
||||
set_property pullup "TRUE" [get_ports "DDR_DQ[19]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[19]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[18]"]
|
||||
set_property PACKAGE_PIN "H28" [get_ports "DDR_DQ[18]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[18]"]
|
||||
set_property pullup "TRUE" [get_ports "DDR_DQ[18]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[18]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[17]"]
|
||||
set_property PACKAGE_PIN "G27" [get_ports "DDR_DQ[17]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[17]"]
|
||||
set_property pullup "TRUE" [get_ports "DDR_DQ[17]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[17]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[16]"]
|
||||
set_property PACKAGE_PIN "H27" [get_ports "DDR_DQ[16]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[16]"]
|
||||
set_property pullup "TRUE" [get_ports "DDR_DQ[16]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[16]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[15]"]
|
||||
set_property PACKAGE_PIN "D29" [get_ports "DDR_DQ[15]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[15]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[15]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[14]"]
|
||||
set_property PACKAGE_PIN "D28" [get_ports "DDR_DQ[14]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[14]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[14]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[13]"]
|
||||
set_property PACKAGE_PIN "D30" [get_ports "DDR_DQ[13]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[13]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[13]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[12]"]
|
||||
set_property PACKAGE_PIN "C28" [get_ports "DDR_DQ[12]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[12]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[12]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[11]"]
|
||||
set_property PACKAGE_PIN "A28" [get_ports "DDR_DQ[11]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[11]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[11]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[10]"]
|
||||
set_property PACKAGE_PIN "A30" [get_ports "DDR_DQ[10]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[10]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[10]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[0]"]
|
||||
set_property PACKAGE_PIN "A25" [get_ports "DDR_DQ[0]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DQ[0]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DQ[0]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DM[3]"]
|
||||
set_property PACKAGE_PIN "K28" [get_ports "DDR_DM[3]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DM[3]"]
|
||||
set_property pullup "TRUE" [get_ports "DDR_DM[3]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[3]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DM[2]"]
|
||||
set_property PACKAGE_PIN "H29" [get_ports "DDR_DM[2]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DM[2]"]
|
||||
set_property pullup "TRUE" [get_ports "DDR_DM[2]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[2]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DM[1]"]
|
||||
set_property PACKAGE_PIN "B30" [get_ports "DDR_DM[1]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DM[1]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[1]"]
|
||||
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DM[0]"]
|
||||
set_property PACKAGE_PIN "C27" [get_ports "DDR_DM[0]"]
|
||||
set_property slew "FAST" [get_ports "DDR_DM[0]"]
|
||||
set_property PIO_DIRECTION "BIDIR" [get_ports "DDR_DM[0]"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_CS_n"]
|
||||
set_property PACKAGE_PIN "N22" [get_ports "DDR_CS_n"]
|
||||
set_property slew "SLOW" [get_ports "DDR_CS_n"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_CS_n"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_CKE"]
|
||||
set_property PACKAGE_PIN "M22" [get_ports "DDR_CKE"]
|
||||
set_property slew "SLOW" [get_ports "DDR_CKE"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_CKE"]
|
||||
set_property iostandard "DIFF_SSTL15" [get_ports "DDR_Clk"]
|
||||
set_property PACKAGE_PIN "K25" [get_ports "DDR_Clk"]
|
||||
set_property slew "FAST" [get_ports "DDR_Clk"]
|
||||
set_property PIO_DIRECTION "INPUT" [get_ports "DDR_Clk"]
|
||||
set_property iostandard "DIFF_SSTL15" [get_ports "DDR_Clk_n"]
|
||||
set_property PACKAGE_PIN "J25" [get_ports "DDR_Clk_n"]
|
||||
set_property slew "FAST" [get_ports "DDR_Clk_n"]
|
||||
set_property PIO_DIRECTION "INPUT" [get_ports "DDR_Clk_n"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_CAS_n"]
|
||||
set_property PACKAGE_PIN "M24" [get_ports "DDR_CAS_n"]
|
||||
set_property slew "SLOW" [get_ports "DDR_CAS_n"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_CAS_n"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_BankAddr[2]"]
|
||||
set_property PACKAGE_PIN "M25" [get_ports "DDR_BankAddr[2]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_BankAddr[2]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_BankAddr[2]"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_BankAddr[1]"]
|
||||
set_property PACKAGE_PIN "M26" [get_ports "DDR_BankAddr[1]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_BankAddr[1]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_BankAddr[1]"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_BankAddr[0]"]
|
||||
set_property PACKAGE_PIN "M27" [get_ports "DDR_BankAddr[0]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_BankAddr[0]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_BankAddr[0]"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_Addr[9]"]
|
||||
set_property PACKAGE_PIN "J23" [get_ports "DDR_Addr[9]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[9]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[9]"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_Addr[8]"]
|
||||
set_property PACKAGE_PIN "F27" [get_ports "DDR_Addr[8]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[8]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[8]"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_Addr[7]"]
|
||||
set_property PACKAGE_PIN "K22" [get_ports "DDR_Addr[7]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[7]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[7]"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_Addr[6]"]
|
||||
set_property PACKAGE_PIN "H26" [get_ports "DDR_Addr[6]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[6]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[6]"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_Addr[5]"]
|
||||
set_property PACKAGE_PIN "G24" [get_ports "DDR_Addr[5]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[5]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[5]"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_Addr[4]"]
|
||||
set_property PACKAGE_PIN "J26" [get_ports "DDR_Addr[4]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[4]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[4]"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_Addr[3]"]
|
||||
set_property PACKAGE_PIN "G25" [get_ports "DDR_Addr[3]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[3]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[3]"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_Addr[2]"]
|
||||
set_property PACKAGE_PIN "L27" [get_ports "DDR_Addr[2]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[2]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[2]"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_Addr[1]"]
|
||||
set_property PACKAGE_PIN "K26" [get_ports "DDR_Addr[1]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[1]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[1]"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_Addr[14]"]
|
||||
set_property PACKAGE_PIN "J24" [get_ports "DDR_Addr[14]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[14]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[14]"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_Addr[13]"]
|
||||
set_property PACKAGE_PIN "H23" [get_ports "DDR_Addr[13]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[13]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[13]"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_Addr[12]"]
|
||||
set_property PACKAGE_PIN "K23" [get_ports "DDR_Addr[12]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[12]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[12]"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_Addr[11]"]
|
||||
set_property PACKAGE_PIN "H24" [get_ports "DDR_Addr[11]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[11]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[11]"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_Addr[10]"]
|
||||
set_property PACKAGE_PIN "G26" [get_ports "DDR_Addr[10]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[10]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[10]"]
|
||||
set_property iostandard "SSTL15" [get_ports "DDR_Addr[0]"]
|
||||
set_property PACKAGE_PIN "L25" [get_ports "DDR_Addr[0]"]
|
||||
set_property slew "SLOW" [get_ports "DDR_Addr[0]"]
|
||||
set_property PIO_DIRECTION "OUTPUT" [get_ports "DDR_Addr[0]"]
|
||||
set_property iostandard "LVCMOS18" [get_ports "PS_PORB"]
|
||||
set_property PACKAGE_PIN "D21" [get_ports "PS_PORB"]
|
||||
set_property slew "fast" [get_ports "PS_PORB"]
|
||||
set_property iostandard "LVCMOS18" [get_ports "PS_SRSTB"]
|
||||
set_property PACKAGE_PIN "B19" [get_ports "PS_SRSTB"]
|
||||
set_property slew "fast" [get_ports "PS_SRSTB"]
|
||||
set_property iostandard "LVCMOS18" [get_ports "PS_CLK"]
|
||||
set_property PACKAGE_PIN "A22" [get_ports "PS_CLK"]
|
||||
set_property slew "fast" [get_ports "PS_CLK"]
|
||||
|
||||
+39260
File diff suppressed because it is too large
Load Diff
BIN
Binary file not shown.
BIN
Binary file not shown.
+97
@@ -0,0 +1,97 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Thu Mar 30 16:05:24 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ipi-bds/system_bd/ip/system_bd_ps_system_0/system_bd_ps_system_0_stub.v
|
||||
// Design : system_bd_ps_system_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z100ffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2019.1.3" *)
|
||||
module system_bd_ps_system_0(GPIO_I, GPIO_O, GPIO_T, M_AXI_GP0_ARVALID,
|
||||
M_AXI_GP0_AWVALID, M_AXI_GP0_BREADY, M_AXI_GP0_RREADY, M_AXI_GP0_WLAST, M_AXI_GP0_WVALID,
|
||||
M_AXI_GP0_ARID, M_AXI_GP0_AWID, M_AXI_GP0_WID, M_AXI_GP0_ARBURST, M_AXI_GP0_ARLOCK,
|
||||
M_AXI_GP0_ARSIZE, M_AXI_GP0_AWBURST, M_AXI_GP0_AWLOCK, M_AXI_GP0_AWSIZE,
|
||||
M_AXI_GP0_ARPROT, M_AXI_GP0_AWPROT, M_AXI_GP0_ARADDR, M_AXI_GP0_AWADDR, M_AXI_GP0_WDATA,
|
||||
M_AXI_GP0_ARCACHE, M_AXI_GP0_ARLEN, M_AXI_GP0_ARQOS, M_AXI_GP0_AWCACHE, M_AXI_GP0_AWLEN,
|
||||
M_AXI_GP0_AWQOS, M_AXI_GP0_WSTRB, M_AXI_GP0_ACLK, M_AXI_GP0_ARREADY, M_AXI_GP0_AWREADY,
|
||||
M_AXI_GP0_BVALID, M_AXI_GP0_RLAST, M_AXI_GP0_RVALID, M_AXI_GP0_WREADY, M_AXI_GP0_BID,
|
||||
M_AXI_GP0_RID, M_AXI_GP0_BRESP, M_AXI_GP0_RRESP, M_AXI_GP0_RDATA, IRQ_F2P, FCLK_CLK0,
|
||||
FCLK_CLK1, FCLK_RESET0_N, MIO, DDR_CAS_n, DDR_CKE, DDR_Clk_n, DDR_Clk, DDR_CS_n, DDR_DRSTB,
|
||||
DDR_ODT, DDR_RAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr, DDR_VRN, DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n,
|
||||
DDR_DQS, PS_SRSTB, PS_CLK, PS_PORB)
|
||||
/* synthesis syn_black_box black_box_pad_pin="GPIO_I[47:0],GPIO_O[47:0],GPIO_T[47:0],M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],IRQ_F2P[0:0],FCLK_CLK0,FCLK_CLK1,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB" */;
|
||||
input [47:0]GPIO_I;
|
||||
output [47:0]GPIO_O;
|
||||
output [47:0]GPIO_T;
|
||||
output M_AXI_GP0_ARVALID;
|
||||
output M_AXI_GP0_AWVALID;
|
||||
output M_AXI_GP0_BREADY;
|
||||
output M_AXI_GP0_RREADY;
|
||||
output M_AXI_GP0_WLAST;
|
||||
output M_AXI_GP0_WVALID;
|
||||
output [11:0]M_AXI_GP0_ARID;
|
||||
output [11:0]M_AXI_GP0_AWID;
|
||||
output [11:0]M_AXI_GP0_WID;
|
||||
output [1:0]M_AXI_GP0_ARBURST;
|
||||
output [1:0]M_AXI_GP0_ARLOCK;
|
||||
output [2:0]M_AXI_GP0_ARSIZE;
|
||||
output [1:0]M_AXI_GP0_AWBURST;
|
||||
output [1:0]M_AXI_GP0_AWLOCK;
|
||||
output [2:0]M_AXI_GP0_AWSIZE;
|
||||
output [2:0]M_AXI_GP0_ARPROT;
|
||||
output [2:0]M_AXI_GP0_AWPROT;
|
||||
output [31:0]M_AXI_GP0_ARADDR;
|
||||
output [31:0]M_AXI_GP0_AWADDR;
|
||||
output [31:0]M_AXI_GP0_WDATA;
|
||||
output [3:0]M_AXI_GP0_ARCACHE;
|
||||
output [3:0]M_AXI_GP0_ARLEN;
|
||||
output [3:0]M_AXI_GP0_ARQOS;
|
||||
output [3:0]M_AXI_GP0_AWCACHE;
|
||||
output [3:0]M_AXI_GP0_AWLEN;
|
||||
output [3:0]M_AXI_GP0_AWQOS;
|
||||
output [3:0]M_AXI_GP0_WSTRB;
|
||||
input M_AXI_GP0_ACLK;
|
||||
input M_AXI_GP0_ARREADY;
|
||||
input M_AXI_GP0_AWREADY;
|
||||
input M_AXI_GP0_BVALID;
|
||||
input M_AXI_GP0_RLAST;
|
||||
input M_AXI_GP0_RVALID;
|
||||
input M_AXI_GP0_WREADY;
|
||||
input [11:0]M_AXI_GP0_BID;
|
||||
input [11:0]M_AXI_GP0_RID;
|
||||
input [1:0]M_AXI_GP0_BRESP;
|
||||
input [1:0]M_AXI_GP0_RRESP;
|
||||
input [31:0]M_AXI_GP0_RDATA;
|
||||
input [0:0]IRQ_F2P;
|
||||
output FCLK_CLK0;
|
||||
output FCLK_CLK1;
|
||||
output FCLK_RESET0_N;
|
||||
inout [53:0]MIO;
|
||||
inout DDR_CAS_n;
|
||||
inout DDR_CKE;
|
||||
inout DDR_Clk_n;
|
||||
inout DDR_Clk;
|
||||
inout DDR_CS_n;
|
||||
inout DDR_DRSTB;
|
||||
inout DDR_ODT;
|
||||
inout DDR_RAS_n;
|
||||
inout DDR_WEB;
|
||||
inout [2:0]DDR_BankAddr;
|
||||
inout [14:0]DDR_Addr;
|
||||
inout DDR_VRN;
|
||||
inout DDR_VRP;
|
||||
inout [3:0]DDR_DM;
|
||||
inout [31:0]DDR_DQ;
|
||||
inout [3:0]DDR_DQS_n;
|
||||
inout [3:0]DDR_DQS;
|
||||
inout PS_SRSTB;
|
||||
inout PS_CLK;
|
||||
inout PS_PORB;
|
||||
endmodule
|
||||
+96
@@ -0,0 +1,96 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Thu Mar 30 16:05:24 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ipi-bds/system_bd/ip/system_bd_ps_system_0/system_bd_ps_system_0_stub.vhdl
|
||||
-- Design : system_bd_ps_system_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z100ffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity system_bd_ps_system_0 is
|
||||
Port (
|
||||
GPIO_I : in STD_LOGIC_VECTOR ( 47 downto 0 );
|
||||
GPIO_O : out STD_LOGIC_VECTOR ( 47 downto 0 );
|
||||
GPIO_T : out STD_LOGIC_VECTOR ( 47 downto 0 );
|
||||
M_AXI_GP0_ARVALID : out STD_LOGIC;
|
||||
M_AXI_GP0_AWVALID : out STD_LOGIC;
|
||||
M_AXI_GP0_BREADY : out STD_LOGIC;
|
||||
M_AXI_GP0_RREADY : out STD_LOGIC;
|
||||
M_AXI_GP0_WLAST : out STD_LOGIC;
|
||||
M_AXI_GP0_WVALID : out STD_LOGIC;
|
||||
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
M_AXI_GP0_ACLK : in STD_LOGIC;
|
||||
M_AXI_GP0_ARREADY : in STD_LOGIC;
|
||||
M_AXI_GP0_AWREADY : in STD_LOGIC;
|
||||
M_AXI_GP0_BVALID : in STD_LOGIC;
|
||||
M_AXI_GP0_RLAST : in STD_LOGIC;
|
||||
M_AXI_GP0_RVALID : in STD_LOGIC;
|
||||
M_AXI_GP0_WREADY : in STD_LOGIC;
|
||||
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
IRQ_F2P : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
FCLK_CLK0 : out STD_LOGIC;
|
||||
FCLK_CLK1 : out STD_LOGIC;
|
||||
FCLK_RESET0_N : out STD_LOGIC;
|
||||
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
|
||||
DDR_CAS_n : inout STD_LOGIC;
|
||||
DDR_CKE : inout STD_LOGIC;
|
||||
DDR_Clk_n : inout STD_LOGIC;
|
||||
DDR_Clk : inout STD_LOGIC;
|
||||
DDR_CS_n : inout STD_LOGIC;
|
||||
DDR_DRSTB : inout STD_LOGIC;
|
||||
DDR_ODT : inout STD_LOGIC;
|
||||
DDR_RAS_n : inout STD_LOGIC;
|
||||
DDR_WEB : inout STD_LOGIC;
|
||||
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
|
||||
DDR_VRN : inout STD_LOGIC;
|
||||
DDR_VRP : inout STD_LOGIC;
|
||||
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
PS_SRSTB : inout STD_LOGIC;
|
||||
PS_CLK : inout STD_LOGIC;
|
||||
PS_PORB : inout STD_LOGIC
|
||||
);
|
||||
|
||||
end system_bd_ps_system_0;
|
||||
|
||||
architecture stub of system_bd_ps_system_0 is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "GPIO_I[47:0],GPIO_O[47:0],GPIO_T[47:0],M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],IRQ_F2P[0:0],FCLK_CLK0,FCLK_CLK1,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "processing_system7_v5_5_processing_system7,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
+147
@@ -0,0 +1,147 @@
|
||||
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
|
||||
-- IP Revision: 13
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY proc_sys_reset_v5_0_13;
|
||||
USE proc_sys_reset_v5_0_13.proc_sys_reset;
|
||||
|
||||
ENTITY system_bd_rst_ps_system_50M_0 IS
|
||||
PORT (
|
||||
slowest_sync_clk : IN STD_LOGIC;
|
||||
ext_reset_in : IN STD_LOGIC;
|
||||
aux_reset_in : IN STD_LOGIC;
|
||||
mb_debug_sys_rst : IN STD_LOGIC;
|
||||
dcm_locked : IN STD_LOGIC;
|
||||
mb_reset : OUT STD_LOGIC;
|
||||
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
|
||||
);
|
||||
END system_bd_rst_ps_system_50M_0;
|
||||
|
||||
ARCHITECTURE system_bd_rst_ps_system_50M_0_arch OF system_bd_rst_ps_system_50M_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_bd_rst_ps_system_50M_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT proc_sys_reset IS
|
||||
GENERIC (
|
||||
C_FAMILY : STRING;
|
||||
C_EXT_RST_WIDTH : INTEGER;
|
||||
C_AUX_RST_WIDTH : INTEGER;
|
||||
C_EXT_RESET_HIGH : STD_LOGIC;
|
||||
C_AUX_RESET_HIGH : STD_LOGIC;
|
||||
C_NUM_BUS_RST : INTEGER;
|
||||
C_NUM_PERP_RST : INTEGER;
|
||||
C_NUM_INTERCONNECT_ARESETN : INTEGER;
|
||||
C_NUM_PERP_ARESETN : INTEGER
|
||||
);
|
||||
PORT (
|
||||
slowest_sync_clk : IN STD_LOGIC;
|
||||
ext_reset_in : IN STD_LOGIC;
|
||||
aux_reset_in : IN STD_LOGIC;
|
||||
mb_debug_sys_rst : IN STD_LOGIC;
|
||||
dcm_locked : IN STD_LOGIC;
|
||||
mb_reset : OUT STD_LOGIC;
|
||||
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT proc_sys_reset;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_aresetn: SIGNAL IS "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF interconnect_aresetn: SIGNAL IS "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_reset: SIGNAL IS "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF bus_struct_reset: SIGNAL IS "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF mb_reset: SIGNAL IS "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF mb_debug_sys_rst: SIGNAL IS "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF aux_reset_in: SIGNAL IS "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF ext_reset_in: SIGNAL IS "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF slowest_sync_clk: SIGNAL IS "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN system_bd_ps_system_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
|
||||
BEGIN
|
||||
U0 : proc_sys_reset
|
||||
GENERIC MAP (
|
||||
C_FAMILY => "zynq",
|
||||
C_EXT_RST_WIDTH => 4,
|
||||
C_AUX_RST_WIDTH => 4,
|
||||
C_EXT_RESET_HIGH => '0',
|
||||
C_AUX_RESET_HIGH => '0',
|
||||
C_NUM_BUS_RST => 1,
|
||||
C_NUM_PERP_RST => 1,
|
||||
C_NUM_INTERCONNECT_ARESETN => 1,
|
||||
C_NUM_PERP_ARESETN => 1
|
||||
)
|
||||
PORT MAP (
|
||||
slowest_sync_clk => slowest_sync_clk,
|
||||
ext_reset_in => ext_reset_in,
|
||||
aux_reset_in => aux_reset_in,
|
||||
mb_debug_sys_rst => mb_debug_sys_rst,
|
||||
dcm_locked => dcm_locked,
|
||||
mb_reset => mb_reset,
|
||||
bus_struct_reset => bus_struct_reset,
|
||||
peripheral_reset => peripheral_reset,
|
||||
interconnect_aresetn => interconnect_aresetn,
|
||||
peripheral_aresetn => peripheral_aresetn
|
||||
);
|
||||
END system_bd_rst_ps_system_50M_0_arch;
|
||||
+153
@@ -0,0 +1,153 @@
|
||||
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
|
||||
-- IP Revision: 13
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY proc_sys_reset_v5_0_13;
|
||||
USE proc_sys_reset_v5_0_13.proc_sys_reset;
|
||||
|
||||
ENTITY system_bd_rst_ps_system_50M_0 IS
|
||||
PORT (
|
||||
slowest_sync_clk : IN STD_LOGIC;
|
||||
ext_reset_in : IN STD_LOGIC;
|
||||
aux_reset_in : IN STD_LOGIC;
|
||||
mb_debug_sys_rst : IN STD_LOGIC;
|
||||
dcm_locked : IN STD_LOGIC;
|
||||
mb_reset : OUT STD_LOGIC;
|
||||
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
|
||||
);
|
||||
END system_bd_rst_ps_system_50M_0;
|
||||
|
||||
ARCHITECTURE system_bd_rst_ps_system_50M_0_arch OF system_bd_rst_ps_system_50M_0 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_bd_rst_ps_system_50M_0_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT proc_sys_reset IS
|
||||
GENERIC (
|
||||
C_FAMILY : STRING;
|
||||
C_EXT_RST_WIDTH : INTEGER;
|
||||
C_AUX_RST_WIDTH : INTEGER;
|
||||
C_EXT_RESET_HIGH : STD_LOGIC;
|
||||
C_AUX_RESET_HIGH : STD_LOGIC;
|
||||
C_NUM_BUS_RST : INTEGER;
|
||||
C_NUM_PERP_RST : INTEGER;
|
||||
C_NUM_INTERCONNECT_ARESETN : INTEGER;
|
||||
C_NUM_PERP_ARESETN : INTEGER
|
||||
);
|
||||
PORT (
|
||||
slowest_sync_clk : IN STD_LOGIC;
|
||||
ext_reset_in : IN STD_LOGIC;
|
||||
aux_reset_in : IN STD_LOGIC;
|
||||
mb_debug_sys_rst : IN STD_LOGIC;
|
||||
dcm_locked : IN STD_LOGIC;
|
||||
mb_reset : OUT STD_LOGIC;
|
||||
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT proc_sys_reset;
|
||||
ATTRIBUTE X_CORE_INFO : STRING;
|
||||
ATTRIBUTE X_CORE_INFO OF system_bd_rst_ps_system_50M_0_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2019.1.3";
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE OF system_bd_rst_ps_system_50M_0_arch : ARCHITECTURE IS "system_bd_rst_ps_system_50M_0,proc_sys_reset,{}";
|
||||
ATTRIBUTE CORE_GENERATION_INFO : STRING;
|
||||
ATTRIBUTE CORE_GENERATION_INFO OF system_bd_rst_ps_system_50M_0_arch: ARCHITECTURE IS "system_bd_rst_ps_system_50M_0,proc_sys_reset,{x_ipProduct=Vivado 2019.1.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=13,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=0,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_aresetn: SIGNAL IS "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF interconnect_aresetn: SIGNAL IS "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_reset: SIGNAL IS "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF bus_struct_reset: SIGNAL IS "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF mb_reset: SIGNAL IS "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF mb_debug_sys_rst: SIGNAL IS "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF aux_reset_in: SIGNAL IS "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF ext_reset_in: SIGNAL IS "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF slowest_sync_clk: SIGNAL IS "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN system_bd_ps_system_0_FCLK_CLK0, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
|
||||
BEGIN
|
||||
U0 : proc_sys_reset
|
||||
GENERIC MAP (
|
||||
C_FAMILY => "zynq",
|
||||
C_EXT_RST_WIDTH => 4,
|
||||
C_AUX_RST_WIDTH => 4,
|
||||
C_EXT_RESET_HIGH => '0',
|
||||
C_AUX_RESET_HIGH => '0',
|
||||
C_NUM_BUS_RST => 1,
|
||||
C_NUM_PERP_RST => 1,
|
||||
C_NUM_INTERCONNECT_ARESETN => 1,
|
||||
C_NUM_PERP_ARESETN => 1
|
||||
)
|
||||
PORT MAP (
|
||||
slowest_sync_clk => slowest_sync_clk,
|
||||
ext_reset_in => ext_reset_in,
|
||||
aux_reset_in => aux_reset_in,
|
||||
mb_debug_sys_rst => mb_debug_sys_rst,
|
||||
dcm_locked => dcm_locked,
|
||||
mb_reset => mb_reset,
|
||||
bus_struct_reset => bus_struct_reset,
|
||||
peripheral_reset => peripheral_reset,
|
||||
interconnect_aresetn => interconnect_aresetn,
|
||||
peripheral_aresetn => peripheral_aresetn
|
||||
);
|
||||
END system_bd_rst_ps_system_50M_0_arch;
|
||||
BIN
Binary file not shown.
+82
@@ -0,0 +1,82 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>xci</spirit:library>
|
||||
<spirit:name>unknown</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>system_bd_rst_ps_system_50M_0</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="proc_sys_reset" spirit:version="5.0"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AUX_RESET.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AUX_RESET.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BUS_STRUCT_RESET.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK.CLK_DOMAIN">system_bd_ps_system_0_FCLK_CLK0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK.FREQ_HZ">50000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.DBG_RESET.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EXT_RESET.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.EXT_RESET.POLARITY">ACTIVE_LOW</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INTERCONNECT_LOW_RST.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MB_RST.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.PERIPHERAL_HIGH_RST.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.PERIPHERAL_LOW_RST.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AUX_RESET_HIGH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AUX_RST_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EXT_RESET_HIGH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EXT_RST_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">zynq</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_BUS_RST">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_INTERCONNECT_ARESETN">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_PERP_ARESETN">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_PERP_RST">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_AUX_RESET_HIGH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_AUX_RST_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_EXT_RESET_HIGH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_EXT_RST_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_BUS_RST">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_INTERCONNECT_ARESETN">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_PERP_ARESETN">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_PERP_RST">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">system_bd_rst_ps_system_50M_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z100</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">13</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1.3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:componentInstanceExtensions>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AUX_RESET.POLARITY" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_AUX_RESET_HIGH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_EXT_RESET_HIGH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:componentInstanceExtensions>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
+49
@@ -0,0 +1,49 @@
|
||||
|
||||
# file: system_bd_rst_ps_system_50M_0.xdc
|
||||
# (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
|
||||
set_false_path -to [get_pins -hier *cdc_to*/D]
|
||||
+942
@@ -0,0 +1,942 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
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||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>customized_ip</spirit:library>
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||||
<spirit:name>system_bd_rst_ps_system_50M_0</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
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||||
<spirit:name>clock</spirit:name>
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||||
<spirit:displayName>Clock</spirit:displayName>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
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||||
<spirit:slave/>
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<spirit:portMaps>
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||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>slowest_sync_clk</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_RESET">mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset</spirit:value>
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||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
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||||
<spirit:displayName>Slowest Sync clock frequency</spirit:displayName>
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||||
<spirit:description>Slowest Synchronous clock frequency</spirit:description>
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<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLOCK.FREQ_HZ">50000000</spirit:value>
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||||
</spirit:parameter>
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||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
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<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK.PHASE">0.000</spirit:value>
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<spirit:vendorExtensions>
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<spirit:parameter>
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<spirit:name>CLK_DOMAIN</spirit:name>
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<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK.CLK_DOMAIN">system_bd_ps_system_0_FCLK_CLK0</spirit:value>
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<spirit:vendorExtensions>
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<xilinx:parameterUsage>none</xilinx:parameterUsage>
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<spirit:parameter>
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<spirit:name>ASSOCIATED_BUSIF</spirit:name>
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<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CLOCK.ASSOCIATED_BUSIF"/>
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<spirit:parameter>
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<spirit:name>INSERT_VIP</spirit:name>
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||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CLOCK.INSERT_VIP">0</spirit:value>
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||||
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<spirit:busInterface>
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<spirit:name>ext_reset</spirit:name>
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||||
<spirit:displayName>Ext_Reset</spirit:displayName>
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||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
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||||
<spirit:slave/>
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||||
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||||
<spirit:portMap>
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||||
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||||
<spirit:name>RST</spirit:name>
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||||
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||||
<spirit:physicalPort>
|
||||
<spirit:name>ext_reset_in</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
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||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>BOARD.ASSOCIATED_PARAM</spirit:name>
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||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.EXT_RESET.BOARD.ASSOCIATED_PARAM">RESET_BOARD_INTERFACE</spirit:value>
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<spirit:vendorExtensions>
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<spirit:parameter>
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||||
<spirit:name>POLARITY</spirit:name>
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||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.EXT_RESET.POLARITY">ACTIVE_LOW</spirit:value>
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||||
<spirit:vendorExtensions>
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||||
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||||
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||||
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||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.EXT_RESET.INSERT_VIP">0</spirit:value>
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<spirit:vendorExtensions>
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||||
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||||
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||||
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||||
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||||
<spirit:busInterface>
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||||
<spirit:name>aux_reset</spirit:name>
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||||
<spirit:displayName>aux_reset</spirit:displayName>
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||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
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||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
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||||
<spirit:slave/>
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||||
<spirit:portMaps>
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||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>aux_reset_in</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.AUX_RESET.POLARITY">ACTIVE_LOW</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
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||||
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|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.AUX_RESET.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>dbg_reset</spirit:name>
|
||||
<spirit:displayName>DBG_Reset</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>mb_debug_sys_rst</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.DBG_RESET.POLARITY">ACTIVE_HIGH</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.DBG_RESET.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>mb_rst</spirit:name>
|
||||
<spirit:displayName>MB_rst</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>mb_reset</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.MB_RST.POLARITY">ACTIVE_HIGH</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TYPE</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.MB_RST.TYPE">PROCESSOR</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.MB_RST.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>bus_struct_reset</spirit:name>
|
||||
<spirit:displayName>bus_struct_reset</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
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<spirit:left spirit:format="long">0</spirit:left>
|
||||
<spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_NUM_PERP_RST')) - 1)">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>interconnect_aresetn</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">0</spirit:left>
|
||||
<spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_NUM_INTERCONNECT_ARESETN')) - 1)">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>peripheral_aresetn</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">0</spirit:left>
|
||||
<spirit:right spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_NUM_PERP_ARESETN')) - 1)">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_vhdlbehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
<spirit:modelParameters>
|
||||
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="string">
|
||||
<spirit:name>C_FAMILY</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FAMILY">zynq</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>C_EXT_RST_WIDTH</spirit:name>
|
||||
<spirit:displayName>Ext Rst Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EXT_RST_WIDTH" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>C_AUX_RST_WIDTH</spirit:name>
|
||||
<spirit:displayName>Aux Rst Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AUX_RST_WIDTH" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">4</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="std_logic">
|
||||
<spirit:name>C_EXT_RESET_HIGH</spirit:name>
|
||||
<spirit:displayName>Ext Reset High</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_EXT_RESET_HIGH">0</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="std_logic">
|
||||
<spirit:name>C_AUX_RESET_HIGH</spirit:name>
|
||||
<spirit:displayName>Aux Reset High</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_AUX_RESET_HIGH" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">0</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>C_NUM_BUS_RST</spirit:name>
|
||||
<spirit:displayName>No. of Bus Reset (Active High)</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_BUS_RST" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">1</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>C_NUM_PERP_RST</spirit:name>
|
||||
<spirit:displayName>No. of Peripheral Reset (Active High)</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_PERP_RST" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">1</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>C_NUM_INTERCONNECT_ARESETN</spirit:name>
|
||||
<spirit:displayName>No. of Interconnect Reset (Active Low)</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_INTERCONNECT_ARESETN" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">1</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>C_NUM_PERP_ARESETN</spirit:name>
|
||||
<spirit:displayName>No. of Peripheral Reset (Active Low)</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_PERP_ARESETN" spirit:minimum="1" spirit:maximum="31" spirit:rangeType="long">1</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
</spirit:modelParameters>
|
||||
</spirit:model>
|
||||
<spirit:choices>
|
||||
<spirit:choice>
|
||||
<spirit:name>choice_list_ac75ef1e</spirit:name>
|
||||
<spirit:enumeration>Custom</spirit:enumeration>
|
||||
</spirit:choice>
|
||||
</spirit:choices>
|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlsynthesis_xilinx_com_ip_lib_cdc_1_0__ref_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:logicalName>lib_cdc_v1_0_2</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:subCoreRef>
|
||||
<xilinx:componentRef xilinx:vendor="xilinx.com" xilinx:library="ip" xilinx:name="lib_cdc" xilinx:version="1.0" xilinx:isGenerated="true" xilinx:checksum="726cb4eb">
|
||||
<xilinx:mode xilinx:name="copy_mode"/>
|
||||
</xilinx:componentRef>
|
||||
</xilinx:subCoreRef>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlsynthesis_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:logicalName>proc_sys_reset_v5_0_13</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>system_bd_rst_ps_system_50M_0.xdc</spirit:name>
|
||||
<spirit:userFileType>xdc</spirit:userFileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_synthesisconstraints_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>system_bd_rst_ps_system_50M_0_ooc.xdc</spirit:name>
|
||||
<spirit:userFileType>xdc</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_out_of_context</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlsynthesiswrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>synth/system_bd_rst_ps_system_50M_0.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlbehavioralsimulation_xilinx_com_ip_lib_cdc_1_0__ref_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/ef1e/hdl/lib_cdc_v1_0_rfs.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
|
||||
<spirit:logicalName>lib_cdc_v1_0_2</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:subCoreRef>
|
||||
<xilinx:componentRef xilinx:vendor="xilinx.com" xilinx:library="ip" xilinx:name="lib_cdc" xilinx:version="1.0" xilinx:isGenerated="true" xilinx:checksum="726cb4eb">
|
||||
<xilinx:mode xilinx:name="copy_mode"/>
|
||||
</xilinx:componentRef>
|
||||
</xilinx:subCoreRef>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlbehavioralsimulation_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/8842/hdl/proc_sys_reset_v5_0_vh_rfs.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
|
||||
<spirit:logicalName>proc_sys_reset_v5_0_13</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_vhdlsimulationwrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>sim/system_bd_rst_ps_system_50M_0.vhd</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_implementation_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>system_bd_rst_ps_system_50M_0_board.xdc</spirit:name>
|
||||
<spirit:userFileType>xdc</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_board</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>system_bd_rst_ps_system_50M_0.dcp</spirit:name>
|
||||
<spirit:userFileType>dcp</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>system_bd_rst_ps_system_50M_0_stub.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>system_bd_rst_ps_system_50M_0_stub.vhdl</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>system_bd_rst_ps_system_50M_0_sim_netlist.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>system_bd_rst_ps_system_50M_0_sim_netlist.vhdl</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>Processor Reset System</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_NUM_PERP_ARESETN</spirit:name>
|
||||
<spirit:displayName>No. of Peripheral Reset (Active Low)</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_PERP_ARESETN" spirit:order="1800" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">1</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_NUM_INTERCONNECT_ARESETN</spirit:name>
|
||||
<spirit:displayName>No. of Interconnect Reset (Active Low)</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_INTERCONNECT_ARESETN" spirit:order="1700" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_NUM_PERP_RST</spirit:name>
|
||||
<spirit:displayName>No. of Peripheral Reset (Active High)</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_PERP_RST" spirit:order="1600" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">1</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_NUM_BUS_RST</spirit:name>
|
||||
<spirit:displayName>No. of Bus Reset (Active High)</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_NUM_BUS_RST" spirit:order="1500" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_AUX_RESET_HIGH</spirit:name>
|
||||
<spirit:displayName>Aux Reset High</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_AUX_RESET_HIGH" spirit:order="1400" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_EXT_RESET_HIGH</spirit:name>
|
||||
<spirit:displayName>Ext Reset High</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_EXT_RESET_HIGH" spirit:order="1300" spirit:minimum="0" spirit:maximum="1" spirit:rangeType="long">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_AUX_RST_WIDTH</spirit:name>
|
||||
<spirit:displayName>Aux Rst Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_AUX_RST_WIDTH" spirit:order="1200" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>C_EXT_RST_WIDTH</spirit:name>
|
||||
<spirit:displayName>Ext Rst Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_EXT_RST_WIDTH" spirit:order="1100" spirit:minimum="1" spirit:maximum="16" spirit:rangeType="long">4</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">system_bd_rst_ps_system_50M_0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>USE_BOARD_FLOW</spirit:name>
|
||||
<spirit:displayName>Generate Board based IO Constraints</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_BOARD_FLOW" spirit:order="2">false</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>RESET_BOARD_INTERFACE</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RESET_BOARD_INTERFACE" spirit:choiceRef="choice_list_ac75ef1e" spirit:order="3">Custom</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:coreExtensions>
|
||||
<xilinx:displayName>Processor System Reset</xilinx:displayName>
|
||||
<xilinx:coreRevision>13</xilinx:coreRevision>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AUX_RESET.POLARITY" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.CLOCK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_AUX_RESET_HIGH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_EXT_RESET_HIGH" xilinx:valueSource="propagated" xilinx:valuePermission="bd"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2019.1.3</xilinx:xilinxVersion>
|
||||
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="26169568"/>
|
||||
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="af82d8e6"/>
|
||||
<xilinx:checksum xilinx:scope="ports" xilinx:value="f2ac9635"/>
|
||||
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="404de108"/>
|
||||
<xilinx:checksum xilinx:scope="parameters" xilinx:value="8319b917"/>
|
||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
+2
@@ -0,0 +1,2 @@
|
||||
#--------------------Physical Constraints-----------------
|
||||
|
||||
+57
@@ -0,0 +1,57 @@
|
||||
# (c) Copyright 2012-2023 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
# DO NOT MODIFY THIS FILE.
|
||||
# #########################################################
|
||||
#
|
||||
# This XDC is used only in OOC mode for synthesis, implementation
|
||||
#
|
||||
# #########################################################
|
||||
|
||||
|
||||
create_clock -period 20 -name slowest_sync_clk [get_ports slowest_sync_clk]
|
||||
|
||||
|
||||
BIN
Binary file not shown.
BIN
Binary file not shown.
+31
@@ -0,0 +1,31 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Thu Mar 30 16:05:22 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ipi-bds/system_bd/ip/system_bd_rst_ps_system_50M_0/system_bd_rst_ps_system_50M_0_stub.v
|
||||
// Design : system_bd_rst_ps_system_50M_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z100ffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "proc_sys_reset,Vivado 2019.1.3" *)
|
||||
module system_bd_rst_ps_system_50M_0(slowest_sync_clk, ext_reset_in, aux_reset_in,
|
||||
mb_debug_sys_rst, dcm_locked, mb_reset, bus_struct_reset, peripheral_reset,
|
||||
interconnect_aresetn, peripheral_aresetn)
|
||||
/* synthesis syn_black_box black_box_pad_pin="slowest_sync_clk,ext_reset_in,aux_reset_in,mb_debug_sys_rst,dcm_locked,mb_reset,bus_struct_reset[0:0],peripheral_reset[0:0],interconnect_aresetn[0:0],peripheral_aresetn[0:0]" */;
|
||||
input slowest_sync_clk;
|
||||
input ext_reset_in;
|
||||
input aux_reset_in;
|
||||
input mb_debug_sys_rst;
|
||||
input dcm_locked;
|
||||
output mb_reset;
|
||||
output [0:0]bus_struct_reset;
|
||||
output [0:0]peripheral_reset;
|
||||
output [0:0]interconnect_aresetn;
|
||||
output [0:0]peripheral_aresetn;
|
||||
endmodule
|
||||
+39
@@ -0,0 +1,39 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Thu Mar 30 16:05:22 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ipi-bds/system_bd/ip/system_bd_rst_ps_system_50M_0/system_bd_rst_ps_system_50M_0_stub.vhdl
|
||||
-- Design : system_bd_rst_ps_system_50M_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z100ffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity system_bd_rst_ps_system_50M_0 is
|
||||
Port (
|
||||
slowest_sync_clk : in STD_LOGIC;
|
||||
ext_reset_in : in STD_LOGIC;
|
||||
aux_reset_in : in STD_LOGIC;
|
||||
mb_debug_sys_rst : in STD_LOGIC;
|
||||
dcm_locked : in STD_LOGIC;
|
||||
mb_reset : out STD_LOGIC;
|
||||
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
|
||||
);
|
||||
|
||||
end system_bd_rst_ps_system_50M_0;
|
||||
|
||||
architecture stub of system_bd_rst_ps_system_50M_0 is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "slowest_sync_clk,ext_reset_in,aux_reset_in,mb_debug_sys_rst,dcm_locked,mb_reset,bus_struct_reset[0:0],peripheral_reset[0:0],interconnect_aresetn[0:0],peripheral_aresetn[0:0]";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "proc_sys_reset,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
+156
@@ -0,0 +1,156 @@
|
||||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: analog.com:user:spi_engine_execution:1.0
|
||||
// IP Revision: 1
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* IP_DEFINITION_SOURCE = "package_project" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module system_bd_spi_engine_execution_0 (
|
||||
clk,
|
||||
resetn,
|
||||
active,
|
||||
cmd_ready,
|
||||
cmd_valid,
|
||||
cmd,
|
||||
sdo_data_valid,
|
||||
sdo_data_ready,
|
||||
sdo_data,
|
||||
sdi_data_ready,
|
||||
sdi_data_valid,
|
||||
sdi_data,
|
||||
sync_ready,
|
||||
sync_valid,
|
||||
sync,
|
||||
sclk,
|
||||
sdo,
|
||||
sdo_t,
|
||||
sdi,
|
||||
cs,
|
||||
three_wire
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME ctrl_signal_clock, ASSOCIATED_BUSIF ctrl, ASSOCIATED_RESET resetn, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0, XIL_INTERFACENAME spi_signal_clock, ASSOCIATED_BUSIF spi, ASSOCIATED_RESET resetn, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN system_bd_ps_system_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 ctrl_signal_clock CLK, xilinx.com:signal:clock:1.0 spi_signal_clock CLK" *)
|
||||
input wire clk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME ctrl_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0, XIL_INTERFACENAME spi_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 ctrl_signal_reset RST, xilinx.com:signal:reset:1.0 spi_signal_reset RST" *)
|
||||
input wire resetn;
|
||||
output wire active;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl CMD_READY" *)
|
||||
output wire cmd_ready;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl CMD_VALID" *)
|
||||
input wire cmd_valid;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl CMD_DATA" *)
|
||||
input wire [15 : 0] cmd;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl SDO_VALID" *)
|
||||
input wire sdo_data_valid;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl SDO_READY" *)
|
||||
output wire sdo_data_ready;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl SDO_DATA" *)
|
||||
input wire [7 : 0] sdo_data;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl SDI_READY" *)
|
||||
input wire sdi_data_ready;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl SDI_VALID" *)
|
||||
output wire sdi_data_valid;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl SDI_DATA" *)
|
||||
output wire [7 : 0] sdi_data;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl SYNC_READY" *)
|
||||
input wire sync_ready;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl SYNC_VALID" *)
|
||||
output wire sync_valid;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl SYNC_DATA" *)
|
||||
output wire [7 : 0] sync;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_master:1.0 spi SCLK" *)
|
||||
output wire sclk;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_master:1.0 spi SDO" *)
|
||||
output wire sdo;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_master:1.0 spi SDO_T" *)
|
||||
output wire sdo_t;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_master:1.0 spi SDI" *)
|
||||
input wire [0 : 0] sdi;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_master:1.0 spi CS" *)
|
||||
output wire [2 : 0] cs;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_master:1.0 spi THREE_WIRE" *)
|
||||
output wire three_wire;
|
||||
|
||||
spi_engine_execution #(
|
||||
.NUM_OF_CS(3),
|
||||
.DEFAULT_SPI_CFG(0),
|
||||
.DEFAULT_CLK_DIV(0),
|
||||
.DATA_WIDTH(8),
|
||||
.NUM_OF_SDI(1),
|
||||
.SDO_DEFAULT(1'B0),
|
||||
.SDI_DELAY(1'B0)
|
||||
) inst (
|
||||
.clk(clk),
|
||||
.resetn(resetn),
|
||||
.active(active),
|
||||
.cmd_ready(cmd_ready),
|
||||
.cmd_valid(cmd_valid),
|
||||
.cmd(cmd),
|
||||
.sdo_data_valid(sdo_data_valid),
|
||||
.sdo_data_ready(sdo_data_ready),
|
||||
.sdo_data(sdo_data),
|
||||
.sdi_data_ready(sdi_data_ready),
|
||||
.sdi_data_valid(sdi_data_valid),
|
||||
.sdi_data(sdi_data),
|
||||
.sync_ready(sync_ready),
|
||||
.sync_valid(sync_valid),
|
||||
.sync(sync),
|
||||
.sclk(sclk),
|
||||
.sdo(sdo),
|
||||
.sdo_t(sdo_t),
|
||||
.sdi(sdi),
|
||||
.cs(cs),
|
||||
.three_wire(three_wire)
|
||||
);
|
||||
endmodule
|
||||
+156
@@ -0,0 +1,156 @@
|
||||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: analog.com:user:spi_engine_execution:1.0
|
||||
// IP Revision: 1
|
||||
|
||||
(* X_CORE_INFO = "spi_engine_execution,Vivado 2019.1.3" *)
|
||||
(* CHECK_LICENSE_TYPE = "system_bd_spi_engine_execution_0,spi_engine_execution,{}" *)
|
||||
(* IP_DEFINITION_SOURCE = "package_project" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module system_bd_spi_engine_execution_0 (
|
||||
clk,
|
||||
resetn,
|
||||
active,
|
||||
cmd_ready,
|
||||
cmd_valid,
|
||||
cmd,
|
||||
sdo_data_valid,
|
||||
sdo_data_ready,
|
||||
sdo_data,
|
||||
sdi_data_ready,
|
||||
sdi_data_valid,
|
||||
sdi_data,
|
||||
sync_ready,
|
||||
sync_valid,
|
||||
sync,
|
||||
sclk,
|
||||
sdo,
|
||||
sdo_t,
|
||||
sdi,
|
||||
cs,
|
||||
three_wire
|
||||
);
|
||||
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME ctrl_signal_clock, ASSOCIATED_BUSIF ctrl, ASSOCIATED_RESET resetn, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0, XIL_INTERFACENAME spi_signal_clock, ASSOCIATED_BUSIF spi, ASSOCIATED_RESET resetn, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN system_bd_ps_system_0_FCLK_CLK0, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 ctrl_signal_clock CLK, xilinx.com:signal:clock:1.0 spi_signal_clock CLK" *)
|
||||
input wire clk;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME ctrl_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0, XIL_INTERFACENAME spi_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 ctrl_signal_reset RST, xilinx.com:signal:reset:1.0 spi_signal_reset RST" *)
|
||||
input wire resetn;
|
||||
output wire active;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl CMD_READY" *)
|
||||
output wire cmd_ready;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl CMD_VALID" *)
|
||||
input wire cmd_valid;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl CMD_DATA" *)
|
||||
input wire [15 : 0] cmd;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl SDO_VALID" *)
|
||||
input wire sdo_data_valid;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl SDO_READY" *)
|
||||
output wire sdo_data_ready;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl SDO_DATA" *)
|
||||
input wire [7 : 0] sdo_data;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl SDI_READY" *)
|
||||
input wire sdi_data_ready;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl SDI_VALID" *)
|
||||
output wire sdi_data_valid;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl SDI_DATA" *)
|
||||
output wire [7 : 0] sdi_data;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl SYNC_READY" *)
|
||||
input wire sync_ready;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl SYNC_VALID" *)
|
||||
output wire sync_valid;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_engine_ctrl:1.0 ctrl SYNC_DATA" *)
|
||||
output wire [7 : 0] sync;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_master:1.0 spi SCLK" *)
|
||||
output wire sclk;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_master:1.0 spi SDO" *)
|
||||
output wire sdo;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_master:1.0 spi SDO_T" *)
|
||||
output wire sdo_t;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_master:1.0 spi SDI" *)
|
||||
input wire [0 : 0] sdi;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_master:1.0 spi CS" *)
|
||||
output wire [2 : 0] cs;
|
||||
(* X_INTERFACE_INFO = "analog.com:interface:spi_master:1.0 spi THREE_WIRE" *)
|
||||
output wire three_wire;
|
||||
|
||||
spi_engine_execution #(
|
||||
.NUM_OF_CS(3),
|
||||
.DEFAULT_SPI_CFG(0),
|
||||
.DEFAULT_CLK_DIV(0),
|
||||
.DATA_WIDTH(8),
|
||||
.NUM_OF_SDI(1),
|
||||
.SDO_DEFAULT(1'B0),
|
||||
.SDI_DELAY(1'B0)
|
||||
) inst (
|
||||
.clk(clk),
|
||||
.resetn(resetn),
|
||||
.active(active),
|
||||
.cmd_ready(cmd_ready),
|
||||
.cmd_valid(cmd_valid),
|
||||
.cmd(cmd),
|
||||
.sdo_data_valid(sdo_data_valid),
|
||||
.sdo_data_ready(sdo_data_ready),
|
||||
.sdo_data(sdo_data),
|
||||
.sdi_data_ready(sdi_data_ready),
|
||||
.sdi_data_valid(sdi_data_valid),
|
||||
.sdi_data(sdi_data),
|
||||
.sync_ready(sync_ready),
|
||||
.sync_valid(sync_valid),
|
||||
.sync(sync),
|
||||
.sclk(sclk),
|
||||
.sdo(sdo),
|
||||
.sdo_t(sdo_t),
|
||||
.sdi(sdi),
|
||||
.cs(cs),
|
||||
.three_wire(three_wire)
|
||||
);
|
||||
endmodule
|
||||
BIN
Binary file not shown.
+72
@@ -0,0 +1,72 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>xci</spirit:library>
|
||||
<spirit:name>unknown</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>system_bd_spi_engine_execution_0</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="analog.com" spirit:library="user" spirit:name="spi_engine_execution" spirit:version="1.0"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CTRL_SIGNAL_CLOCK.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CTRL_SIGNAL_CLOCK.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CTRL_SIGNAL_CLOCK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CTRL_SIGNAL_CLOCK.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CTRL_SIGNAL_RESET.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SPI_SIGNAL_CLOCK.CLK_DOMAIN">system_bd_ps_system_0_FCLK_CLK0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SPI_SIGNAL_CLOCK.FREQ_HZ">50000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SPI_SIGNAL_CLOCK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SPI_SIGNAL_CLOCK.PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SPI_SIGNAL_RESET.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DATA_WIDTH">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DEFAULT_CLK_DIV">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DEFAULT_SPI_CFG">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.NUM_OF_CS">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.NUM_OF_SDI">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SDI_DELAY">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SDO_DEFAULT">"0"</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">system_bd_spi_engine_execution_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DEFAULT_CLK_DIV">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DEFAULT_SPI_CFG">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_OF_CS">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_OF_SDI">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SDI_DELAY">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SDO_DEFAULT">"0"</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z100</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1.3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:componentInstanceExtensions>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SPI_SIGNAL_CLOCK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SPI_SIGNAL_CLOCK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.DATA_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.NUM_OF_CS" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.NUM_OF_SDI" xilinx:valueSource="user"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:componentInstanceExtensions>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
+963
@@ -0,0 +1,963 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>analog.com</spirit:vendor>
|
||||
<spirit:library>customized_ip</spirit:library>
|
||||
<spirit:name>system_bd_spi_engine_execution_0</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>ctrl</spirit:name>
|
||||
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="spi_engine_ctrl" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="spi_engine_ctrl_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CMD_READY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>cmd_ready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CMD_VALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>cmd_valid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CMD_DATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>cmd</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SDO_READY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sdo_data_ready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SDO_VALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sdo_data_valid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SDO_DATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sdo_data</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SDI_READY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sdi_data_ready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SDI_VALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sdi_data_valid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SDI_DATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sdi_data</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SYNC_READY</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sync_ready</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SYNC_VALID</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sync_valid</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SYNC_DATA</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sync</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>ctrl_signal_clock</spirit:name>
|
||||
<spirit:displayName>ctrl_signal_clock</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>clk</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.CTRL_SIGNAL_CLOCK.ASSOCIATED_BUSIF">ctrl</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.CTRL_SIGNAL_CLOCK.ASSOCIATED_RESET">resetn</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CTRL_SIGNAL_CLOCK.FREQ_HZ">100000000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CTRL_SIGNAL_CLOCK.PHASE">0.000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.CTRL_SIGNAL_CLOCK.CLK_DOMAIN"/>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CTRL_SIGNAL_CLOCK.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>ctrl_signal_reset</spirit:name>
|
||||
<spirit:displayName>ctrl_signal_reset</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>resetn</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.CTRL_SIGNAL_RESET.POLARITY">ACTIVE_LOW</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.CTRL_SIGNAL_RESET.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>spi</spirit:name>
|
||||
<spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="spi_master" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="spi_master_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SCLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sclk</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SDI</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sdi</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SDO</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sdo</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>SDO_T</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>sdo_t</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>THREE_WIRE</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>three_wire</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CS</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>cs</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>spi_signal_clock</spirit:name>
|
||||
<spirit:displayName>spi_signal_clock</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>clk</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.SPI_SIGNAL_CLOCK.ASSOCIATED_BUSIF">spi</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.SPI_SIGNAL_CLOCK.ASSOCIATED_RESET">resetn</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SPI_SIGNAL_CLOCK.FREQ_HZ">50000000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SPI_SIGNAL_CLOCK.PHASE">0.000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.SPI_SIGNAL_CLOCK.CLK_DOMAIN">system_bd_ps_system_0_FCLK_CLK0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>none</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.SPI_SIGNAL_CLOCK.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>spi_signal_reset</spirit:name>
|
||||
<spirit:displayName>spi_signal_reset</spirit:displayName>
|
||||
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>resetn</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value spirit:id="BUSIFPARAM_VALUE.SPI_SIGNAL_RESET.POLARITY">ACTIVE_LOW</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>INSERT_VIP</spirit:name>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.SPI_SIGNAL_RESET.INSERT_VIP">0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:parameterInfo>
|
||||
<xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
|
||||
</xilinx:parameterInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
</spirit:busInterfaces>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagesynthesis</spirit:name>
|
||||
<spirit:displayName>Synthesis</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
|
||||
<spirit:modelName>spi_engine_execution</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Mar 30 08:04:58 UTC 2023</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:47ffe325</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_synthesisconstraints</spirit:name>
|
||||
<spirit:displayName>Synthesis Constraints</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:synthesis.constraints</spirit:envIdentifier>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:47ffe325</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_verilogsynthesiswrapper</spirit:name>
|
||||
<spirit:displayName>Verilog Synthesis Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>verilog</spirit:language>
|
||||
<spirit:modelName>system_bd_spi_engine_execution_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_verilogsynthesiswrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Mar 30 08:04:58 UTC 2023</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:47ffe325</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
|
||||
<spirit:displayName>Simulation</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
||||
<spirit:modelName>spi_engine_execution</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Mar 30 08:04:58 UTC 2023</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:37ab2daa</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_verilogsimulationwrapper</spirit:name>
|
||||
<spirit:displayName>Verilog Simulation Wrapper</spirit:displayName>
|
||||
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
|
||||
<spirit:language>verilog</spirit:language>
|
||||
<spirit:modelName>system_bd_spi_engine_execution_0</spirit:modelName>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_verilogsimulationwrapper_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Mar 30 08:04:58 UTC 2023</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:37ab2daa</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
<spirit:view>
|
||||
<spirit:name>xilinx_externalfiles</spirit:name>
|
||||
<spirit:displayName>External Files</spirit:displayName>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:external.files</spirit:envIdentifier>
|
||||
<spirit:fileSetRef>
|
||||
<spirit:localName>xilinx_externalfiles_view_fileset</spirit:localName>
|
||||
</spirit:fileSetRef>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>GENtimestamp</spirit:name>
|
||||
<spirit:value>Thu Mar 30 08:05:22 UTC 2023</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>outputProductCRC</spirit:name>
|
||||
<spirit:value>9:47ffe325</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>clk</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>resetn</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>active</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>reg</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>cmd_ready</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>cmd_valid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>cmd</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">15</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>sdo_data_valid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>sdo_data_ready</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>reg</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>sdo_data</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.DATA_WIDTH')) - 1)">7</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>sdi_data_ready</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>sdi_data_valid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>reg</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>sdi_data</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.NUM_OF_SDI')) * spirit:decode(id('MODELPARAM_VALUE.DATA_WIDTH'))) - 1)">7</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
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|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>sync_ready</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>sync_valid</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>reg</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>sync</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long">7</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>sclk</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>reg</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>sdo</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>reg</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>sdo_t</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>reg</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>sdi</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_SDI')) - 1)">0</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>std_logic_vector</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
<spirit:driver>
|
||||
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
|
||||
</spirit:driver>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>cs</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:vector>
|
||||
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CS')) - 1)">2</spirit:left>
|
||||
<spirit:right spirit:format="long">0</spirit:right>
|
||||
</spirit:vector>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>reg</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>three_wire</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
<spirit:wireTypeDefs>
|
||||
<spirit:wireTypeDef>
|
||||
<spirit:typeName>reg</spirit:typeName>
|
||||
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
|
||||
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
|
||||
</spirit:wireTypeDef>
|
||||
</spirit:wireTypeDefs>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
<spirit:modelParameters>
|
||||
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
|
||||
<spirit:name>NUM_OF_CS</spirit:name>
|
||||
<spirit:displayName>Num Of Cs</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.NUM_OF_CS">3</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>DEFAULT_SPI_CFG</spirit:name>
|
||||
<spirit:displayName>Default Spi Cfg</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DEFAULT_SPI_CFG">0</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>DEFAULT_CLK_DIV</spirit:name>
|
||||
<spirit:displayName>Default Clk Div</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DEFAULT_CLK_DIV">0</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>DATA_WIDTH</spirit:name>
|
||||
<spirit:displayName>Data Width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DATA_WIDTH">8</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>NUM_OF_SDI</spirit:name>
|
||||
<spirit:displayName>Num Of Sdi</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.NUM_OF_SDI">1</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>SDO_DEFAULT</spirit:name>
|
||||
<spirit:displayName>Sdo Default</spirit:displayName>
|
||||
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SDO_DEFAULT" spirit:bitStringLength="1">"0"</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
<spirit:modelParameter spirit:dataType="integer">
|
||||
<spirit:name>SDI_DELAY</spirit:name>
|
||||
<spirit:displayName>Sdi Delay</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SDI_DELAY">false</spirit:value>
|
||||
</spirit:modelParameter>
|
||||
</spirit:modelParameters>
|
||||
</spirit:model>
|
||||
<spirit:choices>
|
||||
<spirit:choice>
|
||||
<spirit:name>choice_list_5ec0cd51</spirit:name>
|
||||
<spirit:enumeration>"0"</spirit:enumeration>
|
||||
<spirit:enumeration>"1"</spirit:enumeration>
|
||||
</spirit:choice>
|
||||
<spirit:choice>
|
||||
<spirit:name>choice_list_6e3ded9c</spirit:name>
|
||||
<spirit:enumeration>0</spirit:enumeration>
|
||||
<spirit:enumeration>1</spirit:enumeration>
|
||||
<spirit:enumeration>2</spirit:enumeration>
|
||||
<spirit:enumeration>3</spirit:enumeration>
|
||||
</spirit:choice>
|
||||
</spirit:choices>
|
||||
<spirit:fileSets>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/802c/spi_engine_execution.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_verilogsynthesiswrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>synth/system_bd_spi_engine_execution_0.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>../../ipshared/802c/spi_engine_execution.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_verilogsimulationwrapper_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>sim/system_bd_spi_engine_execution_0.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>system_bd_spi_engine_execution_0.dcp</spirit:name>
|
||||
<spirit:userFileType>dcp</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_implementation</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>system_bd_spi_engine_execution_0_stub.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>system_bd_spi_engine_execution_0_stub.vhdl</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>system_bd_spi_engine_execution_0_sim_netlist.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>system_bd_spi_engine_execution_0_sim_netlist.vhdl</spirit:name>
|
||||
<spirit:fileType>vhdlSource</spirit:fileType>
|
||||
<spirit:userFileType>USED_IN_simulation</spirit:userFileType>
|
||||
<spirit:userFileType>USED_IN_single_language</spirit:userFileType>
|
||||
<spirit:logicalName>xil_defaultlib</spirit:logicalName>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
</spirit:fileSets>
|
||||
<spirit:description>spi_engine_execution_v1_0</spirit:description>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>NUM_OF_CS</spirit:name>
|
||||
<spirit:displayName>Number of CSN lines</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.NUM_OF_CS" spirit:minimum="1" spirit:maximum="32" spirit:rangeType="long">3</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>DEFAULT_SPI_CFG</spirit:name>
|
||||
<spirit:displayName>Default SPI mode</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DEFAULT_SPI_CFG" spirit:choiceRef="choice_list_6e3ded9c">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>DEFAULT_CLK_DIV</spirit:name>
|
||||
<spirit:displayName>Default SCLK divider</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DEFAULT_CLK_DIV" spirit:minimum="0" spirit:maximum="255" spirit:rangeType="long">0</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>DATA_WIDTH</spirit:name>
|
||||
<spirit:displayName>Parallel data width</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DATA_WIDTH" spirit:minimum="8" spirit:maximum="256" spirit:rangeType="long">8</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>NUM_OF_SDI</spirit:name>
|
||||
<spirit:displayName>Number of MISO</spirit:displayName>
|
||||
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.NUM_OF_SDI" spirit:minimum="1" spirit:maximum="8" spirit:rangeType="long">1</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>SDO_DEFAULT</spirit:name>
|
||||
<spirit:displayName>MOSI default level</spirit:displayName>
|
||||
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.SDO_DEFAULT" spirit:choiceRef="choice_list_5ec0cd51" spirit:bitStringLength="1">"0"</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>SDI_DELAY</spirit:name>
|
||||
<spirit:displayName>Delay MISO latching</spirit:displayName>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.SDI_DELAY">false</spirit:value>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>Component_Name</spirit:name>
|
||||
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">system_bd_spi_engine_execution_0</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:coreExtensions>
|
||||
<xilinx:displayName>spi_engine_execution_v1_0</xilinx:displayName>
|
||||
<xilinx:definitionSource>package_project</xilinx:definitionSource>
|
||||
<xilinx:coreRevision>1</xilinx:coreRevision>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SPI_SIGNAL_CLOCK.CLK_DOMAIN" xilinx:valueSource="default_prop" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.SPI_SIGNAL_CLOCK.FREQ_HZ" xilinx:valueSource="user_prop" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.DATA_WIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.NUM_OF_CS" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.NUM_OF_SDI" xilinx:valueSource="user"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
<xilinx:xilinxVersion>2019.1.3</xilinx:xilinxVersion>
|
||||
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="5778d7eb"/>
|
||||
<xilinx:checksum xilinx:scope="ports" xilinx:value="5681b5a9"/>
|
||||
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="8b510ac0"/>
|
||||
<xilinx:checksum xilinx:scope="parameters" xilinx:value="6b1dd38c"/>
|
||||
</xilinx:packagingInfo>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:component>
|
||||
BIN
Binary file not shown.
BIN
Binary file not shown.
+42
@@ -0,0 +1,42 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Thu Mar 30 16:05:22 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ipi-bds/system_bd/ip/system_bd_spi_engine_execution_0/system_bd_spi_engine_execution_0_stub.v
|
||||
// Design : system_bd_spi_engine_execution_0
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z100ffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "spi_engine_execution,Vivado 2019.1.3" *)
|
||||
module system_bd_spi_engine_execution_0(clk, resetn, active, cmd_ready, cmd_valid, cmd,
|
||||
sdo_data_valid, sdo_data_ready, sdo_data, sdi_data_ready, sdi_data_valid, sdi_data,
|
||||
sync_ready, sync_valid, sync, sclk, sdo, sdo_t, sdi, cs, three_wire)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk,resetn,active,cmd_ready,cmd_valid,cmd[15:0],sdo_data_valid,sdo_data_ready,sdo_data[7:0],sdi_data_ready,sdi_data_valid,sdi_data[7:0],sync_ready,sync_valid,sync[7:0],sclk,sdo,sdo_t,sdi[0:0],cs[2:0],three_wire" */;
|
||||
input clk;
|
||||
input resetn;
|
||||
output active;
|
||||
output cmd_ready;
|
||||
input cmd_valid;
|
||||
input [15:0]cmd;
|
||||
input sdo_data_valid;
|
||||
output sdo_data_ready;
|
||||
input [7:0]sdo_data;
|
||||
input sdi_data_ready;
|
||||
output sdi_data_valid;
|
||||
output [7:0]sdi_data;
|
||||
input sync_ready;
|
||||
output sync_valid;
|
||||
output [7:0]sync;
|
||||
output sclk;
|
||||
output sdo;
|
||||
output sdo_t;
|
||||
input [0:0]sdi;
|
||||
output [2:0]cs;
|
||||
output three_wire;
|
||||
endmodule
|
||||
+50
@@ -0,0 +1,50 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Thu Mar 30 16:05:22 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ipi-bds/system_bd/ip/system_bd_spi_engine_execution_0/system_bd_spi_engine_execution_0_stub.vhdl
|
||||
-- Design : system_bd_spi_engine_execution_0
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z100ffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity system_bd_spi_engine_execution_0 is
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
resetn : in STD_LOGIC;
|
||||
active : out STD_LOGIC;
|
||||
cmd_ready : out STD_LOGIC;
|
||||
cmd_valid : in STD_LOGIC;
|
||||
cmd : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
sdo_data_valid : in STD_LOGIC;
|
||||
sdo_data_ready : out STD_LOGIC;
|
||||
sdo_data : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
sdi_data_ready : in STD_LOGIC;
|
||||
sdi_data_valid : out STD_LOGIC;
|
||||
sdi_data : out STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
sync_ready : in STD_LOGIC;
|
||||
sync_valid : out STD_LOGIC;
|
||||
sync : out STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
sclk : out STD_LOGIC;
|
||||
sdo : out STD_LOGIC;
|
||||
sdo_t : out STD_LOGIC;
|
||||
sdi : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
cs : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
three_wire : out STD_LOGIC
|
||||
);
|
||||
|
||||
end system_bd_spi_engine_execution_0;
|
||||
|
||||
architecture stub of system_bd_spi_engine_execution_0 is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,resetn,active,cmd_ready,cmd_valid,cmd[15:0],sdo_data_valid,sdo_data_ready,sdo_data[7:0],sdi_data_ready,sdi_data_valid,sdi_data[7:0],sync_ready,sync_valid,sync[7:0],sclk,sdo,sdo_t,sdi[0:0],cs[2:0],three_wire";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "spi_engine_execution,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
+134
@@ -0,0 +1,134 @@
|
||||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:xlconcat:2.1
|
||||
// IP Revision: 3
|
||||
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module system_bd_xlconcat_irpt_0 (
|
||||
In0,
|
||||
dout
|
||||
);
|
||||
|
||||
input wire [0 : 0] In0;
|
||||
output wire [0 : 0] dout;
|
||||
|
||||
xlconcat_v2_1_3_xlconcat #(
|
||||
.IN0_WIDTH(1),
|
||||
.IN1_WIDTH(1),
|
||||
.IN2_WIDTH(1),
|
||||
.IN3_WIDTH(1),
|
||||
.IN4_WIDTH(1),
|
||||
.IN5_WIDTH(1),
|
||||
.IN6_WIDTH(1),
|
||||
.IN7_WIDTH(1),
|
||||
.IN8_WIDTH(1),
|
||||
.IN9_WIDTH(1),
|
||||
.IN10_WIDTH(1),
|
||||
.IN11_WIDTH(1),
|
||||
.IN12_WIDTH(1),
|
||||
.IN13_WIDTH(1),
|
||||
.IN14_WIDTH(1),
|
||||
.IN15_WIDTH(1),
|
||||
.IN16_WIDTH(1),
|
||||
.IN17_WIDTH(1),
|
||||
.IN18_WIDTH(1),
|
||||
.IN19_WIDTH(1),
|
||||
.IN20_WIDTH(1),
|
||||
.IN21_WIDTH(1),
|
||||
.IN22_WIDTH(1),
|
||||
.IN23_WIDTH(1),
|
||||
.IN24_WIDTH(1),
|
||||
.IN25_WIDTH(1),
|
||||
.IN26_WIDTH(1),
|
||||
.IN27_WIDTH(1),
|
||||
.IN28_WIDTH(1),
|
||||
.IN29_WIDTH(1),
|
||||
.IN30_WIDTH(1),
|
||||
.IN31_WIDTH(1),
|
||||
.dout_width(1),
|
||||
.NUM_PORTS(1)
|
||||
) inst (
|
||||
.In0(In0),
|
||||
.In1(1'B0),
|
||||
.In2(1'B0),
|
||||
.In3(1'B0),
|
||||
.In4(1'B0),
|
||||
.In5(1'B0),
|
||||
.In6(1'B0),
|
||||
.In7(1'B0),
|
||||
.In8(1'B0),
|
||||
.In9(1'B0),
|
||||
.In10(1'B0),
|
||||
.In11(1'B0),
|
||||
.In12(1'B0),
|
||||
.In13(1'B0),
|
||||
.In14(1'B0),
|
||||
.In15(1'B0),
|
||||
.In16(1'B0),
|
||||
.In17(1'B0),
|
||||
.In18(1'B0),
|
||||
.In19(1'B0),
|
||||
.In20(1'B0),
|
||||
.In21(1'B0),
|
||||
.In22(1'B0),
|
||||
.In23(1'B0),
|
||||
.In24(1'B0),
|
||||
.In25(1'B0),
|
||||
.In26(1'B0),
|
||||
.In27(1'B0),
|
||||
.In28(1'B0),
|
||||
.In29(1'B0),
|
||||
.In30(1'B0),
|
||||
.In31(1'B0),
|
||||
.dout(dout)
|
||||
);
|
||||
endmodule
|
||||
+136
@@ -0,0 +1,136 @@
|
||||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// IP VLNV: xilinx.com:ip:xlconcat:2.1
|
||||
// IP Revision: 3
|
||||
|
||||
(* X_CORE_INFO = "xlconcat_v2_1_3_xlconcat,Vivado 2019.1.3" *)
|
||||
(* CHECK_LICENSE_TYPE = "system_bd_xlconcat_irpt_0,xlconcat_v2_1_3_xlconcat,{}" *)
|
||||
(* CORE_GENERATION_INFO = "system_bd_xlconcat_irpt_0,xlconcat_v2_1_3_xlconcat,{x_ipProduct=Vivado 2019.1.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconcat,x_ipVersion=2.1,x_ipCoreRevision=3,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,IN0_WIDTH=1,IN1_WIDTH=1,IN2_WIDTH=1,IN3_WIDTH=1,IN4_WIDTH=1,IN5_WIDTH=1,IN6_WIDTH=1,IN7_WIDTH=1,IN8_WIDTH=1,IN9_WIDTH=1,IN10_WIDTH=1,IN11_WIDTH=1,IN12_WIDTH=1,IN13_WIDTH=1,IN14_WIDTH=1,IN15_WIDTH=1,IN16_WIDTH=1,IN17_WIDTH=1,IN18_WIDTH=1,IN19_WIDTH=1,IN20_WIDTH=1,IN21_WIDTH=1,IN22_WIDTH=\
|
||||
1,IN23_WIDTH=1,IN24_WIDTH=1,IN25_WIDTH=1,IN26_WIDTH=1,IN27_WIDTH=1,IN28_WIDTH=1,IN29_WIDTH=1,IN30_WIDTH=1,IN31_WIDTH=1,dout_width=1,NUM_PORTS=1}" *)
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module system_bd_xlconcat_irpt_0 (
|
||||
In0,
|
||||
dout
|
||||
);
|
||||
|
||||
input wire [0 : 0] In0;
|
||||
output wire [0 : 0] dout;
|
||||
|
||||
xlconcat_v2_1_3_xlconcat #(
|
||||
.IN0_WIDTH(1),
|
||||
.IN1_WIDTH(1),
|
||||
.IN2_WIDTH(1),
|
||||
.IN3_WIDTH(1),
|
||||
.IN4_WIDTH(1),
|
||||
.IN5_WIDTH(1),
|
||||
.IN6_WIDTH(1),
|
||||
.IN7_WIDTH(1),
|
||||
.IN8_WIDTH(1),
|
||||
.IN9_WIDTH(1),
|
||||
.IN10_WIDTH(1),
|
||||
.IN11_WIDTH(1),
|
||||
.IN12_WIDTH(1),
|
||||
.IN13_WIDTH(1),
|
||||
.IN14_WIDTH(1),
|
||||
.IN15_WIDTH(1),
|
||||
.IN16_WIDTH(1),
|
||||
.IN17_WIDTH(1),
|
||||
.IN18_WIDTH(1),
|
||||
.IN19_WIDTH(1),
|
||||
.IN20_WIDTH(1),
|
||||
.IN21_WIDTH(1),
|
||||
.IN22_WIDTH(1),
|
||||
.IN23_WIDTH(1),
|
||||
.IN24_WIDTH(1),
|
||||
.IN25_WIDTH(1),
|
||||
.IN26_WIDTH(1),
|
||||
.IN27_WIDTH(1),
|
||||
.IN28_WIDTH(1),
|
||||
.IN29_WIDTH(1),
|
||||
.IN30_WIDTH(1),
|
||||
.IN31_WIDTH(1),
|
||||
.dout_width(1),
|
||||
.NUM_PORTS(1)
|
||||
) inst (
|
||||
.In0(In0),
|
||||
.In1(1'B0),
|
||||
.In2(1'B0),
|
||||
.In3(1'B0),
|
||||
.In4(1'B0),
|
||||
.In5(1'B0),
|
||||
.In6(1'B0),
|
||||
.In7(1'B0),
|
||||
.In8(1'B0),
|
||||
.In9(1'B0),
|
||||
.In10(1'B0),
|
||||
.In11(1'B0),
|
||||
.In12(1'B0),
|
||||
.In13(1'B0),
|
||||
.In14(1'B0),
|
||||
.In15(1'B0),
|
||||
.In16(1'B0),
|
||||
.In17(1'B0),
|
||||
.In18(1'B0),
|
||||
.In19(1'B0),
|
||||
.In20(1'B0),
|
||||
.In21(1'B0),
|
||||
.In22(1'B0),
|
||||
.In23(1'B0),
|
||||
.In24(1'B0),
|
||||
.In25(1'B0),
|
||||
.In26(1'B0),
|
||||
.In27(1'B0),
|
||||
.In28(1'B0),
|
||||
.In29(1'B0),
|
||||
.In30(1'B0),
|
||||
.In31(1'B0),
|
||||
.dout(dout)
|
||||
);
|
||||
endmodule
|
||||
+113
@@ -0,0 +1,113 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>xci</spirit:library>
|
||||
<spirit:name>unknown</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>system_bd_xlconcat_irpt_0</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="xlconcat" spirit:version="2.1"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IN0_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IN10_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IN11_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IN12_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IN13_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IN14_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IN15_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IN16_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IN17_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IN18_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IN19_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IN1_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IN20_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IN21_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IN22_WIDTH">1</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IN23_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IN24_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IN25_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IN26_WIDTH">1</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IN27_WIDTH">1</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IN28_WIDTH">1</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IN29_WIDTH">1</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IN2_WIDTH">1</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IN30_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IN31_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IN3_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IN4_WIDTH">1</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IN5_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IN6_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IN7_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IN8_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.IN9_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.NUM_PORTS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.dout_width">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">system_bd_xlconcat_irpt_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN0_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN10_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN11_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN12_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN13_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN14_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN15_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN16_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN17_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN18_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN19_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN1_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN20_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN21_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN22_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN23_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN24_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN25_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN26_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN27_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN28_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN29_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN2_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN30_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN31_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN3_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN4_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN5_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN6_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN7_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN8_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN9_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_PORTS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dout_width">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z100</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Integrator</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">../../ipshared</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1.3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:componentInstanceExtensions>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.IN0_WIDTH" xilinx:valueSource="propagated" xilinx:valuePermission="bd_and_user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.NUM_PORTS" xilinx:valueSource="user"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:componentInstanceExtensions>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
+1386
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user