Archived
first commit after restructuring
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
|
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_spi_engine #(
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parameter CMD_FIFO_ADDRESS_WIDTH = 4,
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parameter SYNC_FIFO_ADDRESS_WIDTH = 4,
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parameter SDO_FIFO_ADDRESS_WIDTH = 5,
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parameter SDI_FIFO_ADDRESS_WIDTH = 5,
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parameter MM_IF_TYPE = 0,
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parameter ASYNC_SPI_CLK = 0,
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parameter NUM_OFFLOAD = 0,
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parameter OFFLOAD0_CMD_MEM_ADDRESS_WIDTH = 4,
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parameter OFFLOAD0_SDO_MEM_ADDRESS_WIDTH = 4,
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parameter ID = 0,
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parameter [15:0] DATA_WIDTH = 8,
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parameter [ 7:0] NUM_OF_SDI = 1 ) (
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// Slave AXI interface
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input s_axi_aclk,
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input s_axi_aresetn,
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input s_axi_awvalid,
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input [15:0] s_axi_awaddr,
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output s_axi_awready,
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input [2:0] s_axi_awprot,
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input s_axi_wvalid,
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input [31:0] s_axi_wdata,
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input [ 3:0] s_axi_wstrb,
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output s_axi_wready,
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output s_axi_bvalid,
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output [ 1:0] s_axi_bresp,
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input s_axi_bready,
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input s_axi_arvalid,
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input [15:0] s_axi_araddr,
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output s_axi_arready,
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input [2:0] s_axi_arprot,
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output s_axi_rvalid,
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input s_axi_rready,
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output [ 1:0] s_axi_rresp,
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output [31:0] s_axi_rdata,
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// up interface
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input up_clk,
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input up_rstn,
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input up_wreq,
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input [13:0] up_waddr,
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input [31:0] up_wdata,
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output up_wack,
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input up_rreq,
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input [13:0] up_raddr,
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output [31:0] up_rdata,
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output up_rack,
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output reg irq,
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// SPI signals
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input spi_clk,
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output spi_resetn,
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input cmd_ready,
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output cmd_valid,
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output [15:0] cmd_data,
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input sdo_data_ready,
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output sdo_data_valid,
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output [(DATA_WIDTH-1):0] sdo_data,
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output sdi_data_ready,
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input sdi_data_valid,
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input [(NUM_OF_SDI * DATA_WIDTH-1):0] sdi_data,
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output sync_ready,
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input sync_valid,
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input [7:0] sync_data,
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// Offload ctrl signals
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output offload0_cmd_wr_en,
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output [15:0] offload0_cmd_wr_data,
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output offload0_sdo_wr_en,
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output [(DATA_WIDTH-1):0] offload0_sdo_wr_data,
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output offload0_mem_reset,
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output offload0_enable,
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input offload0_enabled,
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output offload_sync_ready,
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input offload_sync_valid,
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input [7:0] offload_sync_data);
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localparam PCORE_VERSION = 'h010071;
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localparam S_AXI = 0;
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localparam UP_FIFO = 1;
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wire clk;
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wire rstn;
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wire [CMD_FIFO_ADDRESS_WIDTH:0] cmd_fifo_room;
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wire cmd_fifo_almost_empty;
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wire [15:0] cmd_fifo_in_data;
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wire cmd_fifo_in_ready;
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wire cmd_fifo_in_valid;
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wire [SDO_FIFO_ADDRESS_WIDTH:0] sdo_fifo_room;
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wire sdo_fifo_almost_empty;
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wire [(DATA_WIDTH-1):0] sdo_fifo_in_data;
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wire sdo_fifo_in_ready;
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wire sdo_fifo_in_valid;
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wire sdi_fifo_out_data_msb_s;
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wire [SDI_FIFO_ADDRESS_WIDTH:0] sdi_fifo_level;
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wire sdi_fifo_almost_full;
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wire [(NUM_OF_SDI * DATA_WIDTH-1):0] sdi_fifo_out_data;
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wire sdi_fifo_out_ready;
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wire sdi_fifo_out_valid;
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wire [7:0] sync_fifo_data;
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wire sync_fifo_valid;
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wire [7:0] offload_sync_fifo_data;
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wire offload_sync_fifo_valid;
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reg up_sw_reset = 1'b1;
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wire up_sw_resetn = ~up_sw_reset;
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reg [31:0] up_rdata_ff = 'd0;
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reg up_wack_ff = 1'b0;
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reg up_rack_ff = 1'b0;
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wire up_wreq_s;
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wire up_rreq_s;
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wire [31:0] up_wdata_s;
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wire [13:0] up_waddr_s;
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wire [13:0] up_raddr_s;
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// Scratch register
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reg [31:0] up_scratch = 'h00;
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reg [7:0] sync_id = 'h00;
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reg sync_id_pending = 1'b0;
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reg [7:0] offload_sync_id = 'h00;
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reg offload_sync_id_pending = 1'b0;
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generate if (MM_IF_TYPE == S_AXI) begin
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// assign clock and reset
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assign clk = s_axi_aclk;
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assign rstn = s_axi_aresetn;
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// interface wrapper
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up_axi #(
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.AXI_ADDRESS_WIDTH (16)
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) i_up_axi (
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.up_rstn(rstn),
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.up_clk(clk),
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.up_axi_awvalid(s_axi_awvalid),
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.up_axi_awaddr(s_axi_awaddr),
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.up_axi_awready(s_axi_awready),
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.up_axi_wvalid(s_axi_wvalid),
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.up_axi_wdata(s_axi_wdata),
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.up_axi_wstrb(s_axi_wstrb),
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.up_axi_wready(s_axi_wready),
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.up_axi_bvalid(s_axi_bvalid),
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.up_axi_bresp(s_axi_bresp),
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.up_axi_bready(s_axi_bready),
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.up_axi_arvalid(s_axi_arvalid),
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.up_axi_araddr(s_axi_araddr),
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.up_axi_arready(s_axi_arready),
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.up_axi_rvalid(s_axi_rvalid),
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.up_axi_rresp(s_axi_rresp),
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.up_axi_rdata(s_axi_rdata),
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.up_axi_rready(s_axi_rready),
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.up_wreq(up_wreq_s),
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.up_waddr(up_waddr_s),
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.up_wdata(up_wdata_s),
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.up_wack(up_wack_ff),
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.up_rreq(up_rreq_s),
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.up_raddr(up_raddr_s),
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.up_rdata(up_rdata_ff),
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.up_rack(up_rack_ff)
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);
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assign up_rdata = 32'b0;
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assign up_rack = 1'b0;
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assign up_wack = 1'b0;
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end
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endgenerate
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generate if (MM_IF_TYPE == UP_FIFO) begin
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// assign clock and reset
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assign clk = up_clk;
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assign rstn = up_rstn;
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assign up_wreq_s = up_wreq;
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assign up_waddr_s = up_waddr;
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assign up_wdata_s = up_wdata;
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assign up_wack = up_wack_ff;
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assign up_rreq_s = up_rreq;
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assign up_raddr_s = up_raddr;
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assign up_rdata = up_rdata_ff;
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assign up_rack = up_rack_ff;
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end
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endgenerate
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// IRQ handling
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reg [3:0] up_irq_mask = 'h0;
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wire [3:0] up_irq_source;
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wire [3:0] up_irq_pending;
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assign up_irq_source = {
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offload_sync_id_pending,
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sync_id_pending,
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sdi_fifo_almost_full,
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sdo_fifo_almost_empty,
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cmd_fifo_almost_empty
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};
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assign up_irq_pending = up_irq_mask & up_irq_source;
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always @(posedge clk) begin
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if (rstn == 1'b0)
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irq <= 1'b0;
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else
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irq <= |up_irq_pending;
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end
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always @(posedge clk) begin
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if (rstn == 1'b0) begin
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up_wack_ff <= 1'b0;
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up_scratch <= 'h00;
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up_sw_reset <= 1'b1;
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end else begin
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up_wack_ff <= up_wreq_s;
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if (up_wreq_s) begin
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case (up_waddr_s)
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8'h02: up_scratch <= up_wdata_s;
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8'h10: up_sw_reset <= up_wdata_s;
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endcase
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end
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end
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end
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reg offload0_enable_reg;
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reg offload0_mem_reset_reg;
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wire offload0_enabled_s;
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// the software reset should reset all the registers
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always @(posedge clk) begin
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if (up_sw_resetn == 1'b0) begin
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up_irq_mask <= 'h00;
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offload0_enable_reg <= 1'b0;
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offload0_mem_reset_reg <= 1'b0;
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end else begin
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if (up_wreq_s) begin
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case (up_waddr_s)
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8'h20: up_irq_mask <= up_wdata_s;
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8'h40: offload0_enable_reg <= up_wdata_s[0];
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8'h42: offload0_mem_reset_reg <= up_wdata_s[0];
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endcase
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end
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end
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end
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always @(posedge clk) begin
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if (rstn == 1'b0) begin
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up_rack_ff <= 'd0;
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end else begin
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up_rack_ff <= up_rreq_s;
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end
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end
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generate
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if (NUM_OF_SDI > 1) begin
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// Only the first two SDI data can be recovered through AXI regmap
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assign sdi_fifo_out_data_msb_s = sdi_fifo_out_data[DATA_WIDTH+:DATA_WIDTH];
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end else begin
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assign sdi_fifo_out_data_msb_s = sdi_fifo_out_data;
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end
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endgenerate
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always @(posedge clk) begin
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case (up_raddr_s)
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8'h00: up_rdata_ff <= PCORE_VERSION;
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8'h01: up_rdata_ff <= ID;
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8'h02: up_rdata_ff <= up_scratch;
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8'h03: up_rdata_ff <= {8'b0, NUM_OF_SDI, DATA_WIDTH};
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8'h10: up_rdata_ff <= up_sw_reset;
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8'h20: up_rdata_ff <= up_irq_mask;
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8'h21: up_rdata_ff <= up_irq_pending;
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8'h22: up_rdata_ff <= up_irq_source;
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8'h30: up_rdata_ff <= sync_id;
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8'h31: up_rdata_ff <= offload_sync_id;
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8'h34: up_rdata_ff <= cmd_fifo_room;
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8'h35: up_rdata_ff <= sdo_fifo_room;
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8'h36: up_rdata_ff <= sdi_fifo_level;
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8'h3a: up_rdata_ff <= sdi_fifo_out_data[DATA_WIDTH-1:0];
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8'h3b: up_rdata_ff <= sdi_fifo_out_data_msb_s; /* store SDI's 32 bits MSB, if exists */
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8'h3c: up_rdata_ff <= sdi_fifo_out_data; /* PEEK register */
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8'h40: up_rdata_ff <= {offload0_enable_reg};
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8'h41: up_rdata_ff <= {offload0_enabled_s};
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||||
default: up_rdata_ff <= 'h00;
|
||||
endcase
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (up_sw_resetn == 1'b0) begin
|
||||
sync_id <= 'h00;
|
||||
sync_id_pending <= 1'b0;
|
||||
end else begin
|
||||
if (sync_fifo_valid == 1'b1) begin
|
||||
sync_id <= sync_fifo_data;
|
||||
sync_id_pending <= 1'b1;
|
||||
end else if (up_wreq_s == 1'b1 && up_waddr_s == 8'h21 && up_wdata_s[3] == 1'b1) begin
|
||||
sync_id_pending <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (up_sw_resetn == 1'b0) begin
|
||||
offload_sync_id <= 'h00;
|
||||
offload_sync_id_pending <= 1'b0;
|
||||
end else begin
|
||||
if (offload_sync_fifo_valid == 1'b1) begin
|
||||
offload_sync_id <= offload_sync_fifo_data;
|
||||
offload_sync_id_pending <= 1'b1;
|
||||
end else if (up_wreq_s == 1'b1 && up_waddr_s == 8'h21 && up_wdata_s[3] == 1'b1) begin
|
||||
offload_sync_id_pending <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
generate if (ASYNC_SPI_CLK) begin
|
||||
|
||||
wire spi_reset;
|
||||
ad_rst i_spi_resetn (
|
||||
.rst_async(up_sw_reset),
|
||||
.clk(spi_clk),
|
||||
.rst(spi_reset),
|
||||
.rstn()
|
||||
);
|
||||
assign spi_resetn = ~spi_reset;
|
||||
end else begin
|
||||
assign spi_resetn = ~up_sw_reset;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
/* Evaluates to true if FIFO level/room is 3/4 or above */
|
||||
`define axi_spi_engine_check_watermark(x, n) \
|
||||
(x[n] == 1'b1 || x[n-1:n-2] == 2'b11)
|
||||
|
||||
assign cmd_fifo_in_valid = up_wreq_s == 1'b1 && up_waddr_s == 8'h38;
|
||||
assign cmd_fifo_in_data = up_wdata_s[15:0];
|
||||
assign cmd_fifo_almost_empty =
|
||||
`axi_spi_engine_check_watermark(cmd_fifo_room, CMD_FIFO_ADDRESS_WIDTH);
|
||||
|
||||
util_axis_fifo #(
|
||||
.DATA_WIDTH(16),
|
||||
.ASYNC_CLK(ASYNC_SPI_CLK),
|
||||
.ADDRESS_WIDTH(CMD_FIFO_ADDRESS_WIDTH),
|
||||
.S_AXIS_REGISTERED(0)
|
||||
) i_cmd_fifo (
|
||||
.s_axis_aclk(clk),
|
||||
.s_axis_aresetn(up_sw_resetn),
|
||||
.s_axis_ready(cmd_fifo_in_ready),
|
||||
.s_axis_valid(cmd_fifo_in_valid),
|
||||
.s_axis_data(cmd_fifo_in_data),
|
||||
.s_axis_room(cmd_fifo_room),
|
||||
.s_axis_empty(),
|
||||
.m_axis_aclk(spi_clk),
|
||||
.m_axis_aresetn(spi_resetn),
|
||||
.m_axis_ready(cmd_ready),
|
||||
.m_axis_valid(cmd_valid),
|
||||
.m_axis_data(cmd_data),
|
||||
.m_axis_level()
|
||||
);
|
||||
|
||||
assign sdo_fifo_in_valid = up_wreq_s == 1'b1 && up_waddr_s == 8'h39;
|
||||
assign sdo_fifo_in_data = up_wdata_s[(DATA_WIDTH-1):0];
|
||||
assign sdo_fifo_almost_empty =
|
||||
`axi_spi_engine_check_watermark(sdo_fifo_room, SDO_FIFO_ADDRESS_WIDTH);
|
||||
|
||||
util_axis_fifo #(
|
||||
.DATA_WIDTH(DATA_WIDTH),
|
||||
.ASYNC_CLK(ASYNC_SPI_CLK),
|
||||
.ADDRESS_WIDTH(SDO_FIFO_ADDRESS_WIDTH),
|
||||
.S_AXIS_REGISTERED(0)
|
||||
) i_sdo_fifo (
|
||||
.s_axis_aclk(clk),
|
||||
.s_axis_aresetn(up_sw_resetn),
|
||||
.s_axis_ready(sdo_fifo_in_ready),
|
||||
.s_axis_valid(sdo_fifo_in_valid),
|
||||
.s_axis_data(sdo_fifo_in_data),
|
||||
.s_axis_room(sdo_fifo_room),
|
||||
.s_axis_empty(),
|
||||
.m_axis_aclk(spi_clk),
|
||||
.m_axis_aresetn(spi_resetn),
|
||||
.m_axis_ready(sdo_data_ready),
|
||||
.m_axis_valid(sdo_data_valid),
|
||||
.m_axis_data(sdo_data),
|
||||
.m_axis_level()
|
||||
);
|
||||
|
||||
assign sdi_fifo_out_ready = up_rreq_s == 1'b1 && up_raddr_s == 8'h3a;
|
||||
assign sdi_fifo_almost_full =
|
||||
`axi_spi_engine_check_watermark(sdi_fifo_level, SDI_FIFO_ADDRESS_WIDTH);
|
||||
|
||||
util_axis_fifo #(
|
||||
.DATA_WIDTH(NUM_OF_SDI * DATA_WIDTH),
|
||||
.ASYNC_CLK(ASYNC_SPI_CLK),
|
||||
.ADDRESS_WIDTH(SDI_FIFO_ADDRESS_WIDTH),
|
||||
.S_AXIS_REGISTERED(0)
|
||||
) i_sdi_fifo (
|
||||
.s_axis_aclk(spi_clk),
|
||||
.s_axis_aresetn(spi_resetn),
|
||||
.s_axis_ready(sdi_data_ready),
|
||||
.s_axis_valid(sdi_data_valid),
|
||||
.s_axis_data(sdi_data),
|
||||
.s_axis_room(),
|
||||
.s_axis_empty(),
|
||||
.m_axis_aclk(clk),
|
||||
.m_axis_aresetn(up_sw_resetn),
|
||||
.m_axis_ready(sdi_fifo_out_ready),
|
||||
.m_axis_valid(sdi_fifo_out_valid),
|
||||
.m_axis_data(sdi_fifo_out_data),
|
||||
.m_axis_level(sdi_fifo_level)
|
||||
);
|
||||
|
||||
generate if (ASYNC_SPI_CLK) begin
|
||||
|
||||
// synchronization FIFO for the SYNC interface
|
||||
util_axis_fifo #(
|
||||
.DATA_WIDTH(8),
|
||||
.ASYNC_CLK(ASYNC_SPI_CLK),
|
||||
.ADDRESS_WIDTH(SYNC_FIFO_ADDRESS_WIDTH),
|
||||
.S_AXIS_REGISTERED(0)
|
||||
) i_sync_fifo (
|
||||
.s_axis_aclk(spi_clk),
|
||||
.s_axis_aresetn(spi_resetn),
|
||||
.s_axis_ready(sync_ready),
|
||||
.s_axis_valid(sync_valid),
|
||||
.s_axis_data(sync_data),
|
||||
.s_axis_room(),
|
||||
.s_axis_empty(),
|
||||
.m_axis_aclk(clk),
|
||||
.m_axis_aresetn(up_sw_resetn),
|
||||
.m_axis_ready(1'b1),
|
||||
.m_axis_valid(sync_fifo_valid),
|
||||
.m_axis_data(sync_fifo_data),
|
||||
.m_axis_level()
|
||||
);
|
||||
|
||||
// synchronization FIFO for the offload command interface
|
||||
wire up_offload0_cmd_wr_en_s;
|
||||
wire [15:0] up_offload0_cmd_wr_data_s;
|
||||
|
||||
util_axis_fifo #(
|
||||
.DATA_WIDTH(16),
|
||||
.ASYNC_CLK(ASYNC_SPI_CLK),
|
||||
.ADDRESS_WIDTH(SYNC_FIFO_ADDRESS_WIDTH),
|
||||
.S_AXIS_REGISTERED(0)
|
||||
) i_offload_cmd_fifo (
|
||||
.s_axis_aclk(clk),
|
||||
.s_axis_aresetn(up_sw_resetn),
|
||||
.s_axis_ready(),
|
||||
.s_axis_valid(up_offload0_cmd_wr_en_s),
|
||||
.s_axis_data(up_offload0_cmd_wr_data_s),
|
||||
.s_axis_room(),
|
||||
.s_axis_empty(),
|
||||
.m_axis_aclk(spi_clk),
|
||||
.m_axis_aresetn(spi_resetn),
|
||||
.m_axis_ready(1'b1),
|
||||
.m_axis_valid(offload0_cmd_wr_en),
|
||||
.m_axis_data(offload0_cmd_wr_data),
|
||||
.m_axis_level()
|
||||
);
|
||||
|
||||
assign up_offload0_cmd_wr_en_s = up_wreq_s == 1'b1 && up_waddr_s == 8'h44;
|
||||
assign up_offload0_cmd_wr_data_s = up_wdata_s[15:0];
|
||||
|
||||
// synchronization FIFO for the offload SDO interface
|
||||
wire up_offload0_sdo_wr_en_s;
|
||||
wire [DATA_WIDTH-1:0] up_offload0_sdo_wr_data_s;
|
||||
|
||||
util_axis_fifo #(
|
||||
.DATA_WIDTH(DATA_WIDTH),
|
||||
.ASYNC_CLK(ASYNC_SPI_CLK),
|
||||
.ADDRESS_WIDTH(SYNC_FIFO_ADDRESS_WIDTH),
|
||||
.S_AXIS_REGISTERED(0)
|
||||
) i_offload_sdo_fifo (
|
||||
.s_axis_aclk(clk),
|
||||
.s_axis_aresetn(up_sw_resetn),
|
||||
.s_axis_ready(),
|
||||
.s_axis_valid(up_offload0_sdo_wr_en_s),
|
||||
.s_axis_data(up_offload0_sdo_wr_data_s),
|
||||
.s_axis_room(),
|
||||
.s_axis_empty(),
|
||||
.m_axis_aclk(spi_clk),
|
||||
.m_axis_aresetn(spi_resetn),
|
||||
.m_axis_ready(1'b1),
|
||||
.m_axis_valid(offload0_sdo_wr_en),
|
||||
.m_axis_data(offload0_sdo_wr_data),
|
||||
.m_axis_level()
|
||||
);
|
||||
|
||||
assign up_offload0_sdo_wr_en_s = up_wreq_s == 1'b1 && up_waddr_s == 8'h45;
|
||||
assign up_offload0_sdo_wr_data_s = up_wdata_s[DATA_WIDTH-1:0];
|
||||
|
||||
// synchronization FIFO for the Offload SYNC interface
|
||||
util_axis_fifo #(
|
||||
.DATA_WIDTH(8),
|
||||
.ASYNC_CLK(ASYNC_SPI_CLK),
|
||||
.ADDRESS_WIDTH(SYNC_FIFO_ADDRESS_WIDTH),
|
||||
.S_AXIS_REGISTERED(0)
|
||||
) i_offload_sync_fifo (
|
||||
.s_axis_aclk(spi_clk),
|
||||
.s_axis_aresetn(spi_resetn),
|
||||
.s_axis_ready(offload_sync_ready),
|
||||
.s_axis_valid(offload_sync_valid),
|
||||
.s_axis_data(offload_sync_data),
|
||||
.s_axis_room(),
|
||||
.s_axis_empty(),
|
||||
.m_axis_aclk(clk),
|
||||
.m_axis_aresetn(up_sw_resetn),
|
||||
.m_axis_ready(1'b1),
|
||||
.m_axis_valid(offload_sync_fifo_valid),
|
||||
.m_axis_data(offload_sync_fifo_data),
|
||||
.m_axis_level()
|
||||
);
|
||||
|
||||
end else begin /* ASYNC_SPI_CLK == 0 */
|
||||
|
||||
assign sync_fifo_valid = sync_valid;
|
||||
assign sync_fifo_data = sync_data;
|
||||
assign sync_ready = 1'b1;
|
||||
|
||||
assign offload0_cmd_wr_en = up_wreq_s == 1'b1 && up_waddr_s == 8'h44;
|
||||
assign offload0_cmd_wr_data = up_wdata_s[15:0];
|
||||
|
||||
assign offload0_sdo_wr_en = up_wreq_s == 1'b1 && up_waddr_s == 8'h45;
|
||||
assign offload0_sdo_wr_data = up_wdata_s[DATA_WIDTH-1:0];
|
||||
|
||||
assign offload_sync_fifo_valid = offload_sync_valid;
|
||||
assign offload_sync_fifo_data = offload_sync_data;
|
||||
assign offload_sync_ready = 1'b1;
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
sync_bits #(
|
||||
.NUM_OF_BITS (1),
|
||||
.ASYNC_CLK (ASYNC_SPI_CLK)
|
||||
) i_offload_enable_sync (
|
||||
.in_bits (offload0_enable_reg),
|
||||
.out_resetn (spi_resetn),
|
||||
.out_clk (spi_clk),
|
||||
.out_bits (offload0_enable));
|
||||
|
||||
sync_bits #(
|
||||
.NUM_OF_BITS (1),
|
||||
.ASYNC_CLK (ASYNC_SPI_CLK)
|
||||
) i_offload_enabled_sync (
|
||||
.in_bits (offload0_enabled),
|
||||
.out_resetn (up_sw_resetn),
|
||||
.out_clk (clk),
|
||||
.out_bits (offload0_enabled_s));
|
||||
|
||||
sync_bits #(
|
||||
.NUM_OF_BITS (1),
|
||||
.ASYNC_CLK (ASYNC_SPI_CLK)
|
||||
) i_offload_mem_reset_sync (
|
||||
.in_bits (offload0_mem_reset_reg),
|
||||
.out_resetn (spi_resetn),
|
||||
.out_clk (spi_clk),
|
||||
.out_bits (offload0_mem_reset));
|
||||
|
||||
endmodule
|
||||
Reference in New Issue
Block a user