first commit after restructuring

projects/duifei/common_ipi-bd/basic_driver_bd/ipshared/cb53/sync_bits.v

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+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
+//
+// In this HDL repository, there are many different and unique modules, consisting
+// of various HDL (Verilog or VHDL) components. The individual modules are
+// developed independently, and may be accompanied by separate and unique license
+// terms.
+//
+// The user should read each of these license terms, and understand the
+// freedoms and responsibilities that he or she has by using this source/core.
+//
+// This core is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+// A PARTICULAR PURPOSE.
+//
+// Redistribution and use of source or resulting binaries, with or without modification
+// of this file, are permitted under one of the following two license terms:
+//
+//   1. The GNU General Public License version 2 as published by the
+//      Free Software Foundation, which can be found in the top level directory
+//      of this repository (LICENSE_GPL2), and also online at:
+//      <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
+//
+// OR
+//
+//   2. An ADI specific BSD license, which can be found in the top level directory
+//      of this repository (LICENSE_ADIBSD), and also on-line at:
+//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      This will allow to generate bit files and not release the source code,
+//      as long as it attaches to an ADI device.
+//
+// ***************************************************************************
+// ***************************************************************************
+
+/*
+ * Helper module for synchronizing bit signals from one clock domain to another.
+ * It uses the standard approach of 2 FF in series.
+ * Note, that while the module allows to synchronize multiple bits at once it is
+ * only able to synchronize multi-bit signals where at max one bit changes per
+ * clock cycle (e.g. a gray counter).
+ */
+
+`timescale 1ns/100ps
+
+module sync_bits #(
+
+  // Number of bits to synchronize
+  parameter NUM_OF_BITS = 1,
+  // Whether input and output clocks are asynchronous, if 0 the synchronizer will
+  // be bypassed and the output signal equals the input signal.
+  parameter ASYNC_CLK = 1)(
+
+  input [NUM_OF_BITS-1:0] in_bits,
+  input out_resetn,
+  input out_clk,
+  output [NUM_OF_BITS-1:0] out_bits);
+
+generate if (ASYNC_CLK == 1) begin
+  reg [NUM_OF_BITS-1:0] cdc_sync_stage1 = 'h0;
+  reg [NUM_OF_BITS-1:0] cdc_sync_stage2 = 'h0;
+
+  always @(posedge out_clk)
+  begin
+    if (out_resetn == 1'b0) begin
+      cdc_sync_stage1 <= 'b0;
+      cdc_sync_stage2 <= 'b0;
+    end else begin
+      cdc_sync_stage1 <= in_bits;
+      cdc_sync_stage2 <= cdc_sync_stage1;
+    end
+  end
+
+  assign out_bits = cdc_sync_stage2;
+end else begin
+  assign out_bits = in_bits;
+end endgenerate
+
+endmodule

projects/duifei/common_ipi-bd/basic_driver_bd/ipshared/cb53/sync_data.v

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+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
+//
+// In this HDL repository, there are many different and unique modules, consisting
+// of various HDL (Verilog or VHDL) components. The individual modules are
+// developed independently, and may be accompanied by separate and unique license
+// terms.
+//
+// The user should read each of these license terms, and understand the
+// freedoms and responsibilities that he or she has by using this source/core.
+//
+// This core is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+// A PARTICULAR PURPOSE.
+//
+// Redistribution and use of source or resulting binaries, with or without modification
+// of this file, are permitted under one of the following two license terms:
+//
+//   1. The GNU General Public License version 2 as published by the
+//      Free Software Foundation, which can be found in the top level directory
+//      of this repository (LICENSE_GPL2), and also online at:
+//      <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
+//
+// OR
+//
+//   2. An ADI specific BSD license, which can be found in the top level directory
+//      of this repository (LICENSE_ADIBSD), and also on-line at:
+//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      This will allow to generate bit files and not release the source code,
+//      as long as it attaches to an ADI device.
+//
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module sync_data #(
+  parameter NUM_OF_BITS = 1,
+  parameter ASYNC_CLK = 1
+) (
+  input in_clk,
+  input [NUM_OF_BITS-1:0] in_data,
+  input out_clk,
+  output reg [NUM_OF_BITS-1:0] out_data
+);
+
+generate
+if (ASYNC_CLK == 1) begin
+
+wire out_toggle;
+wire in_toggle;
+
+reg out_toggle_d1 = 1'b0;
+reg in_toggle_d1 = 1'b0;
+
+reg [NUM_OF_BITS-1:0] cdc_hold;
+
+sync_bits i_sync_out (
+  .in_bits(in_toggle_d1),
+  .out_clk(out_clk),
+  .out_resetn(1'b1),
+  .out_bits(out_toggle)
+);
+
+sync_bits i_sync_in (
+  .in_bits(out_toggle_d1),
+  .out_clk(in_clk),
+  .out_resetn(1'b1),
+  .out_bits(in_toggle)
+);
+
+wire in_load = in_toggle == in_toggle_d1;
+wire out_load = out_toggle ^ out_toggle_d1;
+
+always @(posedge in_clk) begin
+  if (in_load == 1'b1) begin
+    cdc_hold <= in_data;
+    in_toggle_d1 <= ~in_toggle_d1;
+  end
+end
+
+always @(posedge out_clk) begin
+  if (out_load == 1'b1) begin
+    out_data <= cdc_hold;
+  end
+  out_toggle_d1 <= out_toggle;
+end
+
+end else begin
+  always @(*) begin
+    out_data <= in_data;
+  end
+end
+endgenerate
+
+endmodule

projects/duifei/common_ipi-bd/basic_driver_bd/ipshared/cb53/sync_event.v

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+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
+//
+// In this HDL repository, there are many different and unique modules, consisting
+// of various HDL (Verilog or VHDL) components. The individual modules are
+// developed independently, and may be accompanied by separate and unique license
+// terms.
+//
+// The user should read each of these license terms, and understand the
+// freedoms and responsibilities that he or she has by using this source/core.
+//
+// This core is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+// A PARTICULAR PURPOSE.
+//
+// Redistribution and use of source or resulting binaries, with or without modification
+// of this file, are permitted under one of the following two license terms:
+//
+//   1. The GNU General Public License version 2 as published by the
+//      Free Software Foundation, which can be found in the top level directory
+//      of this repository (LICENSE_GPL2), and also online at:
+//      <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
+//
+// OR
+//
+//   2. An ADI specific BSD license, which can be found in the top level directory
+//      of this repository (LICENSE_ADIBSD), and also on-line at:
+//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      This will allow to generate bit files and not release the source code,
+//      as long as it attaches to an ADI device.
+//
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module sync_event #(
+  parameter NUM_OF_EVENTS = 1,
+  parameter ASYNC_CLK = 1
+) (
+  input in_clk,
+  input [NUM_OF_EVENTS-1:0] in_event,
+  input out_clk,
+  output reg [NUM_OF_EVENTS-1:0] out_event
+);
+
+generate
+if (ASYNC_CLK == 1) begin
+
+wire out_toggle;
+wire in_toggle;
+
+reg out_toggle_d1 = 1'b0;
+reg in_toggle_d1 = 1'b0;
+
+sync_bits i_sync_out (
+  .in_bits(in_toggle_d1),
+  .out_clk(out_clk),
+  .out_resetn(1'b1),
+  .out_bits(out_toggle)
+);
+
+sync_bits i_sync_in (
+  .in_bits(out_toggle_d1),
+  .out_clk(in_clk),
+  .out_resetn(1'b1),
+  .out_bits(in_toggle)
+);
+
+wire in_ready = in_toggle == in_toggle_d1;
+wire load_out = out_toggle ^ out_toggle_d1;
+
+reg [NUM_OF_EVENTS-1:0] in_event_sticky = 'h00;
+wire [NUM_OF_EVENTS-1:0] pending_events = in_event_sticky | in_event;
+wire [NUM_OF_EVENTS-1:0] out_event_s;
+
+always @(posedge in_clk) begin
+  if (in_ready == 1'b1) begin
+    in_event_sticky <= {NUM_OF_EVENTS{1'b0}};
+    if (|pending_events == 1'b1) begin
+      in_toggle_d1 <= ~in_toggle_d1;
+    end
+  end else begin
+    in_event_sticky <= pending_events;
+  end
+end
+
+if (NUM_OF_EVENTS > 1) begin
+  reg [NUM_OF_EVENTS-1:0] cdc_hold = 'h00;
+
+  always @(posedge in_clk) begin
+    if (in_ready == 1'b1) begin
+      cdc_hold <= pending_events;
+    end
+  end
+
+  assign out_event_s = cdc_hold;
+end else begin
+  // When there is only one event, we know that it is set.
+  assign out_event_s = 1'b1;
+end
+
+always @(posedge out_clk) begin
+  if (load_out == 1'b1) begin
+    out_event <= out_event_s;
+  end else begin
+    out_event <= {NUM_OF_EVENTS{1'b0}};
+  end
+  out_toggle_d1 <= out_toggle;
+end
+
+end else begin
+  always @(*) begin
+    out_event <= in_event;
+  end
+end
+endgenerate
+
+endmodule

projects/duifei/common_ipi-bd/basic_driver_bd/ipshared/cb53/sync_gray.v

@@ -0,0 +1,115 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
+//
+// In this HDL repository, there are many different and unique modules, consisting
+// of various HDL (Verilog or VHDL) components. The individual modules are
+// developed independently, and may be accompanied by separate and unique license
+// terms.
+//
+// The user should read each of these license terms, and understand the
+// freedoms and responsibilities that he or she has by using this source/core.
+//
+// This core is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+// A PARTICULAR PURPOSE.
+//
+// Redistribution and use of source or resulting binaries, with or without modification
+// of this file, are permitted under one of the following two license terms:
+//
+//   1. The GNU General Public License version 2 as published by the
+//      Free Software Foundation, which can be found in the top level directory
+//      of this repository (LICENSE_GPL2), and also online at:
+//      <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
+//
+// OR
+//
+//   2. An ADI specific BSD license, which can be found in the top level directory
+//      of this repository (LICENSE_ADIBSD), and also on-line at:
+//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      This will allow to generate bit files and not release the source code,
+//      as long as it attaches to an ADI device.
+//
+// ***************************************************************************
+// ***************************************************************************
+
+/*
+ * Helper module for synchronizing a counter from one clock domain to another
+ * using gray code. To work correctly the counter must not change its value by
+ * more than one in one clock cycle in the source domain. I.e. the value may
+ * change by either -1, 0 or +1.
+ */
+
+`timescale 1ns/100ps
+
+module sync_gray #(
+
+  // Bit-width of the counter
+  parameter DATA_WIDTH = 1,
+  // Whether the input and output clock are asynchronous, if set to 0 the
+  // synchronizer will be bypassed and out_count will be in_count.
+  parameter ASYNC_CLK = 1)(
+
+  input in_clk,
+  input in_resetn,
+  input [DATA_WIDTH-1:0] in_count,
+  input out_resetn,
+  input out_clk,
+  output [DATA_WIDTH-1:0] out_count);
+
+generate if (ASYNC_CLK == 1) begin
+  reg [DATA_WIDTH-1:0] cdc_sync_stage0 = 'h0;
+  reg [DATA_WIDTH-1:0] cdc_sync_stage1 = 'h0;
+  reg [DATA_WIDTH-1:0] cdc_sync_stage2 = 'h0;
+  reg [DATA_WIDTH-1:0] out_count_m = 'h0;
+
+  function [DATA_WIDTH-1:0] g2b;
+    input [DATA_WIDTH-1:0] g;
+    reg   [DATA_WIDTH-1:0] b;
+    integer i;
+    begin
+      b[DATA_WIDTH-1] = g[DATA_WIDTH-1];
+      for (i = DATA_WIDTH - 2; i >= 0; i =  i - 1)
+        b[i] = b[i + 1] ^ g[i];
+      g2b = b;
+    end
+  endfunction
+
+  function [DATA_WIDTH-1:0] b2g;
+    input [DATA_WIDTH-1:0] b;
+    reg [DATA_WIDTH-1:0] g;
+    integer i;
+    begin
+      g[DATA_WIDTH-1] = b[DATA_WIDTH-1];
+      for (i = DATA_WIDTH - 2; i >= 0; i = i -1)
+          g[i] = b[i + 1] ^ b[i];
+      b2g = g;
+    end
+  endfunction
+
+  always @(posedge in_clk) begin
+    if (in_resetn == 1'b0) begin
+      cdc_sync_stage0 <= 'h00;
+    end else begin
+      cdc_sync_stage0 <= b2g(in_count);
+    end
+  end
+
+  always @(posedge out_clk) begin
+    if (out_resetn == 1'b0) begin
+      cdc_sync_stage1 <= 'h00;
+      cdc_sync_stage2 <= 'h00;
+      out_count_m <= 'h00;
+    end else begin
+      cdc_sync_stage1 <= cdc_sync_stage0;
+      cdc_sync_stage2 <= cdc_sync_stage1;
+      out_count_m <= g2b(cdc_sync_stage2);
+    end
+  end
+
+  assign out_count = out_count_m;
+end else begin
+  assign out_count = in_count;
+end endgenerate
+
+endmodule