Archived
first commit after restructuring
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################################################################################
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########################### Single Project Specific ############################
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################################################################################
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# ------------------------------------------------------------------------------
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# ------------------------------ Vivado Specific -------------------------------
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# ------------------------------------------------------------------------------
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# exclude everything in project directory
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project/**
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# include hardware manager projects and sources
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# 1. include `.hw` directory
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# 2. include everything in `.hw` directory
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!project/*.hw/
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!project/*.hw/**
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# include design run results
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# 1. include `*.runs` directory
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# 2. exclude everything in `.runs` directory
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# 3. include `.impl_*` directory
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# 4. include `*.bit` file in `.impl_*` directory
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# 5. include `*.ltx` file in `.impl_*` directory
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!/project/*.runs/
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/project/*.runs/**
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!/project/*.runs/impl_*/
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!/project/*.runs/impl_*/*.bit
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!/project/*.runs/impl_*/*.ltx
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# ------------------------------------------------------------------------------
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# -------------------------------- SDK Specific --------------------------------
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# ------------------------------------------------------------------------------
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# include sdk directory and everything in it
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!/project/*.sdk/
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!/project/*.sdk/**
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/project/*.sdk/**.log
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# exclude some obscure hidden SDK folders
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||||
/project/*.sdk/.metadata/
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/project/*.sdk/.sdk/
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/project/*.sdk/RemoteSystemsTempFiles/
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/project/*.sdk/webtalk/
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# hw_platform: exclude the entire hw_platform folder, as everything can be
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||||
# generated from the .hdf file. Make sure to include the bitstream in the .hdf
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||||
# file when exporting from Vivado!
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||||
/project/*.sdk/*_hw_platform_*/
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# BSP: only keep `.cproject`, `.project`, `.sdkproject`, `.system.mss` and
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# Makefile, ps lib files are regenerated automatically
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/project/*.sdk/*_bsp/*
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!/project/*.sdk/*_bsp/*.cproject
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||||
!/project/*.sdk/*_bsp/*.project
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||||
!/project/*.sdk/*_bsp/*.sdkproject
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||||
!/project/*.sdk/*_bsp/system.mss
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||||
!/project/*.sdk/*_bsp/Makefile
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||||
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||||
# Application: ignored file patterns, exclude Debug & Release folders
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/project/*.sdk/**/*.o
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/project/*.sdk/**/*.d
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/project/*.sdk/**/*.a
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/project/*.sdk/*/Debug/
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/project/*.sdk/*/Release/
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||||
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||||
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################################################################################
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||||
# ############################ Multi Project Specific ############################
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||||
# ################################################################################
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||||
|
||||
# # ------------------------------------------------------------------------------
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||||
# # ------------------------------ Vivado Specific -------------------------------
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||||
# # ------------------------------------------------------------------------------
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||||
|
||||
# # exclude everything in project directory expect for top level directory
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# project/**
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||||
# !/project/*/
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||||
|
||||
# # include hardware manager projects and sources
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||||
# # 1. include `.hw` directory
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||||
# # 2. include everything in `.hw` directory
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||||
# !project/*/*.hw/
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# !project/*/*.hw/**
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||||
|
||||
# # include design run results
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||||
# # 1. include `*.runs` directory
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||||
# # 2. exclude everything in `.runs` directory
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||||
# # 3. include `.impl_*` directory
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||||
# # 4. include `*.bit` file in `.impl_*` directory
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# # 5. include `*.ltx` file in `.impl_*` directory
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||||
# !/project/*/*.runs/
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# /project/*/*.runs/**
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# !/project/*/*.runs/impl_*/
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# !/project/*/*.runs/impl_*/*.bit
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# !/project/*/*.runs/impl_*/*.ltx
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||||
|
||||
# # ------------------------------------------------------------------------------
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||||
# # -------------------------------- SDK Specific --------------------------------
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||||
# # ------------------------------------------------------------------------------
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||||
|
||||
# # include sdk directory and everything in it
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||||
# !/project/*/*.sdk/
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||||
# !/project/*/*.sdk/**
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||||
# /project/*/*.sdk/**.log
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||||
|
||||
# # exclude some obscure hidden SDK folders
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||||
# /project/*/*.sdk/.metadata/
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# /project/*/*.sdk/.sdk/
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||||
# /project/*/*.sdk/RemoteSystemsTempFiles/
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||||
# /project/*/*.sdk/webtalk/
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||||
|
||||
# # hw_platform: exclude the entire hw_platform folder, as everything can be
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||||
# # generated from the .hdf file. Make sure to include the bitstream in the .hdf
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||||
# # file when exporting from Vivado!
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||||
# /project/*/*.sdk/*_hw_platform_*/
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||||
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||||
# # BSP: only keep `.cproject`, `.project`, `.sdkproject`, `.system.mss` and
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||||
# # Makefile, ps lib files are regenerated automatically
|
||||
# /project/*/*.sdk/*_bsp/*
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||||
# !/project/*/*.sdk/*_bsp/*.cproject
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# !/project/*/*.sdk/*_bsp/*.project
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||||
# !/project/*/*.sdk/*_bsp/*.sdkproject
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||||
# !/project/*/*.sdk/*_bsp/system.mss
|
||||
# !/project/*/*.sdk/*_bsp/Makefile
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||||
|
||||
# # Application: ignored file patterns, exclude Debug & Release folders
|
||||
# /project/*/*.sdk/**/*.o
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||||
# /project/*/*.sdk/**/*.d
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||||
# /project/*/*.sdk/**/*.a
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# /project/*/*.sdk/*/Debug/
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# /project/*/*.sdk/*/Release/
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@@ -0,0 +1,194 @@
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# df_z7100_2ad9361
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## Timing Assertions Section
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## Physical Constraints Section
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# Clocks
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set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVDS } [get_ports clk_250m_p ] ;# FPGA_DAC_LOGIC_CLK_C_P
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set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVCMOS18} [get_ports ad9361_1_buffer_clk ] ;# AD9361_CLK_OUT
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set_property -dict {PACKAGE_PIN F4 IOSTANDARD LVCMOS18} [get_ports ad9361_2_buffer_clk ] ;# B_AD9361_CLK_OUT
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# HMC7044-1 Interface
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set_property -dict {PACKAGE_PIN AD13 IOSTANDARD LVCMOS33} [get_ports hmc7044_spi_clk ] ;# HMC7044_1_SCLK
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set_property -dict {PACKAGE_PIN AD14 IOSTANDARD LVCMOS33} [get_ports hmc7044_spi_csn ] ;# HMC7044_1_SLEN
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set_property -dict {PACKAGE_PIN AG12 IOSTANDARD LVCMOS33} [get_ports hmc7044_spi_sdio ] ;# HMC7044_1_DATA
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set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVCMOS33} [get_ports hmc7044_reset ] ;# HMC7044_1_RESET
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set_property -dict {PACKAGE_PIN AF13 IOSTANDARD LVCMOS33} [get_ports hmc7044_sync ] ;# HMC7044_1_SYNC
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set_property -dict {PACKAGE_PIN AH16 IOSTANDARD LVCMOS33} [get_ports hmc7044_gpio[0] ] ;# HMC7044_1_GPIO1
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set_property -dict {PACKAGE_PIN AE12 IOSTANDARD LVCMOS33} [get_ports hmc7044_gpio[1] ] ;# HMC7044_1_GPIO2
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set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVCMOS33} [get_ports hmc7044_gpio[2] ] ;# HMC7044_1_GPIO3
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set_property -dict {PACKAGE_PIN AH14 IOSTANDARD LVCMOS33} [get_ports hmc7044_gpio[3] ] ;# HMC7044_1_GPIO4
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# AD9361-1 Interface
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set_property -dict {PACKAGE_PIN F5 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data_clk ] ;# AD9361_DATA_CLK_P
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set_property -dict {PACKAGE_PIN J1 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_frame ] ;# AD9361_RX_FRAME_P
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set_property -dict {PACKAGE_PIN B1 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[0] ] ;# AD9361_TX_00_D0_N
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set_property -dict {PACKAGE_PIN B2 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[1] ] ;# AD9361_TX_01_D0_P
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set_property -dict {PACKAGE_PIN C3 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[2] ] ;# AD9361_TX_02_D1_N
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set_property -dict {PACKAGE_PIN C4 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[3] ] ;# AD9361_TX_03_D1_P
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set_property -dict {PACKAGE_PIN B11 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[4] ] ;# AD9361_TX_04_D2_N
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set_property -dict {PACKAGE_PIN C11 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[5] ] ;# AD9361_TX_05_D2_P
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set_property -dict {PACKAGE_PIN B4 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[6] ] ;# AD9361_TX_06_D3_N
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set_property -dict {PACKAGE_PIN B5 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[7] ] ;# AD9361_TX_07_D3_P
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set_property -dict {PACKAGE_PIN A9 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[8] ] ;# AD9361_TX_08_D4_N
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set_property -dict {PACKAGE_PIN B9 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[9] ] ;# AD9361_TX_09_D4_P
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set_property -dict {PACKAGE_PIN B6 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[10] ] ;# AD9361_TX_10_D5_N
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set_property -dict {PACKAGE_PIN C6 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[11] ] ;# AD9361_TX_11_D5_P
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set_property -dict {PACKAGE_PIN E13 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_fb_clk ] ;# AD9361_FB_CLK_P
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set_property -dict {PACKAGE_PIN C12 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_frame ] ;# AD9361_TX_FRAME_P
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set_property -dict {PACKAGE_PIN A2 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[0] ] ;# AD9361_RX_00_D0_N
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set_property -dict {PACKAGE_PIN A3 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[1] ] ;# AD9361_RX_01_D0_P
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set_property -dict {PACKAGE_PIN A4 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[2] ] ;# AD9361_RX_02_D1_N
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set_property -dict {PACKAGE_PIN A5 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[3] ] ;# AD9361_RX_03_D1_P
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set_property -dict {PACKAGE_PIN B7 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[4] ] ;# AD9361_RX_04_D2_N
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set_property -dict {PACKAGE_PIN C7 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[5] ] ;# AD9361_RX_05_D2_P
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set_property -dict {PACKAGE_PIN A10 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[6] ] ;# AD9361_RX_06_D3_N
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set_property -dict {PACKAGE_PIN B10 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[7] ] ;# AD9361_RX_07_D3_P
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set_property -dict {PACKAGE_PIN A7 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[8] ] ;# AD9361_RX_08_D4_N
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set_property -dict {PACKAGE_PIN A8 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[9] ] ;# AD9361_RX_09_D4_P
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set_property -dict {PACKAGE_PIN C8 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[10] ] ;# AD9361_RX_10_D5_N
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set_property -dict {PACKAGE_PIN C9 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[11] ] ;# AD9361_RX_11_D5_P
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set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVCMOS18} [get_ports ad9361_1_spi_clk ] ;# AD9361_SPI_CLK
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set_property -dict {PACKAGE_PIN A15 IOSTANDARD LVCMOS18} [get_ports ad9361_1_spi_csn ] ;# AD9361_SPI_ENB
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set_property -dict {PACKAGE_PIN H13 IOSTANDARD LVCMOS18} [get_ports ad9361_1_spi_mosi ] ;# AD9361_SPI_DI
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set_property -dict {PACKAGE_PIN D14 IOSTANDARD LVCMOS18} [get_ports ad9361_1_spi_miso ] ;# AD9361_SPI_DO
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set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS18} [get_ports ad9361_1_reset_b ] ;# AD9361_RESETB
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set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVCMOS18} [get_ports ad9361_1_en_agc ] ;# AD9361_EN_AGC
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set_property -dict {PACKAGE_PIN C13 IOSTANDARD LVCMOS18} [get_ports ad9361_1_enable ] ;# AD9361_ENABLE
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set_property -dict {PACKAGE_PIN A12 IOSTANDARD LVCMOS18} [get_ports ad9361_1_txnrx ] ;# AD9361_TXNRX
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set_property -dict {PACKAGE_PIN C14 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_in[0] ] ;# AD9361_CTRL_IN0
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set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_in[1] ] ;# AD9361_CTRL_IN1
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set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_in[2] ] ;# AD9361_CTRL_IN2
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set_property -dict {PACKAGE_PIN B14 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_in[3] ] ;# AD9361_CTRL_IN3
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set_property -dict {PACKAGE_PIN D16 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[0] ] ;# AD9361_CTRL_OUT0
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set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[1] ] ;# AD9361_CTRL_OUT1
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set_property -dict {PACKAGE_PIN A14 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[2] ] ;# AD9361_CTRL_OUT2
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set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[3] ] ;# AD9361_CTRL_OUT3
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set_property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[4] ] ;# AD9361_CTRL_OUT4
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set_property -dict {PACKAGE_PIN B16 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[5] ] ;# AD9361_CTRL_OUT5
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set_property -dict {PACKAGE_PIN B15 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[6] ] ;# AD9361_CTRL_OUT6
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set_property -dict {PACKAGE_PIN M12 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[7] ] ;# AD9361_CTRL_OUT7
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set_property -dict {PACKAGE_PIN F9 IOSTANDARD LVCMOS18} [get_ports ad9361_sync ] ;# AD9361_SYNC_IN
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# AD9361-2 Interface
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set_property -dict {PACKAGE_PIN G5 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data_clk ] ;# B_AD9361_DATA_CLK_P
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set_property -dict {PACKAGE_PIN E1 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_frame ] ;# B_AD9361_RX_FRAME_P
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set_property -dict {PACKAGE_PIN D5 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[0] ] ;# B_AD9361_TX_00_D0_N
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set_property -dict {PACKAGE_PIN E6 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[1] ] ;# B_AD9361_TX_01_D0_P
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set_property -dict {PACKAGE_PIN H3 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[2] ] ;# B_AD9361_TX_02_D1_N
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set_property -dict {PACKAGE_PIN H4 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[3] ] ;# B_AD9361_TX_03_D1_P
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set_property -dict {PACKAGE_PIN J6 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[4] ] ;# B_AD9361_TX_04_D2_N
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set_property -dict {PACKAGE_PIN K6 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[5] ] ;# B_AD9361_TX_05_D2_P
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||||
set_property -dict {PACKAGE_PIN J5 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[6] ] ;# B_AD9361_TX_06_D3_N
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||||
set_property -dict {PACKAGE_PIN K5 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[7] ] ;# B_AD9361_TX_07_D3_P
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||||
set_property -dict {PACKAGE_PIN L2 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[8] ] ;# B_AD9361_TX_08_D4_N
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||||
set_property -dict {PACKAGE_PIN L3 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[9] ] ;# B_AD9361_TX_09_D4_P
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||||
set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[10] ] ;# B_AD9361_TX_10_D5_N
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||||
set_property -dict {PACKAGE_PIN K3 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[11] ] ;# B_AD9361_TX_11_D5_P
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||||
|
||||
set_property -dict {PACKAGE_PIN G10 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_fb_clk ] ;# B_AD9361_FB_CLK_P
|
||||
set_property -dict {PACKAGE_PIN H6 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_frame ] ;# B_AD9361_TX_FRAME_P
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||||
set_property -dict {PACKAGE_PIN E2 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[0] ] ;# B_AD9361_RX_00_D0_N
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||||
set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[1] ] ;# B_AD9361_RX_01_D0_P
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||||
set_property -dict {PACKAGE_PIN F2 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[2] ] ;# B_AD9361_RX_02_D1_N
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||||
set_property -dict {PACKAGE_PIN G2 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[3] ] ;# B_AD9361_RX_03_D1_P
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||||
set_property -dict {PACKAGE_PIN J3 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[4] ] ;# B_AD9361_RX_04_D2_N
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||||
set_property -dict {PACKAGE_PIN J4 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[5] ] ;# B_AD9361_RX_05_D2_P
|
||||
set_property -dict {PACKAGE_PIN H16 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[6] ] ;# B_AD9361_RX_06_D3_N
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||||
set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[7] ] ;# B_AD9361_RX_07_D3_P
|
||||
set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[8] ] ;# B_AD9361_RX_08_D4_N
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||||
set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[9] ] ;# B_AD9361_RX_09_D4_P
|
||||
set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[10] ] ;# B_AD9361_RX_10_D5_N
|
||||
set_property -dict {PACKAGE_PIN L13 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[11] ] ;# B_AD9361_RX_11_D5_P
|
||||
|
||||
set_property -dict {PACKAGE_PIN L9 IOSTANDARD LVCMOS18} [get_ports ad9361_2_spi_clk ] ;# B_AD9361_SPI_CLK
|
||||
set_property -dict {PACKAGE_PIN M10 IOSTANDARD LVCMOS18} [get_ports ad9361_2_spi_csn ] ;# B_AD9361_SPI_ENB
|
||||
set_property -dict {PACKAGE_PIN L12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_spi_mosi ] ;# B_AD9361_SPI_DI
|
||||
set_property -dict {PACKAGE_PIN K12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_spi_miso ] ;# B_AD9361_SPI_DO
|
||||
|
||||
set_property -dict {PACKAGE_PIN J10 IOSTANDARD LVCMOS18} [get_ports ad9361_2_reset_b ] ;# B_AD9361_RESETB
|
||||
set_property -dict {PACKAGE_PIN D4 IOSTANDARD LVCMOS18} [get_ports ad9361_2_en_agc ] ;# B_AD9361_EN_AGC
|
||||
set_property -dict {PACKAGE_PIN D3 IOSTANDARD LVCMOS18} [get_ports ad9361_2_enable ] ;# B_AD9361_ENABLE
|
||||
set_property -dict {PACKAGE_PIN J9 IOSTANDARD LVCMOS18} [get_ports ad9361_2_txnrx ] ;# B_AD9361_TXNRX
|
||||
|
||||
set_property -dict {PACKAGE_PIN L10 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_in[0] ] ;# B_AD9361_CTRL_IN0
|
||||
set_property -dict {PACKAGE_PIN D6 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_in[1] ] ;# B_AD9361_CTRL_IN1
|
||||
set_property -dict {PACKAGE_PIN E7 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_in[2] ] ;# B_AD9361_CTRL_IN2
|
||||
set_property -dict {PACKAGE_PIN K8 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_in[3] ] ;# B_AD9361_CTRL_IN3
|
||||
|
||||
set_property -dict {PACKAGE_PIN H11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[0] ] ;# B_AD9361_CTRL_OUT0
|
||||
set_property -dict {PACKAGE_PIN J11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[1] ] ;# B_AD9361_CTRL_OUT1
|
||||
set_property -dict {PACKAGE_PIN K7 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[2] ] ;# B_AD9361_CTRL_OUT2
|
||||
set_property -dict {PACKAGE_PIN L7 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[3] ] ;# B_AD9361_CTRL_OUT3
|
||||
set_property -dict {PACKAGE_PIN G7 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[4] ] ;# B_AD9361_CTRL_OUT4
|
||||
set_property -dict {PACKAGE_PIN H7 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[5] ] ;# B_AD9361_CTRL_OUT5
|
||||
set_property -dict {PACKAGE_PIN K10 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[6] ] ;# B_AD9361_CTRL_OUT6
|
||||
set_property -dict {PACKAGE_PIN K11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[7] ] ;# B_AD9361_CTRL_OUT7
|
||||
|
||||
# Phased-Array Control
|
||||
set_property -dict {PACKAGE_PIN AC28 IOSTANDARD LVTTL } [get_ports ant_clk ] ;# ANT_CLK
|
||||
set_property -dict {PACKAGE_PIN AD25 IOSTANDARD LVTTL } [get_ports ant_en ] ;# ANT_EN
|
||||
set_property -dict {PACKAGE_PIN AD29 IOSTANDARD LVTTL } [get_ports ant_data ] ;# ANT_DATA
|
||||
set_property -dict {PACKAGE_PIN AE26 IOSTANDARD LVTTL } [get_ports ant_tr ] ;# ANT_TR
|
||||
set_property -dict {PACKAGE_PIN AB27 IOSTANDARD LVTTL } [get_ports ant_dary ] ;# ANT_DARY
|
||||
set_property -dict {PACKAGE_PIN AC27 IOSTANDARD LVTTL } [get_ports ant_dout ] ;# ANT_DOUT
|
||||
|
||||
# RF Synthesizer Control
|
||||
set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS33} [get_ports rf_standby ] ;# ANT_standby_R
|
||||
set_property -dict {PACKAGE_PIN R22 IOSTANDARD LVCMOS33} [get_ports rf_sw_pll ] ;# ANT_SW_PLL_R
|
||||
set_property -dict {PACKAGE_PIN T23 IOSTANDARD LVCMOS33} [get_ports rf_t ] ;# ANT_T_R
|
||||
set_property -dict {PACKAGE_PIN U25 IOSTANDARD LVCMOS33} [get_ports rf_r ] ;# ANT_R_R
|
||||
set_property -dict {PACKAGE_PIN T25 IOSTANDARD LVCMOS33} [get_ports rf_sw_bpf ] ;# ANT_SW_BPF_R
|
||||
set_property -dict {PACKAGE_PIN R25 IOSTANDARD LVCMOS33} [get_ports rf_sclk1 ] ;# ANT_SCLK1_R
|
||||
set_property -dict {PACKAGE_PIN T27 IOSTANDARD LVCMOS33} [get_ports rf_sdio1 ] ;# ANT_SDIO1_R
|
||||
set_property -dict {PACKAGE_PIN R28 IOSTANDARD LVCMOS33} [get_ports rf_cs1 ] ;# ANT_CS1_R
|
||||
set_property -dict {PACKAGE_PIN T28 IOSTANDARD LVCMOS33} [get_ports rf_ld1 ] ;# ANT_LD1_R
|
||||
set_property -dict {PACKAGE_PIN U26 IOSTANDARD LVCMOS33} [get_ports rf_sclk2 ] ;# ANT_SCLK2_R
|
||||
set_property -dict {PACKAGE_PIN V29 IOSTANDARD LVCMOS33} [get_ports rf_sdio2 ] ;# ANT_SDIO2_R
|
||||
set_property -dict {PACKAGE_PIN W29 IOSTANDARD LVCMOS33} [get_ports rf_cs2 ] ;# ANT_CS2_R
|
||||
set_property -dict {PACKAGE_PIN W30 IOSTANDARD LVCMOS33} [get_ports rf_ld2 ] ;# ANT_LD2_R
|
||||
set_property -dict {PACKAGE_PIN AE28 IOSTANDARD LVCMOS33} [get_ports rf_sclk3 ] ;# ANT_SCLK3_R
|
||||
set_property -dict {PACKAGE_PIN N29 IOSTANDARD LVCMOS33} [get_ports rf_sdio3 ] ;# ANT_SDIO3_R
|
||||
set_property -dict {PACKAGE_PIN AH28 IOSTANDARD LVCMOS33} [get_ports rf_cs3 ] ;# ANT_CS3_R
|
||||
set_property -dict {PACKAGE_PIN AJ30 IOSTANDARD LVCMOS33} [get_ports rf_ld3 ] ;# ANT_LD3_R
|
||||
set_property -dict {PACKAGE_PIN AJ28 IOSTANDARD LVCMOS33} [get_ports rf_tmgc_16 ] ;# ANT_TMGC_16_R
|
||||
set_property -dict {PACKAGE_PIN AH29 IOSTANDARD LVCMOS33} [get_ports rf_tmgc_8 ] ;# ANT_TMGC_8_R
|
||||
set_property -dict {PACKAGE_PIN AF27 IOSTANDARD LVCMOS33} [get_ports rf_tmgc_4 ] ;# ANT_TMGC_4_R
|
||||
set_property -dict {PACKAGE_PIN AG29 IOSTANDARD LVCMOS33} [get_ports rf_tmgc_2 ] ;# ANT_TMGC_2_R
|
||||
set_property -dict {PACKAGE_PIN AE27 IOSTANDARD LVCMOS33} [get_ports rf_tmgc_1 ] ;# ANT_TMGC_1_R
|
||||
set_property -dict {PACKAGE_PIN AG30 IOSTANDARD LVCMOS33} [get_ports rf_rmgc_16 ] ;# ANT_RMGC_16_R
|
||||
set_property -dict {PACKAGE_PIN AF28 IOSTANDARD LVCMOS33} [get_ports rf_rmgc_8 ] ;# ANT_RMGC_8_R
|
||||
set_property -dict {PACKAGE_PIN AG27 IOSTANDARD LVCMOS33} [get_ports rf_rmgc_4 ] ;# ANT_RMGC_4_R
|
||||
set_property -dict {PACKAGE_PIN AD28 IOSTANDARD LVCMOS33} [get_ports rf_rmgc_2 ] ;# ANT_RMGC_2_R
|
||||
set_property -dict {PACKAGE_PIN AK28 IOSTANDARD LVCMOS33} [get_ports rf_rmgc_1 ] ;# ANT_RMGC_1_R
|
||||
set_property -dict {PACKAGE_PIN AK27 IOSTANDARD LVCMOS33} [get_ports rf_enable ] ;# ANT_ENABLE_R
|
||||
set_property -dict {PACKAGE_PIN AH26 IOSTANDARD LVCMOS33} [get_ports rf_sc ] ;# ANT_SC_R
|
||||
set_property -dict {PACKAGE_PIN AG26 IOSTANDARD LVCMOS33} [get_ports rf_sd ] ;# ANT_SD_R
|
||||
set_property -dict {PACKAGE_PIN AE25 IOSTANDARD LVCMOS33} [get_ports rf_endsyn ] ;# ANT_END/SYN_R
|
||||
set_property -dict {PACKAGE_PIN AF25 IOSTANDARD LVCMOS33} [get_ports rf_sdout ] ;# ANT_SDOUT_R
|
||||
set_property -dict {PACKAGE_PIN AK30 IOSTANDARD LVCMOS33} [get_ports rf_dq_wd ] ;# ANT_DQ-WD_R 15
|
||||
set_property -dict {PACKAGE_PIN AJ29 IOSTANDARD LVCMOS33} [get_ports rf_sw_rx ] ;# ANT_SW_RX_R
|
||||
|
||||
# Debug IO
|
||||
set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVCMOS33} [get_ports uart1_txd ] ;# UART1_TXD
|
||||
set_property -dict {PACKAGE_PIN AA20 IOSTANDARD LVCMOS33} [get_ports uart1_rxd ] ;# UART1_RXD
|
||||
set_property -dict {PACKAGE_PIN AC18 IOSTANDARD LVCMOS33} [get_ports uart2_txd ] ;# UART2_TXD
|
||||
set_property -dict {PACKAGE_PIN AC19 IOSTANDARD LVCMOS33} [get_ports uart2_rxd ] ;# UART2_RXD
|
||||
set_property -dict {PACKAGE_PIN AD18 IOSTANDARD LVCMOS33} [get_ports uart3_txd ] ;# UART3_TXD
|
||||
set_property -dict {PACKAGE_PIN AD19 IOSTANDARD LVCMOS33} [get_ports uart3_rxd ] ;# UART3_RXD
|
||||
set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVCMOS18} [get_ports debug_io_1 ] ;# DEBUG_IO_1
|
||||
set_property -dict {PACKAGE_PIN K16 IOSTANDARD LVCMOS18} [get_ports debug_io_2 ] ;# DEBUG_IO_2
|
||||
set_property -dict {PACKAGE_PIN AG16 IOSTANDARD LVCMOS33} [get_ports debug_io_3 ] ;# DEBUG_IO_3
|
||||
set_property -dict {PACKAGE_PIN AF15 IOSTANDARD LVCMOS33} [get_ports debug_io_4 ] ;# DEBUG_IO_4
|
||||
set_property -dict {PACKAGE_PIN AG15 IOSTANDARD LVCMOS33} [get_ports debug_io_5 ] ;# DEBUG_IO_5
|
||||
set_property -dict {PACKAGE_PIN AF18 IOSTANDARD LVCMOS33} [get_ports debug_io_6 ] ;# DEBUG_IO_6
|
||||
set_property -dict {PACKAGE_PIN AG17 IOSTANDARD LVCMOS33} [get_ports debug_io_7 ] ;# DEBUG_IO_7
|
||||
@@ -0,0 +1 @@
|
||||
set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets u_clk_dist/u_ad9361_2_clk_gen/inst/clk_in1_ad9361_clk_gen_cmos_2t2r]
|
||||
BIN
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|
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|
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|
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|
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|
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|
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|
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|
@@ -0,0 +1,44 @@
|
||||
close all;
|
||||
|
||||
% 4 ch
|
||||
fileNameList = [...
|
||||
"iladata_duifei_1t2r_48msps_bw15m_trx_ext_lo_noise_1-1.csv",...
|
||||
"iladata_duifei_1t2r_48msps_bw15m_trx_ext_lo_noise_1-2.csv",...
|
||||
"iladata_duifei_1t2r_48msps_bw15m_trx_ext_lo_noise_1-3.csv",...
|
||||
"iladata_duifei_1t2r_48msps_bw15m_trx_ext_lo_noise_2-1.csv",...
|
||||
"iladata_duifei_1t2r_48msps_bw15m_trx_ext_lo_noise_2-2.csv",...
|
||||
"iladata_duifei_1t2r_48msps_bw15m_trx_ext_lo_noise_2-3.csv",...
|
||||
"iladata_duifei_1t2r_48msps_bw15m_trx_ext_lo_noise_3-1.csv",...
|
||||
"iladata_duifei_1t2r_48msps_bw15m_trx_ext_lo_noise_3-2.csv",...
|
||||
"iladata_duifei_1t2r_48msps_bw15m_trx_ext_lo_noise_3-3.csv"
|
||||
];
|
||||
|
||||
[~,fileNum] = size(fileNameList);
|
||||
|
||||
maxList = strings(fileNum+1,5);
|
||||
stdList = strings(fileNum+1,5);
|
||||
|
||||
maxList(1,:) = ["Max Value", "ch1", "ch2", "ch3", "ch4"];
|
||||
maxList(2:end,1) = fileNameList;
|
||||
stdList(1,:) = ["Std Value", "ch1", "ch2", "ch3", "ch4"];
|
||||
stdList(2:end,1) = fileNameList;
|
||||
|
||||
for i = 1:fileNum
|
||||
rxRaw = readmatrix(fileNameList(:,i));
|
||||
[rowNum,colNum] = size(rxRaw);
|
||||
|
||||
if (colNum == 11)
|
||||
rx = [rxRaw(:, 4)+1i*rxRaw(:, 5),rxRaw(:, 6)+1i*rxRaw(:, 7),...
|
||||
rxRaw(:, 8)+1i*rxRaw(:, 9),rxRaw(:,10)+1i*rxRaw(:,11)];
|
||||
elseif (colNum == 7)
|
||||
rx = [rxRaw(:, 4)+1i*rxRaw(:, 5),rxRaw(:, 6)+1i*rxRaw(:, 7),...
|
||||
zeros(rowNum,1),zeros(rowNum,1)];
|
||||
else
|
||||
disp('Invalid Data Format.')
|
||||
return
|
||||
end
|
||||
|
||||
maxList(i+1,2:end) = string(max(rx));
|
||||
stdList(i+1,2:end) = string(std(rx));
|
||||
|
||||
end
|
||||
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|
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|
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|
+86
@@ -0,0 +1,86 @@
|
||||
%% File Header/文件说明
|
||||
%
|
||||
% Beamforming with phased array derives signal characteristics from phase
|
||||
% differences between sensors. Therefore the amplitude-phase consistence is
|
||||
% vital to phased systems.
|
||||
%
|
||||
% The script analyzes the amp-phase relations of ILA captured data, the format
|
||||
% of which is square-shaped pseudorandorm bit sequence. Each channel is
|
||||
% processed seperately with different frequency shifts and different optimum
|
||||
% sampling points. The estimation of amplitude and phase are based on
|
||||
% acculumated correlation peaks.
|
||||
%
|
||||
clc; clear;
|
||||
%% initial parameters/初始参数
|
||||
interp = 8; % interpolation factor
|
||||
channelNum = 4;
|
||||
dataLen = 131072;
|
||||
fs = 48e6;
|
||||
dataFile = "iladata_duifei_1t2r_48msps_bw15m_rx_ext_lo_bpsk_2-1.csv";
|
||||
|
||||
% standard pn sequence
|
||||
pnSequence = comm.PNSequence('Polynomial','x^7+x^6+1', ...
|
||||
'InitialConditions',[zeros(1,6),1],'SamplesPerFrame',2^7-1);
|
||||
PRBS7 = pnSequence();
|
||||
PRBS7_polar = 1-2*[PRBS7;0];
|
||||
|
||||
chipLen = length(PRBS7_polar); % pn chip length
|
||||
symNum = dataLen/chipLen/interp; % total symbol number
|
||||
symNumPerAccum = 1; % symbol nbumber of each accumulation
|
||||
accNum = symNum/symNumPerAccum; % total accumulation numbers, i.e. peak numbers
|
||||
|
||||
%% data analysis
|
||||
|
||||
% read data, and swap ch1 and ch2, because loop data locate at ch2 and ch4
|
||||
rxdata = readmatrix(dataFile);
|
||||
seqRx(:,1) = (rxdata(:, 6) + 1i*rxdata(:, 7)).';
|
||||
seqRx(:,2) = (rxdata(:, 4) + 1i*rxdata(:, 5)).';
|
||||
seqRx(:,3) = (rxdata(:, 8) + 1i*rxdata(:, 9)).';
|
||||
seqRx(:,4) = (rxdata(:,10) + 1i*rxdata(:,11)).';
|
||||
|
||||
% compensate frequecny deviation and downsample at optimum sample position based
|
||||
% on the varience of constellation
|
||||
[seqRxDown,fd,samplePos] = suqareShapeFreqEst(seqRx,interp,fs,-50,50,5);
|
||||
|
||||
% split [seqRxDown] into multiple groups, each group contains several symbols to
|
||||
% be correlated with PRBS7 and accumulated
|
||||
seqRxDownSplit = reshape(seqRxDown(1:dataLen/interp,:),chipLen*symNumPerAccum, ...
|
||||
accNum,channelNum);
|
||||
|
||||
seqRxAcc = zeros(chipLen,accNum,channelNum);
|
||||
desiredPnt = zeros(accNum,channelNum);
|
||||
ampEstSym = zeros(accNum,channelNum);
|
||||
angleEstSym = zeros(accNum,channelNum);
|
||||
|
||||
for i = 1:accNum
|
||||
for j = 1:channelNum
|
||||
% correlation & multi-symbol accumulation
|
||||
groupCorrAcc = sum(reshape(conv(flip(seqRxDownSplit(:,i,j)), ...
|
||||
PRBS7_polar,'same'),chipLen,symNumPerAccum),2)';
|
||||
seqRxAcc(:,i,j) = groupCorrAcc;
|
||||
% peak position
|
||||
desiredPnt(i,j) = groupCorrAcc(abs(groupCorrAcc)==max(abs(groupCorrAcc)));
|
||||
end
|
||||
end
|
||||
|
||||
for i = 1:channelNum
|
||||
ampEstSym(:,i) = abs(desiredPnt(:,i))./abs(desiredPnt(:,1));
|
||||
angleEstSym(:,i) = mod((angle(desiredPnt(:,i))-angle(desiredPnt(:,1)))/pi*180,360);
|
||||
end
|
||||
|
||||
%% figures
|
||||
figure(1);
|
||||
|
||||
subplot(121);
|
||||
plot(ampEstSym(:,[1,4]));
|
||||
legend({"ch1","ch4"});
|
||||
title("Amplitude Estimation");
|
||||
ylim([min(ampEstSym(:,[1,4]),[],'all')-0.1,max(ampEstSym(:,[1,4]),[],'all')+0.1]);
|
||||
grid on; grid minor;
|
||||
|
||||
subplot(122);
|
||||
plot(angleEstSym(:,[1,4]));
|
||||
legend({"ch1","ch4"});
|
||||
title("Angle Estimation");
|
||||
ylim([min(angleEstSym(:,[1,4]),[],'all')-1,max(angleEstSym(:,[1,4]),[],'all')+1]);
|
||||
grid on; grid minor;
|
||||
@@ -0,0 +1,50 @@
|
||||
function [dataOut, fdTarget, samplePosTarget] = suqareShapeFreqEst(dataIn, interp, fs, fmin, fmax, fd)
|
||||
%suqareShapeFreqEst - 利用星座图的集中程度在一定频率范围内使用频率步进估计方波成形信号的频偏
|
||||
%
|
||||
% data - input complex data, row vector
|
||||
% dataLen - data length
|
||||
% interp - interpolation rate
|
||||
% fs - sampling rate, in Herts
|
||||
% fmin - minimum estimation frequency, in Herts
|
||||
% fmax - maximum estimation frequency, in Herts
|
||||
% fd - estimation frequency step, in Herts
|
||||
|
||||
% dimension
|
||||
[dataLen,channelNum] = size(dataIn);
|
||||
|
||||
freqList = fmin:fd:fmax;
|
||||
freqNum = length(freqList);
|
||||
varRecord = zeros(freqNum,interp);
|
||||
|
||||
dataOut = zeros(dataLen/interp,channelNum);
|
||||
fdTarget = zeros(channelNum,1);
|
||||
samplePosTarget = zeros(channelNum,1);
|
||||
|
||||
for channel = 1:channelNum
|
||||
|
||||
for freq = 1:freqNum
|
||||
|
||||
% carrier
|
||||
cxr = exp(-1i*2*pi*freqList(freq)/fs*(0:dataLen-1)');
|
||||
|
||||
% apply frequency shift onto input data
|
||||
seqRx = dataIn(:,channel).*cxr;
|
||||
|
||||
for samplePos = 0:interp-1
|
||||
seqRxDown = downsample(seqRx,interp,samplePos); % 下采样
|
||||
seqRxDownQuaterOne = abs(real(seqRxDown)) + 1i*abs(imag(seqRxDown)); % 集中到第一象限
|
||||
varRecord(freq,samplePos+1) = var(seqRxDownQuaterOne);
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
[fdIndex, samplePosIndex] = find(varRecord==min(min(varRecord)));
|
||||
fdTarget(channel) = freqList(fdIndex);
|
||||
samplePosTarget(channel) = samplePosIndex-1;
|
||||
|
||||
cxrTarget = exp(-1i*2*pi*fdTarget(channel)/fs*(0:dataLen-1)');
|
||||
seqRxTarget = dataIn(:,channel).*cxrTarget;
|
||||
dataOut(:,channel) = downsample(seqRxTarget,interp,samplePosTarget(channel));
|
||||
end
|
||||
|
||||
end
|
||||
Binary file not shown.
@@ -0,0 +1 @@
|
||||
The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.
|
||||
@@ -0,0 +1,83 @@
|
||||
// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
|
||||
ila_cal your_instance_name (
|
||||
.clk(clk), // input wire clk
|
||||
|
||||
|
||||
.probe0(probe0), // input wire [0:0] probe0
|
||||
.probe1(probe1), // input wire [0:0] probe1
|
||||
.probe2(probe2), // input wire [0:0] probe2
|
||||
.probe3(probe3), // input wire [0:0] probe3
|
||||
.probe4(probe4), // input wire [0:0] probe4
|
||||
.probe5(probe5), // input wire [0:0] probe5
|
||||
.probe6(probe6), // input wire [1:0] probe6
|
||||
.probe7(probe7), // input wire [11:0] probe7
|
||||
.probe8(probe8), // input wire [11:0] probe8
|
||||
.probe9(probe9), // input wire [11:0] probe9
|
||||
.probe10(probe10), // input wire [11:0] probe10
|
||||
.probe11(probe11), // input wire [11:0] probe11
|
||||
.probe12(probe12), // input wire [11:0] probe12
|
||||
.probe13(probe13), // input wire [11:0] probe13
|
||||
.probe14(probe14) // input wire [11:0] probe14
|
||||
);
|
||||
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
// You must compile the wrapper file ila_cal when simulating
|
||||
// the core, ila_cal. When compiling the wrapper file, be sure to
|
||||
// reference the Verilog simulation library.
|
||||
|
||||
|
||||
BIN
Binary file not shown.
BIN
Binary file not shown.
@@ -0,0 +1,36 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Mon Apr 3 12:05:41 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/duifei/duifei_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/ila_cal_synth_1/ila_cal_stub.v
|
||||
// Design : ila_cal
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z100ffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "ila,Vivado 2019.1.3" *)
|
||||
module ila_cal(clk, probe0, probe1, probe2, probe3, probe4, probe5,
|
||||
probe6, probe7, probe8, probe9, probe10, probe11, probe12, probe13, probe14)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[0:0],probe1[0:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[1:0],probe7[11:0],probe8[11:0],probe9[11:0],probe10[11:0],probe11[11:0],probe12[11:0],probe13[11:0],probe14[11:0]" */;
|
||||
input clk;
|
||||
input [0:0]probe0;
|
||||
input [0:0]probe1;
|
||||
input [0:0]probe2;
|
||||
input [0:0]probe3;
|
||||
input [0:0]probe4;
|
||||
input [0:0]probe5;
|
||||
input [1:0]probe6;
|
||||
input [11:0]probe7;
|
||||
input [11:0]probe8;
|
||||
input [11:0]probe9;
|
||||
input [11:0]probe10;
|
||||
input [11:0]probe11;
|
||||
input [11:0]probe12;
|
||||
input [11:0]probe13;
|
||||
input [11:0]probe14;
|
||||
endmodule
|
||||
@@ -0,0 +1,45 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Mon Apr 3 12:05:41 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/duifei/duifei_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/ila_cal_synth_1/ila_cal_stub.vhdl
|
||||
-- Design : ila_cal
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z100ffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity ila_cal is
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
probe0 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe1 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe2 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe3 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe4 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe5 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe6 : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe7 : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe8 : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe9 : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe10 : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe11 : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe12 : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe13 : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe14 : in STD_LOGIC_VECTOR ( 11 downto 0 )
|
||||
);
|
||||
|
||||
end ila_cal;
|
||||
|
||||
architecture stub of ila_cal is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe0[0:0],probe1[0:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[1:0],probe7[11:0],probe8[11:0],probe9[11:0],probe10[11:0],probe11[11:0],probe12[11:0],probe13[11:0],probe14[11:0]";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
@@ -0,0 +1,90 @@
|
||||
// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
`timescale 1ns / 1ps
|
||||
module ila_cal (
|
||||
clk,
|
||||
|
||||
|
||||
probe0,
|
||||
probe1,
|
||||
probe2,
|
||||
probe3,
|
||||
probe4,
|
||||
probe5,
|
||||
probe6,
|
||||
probe7,
|
||||
probe8,
|
||||
probe9,
|
||||
probe10,
|
||||
probe11,
|
||||
probe12,
|
||||
probe13,
|
||||
probe14
|
||||
);
|
||||
|
||||
input clk;
|
||||
|
||||
|
||||
input [0 : 0] probe0;
|
||||
input [0 : 0] probe1;
|
||||
input [0 : 0] probe2;
|
||||
input [0 : 0] probe3;
|
||||
input [0 : 0] probe4;
|
||||
input [0 : 0] probe5;
|
||||
input [1 : 0] probe6;
|
||||
input [11 : 0] probe7;
|
||||
input [11 : 0] probe8;
|
||||
input [11 : 0] probe9;
|
||||
input [11 : 0] probe10;
|
||||
input [11 : 0] probe11;
|
||||
input [11 : 0] probe12;
|
||||
input [11 : 0] probe13;
|
||||
input [11 : 0] probe14;
|
||||
|
||||
|
||||
endmodule
|
||||
+61
@@ -0,0 +1,61 @@
|
||||
// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
`timescale 1ns / 1ps
|
||||
module vio_clk_ld_rd (
|
||||
clk,
|
||||
probe_in0,probe_in1
|
||||
|
||||
);
|
||||
|
||||
input clk;
|
||||
input [0 : 0] probe_in0;
|
||||
input [0 : 0] probe_in1;
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,67 @@
|
||||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
// IP VLNV: xilinx.com:ip:vio:3.0
|
||||
// IP Revision: 20
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
vio_clk_ld_rd your_instance_name (
|
||||
.clk(clk), // input wire clk
|
||||
.probe_in0(probe_in0), // input wire [0 : 0] probe_in0
|
||||
.probe_in1(probe_in1) // input wire [0 : 0] probe_in1
|
||||
);
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
// You must compile the wrapper file vio_clk_ld_rd.v when simulating
|
||||
// the core, vio_clk_ld_rd. When compiling the wrapper file, be sure to
|
||||
// reference the Verilog simulation library.
|
||||
|
||||
@@ -0,0 +1,79 @@
|
||||
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:vio:3.0
|
||||
-- IP Revision: 20
|
||||
|
||||
-- The following code must appear in the VHDL architecture header.
|
||||
|
||||
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
|
||||
COMPONENT vio_clk_ld_rd
|
||||
PORT (
|
||||
clk : IN STD_LOGIC;
|
||||
probe_in0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe_in1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
||||
|
||||
-- The following code must appear in the VHDL architecture
|
||||
-- body. Substitute your own instance name and net names.
|
||||
|
||||
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
|
||||
your_instance_name : vio_clk_ld_rd
|
||||
PORT MAP (
|
||||
clk => clk,
|
||||
probe_in0 => probe_in0,
|
||||
probe_in1 => probe_in1
|
||||
);
|
||||
-- INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
-- You must compile the wrapper file vio_clk_ld_rd.vhd when simulating
|
||||
-- the core, vio_clk_ld_rd. When compiling the wrapper file, be sure to
|
||||
-- reference the VHDL simulation library.
|
||||
|
||||
BIN
Binary file not shown.
LFS
BIN
Binary file not shown.
+22
@@ -0,0 +1,22 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Thu Mar 30 16:42:41 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ip/managed_ip_project/managed_ip_project.runs/vio_clk_ld_rd_synth_1/vio_clk_ld_rd_stub.v
|
||||
// Design : vio_clk_ld_rd
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z100ffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "vio,Vivado 2019.1.3" *)
|
||||
module vio_clk_ld_rd(clk, probe_in0, probe_in1)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[0:0],probe_in1[0:0]" */;
|
||||
input clk;
|
||||
input [0:0]probe_in0;
|
||||
input [0:0]probe_in1;
|
||||
endmodule
|
||||
+32
@@ -0,0 +1,32 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Thu Mar 30 16:42:42 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/duifei/duifei_cmos/ip/managed_ip_project/managed_ip_project.runs/vio_clk_ld_rd_synth_1/vio_clk_ld_rd_stub.vhdl
|
||||
-- Design : vio_clk_ld_rd
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z100ffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity vio_clk_ld_rd is
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
probe_in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_in1 : in STD_LOGIC_VECTOR ( 0 to 0 )
|
||||
);
|
||||
|
||||
end vio_clk_ld_rd;
|
||||
|
||||
architecture stub of vio_clk_ld_rd is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[0:0],probe_in1[0:0]";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
@@ -0,0 +1,83 @@
|
||||
################################################################################
|
||||
# Vivado (TM) v2019.1.3 (64-bit)
|
||||
#
|
||||
# README.txt: Please read the sections below to understand the steps required
|
||||
# to simulate the design for a simulator, the directory structure
|
||||
# and the generated exported files.
|
||||
#
|
||||
################################################################################
|
||||
|
||||
1. Simulate Design
|
||||
|
||||
To simulate design, cd to the simulator directory and execute the script.
|
||||
|
||||
For example:-
|
||||
|
||||
% cd questa
|
||||
% ./top.sh
|
||||
|
||||
The export simulation flow requires the Xilinx pre-compiled simulation library
|
||||
components for the target simulator. These components are referred using the
|
||||
'-lib_map_path' switch. If this switch is specified, then the export simulation
|
||||
will automatically set this library path in the generated script and update,
|
||||
copy the simulator setup file(s) in the exported directory.
|
||||
|
||||
If '-lib_map_path' is not specified, then the pre-compiled simulation library
|
||||
information will not be included in the exported scripts and that may cause
|
||||
simulation errors when running this script. Alternatively, you can provide the
|
||||
library information using this switch while executing the generated script.
|
||||
|
||||
For example:-
|
||||
|
||||
% ./top.sh -lib_map_path /design/questa/clibs
|
||||
|
||||
Please refer to the generated script header 'Prerequisite' section for more details.
|
||||
|
||||
2. Directory Structure
|
||||
|
||||
By default, if the -directory switch is not specified, export_simulation will
|
||||
create the following directory structure:-
|
||||
|
||||
<current_working_directory>/export_sim/<simulator>
|
||||
|
||||
For example, if the current working directory is /tmp/test, export_simulation
|
||||
will create the following directory path:-
|
||||
|
||||
/tmp/test/export_sim/questa
|
||||
|
||||
If -directory switch is specified, export_simulation will create a simulator
|
||||
sub-directory under the specified directory path.
|
||||
|
||||
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
|
||||
command will create the following directory:-
|
||||
|
||||
/tmp/test/my_test_area/func_sim/questa
|
||||
|
||||
By default, if -simulator is not specified, export_simulation will create a
|
||||
simulator sub-directory for each simulator and export the files for each simulator
|
||||
in this sub-directory respectively.
|
||||
|
||||
IMPORTANT: Please note that the simulation library path must be specified manually
|
||||
in the generated script for the respective simulator. Please refer to the generated
|
||||
script header 'Prerequisite' section for more details.
|
||||
|
||||
3. Exported script and files
|
||||
|
||||
Export simulation will create the driver shell script, setup files and copy the
|
||||
design sources in the output directory path.
|
||||
|
||||
By default, when the -script_name switch is not specified, export_simulation will
|
||||
create the following script name:-
|
||||
|
||||
<simulation_top>.sh (Unix)
|
||||
When exporting the files for an IP using the -of_objects switch, export_simulation
|
||||
will create the following script name:-
|
||||
|
||||
<ip-name>.sh (Unix)
|
||||
Export simulation will create the setup files for the target simulator specified
|
||||
with the -simulator switch.
|
||||
|
||||
For example, if the target simulator is "ies", export_simulation will create the
|
||||
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
|
||||
file.
|
||||
|
||||
+49
@@ -0,0 +1,49 @@
|
||||
################################################################################
|
||||
# Vivado (TM) v2019.1.3 (64-bit)
|
||||
#
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Thu Apr 13 11:50:19 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
1. How to run the generated simulation script:-
|
||||
|
||||
From the shell prompt in the current directory, issue the following command:-
|
||||
|
||||
./ila_cal.sh
|
||||
|
||||
This command will launch the 'compile', 'elaborate' and 'simulate' functions
|
||||
implemented in the script file for the 3-step flow. These functions are called
|
||||
from the main 'run' function in the script file.
|
||||
|
||||
The 'run' function first executes the 'setup' function, the purpose of which is to
|
||||
create simulator specific setup files, create design library mappings and library
|
||||
directories and copy 'glbl.v' from the Vivado software install location into the
|
||||
current directory.
|
||||
|
||||
The 'setup' function is also used for removing the simulator generated data in
|
||||
order to reset the current directory to the original state when export_simulation
|
||||
was launched from Vivado. This generated data can be removed by specifying the
|
||||
'-reset_run' switch to the './ila_cal.sh' script.
|
||||
|
||||
./ila_cal.sh -reset_run
|
||||
|
||||
To keep the generated data from the previous run but regenerate the setup files and
|
||||
library directories, use the '-noclean_files' switch.
|
||||
|
||||
./ila_cal.sh -noclean_files
|
||||
|
||||
For more information on the script, please type './ila_cal.sh -help'.
|
||||
|
||||
2. Additional design information files:-
|
||||
|
||||
export_simulation generates following additional file that can be used for fetching
|
||||
the design files information or for integrating with external custom scripts.
|
||||
|
||||
Name : file_info.txt
|
||||
Purpose: This file contains detail design file information based on the compile order
|
||||
when export_simulation was executed from Vivado. The file contains information
|
||||
about the file type, name, whether it is part of the IP, associated library
|
||||
and the file path information.
|
||||
+22
@@ -0,0 +1,22 @@
|
||||
vlib work
|
||||
vlib activehdl
|
||||
|
||||
vlib activehdl/xil_defaultlib
|
||||
vlib activehdl/xpm
|
||||
|
||||
vmap xil_defaultlib activehdl/xil_defaultlib
|
||||
vmap xpm activehdl/xpm
|
||||
|
||||
vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ip/ila_cal/hdl/verilog" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
|
||||
vcom -work xpm -93 \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
|
||||
vlog -work xil_defaultlib -v2k5 "+incdir+../../../ip/ila_cal/hdl/verilog" \
|
||||
"../../../ip/ila_cal/sim/ila_cal.v" \
|
||||
|
||||
vlog -work xil_defaultlib \
|
||||
"glbl.v"
|
||||
|
||||
+5
@@ -0,0 +1,5 @@
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_cal/hdl/verilog"
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_cal/hdl/verilog"
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_cal/hdl/verilog"
|
||||
ila_cal.v,verilog,xil_defaultlib,../../../ip/ila_cal/sim/ila_cal.v,incdir="../../../ip/ila_cal/hdl/verilog"
|
||||
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||
+71
@@ -0,0 +1,71 @@
|
||||
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
Executable
+152
@@ -0,0 +1,152 @@
|
||||
#!/bin/bash -f
|
||||
#*********************************************************************************************************
|
||||
# Vivado (TM) v2019.1.3 (64-bit)
|
||||
#
|
||||
# Filename : ila_cal.sh
|
||||
# Simulator : Aldec Active-HDL Simulator
|
||||
# Description : Simulation script for compiling, elaborating and verifying the project source files.
|
||||
# The script will automatically create the design libraries sub-directories in the run
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Thu Apr 13 11:50:19 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
# usage: ila_cal.sh [-help]
|
||||
# usage: ila_cal.sh [-lib_map_path]
|
||||
# usage: ila_cal.sh [-noclean_files]
|
||||
# usage: ila_cal.sh [-reset_run]
|
||||
#
|
||||
# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
|
||||
# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
|
||||
# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
|
||||
# that points to these libraries and rerun export_simulation. For more information about this switch please
|
||||
# type 'export_simulation -help' in the Tcl shell.
|
||||
#
|
||||
# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
|
||||
# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
|
||||
# executing this script. Please type 'ila_cal.sh -help' for more information.
|
||||
#
|
||||
# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
|
||||
#
|
||||
#*********************************************************************************************************
|
||||
|
||||
|
||||
# Script info
|
||||
echo -e "ila_cal.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
|
||||
|
||||
# Main steps
|
||||
run()
|
||||
{
|
||||
check_args $# $1
|
||||
setup $1 $2
|
||||
compile
|
||||
simulate
|
||||
}
|
||||
|
||||
# RUN_STEP: <compile>
|
||||
compile()
|
||||
{
|
||||
# Compile design files
|
||||
source compile.do 2>&1 | tee -a compile.log
|
||||
|
||||
}
|
||||
|
||||
# RUN_STEP: <simulate>
|
||||
simulate()
|
||||
{
|
||||
runvsimsa -l simulate.log -do "do {simulate.do}"
|
||||
}
|
||||
|
||||
# STEP: setup
|
||||
setup()
|
||||
{
|
||||
case $1 in
|
||||
"-lib_map_path" )
|
||||
if [[ ($2 == "") ]]; then
|
||||
echo -e "ERROR: Simulation library directory path not specified (type \"./ila_cal.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
map_setup_file $2
|
||||
;;
|
||||
"-reset_run" )
|
||||
reset_run
|
||||
echo -e "INFO: Simulation run files deleted.\n"
|
||||
exit 0
|
||||
;;
|
||||
"-noclean_files" )
|
||||
# do not remove previous data
|
||||
;;
|
||||
* )
|
||||
map_setup_file $2
|
||||
esac
|
||||
|
||||
# Add any setup/initialization commands here:-
|
||||
|
||||
# <user specific commands>
|
||||
|
||||
}
|
||||
|
||||
# Map library.cfg file
|
||||
map_setup_file()
|
||||
{
|
||||
file="library.cfg"
|
||||
lib_map_path=""
|
||||
if [[ ($1 != "") ]]; then
|
||||
lib_map_path="$1"
|
||||
fi
|
||||
if [[ ($lib_map_path != "") ]]; then
|
||||
src_file="$lib_map_path/$file"
|
||||
if [[ -e $src_file ]]; then
|
||||
vmap -link $lib_map_path
|
||||
fi
|
||||
fi
|
||||
}
|
||||
|
||||
# Delete generated data from the previous run
|
||||
reset_run()
|
||||
{
|
||||
files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl)
|
||||
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
|
||||
file="${files_to_remove[i]}"
|
||||
if [[ -e $file ]]; then
|
||||
rm -rf $file
|
||||
fi
|
||||
done
|
||||
}
|
||||
|
||||
# Check command line arguments
|
||||
check_args()
|
||||
{
|
||||
if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
|
||||
echo -e "ERROR: Unknown option specified '$2' (type \"./ila_cal.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
|
||||
if [[ ($2 == "-help" || $2 == "-h") ]]; then
|
||||
usage
|
||||
fi
|
||||
}
|
||||
|
||||
# Script usage
|
||||
usage()
|
||||
{
|
||||
msg="Usage: ila_cal.sh [-help]\n\
|
||||
Usage: ila_cal.sh [-lib_map_path]\n\
|
||||
Usage: ila_cal.sh [-reset_run]\n\
|
||||
Usage: ila_cal.sh [-noclean_files]\n\n\
|
||||
[-help] -- Print help information for this script\n\n\
|
||||
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
|
||||
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
|
||||
[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
|
||||
from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
|
||||
-noclean_files switch.\n\n\
|
||||
[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
|
||||
echo -e $msg
|
||||
exit 1
|
||||
}
|
||||
|
||||
# Launch script
|
||||
run $1 $2
|
||||
+17
@@ -0,0 +1,17 @@
|
||||
onbreak {quit -force}
|
||||
onerror {quit -force}
|
||||
|
||||
asim -t 1ps +access +r +m+ila_cal -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.ila_cal xil_defaultlib.glbl
|
||||
|
||||
do {wave.do}
|
||||
|
||||
view wave
|
||||
view structure
|
||||
|
||||
do {ila_cal.udo}
|
||||
|
||||
run -all
|
||||
|
||||
endsim
|
||||
|
||||
quit -force
|
||||
+2
@@ -0,0 +1,2 @@
|
||||
add wave *
|
||||
add wave /glbl/GSR
|
||||
@@ -0,0 +1,48 @@
|
||||
################################################################################
|
||||
# Vivado (TM) v2019.1.3 (64-bit)
|
||||
#
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Thu Apr 13 11:50:19 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
1. How to run the generated simulation script:-
|
||||
|
||||
From the shell prompt in the current directory, issue the following command:-
|
||||
|
||||
./ila_cal.sh
|
||||
|
||||
This command will launch the 'execute' function for the single-step flow. This
|
||||
function is called from the main 'run' function in the script file.
|
||||
|
||||
The 'run' function first executes the 'setup' function, the purpose of which is to
|
||||
create simulator specific setup files, create design library mappings and library
|
||||
directories and copy 'glbl.v' from the Vivado software install location into the
|
||||
current directory.
|
||||
|
||||
The 'setup' function is also used for removing the simulator generated data in
|
||||
order to reset the current directory to the original state when export_simulation
|
||||
was launched from Vivado. This generated data can be removed by specifying the
|
||||
'-reset_run' switch to the './ila_cal.sh' script.
|
||||
|
||||
./ila_cal.sh -reset_run
|
||||
|
||||
To keep the generated data from the previous run but regenerate the setup files and
|
||||
library directories, use the '-noclean_files' switch.
|
||||
|
||||
./ila_cal.sh -noclean_files
|
||||
|
||||
For more information on the script, please type './ila_cal.sh -help'.
|
||||
|
||||
2. Additional design information files:-
|
||||
|
||||
export_simulation generates following additional file that can be used for fetching
|
||||
the design files information or for integrating with external custom scripts.
|
||||
|
||||
Name : file_info.txt
|
||||
Purpose: This file contains detail design file information based on the compile order
|
||||
when export_simulation was executed from Vivado. The file contains information
|
||||
about the file type, name, whether it is part of the IP, associated library
|
||||
and the file path information.
|
||||
+5
@@ -0,0 +1,5 @@
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_cal/hdl/verilog"
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_cal/hdl/verilog"
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_cal/hdl/verilog"
|
||||
ila_cal.v,verilog,xil_defaultlib,../../../ip/ila_cal/sim/ila_cal.v,incdir="../../../ip/ila_cal/hdl/verilog"
|
||||
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||
@@ -0,0 +1,71 @@
|
||||
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
+176
@@ -0,0 +1,176 @@
|
||||
#!/bin/bash -f
|
||||
#*********************************************************************************************************
|
||||
# Vivado (TM) v2019.1.3 (64-bit)
|
||||
#
|
||||
# Filename : ila_cal.sh
|
||||
# Simulator : Cadence Incisive Enterprise Simulator
|
||||
# Description : Simulation script for compiling, elaborating and verifying the project source files.
|
||||
# The script will automatically create the design libraries sub-directories in the run
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Thu Apr 13 11:50:19 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
# usage: ila_cal.sh [-help]
|
||||
# usage: ila_cal.sh [-lib_map_path]
|
||||
# usage: ila_cal.sh [-noclean_files]
|
||||
# usage: ila_cal.sh [-reset_run]
|
||||
#
|
||||
# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
|
||||
# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
|
||||
# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
|
||||
# that points to these libraries and rerun export_simulation. For more information about this switch please
|
||||
# type 'export_simulation -help' in the Tcl shell.
|
||||
#
|
||||
# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
|
||||
# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
|
||||
# executing this script. Please type 'ila_cal.sh -help' for more information.
|
||||
#
|
||||
# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
|
||||
#
|
||||
#*********************************************************************************************************
|
||||
|
||||
# Directory path for design sources and include directories (if any) wrt this path
|
||||
ref_dir="."
|
||||
|
||||
# Override directory with 'export_sim_ref_dir' env path value if set in the shell
|
||||
if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
|
||||
ref_dir="$export_sim_ref_dir"
|
||||
fi
|
||||
|
||||
# Set the compiled library directory
|
||||
ref_lib_dir="."
|
||||
|
||||
# Command line options
|
||||
irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen"
|
||||
|
||||
# Design libraries
|
||||
design_libs=(xil_defaultlib xpm)
|
||||
|
||||
# Simulation root library directory
|
||||
sim_lib_dir="ies_lib"
|
||||
|
||||
# Script info
|
||||
echo -e "ila_cal.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
|
||||
|
||||
# Main steps
|
||||
run()
|
||||
{
|
||||
check_args $# $1
|
||||
setup $1 $2
|
||||
execute
|
||||
}
|
||||
|
||||
# RUN_STEP: <execute>
|
||||
execute()
|
||||
{
|
||||
irun $irun_opts \
|
||||
-reflib "$ref_lib_dir/unisim:unisim" \
|
||||
-reflib "$ref_lib_dir/unisims_ver:unisims_ver" \
|
||||
-reflib "$ref_lib_dir/secureip:secureip" \
|
||||
-reflib "$ref_lib_dir/unimacro:unimacro" \
|
||||
-reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \
|
||||
-top xil_defaultlib.ila_cal \
|
||||
-f run.f \
|
||||
-top glbl \
|
||||
glbl.v \
|
||||
+incdir+"../../../ip/ila_cal/hdl/verilog"
|
||||
}
|
||||
|
||||
# STEP: setup
|
||||
setup()
|
||||
{
|
||||
case $1 in
|
||||
"-lib_map_path" )
|
||||
if [[ ($2 == "") ]]; then
|
||||
echo -e "ERROR: Simulation library directory path not specified (type \"./ila_cal.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
else
|
||||
ref_lib_dir=$2
|
||||
fi
|
||||
;;
|
||||
"-reset_run" )
|
||||
reset_run
|
||||
echo -e "INFO: Simulation run files deleted.\n"
|
||||
exit 0
|
||||
;;
|
||||
"-noclean_files" )
|
||||
# do not remove previous data
|
||||
;;
|
||||
* )
|
||||
esac
|
||||
|
||||
create_lib_dir
|
||||
|
||||
# Add any setup/initialization commands here:-
|
||||
|
||||
# <user specific commands>
|
||||
|
||||
}
|
||||
|
||||
# Create design library directory paths
|
||||
create_lib_dir()
|
||||
{
|
||||
if [[ -e $sim_lib_dir ]]; then
|
||||
rm -rf $sim_lib_dir
|
||||
fi
|
||||
|
||||
for (( i=0; i<${#design_libs[*]}; i++ )); do
|
||||
lib="${design_libs[i]}"
|
||||
lib_dir="$sim_lib_dir/$lib"
|
||||
if [[ ! -e $lib_dir ]]; then
|
||||
mkdir -p $lib_dir
|
||||
fi
|
||||
done
|
||||
}
|
||||
|
||||
# Delete generated data from the previous run
|
||||
reset_run()
|
||||
{
|
||||
files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs)
|
||||
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
|
||||
file="${files_to_remove[i]}"
|
||||
if [[ -e $file ]]; then
|
||||
rm -rf $file
|
||||
fi
|
||||
done
|
||||
|
||||
create_lib_dir
|
||||
}
|
||||
|
||||
# Check command line arguments
|
||||
check_args()
|
||||
{
|
||||
if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
|
||||
echo -e "ERROR: Unknown option specified '$2' (type \"./ila_cal.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
|
||||
if [[ ($2 == "-help" || $2 == "-h") ]]; then
|
||||
usage
|
||||
fi
|
||||
}
|
||||
|
||||
# Script usage
|
||||
usage()
|
||||
{
|
||||
msg="Usage: ila_cal.sh [-help]\n\
|
||||
Usage: ila_cal.sh [-lib_map_path]\n\
|
||||
Usage: ila_cal.sh [-reset_run]\n\
|
||||
Usage: ila_cal.sh [-noclean_files]\n\n\
|
||||
[-help] -- Print help information for this script\n\n\
|
||||
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
|
||||
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
|
||||
[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
|
||||
from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
|
||||
-noclean_files switch.\n\n\
|
||||
[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
|
||||
echo -e $msg
|
||||
exit 1
|
||||
}
|
||||
|
||||
# Launch script
|
||||
run $1 $2
|
||||
@@ -0,0 +1,14 @@
|
||||
-makelib ies_lib/xil_defaultlib -sv \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
-endlib
|
||||
-makelib ies_lib/xpm \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
-endlib
|
||||
-makelib ies_lib/xil_defaultlib \
|
||||
"../../../ip/ila_cal/sim/ila_cal.v" \
|
||||
-endlib
|
||||
-makelib ies_lib/xil_defaultlib \
|
||||
glbl.v
|
||||
-endlib
|
||||
|
||||
+49
@@ -0,0 +1,49 @@
|
||||
################################################################################
|
||||
# Vivado (TM) v2019.1.3 (64-bit)
|
||||
#
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Thu Apr 13 11:50:19 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
1. How to run the generated simulation script:-
|
||||
|
||||
From the shell prompt in the current directory, issue the following command:-
|
||||
|
||||
./ila_cal.sh
|
||||
|
||||
This command will launch the 'compile', 'elaborate' and 'simulate' functions
|
||||
implemented in the script file for the 3-step flow. These functions are called
|
||||
from the main 'run' function in the script file.
|
||||
|
||||
The 'run' function first executes the 'setup' function, the purpose of which is to
|
||||
create simulator specific setup files, create design library mappings and library
|
||||
directories and copy 'glbl.v' from the Vivado software install location into the
|
||||
current directory.
|
||||
|
||||
The 'setup' function is also used for removing the simulator generated data in
|
||||
order to reset the current directory to the original state when export_simulation
|
||||
was launched from Vivado. This generated data can be removed by specifying the
|
||||
'-reset_run' switch to the './ila_cal.sh' script.
|
||||
|
||||
./ila_cal.sh -reset_run
|
||||
|
||||
To keep the generated data from the previous run but regenerate the setup files and
|
||||
library directories, use the '-noclean_files' switch.
|
||||
|
||||
./ila_cal.sh -noclean_files
|
||||
|
||||
For more information on the script, please type './ila_cal.sh -help'.
|
||||
|
||||
2. Additional design information files:-
|
||||
|
||||
export_simulation generates following additional file that can be used for fetching
|
||||
the design files information or for integrating with external custom scripts.
|
||||
|
||||
Name : file_info.txt
|
||||
Purpose: This file contains detail design file information based on the compile order
|
||||
when export_simulation was executed from Vivado. The file contains information
|
||||
about the file type, name, whether it is part of the IP, associated library
|
||||
and the file path information.
|
||||
+22
@@ -0,0 +1,22 @@
|
||||
vlib modelsim_lib/work
|
||||
vlib modelsim_lib/msim
|
||||
|
||||
vlib modelsim_lib/msim/xil_defaultlib
|
||||
vlib modelsim_lib/msim/xpm
|
||||
|
||||
vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib
|
||||
vmap xpm modelsim_lib/msim/xpm
|
||||
|
||||
vlog -work xil_defaultlib -64 -incr -sv "+incdir+../../../ip/ila_cal/hdl/verilog" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
|
||||
vcom -work xpm -64 -93 \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
|
||||
vlog -work xil_defaultlib -64 -incr "+incdir+../../../ip/ila_cal/hdl/verilog" \
|
||||
"../../../ip/ila_cal/sim/ila_cal.v" \
|
||||
|
||||
vlog -work xil_defaultlib \
|
||||
"glbl.v"
|
||||
|
||||
+5
@@ -0,0 +1,5 @@
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_cal/hdl/verilog"
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_cal/hdl/verilog"
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_cal/hdl/verilog"
|
||||
ila_cal.v,verilog,xil_defaultlib,../../../ip/ila_cal/sim/ila_cal.v,incdir="../../../ip/ila_cal/hdl/verilog"
|
||||
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||
+71
@@ -0,0 +1,71 @@
|
||||
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
Executable
+168
@@ -0,0 +1,168 @@
|
||||
#!/bin/bash -f
|
||||
#*********************************************************************************************************
|
||||
# Vivado (TM) v2019.1.3 (64-bit)
|
||||
#
|
||||
# Filename : ila_cal.sh
|
||||
# Simulator : Mentor Graphics ModelSim Simulator
|
||||
# Description : Simulation script for compiling, elaborating and verifying the project source files.
|
||||
# The script will automatically create the design libraries sub-directories in the run
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Thu Apr 13 11:50:19 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
# usage: ila_cal.sh [-help]
|
||||
# usage: ila_cal.sh [-lib_map_path]
|
||||
# usage: ila_cal.sh [-noclean_files]
|
||||
# usage: ila_cal.sh [-reset_run]
|
||||
#
|
||||
# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
|
||||
# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
|
||||
# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
|
||||
# that points to these libraries and rerun export_simulation. For more information about this switch please
|
||||
# type 'export_simulation -help' in the Tcl shell.
|
||||
#
|
||||
# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
|
||||
# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
|
||||
# executing this script. Please type 'ila_cal.sh -help' for more information.
|
||||
#
|
||||
# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
|
||||
#
|
||||
#*********************************************************************************************************
|
||||
|
||||
|
||||
# Script info
|
||||
echo -e "ila_cal.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
|
||||
|
||||
# Main steps
|
||||
run()
|
||||
{
|
||||
check_args $# $1
|
||||
setup $1 $2
|
||||
compile
|
||||
simulate
|
||||
}
|
||||
|
||||
# RUN_STEP: <compile>
|
||||
compile()
|
||||
{
|
||||
# Compile design files
|
||||
source compile.do 2>&1 | tee -a compile.log
|
||||
|
||||
}
|
||||
|
||||
# RUN_STEP: <simulate>
|
||||
simulate()
|
||||
{
|
||||
vsim -64 -c -do "do {simulate.do}" -l simulate.log
|
||||
}
|
||||
|
||||
# STEP: setup
|
||||
setup()
|
||||
{
|
||||
case $1 in
|
||||
"-lib_map_path" )
|
||||
if [[ ($2 == "") ]]; then
|
||||
echo -e "ERROR: Simulation library directory path not specified (type \"./ila_cal.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
copy_setup_file $2
|
||||
;;
|
||||
"-reset_run" )
|
||||
reset_run
|
||||
echo -e "INFO: Simulation run files deleted.\n"
|
||||
exit 0
|
||||
;;
|
||||
"-noclean_files" )
|
||||
# do not remove previous data
|
||||
;;
|
||||
* )
|
||||
copy_setup_file $2
|
||||
esac
|
||||
|
||||
create_lib_dir
|
||||
|
||||
# Add any setup/initialization commands here:-
|
||||
|
||||
# <user specific commands>
|
||||
|
||||
}
|
||||
|
||||
# Copy modelsim.ini file
|
||||
copy_setup_file()
|
||||
{
|
||||
file="modelsim.ini"
|
||||
lib_map_path="<SPECIFY_COMPILED_LIB_PATH>"
|
||||
if [[ ($1 != "" && -e $1) ]]; then
|
||||
lib_map_path="$1"
|
||||
else
|
||||
echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n"
|
||||
fi
|
||||
if [[ ($lib_map_path != "") ]]; then
|
||||
src_file="$lib_map_path/$file"
|
||||
cp $src_file .
|
||||
fi
|
||||
}
|
||||
|
||||
# Create design library directory
|
||||
create_lib_dir()
|
||||
{
|
||||
lib_dir="modelsim_lib"
|
||||
if [[ -e $lib_dir ]]; then
|
||||
rm -rf $lib_dir
|
||||
fi
|
||||
|
||||
mkdir $lib_dir
|
||||
|
||||
}
|
||||
|
||||
# Delete generated data from the previous run
|
||||
reset_run()
|
||||
{
|
||||
files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib)
|
||||
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
|
||||
file="${files_to_remove[i]}"
|
||||
if [[ -e $file ]]; then
|
||||
rm -rf $file
|
||||
fi
|
||||
done
|
||||
|
||||
create_lib_dir
|
||||
}
|
||||
|
||||
# Check command line arguments
|
||||
check_args()
|
||||
{
|
||||
if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
|
||||
echo -e "ERROR: Unknown option specified '$2' (type \"./ila_cal.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
|
||||
if [[ ($2 == "-help" || $2 == "-h") ]]; then
|
||||
usage
|
||||
fi
|
||||
}
|
||||
|
||||
# Script usage
|
||||
usage()
|
||||
{
|
||||
msg="Usage: ila_cal.sh [-help]\n\
|
||||
Usage: ila_cal.sh [-lib_map_path]\n\
|
||||
Usage: ila_cal.sh [-reset_run]\n\
|
||||
Usage: ila_cal.sh [-noclean_files]\n\n\
|
||||
[-help] -- Print help information for this script\n\n\
|
||||
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
|
||||
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
|
||||
[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
|
||||
from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
|
||||
-noclean_files switch.\n\n\
|
||||
[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
|
||||
echo -e $msg
|
||||
exit 1
|
||||
}
|
||||
|
||||
# Launch script
|
||||
run $1 $2
|
||||
+16
@@ -0,0 +1,16 @@
|
||||
onbreak {quit -f}
|
||||
onerror {quit -f}
|
||||
|
||||
vsim -voptargs="+acc" -t 1ps -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.ila_cal xil_defaultlib.glbl
|
||||
|
||||
do {wave.do}
|
||||
|
||||
view wave
|
||||
view structure
|
||||
view signals
|
||||
|
||||
do {ila_cal.udo}
|
||||
|
||||
run -all
|
||||
|
||||
quit -force
|
||||
+2
@@ -0,0 +1,2 @@
|
||||
add wave *
|
||||
add wave /glbl/GSR
|
||||
+49
@@ -0,0 +1,49 @@
|
||||
################################################################################
|
||||
# Vivado (TM) v2019.1.3 (64-bit)
|
||||
#
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Thu Apr 13 11:50:19 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
1. How to run the generated simulation script:-
|
||||
|
||||
From the shell prompt in the current directory, issue the following command:-
|
||||
|
||||
./ila_cal.sh
|
||||
|
||||
This command will launch the 'compile', 'elaborate' and 'simulate' functions
|
||||
implemented in the script file for the 3-step flow. These functions are called
|
||||
from the main 'run' function in the script file.
|
||||
|
||||
The 'run' function first executes the 'setup' function, the purpose of which is to
|
||||
create simulator specific setup files, create design library mappings and library
|
||||
directories and copy 'glbl.v' from the Vivado software install location into the
|
||||
current directory.
|
||||
|
||||
The 'setup' function is also used for removing the simulator generated data in
|
||||
order to reset the current directory to the original state when export_simulation
|
||||
was launched from Vivado. This generated data can be removed by specifying the
|
||||
'-reset_run' switch to the './ila_cal.sh' script.
|
||||
|
||||
./ila_cal.sh -reset_run
|
||||
|
||||
To keep the generated data from the previous run but regenerate the setup files and
|
||||
library directories, use the '-noclean_files' switch.
|
||||
|
||||
./ila_cal.sh -noclean_files
|
||||
|
||||
For more information on the script, please type './ila_cal.sh -help'.
|
||||
|
||||
2. Additional design information files:-
|
||||
|
||||
export_simulation generates following additional file that can be used for fetching
|
||||
the design files information or for integrating with external custom scripts.
|
||||
|
||||
Name : file_info.txt
|
||||
Purpose: This file contains detail design file information based on the compile order
|
||||
when export_simulation was executed from Vivado. The file contains information
|
||||
about the file type, name, whether it is part of the IP, associated library
|
||||
and the file path information.
|
||||
+22
@@ -0,0 +1,22 @@
|
||||
vlib questa_lib/work
|
||||
vlib questa_lib/msim
|
||||
|
||||
vlib questa_lib/msim/xil_defaultlib
|
||||
vlib questa_lib/msim/xpm
|
||||
|
||||
vmap xil_defaultlib questa_lib/msim/xil_defaultlib
|
||||
vmap xpm questa_lib/msim/xpm
|
||||
|
||||
vlog -work xil_defaultlib -64 -sv "+incdir+../../../ip/ila_cal/hdl/verilog" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
|
||||
vcom -work xpm -64 -93 \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
|
||||
vlog -work xil_defaultlib -64 "+incdir+../../../ip/ila_cal/hdl/verilog" \
|
||||
"../../../ip/ila_cal/sim/ila_cal.v" \
|
||||
|
||||
vlog -work xil_defaultlib \
|
||||
"glbl.v"
|
||||
|
||||
+1
@@ -0,0 +1 @@
|
||||
vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.ila_cal xil_defaultlib.glbl -o ila_cal_opt
|
||||
+5
@@ -0,0 +1,5 @@
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_cal/hdl/verilog"
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_cal/hdl/verilog"
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_cal/hdl/verilog"
|
||||
ila_cal.v,verilog,xil_defaultlib,../../../ip/ila_cal/sim/ila_cal.v,incdir="../../../ip/ila_cal/hdl/verilog"
|
||||
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||
@@ -0,0 +1,71 @@
|
||||
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
+173
@@ -0,0 +1,173 @@
|
||||
#!/bin/bash -f
|
||||
#*********************************************************************************************************
|
||||
# Vivado (TM) v2019.1.3 (64-bit)
|
||||
#
|
||||
# Filename : ila_cal.sh
|
||||
# Simulator : Mentor Graphics Questa Advanced Simulator
|
||||
# Description : Simulation script for compiling, elaborating and verifying the project source files.
|
||||
# The script will automatically create the design libraries sub-directories in the run
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Thu Apr 13 11:50:19 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
# usage: ila_cal.sh [-help]
|
||||
# usage: ila_cal.sh [-lib_map_path]
|
||||
# usage: ila_cal.sh [-noclean_files]
|
||||
# usage: ila_cal.sh [-reset_run]
|
||||
#
|
||||
# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
|
||||
# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
|
||||
# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
|
||||
# that points to these libraries and rerun export_simulation. For more information about this switch please
|
||||
# type 'export_simulation -help' in the Tcl shell.
|
||||
#
|
||||
# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
|
||||
# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
|
||||
# executing this script. Please type 'ila_cal.sh -help' for more information.
|
||||
#
|
||||
# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
|
||||
#
|
||||
#*********************************************************************************************************
|
||||
|
||||
|
||||
# Script info
|
||||
echo -e "ila_cal.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
|
||||
|
||||
# Main steps
|
||||
run()
|
||||
{
|
||||
check_args $# $1
|
||||
setup $1 $2
|
||||
compile
|
||||
elaborate
|
||||
simulate
|
||||
}
|
||||
|
||||
# RUN_STEP: <compile>
|
||||
compile()
|
||||
{
|
||||
# Compile design files
|
||||
source compile.do 2>&1 | tee -a compile.log
|
||||
|
||||
}
|
||||
|
||||
# RUN_STEP: <elaborate>
|
||||
elaborate()
|
||||
{
|
||||
source elaborate.do 2>&1 | tee -a elaborate.log
|
||||
}
|
||||
|
||||
# RUN_STEP: <simulate>
|
||||
simulate()
|
||||
{
|
||||
vsim -64 -c -do "do {simulate.do}" -l simulate.log
|
||||
}
|
||||
|
||||
# STEP: setup
|
||||
setup()
|
||||
{
|
||||
case $1 in
|
||||
"-lib_map_path" )
|
||||
if [[ ($2 == "") ]]; then
|
||||
echo -e "ERROR: Simulation library directory path not specified (type \"./ila_cal.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
copy_setup_file $2
|
||||
;;
|
||||
"-reset_run" )
|
||||
reset_run
|
||||
echo -e "INFO: Simulation run files deleted.\n"
|
||||
exit 0
|
||||
;;
|
||||
"-noclean_files" )
|
||||
# do not remove previous data
|
||||
;;
|
||||
* )
|
||||
copy_setup_file $2
|
||||
esac
|
||||
|
||||
create_lib_dir
|
||||
|
||||
# Add any setup/initialization commands here:-
|
||||
|
||||
# <user specific commands>
|
||||
|
||||
}
|
||||
|
||||
# Copy modelsim.ini file
|
||||
copy_setup_file()
|
||||
{
|
||||
file="modelsim.ini"
|
||||
lib_map_path=""
|
||||
if [[ ($1 != "") ]]; then
|
||||
lib_map_path="$1"
|
||||
fi
|
||||
if [[ ($lib_map_path != "") ]]; then
|
||||
src_file="$lib_map_path/$file"
|
||||
cp $src_file .
|
||||
fi
|
||||
}
|
||||
|
||||
# Create design library directory
|
||||
create_lib_dir()
|
||||
{
|
||||
lib_dir="questa_lib"
|
||||
if [[ -e $lib_dir ]]; then
|
||||
rm -rf $lib_dir
|
||||
fi
|
||||
|
||||
mkdir $lib_dir
|
||||
|
||||
}
|
||||
|
||||
# Delete generated data from the previous run
|
||||
reset_run()
|
||||
{
|
||||
files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib)
|
||||
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
|
||||
file="${files_to_remove[i]}"
|
||||
if [[ -e $file ]]; then
|
||||
rm -rf $file
|
||||
fi
|
||||
done
|
||||
|
||||
create_lib_dir
|
||||
}
|
||||
|
||||
# Check command line arguments
|
||||
check_args()
|
||||
{
|
||||
if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
|
||||
echo -e "ERROR: Unknown option specified '$2' (type \"./ila_cal.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
|
||||
if [[ ($2 == "-help" || $2 == "-h") ]]; then
|
||||
usage
|
||||
fi
|
||||
}
|
||||
|
||||
# Script usage
|
||||
usage()
|
||||
{
|
||||
msg="Usage: ila_cal.sh [-help]\n\
|
||||
Usage: ila_cal.sh [-lib_map_path]\n\
|
||||
Usage: ila_cal.sh [-reset_run]\n\
|
||||
Usage: ila_cal.sh [-noclean_files]\n\n\
|
||||
[-help] -- Print help information for this script\n\n\
|
||||
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
|
||||
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
|
||||
[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
|
||||
from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
|
||||
-noclean_files switch.\n\n\
|
||||
[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
|
||||
echo -e $msg
|
||||
exit 1
|
||||
}
|
||||
|
||||
# Launch script
|
||||
run $1 $2
|
||||
+16
@@ -0,0 +1,16 @@
|
||||
onbreak {quit -f}
|
||||
onerror {quit -f}
|
||||
|
||||
vsim -t 1ps -lib xil_defaultlib ila_cal_opt
|
||||
|
||||
do {wave.do}
|
||||
|
||||
view wave
|
||||
view structure
|
||||
view signals
|
||||
|
||||
do {ila_cal.udo}
|
||||
|
||||
run -all
|
||||
|
||||
quit -force
|
||||
@@ -0,0 +1,2 @@
|
||||
add wave *
|
||||
add wave /glbl/GSR
|
||||
+49
@@ -0,0 +1,49 @@
|
||||
################################################################################
|
||||
# Vivado (TM) v2019.1.3 (64-bit)
|
||||
#
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Thu Apr 13 11:50:19 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
1. How to run the generated simulation script:-
|
||||
|
||||
From the shell prompt in the current directory, issue the following command:-
|
||||
|
||||
./ila_cal.sh
|
||||
|
||||
This command will launch the 'compile', 'elaborate' and 'simulate' functions
|
||||
implemented in the script file for the 3-step flow. These functions are called
|
||||
from the main 'run' function in the script file.
|
||||
|
||||
The 'run' function first executes the 'setup' function, the purpose of which is to
|
||||
create simulator specific setup files, create design library mappings and library
|
||||
directories and copy 'glbl.v' from the Vivado software install location into the
|
||||
current directory.
|
||||
|
||||
The 'setup' function is also used for removing the simulator generated data in
|
||||
order to reset the current directory to the original state when export_simulation
|
||||
was launched from Vivado. This generated data can be removed by specifying the
|
||||
'-reset_run' switch to the './ila_cal.sh' script.
|
||||
|
||||
./ila_cal.sh -reset_run
|
||||
|
||||
To keep the generated data from the previous run but regenerate the setup files and
|
||||
library directories, use the '-noclean_files' switch.
|
||||
|
||||
./ila_cal.sh -noclean_files
|
||||
|
||||
For more information on the script, please type './ila_cal.sh -help'.
|
||||
|
||||
2. Additional design information files:-
|
||||
|
||||
export_simulation generates following additional file that can be used for fetching
|
||||
the design files information or for integrating with external custom scripts.
|
||||
|
||||
Name : file_info.txt
|
||||
Purpose: This file contains detail design file information based on the compile order
|
||||
when export_simulation was executed from Vivado. The file contains information
|
||||
about the file type, name, whether it is part of the IP, associated library
|
||||
and the file path information.
|
||||
+22
@@ -0,0 +1,22 @@
|
||||
vlib work
|
||||
vlib riviera
|
||||
|
||||
vlib riviera/xil_defaultlib
|
||||
vlib riviera/xpm
|
||||
|
||||
vmap xil_defaultlib riviera/xil_defaultlib
|
||||
vmap xpm riviera/xpm
|
||||
|
||||
vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ip/ila_cal/hdl/verilog" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
|
||||
vcom -work xpm -93 \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
|
||||
vlog -work xil_defaultlib -v2k5 "+incdir+../../../ip/ila_cal/hdl/verilog" \
|
||||
"../../../ip/ila_cal/sim/ila_cal.v" \
|
||||
|
||||
vlog -work xil_defaultlib \
|
||||
"glbl.v"
|
||||
|
||||
+5
@@ -0,0 +1,5 @@
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_cal/hdl/verilog"
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_cal/hdl/verilog"
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_cal/hdl/verilog"
|
||||
ila_cal.v,verilog,xil_defaultlib,../../../ip/ila_cal/sim/ila_cal.v,incdir="../../../ip/ila_cal/hdl/verilog"
|
||||
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||
@@ -0,0 +1,71 @@
|
||||
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
Executable
+152
@@ -0,0 +1,152 @@
|
||||
#!/bin/bash -f
|
||||
#*********************************************************************************************************
|
||||
# Vivado (TM) v2019.1.3 (64-bit)
|
||||
#
|
||||
# Filename : ila_cal.sh
|
||||
# Simulator : Aldec Riviera-PRO Simulator
|
||||
# Description : Simulation script for compiling, elaborating and verifying the project source files.
|
||||
# The script will automatically create the design libraries sub-directories in the run
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Thu Apr 13 11:50:19 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
# usage: ila_cal.sh [-help]
|
||||
# usage: ila_cal.sh [-lib_map_path]
|
||||
# usage: ila_cal.sh [-noclean_files]
|
||||
# usage: ila_cal.sh [-reset_run]
|
||||
#
|
||||
# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
|
||||
# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
|
||||
# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
|
||||
# that points to these libraries and rerun export_simulation. For more information about this switch please
|
||||
# type 'export_simulation -help' in the Tcl shell.
|
||||
#
|
||||
# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
|
||||
# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
|
||||
# executing this script. Please type 'ila_cal.sh -help' for more information.
|
||||
#
|
||||
# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
|
||||
#
|
||||
#*********************************************************************************************************
|
||||
|
||||
|
||||
# Script info
|
||||
echo -e "ila_cal.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
|
||||
|
||||
# Main steps
|
||||
run()
|
||||
{
|
||||
check_args $# $1
|
||||
setup $1 $2
|
||||
compile
|
||||
simulate
|
||||
}
|
||||
|
||||
# RUN_STEP: <compile>
|
||||
compile()
|
||||
{
|
||||
# Compile design files
|
||||
source compile.do 2>&1 | tee -a compile.log
|
||||
|
||||
}
|
||||
|
||||
# RUN_STEP: <simulate>
|
||||
simulate()
|
||||
{
|
||||
runvsimsa -l simulate.log -do "do {simulate.do}"
|
||||
}
|
||||
|
||||
# STEP: setup
|
||||
setup()
|
||||
{
|
||||
case $1 in
|
||||
"-lib_map_path" )
|
||||
if [[ ($2 == "") ]]; then
|
||||
echo -e "ERROR: Simulation library directory path not specified (type \"./ila_cal.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
map_setup_file $2
|
||||
;;
|
||||
"-reset_run" )
|
||||
reset_run
|
||||
echo -e "INFO: Simulation run files deleted.\n"
|
||||
exit 0
|
||||
;;
|
||||
"-noclean_files" )
|
||||
# do not remove previous data
|
||||
;;
|
||||
* )
|
||||
map_setup_file $2
|
||||
esac
|
||||
|
||||
# Add any setup/initialization commands here:-
|
||||
|
||||
# <user specific commands>
|
||||
|
||||
}
|
||||
|
||||
# Map library.cfg file
|
||||
map_setup_file()
|
||||
{
|
||||
file="library.cfg"
|
||||
lib_map_path=""
|
||||
if [[ ($1 != "") ]]; then
|
||||
lib_map_path="$1"
|
||||
fi
|
||||
if [[ ($lib_map_path != "") ]]; then
|
||||
src_file="$lib_map_path/$file"
|
||||
if [[ -e $src_file ]]; then
|
||||
vmap -link $lib_map_path
|
||||
fi
|
||||
fi
|
||||
}
|
||||
|
||||
# Delete generated data from the previous run
|
||||
reset_run()
|
||||
{
|
||||
files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera)
|
||||
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
|
||||
file="${files_to_remove[i]}"
|
||||
if [[ -e $file ]]; then
|
||||
rm -rf $file
|
||||
fi
|
||||
done
|
||||
}
|
||||
|
||||
# Check command line arguments
|
||||
check_args()
|
||||
{
|
||||
if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
|
||||
echo -e "ERROR: Unknown option specified '$2' (type \"./ila_cal.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
|
||||
if [[ ($2 == "-help" || $2 == "-h") ]]; then
|
||||
usage
|
||||
fi
|
||||
}
|
||||
|
||||
# Script usage
|
||||
usage()
|
||||
{
|
||||
msg="Usage: ila_cal.sh [-help]\n\
|
||||
Usage: ila_cal.sh [-lib_map_path]\n\
|
||||
Usage: ila_cal.sh [-reset_run]\n\
|
||||
Usage: ila_cal.sh [-noclean_files]\n\n\
|
||||
[-help] -- Print help information for this script\n\n\
|
||||
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
|
||||
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
|
||||
[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
|
||||
from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
|
||||
-noclean_files switch.\n\n\
|
||||
[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
|
||||
echo -e $msg
|
||||
exit 1
|
||||
}
|
||||
|
||||
# Launch script
|
||||
run $1 $2
|
||||
+17
@@ -0,0 +1,17 @@
|
||||
onbreak {quit -force}
|
||||
onerror {quit -force}
|
||||
|
||||
asim -t 1ps +access +r +m+ila_cal -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.ila_cal xil_defaultlib.glbl
|
||||
|
||||
do {wave.do}
|
||||
|
||||
view wave
|
||||
view structure
|
||||
|
||||
do {ila_cal.udo}
|
||||
|
||||
run -all
|
||||
|
||||
endsim
|
||||
|
||||
quit -force
|
||||
@@ -0,0 +1,2 @@
|
||||
add wave *
|
||||
add wave /glbl/GSR
|
||||
@@ -0,0 +1,49 @@
|
||||
################################################################################
|
||||
# Vivado (TM) v2019.1.3 (64-bit)
|
||||
#
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Thu Apr 13 11:50:19 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
1. How to run the generated simulation script:-
|
||||
|
||||
From the shell prompt in the current directory, issue the following command:-
|
||||
|
||||
./ila_cal.sh
|
||||
|
||||
This command will launch the 'compile', 'elaborate' and 'simulate' functions
|
||||
implemented in the script file for the 3-step flow. These functions are called
|
||||
from the main 'run' function in the script file.
|
||||
|
||||
The 'run' function first executes the 'setup' function, the purpose of which is to
|
||||
create simulator specific setup files, create design library mappings and library
|
||||
directories and copy 'glbl.v' from the Vivado software install location into the
|
||||
current directory.
|
||||
|
||||
The 'setup' function is also used for removing the simulator generated data in
|
||||
order to reset the current directory to the original state when export_simulation
|
||||
was launched from Vivado. This generated data can be removed by specifying the
|
||||
'-reset_run' switch to the './ila_cal.sh' script.
|
||||
|
||||
./ila_cal.sh -reset_run
|
||||
|
||||
To keep the generated data from the previous run but regenerate the setup files and
|
||||
library directories, use the '-noclean_files' switch.
|
||||
|
||||
./ila_cal.sh -noclean_files
|
||||
|
||||
For more information on the script, please type './ila_cal.sh -help'.
|
||||
|
||||
2. Additional design information files:-
|
||||
|
||||
export_simulation generates following additional file that can be used for fetching
|
||||
the design files information or for integrating with external custom scripts.
|
||||
|
||||
Name : file_info.txt
|
||||
Purpose: This file contains detail design file information based on the compile order
|
||||
when export_simulation was executed from Vivado. The file contains information
|
||||
about the file type, name, whether it is part of the IP, associated library
|
||||
and the file path information.
|
||||
+5
@@ -0,0 +1,5 @@
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_cal/hdl/verilog"
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_cal/hdl/verilog"
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_cal/hdl/verilog"
|
||||
ila_cal.v,verilog,xil_defaultlib,../../../ip/ila_cal/sim/ila_cal.v,incdir="../../../ip/ila_cal/hdl/verilog"
|
||||
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||
@@ -0,0 +1,71 @@
|
||||
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
+229
@@ -0,0 +1,229 @@
|
||||
#!/bin/bash -f
|
||||
#*********************************************************************************************************
|
||||
# Vivado (TM) v2019.1.3 (64-bit)
|
||||
#
|
||||
# Filename : ila_cal.sh
|
||||
# Simulator : Synopsys Verilog Compiler Simulator
|
||||
# Description : Simulation script for compiling, elaborating and verifying the project source files.
|
||||
# The script will automatically create the design libraries sub-directories in the run
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Thu Apr 13 11:50:19 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
# usage: ila_cal.sh [-help]
|
||||
# usage: ila_cal.sh [-lib_map_path]
|
||||
# usage: ila_cal.sh [-noclean_files]
|
||||
# usage: ila_cal.sh [-reset_run]
|
||||
#
|
||||
# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
|
||||
# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
|
||||
# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
|
||||
# that points to these libraries and rerun export_simulation. For more information about this switch please
|
||||
# type 'export_simulation -help' in the Tcl shell.
|
||||
#
|
||||
# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
|
||||
# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
|
||||
# executing this script. Please type 'ila_cal.sh -help' for more information.
|
||||
#
|
||||
# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
|
||||
#
|
||||
#*********************************************************************************************************
|
||||
|
||||
# Directory path for design sources and include directories (if any) wrt this path
|
||||
ref_dir="."
|
||||
|
||||
# Override directory with 'export_sim_ref_dir' env path value if set in the shell
|
||||
if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
|
||||
ref_dir="$export_sim_ref_dir"
|
||||
fi
|
||||
|
||||
# Command line options
|
||||
vlogan_opts="-full64"
|
||||
vhdlan_opts="-full64"
|
||||
vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log"
|
||||
vcs_sim_opts="-ucli -licqueue -l simulate.log"
|
||||
|
||||
# Design libraries
|
||||
design_libs=(xil_defaultlib xpm)
|
||||
|
||||
# Simulation root library directory
|
||||
sim_lib_dir="vcs_lib"
|
||||
|
||||
# Script info
|
||||
echo -e "ila_cal.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
|
||||
|
||||
# Main steps
|
||||
run()
|
||||
{
|
||||
check_args $# $1
|
||||
setup $1 $2
|
||||
compile
|
||||
elaborate
|
||||
simulate
|
||||
}
|
||||
|
||||
# RUN_STEP: <compile>
|
||||
compile()
|
||||
{
|
||||
# Compile design files
|
||||
vlogan -work xil_defaultlib $vlogan_opts -sverilog +incdir+"$ref_dir/../../../ip/ila_cal/hdl/verilog" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
2>&1 | tee -a vlogan.log
|
||||
|
||||
vhdlan -work xpm $vhdlan_opts \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
2>&1 | tee -a vhdlan.log
|
||||
|
||||
vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../ip/ila_cal/hdl/verilog" \
|
||||
"$ref_dir/../../../ip/ila_cal/sim/ila_cal.v" \
|
||||
2>&1 | tee -a vlogan.log
|
||||
|
||||
|
||||
vlogan -work xil_defaultlib $vlogan_opts +v2k \
|
||||
glbl.v \
|
||||
2>&1 | tee -a vlogan.log
|
||||
|
||||
}
|
||||
|
||||
# RUN_STEP: <elaborate>
|
||||
elaborate()
|
||||
{
|
||||
vcs $vcs_elab_opts xil_defaultlib.ila_cal xil_defaultlib.glbl -o ila_cal_simv
|
||||
}
|
||||
|
||||
# RUN_STEP: <simulate>
|
||||
simulate()
|
||||
{
|
||||
./ila_cal_simv $vcs_sim_opts -do simulate.do
|
||||
}
|
||||
|
||||
# STEP: setup
|
||||
setup()
|
||||
{
|
||||
case $1 in
|
||||
"-lib_map_path" )
|
||||
if [[ ($2 == "") ]]; then
|
||||
echo -e "ERROR: Simulation library directory path not specified (type \"./ila_cal.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
create_lib_mappings $2
|
||||
;;
|
||||
"-reset_run" )
|
||||
reset_run
|
||||
echo -e "INFO: Simulation run files deleted.\n"
|
||||
exit 0
|
||||
;;
|
||||
"-noclean_files" )
|
||||
# do not remove previous data
|
||||
;;
|
||||
* )
|
||||
create_lib_mappings $2
|
||||
esac
|
||||
|
||||
create_lib_dir
|
||||
|
||||
# Add any setup/initialization commands here:-
|
||||
|
||||
# <user specific commands>
|
||||
|
||||
}
|
||||
|
||||
# Define design library mappings
|
||||
create_lib_mappings()
|
||||
{
|
||||
file="synopsys_sim.setup"
|
||||
if [[ -e $file ]]; then
|
||||
if [[ ($1 == "") ]]; then
|
||||
return
|
||||
else
|
||||
rm -rf $file
|
||||
fi
|
||||
fi
|
||||
|
||||
touch $file
|
||||
|
||||
lib_map_path=""
|
||||
if [[ ($1 != "") ]]; then
|
||||
lib_map_path="$1"
|
||||
fi
|
||||
|
||||
for (( i=0; i<${#design_libs[*]}; i++ )); do
|
||||
lib="${design_libs[i]}"
|
||||
mapping="$lib:$sim_lib_dir/$lib"
|
||||
echo $mapping >> $file
|
||||
done
|
||||
|
||||
if [[ ($lib_map_path != "") ]]; then
|
||||
incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup"
|
||||
echo $incl_ref >> $file
|
||||
fi
|
||||
}
|
||||
|
||||
# Create design library directory paths
|
||||
create_lib_dir()
|
||||
{
|
||||
if [[ -e $sim_lib_dir ]]; then
|
||||
rm -rf $sim_lib_dir
|
||||
fi
|
||||
|
||||
for (( i=0; i<${#design_libs[*]}; i++ )); do
|
||||
lib="${design_libs[i]}"
|
||||
lib_dir="$sim_lib_dir/$lib"
|
||||
if [[ ! -e $lib_dir ]]; then
|
||||
mkdir -p $lib_dir
|
||||
fi
|
||||
done
|
||||
}
|
||||
|
||||
# Delete generated data from the previous run
|
||||
reset_run()
|
||||
{
|
||||
files_to_remove=(ucli.key ila_cal_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc ila_cal_simv.daidir)
|
||||
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
|
||||
file="${files_to_remove[i]}"
|
||||
if [[ -e $file ]]; then
|
||||
rm -rf $file
|
||||
fi
|
||||
done
|
||||
|
||||
create_lib_dir
|
||||
}
|
||||
|
||||
# Check command line arguments
|
||||
check_args()
|
||||
{
|
||||
if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
|
||||
echo -e "ERROR: Unknown option specified '$2' (type \"./ila_cal.sh -help\" for more information)\n"
|
||||
exit 1
|
||||
fi
|
||||
|
||||
if [[ ($2 == "-help" || $2 == "-h") ]]; then
|
||||
usage
|
||||
fi
|
||||
}
|
||||
|
||||
# Script usage
|
||||
usage()
|
||||
{
|
||||
msg="Usage: ila_cal.sh [-help]\n\
|
||||
Usage: ila_cal.sh [-lib_map_path]\n\
|
||||
Usage: ila_cal.sh [-reset_run]\n\
|
||||
Usage: ila_cal.sh [-noclean_files]\n\n\
|
||||
[-help] -- Print help information for this script\n\n\
|
||||
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
|
||||
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
|
||||
[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
|
||||
from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
|
||||
-noclean_files switch.\n\n\
|
||||
[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
|
||||
echo -e $msg
|
||||
exit 1
|
||||
}
|
||||
|
||||
# Launch script
|
||||
run $1 $2
|
||||
@@ -0,0 +1,2 @@
|
||||
run
|
||||
quit
|
||||
+48
@@ -0,0 +1,48 @@
|
||||
################################################################################
|
||||
# Vivado (TM) v2019.1.3 (64-bit)
|
||||
#
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Thu Apr 13 11:50:19 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
1. How to run the generated simulation script:-
|
||||
|
||||
From the shell prompt in the current directory, issue the following command:-
|
||||
|
||||
./ila_cal.sh
|
||||
|
||||
This command will launch the 'execute' function for the single-step flow. This
|
||||
function is called from the main 'run' function in the script file.
|
||||
|
||||
The 'run' function first executes the 'setup' function, the purpose of which is to
|
||||
create simulator specific setup files, create design library mappings and library
|
||||
directories and copy 'glbl.v' from the Vivado software install location into the
|
||||
current directory.
|
||||
|
||||
The 'setup' function is also used for removing the simulator generated data in
|
||||
order to reset the current directory to the original state when export_simulation
|
||||
was launched from Vivado. This generated data can be removed by specifying the
|
||||
'-reset_run' switch to the './ila_cal.sh' script.
|
||||
|
||||
./ila_cal.sh -reset_run
|
||||
|
||||
To keep the generated data from the previous run but regenerate the setup files and
|
||||
library directories, use the '-noclean_files' switch.
|
||||
|
||||
./ila_cal.sh -noclean_files
|
||||
|
||||
For more information on the script, please type './ila_cal.sh -help'.
|
||||
|
||||
2. Additional design information files:-
|
||||
|
||||
export_simulation generates following additional file that can be used for fetching
|
||||
the design files information or for integrating with external custom scripts.
|
||||
|
||||
Name : file_info.txt
|
||||
Purpose: This file contains detail design file information based on the compile order
|
||||
when export_simulation was executed from Vivado. The file contains information
|
||||
about the file type, name, whether it is part of the IP, associated library
|
||||
and the file path information.
|
||||
+5
@@ -0,0 +1,5 @@
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_cal/hdl/verilog"
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_cal/hdl/verilog"
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_cal/hdl/verilog"
|
||||
ila_cal.v,verilog,xil_defaultlib,../../../ip/ila_cal/sim/ila_cal.v,incdir="../../../ip/ila_cal/hdl/verilog"
|
||||
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||
@@ -0,0 +1,71 @@
|
||||
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
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Reference in New Issue
Block a user