Archived
first commit after restructuring
This commit is contained in:
@@ -0,0 +1,5 @@
|
||||
*.xcix filter=lfs diff=lfs merge=lfs -text
|
||||
*.csv filter=lfs diff=lfs merge=lfs -text
|
||||
*.dcp filter=lfs diff=lfs merge=lfs -text
|
||||
*_sim_netlist.v filter=lfs diff=lfs merge=lfs -text
|
||||
*_sim_netlist.vhdl filter=lfs diff=lfs merge=lfs -text
|
||||
+57
@@ -0,0 +1,57 @@
|
||||
################################################################################
|
||||
########################## Basic Directory Structure ###########################
|
||||
################################################################################
|
||||
|
||||
# everything
|
||||
*
|
||||
|
||||
# exclude the directory structure
|
||||
!/adi_library/
|
||||
!/adi_library/**/*
|
||||
!/common/
|
||||
!/common/**/*
|
||||
!/custom_ips/
|
||||
!/custom_ips/**/*
|
||||
!/modules/
|
||||
!/modules/**/*
|
||||
!/projects/
|
||||
!/projects/**/*
|
||||
!/template/
|
||||
!/template/**/*
|
||||
!/.gitattributes
|
||||
!/.gitignore
|
||||
!/README.md
|
||||
|
||||
# include gitkeep in template directory only
|
||||
.gitkeep
|
||||
!/template/**/.gitkeep
|
||||
|
||||
################################################################################
|
||||
############################### Modules Specific ###############################
|
||||
################################################################################
|
||||
|
||||
# exclude everything in project directory
|
||||
/modules/*/*/project/
|
||||
|
||||
################################################################################
|
||||
############################# Vivado & SDK Common ##############################
|
||||
################################################################################
|
||||
|
||||
# folders (and all of their contents) that should always be ignored, anywhere
|
||||
# in the repo
|
||||
.Xil/
|
||||
|
||||
# file patterns that should always be ignored (journal files, log files, dump
|
||||
# files that are created upon Vivado/SDK errors)
|
||||
*.jou
|
||||
*.log
|
||||
*.backup.jou
|
||||
*.backup.log
|
||||
*.upgrade_log
|
||||
*.dmp
|
||||
vivado_pid*
|
||||
*~
|
||||
|
||||
# vivado workspace files
|
||||
xsim.dir/
|
||||
xvlog.pb
|
||||
@@ -0,0 +1,232 @@
|
||||
# Vivado Git Repository
|
||||
|
||||
This repository includes all the design sources and third-party reference used in my vivado project.
|
||||
|
||||
## Table of Contents
|
||||
|
||||
- [Vivado Git Repository](#vivado-git-repository)
|
||||
- [Table of Contents](#table-of-contents)
|
||||
- [Background](#background)
|
||||
- [How this repository is constructed?](#how-this-repository-is-constructed)
|
||||
- [Overview](#overview)
|
||||
- [Top Level](#top-level)
|
||||
- [Basic Vivado Project Structure](#basic-vivado-project-structure)
|
||||
- [Demos](#demos)
|
||||
- [RTL Vivado Project Design Demo](#rtl-vivado-project-design-demo)
|
||||
- [RTL Vivado Project Recreate Demo](#rtl-vivado-project-recreate-demo)
|
||||
|
||||
## Background
|
||||
|
||||
Since the day I joined my lab, managing Vivado projects has always been a pain in the ass for me and my colleagues. It was not until I accidentally overwrote the initial version of one of my modules that I realized how crucial revision control is for software/hardware developers. After spending a couple of days learning Vivado revision control tricks, I created this repository.
|
||||
|
||||
## How this repository is constructed?
|
||||
|
||||
This repository is designed to store Vivado project design sources and Verilog/VHDL files primarily, but it can also hold associated MATLAB codes of algorithm verification or data analysis and related documentation explaining how the modules work and things that need to be taken care of when interfacing with the modules.
|
||||
|
||||
### Overview
|
||||
|
||||
``` plain
|
||||
.
|
||||
├── .git
|
||||
├── .gitignore
|
||||
├── README.md
|
||||
├── adi_library/
|
||||
│ └── ...
|
||||
├── common
|
||||
│ ├── adder_tree_ppl.v
|
||||
│ └── ...
|
||||
├── custom_ips
|
||||
│ └── ...
|
||||
├── modules/
|
||||
│ └── xc7k410tffg900-2/
|
||||
│ └── tx_qpsk/
|
||||
│ ├── project.tcl
|
||||
│ ├── constraints
|
||||
│ ├── docs
|
||||
│ ├── ip/
|
||||
│ │ ├── hrc_64_12_025.xcix
|
||||
│ │ ├── coe/
|
||||
│ │ │ └── hrc_64_12_025.coe
|
||||
│ │ └── managed_ip_project/
|
||||
│ │ └── ...
|
||||
│ ├── ipi-bds
|
||||
│ │ └── ...
|
||||
│ ├── rtl/
|
||||
│ │ └── tx_qpsk.v
|
||||
│ ├── scripts
|
||||
│ └── testbenches/
|
||||
│ └── tb_tx_qpsk.v
|
||||
├── projects/
|
||||
│ └── datalink_814/
|
||||
│ └── dl814_k7/
|
||||
│ ├── project.tcl
|
||||
│ ├── constraints/
|
||||
│ │ └── k7410t_ad9516_2ad9361_physical.xdc
|
||||
│ ├── docs
|
||||
│ ├── ip/
|
||||
│ │ ├── sys_clk_gen.xcix
|
||||
│ │ └── managed_ip_project/
|
||||
│ │ └── ...
|
||||
│ ├── ipi-bds/
|
||||
│ │ └── system_bd/
|
||||
│ │ ├── system_bd.bd
|
||||
│ │ └── hdl/
|
||||
│ │ └── system_bd_wrapper.v
|
||||
│ ├── project/
|
||||
│ │ └── project/
|
||||
│ │ ├── project.hw/
|
||||
│ │ │ project.lpr
|
||||
│ │ ├── project.runs/
|
||||
│ │ │ └── impl_1/
|
||||
│ │ │ ├── system_top.bit
|
||||
│ │ │ └── ...
|
||||
│ │ └── project.sdk/
|
||||
│ │ ├── system_top.hdf
|
||||
│ │ ├── dl814_cmos_48m/
|
||||
│ │ │ └── src
|
||||
│ │ │ └── ...
|
||||
│ │ └── dl814_cmos_48m_bsp
|
||||
│ │ └── system.mss
|
||||
│ ├── rtl
|
||||
│ │ ├── system_top.v
|
||||
│ │ └── ...
|
||||
│ ├── scripts
|
||||
│ └── testbenches
|
||||
└── template
|
||||
├── constraints
|
||||
├── docs
|
||||
├── ip
|
||||
├── ipi-bds
|
||||
├── project
|
||||
├── rtl
|
||||
├── scripts
|
||||
└── testbenches
|
||||
|
||||
```
|
||||
|
||||
### Top Level
|
||||
|
||||
The organization of the top level structure is shown in the table below.
|
||||
|
||||
| Name | Description | Synthesis Required | Implementation Required | Bitstream Required |
|
||||
| :-----------: | :------------------------------------------------- | :--: | :--: | :--: |
|
||||
| `adi_library` | ADI no-OS IP Library, built with Xilinx Vivado 2019.1. | N/A | N/A | N/A |
|
||||
| `common` | Common Verilog/VHDL modules that can work solely without other IPs. | Yes | No | No |
|
||||
| `custom_ips` | Custom IPs. | Yes | No | No |
|
||||
| `modules` | Verilog/VHDL modules that work with other IPs, thus the modules are FPGA specific and they are managed in project mode. In the future the modules may also be categorised by different Vivado versions. | Yes | No | No |
|
||||
| `projects` | Engineering project or board specific Vivado projects, that can be run on hardware. | Yes | Yes | Yes |
|
||||
| `template` | Git-friendly Vivado project structure initialization template. (However this folder cannot be managed with git since it is empty.) | N/A | N/A | N/A |
|
||||
| `.gitignore` | gitignore file that tells git which files to ignore. | N/A | N/A | N/A |
|
||||
| `README.md` | This readme. | N/A | N/A | N/A |
|
||||
|
||||
> All Vivado projects that are managed in project mode is named `project` or `projectxxx`, considering that Windows OS limit the file path length to 260 characters.
|
||||
|
||||
### Basic Vivado Project Structure
|
||||
|
||||
As listed above, modules and Vivado projects are managed in project mode, in which Vivado automatically manages the source files, constraints, IPs, run results, and so on. However, the directory structures are not friendly to revision control systems because they contain many redundant files that do not require revision control, such as synthesis and implementation results, and simulation intermediate files.
|
||||
|
||||
Fortunately, Vivado designers have already considered almost everything related to revision control. According to the *Vivado Design Suite User Guide: Design Flows Overview* ([UG892](https://docs.xilinx.com/v/u/2019.1-English/ug892-vivado-design-flows-overview)), the only thing we need to do is **store the design sources outside of the Vivado project directory**.
|
||||
|
||||
The basic git-friendly Vivado project structure is based on [UG892](https://docs.xilinx.com/v/u/2019.1-English/ug892-vivado-design-flows-overview) and several Vivado quick take videos.
|
||||
|
||||
1. [*Using Vivado Design Suite with Revision Control*](https://www.xilinx.com/video/hardware/vivado-design-suite-revision-control.html): explains basic concepts of Vivado revision control.
|
||||
|
||||
2. [*Configuring and Managing Reusable IP in Vivado*](https://www.xilinx.com/video/hardware/configuring-managing-reusable-ip-vivado.html): includes how to use Vivado Manage IP project.
|
||||
|
||||
3. [*IP Revision Control*](https://www.xilinx.com/video/hardware/ip-revision-control.html): mainly focuses on the new feature of Vivado 2021.1 that makes revision control easier.
|
||||
|
||||
The repository follows a **maximum flexibility** revision control strategy, wherein **all output products undergo revision control** to reduce the Vivado project rebuild time and provide an option of using IP in future releases of Vivado without upgrading.
|
||||
|
||||
The table below outlines the git-friendly Vivado project structure. It is important to note that all items listed, except for most files in the `project` directory, will be under revision control. For additional information, please refer to the .gitignore file.
|
||||
|
||||
| Name | Description |
|
||||
| :-----------: | :---------- |
|
||||
| `rtl` | All RTL-based source files including .include files. |
|
||||
| `ip` | The IP source files and output products. The IPs are stored using **core container** feature, and managed by Vivado **Manage IP** project. |
|
||||
| `ipi-bds` | The IP Integrator block design source file (.bd), along with IP subdirectory including IP source files and output products. |
|
||||
| `testbenches` | Simulation test benches and stimulus files. |
|
||||
| `constraints` | All XDC constraint files and Tcl commands used as constraints. |
|
||||
| `project` | Vivado project directory. For single project mode, there is no project subdirectories needed; for multi project mode, each project is stored in a subdirectory containing a single Vivado project. It should be noted that the `.gitignore` is different for single project mode and multi project mode, because the directory depth are not the same. Therefore, `.gitignore` should always be checked before the first commit. |
|
||||
| `scripts` | Run scripts used to compile the design including any pre and post scripts used when launching runs, along with any other custom scripts such as MATLAB scripts. |
|
||||
| `docs` | Any design related documentations, specifications, reports, etc. |
|
||||
| `project.tcl` | The script used to recreate the associated Vivado project. |
|
||||
|
||||
## Demos
|
||||
|
||||
### RTL Vivado Project Design Demo
|
||||
|
||||
1. Initialize project directory structure
|
||||
|
||||
Copy the `./template` folder to target engineering project folder (`./projects/<engProj>`). Then rename the folder to `<gitProj>`.
|
||||
|
||||
2. Create Vivado RTL Project
|
||||
|
||||
- For **single project mode**, create Vivado RTL Project named `project` in `./projects/<engProj>/<gitProj>/project` with option `Create project subdirectory` *unchecked* . The location of the Vivado project should be `./projects/<engProj>/<gitProj>/project`.
|
||||
|
||||
- For **multi project mode**, create Vivado RTL Project named `<vivadoProj>` in `./projects/<engProj>/<gitProj>/project` with option `Create project subdirectory` *checked* . The location of the Vivado project should be `./projects/<engProj>/<gitProj>/project/<vivadoProj>`.
|
||||
|
||||
3. Add RTL sources
|
||||
|
||||
- **Add** existing RTL sources (e.g. `./projects/<engProj>/<gitProj>/rtl/<rtlName>.v`) via **File -> Add Sources -> Add or create design sources -> Add Files** with option `Copy sources into project` *unchecked*.
|
||||
|
||||
- **Create** new RTL sources via **File -> Add Sources -> Add or create design sources -> Create File**, change the `File location` to `./projects/<engProj>/<gitProj>/rtl`. Several subdirectories can be created to group modules with distinct functions.
|
||||
|
||||
4. Add IP
|
||||
|
||||
- **Add** existing IP (e.g. `./projects/<engProj>/<gitProj>/ip/<ipName>.xcix`) via **File -> Add Sources -> Add or create design sources -> Add Files** with option `Copy sources into project` *unchecked*.
|
||||
|
||||
- **Create** new IP. First, create Manage IP project with `IP location` at `./projects/<engProj>/<gitProj>/ip`. Then, use the Manage IP project to customize and manage IP, and generate output products. Finally, add IP `./projects/<engProj>/<gitProj>/ip/<ipName>.xcix` via **ile -> Add Sources -> Add or create design sources -> Create File** to the Vivado project with option `Copy sources into project` *unchecked*. Several subdirectories can be created to group IPs with distinct functions.
|
||||
|
||||
5. Add IPI Block Design
|
||||
|
||||
- **Add** existing ipi-bd file (e.g. `./projects/<engProj>/<gitProj>/ipi-bds/<bdName>/<bdName>.bd`) and its wrapper (assuming the wrapper is generated with option `Let Vivado manage wrapper and auto-update`, e.g. `./projects/<engProj>/<gitProj>/ipi-bds/<bdName>/hdl/<bdName>_wrapper.v`) via **File -> Add Sources -> Add or create design sources -> Add Files**, with option `Copy sources into project` unchecked.
|
||||
|
||||
- **Create** new ipi-bd via **Flow -> Create Block Design**, change the `Directory` to `./projects/<engProj>/<gitProj>/ipi-bds`. Once the IPI design is complete, generate the wrapper with option `Let Vivado manage wrapper and auto-update`.
|
||||
|
||||
6. Add Constraints
|
||||
|
||||
- **Add** existing constraint file (e.g. `./projects/<engProj>/<gitProj>/constraints/<constraintName>.xdc`) via **File -> Add Sources -> Add or create constraints -> Add Files** with option `Copy constraints files into project` *unchecked*.
|
||||
|
||||
- **Create** new constraint file via **File -> Add Sources -> Add or create constraints -> Create File**, change the `File location` to `./projects/<engProj>/<gitProj>/constraints`. Several subdirectories may be created to group constraints with distinct functions.
|
||||
|
||||
- Create new constraints with GUI interactively. Remember to change the `File location` to `./projects/<engProj>/<gitProj>/constraints` before saving any constrains.
|
||||
|
||||
7. Add Simulation Sources
|
||||
|
||||
- **Add** existing testbench (e.g. `./projects/<engProj>/<gitProj>/testbenches/<testbenchName>.v`) via **File -> Add Sources -> Add or create simulation sources -> Add Files** with option `Copy sources into project` *unchecked*.
|
||||
|
||||
- **Create** new testbenches via **File -> Add Sources -> Add or create simulation sources -> Create File**, change the `File location` to `./projects/<engProj>/<gitProj>/testbenches`. Several subdirectories can be created to group modules with distinct functions.
|
||||
|
||||
> The stimulus files should be included in `testbenches` folder.
|
||||
|
||||
8. Run Synthesis, Implementation and Generate Bitstream via **Flow -> Run Synthesis**, **Flow -> Run Implementation** and **Flow -> Generate Bitstream**
|
||||
|
||||
9. (Optional) Export Hardware and Develop Xilinx SDK/Vitis Programmes
|
||||
|
||||
10. Generate Project Recreation Script
|
||||
|
||||
Create new script used to recreate the Vivado project via **File -> Project -> Write Tcl** with all checkbox set as default, set `Output File` to be `./projects/<engProj>/<gitProj>/project.tcl`.
|
||||
|
||||
11. (Optional) Archive Project
|
||||
|
||||
Archive the Vivado project into a compressed zip file via **File -> Archive**, change `Archive location` to anywhere except the git repository, because the archived project is currently not under revision control. The archive command copies all local or remote sources and run results, so the archive is self-contained.
|
||||
|
||||
### RTL Vivado Project Recreate Demo
|
||||
|
||||
1. Pull the Repository to Local (Sparse checkout Recommended).
|
||||
|
||||
2. Source the Project Script
|
||||
|
||||
Open Vivado. In Tcl Console, change current working directory to `./projects/<engProj>/<gitProj>`.
|
||||
|
||||
``` tcl
|
||||
cd ./projects/<engProj>/<gitProj>
|
||||
```
|
||||
|
||||
Make sure all files included the script header are present, then source the script.
|
||||
|
||||
``` tcl
|
||||
source ./project.tcl
|
||||
```
|
||||
|
||||
> Xilinx recommends sourcing the Tcl script from the same directory in which the project was created, to maintain the relative path between the current working directory and the source files.
|
||||
@@ -0,0 +1,239 @@
|
||||
####################################################################################
|
||||
####################################################################################
|
||||
## Copyright 2011(c) Analog Devices, Inc.
|
||||
## Auto-generated, do not modify!
|
||||
####################################################################################
|
||||
####################################################################################
|
||||
|
||||
include ../quiet.mk
|
||||
|
||||
.PHONY: all lib clean clean-all
|
||||
all: lib
|
||||
|
||||
|
||||
clean:
|
||||
$(MAKE) -C axi_ad5766 clean
|
||||
$(MAKE) -C axi_ad6676 clean
|
||||
$(MAKE) -C axi_ad7616 clean
|
||||
$(MAKE) -C axi_ad9122 clean
|
||||
$(MAKE) -C axi_ad9144 clean
|
||||
$(MAKE) -C axi_ad9152 clean
|
||||
$(MAKE) -C axi_ad9162 clean
|
||||
$(MAKE) -C axi_ad9250 clean
|
||||
$(MAKE) -C axi_ad9265 clean
|
||||
$(MAKE) -C axi_ad9361 clean
|
||||
$(MAKE) -C axi_ad9371 clean
|
||||
$(MAKE) -C axi_ad9434 clean
|
||||
$(MAKE) -C axi_ad9467 clean
|
||||
$(MAKE) -C axi_ad9625 clean
|
||||
$(MAKE) -C axi_ad9671 clean
|
||||
$(MAKE) -C axi_ad9680 clean
|
||||
$(MAKE) -C axi_ad9684 clean
|
||||
$(MAKE) -C axi_ad9739a clean
|
||||
$(MAKE) -C axi_ad9963 clean
|
||||
$(MAKE) -C axi_adc_decimate clean
|
||||
$(MAKE) -C axi_adc_trigger clean
|
||||
$(MAKE) -C axi_adrv9001 clean
|
||||
$(MAKE) -C axi_adrv9009 clean
|
||||
$(MAKE) -C axi_clkgen clean
|
||||
$(MAKE) -C axi_dac_interpolate clean
|
||||
$(MAKE) -C axi_dmac clean
|
||||
$(MAKE) -C axi_fan_control clean
|
||||
$(MAKE) -C axi_fmcadc5_sync clean
|
||||
$(MAKE) -C axi_generic_adc clean
|
||||
$(MAKE) -C axi_gpreg clean
|
||||
$(MAKE) -C axi_hdmi_rx clean
|
||||
$(MAKE) -C axi_hdmi_tx clean
|
||||
$(MAKE) -C axi_i2s_adi clean
|
||||
$(MAKE) -C axi_intr_monitor clean
|
||||
$(MAKE) -C axi_laser_driver clean
|
||||
$(MAKE) -C axi_logic_analyzer clean
|
||||
$(MAKE) -C axi_mc_controller clean
|
||||
$(MAKE) -C axi_mc_current_monitor clean
|
||||
$(MAKE) -C axi_mc_speed clean
|
||||
$(MAKE) -C axi_pulse_gen clean
|
||||
$(MAKE) -C axi_rd_wr_combiner clean
|
||||
$(MAKE) -C axi_spdif_rx clean
|
||||
$(MAKE) -C axi_spdif_tx clean
|
||||
$(MAKE) -C axi_sysid clean
|
||||
$(MAKE) -C axi_usb_fx3 clean
|
||||
$(MAKE) -C cn0363/cn0363_dma_sequencer clean
|
||||
$(MAKE) -C cn0363/cn0363_phase_data_sync clean
|
||||
$(MAKE) -C cordic_demod clean
|
||||
$(MAKE) -C intel/adi_jesd204 clean
|
||||
$(MAKE) -C intel/avl_adxcfg clean
|
||||
$(MAKE) -C intel/avl_adxcvr clean
|
||||
$(MAKE) -C intel/avl_adxcvr_octet_swap clean
|
||||
$(MAKE) -C intel/avl_adxphy clean
|
||||
$(MAKE) -C intel/avl_dacfifo clean
|
||||
$(MAKE) -C intel/axi_adxcvr clean
|
||||
$(MAKE) -C intel/common/intel_mem_asym clean
|
||||
$(MAKE) -C intel/common/intel_serdes clean
|
||||
$(MAKE) -C intel/jesd204_phy clean
|
||||
$(MAKE) -C intel/util_clkdiv clean
|
||||
$(MAKE) -C jesd204/ad_ip_jesd204_tpl_adc clean
|
||||
$(MAKE) -C jesd204/ad_ip_jesd204_tpl_dac clean
|
||||
$(MAKE) -C jesd204/axi_jesd204_common clean
|
||||
$(MAKE) -C jesd204/axi_jesd204_rx clean
|
||||
$(MAKE) -C jesd204/axi_jesd204_tx clean
|
||||
$(MAKE) -C jesd204/jesd204_common clean
|
||||
$(MAKE) -C jesd204/jesd204_rx clean
|
||||
$(MAKE) -C jesd204/jesd204_rx_static_config clean
|
||||
$(MAKE) -C jesd204/jesd204_soft_pcs_rx clean
|
||||
$(MAKE) -C jesd204/jesd204_soft_pcs_tx clean
|
||||
$(MAKE) -C jesd204/jesd204_tx clean
|
||||
$(MAKE) -C jesd204/jesd204_tx_static_config clean
|
||||
$(MAKE) -C spi_engine/axi_spi_engine clean
|
||||
$(MAKE) -C spi_engine/spi_engine_execution clean
|
||||
$(MAKE) -C spi_engine/spi_engine_interconnect clean
|
||||
$(MAKE) -C spi_engine/spi_engine_offload clean
|
||||
$(MAKE) -C sysid_rom clean
|
||||
$(MAKE) -C util_adcfifo clean
|
||||
$(MAKE) -C util_axis_fifo clean
|
||||
$(MAKE) -C util_axis_resize clean
|
||||
$(MAKE) -C util_axis_upscale clean
|
||||
$(MAKE) -C util_bsplit clean
|
||||
$(MAKE) -C util_cdc clean
|
||||
$(MAKE) -C util_cic clean
|
||||
$(MAKE) -C util_dacfifo clean
|
||||
$(MAKE) -C util_dec256sinc24b clean
|
||||
$(MAKE) -C util_delay clean
|
||||
$(MAKE) -C util_extract clean
|
||||
$(MAKE) -C util_fir_dec clean
|
||||
$(MAKE) -C util_fir_int clean
|
||||
$(MAKE) -C util_gmii_to_rgmii clean
|
||||
$(MAKE) -C util_i2c_mixer clean
|
||||
$(MAKE) -C util_mfifo clean
|
||||
$(MAKE) -C util_pack/util_cpack2 clean
|
||||
$(MAKE) -C util_pack/util_upack2 clean
|
||||
$(MAKE) -C util_pulse_gen clean
|
||||
$(MAKE) -C util_rfifo clean
|
||||
$(MAKE) -C util_sigma_delta_spi clean
|
||||
$(MAKE) -C util_tdd_sync clean
|
||||
$(MAKE) -C util_var_fifo clean
|
||||
$(MAKE) -C util_wfifo clean
|
||||
$(MAKE) -C xilinx/axi_adcfifo clean
|
||||
$(MAKE) -C xilinx/axi_adxcvr clean
|
||||
$(MAKE) -C xilinx/axi_dacfifo clean
|
||||
$(MAKE) -C xilinx/axi_xcvrlb clean
|
||||
$(MAKE) -C xilinx/util_adxcvr clean
|
||||
$(MAKE) -C xilinx/util_clkdiv clean
|
||||
|
||||
$(MAKE) -C interfaces clean
|
||||
|
||||
|
||||
clean-all:clean
|
||||
|
||||
|
||||
lib:
|
||||
$(MAKE) -C axi_ad5766
|
||||
$(MAKE) -C axi_ad6676
|
||||
$(MAKE) -C axi_ad7616
|
||||
$(MAKE) -C axi_ad9122
|
||||
$(MAKE) -C axi_ad9144
|
||||
$(MAKE) -C axi_ad9152
|
||||
$(MAKE) -C axi_ad9162
|
||||
$(MAKE) -C axi_ad9250
|
||||
$(MAKE) -C axi_ad9265
|
||||
$(MAKE) -C axi_ad9361
|
||||
$(MAKE) -C axi_ad9371
|
||||
$(MAKE) -C axi_ad9434
|
||||
$(MAKE) -C axi_ad9467
|
||||
$(MAKE) -C axi_ad9625
|
||||
$(MAKE) -C axi_ad9671
|
||||
$(MAKE) -C axi_ad9680
|
||||
$(MAKE) -C axi_ad9684
|
||||
$(MAKE) -C axi_ad9739a
|
||||
$(MAKE) -C axi_ad9963
|
||||
$(MAKE) -C axi_adc_decimate
|
||||
$(MAKE) -C axi_adc_trigger
|
||||
$(MAKE) -C axi_adrv9001
|
||||
$(MAKE) -C axi_adrv9009
|
||||
$(MAKE) -C axi_clkgen
|
||||
$(MAKE) -C axi_dac_interpolate
|
||||
$(MAKE) -C axi_dmac
|
||||
$(MAKE) -C axi_fan_control
|
||||
$(MAKE) -C axi_fmcadc5_sync
|
||||
$(MAKE) -C axi_generic_adc
|
||||
$(MAKE) -C axi_gpreg
|
||||
$(MAKE) -C axi_hdmi_rx
|
||||
$(MAKE) -C axi_hdmi_tx
|
||||
$(MAKE) -C axi_i2s_adi
|
||||
$(MAKE) -C axi_intr_monitor
|
||||
$(MAKE) -C axi_laser_driver
|
||||
$(MAKE) -C axi_logic_analyzer
|
||||
$(MAKE) -C axi_mc_controller
|
||||
$(MAKE) -C axi_mc_current_monitor
|
||||
$(MAKE) -C axi_mc_speed
|
||||
$(MAKE) -C axi_pulse_gen
|
||||
$(MAKE) -C axi_rd_wr_combiner
|
||||
$(MAKE) -C axi_spdif_rx
|
||||
$(MAKE) -C axi_spdif_tx
|
||||
$(MAKE) -C axi_sysid
|
||||
$(MAKE) -C axi_usb_fx3
|
||||
$(MAKE) -C cn0363/cn0363_dma_sequencer
|
||||
$(MAKE) -C cn0363/cn0363_phase_data_sync
|
||||
$(MAKE) -C cordic_demod
|
||||
$(MAKE) -C intel/adi_jesd204
|
||||
$(MAKE) -C intel/avl_adxcfg
|
||||
$(MAKE) -C intel/avl_adxcvr
|
||||
$(MAKE) -C intel/avl_adxcvr_octet_swap
|
||||
$(MAKE) -C intel/avl_adxphy
|
||||
$(MAKE) -C intel/avl_dacfifo
|
||||
$(MAKE) -C intel/axi_adxcvr
|
||||
$(MAKE) -C intel/common/intel_mem_asym
|
||||
$(MAKE) -C intel/common/intel_serdes
|
||||
$(MAKE) -C intel/jesd204_phy
|
||||
$(MAKE) -C intel/util_clkdiv
|
||||
$(MAKE) -C jesd204/ad_ip_jesd204_tpl_adc
|
||||
$(MAKE) -C jesd204/ad_ip_jesd204_tpl_dac
|
||||
$(MAKE) -C jesd204/axi_jesd204_common
|
||||
$(MAKE) -C jesd204/axi_jesd204_rx
|
||||
$(MAKE) -C jesd204/axi_jesd204_tx
|
||||
$(MAKE) -C jesd204/jesd204_common
|
||||
$(MAKE) -C jesd204/jesd204_rx
|
||||
$(MAKE) -C jesd204/jesd204_rx_static_config
|
||||
$(MAKE) -C jesd204/jesd204_soft_pcs_rx
|
||||
$(MAKE) -C jesd204/jesd204_soft_pcs_tx
|
||||
$(MAKE) -C jesd204/jesd204_tx
|
||||
$(MAKE) -C jesd204/jesd204_tx_static_config
|
||||
$(MAKE) -C spi_engine/axi_spi_engine
|
||||
$(MAKE) -C spi_engine/spi_engine_execution
|
||||
$(MAKE) -C spi_engine/spi_engine_interconnect
|
||||
$(MAKE) -C spi_engine/spi_engine_offload
|
||||
$(MAKE) -C sysid_rom
|
||||
$(MAKE) -C util_adcfifo
|
||||
$(MAKE) -C util_axis_fifo
|
||||
$(MAKE) -C util_axis_resize
|
||||
$(MAKE) -C util_axis_upscale
|
||||
$(MAKE) -C util_bsplit
|
||||
$(MAKE) -C util_cdc
|
||||
$(MAKE) -C util_cic
|
||||
$(MAKE) -C util_dacfifo
|
||||
$(MAKE) -C util_dec256sinc24b
|
||||
$(MAKE) -C util_delay
|
||||
$(MAKE) -C util_extract
|
||||
$(MAKE) -C util_fir_dec
|
||||
$(MAKE) -C util_fir_int
|
||||
$(MAKE) -C util_gmii_to_rgmii
|
||||
$(MAKE) -C util_i2c_mixer
|
||||
$(MAKE) -C util_mfifo
|
||||
$(MAKE) -C util_pack/util_cpack2
|
||||
$(MAKE) -C util_pack/util_upack2
|
||||
$(MAKE) -C util_pulse_gen
|
||||
$(MAKE) -C util_rfifo
|
||||
$(MAKE) -C util_sigma_delta_spi
|
||||
$(MAKE) -C util_tdd_sync
|
||||
$(MAKE) -C util_var_fifo
|
||||
$(MAKE) -C util_wfifo
|
||||
$(MAKE) -C xilinx/axi_adcfifo
|
||||
$(MAKE) -C xilinx/axi_adxcvr
|
||||
$(MAKE) -C xilinx/axi_dacfifo
|
||||
$(MAKE) -C xilinx/axi_xcvrlb
|
||||
$(MAKE) -C xilinx/util_adxcvr
|
||||
$(MAKE) -C xilinx/util_clkdiv
|
||||
|
||||
$(MAKE) -C interfaces
|
||||
|
||||
####################################################################################
|
||||
####################################################################################
|
||||
@@ -0,0 +1,27 @@
|
||||
####################################################################################
|
||||
## Copyright 2018(c) Analog Devices, Inc.
|
||||
## Auto-generated, do not modify!
|
||||
####################################################################################
|
||||
|
||||
LIBRARY_NAME := axi_ad5766
|
||||
|
||||
GENERIC_DEPS += ../common/ad_rst.v
|
||||
GENERIC_DEPS += ../common/up_axi.v
|
||||
GENERIC_DEPS += ../common/up_clock_mon.v
|
||||
GENERIC_DEPS += ../common/up_dac_common.v
|
||||
GENERIC_DEPS += ../common/up_xfer_cntrl.v
|
||||
GENERIC_DEPS += ../common/up_xfer_status.v
|
||||
GENERIC_DEPS += ../common/util_pulse_gen.v
|
||||
GENERIC_DEPS += axi_ad5766.v
|
||||
GENERIC_DEPS += up_ad5766_sequencer.v
|
||||
|
||||
XILINX_DEPS += axi_ad5766_ip.tcl
|
||||
|
||||
XILINX_DEPS += ../spi_engine/interfaces/spi_engine_ctrl.xml
|
||||
XILINX_DEPS += ../spi_engine/interfaces/spi_engine_ctrl_rtl.xml
|
||||
XILINX_DEPS += ../spi_engine/interfaces/spi_engine_offload_ctrl.xml
|
||||
XILINX_DEPS += ../spi_engine/interfaces/spi_engine_offload_ctrl_rtl.xml
|
||||
|
||||
XILINX_LIB_DEPS += util_cdc
|
||||
|
||||
include ../scripts/library.mk
|
||||
@@ -0,0 +1,3 @@
|
||||
version:1
|
||||
6d6f64655f636f756e7465727c42617463684d6f6465:1
|
||||
eof:
|
||||
@@ -0,0 +1,6 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<labtools version="1" minor="0"/>
|
||||
@@ -0,0 +1,434 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module axi_ad5766 #(
|
||||
|
||||
parameter FPGA_TECHNOLOGY = 0,
|
||||
parameter FPGA_FAMILY = 0,
|
||||
parameter SPEED_GRADE = 0,
|
||||
parameter DEV_PACKAGE = 0,
|
||||
parameter ASYNC_SPI_CLK = 0,
|
||||
parameter CMD_MEM_ADDRESS_WIDTH = 4,
|
||||
parameter SDO_MEM_ADDRESS_WIDTH = 4)(
|
||||
|
||||
// Slave AXI interface
|
||||
|
||||
input s_axi_aclk,
|
||||
input s_axi_aresetn,
|
||||
input s_axi_awvalid,
|
||||
input [15:0] s_axi_awaddr,
|
||||
output s_axi_awready,
|
||||
input [ 2:0] s_axi_awprot,
|
||||
input s_axi_wvalid,
|
||||
input [31:0] s_axi_wdata,
|
||||
input [ 3:0] s_axi_wstrb,
|
||||
output s_axi_wready,
|
||||
output s_axi_bvalid,
|
||||
output [ 1:0] s_axi_bresp,
|
||||
input s_axi_bready,
|
||||
input s_axi_arvalid,
|
||||
input [15:0] s_axi_araddr,
|
||||
output s_axi_arready,
|
||||
input [ 2:0] s_axi_arprot,
|
||||
output s_axi_rvalid,
|
||||
input s_axi_rready,
|
||||
output [ 1:0] s_axi_rresp,
|
||||
output [31:0] s_axi_rdata,
|
||||
|
||||
// FIFO transmit
|
||||
|
||||
output dma_clk,
|
||||
output reg dma_valid,
|
||||
input dma_enable,
|
||||
input [15:0] dma_data,
|
||||
input dma_xfer_req,
|
||||
input dma_underflow,
|
||||
|
||||
// SPI engine control interface (to the SPI engine interconnect)
|
||||
|
||||
input spi_clk, // should be connected to up_clk
|
||||
input spi_resetn,
|
||||
|
||||
input cmd_ready,
|
||||
output cmd_valid,
|
||||
output [15:0] cmd_data,
|
||||
|
||||
input sdo_data_ready,
|
||||
output sdo_data_valid,
|
||||
output [ 7:0] sdo_data,
|
||||
|
||||
output sdi_data_ready,
|
||||
input sdi_data_valid,
|
||||
input [ 7:0] sdi_data,
|
||||
|
||||
output sync_ready,
|
||||
input sync_valid,
|
||||
input [ 7:0] sync_data,
|
||||
|
||||
// SPI engine offload interface (to the AXI SPI engine)
|
||||
|
||||
input ctrl_clk,
|
||||
input ctrl_cmd_wr_en,
|
||||
input [15:0] ctrl_cmd_wr_data,
|
||||
|
||||
input ctrl_enable,
|
||||
output ctrl_enabled,
|
||||
input ctrl_mem_reset);
|
||||
|
||||
// internal wires
|
||||
|
||||
wire up_wreq_s;
|
||||
wire [13:0] up_waddr_s;
|
||||
wire [31:0] up_wdata_s;
|
||||
wire up_rreq_s;
|
||||
wire [13:0] up_raddr_s;
|
||||
wire [31:0] up_rdata_s[0:1];
|
||||
wire up_rack_s[0:1];
|
||||
wire up_wack_s[0:1];
|
||||
wire trigger_s;
|
||||
wire [31:0] pulse_period_s;
|
||||
wire [15:0] dac_datarate_s;
|
||||
wire spi_reset;
|
||||
wire spi_enable_s;
|
||||
wire [ 3:0] sequencer[15:0];
|
||||
wire [ 3:0] cmd_bits;
|
||||
wire [ 3:0] end_of_sequence;
|
||||
wire spi_mem_reset_s;
|
||||
wire sequence_valid_s;
|
||||
wire [ 7:0] sequence_data_s;
|
||||
wire dac_rst_s;
|
||||
wire dac_rstn_s;
|
||||
wire [CMD_MEM_ADDRESS_WIDTH-1:0] spi_cmd_rd_addr_next;
|
||||
|
||||
// registers
|
||||
|
||||
reg [31:0] up_rdata = 32'b0;
|
||||
reg up_rack = 0;
|
||||
reg up_wack = 1'b0;
|
||||
reg [15:0] cmd_mem[0:2**CMD_MEM_ADDRESS_WIDTH-1];
|
||||
reg [ 7:0] sdo_mem[0:2];
|
||||
reg [CMD_MEM_ADDRESS_WIDTH-1:0] ctrl_cmd_wr_addr = 'b0;
|
||||
reg [CMD_MEM_ADDRESS_WIDTH-1:0] spi_cmd_rd_addr = 'b0;
|
||||
reg [SDO_MEM_ADDRESS_WIDTH-1:0] ctrl_sdo_wr_addr = 'b0;
|
||||
reg [SDO_MEM_ADDRESS_WIDTH-1:0] spi_sdo_rd_addr = 'b0;
|
||||
reg spi_active = 1'b0;
|
||||
|
||||
assign up_rstn = s_axi_aresetn;
|
||||
|
||||
// the dma interface runs on SPI_CLK
|
||||
|
||||
assign dma_clk = spi_clk;
|
||||
|
||||
// command and SDO data offload
|
||||
|
||||
assign cmd_valid = spi_active;
|
||||
assign cmd_data = cmd_mem[spi_cmd_rd_addr];
|
||||
assign sdo_data_valid = spi_active;
|
||||
assign sdo_data = sdo_mem[spi_sdo_rd_addr];
|
||||
assign sync_ready = 1'b1;
|
||||
|
||||
assign sdi_data_ready = 1'b0;
|
||||
|
||||
generate if (ASYNC_SPI_CLK) begin
|
||||
|
||||
/*
|
||||
* The synchronization circuit takes care that there are no glitches on the
|
||||
* ctrl_enabled signal. ctrl_do_enable is asserted whenever ctrl_enable is
|
||||
* asserted, but only deasserted once the signal has been synchronized back from
|
||||
* the SPI domain. This makes sure that we can't end up in a state where the
|
||||
* enable signal in the SPI domain is asserted, but neither enable nor enabled
|
||||
* is asserted in the control domain.
|
||||
*/
|
||||
|
||||
reg ctrl_do_enable = 1'b0;
|
||||
wire ctrl_is_enabled;
|
||||
reg spi_enabled = 1'b0;
|
||||
|
||||
always @(posedge ctrl_clk) begin
|
||||
if (ctrl_enable == 1'b1) begin
|
||||
ctrl_do_enable <= 1'b1;
|
||||
end else if (ctrl_is_enabled == 1'b1) begin
|
||||
ctrl_do_enable <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
assign ctrl_enabled = ctrl_is_enabled | ctrl_do_enable;
|
||||
|
||||
always @(posedge spi_clk) begin
|
||||
spi_enabled <= spi_enable_s | spi_active;
|
||||
end
|
||||
|
||||
sync_bits # (
|
||||
.NUM_OF_BITS(1),
|
||||
.ASYNC_CLK(1)
|
||||
) i_sync_enable (
|
||||
.in_bits(ctrl_do_enable),
|
||||
.out_clk(spi_clk),
|
||||
.out_resetn(1'b1),
|
||||
.out_bits(spi_enable_s)
|
||||
);
|
||||
|
||||
sync_bits # (
|
||||
.NUM_OF_BITS(1),
|
||||
.ASYNC_CLK(1)
|
||||
) i_sync_enabled (
|
||||
.in_bits(spi_enabled),
|
||||
.out_clk(ctrl_clk),
|
||||
.out_resetn(1'b1),
|
||||
.out_bits(ctrl_is_enabled)
|
||||
);
|
||||
|
||||
sync_bits # (
|
||||
.NUM_OF_BITS(1),
|
||||
.ASYNC_CLK(1)
|
||||
) i_sync_mem_reset (
|
||||
.in_bits(ctrl_mem_reset),
|
||||
.out_clk(spi_clk),
|
||||
.out_resetn(1'b1),
|
||||
.out_bits(spi_mem_reset_s)
|
||||
);
|
||||
|
||||
end else begin
|
||||
assign spi_enable_s = ctrl_enable;
|
||||
assign ctrl_enabled = spi_enable_s | spi_active;
|
||||
assign spi_mem_reset_s = ctrl_mem_reset;
|
||||
end endgenerate
|
||||
|
||||
assign spi_cmd_rd_addr_next = spi_cmd_rd_addr + 1;
|
||||
|
||||
always @(posedge spi_clk) begin
|
||||
if (spi_resetn == 1'b0) begin
|
||||
spi_active <= 1'b0;
|
||||
end else begin
|
||||
if (spi_active == 1'b0) begin
|
||||
if ((trigger_s == 1'b1 && spi_enable_s == 1'b1)) begin
|
||||
spi_active <= 1'b1;
|
||||
end
|
||||
end else if (cmd_ready == 1'b1 && spi_cmd_rd_addr_next == ctrl_cmd_wr_addr) begin
|
||||
spi_active <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge spi_clk) begin
|
||||
if (cmd_valid == 1'b0) begin
|
||||
spi_cmd_rd_addr <= 'h00;
|
||||
end else if (cmd_ready == 1'b1) begin
|
||||
spi_cmd_rd_addr <= spi_cmd_rd_addr_next;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge spi_clk) begin
|
||||
if (spi_active == 1'b0) begin
|
||||
spi_sdo_rd_addr <= 'h00;
|
||||
end else if (sdo_data_ready == 1'b1) begin
|
||||
spi_sdo_rd_addr <= spi_sdo_rd_addr + 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge ctrl_clk) begin
|
||||
if (ctrl_cmd_wr_en == 1'b1) begin
|
||||
cmd_mem[ctrl_cmd_wr_addr] <= ctrl_cmd_wr_data;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge ctrl_clk) begin
|
||||
if (ctrl_mem_reset == 1'b1) begin
|
||||
ctrl_cmd_wr_addr <= 0;
|
||||
end else if (ctrl_cmd_wr_en == 1'b1) begin
|
||||
ctrl_cmd_wr_addr <= ctrl_cmd_wr_addr + 1;
|
||||
end
|
||||
end
|
||||
|
||||
// request data from the DMA at the desired rate
|
||||
|
||||
always @(posedge dma_clk) begin
|
||||
if (dma_xfer_req == 1'b0) begin
|
||||
dma_valid <= 1'b0;
|
||||
end else begin
|
||||
if ((trigger_s == 1'b1) && (dma_enable == 1'b1) && (spi_enable_s == 1'b1)) begin
|
||||
dma_valid <= 1'b1;
|
||||
end
|
||||
if (dma_valid == 1'b1) begin
|
||||
dma_valid <= 1'b0;
|
||||
end
|
||||
end
|
||||
if (dma_valid == 1'b1) begin
|
||||
sdo_mem[1] <= dma_data[15:8];
|
||||
sdo_mem[2] <= dma_data[ 7:0];
|
||||
end
|
||||
if (sequence_valid_s == 1'b1) begin
|
||||
sdo_mem[0] <= sequence_data_s;
|
||||
end
|
||||
end
|
||||
|
||||
// rate controller
|
||||
|
||||
assign dac_rstn_s = ~dac_rst_s;
|
||||
util_pulse_gen #(.PULSE_WIDTH(1)) i_trigger_gen (
|
||||
.clk (spi_clk),
|
||||
.rstn (dac_rstn_s),
|
||||
.pulse_width (1'b1),
|
||||
.pulse_period (pulse_period_s),
|
||||
.load_config (1'b1),
|
||||
.pulse (trigger_s)
|
||||
);
|
||||
|
||||
// offset of the sequencer registers are 8'h40
|
||||
|
||||
always @(negedge up_rstn or posedge spi_clk) begin
|
||||
if (up_rstn == 1'b0) begin
|
||||
up_rdata <= 'd0;
|
||||
up_rack <= 'd0;
|
||||
up_wack <= 'd0;
|
||||
end else begin
|
||||
up_rdata <= up_rdata_s[0] | up_rdata_s[1];
|
||||
up_rack <= up_rack_s[0] | up_rack_s[1];
|
||||
up_wack <= up_wack_s[0] | up_wack_s[1];
|
||||
end
|
||||
end
|
||||
|
||||
// DAC common registermap
|
||||
|
||||
assign pulse_period_s = {16'h0, dac_datarate_s};
|
||||
|
||||
up_ad5766_sequencer #(
|
||||
.SEQ_ID(4))
|
||||
i_sequencer (
|
||||
.sequence_clk (spi_clk),
|
||||
.sequence_rst (spi_mem_reset_s),
|
||||
.sequence_req (dma_valid),
|
||||
.sequence_valid (sequence_valid_s),
|
||||
.sequence_data (sequence_data_s),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (spi_clk),
|
||||
.up_wreq (up_wreq_s),
|
||||
.up_waddr (up_waddr_s),
|
||||
.up_wdata (up_wdata_s),
|
||||
.up_wack (up_wack_s[1]),
|
||||
.up_rreq (up_rreq_s),
|
||||
.up_raddr (up_raddr_s),
|
||||
.up_rdata (up_rdata_s[1]),
|
||||
.up_rack (up_rack_s[1]));
|
||||
|
||||
up_dac_common #(
|
||||
.COMMON_ID (0),
|
||||
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
|
||||
.FPGA_FAMILY (FPGA_FAMILY),
|
||||
.SPEED_GRADE (SPEED_GRADE),
|
||||
.DEV_PACKAGE (DEV_PACKAGE),
|
||||
.CONFIG (0),
|
||||
.CLK_EDGE_SEL (0),
|
||||
.DRP_DISABLE (6'h00),
|
||||
.USERPORTS_DISABLE (0),
|
||||
.GPIO_DISABLE (0)
|
||||
) i_dac_common (
|
||||
.mmcm_rst (),
|
||||
.dac_clk (spi_clk),
|
||||
.dac_rst (dac_rst_s),
|
||||
.dac_sync (),
|
||||
.dac_frame (),
|
||||
.dac_clksel (),
|
||||
.dac_par_type (),
|
||||
.dac_par_enb (),
|
||||
.dac_r1_mode (),
|
||||
.dac_datafmt (dac_datafmt),
|
||||
.dac_datarate (dac_datarate_s),
|
||||
.dac_status (1'b0),
|
||||
.dac_status_unf (dma_underflow),
|
||||
.dac_clk_ratio (32'b0),
|
||||
.up_dac_ce (),
|
||||
.up_pps_rcounter (32'b0),
|
||||
.up_pps_status (1'b0),
|
||||
.up_pps_irq_mask (),
|
||||
.up_drp_sel (),
|
||||
.up_drp_wr (),
|
||||
.up_drp_addr (),
|
||||
.up_drp_wdata (),
|
||||
.up_drp_rdata (16'b0),
|
||||
.up_drp_ready (1'b0),
|
||||
.up_drp_locked (1'b0),
|
||||
.up_usr_chanmax (),
|
||||
.dac_usr_chanmax (8'b0),
|
||||
.up_dac_gpio_in (32'b0),
|
||||
.up_dac_gpio_out (),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (spi_clk),
|
||||
.up_wreq (up_wreq_s),
|
||||
.up_waddr (up_waddr_s),
|
||||
.up_wdata (up_wdata_s),
|
||||
.up_wack (up_wack_s[0]),
|
||||
.up_rreq (up_rreq_s),
|
||||
.up_raddr (up_raddr_s),
|
||||
.up_rdata (up_rdata_s[0]),
|
||||
.up_rack (up_rack_s[0]));
|
||||
|
||||
|
||||
// AXI wrapper
|
||||
|
||||
up_axi #(
|
||||
.AXI_ADDRESS_WIDTH (16)
|
||||
) i_up_axi (
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (spi_clk),
|
||||
.up_axi_awvalid (s_axi_awvalid),
|
||||
.up_axi_awaddr (s_axi_awaddr),
|
||||
.up_axi_awready (s_axi_awready),
|
||||
.up_axi_wvalid (s_axi_wvalid),
|
||||
.up_axi_wdata (s_axi_wdata),
|
||||
.up_axi_wstrb (s_axi_wstrb),
|
||||
.up_axi_wready (s_axi_wready),
|
||||
.up_axi_bvalid (s_axi_bvalid),
|
||||
.up_axi_bresp (s_axi_bresp),
|
||||
.up_axi_bready (s_axi_bready),
|
||||
.up_axi_arvalid (s_axi_arvalid),
|
||||
.up_axi_araddr (s_axi_araddr),
|
||||
.up_axi_arready (s_axi_arready),
|
||||
.up_axi_rvalid (s_axi_rvalid),
|
||||
.up_axi_rresp (s_axi_rresp),
|
||||
.up_axi_rdata (s_axi_rdata),
|
||||
.up_axi_rready (s_axi_rready),
|
||||
.up_wreq (up_wreq_s),
|
||||
.up_waddr (up_waddr_s),
|
||||
.up_wdata (up_wdata_s),
|
||||
.up_wack (up_wack),
|
||||
.up_rreq (up_rreq_s),
|
||||
.up_raddr (up_raddr_s),
|
||||
.up_rdata (up_rdata),
|
||||
.up_rack (up_rack));
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,439 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Version="7" Minor="40" Path="/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad5766/axi_ad5766.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="89a4cfc7fabc4081bb198b02ac300e6a"/>
|
||||
<Option Name="Part" Val="xc7vx485tffg1157-1"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="BoardPart" Val=""/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../library"/>
|
||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../../ghdl/library"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="DSAVendor" Val="xilinx"/>
|
||||
<Option Name="DSANumComputeUnits" Val="60"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="0"/>
|
||||
<Option Name="WTModelSimExportSim" Val="0"/>
|
||||
<Option Name="WTQuestaExportSim" Val="0"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="0"/>
|
||||
<Option Name="WTRivieraExportSim" Val="0"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
<Option Name="SimTypes" Val="bfm"/>
|
||||
<Option Name="SimTypes" Val="tlm"/>
|
||||
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="31">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/../common/ad_rst.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/up_ad5766_sequencer.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../common/up_axi.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../common/up_clock_mon.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../common/up_dac_common.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../common/up_xfer_cntrl.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../common/up_xfer_status.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../common/util_pulse_gen.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/axi_ad5766.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/component.xml">
|
||||
<FileInfo SFType="IPXACT"/>
|
||||
</File>
|
||||
<File Path="$PPRDIR/bd/bd.tcl">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="axi_ad5766"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="IES">
|
||||
<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Xcelium">
|
||||
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="VCS">
|
||||
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="10">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Vivado 12-1790"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="1"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="Evaluation"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="features"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="should"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="NOT"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="be"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="used"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="in"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="production"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="systems."/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Place 30-73"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="10"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="axi_spi"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val=""/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="11"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1343"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="2"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1306"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="3"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="ERROR"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1276"/>
|
||||
<MsgAttr Name="Severity" Val="CRITICAL WARNING"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="4"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-3656"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="5"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-4623"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="6"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-459"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="7"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Synth 8-3331"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="8"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Designutils 20-3303"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="9"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="HDPYFinalizeIO"/>
|
||||
</MsgRule>
|
||||
<Board/>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
<BootPmcSettings Version="1" Minor="0">
|
||||
<Parameters>
|
||||
<Parameter Name="PMC_CDO.ATTRS.LOADADDR" Value="" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_FB_CLK" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_FREQ" Value="300" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_BUS_WIDTH" Value="x1" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_DATA_MODE" Value="Single" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_FREQ" Value="200" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_SLOT_TYPE" Value="SD 2.0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_FREQ" Value="200" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_SLOT_TYPE" Value="SD 2.0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSPI_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSPI_FREQ" Value="300" Type="string"/>
|
||||
<Parameter Name="BOOT.USB_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SMAP_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SMAP_DATA_WIDTH" Value="32 Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSC_FREQ" Value="33.333" Type="string"/>
|
||||
<Parameter Name="BOOT.SECONDARY.PCIE_ENABLE" Value="0" Type="string"/>
|
||||
</Parameters>
|
||||
</BootPmcSettings>
|
||||
</Project>
|
||||
@@ -0,0 +1,64 @@
|
||||
# ip
|
||||
|
||||
source ../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
|
||||
adi_ip_create axi_ad5766
|
||||
adi_ip_files axi_ad5766 [list \
|
||||
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
|
||||
"$ad_hdl_dir/library/common/up_xfer_status.v" \
|
||||
"$ad_hdl_dir/library/common/ad_rst.v" \
|
||||
"$ad_hdl_dir/library/common/up_dac_common.v" \
|
||||
"$ad_hdl_dir/library/common/up_clock_mon.v" \
|
||||
"$ad_hdl_dir/library/common/up_axi.v" \
|
||||
"$ad_hdl_dir/library/common/util_pulse_gen.v" \
|
||||
"up_ad5766_sequencer.v" \
|
||||
"axi_ad5766.v" ]
|
||||
|
||||
adi_ip_properties axi_ad5766
|
||||
|
||||
adi_init_bd_tcl
|
||||
adi_ip_bd axi_ad5766 "bd/bd.tcl"
|
||||
|
||||
adi_ip_add_core_dependencies { \
|
||||
analog.com:user:util_cdc:1.0 \
|
||||
}
|
||||
|
||||
adi_add_bus "spi_engine_ctrl" "master" \
|
||||
"analog.com:interface:spi_engine_ctrl_rtl:1.0" \
|
||||
"analog.com:interface:spi_engine_ctrl:1.0" \
|
||||
{
|
||||
{"cmd_ready" "CMD_READY"} \
|
||||
{"cmd_valid" "CMD_VALID"} \
|
||||
{"cmd_data" "CMD_DATA"} \
|
||||
{"sdo_data_ready" "SDO_READY"} \
|
||||
{"sdo_data_valid" "SDO_VALID"} \
|
||||
{"sdo_data" "SDO_DATA"} \
|
||||
{"sdi_data_ready" "SDI_READY"} \
|
||||
{"sdi_data_valid" "SDI_VALID"} \
|
||||
{"sdi_data" "SDI_DATA"} \
|
||||
{"sync_ready" "SYNC_READY"} \
|
||||
{"sync_valid" "SYNC_VALID"} \
|
||||
{"sync_data" "SYNC_DATA"} \
|
||||
}
|
||||
|
||||
adi_add_bus "spi_engine_offload_ctrl" "slave" \
|
||||
"analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" \
|
||||
"analog.com:interface:spi_engine_offload_ctrl:1.0" \
|
||||
{ \
|
||||
{ "ctrl_cmd_wr_en" "CMD_WR_EN"} \
|
||||
{ "ctrl_cmd_wr_data" "CMD_WR_DATA"} \
|
||||
{ "ctrl_enable" "ENABLE"} \
|
||||
{ "ctrl_enabled" "ENABLED"} \
|
||||
{ "ctrl_mem_reset" "MEM_RESET"} \
|
||||
}
|
||||
|
||||
adi_add_bus_clock "ctrl_clk" "spi_engine_offload_ctrl"
|
||||
adi_add_bus_clock "spi_clk" "spi_engine_ctrl" "spi_resetn"
|
||||
adi_add_bus_clock "dma_clk" "dma_fifo_tx"
|
||||
|
||||
adi_add_auto_fpga_spec_params
|
||||
ipx::create_xgui_files [ipx::current_core]
|
||||
|
||||
ipx::save_core [ipx::current_core]
|
||||
|
||||
@@ -0,0 +1,47 @@
|
||||
# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!
|
||||
proc init {cellpath otherInfo} {
|
||||
set ip [get_bd_cells $cellpath]
|
||||
|
||||
bd::mark_propagate_only $ip " \
|
||||
DEV_PACKAGE \
|
||||
SPEED_GRADE \
|
||||
FPGA_FAMILY \
|
||||
FPGA_TECHNOLOGY"
|
||||
|
||||
adi_auto_assign_device_spec $cellpath
|
||||
}
|
||||
|
||||
# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)
|
||||
proc adi_auto_assign_device_spec {cellpath} {
|
||||
|
||||
set ip [get_bd_cells $cellpath]
|
||||
set ip_param_list [list_property $ip]
|
||||
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
|
||||
|
||||
set parent_dir "../"
|
||||
for {set x 1} {$x<=4} {incr x} {
|
||||
set linkname ${ip_path}${parent_dir}scripts/adi_xilinx_device_info_enc.tcl
|
||||
if { [file exists $linkname] } {
|
||||
source ${ip_path}${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl
|
||||
break
|
||||
}
|
||||
append parent_dir "../"
|
||||
}
|
||||
|
||||
# Find predefindes auto assignable parameters
|
||||
foreach i $auto_set_param_list {
|
||||
if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
|
||||
set val [adi_device_spec $cellpath $i]
|
||||
set_property CONFIG.$i $val $ip
|
||||
}
|
||||
}
|
||||
|
||||
# Find predefindes auto assignable/overwritable parameters
|
||||
foreach i $auto_set_param_list_overwritable {
|
||||
if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
|
||||
set val [adi_device_spec $cellpath $i]
|
||||
set_property CONFIG.$i $val $ip
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,2 @@
|
||||
CLEAN_TARGET += bd
|
||||
CLEAN_TARGET += temporary_case_dependencies.mk
|
||||
@@ -0,0 +1,258 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module up_ad5766_sequencer #(
|
||||
|
||||
parameter SEQ_ID = 0)(
|
||||
|
||||
input sequence_clk,
|
||||
input sequence_rst,
|
||||
input sequence_req,
|
||||
output reg sequence_valid,
|
||||
output reg [ 7:0] sequence_data,
|
||||
|
||||
input up_rstn,
|
||||
input up_clk,
|
||||
input up_wreq,
|
||||
input [13:0] up_waddr,
|
||||
input [31:0] up_wdata,
|
||||
output reg up_wack,
|
||||
input up_rreq,
|
||||
input [13:0] up_raddr,
|
||||
output reg [31:0] up_rdata,
|
||||
output reg up_rack);
|
||||
|
||||
|
||||
// registers
|
||||
|
||||
reg [ 7:0] up_sequencer[15:0];
|
||||
reg [ 3:0] up_endof_seq = 4'b0;
|
||||
reg up_xfer_req = 1'b0;
|
||||
reg [ 3:0] sequence_counter = 0;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire up_wreq_s;
|
||||
wire up_rreq_s;
|
||||
wire [ 7:0] sequencer[15:0];
|
||||
wire [ 3:0] end_of_sequence;
|
||||
|
||||
integer i;
|
||||
|
||||
// sequence counter
|
||||
|
||||
always @(posedge sequence_clk) begin
|
||||
if (sequence_rst) begin
|
||||
sequence_counter <= 4'b0;
|
||||
end else if (sequence_req) begin
|
||||
sequence_counter <= (sequence_counter == end_of_sequence) ? 0 : sequence_counter + 1;
|
||||
end
|
||||
end
|
||||
|
||||
// sequence output mux
|
||||
|
||||
always @(posedge sequence_clk) begin
|
||||
if (sequence_rst) begin
|
||||
sequence_data <= 16'b0;
|
||||
end
|
||||
else if (sequence_req) begin
|
||||
sequence_data <= sequencer[sequence_counter];
|
||||
end
|
||||
sequence_valid <= sequence_req;
|
||||
end
|
||||
|
||||
// decode block select
|
||||
|
||||
assign up_wreq_s = (up_waddr[13:8] == SEQ_ID) ? up_wreq : 1'b0;
|
||||
assign up_rreq_s = (up_raddr[13:8] == SEQ_ID) ? up_rreq : 1'b0;
|
||||
|
||||
// processor write interface
|
||||
|
||||
always @(negedge up_rstn or posedge up_clk) begin
|
||||
if (up_rstn == 0) begin
|
||||
for (i=0; i<16; i=i+1) begin
|
||||
up_sequencer[i] <= 8'b0;
|
||||
end
|
||||
up_endof_seq <= 4'b0;
|
||||
up_wack <= 1'b0;
|
||||
end else begin
|
||||
up_wack <= up_wreq_s;
|
||||
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h40)) begin
|
||||
up_sequencer[0] <= up_wdata[7:0];
|
||||
up_endof_seq <= (up_wdata[16]) ? up_waddr[3:0] : 4'b0;
|
||||
end
|
||||
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h41)) begin
|
||||
up_sequencer[1] <= up_wdata[7:0];
|
||||
up_endof_seq <= (up_wdata[16]) ? up_waddr[3:0] : 4'b0;
|
||||
end
|
||||
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h42)) begin
|
||||
up_sequencer[2] <= up_wdata[7:0];
|
||||
up_endof_seq <= (up_wdata[16]) ? up_waddr[3:0] : 4'b0;
|
||||
end
|
||||
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h43)) begin
|
||||
up_sequencer[3] <= up_wdata[7:0];
|
||||
up_endof_seq <= (up_wdata[16]) ? up_waddr[3:0] : 4'b0;
|
||||
end
|
||||
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h44)) begin
|
||||
up_sequencer[4] <= up_wdata[7:0];
|
||||
up_endof_seq <= (up_wdata[16]) ? up_waddr[3:0] : 4'b0;
|
||||
end
|
||||
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h45)) begin
|
||||
up_sequencer[5] <= up_wdata[7:0];
|
||||
up_endof_seq <= (up_wdata[16]) ? up_waddr[3:0] : 4'b0;
|
||||
end
|
||||
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h46)) begin
|
||||
up_sequencer[6] <= up_wdata[7:0];
|
||||
up_endof_seq <= (up_wdata[16]) ? up_waddr[3:0] : 4'b0;
|
||||
end
|
||||
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h47)) begin
|
||||
up_sequencer[7] <= up_wdata[7:0];
|
||||
up_endof_seq <= (up_wdata[16]) ? up_waddr[3:0] : 4'b0;
|
||||
end
|
||||
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h48)) begin
|
||||
up_sequencer[8] <= up_wdata[7:0];
|
||||
up_endof_seq <= (up_wdata[16]) ? up_waddr[3:0] : 4'b0;
|
||||
end
|
||||
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h49)) begin
|
||||
up_sequencer[9] <= up_wdata[7:0];
|
||||
up_endof_seq <= (up_wdata[16]) ? up_waddr[3:0] : 4'b0;
|
||||
end
|
||||
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h4a)) begin
|
||||
up_sequencer[10] <= up_wdata[7:0];
|
||||
up_endof_seq <= (up_wdata[16]) ? up_waddr[3:0] : 4'b0;
|
||||
end
|
||||
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h4b)) begin
|
||||
up_sequencer[11] <= up_wdata[7:0];
|
||||
up_endof_seq <= (up_wdata[16]) ? up_waddr[3:0] : 4'b0;
|
||||
end
|
||||
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h4c)) begin
|
||||
up_sequencer[12] <= up_wdata[7:0];
|
||||
up_endof_seq <= (up_wdata[16]) ? up_waddr[3:0] : 4'b0;
|
||||
end
|
||||
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h4d)) begin
|
||||
up_sequencer[13] <= up_wdata[7:0];
|
||||
up_endof_seq <= (up_wdata[16]) ? up_waddr[3:0] : 4'b0;
|
||||
end
|
||||
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h4e)) begin
|
||||
up_sequencer[14] <= up_wdata[7:0];
|
||||
up_endof_seq <= (up_wdata[16]) ? up_waddr[3:0] : 4'b0;
|
||||
end
|
||||
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h4f)) begin
|
||||
up_sequencer[15] <= up_wdata[7:0];
|
||||
up_endof_seq <= (up_wdata[16]) ? up_waddr[3:0] : 4'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// processor read interface
|
||||
|
||||
always @(negedge up_rstn or posedge up_clk) begin
|
||||
if (up_rstn == 0) begin
|
||||
up_rack <= 'd0;
|
||||
up_rdata <= 'd0;
|
||||
end else begin
|
||||
up_rack <= up_rreq_s;
|
||||
if (up_rreq_s == 1'b1) begin
|
||||
case (up_raddr[7:0])
|
||||
8'h40 : up_rdata <= {24'b0, up_sequencer[0]};
|
||||
8'h41 : up_rdata <= {24'b0, up_sequencer[1]};
|
||||
8'h42 : up_rdata <= {24'b0, up_sequencer[2]};
|
||||
8'h43 : up_rdata <= {24'b0, up_sequencer[3]};
|
||||
8'h44 : up_rdata <= {24'b0, up_sequencer[4]};
|
||||
8'h45 : up_rdata <= {24'b0, up_sequencer[5]};
|
||||
8'h46 : up_rdata <= {24'b0, up_sequencer[6]};
|
||||
8'h47 : up_rdata <= {24'b0, up_sequencer[7]};
|
||||
8'h48 : up_rdata <= {24'b0, up_sequencer[8]};
|
||||
8'h49 : up_rdata <= {24'b0, up_sequencer[9]};
|
||||
8'h4a : up_rdata <= {24'b0, up_sequencer[10]};
|
||||
8'h4b : up_rdata <= {24'b0, up_sequencer[11]};
|
||||
8'h4c : up_rdata <= {24'b0, up_sequencer[12]};
|
||||
8'h4d : up_rdata <= {24'b0, up_sequencer[13]};
|
||||
8'h4e : up_rdata <= {24'b0, up_sequencer[14]};
|
||||
8'h4f : up_rdata <= {24'b0, up_sequencer[15]};
|
||||
8'h60 : up_rdata <= {27'b0, up_xfer_req, up_endof_seq};
|
||||
endcase
|
||||
end else begin
|
||||
up_rdata <= 32'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// CDC
|
||||
|
||||
up_xfer_cntrl #(.DATA_WIDTH(132)) i_xfer_cntrl (
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_data_cntrl ({up_endof_seq,
|
||||
up_sequencer[0],
|
||||
up_sequencer[1],
|
||||
up_sequencer[2],
|
||||
up_sequencer[3],
|
||||
up_sequencer[4],
|
||||
up_sequencer[5],
|
||||
up_sequencer[6],
|
||||
up_sequencer[7],
|
||||
up_sequencer[8],
|
||||
up_sequencer[9],
|
||||
up_sequencer[10],
|
||||
up_sequencer[11],
|
||||
up_sequencer[12],
|
||||
up_sequencer[13],
|
||||
up_sequencer[14],
|
||||
up_sequencer[15]}),
|
||||
.up_xfer_done (up_cntrl_xfer_done),
|
||||
.d_rst (sequence_rst),
|
||||
.d_clk (sequence_clk),
|
||||
.d_data_cntrl ({end_of_sequence,
|
||||
sequencer[0],
|
||||
sequencer[1],
|
||||
sequencer[2],
|
||||
sequencer[3],
|
||||
sequencer[4],
|
||||
sequencer[5],
|
||||
sequencer[6],
|
||||
sequencer[7],
|
||||
sequencer[8],
|
||||
sequencer[9],
|
||||
sequencer[10],
|
||||
sequencer[11],
|
||||
sequencer[12],
|
||||
sequencer[13],
|
||||
sequencer[14],
|
||||
sequencer[15]}));
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,118 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||
ipgui::add_param $IPINST -name "ASYNC_SPI_CLK" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "CMD_MEM_ADDRESS_WIDTH" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "SDO_MEM_ADDRESS_WIDTH" -parent ${Page_0}
|
||||
#Adding Group
|
||||
set FPGA_info [ipgui::add_group $IPINST -name "FPGA info" -parent ${Page_0}]
|
||||
ipgui::add_param $IPINST -name "FPGA_TECHNOLOGY" -parent ${FPGA_info} -widget comboBox
|
||||
ipgui::add_param $IPINST -name "FPGA_FAMILY" -parent ${FPGA_info} -widget comboBox
|
||||
ipgui::add_param $IPINST -name "SPEED_GRADE" -parent ${FPGA_info} -widget comboBox
|
||||
ipgui::add_param $IPINST -name "DEV_PACKAGE" -parent ${FPGA_info} -widget comboBox
|
||||
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ASYNC_SPI_CLK { PARAM_VALUE.ASYNC_SPI_CLK } {
|
||||
# Procedure called to update ASYNC_SPI_CLK when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ASYNC_SPI_CLK { PARAM_VALUE.ASYNC_SPI_CLK } {
|
||||
# Procedure called to validate ASYNC_SPI_CLK
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.CMD_MEM_ADDRESS_WIDTH { PARAM_VALUE.CMD_MEM_ADDRESS_WIDTH } {
|
||||
# Procedure called to update CMD_MEM_ADDRESS_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.CMD_MEM_ADDRESS_WIDTH { PARAM_VALUE.CMD_MEM_ADDRESS_WIDTH } {
|
||||
# Procedure called to validate CMD_MEM_ADDRESS_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } {
|
||||
# Procedure called to update DEV_PACKAGE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } {
|
||||
# Procedure called to validate DEV_PACKAGE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } {
|
||||
# Procedure called to update FPGA_FAMILY when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } {
|
||||
# Procedure called to validate FPGA_FAMILY
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } {
|
||||
# Procedure called to update FPGA_TECHNOLOGY when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } {
|
||||
# Procedure called to validate FPGA_TECHNOLOGY
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.SDO_MEM_ADDRESS_WIDTH { PARAM_VALUE.SDO_MEM_ADDRESS_WIDTH } {
|
||||
# Procedure called to update SDO_MEM_ADDRESS_WIDTH when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.SDO_MEM_ADDRESS_WIDTH { PARAM_VALUE.SDO_MEM_ADDRESS_WIDTH } {
|
||||
# Procedure called to validate SDO_MEM_ADDRESS_WIDTH
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } {
|
||||
# Procedure called to update SPEED_GRADE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } {
|
||||
# Procedure called to validate SPEED_GRADE
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.FPGA_TECHNOLOGY { MODELPARAM_VALUE.FPGA_TECHNOLOGY PARAM_VALUE.FPGA_TECHNOLOGY } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.FPGA_TECHNOLOGY}] ${MODELPARAM_VALUE.FPGA_TECHNOLOGY}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.FPGA_FAMILY { MODELPARAM_VALUE.FPGA_FAMILY PARAM_VALUE.FPGA_FAMILY } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.FPGA_FAMILY}] ${MODELPARAM_VALUE.FPGA_FAMILY}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.SPEED_GRADE { MODELPARAM_VALUE.SPEED_GRADE PARAM_VALUE.SPEED_GRADE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.SPEED_GRADE}] ${MODELPARAM_VALUE.SPEED_GRADE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DEV_PACKAGE { MODELPARAM_VALUE.DEV_PACKAGE PARAM_VALUE.DEV_PACKAGE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DEV_PACKAGE}] ${MODELPARAM_VALUE.DEV_PACKAGE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.ASYNC_SPI_CLK { MODELPARAM_VALUE.ASYNC_SPI_CLK PARAM_VALUE.ASYNC_SPI_CLK } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ASYNC_SPI_CLK}] ${MODELPARAM_VALUE.ASYNC_SPI_CLK}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.CMD_MEM_ADDRESS_WIDTH { MODELPARAM_VALUE.CMD_MEM_ADDRESS_WIDTH PARAM_VALUE.CMD_MEM_ADDRESS_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.CMD_MEM_ADDRESS_WIDTH}] ${MODELPARAM_VALUE.CMD_MEM_ADDRESS_WIDTH}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.SDO_MEM_ADDRESS_WIDTH { MODELPARAM_VALUE.SDO_MEM_ADDRESS_WIDTH PARAM_VALUE.SDO_MEM_ADDRESS_WIDTH } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.SDO_MEM_ADDRESS_WIDTH}] ${MODELPARAM_VALUE.SDO_MEM_ADDRESS_WIDTH}
|
||||
}
|
||||
|
||||
@@ -0,0 +1,14 @@
|
||||
####################################################################################
|
||||
## Copyright 2018(c) Analog Devices, Inc.
|
||||
## Auto-generated, do not modify!
|
||||
####################################################################################
|
||||
|
||||
LIBRARY_NAME := axi_ad6676
|
||||
|
||||
GENERIC_DEPS += axi_ad6676.v
|
||||
|
||||
XILINX_DEPS += axi_ad6676_ip.tcl
|
||||
|
||||
XILINX_LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc
|
||||
|
||||
include ../scripts/library.mk
|
||||
@@ -0,0 +1,3 @@
|
||||
version:1
|
||||
6d6f64655f636f756e7465727c42617463684d6f6465:1
|
||||
eof:
|
||||
@@ -0,0 +1,6 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<labtools version="1" minor="0"/>
|
||||
@@ -0,0 +1,143 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module axi_ad6676 #(
|
||||
|
||||
parameter ID = 0,
|
||||
parameter NUM_LANES = 2,
|
||||
parameter FPGA_TECHNOLOGY = 0,
|
||||
parameter FPGA_FAMILY = 0,
|
||||
parameter SPEED_GRADE = 0,
|
||||
parameter DEV_PACKAGE = 0) (
|
||||
|
||||
// jesd interface
|
||||
// rx_clk is (line-rate/40)
|
||||
|
||||
input rx_clk,
|
||||
input [ 3:0] rx_sof,
|
||||
input rx_valid,
|
||||
output rx_ready,
|
||||
input [32*NUM_LANES-1:0] rx_data,
|
||||
|
||||
// dma interface
|
||||
|
||||
output adc_clk,
|
||||
output adc_valid_0,
|
||||
output adc_enable_0,
|
||||
output [31:0] adc_data_0,
|
||||
output adc_valid_1,
|
||||
output adc_enable_1,
|
||||
output [31:0] adc_data_1,
|
||||
input adc_dovf,
|
||||
|
||||
// axi interface
|
||||
|
||||
input s_axi_aclk,
|
||||
input s_axi_aresetn,
|
||||
input s_axi_awvalid,
|
||||
input [11:0] s_axi_awaddr,
|
||||
output s_axi_awready,
|
||||
input s_axi_wvalid,
|
||||
input [31:0] s_axi_wdata,
|
||||
input [ 3:0] s_axi_wstrb,
|
||||
output s_axi_wready,
|
||||
output s_axi_bvalid,
|
||||
output [ 1:0] s_axi_bresp,
|
||||
input s_axi_bready,
|
||||
input s_axi_arvalid,
|
||||
input [11:0] s_axi_araddr,
|
||||
output s_axi_arready,
|
||||
output s_axi_rvalid,
|
||||
output [ 1:0] s_axi_rresp,
|
||||
output [31:0] s_axi_rdata,
|
||||
input s_axi_rready,
|
||||
input [ 2:0] s_axi_awprot,
|
||||
input [ 2:0] s_axi_arprot);
|
||||
|
||||
assign adc_clk = rx_clk;
|
||||
|
||||
ad_ip_jesd204_tpl_adc #(
|
||||
.ID (ID),
|
||||
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
|
||||
.FPGA_FAMILY (FPGA_FAMILY),
|
||||
.SPEED_GRADE (SPEED_GRADE),
|
||||
.DEV_PACKAGE (DEV_PACKAGE),
|
||||
.NUM_LANES (NUM_LANES),
|
||||
.NUM_CHANNELS (2),
|
||||
.SAMPLES_PER_FRAME (1),
|
||||
.CONVERTER_RESOLUTION (16),
|
||||
.BITS_PER_SAMPLE (16),
|
||||
.OCTETS_PER_BEAT (4),
|
||||
.TWOS_COMPLEMENT (1)
|
||||
) i_adc_jesd204 (
|
||||
.link_clk (rx_clk),
|
||||
|
||||
.link_sof (rx_sof),
|
||||
.link_valid (rx_valid),
|
||||
.link_data (rx_data),
|
||||
.link_ready (rx_ready),
|
||||
|
||||
.enable ({adc_enable_1,adc_enable_0}),
|
||||
|
||||
.adc_valid ({adc_valid_1,adc_valid_0}),
|
||||
.adc_data ({adc_data_1,adc_data_0}),
|
||||
.adc_dovf (adc_dovf),
|
||||
|
||||
.s_axi_aclk (s_axi_aclk),
|
||||
.s_axi_aresetn (s_axi_aresetn),
|
||||
.s_axi_awvalid (s_axi_awvalid),
|
||||
.s_axi_awready (s_axi_awready),
|
||||
.s_axi_awaddr (s_axi_awaddr),
|
||||
.s_axi_awprot (s_axi_awprot),
|
||||
.s_axi_wvalid (s_axi_wvalid),
|
||||
.s_axi_wready (s_axi_wready),
|
||||
.s_axi_wdata (s_axi_wdata),
|
||||
.s_axi_wstrb (s_axi_wstrb),
|
||||
.s_axi_bvalid (s_axi_bvalid),
|
||||
.s_axi_bresp (s_axi_bresp),
|
||||
.s_axi_bready (s_axi_bready),
|
||||
.s_axi_arvalid (s_axi_arvalid),
|
||||
.s_axi_arready (s_axi_arready),
|
||||
.s_axi_araddr (s_axi_araddr),
|
||||
.s_axi_arprot (s_axi_arprot),
|
||||
.s_axi_rvalid (s_axi_rvalid),
|
||||
.s_axi_rready(s_axi_rready),
|
||||
.s_axi_rresp (s_axi_rresp),
|
||||
.s_axi_rdata (s_axi_rdata)
|
||||
);
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,383 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Version="7" Minor="40" Path="/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad6676/axi_ad6676.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="7cb7e82e064a46ec979271e29998243b"/>
|
||||
<Option Name="Part" Val="xc7vx485tffg1157-1"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="BoardPart" Val=""/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../library"/>
|
||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../../ghdl/library"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="DSAVendor" Val="xilinx"/>
|
||||
<Option Name="DSANumComputeUnits" Val="60"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="0"/>
|
||||
<Option Name="WTModelSimExportSim" Val="0"/>
|
||||
<Option Name="WTQuestaExportSim" Val="0"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="0"/>
|
||||
<Option Name="WTRivieraExportSim" Val="0"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
<Option Name="SimTypes" Val="bfm"/>
|
||||
<Option Name="SimTypes" Val="tlm"/>
|
||||
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="31">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/axi_ad6676.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/component.xml">
|
||||
<FileInfo SFType="IPXACT"/>
|
||||
</File>
|
||||
<File Path="$PPRDIR/bd/bd.tcl">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="axi_ad6676"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="IES">
|
||||
<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Xcelium">
|
||||
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="VCS">
|
||||
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="10">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Vivado 12-1790"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="1"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="Evaluation"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="features"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="should"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="NOT"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="be"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="used"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="in"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="production"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="systems."/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Place 30-73"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="10"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="axi_spi"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val=""/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="11"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1343"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="2"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1306"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="3"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="ERROR"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1276"/>
|
||||
<MsgAttr Name="Severity" Val="CRITICAL WARNING"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="4"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-3656"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="5"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-4623"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="6"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-459"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="7"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Synth 8-3331"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="8"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Designutils 20-3303"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="9"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="HDPYFinalizeIO"/>
|
||||
</MsgRule>
|
||||
<Board/>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
<BootPmcSettings Version="1" Minor="0">
|
||||
<Parameters>
|
||||
<Parameter Name="PMC_CDO.ATTRS.LOADADDR" Value="" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_FB_CLK" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_FREQ" Value="300" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_BUS_WIDTH" Value="x1" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_DATA_MODE" Value="Single" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_FREQ" Value="200" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_SLOT_TYPE" Value="SD 2.0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_FREQ" Value="200" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_SLOT_TYPE" Value="SD 2.0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSPI_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSPI_FREQ" Value="300" Type="string"/>
|
||||
<Parameter Name="BOOT.USB_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SMAP_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SMAP_DATA_WIDTH" Value="32 Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSC_FREQ" Value="33.333" Type="string"/>
|
||||
<Parameter Name="BOOT.SECONDARY.PCIE_ENABLE" Value="0" Type="string"/>
|
||||
</Parameters>
|
||||
</BootPmcSettings>
|
||||
</Project>
|
||||
@@ -0,0 +1,28 @@
|
||||
# ip
|
||||
|
||||
source ../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
|
||||
adi_ip_create axi_ad6676
|
||||
adi_ip_files axi_ad6676 [list \
|
||||
"axi_ad6676.v" ]
|
||||
|
||||
adi_ip_properties axi_ad6676
|
||||
|
||||
adi_init_bd_tcl
|
||||
adi_ip_bd axi_ad6676 "bd/bd.tcl"
|
||||
|
||||
adi_ip_add_core_dependencies { \
|
||||
analog.com:user:ad_ip_jesd204_tpl_adc:1.0 \
|
||||
}
|
||||
|
||||
set_property driver_value 0 [ipx::get_ports *rx_valid* -of_objects [ipx::current_core]]
|
||||
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
|
||||
|
||||
ipx::infer_bus_interface rx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
|
||||
adi_add_auto_fpga_spec_params
|
||||
ipx::create_xgui_files [ipx::current_core]
|
||||
|
||||
ipx::save_core [ipx::current_core]
|
||||
@@ -0,0 +1,47 @@
|
||||
# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!
|
||||
proc init {cellpath otherInfo} {
|
||||
set ip [get_bd_cells $cellpath]
|
||||
|
||||
bd::mark_propagate_only $ip " \
|
||||
DEV_PACKAGE \
|
||||
SPEED_GRADE \
|
||||
FPGA_FAMILY \
|
||||
FPGA_TECHNOLOGY"
|
||||
|
||||
adi_auto_assign_device_spec $cellpath
|
||||
}
|
||||
|
||||
# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)
|
||||
proc adi_auto_assign_device_spec {cellpath} {
|
||||
|
||||
set ip [get_bd_cells $cellpath]
|
||||
set ip_param_list [list_property $ip]
|
||||
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
|
||||
|
||||
set parent_dir "../"
|
||||
for {set x 1} {$x<=4} {incr x} {
|
||||
set linkname ${ip_path}${parent_dir}scripts/adi_xilinx_device_info_enc.tcl
|
||||
if { [file exists $linkname] } {
|
||||
source ${ip_path}${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl
|
||||
break
|
||||
}
|
||||
append parent_dir "../"
|
||||
}
|
||||
|
||||
# Find predefindes auto assignable parameters
|
||||
foreach i $auto_set_param_list {
|
||||
if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
|
||||
set val [adi_device_spec $cellpath $i]
|
||||
set_property CONFIG.$i $val $ip
|
||||
}
|
||||
}
|
||||
|
||||
# Find predefindes auto assignable/overwritable parameters
|
||||
foreach i $auto_set_param_list_overwritable {
|
||||
if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
|
||||
set val [adi_device_spec $cellpath $i]
|
||||
set_property CONFIG.$i $val $ip
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,2 @@
|
||||
CLEAN_TARGET += bd
|
||||
CLEAN_TARGET += temporary_case_dependencies.mk
|
||||
@@ -0,0 +1,103 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||
ipgui::add_param $IPINST -name "ID" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "NUM_LANES" -parent ${Page_0}
|
||||
#Adding Group
|
||||
set FPGA_info [ipgui::add_group $IPINST -name "FPGA info" -parent ${Page_0}]
|
||||
ipgui::add_param $IPINST -name "FPGA_TECHNOLOGY" -parent ${FPGA_info} -widget comboBox
|
||||
ipgui::add_param $IPINST -name "FPGA_FAMILY" -parent ${FPGA_info} -widget comboBox
|
||||
ipgui::add_param $IPINST -name "SPEED_GRADE" -parent ${FPGA_info} -widget comboBox
|
||||
ipgui::add_param $IPINST -name "DEV_PACKAGE" -parent ${FPGA_info} -widget comboBox
|
||||
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } {
|
||||
# Procedure called to update DEV_PACKAGE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } {
|
||||
# Procedure called to validate DEV_PACKAGE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } {
|
||||
# Procedure called to update FPGA_FAMILY when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } {
|
||||
# Procedure called to validate FPGA_FAMILY
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } {
|
||||
# Procedure called to update FPGA_TECHNOLOGY when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } {
|
||||
# Procedure called to validate FPGA_TECHNOLOGY
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } {
|
||||
# Procedure called to update ID when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } {
|
||||
# Procedure called to validate ID
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.NUM_LANES { PARAM_VALUE.NUM_LANES } {
|
||||
# Procedure called to update NUM_LANES when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.NUM_LANES { PARAM_VALUE.NUM_LANES } {
|
||||
# Procedure called to validate NUM_LANES
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } {
|
||||
# Procedure called to update SPEED_GRADE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } {
|
||||
# Procedure called to validate SPEED_GRADE
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.NUM_LANES { MODELPARAM_VALUE.NUM_LANES PARAM_VALUE.NUM_LANES } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.NUM_LANES}] ${MODELPARAM_VALUE.NUM_LANES}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.FPGA_TECHNOLOGY { MODELPARAM_VALUE.FPGA_TECHNOLOGY PARAM_VALUE.FPGA_TECHNOLOGY } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.FPGA_TECHNOLOGY}] ${MODELPARAM_VALUE.FPGA_TECHNOLOGY}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.FPGA_FAMILY { MODELPARAM_VALUE.FPGA_FAMILY PARAM_VALUE.FPGA_FAMILY } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.FPGA_FAMILY}] ${MODELPARAM_VALUE.FPGA_FAMILY}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.SPEED_GRADE { MODELPARAM_VALUE.SPEED_GRADE PARAM_VALUE.SPEED_GRADE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.SPEED_GRADE}] ${MODELPARAM_VALUE.SPEED_GRADE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DEV_PACKAGE { MODELPARAM_VALUE.DEV_PACKAGE PARAM_VALUE.DEV_PACKAGE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DEV_PACKAGE}] ${MODELPARAM_VALUE.DEV_PACKAGE}
|
||||
}
|
||||
|
||||
@@ -0,0 +1,22 @@
|
||||
####################################################################################
|
||||
## Copyright 2018(c) Analog Devices, Inc.
|
||||
## Auto-generated, do not modify!
|
||||
####################################################################################
|
||||
|
||||
LIBRARY_NAME := axi_ad7616
|
||||
|
||||
GENERIC_DEPS += ../common/ad_edge_detect.v
|
||||
GENERIC_DEPS += ../common/up_axi.v
|
||||
GENERIC_DEPS += axi_ad7616.v
|
||||
GENERIC_DEPS += axi_ad7616_control.v
|
||||
GENERIC_DEPS += axi_ad7616_maxis2wrfifo.v
|
||||
GENERIC_DEPS += axi_ad7616_pif.v
|
||||
|
||||
XILINX_DEPS += axi_ad7616_ip.tcl
|
||||
|
||||
XILINX_LIB_DEPS += spi_engine/axi_spi_engine
|
||||
XILINX_LIB_DEPS += spi_engine/spi_engine_execution
|
||||
XILINX_LIB_DEPS += spi_engine/spi_engine_interconnect
|
||||
XILINX_LIB_DEPS += spi_engine/spi_engine_offload
|
||||
|
||||
include ../scripts/library.mk
|
||||
@@ -0,0 +1,3 @@
|
||||
version:1
|
||||
6d6f64655f636f756e7465727c42617463684d6f6465:1
|
||||
eof:
|
||||
@@ -0,0 +1,6 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<labtools version="1" minor="0"/>
|
||||
@@ -0,0 +1,462 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module axi_ad7616 #(
|
||||
|
||||
parameter ID = 0,
|
||||
parameter IF_TYPE = 1) (
|
||||
|
||||
// physical data interface
|
||||
|
||||
output rx_sclk,
|
||||
output rx_cs_n,
|
||||
output rx_sdo,
|
||||
input [ 1:0] rx_sdi,
|
||||
|
||||
output [15:0] rx_db_o,
|
||||
input [15:0] rx_db_i,
|
||||
output rx_db_t,
|
||||
output rx_rd_n,
|
||||
output rx_wr_n,
|
||||
|
||||
// physical control interface
|
||||
|
||||
output rx_cnvst,
|
||||
input rx_busy,
|
||||
|
||||
// AXI Slave Memory Map
|
||||
|
||||
input s_axi_aclk,
|
||||
input s_axi_aresetn,
|
||||
input s_axi_awvalid,
|
||||
input [15:0] s_axi_awaddr,
|
||||
input [ 2:0] s_axi_awprot,
|
||||
output s_axi_awready,
|
||||
input s_axi_wvalid,
|
||||
input [31:0] s_axi_wdata,
|
||||
input [ 3:0] s_axi_wstrb,
|
||||
output s_axi_wready,
|
||||
output s_axi_bvalid,
|
||||
output [ 1:0] s_axi_bresp,
|
||||
input s_axi_bready,
|
||||
input s_axi_arvalid,
|
||||
input [15:0] s_axi_araddr,
|
||||
input [ 2:0] s_axi_arprot,
|
||||
output s_axi_arready,
|
||||
output s_axi_rvalid,
|
||||
output [ 1:0] s_axi_rresp,
|
||||
output [31:0] s_axi_rdata,
|
||||
input s_axi_rready,
|
||||
|
||||
// Write FIFO interface
|
||||
|
||||
output adc_valid,
|
||||
output [15:0] adc_data,
|
||||
output adc_sync,
|
||||
|
||||
output irq);
|
||||
|
||||
|
||||
localparam NUM_OF_SDI = 2;
|
||||
localparam SERIAL = 0;
|
||||
localparam PARALLEL = 1;
|
||||
localparam NEG_EDGE = 1;
|
||||
|
||||
// internal registers
|
||||
|
||||
reg up_wack = 1'b0;
|
||||
reg up_rack = 1'b0;
|
||||
reg [31:0] up_rdata = 32'b0;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire up_clk;
|
||||
wire up_rstn;
|
||||
wire up_rst;
|
||||
wire up_rreq_s;
|
||||
wire [13:0] up_raddr_s;
|
||||
wire up_wreq_s;
|
||||
wire [13:0] up_waddr_s;
|
||||
wire [31:0] up_wdata_s;
|
||||
|
||||
wire up_wack_if_s;
|
||||
wire up_rack_if_s;
|
||||
wire [31:0] up_rdata_if_s;
|
||||
wire up_wack_cntrl_s;
|
||||
wire up_rack_cntrl_s;
|
||||
wire [31:0] up_rdata_cntrl_s;
|
||||
|
||||
wire trigger_s;
|
||||
|
||||
wire rd_req_s;
|
||||
wire wr_req_s;
|
||||
wire [15:0] wr_data_s;
|
||||
wire [15:0] rd_data_s;
|
||||
wire rd_valid_s;
|
||||
wire [ 4:0] burst_length_s;
|
||||
wire m_axis_ready_s;
|
||||
wire m_axis_valid_s;
|
||||
wire [15:0] m_axis_data_s;
|
||||
wire m_axis_xfer_req_s;
|
||||
|
||||
// defaults
|
||||
|
||||
assign up_clk = s_axi_aclk;
|
||||
assign up_rstn = s_axi_aresetn;
|
||||
assign up_rst = ~s_axi_aresetn;
|
||||
|
||||
// processor read interface
|
||||
|
||||
always @(negedge up_rstn or posedge up_clk) begin
|
||||
if (up_rstn == 0) begin
|
||||
up_wack <= 'd0;
|
||||
up_rack <= 'd0;
|
||||
up_rdata <= 'd0;
|
||||
end else begin
|
||||
up_wack <= up_wack_if_s | up_wack_cntrl_s;
|
||||
up_rack <= up_rack_if_s | up_rack_cntrl_s;
|
||||
up_rdata <= up_rdata_if_s | up_rdata_cntrl_s;
|
||||
end
|
||||
end
|
||||
|
||||
generate if (IF_TYPE == SERIAL) begin
|
||||
|
||||
// ground all parallel interface signals
|
||||
|
||||
assign rx_db_o = 16'b0;
|
||||
assign rx_rd_n = 1'b0;
|
||||
assign rx_wr_n = 1'b0;
|
||||
|
||||
// SPI Framework instances and logic
|
||||
|
||||
wire spi_resetn_s;
|
||||
wire s0_cmd_ready_s;
|
||||
wire s0_cmd_valid_s;
|
||||
wire [15:0] s0_cmd_data_s;
|
||||
wire s0_sdo_data_ready_s;
|
||||
wire s0_sdo_data_valid_s;
|
||||
wire [ 7:0] s0_sdo_data_s;
|
||||
wire s0_sdi_data_ready_s;
|
||||
wire s0_sdi_data_valid_s;
|
||||
wire [15:0] s0_sdi_data_s;
|
||||
wire s0_sync_ready_s;
|
||||
wire s0_sync_valid_s;
|
||||
wire [ 7:0] s0_sync_s;
|
||||
wire s1_cmd_ready_s;
|
||||
wire s1_cmd_valid_s;
|
||||
wire [15:0] s1_cmd_data_s;
|
||||
wire s1_sdo_data_ready_s;
|
||||
wire s1_sdo_data_valid_s;
|
||||
wire [ 7:0] s1_sdo_data_s;
|
||||
wire s1_sdi_data_ready_s;
|
||||
wire s1_sdi_data_valid_s;
|
||||
wire [15:0] s1_sdi_data_s;
|
||||
wire s1_sync_ready_s;
|
||||
wire s1_sync_valid_s;
|
||||
wire [ 7:0] s1_sync_s;
|
||||
wire m_cmd_ready_s;
|
||||
wire m_cmd_valid_s;
|
||||
wire [15:0] m_cmd_data_s;
|
||||
wire m_sdo_data_ready_s;
|
||||
wire m_sdo_data_valid_s;
|
||||
wire [7:0] m_sdo_data_s;
|
||||
wire m_sdi_data_ready_s;
|
||||
wire m_sdi_data_valid_s;
|
||||
wire [15:0] m_sdi_data_s;
|
||||
wire m_sync_ready_s;
|
||||
wire m_sync_valid_s;
|
||||
wire [ 7:0] m_sync_s;
|
||||
wire offload0_cmd_wr_en_s;
|
||||
wire [15:0] offload0_cmd_wr_data_s;
|
||||
wire offload0_sdo_wr_en_s;
|
||||
wire [ 7:0] offload0_sdo_wr_data_s;
|
||||
wire offload0_mem_reset_s;
|
||||
wire offload0_enable_s;
|
||||
wire offload0_enabled_s;
|
||||
|
||||
axi_spi_engine #(
|
||||
.DATA_WIDTH (8),
|
||||
.NUM_OF_SDI (NUM_OF_SDI),
|
||||
.NUM_OFFLOAD(1),
|
||||
.MM_IF_TYPE(1)
|
||||
) i_axi_spi_engine (
|
||||
.up_clk (up_clk),
|
||||
.up_rstn (up_rstn),
|
||||
.up_wreq (up_wreq_s),
|
||||
.up_waddr (up_waddr_s),
|
||||
.up_wdata (up_wdata_s),
|
||||
.up_wack (up_wack_if_s),
|
||||
.up_rreq (up_rreq_s),
|
||||
.up_raddr (up_raddr_s),
|
||||
.up_rdata (up_rdata_if_s),
|
||||
.up_rack (up_rack_if_s),
|
||||
.irq (irq),
|
||||
.spi_clk (up_clk),
|
||||
.spi_resetn (spi_resetn_s),
|
||||
.cmd_ready (s0_cmd_ready_s),
|
||||
.cmd_valid (s0_cmd_valid_s),
|
||||
.cmd_data (s0_cmd_data_s),
|
||||
.sdo_data_ready (s0_sdo_data_ready_s),
|
||||
.sdo_data_valid (s0_sdo_data_valid_s),
|
||||
.sdo_data (s0_sdo_data_s),
|
||||
.sdi_data_ready (s0_sdi_data_ready_s),
|
||||
.sdi_data_valid (s0_sdi_data_valid_s),
|
||||
.sdi_data (s0_sdi_data_s),
|
||||
.sync_ready (s0_sync_ready_s),
|
||||
.sync_valid (s0_sync_valid_s),
|
||||
.sync_data (s0_sync_s),
|
||||
.offload0_cmd_wr_en (offload0_cmd_wr_en_s),
|
||||
.offload0_cmd_wr_data (offload0_cmd_wr_data_s),
|
||||
.offload0_sdo_wr_en (offload0_sdo_wr_en_s),
|
||||
.offload0_sdo_wr_data (offload0_sdo_wr_data_s),
|
||||
.offload0_mem_reset (offload0_mem_reset_s),
|
||||
.offload0_enable (offload0_enable_s),
|
||||
.offload0_enabled(offload0_enabled_s));
|
||||
|
||||
spi_engine_offload #(
|
||||
.DATA_WIDTH (8),
|
||||
.NUM_OF_SDI (NUM_OF_SDI)
|
||||
) i_spi_engine_offload (
|
||||
.ctrl_clk (up_clk),
|
||||
.ctrl_cmd_wr_en (offload0_cmd_wr_en_s),
|
||||
.ctrl_cmd_wr_data (offload0_cmd_wr_data_s),
|
||||
.ctrl_sdo_wr_en (offload0_sdo_wr_en_s),
|
||||
.ctrl_sdo_wr_data (offload0_sdo_wr_data_s),
|
||||
.ctrl_enable (offload0_enable_s),
|
||||
.ctrl_enabled (offload0_enabled_s),
|
||||
.ctrl_mem_reset (offload0_mem_reset_s),
|
||||
.spi_clk (up_clk),
|
||||
.spi_resetn (spi_resetn_s),
|
||||
.trigger (trigger_s),
|
||||
.cmd_valid (s1_cmd_valid_s),
|
||||
.cmd_ready (s1_cmd_ready_s),
|
||||
.cmd (s1_cmd_data_s),
|
||||
.sdo_data_valid (s1_sdo_data_valid_s),
|
||||
.sdo_data_ready (s1_sdo_data_ready_s),
|
||||
.sdo_data (s1_sdo_data_s),
|
||||
.sdi_data_valid (s1_sdi_data_valid_s),
|
||||
.sdi_data_ready (s1_sdi_data_ready_s),
|
||||
.sdi_data (s1_sdi_data_s),
|
||||
.sync_valid (s1_sync_valid_s),
|
||||
.sync_ready (s1_sync_ready_s),
|
||||
.sync_data (s1_sync_s),
|
||||
.offload_sdi_valid (m_axis_valid_s),
|
||||
.offload_sdi_ready (m_axis_ready_s),
|
||||
.offload_sdi_data (m_axis_data_s));
|
||||
|
||||
spi_engine_interconnect #(
|
||||
.DATA_WIDTH (8),
|
||||
.NUM_OF_SDI (NUM_OF_SDI)
|
||||
) i_spi_engine_interconnect (
|
||||
.clk (up_clk),
|
||||
.resetn (spi_resetn_s),
|
||||
.m_cmd_valid (m_cmd_valid_s),
|
||||
.m_cmd_ready (m_cmd_ready_s),
|
||||
.m_cmd_data (m_cmd_data_s),
|
||||
.m_sdo_valid (m_sdo_data_valid_s),
|
||||
.m_sdo_ready (m_sdo_data_ready_s),
|
||||
.m_sdo_data (m_sdo_data_s),
|
||||
.m_sdi_valid (m_sdi_data_valid_s),
|
||||
.m_sdi_ready (m_sdi_data_ready_s),
|
||||
.m_sdi_data (m_sdi_data_s),
|
||||
.m_sync_valid (m_sync_valid_s),
|
||||
.m_sync_ready (m_sync_ready_s),
|
||||
.m_sync (m_sync_s),
|
||||
.s0_cmd_valid (s0_cmd_valid_s),
|
||||
.s0_cmd_ready (s0_cmd_ready_s),
|
||||
.s0_cmd_data (s0_cmd_data_s),
|
||||
.s0_sdo_valid (s0_sdo_data_valid_s),
|
||||
.s0_sdo_ready (s0_sdo_data_ready_s),
|
||||
.s0_sdo_data (s0_sdo_data_s),
|
||||
.s0_sdi_valid (s0_sdi_data_valid_s),
|
||||
.s0_sdi_ready (s0_sdi_data_ready_s),
|
||||
.s0_sdi_data (s0_sdi_data_s),
|
||||
.s0_sync_valid (s0_sync_valid_s),
|
||||
.s0_sync_ready (s0_sync_ready_s),
|
||||
.s0_sync (s0_sync_s),
|
||||
.s1_cmd_valid (s1_cmd_valid_s),
|
||||
.s1_cmd_ready (s1_cmd_ready_s),
|
||||
.s1_cmd_data (s1_cmd_data_s),
|
||||
.s1_sdo_valid (s1_sdo_data_valid_s),
|
||||
.s1_sdo_ready (s1_sdo_data_ready_s),
|
||||
.s1_sdo_data (s1_sdo_data_s),
|
||||
.s1_sdi_valid (s1_sdi_data_valid_s),
|
||||
.s1_sdi_ready (s1_sdi_data_ready_s),
|
||||
.s1_sdi_data (s1_sdi_data_s),
|
||||
.s1_sync_valid (s1_sync_valid_s),
|
||||
.s1_sync_ready (s1_sync_ready_s),
|
||||
.s1_sync (s1_sync_s));
|
||||
|
||||
spi_engine_execution #(
|
||||
.DATA_WIDTH (8),
|
||||
.NUM_OF_SDI (NUM_OF_SDI)
|
||||
) i_spi_engine_execution (
|
||||
.clk (up_clk),
|
||||
.resetn (spi_resetn_s),
|
||||
.active (),
|
||||
.cmd_ready (m_cmd_ready_s),
|
||||
.cmd_valid (m_cmd_valid_s),
|
||||
.cmd (m_cmd_data_s),
|
||||
.sdo_data_valid (m_sdo_data_valid_s),
|
||||
.sdo_data_ready (m_sdo_data_ready_s),
|
||||
.sdo_data (m_sdo_data_s),
|
||||
.sdi_data_ready (m_sdi_data_ready_s),
|
||||
.sdi_data_valid (m_sdi_data_valid_s),
|
||||
.sdi_data (m_sdi_data_s),
|
||||
.sync_ready (m_sync_ready_s),
|
||||
.sync_valid (m_sync_valid_s),
|
||||
.sync (m_sync_s),
|
||||
.sclk (rx_sclk),
|
||||
.sdo (rx_sdo),
|
||||
.sdo_t (),
|
||||
.sdi (rx_sdi),
|
||||
.cs (rx_cs_n),
|
||||
.three_wire ());
|
||||
|
||||
axi_ad7616_maxis2wrfifo #(
|
||||
.DATA_WIDTH(16)
|
||||
) i_maxis2wrfifo (
|
||||
.clk(up_clk),
|
||||
.rstn(up_rstn),
|
||||
.sync_in(trigger_s),
|
||||
.m_axis_data(m_axis_data_s),
|
||||
.m_axis_ready(m_axis_ready_s),
|
||||
.m_axis_valid(m_axis_valid_s),
|
||||
.fifo_wr_en(adc_valid),
|
||||
.fifo_wr_data(adc_data),
|
||||
.fifo_wr_sync(adc_sync),
|
||||
.fifo_wr_xfer_req(1'b1)
|
||||
);
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate if (IF_TYPE == PARALLEL) begin
|
||||
|
||||
assign rx_sclk = 1'h0;
|
||||
assign rx_sdo = 1'h0;
|
||||
assign irq = 1'h0;
|
||||
|
||||
assign up_wack_if_s = 1'h0;
|
||||
assign up_rack_if_s = 1'h0;
|
||||
assign up_rdata_if_s = 1'h0;
|
||||
|
||||
axi_ad7616_pif i_ad7616_parallel_interface (
|
||||
.cs_n (rx_cs_n),
|
||||
.db_o (rx_db_o),
|
||||
.db_i (rx_db_i),
|
||||
.db_t (rx_db_t),
|
||||
.rd_n (rx_rd_n),
|
||||
.wr_n (rx_wr_n),
|
||||
.adc_data (adc_data),
|
||||
.adc_valid (adc_valid),
|
||||
.adc_sync (adc_sync),
|
||||
.end_of_conv (trigger_s),
|
||||
.burst_length(burst_length_s),
|
||||
.clk (up_clk),
|
||||
.rstn (up_rstn),
|
||||
.rd_req (rd_req_s),
|
||||
.wr_req (wr_req_s),
|
||||
.wr_data (wr_data_s),
|
||||
.rd_data (rd_data_s),
|
||||
.rd_valid (rd_valid_s)
|
||||
);
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
axi_ad7616_control #(
|
||||
.ID(ID),
|
||||
.IF_TYPE(IF_TYPE)
|
||||
) i_ad7616_control (
|
||||
.cnvst (rx_cnvst),
|
||||
.busy (rx_busy),
|
||||
.up_burst_length (burst_length_s),
|
||||
.up_read_data (rd_data_s),
|
||||
.up_read_valid (rd_valid_s),
|
||||
.up_write_data (wr_data_s),
|
||||
.up_read_req (rd_req_s),
|
||||
.up_write_req (wr_req_s),
|
||||
.end_of_conv (trigger_s),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq_s),
|
||||
.up_waddr (up_waddr_s),
|
||||
.up_wdata (up_wdata_s),
|
||||
.up_wack (up_wack_cntrl_s),
|
||||
.up_rreq (up_rreq_s),
|
||||
.up_raddr (up_raddr_s),
|
||||
.up_rdata (up_rdata_cntrl_s),
|
||||
.up_rack (up_rack_cntrl_s));
|
||||
|
||||
// up bus interface
|
||||
|
||||
up_axi #(
|
||||
.AXI_ADDRESS_WIDTH (16)
|
||||
) i_up_axi (
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_axi_awvalid (s_axi_awvalid),
|
||||
.up_axi_awaddr (s_axi_awaddr),
|
||||
.up_axi_awready (s_axi_awready),
|
||||
.up_axi_wvalid (s_axi_wvalid),
|
||||
.up_axi_wdata (s_axi_wdata),
|
||||
.up_axi_wstrb (s_axi_wstrb),
|
||||
.up_axi_wready (s_axi_wready),
|
||||
.up_axi_bvalid (s_axi_bvalid),
|
||||
.up_axi_bresp (s_axi_bresp),
|
||||
.up_axi_bready (s_axi_bready),
|
||||
.up_axi_arvalid (s_axi_arvalid),
|
||||
.up_axi_araddr (s_axi_araddr),
|
||||
.up_axi_arready (s_axi_arready),
|
||||
.up_axi_rvalid (s_axi_rvalid),
|
||||
.up_axi_rresp (s_axi_rresp),
|
||||
.up_axi_rdata (s_axi_rdata),
|
||||
.up_axi_rready (s_axi_rready),
|
||||
.up_wreq (up_wreq_s),
|
||||
.up_waddr (up_waddr_s),
|
||||
.up_wdata (up_wdata_s),
|
||||
.up_wack (up_wack),
|
||||
.up_rreq (up_rreq_s),
|
||||
.up_raddr (up_raddr_s),
|
||||
.up_rdata (up_rdata),
|
||||
.up_rack (up_rack));
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
@@ -0,0 +1,411 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Version="7" Minor="40" Path="/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad7616/axi_ad7616.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="93a79731539548dc9c23f3a4f29953b7"/>
|
||||
<Option Name="Part" Val="xc7vx485tffg1157-1"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="BoardPart" Val=""/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../library"/>
|
||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../../ghdl/library"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="DSAVendor" Val="xilinx"/>
|
||||
<Option Name="DSANumComputeUnits" Val="60"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="0"/>
|
||||
<Option Name="WTModelSimExportSim" Val="0"/>
|
||||
<Option Name="WTQuestaExportSim" Val="0"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="0"/>
|
||||
<Option Name="WTRivieraExportSim" Val="0"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
<Option Name="SimTypes" Val="bfm"/>
|
||||
<Option Name="SimTypes" Val="tlm"/>
|
||||
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="31">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/../common/ad_edge_detect.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/axi_ad7616_control.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/axi_ad7616_maxis2wrfifo.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/axi_ad7616_pif.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../common/up_axi.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/axi_ad7616.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/component.xml">
|
||||
<FileInfo SFType="IPXACT"/>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="axi_ad7616"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="IES">
|
||||
<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Xcelium">
|
||||
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="VCS">
|
||||
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="10">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Vivado 12-1790"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="1"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="Evaluation"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="features"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="should"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="NOT"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="be"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="used"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="in"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="production"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="systems."/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Place 30-73"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="10"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="axi_spi"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val=""/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="11"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1343"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="2"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1306"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="3"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="ERROR"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1276"/>
|
||||
<MsgAttr Name="Severity" Val="CRITICAL WARNING"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="4"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-3656"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="5"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-4623"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="6"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-459"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="7"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Synth 8-3331"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="8"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Designutils 20-3303"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="9"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="HDPYFinalizeIO"/>
|
||||
</MsgRule>
|
||||
<Board/>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
<BootPmcSettings Version="1" Minor="0">
|
||||
<Parameters>
|
||||
<Parameter Name="PMC_CDO.ATTRS.LOADADDR" Value="" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_FB_CLK" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_FREQ" Value="300" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_BUS_WIDTH" Value="x1" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_DATA_MODE" Value="Single" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_FREQ" Value="200" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_SLOT_TYPE" Value="SD 2.0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_FREQ" Value="200" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_SLOT_TYPE" Value="SD 2.0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSPI_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSPI_FREQ" Value="300" Type="string"/>
|
||||
<Parameter Name="BOOT.USB_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SMAP_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SMAP_DATA_WIDTH" Value="32 Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSC_FREQ" Value="33.333" Type="string"/>
|
||||
<Parameter Name="BOOT.SECONDARY.PCIE_ENABLE" Value="0" Type="string"/>
|
||||
</Parameters>
|
||||
</BootPmcSettings>
|
||||
</Project>
|
||||
@@ -0,0 +1,211 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module axi_ad7616_control #(
|
||||
|
||||
parameter ID = 0,
|
||||
parameter IF_TYPE = 0) (
|
||||
|
||||
// control signals
|
||||
|
||||
output cnvst,
|
||||
input busy,
|
||||
|
||||
input [15:0] up_read_data,
|
||||
input up_read_valid,
|
||||
output reg [15:0] up_write_data,
|
||||
output up_read_req,
|
||||
output up_write_req,
|
||||
|
||||
output reg [ 4:0] up_burst_length,
|
||||
output end_of_conv,
|
||||
|
||||
// bus interface
|
||||
|
||||
input up_rstn,
|
||||
input up_clk,
|
||||
input up_wreq,
|
||||
input [13:0] up_waddr,
|
||||
input [31:0] up_wdata,
|
||||
output reg up_wack,
|
||||
input up_rreq,
|
||||
input [13:0] up_raddr,
|
||||
output reg [31:0] up_rdata,
|
||||
output reg up_rack
|
||||
);
|
||||
|
||||
|
||||
localparam PCORE_VERSION = 'h00001002;
|
||||
localparam POS_EDGE = 0;
|
||||
localparam NEG_EDGE = 1;
|
||||
localparam SERIAL = 0;
|
||||
localparam PARALLEL = 1;
|
||||
|
||||
// internal signals
|
||||
|
||||
reg [31:0] up_scratch = 32'b0;
|
||||
reg up_resetn = 1'b0;
|
||||
reg up_cnvst_en = 1'b0;
|
||||
reg [31:0] up_conv_rate = 32'b0;
|
||||
|
||||
reg [31:0] cnvst_counter = 32'b0;
|
||||
reg [ 3:0] pulse_counter = 8'b0;
|
||||
reg cnvst_buf = 1'b0;
|
||||
reg cnvst_pulse = 1'b0;
|
||||
reg [ 2:0] chsel_ff = 3'b0;
|
||||
|
||||
wire up_rst;
|
||||
wire up_rack_s;
|
||||
|
||||
wire [31:0] up_read_data_s;
|
||||
wire up_read_valid_s;
|
||||
|
||||
// the up_[read/write]_data interfaces are valid just in parallel mode
|
||||
|
||||
assign up_read_valid_s = (IF_TYPE == PARALLEL) ? up_read_valid : 1'b1;
|
||||
assign up_read_data_s = (IF_TYPE == PARALLEL) ? {16'h0, up_read_data} : {2{16'hDEAD}};
|
||||
|
||||
// processor write interface
|
||||
|
||||
always @(negedge up_rstn or posedge up_clk) begin
|
||||
if (up_rstn == 0) begin
|
||||
up_wack <= 1'h0;
|
||||
up_scratch <= 32'b0;
|
||||
up_resetn <= 1'b0;
|
||||
up_cnvst_en <= 1'b0;
|
||||
up_conv_rate <= 32'b0;
|
||||
up_burst_length <= 5'h0;
|
||||
up_write_data <= 16'h0;
|
||||
end else begin
|
||||
up_wack <= up_wreq;
|
||||
if ((up_wreq == 1'b1) && (up_waddr[8:0] == 9'h102)) begin
|
||||
up_scratch <= up_wdata;
|
||||
end
|
||||
if ((up_wreq == 1'b1) && (up_waddr[8:0] == 9'h110)) begin
|
||||
up_resetn <= up_wdata[0];
|
||||
up_cnvst_en <= up_wdata[1];
|
||||
end
|
||||
if ((up_wreq == 1'b1) && (up_waddr[8:0] == 9'h111)) begin
|
||||
up_conv_rate <= up_wdata;
|
||||
end
|
||||
if ((up_wreq == 1'b1) && (up_waddr[8:0] == 9'h112)) begin
|
||||
up_burst_length <= up_wdata;
|
||||
end
|
||||
if ((up_wreq == 1'b1) && (up_waddr[8:0] == 9'h114)) begin
|
||||
up_write_data <= up_wdata;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign up_write_req = (up_waddr[8:0] == 9'h114) ? up_wreq : 1'h0;
|
||||
|
||||
// processor read interface
|
||||
|
||||
assign up_rack_s = (up_raddr[8:0] == 9'h113) ? up_read_valid_s : up_rreq;
|
||||
assign up_read_req = (up_raddr[8:0] == 9'h113) ? up_rreq : 1'b0;
|
||||
|
||||
always @(negedge up_rstn or posedge up_clk) begin
|
||||
if (up_rstn == 0) begin
|
||||
up_rack <= 1'b0;
|
||||
up_rdata <= 32'b0;
|
||||
end else begin
|
||||
up_rack <= up_rack_s;
|
||||
if (up_rack_s == 1'b1) begin
|
||||
case (up_raddr[8:0])
|
||||
9'h100 : up_rdata <= PCORE_VERSION;
|
||||
9'h101 : up_rdata <= ID;
|
||||
9'h102 : up_rdata <= up_scratch;
|
||||
9'h103 : up_rdata <= IF_TYPE;
|
||||
9'h110 : up_rdata <= {29'b0, up_cnvst_en, up_resetn};
|
||||
9'h111 : up_rdata <= up_conv_rate;
|
||||
9'h112 : up_rdata <= {27'b0, up_burst_length};
|
||||
9'h113 : up_rdata <= up_read_data_s;
|
||||
default : up_rdata <= 'h0;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// instantiations
|
||||
|
||||
assign up_rst = ~up_rstn;
|
||||
|
||||
ad_edge_detect #(
|
||||
.EDGE(NEG_EDGE)
|
||||
) i_ad_edge_detect (
|
||||
.clk (up_clk),
|
||||
.rst (up_rst),
|
||||
.signal_in (busy),
|
||||
.signal_out (end_of_conv)
|
||||
);
|
||||
|
||||
// convertion start generator
|
||||
// NOTE: + The minimum convertion cycle is 1 us
|
||||
// + The rate of the cnvst must be defined in a way,
|
||||
// to not lose any data. cnvst_rate >= t_conversion + t_aquisition
|
||||
// See the AD7616 datasheet for more information.
|
||||
|
||||
always @(posedge up_clk) begin
|
||||
if(up_resetn == 1'b0) begin
|
||||
cnvst_counter <= 32'b0;
|
||||
end else begin
|
||||
cnvst_counter <= (cnvst_counter < up_conv_rate) ? cnvst_counter + 1 : 32'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(cnvst_counter, up_conv_rate) begin
|
||||
cnvst_pulse <= (cnvst_counter == up_conv_rate) ? 1'b1 : 1'b0;
|
||||
end
|
||||
|
||||
always @(posedge up_clk) begin
|
||||
if(up_resetn == 1'b0) begin
|
||||
pulse_counter <= 3'b0;
|
||||
cnvst_buf <= 1'b0;
|
||||
end else begin
|
||||
pulse_counter <= (cnvst == 1'b1) ? pulse_counter + 1 : 3'b0;
|
||||
if(cnvst_pulse == 1'b1) begin
|
||||
cnvst_buf <= 1'b1;
|
||||
end else if (pulse_counter[2] == 1'b1) begin
|
||||
cnvst_buf <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign cnvst = (up_cnvst_en == 1'b1) ? cnvst_buf : 1'b0;
|
||||
|
||||
endmodule
|
||||
|
||||
@@ -0,0 +1,27 @@
|
||||
# ip
|
||||
|
||||
source ../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
|
||||
adi_ip_create axi_ad7616
|
||||
adi_ip_files axi_ad7616 [list \
|
||||
"$ad_hdl_dir/library/common/ad_edge_detect.v" \
|
||||
"$ad_hdl_dir/library/common/up_axi.v" \
|
||||
"axi_ad7616_control.v" \
|
||||
"axi_ad7616_pif.v" \
|
||||
"axi_ad7616_maxis2wrfifo.v" \
|
||||
"axi_ad7616.v" ]
|
||||
|
||||
adi_ip_properties axi_ad7616
|
||||
|
||||
adi_ip_add_core_dependencies { \
|
||||
analog.com:user:spi_engine_execution:1.0 \
|
||||
analog.com:user:axi_spi_engine:1.0 \
|
||||
analog.com:user:spi_engine_offload:1.0 \
|
||||
analog.com:user:spi_engine_interconnect:1.0 \
|
||||
}
|
||||
|
||||
set_property DRIVER_VALUE "0" [ipx::get_ports rx_db_i]
|
||||
|
||||
ipx::save_core [ipx::current_core]
|
||||
|
||||
@@ -0,0 +1,83 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module axi_ad7616_maxis2wrfifo #(
|
||||
|
||||
parameter DATA_WIDTH = 16) (
|
||||
|
||||
input clk,
|
||||
input rstn,
|
||||
input sync_in,
|
||||
|
||||
// m_axis interface
|
||||
|
||||
input [DATA_WIDTH-1:0] m_axis_data,
|
||||
output reg m_axis_ready,
|
||||
input m_axis_valid,
|
||||
output reg m_axis_xfer_req,
|
||||
|
||||
// write fifo interface
|
||||
|
||||
output reg fifo_wr_en,
|
||||
output reg [DATA_WIDTH-1:0] fifo_wr_data,
|
||||
output reg fifo_wr_sync,
|
||||
input fifo_wr_xfer_req
|
||||
);
|
||||
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rstn == 1'b0) begin
|
||||
m_axis_ready <= 1'b0;
|
||||
m_axis_xfer_req <= 1'b0;
|
||||
fifo_wr_data <= 'b0;
|
||||
fifo_wr_en <= 1'b0;
|
||||
fifo_wr_sync <= 1'b0;
|
||||
end else begin
|
||||
m_axis_ready <= 1'b1;
|
||||
m_axis_xfer_req <= fifo_wr_xfer_req;
|
||||
fifo_wr_data <= m_axis_data;
|
||||
fifo_wr_en <= m_axis_valid;
|
||||
if (sync_in == 1'b1) begin
|
||||
fifo_wr_sync <= 1'b1;
|
||||
end else if ((m_axis_valid == 1'b1) &&
|
||||
(fifo_wr_sync == 1'b1)) begin
|
||||
fifo_wr_sync <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,215 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module axi_ad7616_pif #(
|
||||
|
||||
parameter UP_ADDRESS_WIDTH = 14) (
|
||||
|
||||
// physical interface
|
||||
|
||||
output cs_n,
|
||||
output [15:0] db_o,
|
||||
input [15:0] db_i,
|
||||
output db_t,
|
||||
output rd_n,
|
||||
output wr_n,
|
||||
|
||||
// FIFO interface
|
||||
|
||||
output [15:0] adc_data,
|
||||
output adc_valid,
|
||||
output reg adc_sync,
|
||||
|
||||
// end of convertion
|
||||
|
||||
input end_of_conv,
|
||||
input [ 4:0] burst_length,
|
||||
|
||||
// register access
|
||||
|
||||
input clk,
|
||||
input rstn,
|
||||
input rd_req,
|
||||
input wr_req,
|
||||
input [15:0] wr_data,
|
||||
output reg [15:0] rd_data,
|
||||
output reg rd_valid);
|
||||
|
||||
|
||||
// state registers
|
||||
|
||||
localparam [ 2:0] IDLE = 3'h0,
|
||||
CS_LOW = 3'h1,
|
||||
CNTRL0_LOW = 3'h2,
|
||||
CNTRL0_HIGH = 3'h3,
|
||||
CNTRL1_LOW = 3'h4,
|
||||
CNTRL1_HIGH = 3'h5,
|
||||
CS_HIGH = 3'h6;
|
||||
|
||||
// internal registers
|
||||
|
||||
reg [ 2:0] transfer_state = 3'h0;
|
||||
reg [ 2:0] transfer_state_next = 3'h0;
|
||||
reg [ 1:0] width_counter = 2'h0;
|
||||
reg [ 4:0] burst_counter = 5'h0;
|
||||
|
||||
reg wr_req_d = 1'h0;
|
||||
reg rd_req_d = 1'h0;
|
||||
reg rd_conv_d = 1'h0;
|
||||
|
||||
reg xfer_req_d = 1'h0;
|
||||
|
||||
reg rd_valid_d = 1'h0;
|
||||
|
||||
// internal wires
|
||||
|
||||
wire start_transfer_s;
|
||||
wire rd_valid_s;
|
||||
|
||||
// FSM state register
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rstn == 1'b0) begin
|
||||
transfer_state <= 3'h0;
|
||||
end else begin
|
||||
transfer_state <= transfer_state_next;
|
||||
end
|
||||
end
|
||||
|
||||
// counters to control the RD_N and WR_N lines
|
||||
|
||||
assign start_transfer_s = end_of_conv | rd_req | wr_req;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rstn == 1'b0) begin
|
||||
width_counter <= 2'h0;
|
||||
end else begin
|
||||
if((transfer_state == CNTRL0_LOW) || (transfer_state == CNTRL0_HIGH) ||
|
||||
(transfer_state == CNTRL1_LOW) || (transfer_state == CNTRL1_HIGH))
|
||||
width_counter <= width_counter + 1;
|
||||
else
|
||||
width_counter <= 2'h0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rstn == 1'b0) begin
|
||||
burst_counter <= 2'h0;
|
||||
end else begin
|
||||
if (transfer_state == CS_HIGH)
|
||||
burst_counter <= burst_counter + 1;
|
||||
else if (transfer_state == IDLE)
|
||||
burst_counter <= 5'h0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(negedge clk) begin
|
||||
if (transfer_state == IDLE) begin
|
||||
wr_req_d <= wr_req;
|
||||
rd_req_d <= rd_req;
|
||||
rd_conv_d <= end_of_conv;
|
||||
end
|
||||
end
|
||||
|
||||
// FSM next state logic
|
||||
|
||||
always @(*) begin
|
||||
case (transfer_state)
|
||||
IDLE : begin
|
||||
transfer_state_next <= (start_transfer_s == 1'b1) ? CS_LOW : IDLE;
|
||||
end
|
||||
CS_LOW : begin
|
||||
transfer_state_next <= CNTRL0_LOW;
|
||||
end
|
||||
CNTRL0_LOW : begin
|
||||
transfer_state_next <= (width_counter != 2'b11) ? CNTRL0_LOW : CNTRL0_HIGH;
|
||||
end
|
||||
CNTRL0_HIGH : begin
|
||||
transfer_state_next <= (width_counter != 2'b11) ? CNTRL0_HIGH :
|
||||
((wr_req_d == 1'b1) || (rd_req_d == 1'b1)) ? CS_HIGH : CNTRL1_LOW;
|
||||
end
|
||||
CNTRL1_LOW : begin
|
||||
transfer_state_next <= (width_counter != 2'b11) ? CNTRL1_LOW : CNTRL1_HIGH;
|
||||
end
|
||||
CNTRL1_HIGH : begin
|
||||
transfer_state_next <= (width_counter != 2'b11) ? CNTRL1_HIGH : CS_HIGH;
|
||||
end
|
||||
CS_HIGH : begin
|
||||
transfer_state_next <= (burst_length == burst_counter) ? IDLE : CNTRL0_LOW;
|
||||
end
|
||||
default : begin
|
||||
transfer_state_next <= IDLE;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
// data valid for the register access and m_axis interface
|
||||
|
||||
assign rd_valid_s = (((transfer_state == CNTRL0_HIGH) || (transfer_state == CNTRL1_HIGH)) &&
|
||||
((rd_req_d == 1'b1) || (rd_conv_d == 1'b1))) ? 1'b1 : 1'b0;
|
||||
|
||||
// FSM output logic
|
||||
|
||||
assign db_o = wr_data;
|
||||
|
||||
always @(posedge clk) begin
|
||||
rd_data <= (rd_valid_s & ~rd_valid_d) ? db_i : rd_data;
|
||||
rd_valid_d <= rd_valid_s;
|
||||
rd_valid <= rd_valid_s & ~rd_valid_d;
|
||||
end
|
||||
|
||||
assign adc_valid = rd_valid;
|
||||
assign adc_data = rd_data;
|
||||
|
||||
assign cs_n = (transfer_state == IDLE) ? 1'b1 : 1'b0;
|
||||
assign db_t = ~wr_req_d;
|
||||
assign rd_n = (((transfer_state == CNTRL0_LOW) && ((rd_conv_d == 1'b1) || rd_req_d == 1'b1)) ||
|
||||
(transfer_state == CNTRL1_LOW)) ? 1'b0 : 1'b1;
|
||||
assign wr_n = ((transfer_state == CNTRL0_LOW) && (wr_req_d == 1'b1)) ? 1'b0 : 1'b1;
|
||||
|
||||
// sync will be asserted at the first valid data right after the convertion start
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (end_of_conv == 1'b1) begin
|
||||
adc_sync <= 1'b1;
|
||||
end else if (rd_valid == 1'b1) begin
|
||||
adc_sync <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,40 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||
ipgui::add_param $IPINST -name "ID" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "IF_TYPE" -parent ${Page_0}
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } {
|
||||
# Procedure called to update ID when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } {
|
||||
# Procedure called to validate ID
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.IF_TYPE { PARAM_VALUE.IF_TYPE } {
|
||||
# Procedure called to update IF_TYPE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.IF_TYPE { PARAM_VALUE.IF_TYPE } {
|
||||
# Procedure called to validate IF_TYPE
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.IF_TYPE { MODELPARAM_VALUE.IF_TYPE PARAM_VALUE.IF_TYPE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.IF_TYPE}] ${MODELPARAM_VALUE.IF_TYPE}
|
||||
}
|
||||
|
||||
@@ -0,0 +1,45 @@
|
||||
####################################################################################
|
||||
## Copyright 2018(c) Analog Devices, Inc.
|
||||
## Auto-generated, do not modify!
|
||||
####################################################################################
|
||||
|
||||
LIBRARY_NAME := axi_ad9122
|
||||
|
||||
GENERIC_DEPS += ../common/ad_dds.v
|
||||
GENERIC_DEPS += ../common/ad_dds_1.v
|
||||
GENERIC_DEPS += ../common/ad_dds_2.v
|
||||
GENERIC_DEPS += ../common/ad_dds_cordic_pipe.v
|
||||
GENERIC_DEPS += ../common/ad_dds_sine.v
|
||||
GENERIC_DEPS += ../common/ad_dds_sine_cordic.v
|
||||
GENERIC_DEPS += ../common/ad_rst.v
|
||||
GENERIC_DEPS += ../common/up_axi.v
|
||||
GENERIC_DEPS += ../common/up_clock_mon.v
|
||||
GENERIC_DEPS += ../common/up_dac_channel.v
|
||||
GENERIC_DEPS += ../common/up_dac_common.v
|
||||
GENERIC_DEPS += ../common/up_xfer_cntrl.v
|
||||
GENERIC_DEPS += ../common/up_xfer_status.v
|
||||
GENERIC_DEPS += axi_ad9122.v
|
||||
GENERIC_DEPS += axi_ad9122_channel.v
|
||||
GENERIC_DEPS += axi_ad9122_core.v
|
||||
GENERIC_DEPS += axi_ad9122_if.v
|
||||
|
||||
XILINX_DEPS += ../xilinx/common/ad_mmcm_drp.v
|
||||
XILINX_DEPS += ../xilinx/common/ad_mul.v
|
||||
XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc
|
||||
XILINX_DEPS += ../xilinx/common/ad_serdes_clk.v
|
||||
XILINX_DEPS += ../xilinx/common/ad_serdes_out.v
|
||||
XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc
|
||||
XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
|
||||
XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc
|
||||
XILINX_DEPS += axi_ad9122_constr.xdc
|
||||
XILINX_DEPS += axi_ad9122_ip.tcl
|
||||
|
||||
INTEL_DEPS += ../intel/common/ad_mul.v
|
||||
INTEL_DEPS += ../intel/common/up_clock_mon_constr.sdc
|
||||
INTEL_DEPS += ../intel/common/up_rst_constr.sdc
|
||||
INTEL_DEPS += ../intel/common/up_xfer_cntrl_constr.sdc
|
||||
INTEL_DEPS += ../intel/common/up_xfer_status_constr.sdc
|
||||
INTEL_DEPS += axi_ad9122_constr.sdc
|
||||
INTEL_DEPS += axi_ad9122_hw.tcl
|
||||
|
||||
include ../scripts/library.mk
|
||||
@@ -0,0 +1,3 @@
|
||||
version:1
|
||||
6d6f64655f636f756e7465727c42617463684d6f6465:1
|
||||
eof:
|
||||
@@ -0,0 +1,6 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<labtools version="1" minor="0"/>
|
||||
@@ -0,0 +1,302 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module axi_ad9122 #(
|
||||
|
||||
parameter ID = 0,
|
||||
parameter FPGA_TECHNOLOGY = 0,
|
||||
parameter FPGA_FAMILY = 0,
|
||||
parameter SPEED_GRADE = 0,
|
||||
parameter DEV_PACKAGE = 0,
|
||||
parameter SERDES_OR_DDR_N = 1,
|
||||
parameter MMCM_OR_BUFIO_N = 1,
|
||||
parameter MMCM_CLKIN_PERIOD = 1.667,
|
||||
parameter MMCM_VCO_DIV = 2,
|
||||
parameter MMCM_VCO_MUL = 4,
|
||||
parameter MMCM_CLK0_DIV = 2,
|
||||
parameter MMCM_CLK1_DIV = 8,
|
||||
parameter DAC_DATAPATH_DISABLE = 0,
|
||||
parameter DAC_DDS_TYPE = 1,
|
||||
parameter DAC_DDS_CORDIC_DW = 20,
|
||||
parameter DAC_DDS_CORDIC_PHASE_DW = 18,
|
||||
parameter IO_DELAY_GROUP = "dev_if_delay_group") (
|
||||
|
||||
// dac interface
|
||||
|
||||
input dac_clk_in_p,
|
||||
input dac_clk_in_n,
|
||||
output dac_clk_out_p,
|
||||
output dac_clk_out_n,
|
||||
output dac_frame_out_p,
|
||||
output dac_frame_out_n,
|
||||
output [15:0] dac_data_out_p,
|
||||
output [15:0] dac_data_out_n,
|
||||
|
||||
// master/slave
|
||||
|
||||
output dac_sync_out,
|
||||
input dac_sync_in,
|
||||
|
||||
// dma interface
|
||||
|
||||
output dac_div_clk,
|
||||
output dac_valid_0,
|
||||
output dac_enable_0,
|
||||
input [63:0] dac_ddata_0,
|
||||
output dac_valid_1,
|
||||
output dac_enable_1,
|
||||
input [63:0] dac_ddata_1,
|
||||
input dac_dunf,
|
||||
|
||||
// axi interface
|
||||
|
||||
input s_axi_aclk,
|
||||
input s_axi_aresetn,
|
||||
input s_axi_awvalid,
|
||||
input [15:0] s_axi_awaddr,
|
||||
output s_axi_awready,
|
||||
input s_axi_wvalid,
|
||||
input [31:0] s_axi_wdata,
|
||||
input [ 3:0] s_axi_wstrb,
|
||||
output s_axi_wready,
|
||||
output s_axi_bvalid,
|
||||
output [ 1:0] s_axi_bresp,
|
||||
input s_axi_bready,
|
||||
input s_axi_arvalid,
|
||||
input [15:0] s_axi_araddr,
|
||||
output s_axi_arready,
|
||||
output s_axi_rvalid,
|
||||
output [31:0] s_axi_rdata,
|
||||
output [ 1:0] s_axi_rresp,
|
||||
input s_axi_rready,
|
||||
input [ 2:0] s_axi_awprot,
|
||||
input [ 2:0] s_axi_arprot);
|
||||
|
||||
|
||||
// internal clocks and resets
|
||||
|
||||
wire dac_rst;
|
||||
wire mmcm_rst;
|
||||
wire up_clk;
|
||||
wire up_rstn;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire dac_frame_i0_s;
|
||||
wire [15:0] dac_data_i0_s;
|
||||
wire dac_frame_i1_s;
|
||||
wire [15:0] dac_data_i1_s;
|
||||
wire dac_frame_i2_s;
|
||||
wire [15:0] dac_data_i2_s;
|
||||
wire dac_frame_i3_s;
|
||||
wire [15:0] dac_data_i3_s;
|
||||
wire dac_frame_q0_s;
|
||||
wire [15:0] dac_data_q0_s;
|
||||
wire dac_frame_q1_s;
|
||||
wire [15:0] dac_data_q1_s;
|
||||
wire dac_frame_q2_s;
|
||||
wire [15:0] dac_data_q2_s;
|
||||
wire dac_frame_q3_s;
|
||||
wire [15:0] dac_data_q3_s;
|
||||
wire dac_status_s;
|
||||
wire up_drp_sel_s;
|
||||
wire up_drp_wr_s;
|
||||
wire [11:0] up_drp_addr_s;
|
||||
wire [31:0] up_drp_wdata_s;
|
||||
wire [31:0] up_drp_rdata_s;
|
||||
wire up_drp_ready_s;
|
||||
wire up_drp_locked_s;
|
||||
wire up_wreq_s;
|
||||
wire [13:0] up_waddr_s;
|
||||
wire [31:0] up_wdata_s;
|
||||
wire up_wack_s;
|
||||
wire up_rreq_s;
|
||||
wire [13:0] up_raddr_s;
|
||||
wire [31:0] up_rdata_s;
|
||||
wire up_rack_s;
|
||||
|
||||
// signal name changes
|
||||
|
||||
assign up_clk = s_axi_aclk;
|
||||
assign up_rstn = s_axi_aresetn;
|
||||
|
||||
// device interface
|
||||
|
||||
axi_ad9122_if #(
|
||||
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
|
||||
.SERDES_OR_DDR_N (SERDES_OR_DDR_N),
|
||||
.MMCM_OR_BUFIO_N (MMCM_OR_BUFIO_N),
|
||||
.MMCM_CLKIN_PERIOD (MMCM_CLKIN_PERIOD),
|
||||
.MMCM_VCO_DIV (MMCM_VCO_DIV),
|
||||
.MMCM_VCO_MUL (MMCM_VCO_MUL),
|
||||
.MMCM_CLK0_DIV (MMCM_CLK0_DIV),
|
||||
.MMCM_CLK1_DIV (MMCM_CLK1_DIV))
|
||||
i_if (
|
||||
.dac_clk_in_p (dac_clk_in_p),
|
||||
.dac_clk_in_n (dac_clk_in_n),
|
||||
.dac_clk_out_p (dac_clk_out_p),
|
||||
.dac_clk_out_n (dac_clk_out_n),
|
||||
.dac_frame_out_p (dac_frame_out_p),
|
||||
.dac_frame_out_n (dac_frame_out_n),
|
||||
.dac_data_out_p (dac_data_out_p),
|
||||
.dac_data_out_n (dac_data_out_n),
|
||||
.dac_rst (dac_rst),
|
||||
.dac_clk (),
|
||||
.dac_div_clk (dac_div_clk),
|
||||
.dac_status (dac_status_s),
|
||||
.dac_frame_i0 (dac_frame_i0_s),
|
||||
.dac_data_i0 (dac_data_i0_s),
|
||||
.dac_frame_i1 (dac_frame_i1_s),
|
||||
.dac_data_i1 (dac_data_i1_s),
|
||||
.dac_frame_i2 (dac_frame_i2_s),
|
||||
.dac_data_i2 (dac_data_i2_s),
|
||||
.dac_frame_i3 (dac_frame_i3_s),
|
||||
.dac_data_i3 (dac_data_i3_s),
|
||||
.dac_frame_q0 (dac_frame_q0_s),
|
||||
.dac_data_q0 (dac_data_q0_s),
|
||||
.dac_frame_q1 (dac_frame_q1_s),
|
||||
.dac_data_q1 (dac_data_q1_s),
|
||||
.dac_frame_q2 (dac_frame_q2_s),
|
||||
.dac_data_q2 (dac_data_q2_s),
|
||||
.dac_frame_q3 (dac_frame_q3_s),
|
||||
.dac_data_q3 (dac_data_q3_s),
|
||||
.mmcm_rst (mmcm_rst),
|
||||
.up_clk (up_clk),
|
||||
.up_rstn (up_rstn),
|
||||
.up_drp_sel (up_drp_sel_s),
|
||||
.up_drp_wr (up_drp_wr_s),
|
||||
.up_drp_addr (up_drp_addr_s),
|
||||
.up_drp_wdata (up_drp_wdata_s),
|
||||
.up_drp_rdata (up_drp_rdata_s),
|
||||
.up_drp_ready (up_drp_ready_s),
|
||||
.up_drp_locked (up_drp_locked_s));
|
||||
|
||||
// core
|
||||
|
||||
axi_ad9122_core #(
|
||||
.ID(ID),
|
||||
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
|
||||
.FPGA_FAMILY (FPGA_FAMILY),
|
||||
.SPEED_GRADE (SPEED_GRADE),
|
||||
.DEV_PACKAGE (DEV_PACKAGE),
|
||||
.DAC_DDS_TYPE (DAC_DDS_TYPE),
|
||||
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
|
||||
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
|
||||
.DATAPATH_DISABLE(DAC_DATAPATH_DISABLE))
|
||||
i_core (
|
||||
.dac_div_clk (dac_div_clk),
|
||||
.dac_rst (dac_rst),
|
||||
.dac_frame_i0 (dac_frame_i0_s),
|
||||
.dac_data_i0 (dac_data_i0_s),
|
||||
.dac_frame_i1 (dac_frame_i1_s),
|
||||
.dac_data_i1 (dac_data_i1_s),
|
||||
.dac_frame_i2 (dac_frame_i2_s),
|
||||
.dac_data_i2 (dac_data_i2_s),
|
||||
.dac_frame_i3 (dac_frame_i3_s),
|
||||
.dac_data_i3 (dac_data_i3_s),
|
||||
.dac_frame_q0 (dac_frame_q0_s),
|
||||
.dac_data_q0 (dac_data_q0_s),
|
||||
.dac_frame_q1 (dac_frame_q1_s),
|
||||
.dac_data_q1 (dac_data_q1_s),
|
||||
.dac_frame_q2 (dac_frame_q2_s),
|
||||
.dac_data_q2 (dac_data_q2_s),
|
||||
.dac_frame_q3 (dac_frame_q3_s),
|
||||
.dac_data_q3 (dac_data_q3_s),
|
||||
.dac_status (dac_status_s),
|
||||
.dac_sync_out (dac_sync_out),
|
||||
.dac_sync_in (dac_sync_in),
|
||||
.dac_valid_0 (dac_valid_0),
|
||||
.dac_enable_0 (dac_enable_0),
|
||||
.dac_ddata_0 (dac_ddata_0),
|
||||
.dac_valid_1 (dac_valid_1),
|
||||
.dac_enable_1 (dac_enable_1),
|
||||
.dac_ddata_1 (dac_ddata_1),
|
||||
.dac_dunf (dac_dunf),
|
||||
.mmcm_rst (mmcm_rst),
|
||||
.up_drp_sel (up_drp_sel_s),
|
||||
.up_drp_wr (up_drp_wr_s),
|
||||
.up_drp_addr (up_drp_addr_s),
|
||||
.up_drp_wdata (up_drp_wdata_s),
|
||||
.up_drp_rdata (up_drp_rdata_s),
|
||||
.up_drp_ready (up_drp_ready_s),
|
||||
.up_drp_locked (up_drp_locked_s),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq_s),
|
||||
.up_waddr (up_waddr_s),
|
||||
.up_wdata (up_wdata_s),
|
||||
.up_wack (up_wack_s),
|
||||
.up_rreq (up_rreq_s),
|
||||
.up_raddr (up_raddr_s),
|
||||
.up_rdata (up_rdata_s),
|
||||
.up_rack (up_rack_s));
|
||||
|
||||
// up bus interface
|
||||
|
||||
up_axi i_up_axi (
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_axi_awvalid (s_axi_awvalid),
|
||||
.up_axi_awaddr (s_axi_awaddr),
|
||||
.up_axi_awready (s_axi_awready),
|
||||
.up_axi_wvalid (s_axi_wvalid),
|
||||
.up_axi_wdata (s_axi_wdata),
|
||||
.up_axi_wstrb (s_axi_wstrb),
|
||||
.up_axi_wready (s_axi_wready),
|
||||
.up_axi_bvalid (s_axi_bvalid),
|
||||
.up_axi_bresp (s_axi_bresp),
|
||||
.up_axi_bready (s_axi_bready),
|
||||
.up_axi_arvalid (s_axi_arvalid),
|
||||
.up_axi_araddr (s_axi_araddr),
|
||||
.up_axi_arready (s_axi_arready),
|
||||
.up_axi_rvalid (s_axi_rvalid),
|
||||
.up_axi_rresp (s_axi_rresp),
|
||||
.up_axi_rdata (s_axi_rdata),
|
||||
.up_axi_rready (s_axi_rready),
|
||||
.up_wreq (up_wreq_s),
|
||||
.up_waddr (up_waddr_s),
|
||||
.up_wdata (up_wdata_s),
|
||||
.up_wack (up_wack_s),
|
||||
.up_rreq (up_rreq_s),
|
||||
.up_raddr (up_raddr_s),
|
||||
.up_rdata (up_rdata_s),
|
||||
.up_rack (up_rack_s));
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
@@ -0,0 +1,553 @@
|
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<?xml version="1.0" encoding="UTF-8"?>
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<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
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<!-- -->
|
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<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
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<Option Name="Id" Val="6e93b6c9b8be4b42a8c8f09776be3a90"/>
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<Option Name="CompiledLibDirXSim" Val=""/>
|
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<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
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<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
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<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
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<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
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<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
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<Option Name="BoardPart" Val=""/>
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<Option Name="ActiveSimSet" Val="sim_1"/>
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<Option Name="DefaultLib" Val="xil_defaultlib"/>
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<Option Name="IPRepoPath" Val="$PPRDIR/../../../ghdl/library"/>
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<Option Name="IPCachePermission" Val="write"/>
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<Option Name="WTXSimExportSim" Val="0"/>
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<Option Name="WTModelSimExportSim" Val="0"/>
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<Option Name="WTQuestaExportSim" Val="0"/>
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<Option Name="WTVcsExportSim" Val="0"/>
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<Option Name="WTRivieraExportSim" Val="0"/>
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<Option Name="WTActivehdlExportSim" Val="0"/>
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<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
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<Option Name="XSimRadix" Val="hex"/>
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<Option Name="XSimTimeUnit" Val="ns"/>
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<Option Name="XSimArrayDisplayLimit" Val="1024"/>
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<Option Name="XSimTraceLimit" Val="65536"/>
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||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
<Option Name="SimTypes" Val="bfm"/>
|
||||
<Option Name="SimTypes" Val="tlm"/>
|
||||
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||
</Configuration>
|
||||
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|
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<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
|
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<FileInfo>
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<File Path="$PPRDIR/../xilinx/common/ad_mul.v">
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<FileInfo>
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<FileInfo>
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<Attr Name="UsedIn" Val="simulation"/>
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<File Path="$PPRDIR/../xilinx/common/ad_serdes_clk.v">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="simulation"/>
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<File Path="$PPRDIR/../xilinx/common/ad_serdes_out.v">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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</File>
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<File Path="$PPRDIR/axi_ad9122_channel.v">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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<File Path="$PPRDIR/axi_ad9122_if.v">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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<FileInfo>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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<File Path="$PPRDIR/../common/up_clock_mon.v">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</File>
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<File Path="$PPRDIR/../common/up_dac_channel.v">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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</File>
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<File Path="$PPRDIR/../common/up_dac_common.v">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="simulation"/>
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<File Path="$PPRDIR/../common/up_xfer_status.v">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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||||
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|
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|
||||
<File Path="$PPRDIR/axi_ad9122.v">
|
||||
<FileInfo>
|
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<Attr Name="UsedIn" Val="synthesis"/>
|
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/component.xml">
|
||||
<FileInfo SFType="IPXACT"/>
|
||||
</File>
|
||||
<File Path="$PPRDIR/bd/bd.tcl">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="axi_ad9122"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<File Path="$PPRDIR/../xilinx/common/up_xfer_cntrl_constr.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
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</FileInfo>
|
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</File>
|
||||
<File Path="$PPRDIR/../xilinx/common/ad_rst_constr.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
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</File>
|
||||
<File Path="$PPRDIR/../xilinx/common/up_xfer_status_constr.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
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<Attr Name="UsedIn" Val="implementation"/>
|
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|
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|
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<File Path="$PPRDIR/../xilinx/common/up_clock_mon_constr.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
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|
||||
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|
||||
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|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
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|
||||
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|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
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|
||||
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|
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<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
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<Config>
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<Option Name="DesignMode" Val="RTL"/>
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<Option Name="TopAutoSet" Val="TRUE"/>
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<Option Name="TransportPathDelay" Val="0"/>
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<Option Name="TransportIntDelay" Val="0"/>
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<Option Name="SrcSet" Val="sources_1"/>
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<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
|
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<Filter Type="Utils"/>
|
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<Config>
|
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<Simulator Name="XSim">
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<Option Name="Description" Val="Vivado Simulator"/>
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<Option Name="CompiledLib" Val="0"/>
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<Simulator Name="ModelSim">
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<Option Name="Description" Val="ModelSim Simulator"/>
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<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
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</Simulator>
|
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<Simulator Name="IES">
|
||||
<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Xcelium">
|
||||
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="VCS">
|
||||
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="10">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Vivado 12-1790"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="1"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="Evaluation"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="features"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="should"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="NOT"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="be"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="used"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="in"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="production"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="systems."/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Place 30-73"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="10"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="axi_spi"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val=""/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="11"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1343"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="2"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1306"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="3"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="ERROR"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1276"/>
|
||||
<MsgAttr Name="Severity" Val="CRITICAL WARNING"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="4"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-3656"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="5"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-4623"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="6"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-459"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="7"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Synth 8-3331"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="8"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Designutils 20-3303"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="9"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="HDPYFinalizeIO"/>
|
||||
</MsgRule>
|
||||
<Board/>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
<BootPmcSettings Version="1" Minor="0">
|
||||
<Parameters>
|
||||
<Parameter Name="PMC_CDO.ATTRS.LOADADDR" Value="" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_FB_CLK" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_FREQ" Value="300" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_BUS_WIDTH" Value="x1" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_DATA_MODE" Value="Single" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_FREQ" Value="200" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_SLOT_TYPE" Value="SD 2.0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_FREQ" Value="200" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_SLOT_TYPE" Value="SD 2.0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSPI_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSPI_FREQ" Value="300" Type="string"/>
|
||||
<Parameter Name="BOOT.USB_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SMAP_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SMAP_DATA_WIDTH" Value="32 Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSC_FREQ" Value="33.333" Type="string"/>
|
||||
<Parameter Name="BOOT.SECONDARY.PCIE_ENABLE" Value="0" Type="string"/>
|
||||
</Parameters>
|
||||
</BootPmcSettings>
|
||||
</Project>
|
||||
@@ -0,0 +1,179 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module axi_ad9122_channel #(
|
||||
|
||||
parameter CHANNEL_ID = 32'h0,
|
||||
parameter DAC_DDS_TYPE = 1,
|
||||
parameter DAC_DDS_CORDIC_DW = 16,
|
||||
parameter DAC_DDS_CORDIC_PHASE_DW = 16,
|
||||
parameter DATAPATH_DISABLE = 0) (
|
||||
|
||||
// dac interface
|
||||
|
||||
input dac_div_clk,
|
||||
input dac_rst,
|
||||
output reg dac_enable,
|
||||
output reg [63:0] dac_data,
|
||||
output reg [ 3:0] dac_frame,
|
||||
input [63:0] dma_data,
|
||||
|
||||
// processor interface
|
||||
|
||||
input dac_data_frame,
|
||||
input dac_data_sync,
|
||||
input dac_dds_format,
|
||||
|
||||
// bus interface
|
||||
|
||||
input up_rstn,
|
||||
input up_clk,
|
||||
input up_wreq,
|
||||
input [13:0] up_waddr,
|
||||
input [31:0] up_wdata,
|
||||
output up_wack,
|
||||
input up_rreq,
|
||||
input [13:0] up_raddr,
|
||||
output [31:0] up_rdata,
|
||||
output up_rack);
|
||||
|
||||
// internal signals
|
||||
|
||||
wire [15:0] dac_dds_data_s;
|
||||
wire [15:0] dac_dds_scale_1_s;
|
||||
wire [15:0] dac_dds_init_1_s;
|
||||
wire [15:0] dac_dds_incr_1_s;
|
||||
wire [15:0] dac_dds_scale_2_s;
|
||||
wire [15:0] dac_dds_init_2_s;
|
||||
wire [15:0] dac_dds_incr_2_s;
|
||||
wire [15:0] dac_pat_data_1_s;
|
||||
wire [15:0] dac_pat_data_2_s;
|
||||
wire [ 3:0] dac_data_sel_s;
|
||||
|
||||
// dac data select
|
||||
|
||||
always @(posedge dac_div_clk) begin
|
||||
dac_enable <= (dac_data_sel_s == 4'h2) ? 1'b1 : 1'b0;
|
||||
case (dac_data_sel_s)
|
||||
4'h2: dac_data <= dma_data;
|
||||
4'ha, 4'h1: dac_data <= {dac_pat_data_2_s, dac_pat_data_1_s,
|
||||
dac_pat_data_2_s, dac_pat_data_1_s};
|
||||
default: dac_data <= dac_dds_data_s;
|
||||
endcase
|
||||
if (dac_data_sel_s == 4'h1) begin
|
||||
dac_frame <= 4'b0101;
|
||||
end else begin
|
||||
dac_frame <= {3'd0, dac_data_frame};
|
||||
end
|
||||
end
|
||||
|
||||
// dds
|
||||
|
||||
ad_dds #(
|
||||
.DISABLE (DATAPATH_DISABLE),
|
||||
.DDS_DW (16),
|
||||
.PHASE_DW (16),
|
||||
.DDS_TYPE (DAC_DDS_TYPE),
|
||||
.CORDIC_DW (DAC_DDS_CORDIC_DW),
|
||||
.CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
|
||||
.CLK_RATIO (4))
|
||||
i_dds (
|
||||
.clk (dac_clk),
|
||||
.dac_dds_format (dac_dds_format),
|
||||
.dac_data_sync (dac_data_sync),
|
||||
.dac_valid (1'b1),
|
||||
.tone_1_scale (dac_dds_scale_1_s),
|
||||
.tone_2_scale (dac_dds_scale_2_s),
|
||||
.tone_1_init_offset (dac_dds_init_1_s),
|
||||
.tone_2_init_offset (dac_dds_init_2_s),
|
||||
.tone_1_freq_word (dac_dds_init_2_s),
|
||||
.tone_2_freq_word (dac_dds_incr_2_s),
|
||||
.dac_dds_data (dac_dds_data_s));
|
||||
|
||||
// single channel processor
|
||||
|
||||
up_dac_channel #(
|
||||
.COMMON_ID (6'h11),
|
||||
.CHANNEL_ID(CHANNEL_ID),
|
||||
.DDS_DISABLE (0),
|
||||
.USERPORTS_DISABLE (0),
|
||||
.IQCORRECTION_DISABLE (0))
|
||||
i_up_dac_channel (
|
||||
.dac_clk (dac_div_clk),
|
||||
.dac_rst (dac_rst),
|
||||
.dac_dds_scale_1 (dac_dds_scale_1_s),
|
||||
.dac_dds_init_1 (dac_dds_init_1_s),
|
||||
.dac_dds_incr_1 (dac_dds_incr_1_s),
|
||||
.dac_dds_scale_2 (dac_dds_scale_2_s),
|
||||
.dac_dds_init_2 (dac_dds_init_2_s),
|
||||
.dac_dds_incr_2 (dac_dds_incr_2_s),
|
||||
.dac_pat_data_1 (dac_pat_data_1_s),
|
||||
.dac_pat_data_2 (dac_pat_data_2_s),
|
||||
.dac_data_sel (dac_data_sel_s),
|
||||
.dac_iq_mode (),
|
||||
.dac_iqcor_enb (),
|
||||
.dac_iqcor_coeff_1 (),
|
||||
.dac_iqcor_coeff_2 (),
|
||||
.up_usr_datatype_be (),
|
||||
.up_usr_datatype_signed (),
|
||||
.up_usr_datatype_shift (),
|
||||
.up_usr_datatype_total_bits (),
|
||||
.up_usr_datatype_bits (),
|
||||
.up_usr_interpolation_m (),
|
||||
.up_usr_interpolation_n (),
|
||||
.dac_usr_datatype_be (1'b0),
|
||||
.dac_usr_datatype_signed (1'b1),
|
||||
.dac_usr_datatype_shift (8'd0),
|
||||
.dac_usr_datatype_total_bits (8'd16),
|
||||
.dac_usr_datatype_bits (8'd16),
|
||||
.dac_usr_interpolation_m (16'd1),
|
||||
.dac_usr_interpolation_n (16'd1),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq),
|
||||
.up_waddr (up_waddr),
|
||||
.up_wdata (up_wdata),
|
||||
.up_wack (up_wack),
|
||||
.up_rreq (up_rreq),
|
||||
.up_raddr (up_raddr),
|
||||
.up_rdata (up_rdata),
|
||||
.up_rack (up_rack));
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
@@ -0,0 +1,3 @@
|
||||
|
||||
set_false_path -from [get_registers *up_drp_locked*] -to [get_registers *dac_status_m1*]
|
||||
|
||||
@@ -0,0 +1,3 @@
|
||||
|
||||
set_false_path -from [get_cells -hier -filter {name =~ *up_drp_locked_reg && IS_SEQUENTIAL}] \
|
||||
-to [get_cells -hier -filter {name =~ *dac_status_m1_reg && IS_SEQUENTIAL}]
|
||||
@@ -0,0 +1,271 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module axi_ad9122_core #(
|
||||
|
||||
parameter ID = 0,
|
||||
parameter FPGA_TECHNOLOGY = 0,
|
||||
parameter FPGA_FAMILY = 0,
|
||||
parameter SPEED_GRADE = 0,
|
||||
parameter DEV_PACKAGE = 0,
|
||||
parameter DAC_DDS_TYPE = 1,
|
||||
parameter DAC_DDS_CORDIC_DW = 16,
|
||||
parameter DAC_DDS_CORDIC_PHASE_DW = 16,
|
||||
parameter DATAPATH_DISABLE = 0) (
|
||||
|
||||
// dac interface
|
||||
|
||||
input dac_div_clk,
|
||||
output dac_rst,
|
||||
output dac_frame_i0,
|
||||
output [15:0] dac_data_i0,
|
||||
output dac_frame_i1,
|
||||
output [15:0] dac_data_i1,
|
||||
output dac_frame_i2,
|
||||
output [15:0] dac_data_i2,
|
||||
output dac_frame_i3,
|
||||
output [15:0] dac_data_i3,
|
||||
output dac_frame_q0,
|
||||
output [15:0] dac_data_q0,
|
||||
output dac_frame_q1,
|
||||
output [15:0] dac_data_q1,
|
||||
output dac_frame_q2,
|
||||
output [15:0] dac_data_q2,
|
||||
output dac_frame_q3,
|
||||
output [15:0] dac_data_q3,
|
||||
input dac_status,
|
||||
|
||||
// master/slave
|
||||
|
||||
output dac_sync_out,
|
||||
input dac_sync_in,
|
||||
|
||||
// dma interface
|
||||
|
||||
output dac_valid_0,
|
||||
output dac_enable_0,
|
||||
input [63:0] dac_ddata_0,
|
||||
output dac_valid_1,
|
||||
output dac_enable_1,
|
||||
input [63:0] dac_ddata_1,
|
||||
input dac_dunf,
|
||||
|
||||
// mmcm reset
|
||||
|
||||
output mmcm_rst,
|
||||
|
||||
// drp interface
|
||||
|
||||
output up_drp_sel,
|
||||
output up_drp_wr,
|
||||
output [11:0] up_drp_addr,
|
||||
output [31:0] up_drp_wdata,
|
||||
input [31:0] up_drp_rdata,
|
||||
input up_drp_ready,
|
||||
input up_drp_locked,
|
||||
|
||||
// processor interface
|
||||
|
||||
input up_rstn,
|
||||
input up_clk,
|
||||
input up_wreq,
|
||||
input [13:0] up_waddr,
|
||||
input [31:0] up_wdata,
|
||||
output reg up_wack,
|
||||
input up_rreq,
|
||||
input [13:0] up_raddr,
|
||||
output reg [31:0] up_rdata,
|
||||
output reg up_rack);
|
||||
|
||||
|
||||
// internal registers
|
||||
|
||||
// internal signals
|
||||
|
||||
wire dac_sync_s;
|
||||
wire dac_frame_s;
|
||||
wire dac_datafmt_s;
|
||||
wire [31:0] up_rdata_0_s;
|
||||
wire up_rack_0_s;
|
||||
wire up_wack_0_s;
|
||||
wire [31:0] up_rdata_1_s;
|
||||
wire up_rack_1_s;
|
||||
wire up_wack_1_s;
|
||||
wire [31:0] up_rdata_s;
|
||||
wire up_rack_s;
|
||||
wire up_wack_s;
|
||||
|
||||
// defaults
|
||||
|
||||
assign dac_valid_0 = 1'b1;
|
||||
assign dac_valid_1 = 1'b1;
|
||||
|
||||
// master/slave (clocks must be synchronous)
|
||||
|
||||
assign dac_sync_s = (ID == 0) ? dac_sync_out : dac_sync_in;
|
||||
|
||||
// processor read interface
|
||||
|
||||
always @(negedge up_rstn or posedge up_clk) begin
|
||||
if (up_rstn == 0) begin
|
||||
up_rdata <= 'd0;
|
||||
up_rack <= 'd0;
|
||||
up_wack <= 'd0;
|
||||
end else begin
|
||||
up_rdata <= up_rdata_s | up_rdata_0_s | up_rdata_1_s;
|
||||
up_rack <= up_rack_s | up_rack_0_s | up_rack_1_s;
|
||||
up_wack <= up_wack_s | up_wack_0_s | up_wack_1_s;
|
||||
end
|
||||
end
|
||||
|
||||
// dac channel
|
||||
|
||||
axi_ad9122_channel #(
|
||||
.CHANNEL_ID(0),
|
||||
.DAC_DDS_TYPE (DAC_DDS_TYPE),
|
||||
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
|
||||
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
|
||||
.DATAPATH_DISABLE(DATAPATH_DISABLE))
|
||||
i_channel_0 (
|
||||
.dac_div_clk (dac_div_clk),
|
||||
.dac_rst (dac_rst),
|
||||
.dac_enable (dac_enable_0),
|
||||
.dac_data ({dac_data_i3, dac_data_i2, dac_data_i1, dac_data_i0}),
|
||||
.dac_frame ({dac_frame_i3, dac_frame_i2, dac_frame_i1, dac_frame_i0}),
|
||||
.dma_data (dac_ddata_0),
|
||||
.dac_data_frame (dac_frame_s),
|
||||
.dac_data_sync (dac_sync_s),
|
||||
.dac_dds_format (dac_datafmt_s),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq),
|
||||
.up_waddr (up_waddr),
|
||||
.up_wdata (up_wdata),
|
||||
.up_wack (up_wack_0_s),
|
||||
.up_rreq (up_rreq),
|
||||
.up_raddr (up_raddr),
|
||||
.up_rdata (up_rdata_0_s),
|
||||
.up_rack (up_rack_0_s));
|
||||
|
||||
// dac channel
|
||||
|
||||
axi_ad9122_channel #(
|
||||
.CHANNEL_ID(1),
|
||||
.DAC_DDS_TYPE (DAC_DDS_TYPE),
|
||||
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
|
||||
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
|
||||
.DATAPATH_DISABLE(DATAPATH_DISABLE))
|
||||
i_channel_1 (
|
||||
.dac_div_clk (dac_div_clk),
|
||||
.dac_rst (dac_rst),
|
||||
.dac_enable (dac_enable_1),
|
||||
.dac_data ({dac_data_q3, dac_data_q2, dac_data_q1, dac_data_q0}),
|
||||
.dac_frame ({dac_frame_q3, dac_frame_q2, dac_frame_q1, dac_frame_q0}),
|
||||
.dma_data (dac_ddata_1),
|
||||
.dac_data_frame (dac_frame_s),
|
||||
.dac_data_sync (dac_sync_s),
|
||||
.dac_dds_format (dac_datafmt_s),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq),
|
||||
.up_waddr (up_waddr),
|
||||
.up_wdata (up_wdata),
|
||||
.up_wack (up_wack_1_s),
|
||||
.up_rreq (up_rreq),
|
||||
.up_raddr (up_raddr),
|
||||
.up_rdata (up_rdata_1_s),
|
||||
.up_rack (up_rack_1_s));
|
||||
|
||||
// dac common processor interface
|
||||
|
||||
up_dac_common #(
|
||||
.ID(ID),
|
||||
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
|
||||
.FPGA_FAMILY (FPGA_FAMILY),
|
||||
.SPEED_GRADE (SPEED_GRADE),
|
||||
.DEV_PACKAGE (DEV_PACKAGE),
|
||||
.CONFIG (0),
|
||||
.CLK_EDGE_SEL (0),
|
||||
.COMMON_ID (6'h10),
|
||||
.DRP_DISABLE (6'h00),
|
||||
.USERPORTS_DISABLE (0),
|
||||
.GPIO_DISABLE (0))
|
||||
i_up_dac_common (
|
||||
.mmcm_rst (mmcm_rst),
|
||||
.dac_clk (dac_div_clk),
|
||||
.dac_rst (dac_rst),
|
||||
.dac_sync (dac_sync_out),
|
||||
.dac_frame (dac_frame_s),
|
||||
.dac_clksel (),
|
||||
.dac_par_type (),
|
||||
.dac_par_enb (),
|
||||
.dac_r1_mode (),
|
||||
.dac_datafmt (dac_datafmt_s),
|
||||
.dac_datarate (),
|
||||
.dac_status (dac_status),
|
||||
.dac_status_unf (dac_dunf),
|
||||
.dac_clk_ratio (32'd4),
|
||||
.up_dac_ce (),
|
||||
.up_pps_rcounter(32'd0),
|
||||
.up_pps_status(1'd0),
|
||||
.up_pps_irq_mask(),
|
||||
.up_drp_sel (up_drp_sel),
|
||||
.up_drp_wr (up_drp_wr),
|
||||
.up_drp_addr (up_drp_addr),
|
||||
.up_drp_wdata (up_drp_wdata),
|
||||
.up_drp_rdata (up_drp_rdata),
|
||||
.up_drp_ready (up_drp_ready),
|
||||
.up_drp_locked (up_drp_locked),
|
||||
.up_usr_chanmax (),
|
||||
.dac_usr_chanmax (8'd3),
|
||||
.up_dac_gpio_in (32'd0),
|
||||
.up_dac_gpio_out (),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq),
|
||||
.up_waddr (up_waddr),
|
||||
.up_wdata (up_wdata),
|
||||
.up_wack (up_wack_s),
|
||||
.up_rreq (up_rreq),
|
||||
.up_raddr (up_raddr),
|
||||
.up_rdata (up_rdata_s),
|
||||
.up_rack (up_rack_s));
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
@@ -0,0 +1,116 @@
|
||||
|
||||
package require qsys
|
||||
package require quartus::device
|
||||
|
||||
source ../scripts/adi_env.tcl
|
||||
source ../scripts/adi_ip_intel.tcl
|
||||
|
||||
ad_ip_create axi_ad9122 {AXI AD9122 Interface}
|
||||
set_module_property VALIDATION_CALLBACK info_param_validate
|
||||
|
||||
ad_ip_files axi_ad9122 [list \
|
||||
$ad_hdl_dir/library/common/ad_dds_cordic_pipe.v \
|
||||
$ad_hdl_dir/library/common/ad_dds_sine_cordic.v \
|
||||
$ad_hdl_dir/library/common/ad_dds_sine.v \
|
||||
$ad_hdl_dir/library/common/ad_dds_2.v \
|
||||
$ad_hdl_dir/library/common/ad_dds_1.v \
|
||||
$ad_hdl_dir/library/common/ad_dds.v \
|
||||
$ad_hdl_dir/library/intel/common/ad_mul.v \
|
||||
$ad_hdl_dir/library/common/ad_rst.v \
|
||||
$ad_hdl_dir/library/common/up_axi.v \
|
||||
$ad_hdl_dir/library/common/up_xfer_cntrl.v \
|
||||
$ad_hdl_dir/library/common/up_xfer_status.v \
|
||||
$ad_hdl_dir/library/common/up_clock_mon.v \
|
||||
$ad_hdl_dir/library/common/up_dac_common.v \
|
||||
$ad_hdl_dir/library/common/up_dac_channel.v \
|
||||
axi_ad9122_channel.v \
|
||||
axi_ad9122_core.v \
|
||||
axi_ad9122_if.v \
|
||||
axi_ad9122.v \
|
||||
$ad_hdl_dir/library/intel/common/up_xfer_cntrl_constr.sdc \
|
||||
$ad_hdl_dir/library/intel/common/up_xfer_status_constr.sdc \
|
||||
$ad_hdl_dir/library/intel/common/up_clock_mon_constr.sdc \
|
||||
$ad_hdl_dir/library/intel/common/up_rst_constr.sdc \
|
||||
axi_ad9122_constr.sdc] \
|
||||
axi_ad9122_fileset
|
||||
|
||||
# parameters
|
||||
|
||||
add_parameter ID INTEGER 0
|
||||
set_parameter_property ID DEFAULT_VALUE 0
|
||||
set_parameter_property ID DISPLAY_NAME ID
|
||||
set_parameter_property ID UNITS None
|
||||
set_parameter_property ID HDL_PARAMETER true
|
||||
|
||||
add_parameter FPGA_TECHNOLOGY INTEGER 0
|
||||
set_parameter_property FPGA_TECHNOLOGY DEFAULT_VALUE 0
|
||||
set_parameter_property FPGA_TECHNOLOGY DISPLAY_NAME FPGA_TECHNOLOGY
|
||||
set_parameter_property FPGA_TECHNOLOGY TYPE INTEGER
|
||||
set_parameter_property FPGA_TECHNOLOGY UNITS None
|
||||
set_parameter_property FPGA_TECHNOLOGY HDL_PARAMETER true
|
||||
|
||||
adi_add_auto_fpga_spec_params
|
||||
|
||||
# axi4 slave
|
||||
|
||||
ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn
|
||||
|
||||
# dac device interface
|
||||
|
||||
add_interface device_if conduit end
|
||||
set_interface_property device_if associatedClock none
|
||||
set_interface_property device_if associatedReset none
|
||||
|
||||
add_interface_port device_if dac_clk_in_p dac_clk_in_p Input 1
|
||||
add_interface_port device_if dac_clk_in_n dac_clk_in_n Input 1
|
||||
add_interface_port device_if dac_clk_out_p dac_clk_out_p Output 1
|
||||
add_interface_port device_if dac_clk_out_n dac_clk_out_n Output 1
|
||||
add_interface_port device_if dac_frame_out_p dac_frame_out_p Output 1
|
||||
add_interface_port device_if dac_frame_out_n dac_frame_out_n Output 1
|
||||
add_interface_port device_if dac_data_out_p dac_data_out_p Output 16
|
||||
add_interface_port device_if dac_data_out_n dac_data_out_n Output 16
|
||||
|
||||
add_interface_port device_if dac_sync_out dac_sync_out Output 1
|
||||
add_interface_port device_if dac_sync_in dac_sync_in Input 1
|
||||
|
||||
# dma interface
|
||||
|
||||
ad_interface clock dac_div_clk Output 1
|
||||
|
||||
add_interface dac_ch_0 conduit end
|
||||
add_interface_port dac_ch_0 dac_valid_0 valid Output 1
|
||||
add_interface_port dac_ch_0 dac_enable_0 enable Output 1
|
||||
add_interface_port dac_ch_0 dac_ddata_0 data Input 64
|
||||
set_interface_property dac_ch_0 associatedClock if_dac_div_clk
|
||||
set_interface_property dac_ch_0 associatedReset none
|
||||
|
||||
add_interface dac_ch_1 conduit end
|
||||
add_interface_port dac_ch_1 dac_valid_1 valid Output 1
|
||||
add_interface_port dac_ch_1 dac_enable_1 enable Output 1
|
||||
add_interface_port dac_ch_1 dac_ddata_1 data Input 64
|
||||
set_interface_property dac_ch_1 associatedClock if_dac_div_clk
|
||||
set_interface_property dac_ch_1 associatedReset none
|
||||
|
||||
ad_interface signal dac_dunf input 1 unf
|
||||
|
||||
# SERDES instances and configurations
|
||||
|
||||
add_hdl_instance ad_serdes_clk_core_tx intel_serdes
|
||||
set_instance_parameter_value ad_serdes_clk_core_tx {MODE} {CLK}
|
||||
set_instance_parameter_value ad_serdes_clk_core_tx {DDR_OR_SDR_N} {1}
|
||||
set_instance_parameter_value ad_serdes_clk_core_tx {SERDES_FACTOR} {8}
|
||||
set_instance_parameter_value ad_serdes_clk_core_tx {CLKIN_FREQUENCY} {500.0}
|
||||
|
||||
add_hdl_instance ad_serdes_out_core intel_serdes
|
||||
set_instance_parameter_value ad_serdes_out_core {MODE} {OUT}
|
||||
set_instance_parameter_value ad_serdes_out_core {DDR_OR_SDR_N} {1}
|
||||
set_instance_parameter_value ad_serdes_out_core {SERDES_FACTOR} {8}
|
||||
set_instance_parameter_value ad_serdes_out_core {CLKIN_FREQUENCY} {500.0}
|
||||
|
||||
proc axi_ad9122_fileset { entityName } {
|
||||
|
||||
ad_ip_modfile ad_serdes_out.v ad_serdes_out.v ad_serdes_out_core
|
||||
ad_ip_modfile ad_serdes_clk.v ad_serdes_clk.v ad_serdes_clk_core_tx
|
||||
|
||||
}
|
||||
|
||||
@@ -0,0 +1,233 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// This is the dac physical interface (drives samples from the low speed clock to the
|
||||
// dac clock domain.
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module axi_ad9122_if #(
|
||||
|
||||
parameter FPGA_TECHNOLOGY = 0,
|
||||
parameter SERDES_OR_DDR_N = 1,
|
||||
parameter MMCM_OR_BUFIO_N = 1,
|
||||
parameter MMCM_CLKIN_PERIOD = 1.667,
|
||||
parameter MMCM_VCO_DIV = 6,
|
||||
parameter MMCM_VCO_MUL = 12,
|
||||
parameter MMCM_CLK0_DIV = 2,
|
||||
parameter MMCM_CLK1_DIV = 8,
|
||||
parameter IO_DELAY_GROUP = "dac_if_delay_group") (
|
||||
|
||||
// dac interface
|
||||
|
||||
input dac_clk_in_p,
|
||||
input dac_clk_in_n,
|
||||
output dac_clk_out_p,
|
||||
output dac_clk_out_n,
|
||||
output dac_frame_out_p,
|
||||
output dac_frame_out_n,
|
||||
output [15:0] dac_data_out_p,
|
||||
output [15:0] dac_data_out_n,
|
||||
|
||||
// internal resets and clocks
|
||||
|
||||
input dac_rst,
|
||||
output dac_clk,
|
||||
output dac_div_clk,
|
||||
output reg dac_status,
|
||||
|
||||
// data interface
|
||||
|
||||
input dac_frame_i0,
|
||||
input [15:0] dac_data_i0,
|
||||
input dac_frame_i1,
|
||||
input [15:0] dac_data_i1,
|
||||
input dac_frame_i2,
|
||||
input [15:0] dac_data_i2,
|
||||
input dac_frame_i3,
|
||||
input [15:0] dac_data_i3,
|
||||
|
||||
input dac_frame_q0,
|
||||
input [15:0] dac_data_q0,
|
||||
input dac_frame_q1,
|
||||
input [15:0] dac_data_q1,
|
||||
input dac_frame_q2,
|
||||
input [15:0] dac_data_q2,
|
||||
input dac_frame_q3,
|
||||
input [15:0] dac_data_q3,
|
||||
|
||||
// mmcm reset
|
||||
|
||||
input mmcm_rst,
|
||||
|
||||
// drp interface
|
||||
|
||||
input up_clk,
|
||||
input up_rstn,
|
||||
input up_drp_sel,
|
||||
input up_drp_wr,
|
||||
input [11:0] up_drp_addr,
|
||||
input [31:0] up_drp_wdata,
|
||||
output [31:0] up_drp_rdata,
|
||||
output up_drp_ready,
|
||||
output up_drp_locked);
|
||||
|
||||
|
||||
// internal registers
|
||||
|
||||
reg dac_status_m1 = 'd0;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire dac_out_clk;
|
||||
wire loaden_s;
|
||||
|
||||
// dac status
|
||||
|
||||
always @(posedge dac_div_clk) begin
|
||||
if (dac_rst == 1'b1) begin
|
||||
dac_status_m1 <= 1'd0;
|
||||
dac_status <= 1'd0;
|
||||
end else begin
|
||||
dac_status_m1 <= up_drp_locked;
|
||||
dac_status <= dac_status_m1;
|
||||
end
|
||||
end
|
||||
|
||||
// dac data output serdes(s) & buffers
|
||||
|
||||
ad_serdes_out #(
|
||||
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
|
||||
.DDR_OR_SDR_N (SERDES_OR_DDR_N),
|
||||
.DATA_WIDTH (16))
|
||||
i_serdes_out_data (
|
||||
.rst (dac_rst),
|
||||
.clk (dac_clk),
|
||||
.div_clk (dac_div_clk),
|
||||
.loaden (loaden_s),
|
||||
.data_oe (1'b1),
|
||||
.data_s0 (dac_data_i0),
|
||||
.data_s1 (dac_data_q0),
|
||||
.data_s2 (dac_data_i1),
|
||||
.data_s3 (dac_data_q1),
|
||||
.data_s4 (dac_data_i2),
|
||||
.data_s5 (dac_data_q2),
|
||||
.data_s6 (dac_data_i3),
|
||||
.data_s7 (dac_data_q3),
|
||||
.data_out_se (),
|
||||
.data_out_p (dac_data_out_p),
|
||||
.data_out_n (dac_data_out_n));
|
||||
|
||||
// dac frame output serdes & buffer
|
||||
|
||||
ad_serdes_out #(
|
||||
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
|
||||
.DDR_OR_SDR_N (SERDES_OR_DDR_N),
|
||||
.DATA_WIDTH (1))
|
||||
i_serdes_out_frame (
|
||||
.rst (dac_rst),
|
||||
.clk (dac_clk),
|
||||
.div_clk (dac_div_clk),
|
||||
.loaden (loaden_s),
|
||||
.data_oe (1'b1),
|
||||
.data_s0 (dac_frame_i0),
|
||||
.data_s1 (dac_frame_q0),
|
||||
.data_s2 (dac_frame_i1),
|
||||
.data_s3 (dac_frame_q1),
|
||||
.data_s4 (dac_frame_i2),
|
||||
.data_s5 (dac_frame_q2),
|
||||
.data_s6 (dac_frame_i3),
|
||||
.data_s7 (dac_frame_q3),
|
||||
.data_out_se (),
|
||||
.data_out_p (dac_frame_out_p),
|
||||
.data_out_n (dac_frame_out_n));
|
||||
|
||||
// dac clock output serdes & buffer
|
||||
|
||||
ad_serdes_out #(
|
||||
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
|
||||
.DDR_OR_SDR_N (SERDES_OR_DDR_N),
|
||||
.DATA_WIDTH (1))
|
||||
i_serdes_out_clk (
|
||||
.rst (dac_rst),
|
||||
.clk (dac_clk),
|
||||
.div_clk (dac_div_clk),
|
||||
.loaden (loaden_s),
|
||||
.data_oe (1'b1),
|
||||
.data_s0 (1'b1),
|
||||
.data_s1 (1'b0),
|
||||
.data_s2 (1'b1),
|
||||
.data_s3 (1'b0),
|
||||
.data_s4 (1'b1),
|
||||
.data_s5 (1'b0),
|
||||
.data_s6 (1'b1),
|
||||
.data_s7 (1'b0),
|
||||
.data_out_se (),
|
||||
.data_out_p (dac_clk_out_p),
|
||||
.data_out_n (dac_clk_out_n));
|
||||
|
||||
// dac clock input buffers
|
||||
|
||||
ad_serdes_clk #(
|
||||
.DDR_OR_SDR_N (SERDES_OR_DDR_N),
|
||||
.MMCM_OR_BUFR_N (MMCM_OR_BUFIO_N),
|
||||
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
|
||||
.MMCM_CLKIN_PERIOD (MMCM_CLKIN_PERIOD),
|
||||
.MMCM_VCO_DIV (MMCM_VCO_DIV),
|
||||
.MMCM_VCO_MUL (MMCM_VCO_MUL),
|
||||
.MMCM_CLK0_DIV (MMCM_CLK0_DIV),
|
||||
.MMCM_CLK1_DIV (MMCM_CLK1_DIV))
|
||||
i_serdes_clk (
|
||||
.rst (mmcm_rst),
|
||||
.clk_in_p (dac_clk_in_p),
|
||||
.clk_in_n (dac_clk_in_n),
|
||||
.clk (dac_clk),
|
||||
.div_clk (dac_div_clk),
|
||||
.out_clk (dac_out_clk),
|
||||
.loaden (loaden_s),
|
||||
.phase (),
|
||||
.up_clk (up_clk),
|
||||
.up_rstn (up_rstn),
|
||||
.up_drp_sel (up_drp_sel),
|
||||
.up_drp_wr (up_drp_wr),
|
||||
.up_drp_addr (up_drp_addr),
|
||||
.up_drp_wdata (up_drp_wdata),
|
||||
.up_drp_rdata (up_drp_rdata),
|
||||
.up_drp_ready (up_drp_ready),
|
||||
.up_drp_locked (up_drp_locked));
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
@@ -0,0 +1,54 @@
|
||||
# ip
|
||||
|
||||
source ../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
|
||||
adi_ip_create axi_ad9122
|
||||
adi_ip_files axi_ad9122 [list \
|
||||
"$ad_hdl_dir/library/xilinx/common/ad_mul.v" \
|
||||
"$ad_hdl_dir/library/common/ad_dds_cordic_pipe.v" \
|
||||
"$ad_hdl_dir/library/common/ad_dds_sine_cordic.v" \
|
||||
"$ad_hdl_dir/library/common/ad_dds_sine.v" \
|
||||
"$ad_hdl_dir/library/common/ad_dds_2.v" \
|
||||
"$ad_hdl_dir/library/common/ad_dds_1.v" \
|
||||
"$ad_hdl_dir/library/common/ad_dds.v" \
|
||||
"$ad_hdl_dir/library/common/ad_rst.v" \
|
||||
"$ad_hdl_dir/library/xilinx/common/ad_mmcm_drp.v" \
|
||||
"$ad_hdl_dir/library/xilinx/common/ad_serdes_out.v" \
|
||||
"$ad_hdl_dir/library/xilinx/common/ad_serdes_clk.v" \
|
||||
"$ad_hdl_dir/library/common/up_axi.v" \
|
||||
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
|
||||
"$ad_hdl_dir/library/common/up_xfer_status.v" \
|
||||
"$ad_hdl_dir/library/common/up_clock_mon.v" \
|
||||
"$ad_hdl_dir/library/common/up_dac_common.v" \
|
||||
"$ad_hdl_dir/library/common/up_dac_channel.v" \
|
||||
"$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \
|
||||
"$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \
|
||||
"$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \
|
||||
"$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \
|
||||
"axi_ad9122_channel.v" \
|
||||
"axi_ad9122_core.v" \
|
||||
"axi_ad9122_if.v" \
|
||||
"axi_ad9122_constr.xdc" \
|
||||
"axi_ad9122.v" ]
|
||||
|
||||
adi_ip_properties axi_ad9122
|
||||
|
||||
adi_init_bd_tcl
|
||||
adi_ip_bd axi_ad9122 "bd/bd.tcl"
|
||||
|
||||
set_property driver_value 0 [ipx::get_ports *dac_sync_in* -of_objects [ipx::current_core]]
|
||||
set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
|
||||
|
||||
ipx::infer_bus_interface dac_clk_in_p xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
ipx::infer_bus_interface dac_clk_in_n xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
ipx::infer_bus_interface dac_clk_out_p xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
ipx::infer_bus_interface dac_clk_out_n xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
ipx::infer_bus_interface dac_div_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
|
||||
adi_add_auto_fpga_spec_params
|
||||
|
||||
ipx::create_xgui_files [ipx::current_core]
|
||||
|
||||
ipx::save_core [ipx::current_core]
|
||||
|
||||
@@ -0,0 +1,47 @@
|
||||
# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!
|
||||
proc init {cellpath otherInfo} {
|
||||
set ip [get_bd_cells $cellpath]
|
||||
|
||||
bd::mark_propagate_only $ip " \
|
||||
DEV_PACKAGE \
|
||||
SPEED_GRADE \
|
||||
FPGA_FAMILY \
|
||||
FPGA_TECHNOLOGY"
|
||||
|
||||
adi_auto_assign_device_spec $cellpath
|
||||
}
|
||||
|
||||
# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)
|
||||
proc adi_auto_assign_device_spec {cellpath} {
|
||||
|
||||
set ip [get_bd_cells $cellpath]
|
||||
set ip_param_list [list_property $ip]
|
||||
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
|
||||
|
||||
set parent_dir "../"
|
||||
for {set x 1} {$x<=4} {incr x} {
|
||||
set linkname ${ip_path}${parent_dir}scripts/adi_xilinx_device_info_enc.tcl
|
||||
if { [file exists $linkname] } {
|
||||
source ${ip_path}${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl
|
||||
break
|
||||
}
|
||||
append parent_dir "../"
|
||||
}
|
||||
|
||||
# Find predefindes auto assignable parameters
|
||||
foreach i $auto_set_param_list {
|
||||
if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
|
||||
set val [adi_device_spec $cellpath $i]
|
||||
set_property CONFIG.$i $val $ip
|
||||
}
|
||||
}
|
||||
|
||||
# Find predefindes auto assignable/overwritable parameters
|
||||
foreach i $auto_set_param_list_overwritable {
|
||||
if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
|
||||
set val [adi_device_spec $cellpath $i]
|
||||
set_property CONFIG.$i $val $ip
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,2 @@
|
||||
CLEAN_TARGET += bd
|
||||
CLEAN_TARGET += temporary_case_dependencies.mk
|
||||
@@ -0,0 +1,268 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||
ipgui::add_param $IPINST -name "DAC_DATAPATH_DISABLE" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "DAC_DDS_CORDIC_DW" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "DAC_DDS_CORDIC_PHASE_DW" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "DAC_DDS_TYPE" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "ID" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "IO_DELAY_GROUP" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "MMCM_CLK0_DIV" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "MMCM_CLK1_DIV" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "MMCM_CLKIN_PERIOD" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "MMCM_OR_BUFIO_N" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "MMCM_VCO_DIV" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "MMCM_VCO_MUL" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "SERDES_OR_DDR_N" -parent ${Page_0}
|
||||
#Adding Group
|
||||
set FPGA_info [ipgui::add_group $IPINST -name "FPGA info" -parent ${Page_0}]
|
||||
ipgui::add_param $IPINST -name "FPGA_TECHNOLOGY" -parent ${FPGA_info} -widget comboBox
|
||||
ipgui::add_param $IPINST -name "FPGA_FAMILY" -parent ${FPGA_info} -widget comboBox
|
||||
ipgui::add_param $IPINST -name "SPEED_GRADE" -parent ${FPGA_info} -widget comboBox
|
||||
ipgui::add_param $IPINST -name "DEV_PACKAGE" -parent ${FPGA_info} -widget comboBox
|
||||
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DAC_DATAPATH_DISABLE { PARAM_VALUE.DAC_DATAPATH_DISABLE } {
|
||||
# Procedure called to update DAC_DATAPATH_DISABLE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DAC_DATAPATH_DISABLE { PARAM_VALUE.DAC_DATAPATH_DISABLE } {
|
||||
# Procedure called to validate DAC_DATAPATH_DISABLE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DAC_DDS_CORDIC_DW { PARAM_VALUE.DAC_DDS_CORDIC_DW } {
|
||||
# Procedure called to update DAC_DDS_CORDIC_DW when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DAC_DDS_CORDIC_DW { PARAM_VALUE.DAC_DDS_CORDIC_DW } {
|
||||
# Procedure called to validate DAC_DDS_CORDIC_DW
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW { PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW } {
|
||||
# Procedure called to update DAC_DDS_CORDIC_PHASE_DW when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW { PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW } {
|
||||
# Procedure called to validate DAC_DDS_CORDIC_PHASE_DW
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DAC_DDS_TYPE { PARAM_VALUE.DAC_DDS_TYPE } {
|
||||
# Procedure called to update DAC_DDS_TYPE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DAC_DDS_TYPE { PARAM_VALUE.DAC_DDS_TYPE } {
|
||||
# Procedure called to validate DAC_DDS_TYPE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } {
|
||||
# Procedure called to update DEV_PACKAGE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } {
|
||||
# Procedure called to validate DEV_PACKAGE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } {
|
||||
# Procedure called to update FPGA_FAMILY when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } {
|
||||
# Procedure called to validate FPGA_FAMILY
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } {
|
||||
# Procedure called to update FPGA_TECHNOLOGY when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } {
|
||||
# Procedure called to validate FPGA_TECHNOLOGY
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } {
|
||||
# Procedure called to update ID when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } {
|
||||
# Procedure called to validate ID
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.IO_DELAY_GROUP { PARAM_VALUE.IO_DELAY_GROUP } {
|
||||
# Procedure called to update IO_DELAY_GROUP when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.IO_DELAY_GROUP { PARAM_VALUE.IO_DELAY_GROUP } {
|
||||
# Procedure called to validate IO_DELAY_GROUP
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.MMCM_CLK0_DIV { PARAM_VALUE.MMCM_CLK0_DIV } {
|
||||
# Procedure called to update MMCM_CLK0_DIV when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.MMCM_CLK0_DIV { PARAM_VALUE.MMCM_CLK0_DIV } {
|
||||
# Procedure called to validate MMCM_CLK0_DIV
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.MMCM_CLK1_DIV { PARAM_VALUE.MMCM_CLK1_DIV } {
|
||||
# Procedure called to update MMCM_CLK1_DIV when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.MMCM_CLK1_DIV { PARAM_VALUE.MMCM_CLK1_DIV } {
|
||||
# Procedure called to validate MMCM_CLK1_DIV
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.MMCM_CLKIN_PERIOD { PARAM_VALUE.MMCM_CLKIN_PERIOD } {
|
||||
# Procedure called to update MMCM_CLKIN_PERIOD when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.MMCM_CLKIN_PERIOD { PARAM_VALUE.MMCM_CLKIN_PERIOD } {
|
||||
# Procedure called to validate MMCM_CLKIN_PERIOD
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.MMCM_OR_BUFIO_N { PARAM_VALUE.MMCM_OR_BUFIO_N } {
|
||||
# Procedure called to update MMCM_OR_BUFIO_N when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.MMCM_OR_BUFIO_N { PARAM_VALUE.MMCM_OR_BUFIO_N } {
|
||||
# Procedure called to validate MMCM_OR_BUFIO_N
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.MMCM_VCO_DIV { PARAM_VALUE.MMCM_VCO_DIV } {
|
||||
# Procedure called to update MMCM_VCO_DIV when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.MMCM_VCO_DIV { PARAM_VALUE.MMCM_VCO_DIV } {
|
||||
# Procedure called to validate MMCM_VCO_DIV
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.MMCM_VCO_MUL { PARAM_VALUE.MMCM_VCO_MUL } {
|
||||
# Procedure called to update MMCM_VCO_MUL when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.MMCM_VCO_MUL { PARAM_VALUE.MMCM_VCO_MUL } {
|
||||
# Procedure called to validate MMCM_VCO_MUL
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.SERDES_OR_DDR_N { PARAM_VALUE.SERDES_OR_DDR_N } {
|
||||
# Procedure called to update SERDES_OR_DDR_N when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.SERDES_OR_DDR_N { PARAM_VALUE.SERDES_OR_DDR_N } {
|
||||
# Procedure called to validate SERDES_OR_DDR_N
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } {
|
||||
# Procedure called to update SPEED_GRADE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } {
|
||||
# Procedure called to validate SPEED_GRADE
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.FPGA_TECHNOLOGY { MODELPARAM_VALUE.FPGA_TECHNOLOGY PARAM_VALUE.FPGA_TECHNOLOGY } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.FPGA_TECHNOLOGY}] ${MODELPARAM_VALUE.FPGA_TECHNOLOGY}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.FPGA_FAMILY { MODELPARAM_VALUE.FPGA_FAMILY PARAM_VALUE.FPGA_FAMILY } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.FPGA_FAMILY}] ${MODELPARAM_VALUE.FPGA_FAMILY}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.SPEED_GRADE { MODELPARAM_VALUE.SPEED_GRADE PARAM_VALUE.SPEED_GRADE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.SPEED_GRADE}] ${MODELPARAM_VALUE.SPEED_GRADE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DEV_PACKAGE { MODELPARAM_VALUE.DEV_PACKAGE PARAM_VALUE.DEV_PACKAGE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DEV_PACKAGE}] ${MODELPARAM_VALUE.DEV_PACKAGE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.SERDES_OR_DDR_N { MODELPARAM_VALUE.SERDES_OR_DDR_N PARAM_VALUE.SERDES_OR_DDR_N } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.SERDES_OR_DDR_N}] ${MODELPARAM_VALUE.SERDES_OR_DDR_N}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.MMCM_OR_BUFIO_N { MODELPARAM_VALUE.MMCM_OR_BUFIO_N PARAM_VALUE.MMCM_OR_BUFIO_N } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.MMCM_OR_BUFIO_N}] ${MODELPARAM_VALUE.MMCM_OR_BUFIO_N}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.MMCM_CLKIN_PERIOD { MODELPARAM_VALUE.MMCM_CLKIN_PERIOD PARAM_VALUE.MMCM_CLKIN_PERIOD } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.MMCM_CLKIN_PERIOD}] ${MODELPARAM_VALUE.MMCM_CLKIN_PERIOD}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.MMCM_VCO_DIV { MODELPARAM_VALUE.MMCM_VCO_DIV PARAM_VALUE.MMCM_VCO_DIV } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.MMCM_VCO_DIV}] ${MODELPARAM_VALUE.MMCM_VCO_DIV}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.MMCM_VCO_MUL { MODELPARAM_VALUE.MMCM_VCO_MUL PARAM_VALUE.MMCM_VCO_MUL } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.MMCM_VCO_MUL}] ${MODELPARAM_VALUE.MMCM_VCO_MUL}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.MMCM_CLK0_DIV { MODELPARAM_VALUE.MMCM_CLK0_DIV PARAM_VALUE.MMCM_CLK0_DIV } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.MMCM_CLK0_DIV}] ${MODELPARAM_VALUE.MMCM_CLK0_DIV}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.MMCM_CLK1_DIV { MODELPARAM_VALUE.MMCM_CLK1_DIV PARAM_VALUE.MMCM_CLK1_DIV } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.MMCM_CLK1_DIV}] ${MODELPARAM_VALUE.MMCM_CLK1_DIV}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DAC_DATAPATH_DISABLE { MODELPARAM_VALUE.DAC_DATAPATH_DISABLE PARAM_VALUE.DAC_DATAPATH_DISABLE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DAC_DATAPATH_DISABLE}] ${MODELPARAM_VALUE.DAC_DATAPATH_DISABLE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DAC_DDS_TYPE { MODELPARAM_VALUE.DAC_DDS_TYPE PARAM_VALUE.DAC_DDS_TYPE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DAC_DDS_TYPE}] ${MODELPARAM_VALUE.DAC_DDS_TYPE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DAC_DDS_CORDIC_DW { MODELPARAM_VALUE.DAC_DDS_CORDIC_DW PARAM_VALUE.DAC_DDS_CORDIC_DW } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DAC_DDS_CORDIC_DW}] ${MODELPARAM_VALUE.DAC_DDS_CORDIC_DW}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW { MODELPARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW}] ${MODELPARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.IO_DELAY_GROUP { MODELPARAM_VALUE.IO_DELAY_GROUP PARAM_VALUE.IO_DELAY_GROUP } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.IO_DELAY_GROUP}] ${MODELPARAM_VALUE.IO_DELAY_GROUP}
|
||||
}
|
||||
|
||||
@@ -0,0 +1,43 @@
|
||||
####################################################################################
|
||||
## Copyright 2018(c) Analog Devices, Inc.
|
||||
## Auto-generated, do not modify!
|
||||
####################################################################################
|
||||
|
||||
LIBRARY_NAME := axi_ad9144
|
||||
|
||||
GENERIC_DEPS += axi_ad9144.v
|
||||
|
||||
XILINX_DEPS += axi_ad9144_ip.tcl
|
||||
|
||||
XILINX_LIB_DEPS += jesd204/ad_ip_jesd204_tpl_dac
|
||||
|
||||
INTEL_DEPS += ../common/ad_dds.v
|
||||
INTEL_DEPS += ../common/ad_dds_1.v
|
||||
INTEL_DEPS += ../common/ad_dds_2.v
|
||||
INTEL_DEPS += ../common/ad_dds_cordic_pipe.v
|
||||
INTEL_DEPS += ../common/ad_dds_sine.v
|
||||
INTEL_DEPS += ../common/ad_dds_sine_cordic.v
|
||||
INTEL_DEPS += ../common/ad_iqcor.v
|
||||
INTEL_DEPS += ../common/ad_perfect_shuffle.v
|
||||
INTEL_DEPS += ../common/ad_rst.v
|
||||
INTEL_DEPS += ../common/up_axi.v
|
||||
INTEL_DEPS += ../common/up_clock_mon.v
|
||||
INTEL_DEPS += ../common/up_dac_channel.v
|
||||
INTEL_DEPS += ../common/up_dac_common.v
|
||||
INTEL_DEPS += ../common/up_xfer_cntrl.v
|
||||
INTEL_DEPS += ../common/up_xfer_status.v
|
||||
INTEL_DEPS += ../intel/common/ad_mul.v
|
||||
INTEL_DEPS += ../intel/common/up_clock_mon_constr.sdc
|
||||
INTEL_DEPS += ../intel/common/up_rst_constr.sdc
|
||||
INTEL_DEPS += ../intel/common/up_xfer_cntrl_constr.sdc
|
||||
INTEL_DEPS += ../intel/common/up_xfer_status_constr.sdc
|
||||
INTEL_DEPS += ../jesd204/ad_ip_jesd204_tpl_common/up_tpl_common.v
|
||||
INTEL_DEPS += ../jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac.v
|
||||
INTEL_DEPS += ../jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_channel.v
|
||||
INTEL_DEPS += ../jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_core.v
|
||||
INTEL_DEPS += ../jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_framer.v
|
||||
INTEL_DEPS += ../jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_pn.v
|
||||
INTEL_DEPS += ../jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_regmap.v
|
||||
INTEL_DEPS += axi_ad9144_hw.tcl
|
||||
|
||||
include ../scripts/library.mk
|
||||
@@ -0,0 +1,3 @@
|
||||
version:1
|
||||
6d6f64655f636f756e7465727c42617463684d6f6465:1
|
||||
eof:
|
||||
@@ -0,0 +1,6 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<labtools version="1" minor="0"/>
|
||||
@@ -0,0 +1,185 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module axi_ad9144 #(
|
||||
|
||||
parameter ID = 0,
|
||||
parameter FPGA_TECHNOLOGY = 0,
|
||||
parameter FPGA_FAMILY = 0,
|
||||
parameter SPEED_GRADE = 0,
|
||||
parameter DEV_PACKAGE = 0,
|
||||
parameter QUAD_OR_DUAL_N = 1,
|
||||
parameter DAC_DDS_TYPE = 1,
|
||||
parameter DAC_DDS_CORDIC_DW = 20,
|
||||
parameter DAC_DDS_CORDIC_PHASE_DW = 18,
|
||||
parameter DAC_DATAPATH_DISABLE = 0) (
|
||||
|
||||
// jesd interface
|
||||
// tx_clk is (line-rate/40)
|
||||
|
||||
input tx_clk,
|
||||
output tx_valid,
|
||||
output [(128*QUAD_OR_DUAL_N)+127:0] tx_data,
|
||||
input tx_ready,
|
||||
|
||||
// dma interface
|
||||
|
||||
output dac_clk,
|
||||
output dac_valid_0,
|
||||
output dac_enable_0,
|
||||
input [63:0] dac_ddata_0,
|
||||
output dac_valid_1,
|
||||
output dac_enable_1,
|
||||
input [63:0] dac_ddata_1,
|
||||
output dac_valid_2,
|
||||
output dac_enable_2,
|
||||
input [63:0] dac_ddata_2,
|
||||
output dac_valid_3,
|
||||
output dac_enable_3,
|
||||
input [63:0] dac_ddata_3,
|
||||
input dac_dunf,
|
||||
|
||||
// axi interface
|
||||
|
||||
input s_axi_aclk,
|
||||
input s_axi_aresetn,
|
||||
input s_axi_awvalid,
|
||||
input [ 11:0] s_axi_awaddr,
|
||||
input [ 2:0] s_axi_awprot,
|
||||
output s_axi_awready,
|
||||
input s_axi_wvalid,
|
||||
input [ 31:0] s_axi_wdata,
|
||||
input [ 3:0] s_axi_wstrb,
|
||||
output s_axi_wready,
|
||||
output s_axi_bvalid,
|
||||
output [ 1:0] s_axi_bresp,
|
||||
input s_axi_bready,
|
||||
input s_axi_arvalid,
|
||||
input [ 11:0] s_axi_araddr,
|
||||
input [ 2:0] s_axi_arprot,
|
||||
output s_axi_arready,
|
||||
output s_axi_rvalid,
|
||||
output [ 31:0] s_axi_rdata,
|
||||
output [ 1:0] s_axi_rresp,
|
||||
input s_axi_rready);
|
||||
|
||||
localparam NUM_CHANNELS = QUAD_OR_DUAL_N ? 4 : 2;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire [NUM_CHANNELS-1:0] dac_valid_s;
|
||||
wire [NUM_CHANNELS-1:0] dac_enable_s;
|
||||
wire [NUM_CHANNELS*64-1:0] dac_ddata_s;
|
||||
|
||||
// dual/quad cores
|
||||
|
||||
assign dac_clk = tx_clk;
|
||||
|
||||
assign dac_valid_0 = dac_valid_s[0];
|
||||
assign dac_valid_1 = dac_valid_s[1];
|
||||
assign dac_enable_0 = dac_enable_s[0];
|
||||
assign dac_enable_1 = dac_enable_s[1];
|
||||
assign dac_ddata_s[63:0] = dac_ddata_0;
|
||||
assign dac_ddata_s[127:64] = dac_ddata_1;
|
||||
|
||||
generate
|
||||
if (QUAD_OR_DUAL_N == 1) begin
|
||||
assign dac_valid_2 = dac_valid_s[2];
|
||||
assign dac_valid_3 = dac_valid_s[3];
|
||||
assign dac_enable_2 = dac_enable_s[2];
|
||||
assign dac_enable_3 = dac_enable_s[3];
|
||||
assign dac_ddata_s[191:128] = dac_ddata_2;
|
||||
assign dac_ddata_s[255:192] = dac_ddata_3;
|
||||
end else begin
|
||||
assign dac_valid_2 = 1'b0;
|
||||
assign dac_valid_3 = 1'b0;
|
||||
assign dac_enable_2 = 1'b0;
|
||||
assign dac_enable_3 = 1'b0;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
ad_ip_jesd204_tpl_dac #(
|
||||
.ID (ID),
|
||||
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
|
||||
.FPGA_FAMILY (FPGA_FAMILY),
|
||||
.SPEED_GRADE (SPEED_GRADE),
|
||||
.DEV_PACKAGE (DEV_PACKAGE),
|
||||
.NUM_LANES (NUM_CHANNELS * 2),
|
||||
.NUM_CHANNELS (NUM_CHANNELS),
|
||||
.CONVERTER_RESOLUTION (16),
|
||||
.BITS_PER_SAMPLE (16),
|
||||
.SAMPLES_PER_FRAME (1),
|
||||
.DDS_TYPE (DAC_DDS_TYPE),
|
||||
.DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
|
||||
.DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
|
||||
.DATAPATH_DISABLE (DAC_DATAPATH_DISABLE)
|
||||
) i_dac_jesd204 (
|
||||
.link_clk (tx_clk),
|
||||
|
||||
.link_valid (tx_valid),
|
||||
.link_data (tx_data),
|
||||
.link_ready (tx_ready),
|
||||
|
||||
.enable (dac_enable_s),
|
||||
.dac_valid (dac_valid_s),
|
||||
.dac_ddata (dac_ddata_s),
|
||||
.dac_dunf (dac_dunf),
|
||||
|
||||
.s_axi_aclk (s_axi_aclk),
|
||||
.s_axi_aresetn (s_axi_aresetn),
|
||||
.s_axi_awvalid (s_axi_awvalid),
|
||||
.s_axi_awready (s_axi_awready),
|
||||
.s_axi_awaddr (s_axi_awaddr),
|
||||
.s_axi_awprot (s_axi_awprot),
|
||||
.s_axi_wvalid (s_axi_wvalid),
|
||||
.s_axi_wready (s_axi_wready),
|
||||
.s_axi_wdata (s_axi_wdata),
|
||||
.s_axi_wstrb (s_axi_wstrb),
|
||||
.s_axi_bvalid (s_axi_bvalid),
|
||||
.s_axi_bready (s_axi_bready),
|
||||
.s_axi_bresp (s_axi_bresp),
|
||||
.s_axi_arvalid (s_axi_arvalid),
|
||||
.s_axi_arready (s_axi_arready),
|
||||
.s_axi_araddr (s_axi_araddr),
|
||||
.s_axi_arprot (s_axi_arprot),
|
||||
.s_axi_rvalid (s_axi_rvalid),
|
||||
.s_axi_rready (s_axi_rready),
|
||||
.s_axi_rdata (s_axi_rdata),
|
||||
.s_axi_rresp (s_axi_rresp)
|
||||
);
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,383 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Version="7" Minor="40" Path="/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9144/axi_ad9144.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="4c86d3848a8c4097a59bc333541c1915"/>
|
||||
<Option Name="Part" Val="xc7vx485tffg1157-1"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="BoardPart" Val=""/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../library"/>
|
||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../../ghdl/library"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="DSAVendor" Val="xilinx"/>
|
||||
<Option Name="DSANumComputeUnits" Val="60"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="0"/>
|
||||
<Option Name="WTModelSimExportSim" Val="0"/>
|
||||
<Option Name="WTQuestaExportSim" Val="0"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="0"/>
|
||||
<Option Name="WTRivieraExportSim" Val="0"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
<Option Name="SimTypes" Val="bfm"/>
|
||||
<Option Name="SimTypes" Val="tlm"/>
|
||||
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="31">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/axi_ad9144.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/component.xml">
|
||||
<FileInfo SFType="IPXACT"/>
|
||||
</File>
|
||||
<File Path="$PPRDIR/bd/bd.tcl">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="axi_ad9144"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="IES">
|
||||
<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Xcelium">
|
||||
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="VCS">
|
||||
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="10">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Vivado 12-1790"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="1"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="Evaluation"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="features"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="should"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="NOT"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="be"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="used"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="in"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="production"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="systems."/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Place 30-73"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="10"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="axi_spi"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val=""/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="11"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1343"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="2"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1306"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="3"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="ERROR"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1276"/>
|
||||
<MsgAttr Name="Severity" Val="CRITICAL WARNING"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="4"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-3656"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="5"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-4623"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="6"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-459"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="7"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Synth 8-3331"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="8"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Designutils 20-3303"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="9"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="HDPYFinalizeIO"/>
|
||||
</MsgRule>
|
||||
<Board/>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
<BootPmcSettings Version="1" Minor="0">
|
||||
<Parameters>
|
||||
<Parameter Name="PMC_CDO.ATTRS.LOADADDR" Value="" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_FB_CLK" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_FREQ" Value="300" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_BUS_WIDTH" Value="x1" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_DATA_MODE" Value="Single" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_FREQ" Value="200" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_SLOT_TYPE" Value="SD 2.0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_FREQ" Value="200" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_SLOT_TYPE" Value="SD 2.0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSPI_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSPI_FREQ" Value="300" Type="string"/>
|
||||
<Parameter Name="BOOT.USB_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SMAP_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SMAP_DATA_WIDTH" Value="32 Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSC_FREQ" Value="33.333" Type="string"/>
|
||||
<Parameter Name="BOOT.SECONDARY.PCIE_ENABLE" Value="0" Type="string"/>
|
||||
</Parameters>
|
||||
</BootPmcSettings>
|
||||
</Project>
|
||||
@@ -0,0 +1,44 @@
|
||||
set up_clk [get_clocks -of_objects [get_ports s_axi_aclk]]
|
||||
set ad9144_clk [get_clocks -of_objects [get_ports dac_clk]]
|
||||
|
||||
set_property ASYNC_REG TRUE \
|
||||
[get_cells -hier *toggle_m1_reg*] \
|
||||
[get_cells -hier *toggle_m2_reg*] \
|
||||
[get_cells -hier *state_m1_reg*] \
|
||||
[get_cells -hier *state_m2_reg*]
|
||||
|
||||
set_false_path \
|
||||
-from [get_cells -hier up_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
|
||||
-to [get_cells -hier d_xfer_toggle_m1_reg* -filter {primitive_subgroup == flop}]
|
||||
set_false_path \
|
||||
-from [get_cells -hier d_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
|
||||
-to [get_cells -hier up_xfer_state_m1_reg* -filter {primitive_subgroup == flop}]
|
||||
set_max_delay -datapath_only \
|
||||
-from [get_cells -hier up_xfer_data_reg* -filter {primitive_subgroup == flop}] \
|
||||
-to [get_cells -hier d_data_cntrl_reg* -filter {primitive_subgroup == flop}] \
|
||||
[get_property PERIOD $ad9144_clk]
|
||||
|
||||
set_false_path \
|
||||
-from [get_cells -hier d_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
|
||||
-to [get_cells -hier up_xfer_toggle_m1_reg* -filter {primitive_subgroup == flop}]
|
||||
set_false_path \
|
||||
-from [get_cells -hier up_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
|
||||
-to [get_cells -hier d_xfer_state_m1_reg* -filter {primitive_subgroup == flop}]
|
||||
set_max_delay -datapath_only \
|
||||
-from [get_cells -hier d_xfer_data_reg* -filter {primitive_subgroup == flop}] \
|
||||
-to [get_cells -hier up_data_status_reg* -filter {primitive_subgroup == flop}] \
|
||||
[get_property PERIOD $up_clk]
|
||||
|
||||
set_false_path \
|
||||
-from [get_cells -hier up_count_toggle_reg* -filter {primitive_subgroup == flop}] \
|
||||
-to [get_cells -hier d_count_toggle_m1_reg* -filter {primitive_subgroup == flop}]
|
||||
set_false_path \
|
||||
-from [get_cells -hier d_count_toggle_reg* -filter {primitive_subgroup == flop}] \
|
||||
-to [get_cells -hier up_count_toggle_m1_reg* -filter {primitive_subgroup == flop}]
|
||||
set_max_delay -datapath_only \
|
||||
-from [get_cells -hier d_count_hold_reg* -filter {primitive_subgroup == flop}] \
|
||||
-to [get_cells -hier up_d_count_reg* -filter {primitive_subgroup == flop}] \
|
||||
[get_property PERIOD $up_clk]
|
||||
|
||||
set_false_path \
|
||||
-to [get_pins -hier */PRE -filter {NAME =~ *i_*rst_reg*}]
|
||||
@@ -0,0 +1,104 @@
|
||||
|
||||
|
||||
package require qsys
|
||||
package require quartus::device
|
||||
source ../scripts/adi_env.tcl
|
||||
source ../scripts/adi_ip_intel.tcl
|
||||
|
||||
set_module_property NAME axi_ad9144
|
||||
set_module_property DESCRIPTION "AXI AD9144 Interface"
|
||||
set_module_property VERSION 1.0
|
||||
set_module_property GROUP "Analog Devices"
|
||||
set_module_property DISPLAY_NAME axi_ad9144
|
||||
set_module_property ELABORATION_CALLBACK p_axi_ad9144
|
||||
set_module_property VALIDATION_CALLBACK info_param_validate
|
||||
|
||||
# files
|
||||
|
||||
ad_ip_files axi_ad9144 [list \
|
||||
$ad_hdl_dir/library/intel/common/ad_mul.v \
|
||||
$ad_hdl_dir/library/common/ad_dds_cordic_pipe.v \
|
||||
$ad_hdl_dir/library/common/ad_dds_sine_cordic.v \
|
||||
$ad_hdl_dir/library/common/ad_dds_sine.v \
|
||||
$ad_hdl_dir/library/common/ad_dds_2.v \
|
||||
$ad_hdl_dir/library/common/ad_dds_1.v \
|
||||
$ad_hdl_dir/library/common/ad_dds.v \
|
||||
$ad_hdl_dir/library/common/ad_iqcor.v \
|
||||
$ad_hdl_dir/library/common/ad_perfect_shuffle.v \
|
||||
$ad_hdl_dir/library/common/ad_rst.v \
|
||||
$ad_hdl_dir/library/common/up_axi.v \
|
||||
$ad_hdl_dir/library/common/up_xfer_cntrl.v \
|
||||
$ad_hdl_dir/library/common/up_xfer_status.v \
|
||||
$ad_hdl_dir/library/common/up_clock_mon.v \
|
||||
$ad_hdl_dir/library/common/up_dac_common.v \
|
||||
$ad_hdl_dir/library/common/up_dac_channel.v \
|
||||
\
|
||||
$ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac.v \
|
||||
$ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_channel.v \
|
||||
$ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_core.v \
|
||||
$ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_framer.v \
|
||||
$ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_pn.v \
|
||||
$ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_regmap.v \
|
||||
$ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_common/up_tpl_common.v \
|
||||
\
|
||||
axi_ad9144.v \
|
||||
$ad_hdl_dir/library/intel/common/up_xfer_cntrl_constr.sdc \
|
||||
$ad_hdl_dir/library/intel/common/up_xfer_status_constr.sdc \
|
||||
$ad_hdl_dir/library/intel/common/up_clock_mon_constr.sdc \
|
||||
$ad_hdl_dir/library/intel/common/up_rst_constr.sdc \
|
||||
]
|
||||
|
||||
# parameters
|
||||
|
||||
add_parameter ID INTEGER 0
|
||||
set_parameter_property ID DEFAULT_VALUE 0
|
||||
set_parameter_property ID DISPLAY_NAME ID
|
||||
set_parameter_property ID UNITS None
|
||||
set_parameter_property ID HDL_PARAMETER true
|
||||
|
||||
add_parameter QUAD_OR_DUAL_N INTEGER 0
|
||||
set_parameter_property QUAD_OR_DUAL_N DEFAULT_VALUE 0
|
||||
set_parameter_property QUAD_OR_DUAL_N DISPLAY_NAME QUAD_OR_DUAL_N
|
||||
set_parameter_property QUAD_OR_DUAL_N UNITS None
|
||||
set_parameter_property QUAD_OR_DUAL_N HDL_PARAMETER true
|
||||
|
||||
adi_add_auto_fpga_spec_params
|
||||
|
||||
# axi4 slave
|
||||
|
||||
ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn 12
|
||||
|
||||
# transceiver interface
|
||||
|
||||
ad_interface clock tx_clk input 1
|
||||
|
||||
add_interface if_tx_data avalon_streaming source
|
||||
add_interface_port if_tx_data tx_data data output 128*(QUAD_OR_DUAL_N+1)
|
||||
add_interface_port if_tx_data tx_valid valid output 1
|
||||
add_interface_port if_tx_data tx_ready ready input 1
|
||||
set_interface_property if_tx_data associatedClock if_tx_clk
|
||||
set_interface_property if_tx_data dataBitsPerSymbol 128
|
||||
|
||||
# dma interface
|
||||
|
||||
ad_interface clock dac_clk output 1
|
||||
|
||||
for {set i 0} {$i < 4} {incr i} {
|
||||
add_interface dac_ch_${i} conduit end
|
||||
add_interface_port dac_ch_${i} dac_enable_${i} enable Output 1
|
||||
add_interface_port dac_ch_${i} dac_valid_${i} valid Output 1
|
||||
add_interface_port dac_ch_${i} dac_ddata_${i} data Input 64
|
||||
|
||||
set_interface_property dac_ch_${i} associatedClock if_tx_clk
|
||||
set_interface_property dac_ch_${i} associatedReset none
|
||||
}
|
||||
|
||||
ad_interface signal dac_dunf input 1 unf
|
||||
|
||||
proc p_axi_ad9144 {} {
|
||||
|
||||
if {[get_parameter_value QUAD_OR_DUAL_N] != 1} {
|
||||
set_interface_property dac_ch_2 ENABLED false
|
||||
set_interface_property dac_ch_3 ENABLED false
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,35 @@
|
||||
# ip
|
||||
|
||||
source ../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
|
||||
adi_ip_create axi_ad9144
|
||||
adi_ip_files axi_ad9144 [list \
|
||||
"axi_ad9144.v" ]
|
||||
|
||||
adi_ip_properties axi_ad9144
|
||||
|
||||
adi_init_bd_tcl
|
||||
adi_ip_bd axi_ad9144 "bd/bd.tcl"
|
||||
|
||||
adi_ip_add_core_dependencies { \
|
||||
analog.com:user:ad_ip_jesd204_tpl_dac:1.0 \
|
||||
}
|
||||
|
||||
adi_set_ports_dependency "dac_valid_2" "QUAD_OR_DUAL_N == 1"
|
||||
adi_set_ports_dependency "dac_valid_3" "QUAD_OR_DUAL_N == 1"
|
||||
adi_set_ports_dependency "dac_enable_2" "QUAD_OR_DUAL_N == 1"
|
||||
adi_set_ports_dependency "dac_enable_3" "QUAD_OR_DUAL_N == 1"
|
||||
adi_set_ports_dependency "dac_ddata_2" "QUAD_OR_DUAL_N == 1" "0"
|
||||
adi_set_ports_dependency "dac_ddata_3" "QUAD_OR_DUAL_N == 1" "0"
|
||||
|
||||
set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
|
||||
set_property driver_value 0 [ipx::get_ports *tx_ready* -of_objects [ipx::current_core]]
|
||||
|
||||
ipx::infer_bus_interface tx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
|
||||
adi_add_auto_fpga_spec_params
|
||||
ipx::create_xgui_files [ipx::current_core]
|
||||
|
||||
ipx::save_core [ipx::current_core]
|
||||
|
||||
@@ -0,0 +1,47 @@
|
||||
# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!
|
||||
proc init {cellpath otherInfo} {
|
||||
set ip [get_bd_cells $cellpath]
|
||||
|
||||
bd::mark_propagate_only $ip " \
|
||||
DEV_PACKAGE \
|
||||
SPEED_GRADE \
|
||||
FPGA_FAMILY \
|
||||
FPGA_TECHNOLOGY"
|
||||
|
||||
adi_auto_assign_device_spec $cellpath
|
||||
}
|
||||
|
||||
# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)
|
||||
proc adi_auto_assign_device_spec {cellpath} {
|
||||
|
||||
set ip [get_bd_cells $cellpath]
|
||||
set ip_param_list [list_property $ip]
|
||||
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
|
||||
|
||||
set parent_dir "../"
|
||||
for {set x 1} {$x<=4} {incr x} {
|
||||
set linkname ${ip_path}${parent_dir}scripts/adi_xilinx_device_info_enc.tcl
|
||||
if { [file exists $linkname] } {
|
||||
source ${ip_path}${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl
|
||||
break
|
||||
}
|
||||
append parent_dir "../"
|
||||
}
|
||||
|
||||
# Find predefindes auto assignable parameters
|
||||
foreach i $auto_set_param_list {
|
||||
if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
|
||||
set val [adi_device_spec $cellpath $i]
|
||||
set_property CONFIG.$i $val $ip
|
||||
}
|
||||
}
|
||||
|
||||
# Find predefindes auto assignable/overwritable parameters
|
||||
foreach i $auto_set_param_list_overwritable {
|
||||
if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
|
||||
set val [adi_device_spec $cellpath $i]
|
||||
set_property CONFIG.$i $val $ip
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,2 @@
|
||||
CLEAN_TARGET += bd
|
||||
CLEAN_TARGET += temporary_case_dependencies.mk
|
||||
@@ -0,0 +1,163 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||
ipgui::add_param $IPINST -name "DAC_DATAPATH_DISABLE" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "DAC_DDS_CORDIC_DW" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "DAC_DDS_CORDIC_PHASE_DW" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "DAC_DDS_TYPE" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "ID" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "QUAD_OR_DUAL_N" -parent ${Page_0}
|
||||
#Adding Group
|
||||
set FPGA_info [ipgui::add_group $IPINST -name "FPGA info" -parent ${Page_0}]
|
||||
ipgui::add_param $IPINST -name "FPGA_TECHNOLOGY" -parent ${FPGA_info} -widget comboBox
|
||||
ipgui::add_param $IPINST -name "FPGA_FAMILY" -parent ${FPGA_info} -widget comboBox
|
||||
ipgui::add_param $IPINST -name "SPEED_GRADE" -parent ${FPGA_info} -widget comboBox
|
||||
ipgui::add_param $IPINST -name "DEV_PACKAGE" -parent ${FPGA_info} -widget comboBox
|
||||
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DAC_DATAPATH_DISABLE { PARAM_VALUE.DAC_DATAPATH_DISABLE } {
|
||||
# Procedure called to update DAC_DATAPATH_DISABLE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DAC_DATAPATH_DISABLE { PARAM_VALUE.DAC_DATAPATH_DISABLE } {
|
||||
# Procedure called to validate DAC_DATAPATH_DISABLE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DAC_DDS_CORDIC_DW { PARAM_VALUE.DAC_DDS_CORDIC_DW } {
|
||||
# Procedure called to update DAC_DDS_CORDIC_DW when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DAC_DDS_CORDIC_DW { PARAM_VALUE.DAC_DDS_CORDIC_DW } {
|
||||
# Procedure called to validate DAC_DDS_CORDIC_DW
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW { PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW } {
|
||||
# Procedure called to update DAC_DDS_CORDIC_PHASE_DW when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW { PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW } {
|
||||
# Procedure called to validate DAC_DDS_CORDIC_PHASE_DW
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DAC_DDS_TYPE { PARAM_VALUE.DAC_DDS_TYPE } {
|
||||
# Procedure called to update DAC_DDS_TYPE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DAC_DDS_TYPE { PARAM_VALUE.DAC_DDS_TYPE } {
|
||||
# Procedure called to validate DAC_DDS_TYPE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } {
|
||||
# Procedure called to update DEV_PACKAGE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } {
|
||||
# Procedure called to validate DEV_PACKAGE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } {
|
||||
# Procedure called to update FPGA_FAMILY when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } {
|
||||
# Procedure called to validate FPGA_FAMILY
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } {
|
||||
# Procedure called to update FPGA_TECHNOLOGY when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } {
|
||||
# Procedure called to validate FPGA_TECHNOLOGY
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } {
|
||||
# Procedure called to update ID when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } {
|
||||
# Procedure called to validate ID
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.QUAD_OR_DUAL_N { PARAM_VALUE.QUAD_OR_DUAL_N } {
|
||||
# Procedure called to update QUAD_OR_DUAL_N when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.QUAD_OR_DUAL_N { PARAM_VALUE.QUAD_OR_DUAL_N } {
|
||||
# Procedure called to validate QUAD_OR_DUAL_N
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } {
|
||||
# Procedure called to update SPEED_GRADE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } {
|
||||
# Procedure called to validate SPEED_GRADE
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.FPGA_TECHNOLOGY { MODELPARAM_VALUE.FPGA_TECHNOLOGY PARAM_VALUE.FPGA_TECHNOLOGY } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.FPGA_TECHNOLOGY}] ${MODELPARAM_VALUE.FPGA_TECHNOLOGY}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.FPGA_FAMILY { MODELPARAM_VALUE.FPGA_FAMILY PARAM_VALUE.FPGA_FAMILY } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.FPGA_FAMILY}] ${MODELPARAM_VALUE.FPGA_FAMILY}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.SPEED_GRADE { MODELPARAM_VALUE.SPEED_GRADE PARAM_VALUE.SPEED_GRADE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.SPEED_GRADE}] ${MODELPARAM_VALUE.SPEED_GRADE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DEV_PACKAGE { MODELPARAM_VALUE.DEV_PACKAGE PARAM_VALUE.DEV_PACKAGE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DEV_PACKAGE}] ${MODELPARAM_VALUE.DEV_PACKAGE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.QUAD_OR_DUAL_N { MODELPARAM_VALUE.QUAD_OR_DUAL_N PARAM_VALUE.QUAD_OR_DUAL_N } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.QUAD_OR_DUAL_N}] ${MODELPARAM_VALUE.QUAD_OR_DUAL_N}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DAC_DDS_TYPE { MODELPARAM_VALUE.DAC_DDS_TYPE PARAM_VALUE.DAC_DDS_TYPE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DAC_DDS_TYPE}] ${MODELPARAM_VALUE.DAC_DDS_TYPE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DAC_DDS_CORDIC_DW { MODELPARAM_VALUE.DAC_DDS_CORDIC_DW PARAM_VALUE.DAC_DDS_CORDIC_DW } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DAC_DDS_CORDIC_DW}] ${MODELPARAM_VALUE.DAC_DDS_CORDIC_DW}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW { MODELPARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW}] ${MODELPARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DAC_DATAPATH_DISABLE { MODELPARAM_VALUE.DAC_DATAPATH_DISABLE PARAM_VALUE.DAC_DATAPATH_DISABLE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DAC_DATAPATH_DISABLE}] ${MODELPARAM_VALUE.DAC_DATAPATH_DISABLE}
|
||||
}
|
||||
|
||||
@@ -0,0 +1,43 @@
|
||||
####################################################################################
|
||||
## Copyright 2018(c) Analog Devices, Inc.
|
||||
## Auto-generated, do not modify!
|
||||
####################################################################################
|
||||
|
||||
LIBRARY_NAME := axi_ad9152
|
||||
|
||||
GENERIC_DEPS += axi_ad9152.v
|
||||
|
||||
XILINX_DEPS += axi_ad9152_ip.tcl
|
||||
|
||||
XILINX_LIB_DEPS += jesd204/ad_ip_jesd204_tpl_dac
|
||||
|
||||
INTEL_DEPS += ../common/ad_dds.v
|
||||
INTEL_DEPS += ../common/ad_dds_1.v
|
||||
INTEL_DEPS += ../common/ad_dds_2.v
|
||||
INTEL_DEPS += ../common/ad_dds_cordic_pipe.v
|
||||
INTEL_DEPS += ../common/ad_dds_sine.v
|
||||
INTEL_DEPS += ../common/ad_dds_sine_cordic.v
|
||||
INTEL_DEPS += ../common/ad_iqcor.v
|
||||
INTEL_DEPS += ../common/ad_perfect_shuffle.v
|
||||
INTEL_DEPS += ../common/ad_rst.v
|
||||
INTEL_DEPS += ../common/up_axi.v
|
||||
INTEL_DEPS += ../common/up_clock_mon.v
|
||||
INTEL_DEPS += ../common/up_dac_channel.v
|
||||
INTEL_DEPS += ../common/up_dac_common.v
|
||||
INTEL_DEPS += ../common/up_xfer_cntrl.v
|
||||
INTEL_DEPS += ../common/up_xfer_status.v
|
||||
INTEL_DEPS += ../intel/common/ad_mul.v
|
||||
INTEL_DEPS += ../intel/common/up_clock_mon_constr.sdc
|
||||
INTEL_DEPS += ../intel/common/up_rst_constr.sdc
|
||||
INTEL_DEPS += ../intel/common/up_xfer_cntrl_constr.sdc
|
||||
INTEL_DEPS += ../intel/common/up_xfer_status_constr.sdc
|
||||
INTEL_DEPS += ../jesd204/ad_ip_jesd204_tpl_common/up_tpl_common.v
|
||||
INTEL_DEPS += ../jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac.v
|
||||
INTEL_DEPS += ../jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_channel.v
|
||||
INTEL_DEPS += ../jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_core.v
|
||||
INTEL_DEPS += ../jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_framer.v
|
||||
INTEL_DEPS += ../jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_pn.v
|
||||
INTEL_DEPS += ../jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_regmap.v
|
||||
INTEL_DEPS += axi_ad9152_hw.tcl
|
||||
|
||||
include ../scripts/library.mk
|
||||
@@ -0,0 +1,3 @@
|
||||
version:1
|
||||
6d6f64655f636f756e7465727c42617463684d6f6465:1
|
||||
eof:
|
||||
@@ -0,0 +1,6 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<labtools version="1" minor="0"/>
|
||||
@@ -0,0 +1,145 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module axi_ad9152 #(
|
||||
|
||||
parameter ID = 0,
|
||||
parameter FPGA_TECHNOLOGY = 0,
|
||||
parameter FPGA_FAMILY = 0,
|
||||
parameter SPEED_GRADE = 0,
|
||||
parameter DEV_PACKAGE = 0,
|
||||
parameter DAC_DDS_TYPE = 1,
|
||||
parameter DAC_DDS_CORDIC_DW = 16,
|
||||
parameter DAC_DDS_CORDIC_PHASE_DW = 16,
|
||||
parameter DAC_DATAPATH_DISABLE = 0) (
|
||||
|
||||
// jesd interface
|
||||
// tx_clk is (line-rate/40)
|
||||
|
||||
input tx_clk,
|
||||
output [127:0] tx_data,
|
||||
output tx_valid,
|
||||
input tx_ready,
|
||||
|
||||
// dma interface
|
||||
|
||||
output dac_clk,
|
||||
output dac_valid_0,
|
||||
output dac_enable_0,
|
||||
input [ 63:0] dac_ddata_0,
|
||||
output dac_valid_1,
|
||||
output dac_enable_1,
|
||||
input [ 63:0] dac_ddata_1,
|
||||
input dac_dunf,
|
||||
|
||||
// axi interface
|
||||
|
||||
input s_axi_aclk,
|
||||
input s_axi_aresetn,
|
||||
input s_axi_awvalid,
|
||||
input [ 11:0] s_axi_awaddr,
|
||||
input [ 2:0] s_axi_awprot,
|
||||
output s_axi_awready,
|
||||
input s_axi_wvalid,
|
||||
input [ 31:0] s_axi_wdata,
|
||||
input [ 3:0] s_axi_wstrb,
|
||||
output s_axi_wready,
|
||||
output s_axi_bvalid,
|
||||
output [ 1:0] s_axi_bresp,
|
||||
input s_axi_bready,
|
||||
input s_axi_arvalid,
|
||||
input [ 11:0] s_axi_araddr,
|
||||
input [ 2:0] s_axi_arprot,
|
||||
output s_axi_arready,
|
||||
output s_axi_rvalid,
|
||||
output [ 31:0] s_axi_rdata,
|
||||
output [ 1:0] s_axi_rresp,
|
||||
input s_axi_rready);
|
||||
|
||||
assign dac_clk = tx_clk;
|
||||
|
||||
ad_ip_jesd204_tpl_dac #(
|
||||
.ID(ID),
|
||||
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
|
||||
.FPGA_FAMILY (FPGA_FAMILY),
|
||||
.SPEED_GRADE (SPEED_GRADE),
|
||||
.DEV_PACKAGE (DEV_PACKAGE),
|
||||
.NUM_LANES(4),
|
||||
.NUM_CHANNELS(2),
|
||||
.CONVERTER_RESOLUTION (16),
|
||||
.BITS_PER_SAMPLE (16),
|
||||
.SAMPLES_PER_FRAME (1),
|
||||
.DDS_TYPE (DAC_DDS_TYPE),
|
||||
.DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
|
||||
.DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
|
||||
.DATAPATH_DISABLE(DAC_DATAPATH_DISABLE)
|
||||
) i_dac_jesd204 (
|
||||
.link_clk (tx_clk),
|
||||
|
||||
.link_valid (tx_valid),
|
||||
.link_data (tx_data),
|
||||
.link_ready (tx_ready),
|
||||
|
||||
.enable ({dac_enable_1,dac_enable_0}),
|
||||
.dac_valid ({dac_valid_1,dac_valid_0}),
|
||||
.dac_ddata ({dac_ddata_1,dac_ddata_0}),
|
||||
.dac_dunf (dac_dunf),
|
||||
|
||||
.s_axi_aclk (s_axi_aclk),
|
||||
.s_axi_aresetn (s_axi_aresetn),
|
||||
.s_axi_awvalid (s_axi_awvalid),
|
||||
.s_axi_awready (s_axi_awready),
|
||||
.s_axi_awaddr (s_axi_awaddr),
|
||||
.s_axi_awprot (s_axi_awprot),
|
||||
.s_axi_wvalid (s_axi_wvalid),
|
||||
.s_axi_wready (s_axi_wready),
|
||||
.s_axi_wdata (s_axi_wdata),
|
||||
.s_axi_wstrb (s_axi_wstrb),
|
||||
.s_axi_bvalid (s_axi_bvalid),
|
||||
.s_axi_bready (s_axi_bready),
|
||||
.s_axi_bresp (s_axi_bresp),
|
||||
.s_axi_arvalid (s_axi_arvalid),
|
||||
.s_axi_arready (s_axi_arready),
|
||||
.s_axi_araddr (s_axi_araddr),
|
||||
.s_axi_arprot (s_axi_arprot),
|
||||
.s_axi_rvalid (s_axi_rvalid),
|
||||
.s_axi_rready (s_axi_rready),
|
||||
.s_axi_rdata (s_axi_rdata),
|
||||
.s_axi_rresp (s_axi_rresp)
|
||||
);
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,383 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Version="7" Minor="40" Path="/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9152/axi_ad9152.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="f0ceb3f4beb64386bdb0061ad1dc7839"/>
|
||||
<Option Name="Part" Val="xc7vx485tffg1157-1"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="BoardPart" Val=""/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../library"/>
|
||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../../ghdl/library"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="DSAVendor" Val="xilinx"/>
|
||||
<Option Name="DSANumComputeUnits" Val="60"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="0"/>
|
||||
<Option Name="WTModelSimExportSim" Val="0"/>
|
||||
<Option Name="WTQuestaExportSim" Val="0"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="0"/>
|
||||
<Option Name="WTRivieraExportSim" Val="0"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
<Option Name="SimTypes" Val="bfm"/>
|
||||
<Option Name="SimTypes" Val="tlm"/>
|
||||
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="31">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/axi_ad9152.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/component.xml">
|
||||
<FileInfo SFType="IPXACT"/>
|
||||
</File>
|
||||
<File Path="$PPRDIR/bd/bd.tcl">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="axi_ad9152"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="IES">
|
||||
<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Xcelium">
|
||||
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="VCS">
|
||||
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="10">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Vivado 12-1790"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="1"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="Evaluation"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="features"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="should"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="NOT"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="be"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="used"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="in"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="production"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="systems."/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Place 30-73"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="10"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="axi_spi"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val=""/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="11"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1343"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="2"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1306"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="3"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="ERROR"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1276"/>
|
||||
<MsgAttr Name="Severity" Val="CRITICAL WARNING"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="4"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-3656"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="5"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-4623"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="6"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-459"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="7"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Synth 8-3331"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="8"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Designutils 20-3303"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="9"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="HDPYFinalizeIO"/>
|
||||
</MsgRule>
|
||||
<Board/>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
<BootPmcSettings Version="1" Minor="0">
|
||||
<Parameters>
|
||||
<Parameter Name="PMC_CDO.ATTRS.LOADADDR" Value="" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_FB_CLK" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_FREQ" Value="300" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_BUS_WIDTH" Value="x1" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_DATA_MODE" Value="Single" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_FREQ" Value="200" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_SLOT_TYPE" Value="SD 2.0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_FREQ" Value="200" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_SLOT_TYPE" Value="SD 2.0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSPI_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSPI_FREQ" Value="300" Type="string"/>
|
||||
<Parameter Name="BOOT.USB_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SMAP_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SMAP_DATA_WIDTH" Value="32 Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSC_FREQ" Value="33.333" Type="string"/>
|
||||
<Parameter Name="BOOT.SECONDARY.PCIE_ENABLE" Value="0" Type="string"/>
|
||||
</Parameters>
|
||||
</BootPmcSettings>
|
||||
</Project>
|
||||
@@ -0,0 +1,44 @@
|
||||
set up_clk [get_clocks -of_objects [get_ports s_axi_aclk]]
|
||||
set ad9152_clk [get_clocks -of_objects [get_ports tx_clk]]
|
||||
|
||||
set_property ASYNC_REG TRUE \
|
||||
[get_cells -hier *toggle_m1_reg*] \
|
||||
[get_cells -hier *toggle_m2_reg*] \
|
||||
[get_cells -hier *state_m1_reg*] \
|
||||
[get_cells -hier *state_m2_reg*]
|
||||
|
||||
set_false_path \
|
||||
-from [get_cells -hier up_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
|
||||
-to [get_cells -hier d_xfer_toggle_m1_reg* -filter {primitive_subgroup == flop}]
|
||||
set_false_path \
|
||||
-from [get_cells -hier d_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
|
||||
-to [get_cells -hier up_xfer_state_m1_reg* -filter {primitive_subgroup == flop}]
|
||||
set_max_delay -datapath_only \
|
||||
-from [get_cells -hier up_xfer_data_reg* -filter {primitive_subgroup == flop}] \
|
||||
-to [get_cells -hier d_data_cntrl_reg* -filter {primitive_subgroup == flop}] \
|
||||
[get_property PERIOD $ad9152_clk]
|
||||
|
||||
set_false_path \
|
||||
-from [get_cells -hier d_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
|
||||
-to [get_cells -hier up_xfer_toggle_m1_reg* -filter {primitive_subgroup == flop}]
|
||||
set_false_path \
|
||||
-from [get_cells -hier up_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
|
||||
-to [get_cells -hier d_xfer_state_m1_reg* -filter {primitive_subgroup == flop}]
|
||||
set_max_delay -datapath_only \
|
||||
-from [get_cells -hier d_xfer_data_reg* -filter {primitive_subgroup == flop}] \
|
||||
-to [get_cells -hier up_data_status_reg* -filter {primitive_subgroup == flop}] \
|
||||
[get_property PERIOD $up_clk]
|
||||
|
||||
set_false_path \
|
||||
-from [get_cells -hier up_count_toggle_reg* -filter {primitive_subgroup == flop}] \
|
||||
-to [get_cells -hier d_count_toggle_m1_reg* -filter {primitive_subgroup == flop}]
|
||||
set_false_path \
|
||||
-from [get_cells -hier d_count_toggle_reg* -filter {primitive_subgroup == flop}] \
|
||||
-to [get_cells -hier up_count_toggle_m1_reg* -filter {primitive_subgroup == flop}]
|
||||
set_max_delay -datapath_only \
|
||||
-from [get_cells -hier d_count_hold_reg* -filter {primitive_subgroup == flop}] \
|
||||
-to [get_cells -hier up_d_count_reg* -filter {primitive_subgroup == flop}] \
|
||||
[get_property PERIOD $up_clk]
|
||||
|
||||
set_false_path \
|
||||
-to [get_pins -hier */PRE -filter {NAME =~ *i_*rst_reg*}]
|
||||
@@ -0,0 +1,97 @@
|
||||
|
||||
|
||||
package require qsys
|
||||
package require quartus::device
|
||||
|
||||
source ../scripts/adi_env.tcl
|
||||
source ../scripts/adi_ip_intel.tcl
|
||||
|
||||
set_module_property NAME axi_ad9152
|
||||
set_module_property DESCRIPTION "AXI AD9152 Interface"
|
||||
set_module_property VERSION 1.0
|
||||
set_module_property GROUP "Analog Devices"
|
||||
set_module_property DISPLAY_NAME axi_ad9152
|
||||
set_module_property VALIDATION_CALLBACK info_param_validate
|
||||
|
||||
# files
|
||||
|
||||
ad_ip_files axi_ad9152 [list \
|
||||
$ad_hdl_dir/library/intel/common/ad_mul.v \
|
||||
$ad_hdl_dir/library/common/ad_dds_sine.v \
|
||||
$ad_hdl_dir/library/common/ad_dds_cordic_pipe.v \
|
||||
$ad_hdl_dir/library/common/ad_dds_sine_cordic.v \
|
||||
$ad_hdl_dir/library/common/ad_dds_2.v \
|
||||
$ad_hdl_dir/library/common/ad_dds_1.v \
|
||||
$ad_hdl_dir/library/common/ad_dds.v \
|
||||
$ad_hdl_dir/library/common/ad_iqcor.v \
|
||||
$ad_hdl_dir/library/common/ad_perfect_shuffle.v \
|
||||
$ad_hdl_dir/library/common/ad_rst.v \
|
||||
$ad_hdl_dir/library/common/up_axi.v \
|
||||
$ad_hdl_dir/library/common/up_xfer_cntrl.v \
|
||||
$ad_hdl_dir/library/common/up_xfer_status.v \
|
||||
$ad_hdl_dir/library/common/up_clock_mon.v \
|
||||
$ad_hdl_dir/library/common/up_dac_common.v \
|
||||
$ad_hdl_dir/library/common/up_dac_channel.v \
|
||||
\
|
||||
$ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac.v \
|
||||
$ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_channel.v \
|
||||
$ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_core.v \
|
||||
$ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_framer.v \
|
||||
$ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_pn.v \
|
||||
$ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_regmap.v \
|
||||
$ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_common/up_tpl_common.v \
|
||||
\
|
||||
axi_ad9152.v \
|
||||
$ad_hdl_dir/library/intel/common/up_xfer_cntrl_constr.sdc \
|
||||
$ad_hdl_dir/library/intel/common/up_xfer_status_constr.sdc \
|
||||
$ad_hdl_dir/library/intel/common/up_clock_mon_constr.sdc \
|
||||
$ad_hdl_dir/library/intel/common/up_rst_constr.sdc \
|
||||
]
|
||||
|
||||
# parameters
|
||||
|
||||
add_parameter ID INTEGER 0
|
||||
set_parameter_property ID DEFAULT_VALUE 0
|
||||
set_parameter_property ID DISPLAY_NAME ID
|
||||
set_parameter_property ID UNITS None
|
||||
set_parameter_property ID HDL_PARAMETER true
|
||||
|
||||
adi_add_auto_fpga_spec_params
|
||||
|
||||
# axi4 slave
|
||||
|
||||
ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn 12
|
||||
|
||||
# transceiver interface
|
||||
|
||||
ad_interface clock tx_clk input 1
|
||||
|
||||
add_interface if_tx_data avalon_streaming source
|
||||
add_interface_port if_tx_data tx_data data output 128
|
||||
add_interface_port if_tx_data tx_valid valid output 1
|
||||
add_interface_port if_tx_data tx_ready ready input 1
|
||||
set_interface_property if_tx_data associatedClock if_tx_clk
|
||||
set_interface_property if_tx_data dataBitsPerSymbol 128
|
||||
|
||||
# dma interface
|
||||
|
||||
ad_interface clock dac_clk output 1
|
||||
|
||||
add_interface dac_ch_0 conduit end
|
||||
add_interface_port dac_ch_0 dac_enable_0 enable Output 1
|
||||
add_interface_port dac_ch_0 dac_valid_0 valid Output 1
|
||||
add_interface_port dac_ch_0 dac_ddata_0 data Input 64
|
||||
|
||||
set_interface_property dac_ch_0 associatedClock if_tx_clk
|
||||
set_interface_property dac_ch_0 associatedReset none
|
||||
|
||||
add_interface dac_ch_1 conduit end
|
||||
add_interface_port dac_ch_1 dac_enable_1 enable Output 1
|
||||
add_interface_port dac_ch_1 dac_valid_1 valid Output 1
|
||||
add_interface_port dac_ch_1 dac_ddata_1 data Input 64
|
||||
|
||||
set_interface_property dac_ch_1 associatedClock if_tx_clk
|
||||
set_interface_property dac_ch_1 associatedReset none
|
||||
|
||||
ad_interface signal dac_dunf input 1 unf
|
||||
|
||||
@@ -0,0 +1,28 @@
|
||||
# ip
|
||||
|
||||
source ../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
|
||||
adi_ip_create axi_ad9152
|
||||
adi_ip_files axi_ad9152 [list \
|
||||
"axi_ad9152.v" ]
|
||||
|
||||
adi_ip_properties axi_ad9152
|
||||
|
||||
adi_init_bd_tcl
|
||||
adi_ip_bd axi_ad9152 "bd/bd.tcl"
|
||||
|
||||
adi_ip_add_core_dependencies { \
|
||||
analog.com:user:ad_ip_jesd204_tpl_dac:1.0 \
|
||||
}
|
||||
|
||||
set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
|
||||
set_property driver_value 0 [ipx::get_ports *tx_ready* -of_objects [ipx::current_core]]
|
||||
|
||||
ipx::infer_bus_interface tx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
ipx::infer_bus_interface dac_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
|
||||
adi_add_auto_fpga_spec_params
|
||||
ipx::create_xgui_files [ipx::current_core]
|
||||
|
||||
ipx::save_core [ipx::current_core]
|
||||
@@ -0,0 +1,47 @@
|
||||
# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!
|
||||
proc init {cellpath otherInfo} {
|
||||
set ip [get_bd_cells $cellpath]
|
||||
|
||||
bd::mark_propagate_only $ip " \
|
||||
DEV_PACKAGE \
|
||||
SPEED_GRADE \
|
||||
FPGA_FAMILY \
|
||||
FPGA_TECHNOLOGY"
|
||||
|
||||
adi_auto_assign_device_spec $cellpath
|
||||
}
|
||||
|
||||
# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)
|
||||
proc adi_auto_assign_device_spec {cellpath} {
|
||||
|
||||
set ip [get_bd_cells $cellpath]
|
||||
set ip_param_list [list_property $ip]
|
||||
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
|
||||
|
||||
set parent_dir "../"
|
||||
for {set x 1} {$x<=4} {incr x} {
|
||||
set linkname ${ip_path}${parent_dir}scripts/adi_xilinx_device_info_enc.tcl
|
||||
if { [file exists $linkname] } {
|
||||
source ${ip_path}${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl
|
||||
break
|
||||
}
|
||||
append parent_dir "../"
|
||||
}
|
||||
|
||||
# Find predefindes auto assignable parameters
|
||||
foreach i $auto_set_param_list {
|
||||
if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
|
||||
set val [adi_device_spec $cellpath $i]
|
||||
set_property CONFIG.$i $val $ip
|
||||
}
|
||||
}
|
||||
|
||||
# Find predefindes auto assignable/overwritable parameters
|
||||
foreach i $auto_set_param_list_overwritable {
|
||||
if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
|
||||
set val [adi_device_spec $cellpath $i]
|
||||
set_property CONFIG.$i $val $ip
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,2 @@
|
||||
CLEAN_TARGET += bd
|
||||
CLEAN_TARGET += temporary_case_dependencies.mk
|
||||
@@ -0,0 +1,148 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||
ipgui::add_param $IPINST -name "DAC_DATAPATH_DISABLE" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "DAC_DDS_CORDIC_DW" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "DAC_DDS_CORDIC_PHASE_DW" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "DAC_DDS_TYPE" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "ID" -parent ${Page_0}
|
||||
#Adding Group
|
||||
set FPGA_info [ipgui::add_group $IPINST -name "FPGA info" -parent ${Page_0}]
|
||||
ipgui::add_param $IPINST -name "FPGA_TECHNOLOGY" -parent ${FPGA_info} -widget comboBox
|
||||
ipgui::add_param $IPINST -name "FPGA_FAMILY" -parent ${FPGA_info} -widget comboBox
|
||||
ipgui::add_param $IPINST -name "SPEED_GRADE" -parent ${FPGA_info} -widget comboBox
|
||||
ipgui::add_param $IPINST -name "DEV_PACKAGE" -parent ${FPGA_info} -widget comboBox
|
||||
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DAC_DATAPATH_DISABLE { PARAM_VALUE.DAC_DATAPATH_DISABLE } {
|
||||
# Procedure called to update DAC_DATAPATH_DISABLE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DAC_DATAPATH_DISABLE { PARAM_VALUE.DAC_DATAPATH_DISABLE } {
|
||||
# Procedure called to validate DAC_DATAPATH_DISABLE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DAC_DDS_CORDIC_DW { PARAM_VALUE.DAC_DDS_CORDIC_DW } {
|
||||
# Procedure called to update DAC_DDS_CORDIC_DW when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DAC_DDS_CORDIC_DW { PARAM_VALUE.DAC_DDS_CORDIC_DW } {
|
||||
# Procedure called to validate DAC_DDS_CORDIC_DW
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW { PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW } {
|
||||
# Procedure called to update DAC_DDS_CORDIC_PHASE_DW when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW { PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW } {
|
||||
# Procedure called to validate DAC_DDS_CORDIC_PHASE_DW
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DAC_DDS_TYPE { PARAM_VALUE.DAC_DDS_TYPE } {
|
||||
# Procedure called to update DAC_DDS_TYPE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DAC_DDS_TYPE { PARAM_VALUE.DAC_DDS_TYPE } {
|
||||
# Procedure called to validate DAC_DDS_TYPE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } {
|
||||
# Procedure called to update DEV_PACKAGE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } {
|
||||
# Procedure called to validate DEV_PACKAGE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } {
|
||||
# Procedure called to update FPGA_FAMILY when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } {
|
||||
# Procedure called to validate FPGA_FAMILY
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } {
|
||||
# Procedure called to update FPGA_TECHNOLOGY when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } {
|
||||
# Procedure called to validate FPGA_TECHNOLOGY
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } {
|
||||
# Procedure called to update ID when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } {
|
||||
# Procedure called to validate ID
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } {
|
||||
# Procedure called to update SPEED_GRADE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } {
|
||||
# Procedure called to validate SPEED_GRADE
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.FPGA_TECHNOLOGY { MODELPARAM_VALUE.FPGA_TECHNOLOGY PARAM_VALUE.FPGA_TECHNOLOGY } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.FPGA_TECHNOLOGY}] ${MODELPARAM_VALUE.FPGA_TECHNOLOGY}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.FPGA_FAMILY { MODELPARAM_VALUE.FPGA_FAMILY PARAM_VALUE.FPGA_FAMILY } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.FPGA_FAMILY}] ${MODELPARAM_VALUE.FPGA_FAMILY}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.SPEED_GRADE { MODELPARAM_VALUE.SPEED_GRADE PARAM_VALUE.SPEED_GRADE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.SPEED_GRADE}] ${MODELPARAM_VALUE.SPEED_GRADE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DEV_PACKAGE { MODELPARAM_VALUE.DEV_PACKAGE PARAM_VALUE.DEV_PACKAGE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DEV_PACKAGE}] ${MODELPARAM_VALUE.DEV_PACKAGE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DAC_DDS_TYPE { MODELPARAM_VALUE.DAC_DDS_TYPE PARAM_VALUE.DAC_DDS_TYPE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DAC_DDS_TYPE}] ${MODELPARAM_VALUE.DAC_DDS_TYPE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DAC_DDS_CORDIC_DW { MODELPARAM_VALUE.DAC_DDS_CORDIC_DW PARAM_VALUE.DAC_DDS_CORDIC_DW } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DAC_DDS_CORDIC_DW}] ${MODELPARAM_VALUE.DAC_DDS_CORDIC_DW}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW { MODELPARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW}] ${MODELPARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DAC_DATAPATH_DISABLE { MODELPARAM_VALUE.DAC_DATAPATH_DISABLE PARAM_VALUE.DAC_DATAPATH_DISABLE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DAC_DATAPATH_DISABLE}] ${MODELPARAM_VALUE.DAC_DATAPATH_DISABLE}
|
||||
}
|
||||
|
||||
@@ -0,0 +1,32 @@
|
||||
####################################################################################
|
||||
## Copyright 2018(c) Analog Devices, Inc.
|
||||
## Auto-generated, do not modify!
|
||||
####################################################################################
|
||||
|
||||
LIBRARY_NAME := axi_ad9162
|
||||
|
||||
GENERIC_DEPS += ../common/ad_dds_1.v
|
||||
GENERIC_DEPS += ../common/ad_dds_2.v
|
||||
GENERIC_DEPS += ../common/ad_dds_cordic_pipe.v
|
||||
GENERIC_DEPS += ../common/ad_dds_sine.v
|
||||
GENERIC_DEPS += ../common/ad_dds_sine_cordic.v
|
||||
GENERIC_DEPS += ../common/ad_rst.v
|
||||
GENERIC_DEPS += ../common/up_axi.v
|
||||
GENERIC_DEPS += ../common/up_clock_mon.v
|
||||
GENERIC_DEPS += ../common/up_dac_channel.v
|
||||
GENERIC_DEPS += ../common/up_dac_common.v
|
||||
GENERIC_DEPS += ../common/up_xfer_cntrl.v
|
||||
GENERIC_DEPS += ../common/up_xfer_status.v
|
||||
GENERIC_DEPS += axi_ad9162.v
|
||||
GENERIC_DEPS += axi_ad9162_channel.v
|
||||
GENERIC_DEPS += axi_ad9162_core.v
|
||||
GENERIC_DEPS += axi_ad9162_if.v
|
||||
|
||||
XILINX_DEPS += ../xilinx/common/ad_mul.v
|
||||
XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc
|
||||
XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc
|
||||
XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
|
||||
XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc
|
||||
XILINX_DEPS += axi_ad9162_ip.tcl
|
||||
|
||||
include ../scripts/library.mk
|
||||
@@ -0,0 +1,3 @@
|
||||
version:1
|
||||
6d6f64655f636f756e7465727c42617463684d6f6465:1
|
||||
eof:
|
||||
@@ -0,0 +1,6 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<labtools version="1" minor="0"/>
|
||||
@@ -0,0 +1,191 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module axi_ad9162 #(
|
||||
|
||||
parameter ID = 0,
|
||||
parameter FPGA_TECHNOLOGY = 0,
|
||||
parameter FPGA_FAMILY = 0,
|
||||
parameter SPEED_GRADE = 0,
|
||||
parameter DEV_PACKAGE = 0,
|
||||
parameter DAC_DDS_TYPE = 1,
|
||||
parameter DAC_DDS_CORDIC_DW = 16,
|
||||
parameter DAC_DDS_CORDIC_PHASE_DW = 16,
|
||||
parameter DAC_DATAPATH_DISABLE = 0) (
|
||||
|
||||
// jesd interface
|
||||
// tx_clk is (line-rate/40)
|
||||
|
||||
input tx_clk,
|
||||
output tx_valid,
|
||||
output [255:0] tx_data,
|
||||
input tx_ready,
|
||||
|
||||
// dma interface
|
||||
|
||||
output dac_clk,
|
||||
output dac_valid,
|
||||
output dac_enable,
|
||||
input [255:0] dac_ddata,
|
||||
input dac_dunf,
|
||||
|
||||
// axi interface
|
||||
|
||||
input s_axi_aclk,
|
||||
input s_axi_aresetn,
|
||||
input s_axi_awvalid,
|
||||
input [ 15:0] s_axi_awaddr,
|
||||
input [ 2:0] s_axi_awprot,
|
||||
output s_axi_awready,
|
||||
input s_axi_wvalid,
|
||||
input [ 31:0] s_axi_wdata,
|
||||
input [ 3:0] s_axi_wstrb,
|
||||
output s_axi_wready,
|
||||
output s_axi_bvalid,
|
||||
output [ 1:0] s_axi_bresp,
|
||||
input s_axi_bready,
|
||||
input s_axi_arvalid,
|
||||
input [ 15:0] s_axi_araddr,
|
||||
input [ 2:0] s_axi_arprot,
|
||||
output s_axi_arready,
|
||||
output s_axi_rvalid,
|
||||
output [ 31:0] s_axi_rdata,
|
||||
output [ 1:0] s_axi_rresp,
|
||||
input s_axi_rready);
|
||||
|
||||
// internal clocks and resets
|
||||
|
||||
wire dac_rst;
|
||||
wire up_clk;
|
||||
wire up_rstn;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire [255:0] dac_data_s;
|
||||
wire up_wreq_s;
|
||||
wire [ 13:0] up_waddr_s;
|
||||
wire [ 31:0] up_wdata_s;
|
||||
wire up_wack_s;
|
||||
wire up_rreq_s;
|
||||
wire [ 13:0] up_raddr_s;
|
||||
wire [ 31:0] up_rdata_s;
|
||||
wire up_rack_s;
|
||||
|
||||
// signal name changes
|
||||
|
||||
assign up_clk = s_axi_aclk;
|
||||
assign up_rstn = s_axi_aresetn;
|
||||
|
||||
// defaults
|
||||
|
||||
assign tx_valid = 1'b1;
|
||||
|
||||
// device interface
|
||||
|
||||
axi_ad9162_if i_if (
|
||||
.tx_clk (tx_clk),
|
||||
.tx_data (tx_data),
|
||||
.dac_clk (dac_clk),
|
||||
.dac_rst (dac_rst),
|
||||
.dac_data (dac_data_s));
|
||||
|
||||
// core
|
||||
|
||||
axi_ad9162_core #(
|
||||
.ID (ID),
|
||||
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
|
||||
.FPGA_FAMILY (FPGA_FAMILY),
|
||||
.SPEED_GRADE (SPEED_GRADE),
|
||||
.DEV_PACKAGE (DEV_PACKAGE),
|
||||
.DAC_DDS_TYPE (DAC_DDS_TYPE),
|
||||
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
|
||||
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
|
||||
.DATAPATH_DISABLE (DAC_DATAPATH_DISABLE))
|
||||
i_core (
|
||||
.dac_clk (dac_clk),
|
||||
.dac_rst (dac_rst),
|
||||
.dac_data (dac_data_s),
|
||||
.dac_valid (dac_valid),
|
||||
.dac_enable (dac_enable),
|
||||
.dac_ddata (dac_ddata),
|
||||
.dac_dunf (dac_dunf),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq_s),
|
||||
.up_waddr (up_waddr_s),
|
||||
.up_wdata (up_wdata_s),
|
||||
.up_wack (up_wack_s),
|
||||
.up_rreq (up_rreq_s),
|
||||
.up_raddr (up_raddr_s),
|
||||
.up_rdata (up_rdata_s),
|
||||
.up_rack (up_rack_s));
|
||||
|
||||
// up bus interface
|
||||
|
||||
up_axi i_up_axi (
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_axi_awvalid (s_axi_awvalid),
|
||||
.up_axi_awaddr (s_axi_awaddr),
|
||||
.up_axi_awready (s_axi_awready),
|
||||
.up_axi_wvalid (s_axi_wvalid),
|
||||
.up_axi_wdata (s_axi_wdata),
|
||||
.up_axi_wstrb (s_axi_wstrb),
|
||||
.up_axi_wready (s_axi_wready),
|
||||
.up_axi_bvalid (s_axi_bvalid),
|
||||
.up_axi_bresp (s_axi_bresp),
|
||||
.up_axi_bready (s_axi_bready),
|
||||
.up_axi_arvalid (s_axi_arvalid),
|
||||
.up_axi_araddr (s_axi_araddr),
|
||||
.up_axi_arready (s_axi_arready),
|
||||
.up_axi_rvalid (s_axi_rvalid),
|
||||
.up_axi_rresp (s_axi_rresp),
|
||||
.up_axi_rdata (s_axi_rdata),
|
||||
.up_axi_rready (s_axi_rready),
|
||||
.up_wreq (up_wreq_s),
|
||||
.up_waddr (up_waddr_s),
|
||||
.up_wdata (up_wdata_s),
|
||||
.up_wack (up_wack_s),
|
||||
.up_rreq (up_rreq_s),
|
||||
.up_raddr (up_raddr_s),
|
||||
.up_rdata (up_rdata_s),
|
||||
.up_rack (up_rack_s));
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
@@ -0,0 +1,519 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Version="7" Minor="40" Path="/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9162/axi_ad9162.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="b27539d14306423b8eea141831d1e472"/>
|
||||
<Option Name="Part" Val="xc7vx485tffg1157-1"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="BoardPart" Val=""/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../library"/>
|
||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../../ghdl/library"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="DSAVendor" Val="xilinx"/>
|
||||
<Option Name="DSANumComputeUnits" Val="60"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="0"/>
|
||||
<Option Name="WTModelSimExportSim" Val="0"/>
|
||||
<Option Name="WTQuestaExportSim" Val="0"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="0"/>
|
||||
<Option Name="WTRivieraExportSim" Val="0"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
<Option Name="SimTypes" Val="bfm"/>
|
||||
<Option Name="SimTypes" Val="tlm"/>
|
||||
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="31">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/../common/ad_dds_1.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../common/ad_dds_2.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../common/ad_dds_cordic_pipe.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../common/ad_dds_sine.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../common/ad_dds_sine_cordic.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../xilinx/common/ad_mul.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../common/ad_rst.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/axi_ad9162_channel.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/axi_ad9162_core.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/axi_ad9162_if.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../common/up_axi.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../common/up_clock_mon.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../common/up_dac_channel.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../common/up_dac_common.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../common/up_xfer_cntrl.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../common/up_xfer_status.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/axi_ad9162.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/component.xml">
|
||||
<FileInfo SFType="IPXACT"/>
|
||||
</File>
|
||||
<File Path="$PPRDIR/bd/bd.tcl">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="axi_ad9162"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<File Path="$PPRDIR/../xilinx/common/up_xfer_cntrl_constr.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../xilinx/common/ad_rst_constr.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../xilinx/common/up_xfer_status_constr.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../xilinx/common/up_clock_mon_constr.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="IES">
|
||||
<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Xcelium">
|
||||
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="VCS">
|
||||
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="10">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Vivado 12-1790"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="1"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="Evaluation"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="features"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="should"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="NOT"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="be"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="used"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="in"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="production"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="systems."/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Place 30-73"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="10"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="axi_spi"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val=""/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="11"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1343"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="2"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1306"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="3"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="ERROR"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1276"/>
|
||||
<MsgAttr Name="Severity" Val="CRITICAL WARNING"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="4"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-3656"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="5"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-4623"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="6"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-459"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="7"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Synth 8-3331"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="8"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Designutils 20-3303"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="9"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="HDPYFinalizeIO"/>
|
||||
</MsgRule>
|
||||
<Board/>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
<BootPmcSettings Version="1" Minor="0">
|
||||
<Parameters>
|
||||
<Parameter Name="PMC_CDO.ATTRS.LOADADDR" Value="" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_FB_CLK" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_FREQ" Value="300" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_BUS_WIDTH" Value="x1" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_DATA_MODE" Value="Single" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_FREQ" Value="200" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_SLOT_TYPE" Value="SD 2.0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_FREQ" Value="200" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_SLOT_TYPE" Value="SD 2.0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSPI_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSPI_FREQ" Value="300" Type="string"/>
|
||||
<Parameter Name="BOOT.USB_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SMAP_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SMAP_DATA_WIDTH" Value="32 Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSC_FREQ" Value="33.333" Type="string"/>
|
||||
<Parameter Name="BOOT.SECONDARY.PCIE_ENABLE" Value="0" Type="string"/>
|
||||
</Parameters>
|
||||
</BootPmcSettings>
|
||||
</Project>
|
||||
@@ -0,0 +1,577 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module axi_ad9162_channel #(
|
||||
|
||||
parameter CHANNEL_ID = 32'h0,
|
||||
parameter DAC_DDS_TYPE = 1,
|
||||
parameter DAC_DDS_CORDIC_DW = 16,
|
||||
parameter DAC_DDS_CORDIC_PHASE_DW = 16,
|
||||
parameter DATAPATH_DISABLE = 0) (
|
||||
|
||||
// dac interface
|
||||
|
||||
input dac_clk,
|
||||
input dac_rst,
|
||||
output dac_enable,
|
||||
output [255:0] dac_data,
|
||||
input [255:0] dma_data,
|
||||
|
||||
// processor interface
|
||||
|
||||
input dac_data_sync,
|
||||
input dac_dds_format,
|
||||
|
||||
// bus interface
|
||||
|
||||
input up_rstn,
|
||||
input up_clk,
|
||||
input up_wreq,
|
||||
input [ 13:0] up_waddr,
|
||||
input [ 31:0] up_wdata,
|
||||
output up_wack,
|
||||
input up_rreq,
|
||||
input [ 13:0] up_raddr,
|
||||
output [ 31:0] up_rdata,
|
||||
output up_rack);
|
||||
|
||||
// internal registers
|
||||
|
||||
reg [255:0] dac_data_int = 'd0;
|
||||
reg dac_enable_int = 'd0;
|
||||
reg [255:0] dac_data_d = 'd0;
|
||||
reg [ 15:0] dac_dds_phase_00_0 = 'd0;
|
||||
reg [ 15:0] dac_dds_phase_00_1 = 'd0;
|
||||
reg [ 15:0] dac_dds_phase_01_0 = 'd0;
|
||||
reg [ 15:0] dac_dds_phase_01_1 = 'd0;
|
||||
reg [ 15:0] dac_dds_phase_02_0 = 'd0;
|
||||
reg [ 15:0] dac_dds_phase_02_1 = 'd0;
|
||||
reg [ 15:0] dac_dds_phase_03_0 = 'd0;
|
||||
reg [ 15:0] dac_dds_phase_03_1 = 'd0;
|
||||
reg [ 15:0] dac_dds_phase_04_0 = 'd0;
|
||||
reg [ 15:0] dac_dds_phase_04_1 = 'd0;
|
||||
reg [ 15:0] dac_dds_phase_05_0 = 'd0;
|
||||
reg [ 15:0] dac_dds_phase_05_1 = 'd0;
|
||||
reg [ 15:0] dac_dds_phase_06_0 = 'd0;
|
||||
reg [ 15:0] dac_dds_phase_06_1 = 'd0;
|
||||
reg [ 15:0] dac_dds_phase_07_0 = 'd0;
|
||||
reg [ 15:0] dac_dds_phase_07_1 = 'd0;
|
||||
reg [ 15:0] dac_dds_phase_08_0 = 'd0;
|
||||
reg [ 15:0] dac_dds_phase_08_1 = 'd0;
|
||||
reg [ 15:0] dac_dds_phase_09_0 = 'd0;
|
||||
reg [ 15:0] dac_dds_phase_09_1 = 'd0;
|
||||
reg [ 15:0] dac_dds_phase_10_0 = 'd0;
|
||||
reg [ 15:0] dac_dds_phase_10_1 = 'd0;
|
||||
reg [ 15:0] dac_dds_phase_11_0 = 'd0;
|
||||
reg [ 15:0] dac_dds_phase_11_1 = 'd0;
|
||||
reg [ 15:0] dac_dds_phase_12_0 = 'd0;
|
||||
reg [ 15:0] dac_dds_phase_12_1 = 'd0;
|
||||
reg [ 15:0] dac_dds_phase_13_0 = 'd0;
|
||||
reg [ 15:0] dac_dds_phase_13_1 = 'd0;
|
||||
reg [ 15:0] dac_dds_phase_14_0 = 'd0;
|
||||
reg [ 15:0] dac_dds_phase_14_1 = 'd0;
|
||||
reg [ 15:0] dac_dds_phase_15_0 = 'd0;
|
||||
reg [ 15:0] dac_dds_phase_15_1 = 'd0;
|
||||
reg [ 15:0] dac_dds_incr_0 = 'd0;
|
||||
reg [ 15:0] dac_dds_incr_1 = 'd0;
|
||||
reg [255:0] dac_dds_data = 'd0;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire [ 15:0] dac_dds_scale_1_s;
|
||||
wire [ 15:0] dac_dds_init_1_s;
|
||||
wire [ 15:0] dac_dds_incr_1_s;
|
||||
wire [ 15:0] dac_dds_scale_2_s;
|
||||
wire [ 15:0] dac_dds_init_2_s;
|
||||
wire [ 15:0] dac_dds_incr_2_s;
|
||||
wire [ 15:0] dac_pat_data_1_s;
|
||||
wire [ 15:0] dac_pat_data_2_s;
|
||||
wire [ 3:0] dac_data_sel_s;
|
||||
wire [ 1:0] dac_iq_mode_s;
|
||||
wire [255:0] dac_pat_data_s;
|
||||
wire [255:0] dac_dds_data_s;
|
||||
wire [255:0] dac_dds_data_i_s;
|
||||
|
||||
// dac sample mux
|
||||
|
||||
assign dac_data = dac_data_int;
|
||||
|
||||
always @(posedge dac_clk) begin
|
||||
dac_data_int[255:240] <= (dac_iq_mode_s[0] == 1'b1) ? dac_data_d[255:240] : dac_data_d[255:240];
|
||||
dac_data_int[239:224] <= (dac_iq_mode_s[0] == 1'b1) ? dac_data_d[223:208] : dac_data_d[239:224];
|
||||
dac_data_int[223:208] <= (dac_iq_mode_s[0] == 1'b1) ? dac_data_d[239:224] : dac_data_d[223:208];
|
||||
dac_data_int[207:192] <= (dac_iq_mode_s[0] == 1'b1) ? dac_data_d[207:192] : dac_data_d[207:192];
|
||||
dac_data_int[191:176] <= (dac_iq_mode_s[0] == 1'b1) ? dac_data_d[191:176] : dac_data_d[191:176];
|
||||
dac_data_int[175:160] <= (dac_iq_mode_s[0] == 1'b1) ? dac_data_d[159:144] : dac_data_d[175:160];
|
||||
dac_data_int[159:144] <= (dac_iq_mode_s[0] == 1'b1) ? dac_data_d[175:160] : dac_data_d[159:144];
|
||||
dac_data_int[143:128] <= (dac_iq_mode_s[0] == 1'b1) ? dac_data_d[143:128] : dac_data_d[143:128];
|
||||
dac_data_int[127:112] <= (dac_iq_mode_s[0] == 1'b1) ? dac_data_d[127:112] : dac_data_d[127:112];
|
||||
dac_data_int[111: 96] <= (dac_iq_mode_s[0] == 1'b1) ? dac_data_d[ 95: 80] : dac_data_d[111: 96];
|
||||
dac_data_int[ 95: 80] <= (dac_iq_mode_s[0] == 1'b1) ? dac_data_d[111: 96] : dac_data_d[ 95: 80];
|
||||
dac_data_int[ 79: 64] <= (dac_iq_mode_s[0] == 1'b1) ? dac_data_d[ 79: 64] : dac_data_d[ 79: 64];
|
||||
dac_data_int[ 63: 48] <= (dac_iq_mode_s[0] == 1'b1) ? dac_data_d[ 63: 48] : dac_data_d[ 63: 48];
|
||||
dac_data_int[ 47: 32] <= (dac_iq_mode_s[0] == 1'b1) ? dac_data_d[ 31: 16] : dac_data_d[ 47: 32];
|
||||
dac_data_int[ 31: 16] <= (dac_iq_mode_s[0] == 1'b1) ? dac_data_d[ 47: 32] : dac_data_d[ 31: 16];
|
||||
dac_data_int[ 15: 0] <= (dac_iq_mode_s[0] == 1'b1) ? dac_data_d[ 15: 0] : dac_data_d[ 15: 0];
|
||||
end
|
||||
|
||||
// dac pattern data
|
||||
|
||||
genvar n;
|
||||
generate
|
||||
for (n = 0; n < 8; n = n + 1) begin: g_dac_pat_data
|
||||
assign dac_pat_data_s[((32*n)+31):((32*n)+16)] = dac_pat_data_2_s;
|
||||
assign dac_pat_data_s[((32*n)+15):((32*n)+ 0)] = dac_pat_data_1_s;
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// dac data select
|
||||
|
||||
assign dac_enable = dac_enable_int;
|
||||
|
||||
always @(posedge dac_clk) begin
|
||||
dac_enable_int <= (dac_data_sel_s == 4'h2) ? 1'b1 : 1'b0;
|
||||
case (dac_data_sel_s)
|
||||
4'h3: dac_data_d <= 256'd0;
|
||||
4'h2: dac_data_d <= dma_data;
|
||||
4'h1: dac_data_d <= dac_pat_data_s;
|
||||
default: dac_data_d <= dac_dds_data;
|
||||
endcase
|
||||
end
|
||||
|
||||
// dds
|
||||
|
||||
always @(posedge dac_clk) begin
|
||||
if (dac_data_sync == 1'b0) begin
|
||||
dac_dds_phase_00_0 <= dac_dds_phase_00_0 + dac_dds_incr_0;
|
||||
dac_dds_phase_00_1 <= dac_dds_phase_00_1 + dac_dds_incr_1;
|
||||
dac_dds_phase_01_0 <= dac_dds_phase_01_0 + dac_dds_incr_0;
|
||||
dac_dds_phase_01_1 <= dac_dds_phase_01_1 + dac_dds_incr_1;
|
||||
dac_dds_phase_02_0 <= dac_dds_phase_02_0 + dac_dds_incr_0;
|
||||
dac_dds_phase_02_1 <= dac_dds_phase_02_1 + dac_dds_incr_1;
|
||||
dac_dds_phase_03_0 <= dac_dds_phase_03_0 + dac_dds_incr_0;
|
||||
dac_dds_phase_03_1 <= dac_dds_phase_03_1 + dac_dds_incr_1;
|
||||
dac_dds_phase_04_0 <= dac_dds_phase_04_0 + dac_dds_incr_0;
|
||||
dac_dds_phase_04_1 <= dac_dds_phase_04_1 + dac_dds_incr_1;
|
||||
dac_dds_phase_05_0 <= dac_dds_phase_05_0 + dac_dds_incr_0;
|
||||
dac_dds_phase_05_1 <= dac_dds_phase_05_1 + dac_dds_incr_1;
|
||||
dac_dds_phase_06_0 <= dac_dds_phase_06_0 + dac_dds_incr_0;
|
||||
dac_dds_phase_06_1 <= dac_dds_phase_06_1 + dac_dds_incr_1;
|
||||
dac_dds_phase_07_0 <= dac_dds_phase_07_0 + dac_dds_incr_0;
|
||||
dac_dds_phase_07_1 <= dac_dds_phase_07_1 + dac_dds_incr_1;
|
||||
dac_dds_phase_08_0 <= dac_dds_phase_08_0 + dac_dds_incr_0;
|
||||
dac_dds_phase_08_1 <= dac_dds_phase_08_1 + dac_dds_incr_1;
|
||||
dac_dds_phase_09_0 <= dac_dds_phase_09_0 + dac_dds_incr_0;
|
||||
dac_dds_phase_09_1 <= dac_dds_phase_09_1 + dac_dds_incr_1;
|
||||
dac_dds_phase_10_0 <= dac_dds_phase_10_0 + dac_dds_incr_0;
|
||||
dac_dds_phase_10_1 <= dac_dds_phase_10_1 + dac_dds_incr_1;
|
||||
dac_dds_phase_11_0 <= dac_dds_phase_11_0 + dac_dds_incr_0;
|
||||
dac_dds_phase_11_1 <= dac_dds_phase_11_1 + dac_dds_incr_1;
|
||||
dac_dds_phase_12_0 <= dac_dds_phase_12_0 + dac_dds_incr_0;
|
||||
dac_dds_phase_12_1 <= dac_dds_phase_12_1 + dac_dds_incr_1;
|
||||
dac_dds_phase_13_0 <= dac_dds_phase_13_0 + dac_dds_incr_0;
|
||||
dac_dds_phase_13_1 <= dac_dds_phase_13_1 + dac_dds_incr_1;
|
||||
dac_dds_phase_14_0 <= dac_dds_phase_14_0 + dac_dds_incr_0;
|
||||
dac_dds_phase_14_1 <= dac_dds_phase_14_1 + dac_dds_incr_1;
|
||||
dac_dds_phase_15_0 <= dac_dds_phase_15_0 + dac_dds_incr_0;
|
||||
dac_dds_phase_15_1 <= dac_dds_phase_15_1 + dac_dds_incr_1;
|
||||
dac_dds_incr_0 <= dac_dds_incr_0;
|
||||
dac_dds_incr_1 <= dac_dds_incr_1;
|
||||
dac_dds_data <= dac_dds_data_s;
|
||||
end else if (dac_iq_mode_s[0] == 1'b1) begin
|
||||
dac_dds_phase_00_0 <= dac_dds_init_1_s;
|
||||
dac_dds_phase_00_1 <= dac_dds_init_2_s;
|
||||
dac_dds_phase_01_0 <= dac_dds_phase_00_0 + 16'h4000;
|
||||
dac_dds_phase_01_1 <= dac_dds_phase_00_1 + 16'h4000;
|
||||
dac_dds_phase_02_0 <= dac_dds_phase_00_0 + dac_dds_incr_1_s;
|
||||
dac_dds_phase_02_1 <= dac_dds_phase_00_1 + dac_dds_incr_2_s;
|
||||
dac_dds_phase_03_0 <= dac_dds_phase_02_0 + 16'h4000;
|
||||
dac_dds_phase_03_1 <= dac_dds_phase_02_1 + 16'h4000;
|
||||
dac_dds_phase_04_0 <= dac_dds_phase_02_0 + dac_dds_incr_1_s;
|
||||
dac_dds_phase_04_1 <= dac_dds_phase_02_1 + dac_dds_incr_2_s;
|
||||
dac_dds_phase_05_0 <= dac_dds_phase_04_0 + 16'h4000;
|
||||
dac_dds_phase_05_1 <= dac_dds_phase_04_1 + 16'h4000;
|
||||
dac_dds_phase_06_0 <= dac_dds_phase_04_0 + dac_dds_incr_1_s;
|
||||
dac_dds_phase_06_1 <= dac_dds_phase_04_1 + dac_dds_incr_2_s;
|
||||
dac_dds_phase_07_0 <= dac_dds_phase_06_0 + 16'h4000;
|
||||
dac_dds_phase_07_1 <= dac_dds_phase_06_1 + 16'h4000;
|
||||
dac_dds_phase_08_0 <= dac_dds_phase_06_0 + dac_dds_incr_1_s;
|
||||
dac_dds_phase_08_1 <= dac_dds_phase_06_1 + dac_dds_incr_2_s;
|
||||
dac_dds_phase_09_0 <= dac_dds_phase_08_0 + 16'h4000;
|
||||
dac_dds_phase_09_1 <= dac_dds_phase_08_1 + 16'h4000;
|
||||
dac_dds_phase_10_0 <= dac_dds_phase_08_0 + dac_dds_incr_1_s;
|
||||
dac_dds_phase_10_1 <= dac_dds_phase_08_1 + dac_dds_incr_2_s;
|
||||
dac_dds_phase_11_0 <= dac_dds_phase_10_0 + 16'h4000;
|
||||
dac_dds_phase_11_1 <= dac_dds_phase_10_1 + 16'h4000;
|
||||
dac_dds_phase_12_0 <= dac_dds_phase_10_0 + dac_dds_incr_1_s;
|
||||
dac_dds_phase_12_1 <= dac_dds_phase_10_1 + dac_dds_incr_2_s;
|
||||
dac_dds_phase_13_0 <= dac_dds_phase_12_0 + 16'h4000;
|
||||
dac_dds_phase_13_1 <= dac_dds_phase_12_1 + 16'h4000;
|
||||
dac_dds_phase_14_0 <= dac_dds_phase_12_0 + dac_dds_incr_1_s;
|
||||
dac_dds_phase_14_1 <= dac_dds_phase_12_1 + dac_dds_incr_2_s;
|
||||
dac_dds_phase_15_0 <= dac_dds_phase_14_0 + 16'h4000;
|
||||
dac_dds_phase_15_1 <= dac_dds_phase_14_1 + 16'h4000;
|
||||
dac_dds_incr_0 <= {dac_dds_incr_1_s[12:0], 3'd0};
|
||||
dac_dds_incr_1 <= {dac_dds_incr_2_s[12:0], 3'd0};
|
||||
dac_dds_data <= 256'd0;
|
||||
end else begin
|
||||
dac_dds_phase_00_0 <= dac_dds_init_1_s;
|
||||
dac_dds_phase_00_1 <= dac_dds_init_2_s;
|
||||
dac_dds_phase_01_0 <= dac_dds_phase_00_0 + dac_dds_incr_1_s;
|
||||
dac_dds_phase_01_1 <= dac_dds_phase_00_1 + dac_dds_incr_2_s;
|
||||
dac_dds_phase_02_0 <= dac_dds_phase_01_0 + dac_dds_incr_1_s;
|
||||
dac_dds_phase_02_1 <= dac_dds_phase_01_1 + dac_dds_incr_2_s;
|
||||
dac_dds_phase_03_0 <= dac_dds_phase_02_0 + dac_dds_incr_1_s;
|
||||
dac_dds_phase_03_1 <= dac_dds_phase_02_1 + dac_dds_incr_2_s;
|
||||
dac_dds_phase_04_0 <= dac_dds_phase_03_0 + dac_dds_incr_1_s;
|
||||
dac_dds_phase_04_1 <= dac_dds_phase_03_1 + dac_dds_incr_2_s;
|
||||
dac_dds_phase_05_0 <= dac_dds_phase_04_0 + dac_dds_incr_1_s;
|
||||
dac_dds_phase_05_1 <= dac_dds_phase_04_1 + dac_dds_incr_2_s;
|
||||
dac_dds_phase_06_0 <= dac_dds_phase_05_0 + dac_dds_incr_1_s;
|
||||
dac_dds_phase_06_1 <= dac_dds_phase_05_1 + dac_dds_incr_2_s;
|
||||
dac_dds_phase_07_0 <= dac_dds_phase_06_0 + dac_dds_incr_1_s;
|
||||
dac_dds_phase_07_1 <= dac_dds_phase_06_1 + dac_dds_incr_2_s;
|
||||
dac_dds_phase_08_0 <= dac_dds_phase_07_0 + dac_dds_incr_1_s;
|
||||
dac_dds_phase_08_1 <= dac_dds_phase_07_1 + dac_dds_incr_2_s;
|
||||
dac_dds_phase_09_0 <= dac_dds_phase_08_0 + dac_dds_incr_1_s;
|
||||
dac_dds_phase_09_1 <= dac_dds_phase_08_1 + dac_dds_incr_2_s;
|
||||
dac_dds_phase_10_0 <= dac_dds_phase_09_0 + dac_dds_incr_1_s;
|
||||
dac_dds_phase_10_1 <= dac_dds_phase_09_1 + dac_dds_incr_2_s;
|
||||
dac_dds_phase_11_0 <= dac_dds_phase_10_0 + dac_dds_incr_1_s;
|
||||
dac_dds_phase_11_1 <= dac_dds_phase_10_1 + dac_dds_incr_2_s;
|
||||
dac_dds_phase_12_0 <= dac_dds_phase_11_0 + dac_dds_incr_1_s;
|
||||
dac_dds_phase_12_1 <= dac_dds_phase_11_1 + dac_dds_incr_2_s;
|
||||
dac_dds_phase_13_0 <= dac_dds_phase_12_0 + dac_dds_incr_1_s;
|
||||
dac_dds_phase_13_1 <= dac_dds_phase_12_1 + dac_dds_incr_2_s;
|
||||
dac_dds_phase_14_0 <= dac_dds_phase_13_0 + dac_dds_incr_1_s;
|
||||
dac_dds_phase_14_1 <= dac_dds_phase_13_1 + dac_dds_incr_2_s;
|
||||
dac_dds_phase_15_0 <= dac_dds_phase_14_0 + dac_dds_incr_1_s;
|
||||
dac_dds_phase_15_1 <= dac_dds_phase_14_1 + dac_dds_incr_2_s;
|
||||
dac_dds_incr_0 <= {dac_dds_incr_1_s[11:0], 4'd0};
|
||||
dac_dds_incr_1 <= {dac_dds_incr_2_s[11:0], 4'd0};
|
||||
dac_dds_data <= 256'd0;
|
||||
end
|
||||
end
|
||||
|
||||
assign dac_dds_data_s[255:240] = (dac_iq_mode_s == 2'b11) ? dac_dds_data_i_s[239:224] : dac_dds_data_i_s[255:240];
|
||||
assign dac_dds_data_s[239:224] = (dac_iq_mode_s == 2'b11) ? dac_dds_data_i_s[255:240] : dac_dds_data_i_s[239:224];
|
||||
assign dac_dds_data_s[223:208] = (dac_iq_mode_s == 2'b11) ? dac_dds_data_i_s[207:192] : dac_dds_data_i_s[223:208];
|
||||
assign dac_dds_data_s[207:192] = (dac_iq_mode_s == 2'b11) ? dac_dds_data_i_s[223:208] : dac_dds_data_i_s[207:192];
|
||||
assign dac_dds_data_s[191:176] = (dac_iq_mode_s == 2'b11) ? dac_dds_data_i_s[175:160] : dac_dds_data_i_s[191:176];
|
||||
assign dac_dds_data_s[175:160] = (dac_iq_mode_s == 2'b11) ? dac_dds_data_i_s[191:176] : dac_dds_data_i_s[175:160];
|
||||
assign dac_dds_data_s[159:144] = (dac_iq_mode_s == 2'b11) ? dac_dds_data_i_s[143:128] : dac_dds_data_i_s[159:144];
|
||||
assign dac_dds_data_s[143:128] = (dac_iq_mode_s == 2'b11) ? dac_dds_data_i_s[159:144] : dac_dds_data_i_s[143:128];
|
||||
assign dac_dds_data_s[127:112] = (dac_iq_mode_s == 2'b11) ? dac_dds_data_i_s[111: 96] : dac_dds_data_i_s[127:112];
|
||||
assign dac_dds_data_s[111: 96] = (dac_iq_mode_s == 2'b11) ? dac_dds_data_i_s[127:112] : dac_dds_data_i_s[111: 96];
|
||||
assign dac_dds_data_s[ 95: 80] = (dac_iq_mode_s == 2'b11) ? dac_dds_data_i_s[ 79: 64] : dac_dds_data_i_s[ 95: 80];
|
||||
assign dac_dds_data_s[ 79: 64] = (dac_iq_mode_s == 2'b11) ? dac_dds_data_i_s[ 95: 80] : dac_dds_data_i_s[ 79: 64];
|
||||
assign dac_dds_data_s[ 63: 48] = (dac_iq_mode_s == 2'b11) ? dac_dds_data_i_s[ 47: 32] : dac_dds_data_i_s[ 63: 48];
|
||||
assign dac_dds_data_s[ 47: 32] = (dac_iq_mode_s == 2'b11) ? dac_dds_data_i_s[ 63: 48] : dac_dds_data_i_s[ 47: 32];
|
||||
assign dac_dds_data_s[ 31: 16] = (dac_iq_mode_s == 2'b11) ? dac_dds_data_i_s[ 15: 0] : dac_dds_data_i_s[ 31: 16];
|
||||
assign dac_dds_data_s[ 15: 0] = (dac_iq_mode_s == 2'b11) ? dac_dds_data_i_s[ 31: 16] : dac_dds_data_i_s[ 15: 0];
|
||||
|
||||
ad_dds_2 #(
|
||||
.DISABLE (DATAPATH_DISABLE),
|
||||
.DDS_TYPE (DAC_DDS_TYPE),
|
||||
.CORDIC_DW (DAC_DDS_CORDIC_DW),
|
||||
.PHASE_DW (DAC_DDS_CORDIC_PHASE_DW))
|
||||
i_dds_00 (
|
||||
.clk (dac_clk),
|
||||
.dds_format (dac_dds_format),
|
||||
.dds_phase_0 (dac_dds_phase_00_0),
|
||||
.dds_scale_0 (dac_dds_scale_1_s),
|
||||
.dds_phase_1 (dac_dds_phase_00_1),
|
||||
.dds_scale_1 (dac_dds_scale_2_s),
|
||||
.dds_data (dac_dds_data_i_s[15:0]));
|
||||
|
||||
ad_dds_2 #(
|
||||
.DISABLE (DATAPATH_DISABLE),
|
||||
.DDS_TYPE (DAC_DDS_TYPE),
|
||||
.CORDIC_DW (DAC_DDS_CORDIC_DW),
|
||||
.PHASE_DW (DAC_DDS_CORDIC_PHASE_DW))
|
||||
i_dds_01 (
|
||||
.clk (dac_clk),
|
||||
.dds_format (dac_dds_format),
|
||||
.dds_phase_0 (dac_dds_phase_01_0),
|
||||
.dds_scale_0 (dac_dds_scale_1_s),
|
||||
.dds_phase_1 (dac_dds_phase_01_1),
|
||||
.dds_scale_1 (dac_dds_scale_2_s),
|
||||
.dds_data (dac_dds_data_i_s[31:16]));
|
||||
|
||||
ad_dds_2 #(
|
||||
.DISABLE (DATAPATH_DISABLE),
|
||||
.DDS_TYPE (DAC_DDS_TYPE),
|
||||
.CORDIC_DW (DAC_DDS_CORDIC_DW),
|
||||
.PHASE_DW (DAC_DDS_CORDIC_PHASE_DW))
|
||||
i_dds_02 (
|
||||
.clk (dac_clk),
|
||||
.dds_format (dac_dds_format),
|
||||
.dds_phase_0 (dac_dds_phase_02_0),
|
||||
.dds_scale_0 (dac_dds_scale_1_s),
|
||||
.dds_phase_1 (dac_dds_phase_02_1),
|
||||
.dds_scale_1 (dac_dds_scale_2_s),
|
||||
.dds_data (dac_dds_data_i_s[47:32]));
|
||||
|
||||
ad_dds_2 #(
|
||||
.DISABLE (DATAPATH_DISABLE),
|
||||
.DDS_TYPE (DAC_DDS_TYPE),
|
||||
.CORDIC_DW (DAC_DDS_CORDIC_DW),
|
||||
.PHASE_DW (DAC_DDS_CORDIC_PHASE_DW))
|
||||
i_dds_03 (
|
||||
.clk (dac_clk),
|
||||
.dds_format (dac_dds_format),
|
||||
.dds_phase_0 (dac_dds_phase_03_0),
|
||||
.dds_scale_0 (dac_dds_scale_1_s),
|
||||
.dds_phase_1 (dac_dds_phase_03_1),
|
||||
.dds_scale_1 (dac_dds_scale_2_s),
|
||||
.dds_data (dac_dds_data_i_s[63:48]));
|
||||
|
||||
ad_dds_2 #(
|
||||
.DISABLE (DATAPATH_DISABLE),
|
||||
.DDS_TYPE (DAC_DDS_TYPE),
|
||||
.CORDIC_DW (DAC_DDS_CORDIC_DW),
|
||||
.PHASE_DW (DAC_DDS_CORDIC_PHASE_DW))
|
||||
i_dds_04 (
|
||||
.clk (dac_clk),
|
||||
.dds_format (dac_dds_format),
|
||||
.dds_phase_0 (dac_dds_phase_04_0),
|
||||
.dds_scale_0 (dac_dds_scale_1_s),
|
||||
.dds_phase_1 (dac_dds_phase_04_1),
|
||||
.dds_scale_1 (dac_dds_scale_2_s),
|
||||
.dds_data (dac_dds_data_i_s[79:64]));
|
||||
|
||||
ad_dds_2 #(
|
||||
.DISABLE (DATAPATH_DISABLE),
|
||||
.DDS_TYPE (DAC_DDS_TYPE),
|
||||
.CORDIC_DW (DAC_DDS_CORDIC_DW),
|
||||
.PHASE_DW (DAC_DDS_CORDIC_PHASE_DW))
|
||||
i_dds_05 (
|
||||
.clk (dac_clk),
|
||||
.dds_format (dac_dds_format),
|
||||
.dds_phase_0 (dac_dds_phase_05_0),
|
||||
.dds_scale_0 (dac_dds_scale_1_s),
|
||||
.dds_phase_1 (dac_dds_phase_05_1),
|
||||
.dds_scale_1 (dac_dds_scale_2_s),
|
||||
.dds_data (dac_dds_data_i_s[95:80]));
|
||||
|
||||
ad_dds_2 #(
|
||||
.DISABLE (DATAPATH_DISABLE),
|
||||
.DDS_TYPE (DAC_DDS_TYPE),
|
||||
.CORDIC_DW (DAC_DDS_CORDIC_DW),
|
||||
.PHASE_DW (DAC_DDS_CORDIC_PHASE_DW))
|
||||
i_dds_06 (
|
||||
.clk (dac_clk),
|
||||
.dds_format (dac_dds_format),
|
||||
.dds_phase_0 (dac_dds_phase_06_0),
|
||||
.dds_scale_0 (dac_dds_scale_1_s),
|
||||
.dds_phase_1 (dac_dds_phase_06_1),
|
||||
.dds_scale_1 (dac_dds_scale_2_s),
|
||||
.dds_data (dac_dds_data_i_s[111:96]));
|
||||
|
||||
ad_dds_2 #(
|
||||
.DISABLE (DATAPATH_DISABLE),
|
||||
.DDS_TYPE (DAC_DDS_TYPE),
|
||||
.CORDIC_DW (DAC_DDS_CORDIC_DW),
|
||||
.PHASE_DW (DAC_DDS_CORDIC_PHASE_DW))
|
||||
i_dds_07 (
|
||||
.clk (dac_clk),
|
||||
.dds_format (dac_dds_format),
|
||||
.dds_phase_0 (dac_dds_phase_07_0),
|
||||
.dds_scale_0 (dac_dds_scale_1_s),
|
||||
.dds_phase_1 (dac_dds_phase_07_1),
|
||||
.dds_scale_1 (dac_dds_scale_2_s),
|
||||
.dds_data (dac_dds_data_i_s[127:112]));
|
||||
|
||||
ad_dds_2 #(
|
||||
.DISABLE (DATAPATH_DISABLE),
|
||||
.DDS_TYPE (DAC_DDS_TYPE),
|
||||
.CORDIC_DW (DAC_DDS_CORDIC_DW),
|
||||
.PHASE_DW (DAC_DDS_CORDIC_PHASE_DW))
|
||||
i_dds_08 (
|
||||
.clk (dac_clk),
|
||||
.dds_format (dac_dds_format),
|
||||
.dds_phase_0 (dac_dds_phase_08_0),
|
||||
.dds_scale_0 (dac_dds_scale_1_s),
|
||||
.dds_phase_1 (dac_dds_phase_08_1),
|
||||
.dds_scale_1 (dac_dds_scale_2_s),
|
||||
.dds_data (dac_dds_data_i_s[143:128]));
|
||||
|
||||
ad_dds_2 #(
|
||||
.DISABLE (DATAPATH_DISABLE),
|
||||
.DDS_TYPE (DAC_DDS_TYPE),
|
||||
.CORDIC_DW (DAC_DDS_CORDIC_DW),
|
||||
.PHASE_DW (DAC_DDS_CORDIC_PHASE_DW))
|
||||
i_dds_09 (
|
||||
.clk (dac_clk),
|
||||
.dds_format (dac_dds_format),
|
||||
.dds_phase_0 (dac_dds_phase_09_0),
|
||||
.dds_scale_0 (dac_dds_scale_1_s),
|
||||
.dds_phase_1 (dac_dds_phase_09_1),
|
||||
.dds_scale_1 (dac_dds_scale_2_s),
|
||||
.dds_data (dac_dds_data_i_s[159:144]));
|
||||
|
||||
ad_dds_2 #(
|
||||
.DISABLE (DATAPATH_DISABLE),
|
||||
.DDS_TYPE (DAC_DDS_TYPE),
|
||||
.CORDIC_DW (DAC_DDS_CORDIC_DW),
|
||||
.PHASE_DW (DAC_DDS_CORDIC_PHASE_DW))
|
||||
i_dds_10 (
|
||||
.clk (dac_clk),
|
||||
.dds_format (dac_dds_format),
|
||||
.dds_phase_0 (dac_dds_phase_10_0),
|
||||
.dds_scale_0 (dac_dds_scale_1_s),
|
||||
.dds_phase_1 (dac_dds_phase_10_1),
|
||||
.dds_scale_1 (dac_dds_scale_2_s),
|
||||
.dds_data (dac_dds_data_i_s[175:160]));
|
||||
|
||||
ad_dds_2 #(
|
||||
.DISABLE (DATAPATH_DISABLE),
|
||||
.DDS_TYPE (DAC_DDS_TYPE),
|
||||
.CORDIC_DW (DAC_DDS_CORDIC_DW),
|
||||
.PHASE_DW (DAC_DDS_CORDIC_PHASE_DW))
|
||||
i_dds_11 (
|
||||
.clk (dac_clk),
|
||||
.dds_format (dac_dds_format),
|
||||
.dds_phase_0 (dac_dds_phase_11_0),
|
||||
.dds_scale_0 (dac_dds_scale_1_s),
|
||||
.dds_phase_1 (dac_dds_phase_11_1),
|
||||
.dds_scale_1 (dac_dds_scale_2_s),
|
||||
.dds_data (dac_dds_data_i_s[191:176]));
|
||||
|
||||
ad_dds_2 #(
|
||||
.DISABLE (DATAPATH_DISABLE),
|
||||
.DDS_TYPE (DAC_DDS_TYPE),
|
||||
.CORDIC_DW (DAC_DDS_CORDIC_DW),
|
||||
.PHASE_DW (DAC_DDS_CORDIC_PHASE_DW))
|
||||
i_dds_12 (
|
||||
.clk (dac_clk),
|
||||
.dds_format (dac_dds_format),
|
||||
.dds_phase_0 (dac_dds_phase_12_0),
|
||||
.dds_scale_0 (dac_dds_scale_1_s),
|
||||
.dds_phase_1 (dac_dds_phase_12_1),
|
||||
.dds_scale_1 (dac_dds_scale_2_s),
|
||||
.dds_data (dac_dds_data_i_s[207:192]));
|
||||
|
||||
ad_dds_2 #(
|
||||
.DISABLE (DATAPATH_DISABLE),
|
||||
.DDS_TYPE (DAC_DDS_TYPE),
|
||||
.CORDIC_DW (DAC_DDS_CORDIC_DW),
|
||||
.PHASE_DW (DAC_DDS_CORDIC_PHASE_DW))
|
||||
i_dds_13 (
|
||||
.clk (dac_clk),
|
||||
.dds_format (dac_dds_format),
|
||||
.dds_phase_0 (dac_dds_phase_13_0),
|
||||
.dds_scale_0 (dac_dds_scale_1_s),
|
||||
.dds_phase_1 (dac_dds_phase_13_1),
|
||||
.dds_scale_1 (dac_dds_scale_2_s),
|
||||
.dds_data (dac_dds_data_i_s[223:208]));
|
||||
|
||||
ad_dds_2 #(
|
||||
.DISABLE (DATAPATH_DISABLE),
|
||||
.DDS_TYPE (DAC_DDS_TYPE),
|
||||
.CORDIC_DW (DAC_DDS_CORDIC_DW),
|
||||
.PHASE_DW (DAC_DDS_CORDIC_PHASE_DW))
|
||||
i_dds_14 (
|
||||
.clk (dac_clk),
|
||||
.dds_format (dac_dds_format),
|
||||
.dds_phase_0 (dac_dds_phase_14_0),
|
||||
.dds_scale_0 (dac_dds_scale_1_s),
|
||||
.dds_phase_1 (dac_dds_phase_14_1),
|
||||
.dds_scale_1 (dac_dds_scale_2_s),
|
||||
.dds_data (dac_dds_data_i_s[239:224]));
|
||||
|
||||
ad_dds_2 #(
|
||||
.DISABLE (DATAPATH_DISABLE),
|
||||
.DDS_TYPE (DAC_DDS_TYPE),
|
||||
.CORDIC_DW (DAC_DDS_CORDIC_DW),
|
||||
.PHASE_DW (DAC_DDS_CORDIC_PHASE_DW))
|
||||
i_dds_15 (
|
||||
.clk (dac_clk),
|
||||
.dds_format (dac_dds_format),
|
||||
.dds_phase_0 (dac_dds_phase_15_0),
|
||||
.dds_scale_0 (dac_dds_scale_1_s),
|
||||
.dds_phase_1 (dac_dds_phase_15_1),
|
||||
.dds_scale_1 (dac_dds_scale_2_s),
|
||||
.dds_data (dac_dds_data_i_s[255:240]));
|
||||
|
||||
// single channel processor
|
||||
|
||||
up_dac_channel #(.CHANNEL_ID(CHANNEL_ID)) i_up_dac_channel (
|
||||
.dac_clk (dac_clk),
|
||||
.dac_rst (dac_rst),
|
||||
.dac_dds_scale_1 (dac_dds_scale_1_s),
|
||||
.dac_dds_init_1 (dac_dds_init_1_s),
|
||||
.dac_dds_incr_1 (dac_dds_incr_1_s),
|
||||
.dac_dds_scale_2 (dac_dds_scale_2_s),
|
||||
.dac_dds_init_2 (dac_dds_init_2_s),
|
||||
.dac_dds_incr_2 (dac_dds_incr_2_s),
|
||||
.dac_pat_data_1 (dac_pat_data_1_s),
|
||||
.dac_pat_data_2 (dac_pat_data_2_s),
|
||||
.dac_data_sel (dac_data_sel_s),
|
||||
.dac_iq_mode (dac_iq_mode_s),
|
||||
.dac_iqcor_enb (),
|
||||
.dac_iqcor_coeff_1 (),
|
||||
.dac_iqcor_coeff_2 (),
|
||||
.up_usr_datatype_be (),
|
||||
.up_usr_datatype_signed (),
|
||||
.up_usr_datatype_shift (),
|
||||
.up_usr_datatype_total_bits (),
|
||||
.up_usr_datatype_bits (),
|
||||
.up_usr_interpolation_m (),
|
||||
.up_usr_interpolation_n (),
|
||||
.dac_usr_datatype_be (1'b0),
|
||||
.dac_usr_datatype_signed (1'b1),
|
||||
.dac_usr_datatype_shift (8'd0),
|
||||
.dac_usr_datatype_total_bits (8'd16),
|
||||
.dac_usr_datatype_bits (8'd16),
|
||||
.dac_usr_interpolation_m (16'd1),
|
||||
.dac_usr_interpolation_n (16'd1),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq),
|
||||
.up_waddr (up_waddr),
|
||||
.up_wdata (up_wdata),
|
||||
.up_wack (up_wack),
|
||||
.up_rreq (up_rreq),
|
||||
.up_raddr (up_raddr),
|
||||
.up_rdata (up_rdata),
|
||||
.up_rack (up_rack));
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
@@ -0,0 +1,190 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module axi_ad9162_core #(
|
||||
|
||||
parameter ID = 0,
|
||||
parameter FPGA_TECHNOLOGY = 0,
|
||||
parameter FPGA_FAMILY = 0,
|
||||
parameter SPEED_GRADE = 0,
|
||||
parameter DEV_PACKAGE = 0,
|
||||
parameter DAC_DDS_TYPE = 1,
|
||||
parameter DAC_DDS_CORDIC_DW = 16,
|
||||
parameter DAC_DDS_CORDIC_PHASE_DW = 16,
|
||||
parameter DATAPATH_DISABLE = 0) (
|
||||
|
||||
// dac interface
|
||||
|
||||
input dac_clk,
|
||||
output dac_rst,
|
||||
output [255:0] dac_data,
|
||||
|
||||
// dma interface
|
||||
|
||||
output dac_valid,
|
||||
output dac_enable,
|
||||
input [255:0] dac_ddata,
|
||||
input dac_dunf,
|
||||
|
||||
// processor interface
|
||||
|
||||
input up_rstn,
|
||||
input up_clk,
|
||||
input up_wreq,
|
||||
input [ 13:0] up_waddr,
|
||||
input [ 31:0] up_wdata,
|
||||
output reg up_wack,
|
||||
input up_rreq,
|
||||
input [ 13:0] up_raddr,
|
||||
output reg [ 31:0] up_rdata,
|
||||
output reg up_rack);
|
||||
|
||||
// internal signals
|
||||
|
||||
wire dac_sync_s;
|
||||
wire dac_datafmt_s;
|
||||
wire [ 31:0] up_rdata_0_s;
|
||||
wire up_rack_0_s;
|
||||
wire up_wack_0_s;
|
||||
wire [ 31:0] up_rdata_s;
|
||||
wire up_rack_s;
|
||||
wire up_wack_s;
|
||||
|
||||
// dac valid
|
||||
|
||||
assign dac_valid = 1'b1;
|
||||
|
||||
// processor read interface
|
||||
|
||||
always @(negedge up_rstn or posedge up_clk) begin
|
||||
if (up_rstn == 0) begin
|
||||
up_rdata <= 'd0;
|
||||
up_rack <= 'd0;
|
||||
up_wack <= 'd0;
|
||||
end else begin
|
||||
up_rdata <= up_rdata_s | up_rdata_0_s;
|
||||
up_rack <= up_rack_s | up_rack_0_s;
|
||||
up_wack <= up_wack_s | up_wack_0_s;
|
||||
end
|
||||
end
|
||||
|
||||
// dac channel
|
||||
|
||||
axi_ad9162_channel #(
|
||||
.CHANNEL_ID (0),
|
||||
.DAC_DDS_TYPE (DAC_DDS_TYPE),
|
||||
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
|
||||
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
|
||||
.DATAPATH_DISABLE (DATAPATH_DISABLE))
|
||||
i_channel_0 (
|
||||
.dac_clk (dac_clk),
|
||||
.dac_rst (dac_rst),
|
||||
.dac_enable (dac_enable),
|
||||
.dac_data (dac_data),
|
||||
.dma_data (dac_ddata),
|
||||
.dac_data_sync (dac_sync_s),
|
||||
.dac_dds_format (dac_datafmt_s),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq),
|
||||
.up_waddr (up_waddr),
|
||||
.up_wdata (up_wdata),
|
||||
.up_wack (up_wack_0_s),
|
||||
.up_rreq (up_rreq),
|
||||
.up_raddr (up_raddr),
|
||||
.up_rdata (up_rdata_0_s),
|
||||
.up_rack (up_rack_0_s));
|
||||
|
||||
// dac common processor interface
|
||||
|
||||
up_dac_common #(
|
||||
.ID (ID),
|
||||
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
|
||||
.FPGA_FAMILY (FPGA_FAMILY),
|
||||
.SPEED_GRADE (SPEED_GRADE),
|
||||
.DEV_PACKAGE (DEV_PACKAGE),
|
||||
.CONFIG (0),
|
||||
.CLK_EDGE_SEL (1'b0),
|
||||
.COMMON_ID (6'h10),
|
||||
.DRP_DISABLE (0),
|
||||
.USERPORTS_DISABLE (0),
|
||||
.GPIO_DISABLE (0))
|
||||
i_up_dac_common (
|
||||
.mmcm_rst (),
|
||||
.dac_clk (dac_clk),
|
||||
.dac_rst (dac_rst),
|
||||
.dac_sync (dac_sync_s),
|
||||
.dac_frame (),
|
||||
.dac_clksel (),
|
||||
.dac_par_type (),
|
||||
.dac_par_enb (),
|
||||
.dac_r1_mode (),
|
||||
.dac_datafmt (dac_datafmt_s),
|
||||
.dac_datarate (),
|
||||
.dac_status (1'b1),
|
||||
.dac_status_unf (dac_dunf),
|
||||
.dac_clk_ratio (32'd16),
|
||||
.up_dac_ce (),
|
||||
.up_pps_rcounter (32'd0),
|
||||
.up_pps_status (1'd0),
|
||||
.up_pps_irq_mask (),
|
||||
.up_drp_sel (),
|
||||
.up_drp_wr (),
|
||||
.up_drp_addr (),
|
||||
.up_drp_wdata (),
|
||||
.up_drp_rdata (32'd0),
|
||||
.up_drp_ready (1'd0),
|
||||
.up_drp_locked (1'd1),
|
||||
.up_usr_chanmax (),
|
||||
.dac_usr_chanmax (8'd0),
|
||||
.up_dac_gpio_in (32'd0),
|
||||
.up_dac_gpio_out (),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_wreq (up_wreq),
|
||||
.up_waddr (up_waddr),
|
||||
.up_wdata (up_wdata),
|
||||
.up_wack (up_wack_s),
|
||||
.up_rreq (up_rreq),
|
||||
.up_raddr (up_raddr),
|
||||
.up_rdata (up_rdata_s),
|
||||
.up_rack (up_rack_s));
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
@@ -0,0 +1,94 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module axi_ad9162_if (
|
||||
|
||||
// jesd interface
|
||||
// tx_clk is (line-rate/40)
|
||||
|
||||
input tx_clk,
|
||||
output reg [255:0] tx_data,
|
||||
|
||||
// dac interface
|
||||
|
||||
output dac_clk,
|
||||
input dac_rst,
|
||||
input [255:0] dac_data);
|
||||
|
||||
// reorder data for the jesd links
|
||||
|
||||
assign dac_clk = tx_clk;
|
||||
|
||||
always @(posedge tx_clk) begin
|
||||
tx_data[255:248] <= dac_data[247:240];
|
||||
tx_data[247:240] <= dac_data[183:176];
|
||||
tx_data[239:232] <= dac_data[119:112];
|
||||
tx_data[231:224] <= dac_data[ 55: 48];
|
||||
tx_data[223:216] <= dac_data[255:248];
|
||||
tx_data[215:208] <= dac_data[191:184];
|
||||
tx_data[207:200] <= dac_data[127:120];
|
||||
tx_data[199:192] <= dac_data[ 63: 56];
|
||||
tx_data[191:184] <= dac_data[231:224];
|
||||
tx_data[183:176] <= dac_data[167:160];
|
||||
tx_data[175:168] <= dac_data[103: 96];
|
||||
tx_data[167:160] <= dac_data[ 39: 32];
|
||||
tx_data[159:152] <= dac_data[239:232];
|
||||
tx_data[151:144] <= dac_data[175:168];
|
||||
tx_data[143:136] <= dac_data[111:104];
|
||||
tx_data[135:128] <= dac_data[ 47: 40];
|
||||
tx_data[127:120] <= dac_data[215:208];
|
||||
tx_data[119:112] <= dac_data[151:144];
|
||||
tx_data[111:104] <= dac_data[ 87: 80];
|
||||
tx_data[103: 96] <= dac_data[ 23: 16];
|
||||
tx_data[ 95: 88] <= dac_data[223:216];
|
||||
tx_data[ 87: 80] <= dac_data[159:152];
|
||||
tx_data[ 79: 72] <= dac_data[ 95: 88];
|
||||
tx_data[ 71: 64] <= dac_data[ 31: 24];
|
||||
tx_data[ 63: 56] <= dac_data[199:192];
|
||||
tx_data[ 55: 48] <= dac_data[135:128];
|
||||
tx_data[ 47: 40] <= dac_data[ 71: 64];
|
||||
tx_data[ 39: 32] <= dac_data[ 7: 0];
|
||||
tx_data[ 31: 24] <= dac_data[207:200];
|
||||
tx_data[ 23: 16] <= dac_data[143:136];
|
||||
tx_data[ 15: 8] <= dac_data[ 79: 72];
|
||||
tx_data[ 7: 0] <= dac_data[ 15: 8];
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
@@ -0,0 +1,43 @@
|
||||
# ip
|
||||
|
||||
source ../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
|
||||
adi_ip_create axi_ad9162
|
||||
adi_ip_files axi_ad9162 [list \
|
||||
"$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \
|
||||
"$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \
|
||||
"$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \
|
||||
"$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \
|
||||
"$ad_hdl_dir/library/xilinx/common/ad_mul.v" \
|
||||
"$ad_hdl_dir/library/common/ad_dds_cordic_pipe.v" \
|
||||
"$ad_hdl_dir/library/common/ad_dds_sine_cordic.v" \
|
||||
"$ad_hdl_dir/library/common/ad_dds_sine.v" \
|
||||
"$ad_hdl_dir/library/common/ad_dds_1.v" \
|
||||
"$ad_hdl_dir/library/common/ad_dds_2.v" \
|
||||
"$ad_hdl_dir/library/common/ad_rst.v" \
|
||||
"$ad_hdl_dir/library/common/up_axi.v" \
|
||||
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
|
||||
"$ad_hdl_dir/library/common/up_xfer_status.v" \
|
||||
"$ad_hdl_dir/library/common/up_clock_mon.v" \
|
||||
"$ad_hdl_dir/library/common/up_dac_common.v" \
|
||||
"$ad_hdl_dir/library/common/up_dac_channel.v" \
|
||||
"axi_ad9162_channel.v" \
|
||||
"axi_ad9162_core.v" \
|
||||
"axi_ad9162_if.v" \
|
||||
"axi_ad9162.v" ]
|
||||
|
||||
adi_ip_properties axi_ad9162
|
||||
|
||||
adi_init_bd_tcl
|
||||
adi_ip_bd axi_ad9162 "bd/bd.tcl"
|
||||
|
||||
set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
|
||||
set_property driver_value 0 [ipx::get_ports *tx_ready* -of_objects [ipx::current_core]]
|
||||
|
||||
ipx::infer_bus_interface tx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
|
||||
adi_add_auto_fpga_spec_params
|
||||
ipx::create_xgui_files [ipx::current_core]
|
||||
|
||||
ipx::save_core [ipx::current_core]
|
||||
@@ -0,0 +1,47 @@
|
||||
# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!
|
||||
proc init {cellpath otherInfo} {
|
||||
set ip [get_bd_cells $cellpath]
|
||||
|
||||
bd::mark_propagate_only $ip " \
|
||||
DEV_PACKAGE \
|
||||
SPEED_GRADE \
|
||||
FPGA_FAMILY \
|
||||
FPGA_TECHNOLOGY"
|
||||
|
||||
adi_auto_assign_device_spec $cellpath
|
||||
}
|
||||
|
||||
# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)
|
||||
proc adi_auto_assign_device_spec {cellpath} {
|
||||
|
||||
set ip [get_bd_cells $cellpath]
|
||||
set ip_param_list [list_property $ip]
|
||||
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
|
||||
|
||||
set parent_dir "../"
|
||||
for {set x 1} {$x<=4} {incr x} {
|
||||
set linkname ${ip_path}${parent_dir}scripts/adi_xilinx_device_info_enc.tcl
|
||||
if { [file exists $linkname] } {
|
||||
source ${ip_path}${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl
|
||||
break
|
||||
}
|
||||
append parent_dir "../"
|
||||
}
|
||||
|
||||
# Find predefindes auto assignable parameters
|
||||
foreach i $auto_set_param_list {
|
||||
if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
|
||||
set val [adi_device_spec $cellpath $i]
|
||||
set_property CONFIG.$i $val $ip
|
||||
}
|
||||
}
|
||||
|
||||
# Find predefindes auto assignable/overwritable parameters
|
||||
foreach i $auto_set_param_list_overwritable {
|
||||
if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
|
||||
set val [adi_device_spec $cellpath $i]
|
||||
set_property CONFIG.$i $val $ip
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,2 @@
|
||||
CLEAN_TARGET += bd
|
||||
CLEAN_TARGET += temporary_case_dependencies.mk
|
||||
@@ -0,0 +1,148 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||
ipgui::add_param $IPINST -name "DAC_DATAPATH_DISABLE" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "DAC_DDS_CORDIC_DW" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "DAC_DDS_CORDIC_PHASE_DW" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "DAC_DDS_TYPE" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "ID" -parent ${Page_0}
|
||||
#Adding Group
|
||||
set FPGA_info [ipgui::add_group $IPINST -name "FPGA info" -parent ${Page_0}]
|
||||
ipgui::add_param $IPINST -name "FPGA_TECHNOLOGY" -parent ${FPGA_info} -widget comboBox
|
||||
ipgui::add_param $IPINST -name "FPGA_FAMILY" -parent ${FPGA_info} -widget comboBox
|
||||
ipgui::add_param $IPINST -name "SPEED_GRADE" -parent ${FPGA_info} -widget comboBox
|
||||
ipgui::add_param $IPINST -name "DEV_PACKAGE" -parent ${FPGA_info} -widget comboBox
|
||||
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DAC_DATAPATH_DISABLE { PARAM_VALUE.DAC_DATAPATH_DISABLE } {
|
||||
# Procedure called to update DAC_DATAPATH_DISABLE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DAC_DATAPATH_DISABLE { PARAM_VALUE.DAC_DATAPATH_DISABLE } {
|
||||
# Procedure called to validate DAC_DATAPATH_DISABLE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DAC_DDS_CORDIC_DW { PARAM_VALUE.DAC_DDS_CORDIC_DW } {
|
||||
# Procedure called to update DAC_DDS_CORDIC_DW when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DAC_DDS_CORDIC_DW { PARAM_VALUE.DAC_DDS_CORDIC_DW } {
|
||||
# Procedure called to validate DAC_DDS_CORDIC_DW
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW { PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW } {
|
||||
# Procedure called to update DAC_DDS_CORDIC_PHASE_DW when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW { PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW } {
|
||||
# Procedure called to validate DAC_DDS_CORDIC_PHASE_DW
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DAC_DDS_TYPE { PARAM_VALUE.DAC_DDS_TYPE } {
|
||||
# Procedure called to update DAC_DDS_TYPE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DAC_DDS_TYPE { PARAM_VALUE.DAC_DDS_TYPE } {
|
||||
# Procedure called to validate DAC_DDS_TYPE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } {
|
||||
# Procedure called to update DEV_PACKAGE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } {
|
||||
# Procedure called to validate DEV_PACKAGE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } {
|
||||
# Procedure called to update FPGA_FAMILY when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } {
|
||||
# Procedure called to validate FPGA_FAMILY
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } {
|
||||
# Procedure called to update FPGA_TECHNOLOGY when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } {
|
||||
# Procedure called to validate FPGA_TECHNOLOGY
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } {
|
||||
# Procedure called to update ID when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } {
|
||||
# Procedure called to validate ID
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } {
|
||||
# Procedure called to update SPEED_GRADE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } {
|
||||
# Procedure called to validate SPEED_GRADE
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.FPGA_TECHNOLOGY { MODELPARAM_VALUE.FPGA_TECHNOLOGY PARAM_VALUE.FPGA_TECHNOLOGY } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.FPGA_TECHNOLOGY}] ${MODELPARAM_VALUE.FPGA_TECHNOLOGY}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.FPGA_FAMILY { MODELPARAM_VALUE.FPGA_FAMILY PARAM_VALUE.FPGA_FAMILY } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.FPGA_FAMILY}] ${MODELPARAM_VALUE.FPGA_FAMILY}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.SPEED_GRADE { MODELPARAM_VALUE.SPEED_GRADE PARAM_VALUE.SPEED_GRADE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.SPEED_GRADE}] ${MODELPARAM_VALUE.SPEED_GRADE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DEV_PACKAGE { MODELPARAM_VALUE.DEV_PACKAGE PARAM_VALUE.DEV_PACKAGE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DEV_PACKAGE}] ${MODELPARAM_VALUE.DEV_PACKAGE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DAC_DDS_TYPE { MODELPARAM_VALUE.DAC_DDS_TYPE PARAM_VALUE.DAC_DDS_TYPE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DAC_DDS_TYPE}] ${MODELPARAM_VALUE.DAC_DDS_TYPE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DAC_DDS_CORDIC_DW { MODELPARAM_VALUE.DAC_DDS_CORDIC_DW PARAM_VALUE.DAC_DDS_CORDIC_DW } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DAC_DDS_CORDIC_DW}] ${MODELPARAM_VALUE.DAC_DDS_CORDIC_DW}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW { MODELPARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW}] ${MODELPARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DAC_DATAPATH_DISABLE { MODELPARAM_VALUE.DAC_DATAPATH_DISABLE PARAM_VALUE.DAC_DATAPATH_DISABLE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DAC_DATAPATH_DISABLE}] ${MODELPARAM_VALUE.DAC_DATAPATH_DISABLE}
|
||||
}
|
||||
|
||||
@@ -0,0 +1,37 @@
|
||||
####################################################################################
|
||||
## Copyright 2018(c) Analog Devices, Inc.
|
||||
## Auto-generated, do not modify!
|
||||
####################################################################################
|
||||
|
||||
LIBRARY_NAME := axi_ad9250
|
||||
|
||||
GENERIC_DEPS += axi_ad9250.v
|
||||
|
||||
XILINX_DEPS += axi_ad9250_ip.tcl
|
||||
|
||||
XILINX_LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc
|
||||
|
||||
INTEL_DEPS += ../common/ad_datafmt.v
|
||||
INTEL_DEPS += ../common/ad_perfect_shuffle.v
|
||||
INTEL_DEPS += ../common/ad_pnmon.v
|
||||
INTEL_DEPS += ../common/ad_rst.v
|
||||
INTEL_DEPS += ../common/ad_xcvr_rx_if.v
|
||||
INTEL_DEPS += ../common/up_adc_channel.v
|
||||
INTEL_DEPS += ../common/up_adc_common.v
|
||||
INTEL_DEPS += ../common/up_axi.v
|
||||
INTEL_DEPS += ../common/up_clock_mon.v
|
||||
INTEL_DEPS += ../common/up_xfer_cntrl.v
|
||||
INTEL_DEPS += ../common/up_xfer_status.v
|
||||
INTEL_DEPS += ../intel/common/up_clock_mon_constr.sdc
|
||||
INTEL_DEPS += ../intel/common/up_rst_constr.sdc
|
||||
INTEL_DEPS += ../intel/common/up_xfer_cntrl_constr.sdc
|
||||
INTEL_DEPS += ../intel/common/up_xfer_status_constr.sdc
|
||||
INTEL_DEPS += ../jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc.v
|
||||
INTEL_DEPS += ../jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_channel.v
|
||||
INTEL_DEPS += ../jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_core.v
|
||||
INTEL_DEPS += ../jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_deframer.v
|
||||
INTEL_DEPS += ../jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_pnmon.v
|
||||
INTEL_DEPS += ../jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_regmap.v
|
||||
INTEL_DEPS += axi_ad9250_hw.tcl
|
||||
|
||||
include ../scripts/library.mk
|
||||
@@ -0,0 +1,3 @@
|
||||
version:1
|
||||
6d6f64655f636f756e7465727c42617463684d6f6465:1
|
||||
eof:
|
||||
@@ -0,0 +1,6 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<labtools version="1" minor="0"/>
|
||||
@@ -0,0 +1,141 @@
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module axi_ad9250 #(
|
||||
parameter ID = 0,
|
||||
parameter FPGA_TECHNOLOGY = 0,
|
||||
parameter FPGA_FAMILY = 0,
|
||||
parameter SPEED_GRADE = 0,
|
||||
parameter DEV_PACKAGE = 0
|
||||
) (
|
||||
|
||||
// jesd interface
|
||||
// rx_clk is (line-rate/40)
|
||||
|
||||
input rx_clk,
|
||||
input [ 3:0] rx_sof,
|
||||
input rx_valid,
|
||||
input [63:0] rx_data,
|
||||
output rx_ready,
|
||||
|
||||
// dma interface
|
||||
|
||||
output adc_clk,
|
||||
output adc_valid_a,
|
||||
output adc_enable_a,
|
||||
output [31:0] adc_data_a,
|
||||
output adc_valid_b,
|
||||
output adc_enable_b,
|
||||
output [31:0] adc_data_b,
|
||||
input adc_dovf,
|
||||
|
||||
// axi interface
|
||||
|
||||
input s_axi_aclk,
|
||||
input s_axi_aresetn,
|
||||
input s_axi_awvalid,
|
||||
input [11:0] s_axi_awaddr,
|
||||
input [ 2:0] s_axi_awprot,
|
||||
output s_axi_awready,
|
||||
input s_axi_wvalid,
|
||||
input [31:0] s_axi_wdata,
|
||||
input [ 3:0] s_axi_wstrb,
|
||||
output s_axi_wready,
|
||||
output s_axi_bvalid,
|
||||
output [ 1:0] s_axi_bresp,
|
||||
input s_axi_bready,
|
||||
input s_axi_arvalid,
|
||||
input [11:0] s_axi_araddr,
|
||||
input [ 2:0] s_axi_arprot,
|
||||
output s_axi_arready,
|
||||
output s_axi_rvalid,
|
||||
output [31:0] s_axi_rdata,
|
||||
output [ 1:0] s_axi_rresp,
|
||||
input s_axi_rready);
|
||||
|
||||
assign adc_clk = rx_clk;
|
||||
|
||||
ad_ip_jesd204_tpl_adc #(
|
||||
.ID (ID),
|
||||
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
|
||||
.FPGA_FAMILY (FPGA_FAMILY),
|
||||
.SPEED_GRADE (SPEED_GRADE),
|
||||
.DEV_PACKAGE (DEV_PACKAGE),
|
||||
.NUM_LANES (2),
|
||||
.NUM_CHANNELS (2),
|
||||
.SAMPLES_PER_FRAME (1),
|
||||
.CONVERTER_RESOLUTION (14),
|
||||
.BITS_PER_SAMPLE (16),
|
||||
.OCTETS_PER_BEAT (4),
|
||||
.TWOS_COMPLEMENT (1)
|
||||
) i_adc_jesd204 (
|
||||
.link_clk (rx_clk),
|
||||
|
||||
.link_sof (rx_sof),
|
||||
.link_valid (rx_valid),
|
||||
.link_data (rx_data),
|
||||
.link_ready (rx_ready),
|
||||
|
||||
.enable ({adc_enable_b,adc_enable_a}),
|
||||
.adc_valid ({adc_valid_b,adc_valid_a}),
|
||||
.adc_data ({adc_data_b,adc_data_a}),
|
||||
.adc_dovf (adc_dovf),
|
||||
|
||||
.s_axi_aclk (s_axi_aclk),
|
||||
.s_axi_aresetn (s_axi_aresetn),
|
||||
.s_axi_awvalid (s_axi_awvalid),
|
||||
.s_axi_awready (s_axi_awready),
|
||||
.s_axi_awaddr (s_axi_awaddr),
|
||||
.s_axi_awprot (s_axi_awprot),
|
||||
.s_axi_wvalid (s_axi_wvalid),
|
||||
.s_axi_wready(s_axi_wready),
|
||||
.s_axi_wdata (s_axi_wdata),
|
||||
.s_axi_wstrb (s_axi_wstrb),
|
||||
.s_axi_bvalid (s_axi_bvalid),
|
||||
.s_axi_bready (s_axi_bready),
|
||||
.s_axi_bresp (s_axi_bresp),
|
||||
.s_axi_arvalid (s_axi_arvalid),
|
||||
.s_axi_arready (s_axi_arready),
|
||||
.s_axi_araddr (s_axi_araddr),
|
||||
.s_axi_arprot (s_axi_arprot),
|
||||
.s_axi_rvalid (s_axi_rvalid),
|
||||
.s_axi_rready (s_axi_rready),
|
||||
.s_axi_rresp (s_axi_rresp),
|
||||
.s_axi_rdata (s_axi_rdata)
|
||||
);
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,383 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2019.1.3 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Version="7" Minor="40" Path="/home/gatsby/Workspace/Vivado2019.1/ADI/hdl/library/axi_ad9250/axi_ad9250.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="c36858bc681542719bfdde15664f4cd1"/>
|
||||
<Option Name="Part" Val="xc7vx485tffg1157-1"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="BoardPart" Val=""/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../library"/>
|
||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../../ghdl/library"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="DSAVendor" Val="xilinx"/>
|
||||
<Option Name="DSANumComputeUnits" Val="60"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="0"/>
|
||||
<Option Name="WTModelSimExportSim" Val="0"/>
|
||||
<Option Name="WTQuestaExportSim" Val="0"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="0"/>
|
||||
<Option Name="WTRivieraExportSim" Val="0"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
<Option Name="SimTypes" Val="bfm"/>
|
||||
<Option Name="SimTypes" Val="tlm"/>
|
||||
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="31">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/axi_ad9250.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/component.xml">
|
||||
<FileInfo SFType="IPXACT"/>
|
||||
</File>
|
||||
<File Path="$PPRDIR/bd/bd.tcl">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="axi_ad9250"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="IES">
|
||||
<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Xcelium">
|
||||
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="VCS">
|
||||
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="10">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Vivado 12-1790"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="1"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="Evaluation"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="features"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="should"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="NOT"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="be"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="used"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="in"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="production"/>
|
||||
<MsgAttr Name="StringsToMatch" Val="systems."/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="Place 30-73"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="10"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="axi_spi"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val=""/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="11"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY"/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1343"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="2"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="WARNING"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1306"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="3"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="ERROR"/>
|
||||
<MsgAttr Name="Id" Val="BD 41-1276"/>
|
||||
<MsgAttr Name="Severity" Val="CRITICAL WARNING"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="4"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-3656"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="5"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-4623"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="6"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="IP_Flow 19-459"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="7"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Synth 8-3331"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="8"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
</MsgRule>
|
||||
<MsgRule>
|
||||
<MsgAttr Name="RuleType" Val="1"/>
|
||||
<MsgAttr Name="Limit" Val="-1"/>
|
||||
<MsgAttr Name="NewSeverity" Val="INFO"/>
|
||||
<MsgAttr Name="Id" Val="Designutils 20-3303"/>
|
||||
<MsgAttr Name="Severity" Val="ANY"/>
|
||||
<MsgAttr Name="ShowRule" Val="1"/>
|
||||
<MsgAttr Name="RuleSource" Val="2"/>
|
||||
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
||||
<MsgAttr Name="RuleId" Val="9"/>
|
||||
<MsgAttr Name="Note" Val=""/>
|
||||
<MsgAttr Name="Author" Val=""/>
|
||||
<MsgAttr Name="CreatedTimestamp" Val=""/>
|
||||
<MsgAttr Name="StringsToMatch" Val="HDPYFinalizeIO"/>
|
||||
</MsgRule>
|
||||
<Board/>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
<BootPmcSettings Version="1" Minor="0">
|
||||
<Parameters>
|
||||
<Parameter Name="PMC_CDO.ATTRS.LOADADDR" Value="" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_FB_CLK" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_FREQ" Value="300" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_BUS_WIDTH" Value="x1" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.QSPI_DATA_MODE" Value="Single" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_FREQ" Value="200" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_SLOT_TYPE" Value="SD 2.0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD0_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_FREQ" Value="200" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_SLOT_TYPE" Value="SD 2.0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SD1_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSPI_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSPI_FREQ" Value="300" Type="string"/>
|
||||
<Parameter Name="BOOT.USB_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SMAP_ENABLE" Value="0" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.SMAP_DATA_WIDTH" Value="32 Bit" Type="string"/>
|
||||
<Parameter Name="BOOT.PMC.OSC_FREQ" Value="33.333" Type="string"/>
|
||||
<Parameter Name="BOOT.SECONDARY.PCIE_ENABLE" Value="0" Type="string"/>
|
||||
</Parameters>
|
||||
</BootPmcSettings>
|
||||
</Project>
|
||||
@@ -0,0 +1,92 @@
|
||||
|
||||
|
||||
package require qsys
|
||||
package require quartus::device
|
||||
|
||||
source ../scripts/adi_env.tcl
|
||||
source ../scripts/adi_ip_intel.tcl
|
||||
|
||||
set_module_property NAME axi_ad9250
|
||||
set_module_property DESCRIPTION "AXI AD9250 Interface"
|
||||
set_module_property VERSION 1.0
|
||||
set_module_property GROUP "Analog Devices"
|
||||
set_module_property DISPLAY_NAME axi_ad9250
|
||||
set_module_property VALIDATION_CALLBACK info_param_validate
|
||||
|
||||
# files
|
||||
|
||||
add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
|
||||
set_fileset_property quartus_synth TOP_LEVEL axi_ad9250
|
||||
add_fileset_file ad_rst.v VERILOG PATH $ad_hdl_dir/library/common/ad_rst.v
|
||||
add_fileset_file ad_perfect_shuffle.v VERILOG PATH $ad_hdl_dir/library/common/ad_perfect_shuffle.v
|
||||
add_fileset_file ad_pnmon.v VERILOG PATH $ad_hdl_dir/library/common/ad_pnmon.v
|
||||
add_fileset_file ad_datafmt.v VERILOG PATH $ad_hdl_dir/library/common/ad_datafmt.v
|
||||
add_fileset_file up_axi.v VERILOG PATH $ad_hdl_dir/library/common/up_axi.v
|
||||
add_fileset_file up_xfer_cntrl.v VERILOG PATH $ad_hdl_dir/library/common/up_xfer_cntrl.v
|
||||
add_fileset_file up_xfer_status.v VERILOG PATH $ad_hdl_dir/library/common/up_xfer_status.v
|
||||
add_fileset_file up_clock_mon.v VERILOG PATH $ad_hdl_dir/library/common/up_clock_mon.v
|
||||
add_fileset_file up_adc_common.v VERILOG PATH $ad_hdl_dir/library/common/up_adc_common.v
|
||||
add_fileset_file up_adc_channel.v VERILOG PATH $ad_hdl_dir/library/common/up_adc_channel.v
|
||||
add_fileset_file ad_xcvr_rx_if.v VERILOG PATH $ad_hdl_dir/library/common/ad_xcvr_rx_if.v
|
||||
|
||||
add_fileset_file ad_ip_jesd204_adc_pnmon.v VERILOG PATH $ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_pnmon.v
|
||||
add_fileset_file ad_ip_jesd204_adc_channel.v VERILOG PATH $ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_channel.v
|
||||
add_fileset_file ad_ip_jesd204_adc_core.v VERILOG PATH $ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_core.v
|
||||
add_fileset_file ad_ip_jesd204_adc_deframer.v VERILOG PATH $ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_deframer.v
|
||||
add_fileset_file ad_ip_jesd204_adc_regmap.v VERILOG PATH $ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_regmap.v
|
||||
add_fileset_file ad_ip_jesd204_adc.v VERILOG PATH $ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc.v
|
||||
|
||||
add_fileset_file axi_ad9250.v VERILOG PATH axi_ad9250.v TOP_LEVEL_FILE
|
||||
add_fileset_file up_xfer_cntrl_constr.sdc SDC PATH $ad_hdl_dir/library/intel/common/up_xfer_cntrl_constr.sdc
|
||||
add_fileset_file up_xfer_status_constr.sdc SDC PATH $ad_hdl_dir/library/intel/common/up_xfer_status_constr.sdc
|
||||
add_fileset_file up_clock_mon_constr.sdc SDC PATH $ad_hdl_dir/library/intel/common/up_clock_mon_constr.sdc
|
||||
add_fileset_file up_rst_constr.sdc SDC PATH $ad_hdl_dir/library/intel/common/up_rst_constr.sdc
|
||||
|
||||
# parameters
|
||||
|
||||
add_parameter ID INTEGER 0
|
||||
set_parameter_property ID DEFAULT_VALUE 0
|
||||
set_parameter_property ID DISPLAY_NAME ID
|
||||
set_parameter_property ID UNITS None
|
||||
set_parameter_property ID HDL_PARAMETER true
|
||||
|
||||
adi_add_auto_fpga_spec_params
|
||||
|
||||
# axi4 slave
|
||||
|
||||
ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn
|
||||
|
||||
# transceiver interface
|
||||
|
||||
ad_interface clock rx_clk input 1
|
||||
ad_interface signal rx_sof input 4 export
|
||||
|
||||
add_interface if_rx_data avalon_streaming sink
|
||||
add_interface_port if_rx_data rx_data data input 64
|
||||
add_interface_port if_rx_data rx_valid valid input 1
|
||||
add_interface_port if_rx_data rx_ready ready output 1
|
||||
set_interface_property if_rx_data associatedClock if_rx_clk
|
||||
set_interface_property if_rx_data dataBitsPerSymbol 64
|
||||
|
||||
# dma interface
|
||||
|
||||
ad_interface clock adc_clk output 1
|
||||
|
||||
add_interface adc_ch_0 conduit end
|
||||
add_interface_port adc_ch_0 adc_enable_a enable Output 1
|
||||
add_interface_port adc_ch_0 adc_valid_a valid Output 1
|
||||
add_interface_port adc_ch_0 adc_data_a data Output 32
|
||||
|
||||
set_interface_property adc_ch_0 associatedClock if_rx_clk
|
||||
set_interface_property adc_ch_0 associatedReset none
|
||||
|
||||
add_interface adc_ch_1 conduit end
|
||||
add_interface_port adc_ch_1 adc_enable_b enable Output 1
|
||||
add_interface_port adc_ch_1 adc_valid_b valid Output 1
|
||||
add_interface_port adc_ch_1 adc_data_b data Output 32
|
||||
|
||||
set_interface_property adc_ch_1 associatedClock if_rx_clk
|
||||
set_interface_property adc_ch_1 associatedReset none
|
||||
|
||||
ad_interface signal adc_dovf input 1 ovf
|
||||
|
||||
@@ -0,0 +1,28 @@
|
||||
# ip
|
||||
|
||||
source ../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
|
||||
|
||||
adi_ip_create axi_ad9250
|
||||
adi_ip_files axi_ad9250 [list \
|
||||
"axi_ad9250.v" ]
|
||||
|
||||
adi_ip_properties axi_ad9250
|
||||
|
||||
adi_init_bd_tcl
|
||||
adi_ip_bd axi_ad9250 "bd/bd.tcl"
|
||||
|
||||
adi_ip_add_core_dependencies { \
|
||||
analog.com:user:ad_ip_jesd204_tpl_adc:1.0 \
|
||||
}
|
||||
|
||||
set_property driver_value 0 [ipx::get_ports *rx_valid* -of_objects [ipx::current_core]]
|
||||
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
|
||||
|
||||
ipx::infer_bus_interface rx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
|
||||
|
||||
adi_add_auto_fpga_spec_params
|
||||
ipx::create_xgui_files [ipx::current_core]
|
||||
|
||||
ipx::save_core [ipx::current_core]
|
||||
@@ -0,0 +1,47 @@
|
||||
# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!
|
||||
proc init {cellpath otherInfo} {
|
||||
set ip [get_bd_cells $cellpath]
|
||||
|
||||
bd::mark_propagate_only $ip " \
|
||||
DEV_PACKAGE \
|
||||
SPEED_GRADE \
|
||||
FPGA_FAMILY \
|
||||
FPGA_TECHNOLOGY"
|
||||
|
||||
adi_auto_assign_device_spec $cellpath
|
||||
}
|
||||
|
||||
# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)
|
||||
proc adi_auto_assign_device_spec {cellpath} {
|
||||
|
||||
set ip [get_bd_cells $cellpath]
|
||||
set ip_param_list [list_property $ip]
|
||||
set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
|
||||
|
||||
set parent_dir "../"
|
||||
for {set x 1} {$x<=4} {incr x} {
|
||||
set linkname ${ip_path}${parent_dir}scripts/adi_xilinx_device_info_enc.tcl
|
||||
if { [file exists $linkname] } {
|
||||
source ${ip_path}${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl
|
||||
break
|
||||
}
|
||||
append parent_dir "../"
|
||||
}
|
||||
|
||||
# Find predefindes auto assignable parameters
|
||||
foreach i $auto_set_param_list {
|
||||
if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
|
||||
set val [adi_device_spec $cellpath $i]
|
||||
set_property CONFIG.$i $val $ip
|
||||
}
|
||||
}
|
||||
|
||||
# Find predefindes auto assignable/overwritable parameters
|
||||
foreach i $auto_set_param_list_overwritable {
|
||||
if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
|
||||
set val [adi_device_spec $cellpath $i]
|
||||
set_property CONFIG.$i $val $ip
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,2 @@
|
||||
CLEAN_TARGET += bd
|
||||
CLEAN_TARGET += temporary_case_dependencies.mk
|
||||
@@ -0,0 +1,88 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||
ipgui::add_param $IPINST -name "ID" -parent ${Page_0}
|
||||
#Adding Group
|
||||
set FPGA_info [ipgui::add_group $IPINST -name "FPGA info" -parent ${Page_0}]
|
||||
ipgui::add_param $IPINST -name "FPGA_TECHNOLOGY" -parent ${FPGA_info} -widget comboBox
|
||||
ipgui::add_param $IPINST -name "FPGA_FAMILY" -parent ${FPGA_info} -widget comboBox
|
||||
ipgui::add_param $IPINST -name "SPEED_GRADE" -parent ${FPGA_info} -widget comboBox
|
||||
ipgui::add_param $IPINST -name "DEV_PACKAGE" -parent ${FPGA_info} -widget comboBox
|
||||
|
||||
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } {
|
||||
# Procedure called to update DEV_PACKAGE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } {
|
||||
# Procedure called to validate DEV_PACKAGE
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } {
|
||||
# Procedure called to update FPGA_FAMILY when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } {
|
||||
# Procedure called to validate FPGA_FAMILY
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } {
|
||||
# Procedure called to update FPGA_TECHNOLOGY when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } {
|
||||
# Procedure called to validate FPGA_TECHNOLOGY
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } {
|
||||
# Procedure called to update ID when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } {
|
||||
# Procedure called to validate ID
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } {
|
||||
# Procedure called to update SPEED_GRADE when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } {
|
||||
# Procedure called to validate SPEED_GRADE
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.FPGA_TECHNOLOGY { MODELPARAM_VALUE.FPGA_TECHNOLOGY PARAM_VALUE.FPGA_TECHNOLOGY } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.FPGA_TECHNOLOGY}] ${MODELPARAM_VALUE.FPGA_TECHNOLOGY}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.FPGA_FAMILY { MODELPARAM_VALUE.FPGA_FAMILY PARAM_VALUE.FPGA_FAMILY } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.FPGA_FAMILY}] ${MODELPARAM_VALUE.FPGA_FAMILY}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.SPEED_GRADE { MODELPARAM_VALUE.SPEED_GRADE PARAM_VALUE.SPEED_GRADE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.SPEED_GRADE}] ${MODELPARAM_VALUE.SPEED_GRADE}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DEV_PACKAGE { MODELPARAM_VALUE.DEV_PACKAGE PARAM_VALUE.DEV_PACKAGE } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DEV_PACKAGE}] ${MODELPARAM_VALUE.DEV_PACKAGE}
|
||||
}
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user