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update dl814_z7 netlist, add project of 001 & 002, modify 005 bootimage
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@@ -74,11 +74,12 @@ module rx_pre_process
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input [ADC_WIDTH-1:0] rx_ch3_q ,
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input [ADC_WIDTH-1:0] rx_ch4_i ,
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input [ADC_WIDTH-1:0] rx_ch4_q ,
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// input channel phase
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input [PHASE_WIDTH-1:0] phase_ch1 ,
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input [PHASE_WIDTH-1:0] phase_ch2 ,
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input [PHASE_WIDTH-1:0] phase_ch3 ,
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input [PHASE_WIDTH-1:0] phase_ch4 ,
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input [PHASE_WIDTH-1:0] phase_ch1 , // sync to [sys_clk]
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input [PHASE_WIDTH-1:0] phase_ch2 , // sync to [sys_clk]
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input [PHASE_WIDTH-1:0] phase_ch3 , // sync to [sys_clk]
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input [PHASE_WIDTH-1:0] phase_ch4 , // sync to [sys_clk]
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// ad9361 calibration interface
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input ad9361_1_cal_start ,
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@@ -90,10 +91,10 @@ module rx_pre_process
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input ad9361_recal ,
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// nulling algorithm interface
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input hop_flag_in_phy ,
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input sync_flag_phy ,
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input lcmv_en_phy ,
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output hop_flag_out ,
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input hop_flag_in_phy , // sync to [sys_clk_phy], hop flag that drives lcmv algorithm and hop data buffering
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input sync_flag_phy , // sync to [sys_clk_phy], 1: sync segment; 0: guard/data segment
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input lcmv_en_phy , // sync to [sys_clk_phy], 1: lcmv; 0: das (delay and sum)
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output hop_flag_out , // sync to [sys_clk], hop flag that drives physical receiver
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output accor_stream_valid , // sync to [clk_96m]
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output accor_stream_data , // sync to [clk_96m]
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