diff --git a/common/truncate_manual.v b/common/truncate_manual.v
new file mode 100644
index 00000000..eb967614
--- /dev/null
+++ b/common/truncate_manual.v
@@ -0,0 +1,43 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//
+// Create Date: 04/21/2023 11:37:14 AM
+// Design Name:
+// Module Name: truncate_manual
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module truncate_manual
+#(
+    DATA_I_WIDTH = 30,
+    DATA_O_WIDTH = 12
+)
+(
+    input clk,
+    input rst,
+
+    input [DATA_I_WIDTH-1 : 0] data_in,
+    input data_in_valid,
+
+    input [$clog2(DATA_I_WIDTH)-1 : 0] trunc_pos,
+
+    output [DATA_O_WIDTH-1 : 0] data_out,
+    output data_out_valid
+);
+
+assign data_out = data_in[trunc_pos -: DATA_O_WIDTH];
+
+endmodule
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/data/20230417-接收数据及权矢量/iladata_rx.csv b/projects/dl814_k7/dl814_k7_cal_coarse/data/20230417-接收数据及权矢量/iladata_rx.csv
old mode 100755
new mode 100644
index e8e982ab..1ef0dea2
--- a/projects/dl814_k7/dl814_k7_cal_coarse/data/20230417-接收数据及权矢量/iladata_rx.csv
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/data/20230417-接收数据及权矢量/iladata_rx.csv
@@ -1,3 +1,3 @@
 version https://git-lfs.github.com/spec/v1
-oid sha256:5d2a53da1fd413ecb5c59bb663c758f29cbe475bf38362e7bcc92e80f213a1f9
-size 9489183
+oid sha256:03a99ac4456eaef04869b9416d6a2c6aee782cb9a7293c5317bb8a5015848fe6
+size 553713
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/data/20230417-接收数据及权矢量/iladata_rx_test.csv b/projects/dl814_k7/dl814_k7_cal_coarse/data/20230417-接收数据及权矢量/iladata_rx_test.csv
new file mode 100755
index 00000000..e8e982ab
--- /dev/null
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/data/20230417-接收数据及权矢量/iladata_rx_test.csv
@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:5d2a53da1fd413ecb5c59bb663c758f29cbe475bf38362e7bcc92e80f213a1f9
+size 9489183
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/data/20230417-接收数据及权矢量/iladata_weight.csv b/projects/dl814_k7/dl814_k7_cal_coarse/data/20230417-接收数据及权矢量/iladata_weight.csv
index 172bafba..9647b2cf 100644
--- a/projects/dl814_k7/dl814_k7_cal_coarse/data/20230417-接收数据及权矢量/iladata_weight.csv
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/data/20230417-接收数据及权矢量/iladata_weight.csv
@@ -1,3 +1,3 @@
 version https://git-lfs.github.com/spec/v1
-oid sha256:2b2536694788ce3ca1ab40dd55f0e91426473e87b26e86badb408e7e4abbc945
-size 1817670
+oid sha256:24590cdc8969ef8d93c4ef768fb63aa4351b1f0616e42515240746dfa87f81e1
+size 40002
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/data/20230417-接收数据及权矢量/iladata_weight_test.csv b/projects/dl814_k7/dl814_k7_cal_coarse/data/20230417-接收数据及权矢量/iladata_weight_test.csv
new file mode 100644
index 00000000..172bafba
--- /dev/null
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/data/20230417-接收数据及权矢量/iladata_weight_test.csv
@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:2b2536694788ce3ca1ab40dd55f0e91426473e87b26e86badb408e7e4abbc945
+size 1817670
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/data/20230417-接收数据及权矢量/untitled.asv b/projects/dl814_k7/dl814_k7_cal_coarse/data/20230417-接收数据及权矢量/untitled_for_test.m
similarity index 74%
rename from projects/dl814_k7/dl814_k7_cal_coarse/data/20230417-接收数据及权矢量/untitled.asv
rename to projects/dl814_k7/dl814_k7_cal_coarse/data/20230417-接收数据及权矢量/untitled_for_test.m
index 0e7344ee..1255146f 100644
--- a/projects/dl814_k7/dl814_k7_cal_coarse/data/20230417-接收数据及权矢量/untitled.asv
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/data/20230417-接收数据及权矢量/untitled_for_test.m
@@ -33,5 +33,17 @@ for i=1:32
   end
 end
 
-weight_stream_data_ind
+weight_stream_data_index = 1;
+flag = 1;
+
+while (flag)
+  weight_stream_data_str = num2str(weight_stream_data((1:32)+weight_stream_data_index-1)');
+  tmp = bin2dec(erase(convertCharsToStrings(weight_stream_data_str)," "));
+  if (tmp == hex2dec("7E7E7E7E"))
+    flag = 0;
+  else 
+    weight_stream_data_index = weight_stream_data_index + 1;
+  end
+end
+
 
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/data/20230423-天线幅相测试-不同频点/iladata_25.0G_1-1.csv b/projects/dl814_k7/dl814_k7_cal_coarse/data/20230423-天线幅相测试-不同频点/iladata_25.0G_1-1.csv
new file mode 100644
index 00000000..f5d83ea9
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+++ b/projects/dl814_k7/dl814_k7_cal_coarse/data/20230423-天线幅相测试-不同频点/iladata_25.0G_1-1.csv
@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
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+size 541069
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/data/20230423-天线幅相测试-不同频点/iladata_25.0G_1-2.csv b/projects/dl814_k7/dl814_k7_cal_coarse/data/20230423-天线幅相测试-不同频点/iladata_25.0G_1-2.csv
new file mode 100644
index 00000000..b70214ae
--- /dev/null
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/data/20230423-天线幅相测试-不同频点/iladata_25.0G_1-2.csv
@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
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+size 561550
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/data/20230423-天线幅相测试-不同频点/iladata_25.0G_1-3.csv b/projects/dl814_k7/dl814_k7_cal_coarse/data/20230423-天线幅相测试-不同频点/iladata_25.0G_1-3.csv
new file mode 100644
index 00000000..72c370aa
--- /dev/null
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/data/20230423-天线幅相测试-不同频点/iladata_25.0G_1-3.csv
@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
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diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/data/20230423-天线幅相测试-不同频点/iladata_25.1G_1-1.csv b/projects/dl814_k7/dl814_k7_cal_coarse/data/20230423-天线幅相测试-不同频点/iladata_25.1G_1-1.csv
new file mode 100644
index 00000000..332fc2a0
--- /dev/null
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/data/20230423-天线幅相测试-不同频点/iladata_25.1G_1-1.csv
@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
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diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/data/20230423-天线幅相测试-不同频点/iladata_25.1G_1-2.csv b/projects/dl814_k7/dl814_k7_cal_coarse/data/20230423-天线幅相测试-不同频点/iladata_25.1G_1-2.csv
new file mode 100644
index 00000000..87a03992
--- /dev/null
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/data/20230423-天线幅相测试-不同频点/iladata_25.1G_1-2.csv
@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
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diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/data/20230423-天线幅相测试-不同频点/iladata_25.1G_1-3.csv b/projects/dl814_k7/dl814_k7_cal_coarse/data/20230423-天线幅相测试-不同频点/iladata_25.1G_1-3.csv
new file mode 100644
index 00000000..e7afa634
--- /dev/null
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/data/20230423-天线幅相测试-不同频点/iladata_25.1G_1-3.csv
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new file mode 100644
index 00000000..d3fafabf
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@@ -0,0 +1,3 @@
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new file mode 100644
index 00000000..cbfe5b52
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@@ -0,0 +1,3 @@
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new file mode 100644
index 00000000..0269017b
--- /dev/null
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/data/20230423-天线幅相测试-不同频点/iladata_25.2G_1-3.csv
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new file mode 100644
index 00000000..9f39f266
--- /dev/null
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/data/20230423-天线幅相测试-不同频点/iladata_25.3G_1-1.csv
@@ -0,0 +1,3 @@
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new file mode 100644
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new file mode 100644
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new file mode 100644
index 00000000..c4fe9892
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@@ -0,0 +1,3 @@
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new file mode 100644
index 00000000..ae417902
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new file mode 100644
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+++ b/projects/dl814_k7/dl814_k7_cal_coarse/data/20230423-天线幅相测试-不同频点/iladata_25.5G_1-1.csv
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new file mode 100644
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new file mode 100644
index 00000000..0295f6ce
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diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/data/20230423-天线幅相测试-不同频点/iladata_26.6G_1-2.csv b/projects/dl814_k7/dl814_k7_cal_coarse/data/20230423-天线幅相测试-不同频点/iladata_26.6G_1-2.csv
new file mode 100644
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diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/data/20230423-天线幅相测试-不同频点/iladata_26.6G_1-3.csv b/projects/dl814_k7/dl814_k7_cal_coarse/data/20230423-天线幅相测试-不同频点/iladata_26.6G_1-3.csv
new file mode 100644
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diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/data/20230423-天线幅相测试-不同频点/iladata_26.7G_1-1.csv b/projects/dl814_k7/dl814_k7_cal_coarse/data/20230423-天线幅相测试-不同频点/iladata_26.7G_1-1.csv
new file mode 100644
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diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/data/20230423-天线幅相测试-不同频点/iladata_26.7G_1-2.csv b/projects/dl814_k7/dl814_k7_cal_coarse/data/20230423-天线幅相测试-不同频点/iladata_26.7G_1-2.csv
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diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/data/20230423-天线幅相测试-不同频点/iladata_26.8G_1-1.csv b/projects/dl814_k7/dl814_k7_cal_coarse/data/20230423-天线幅相测试-不同频点/iladata_26.8G_1-1.csv
new file mode 100644
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diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/data/20230423-天线幅相测试-不同频点/iladata_26.8G_1-2.csv b/projects/dl814_k7/dl814_k7_cal_coarse/data/20230423-天线幅相测试-不同频点/iladata_26.8G_1-2.csv
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diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/data/20230423-天线幅相测试-不同频点/iladata_26.8G_1-3.csv b/projects/dl814_k7/dl814_k7_cal_coarse/data/20230423-天线幅相测试-不同频点/iladata_26.8G_1-3.csv
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diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/data/20230423-天线幅相测试-不同频点/iladata_26.9G_1-1.csv b/projects/dl814_k7/dl814_k7_cal_coarse/data/20230423-天线幅相测试-不同频点/iladata_26.9G_1-1.csv
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diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/data/20230423-天线幅相测试-不同频点/iladata_27.0G_1-1.csv b/projects/dl814_k7/dl814_k7_cal_coarse/data/20230423-天线幅相测试-不同频点/iladata_27.0G_1-1.csv
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+version https://git-lfs.github.com/spec/v1
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diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/data/20230423-天线幅相测试-不同频点/iladata_27.0G_1-2.csv b/projects/dl814_k7/dl814_k7_cal_coarse/data/20230423-天线幅相测试-不同频点/iladata_27.0G_1-2.csv
new file mode 100644
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diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/data/20230423-天线幅相测试-不同频点/iladata_27.0G_1-3.csv b/projects/dl814_k7/dl814_k7_cal_coarse/data/20230423-天线幅相测试-不同频点/iladata_27.0G_1-3.csv
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+version https://git-lfs.github.com/spec/v1
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diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/data/20230423-天线幅相测试-不同频点/multiBitCorrInterSampleDiff.asv b/projects/dl814_k7/dl814_k7_cal_coarse/data/20230423-天线幅相测试-不同频点/multiBitCorrInterSampleDiff.asv
new file mode 100644
index 00000000..6c82eb5a
--- /dev/null
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/data/20230423-天线幅相测试-不同频点/multiBitCorrInterSampleDiff.asv
@@ -0,0 +1,204 @@
+%% File Header/文件说明
+%
+% Beamforming with phased array derives signal characteristics from phase
+% differences between sensors. Therefore the amplitude-phase consistence is
+% vital to phased systems.
+%
+% The script analyzes the amp-phase relations of ILA captured data, the format
+% of which is square-shaped pseudorandorm bit sequence. Each channel is
+% processed seperately with different frequency shifts and different optimum
+% sampling points. The estimation of amplitude and phase are based on
+% acculumated correlation peaks.
+%
+clc; clear;
+%% initial parameters/初始参数
+interp = 8; % interpolation factor
+channelNum = 4;
+dataLen = 8192;
+fs = 48e6;
+dataFile = [...
+"iladata_25.0G_1-1.csv",...
+"iladata_25.0G_1-2.csv",...
+"iladata_25.0G_1-3.csv",...
+"iladata_25.1G_1-1.csv",...
+"iladata_25.1G_1-2.csv",...
+"iladata_25.1G_1-3.csv",...
+"iladata_25.2G_1-1.csv",...
+"iladata_25.2G_1-2.csv",...
+"iladata_25.2G_1-3.csv",...
+"iladata_25.3G_1-1.csv",...
+"iladata_25.3G_1-2.csv",...
+"iladata_25.3G_1-3.csv",...
+"iladata_25.4G_1-1.csv",...
+"iladata_25.4G_1-2.csv",...
+"iladata_25.4G_1-3.csv",...
+"iladata_25.5G_1-1.csv",...
+"iladata_25.5G_1-2.csv",...
+"iladata_25.5G_1-3.csv",...
+"iladata_25.6G_1-1.csv",...
+"iladata_25.6G_1-2.csv",...
+"iladata_25.6G_1-3.csv",...
+"iladata_25.7G_1-1.csv",...
+"iladata_25.7G_1-2.csv",...
+"iladata_25.7G_1-3.csv",...
+"iladata_25.8G_1-1.csv",...
+"iladata_25.8G_1-2.csv",...
+"iladata_25.8G_1-3.csv",...
+"iladata_25.9G_1-1.csv",...
+"iladata_25.9G_1-2.csv",...
+"iladata_25.9G_1-3.csv",...
+"iladata_26.0G_1-1.csv",...
+"iladata_26.0G_1-2.csv",...
+"iladata_26.0G_1-3.csv",...
+"iladata_26.1G_1-1.csv",...
+"iladata_26.1G_1-2.csv",...
+"iladata_26.1G_1-3.csv",...
+"iladata_26.2G_1-1.csv",...
+"iladata_26.2G_1-2.csv",...
+"iladata_26.2G_1-3.csv",...
+"iladata_26.3G_1-1.csv",...
+"iladata_26.3G_1-2.csv",...
+"iladata_26.3G_1-3.csv",...
+"iladata_26.4G_1-1.csv",...
+"iladata_26.4G_1-2.csv",...
+"iladata_26.4G_1-3.csv",...
+"iladata_26.5G_1-1.csv",...
+"iladata_26.5G_1-2.csv",...
+"iladata_26.5G_1-3.csv",...
+"iladata_26.6G_1-1.csv",...
+"iladata_26.6G_1-2.csv",...
+"iladata_26.6G_1-3.csv",...
+"iladata_26.7G_1-1.csv",...
+"iladata_26.7G_1-2.csv",...
+"iladata_26.8G_1-1.csv",...
+"iladata_26.8G_1-2.csv",...
+"iladata_26.8G_1-3.csv",...
+"iladata_26.9G_1-1.csv",...
+"iladata_26.9G_1-2.csv",...
+"iladata_26.9G_1-3.csv",...
+"iladata_27.0G_1-1.csv",...
+"iladata_27.0G_1-2.csv",...
+"iladata_27.0G_1-3.csv",...  
+];
+dataFileNum = length(dataFile);
+
+% standard pn sequence
+pnSequence = comm.PNSequence('Polynomial','x^7+x^6+1', ...
+  'InitialConditions',[zeros(1,6),1],'SamplesPerFrame',2^7-1);
+PRBS7 = pnSequence();
+PRBS7_polar = 1-2*[PRBS7;0];
+
+chipLen = length(PRBS7_polar);    % pn chip length
+symNum = dataLen/chipLen/interp;  % total symbol number
+symNumPerAccum = 1;               % symbol nbumber of each accumulation
+accNum = symNum/symNumPerAccum;   % total accumulation numbers, i.e. peak numbers
+
+ampEstSymMax   = zeros(dataFileNum,channelNum);
+ampEstSymMin   = zeros(dataFileNum,channelNum);
+ampEstSymAvg   = zeros(dataFileNum,channelNum);
+angleEstSymMax = zeros(dataFileNum,channelNum);
+angleEstSymMin = zeros(dataFileNum,channelNum);
+angleEstSymAvg = zeros(dataFileNum,channelNum);
+
+ampEstSymMaxList   = strings(dataFileNum+1,channelNum+1);
+ampEstSymMinList   = strings(dataFileNum+1,channelNum+1);
+ampEstSymAvgList   = strings(dataFileNum+1,channelNum+1);
+angleEstSymMaxList = strings(dataFileNum+1,channelNum+1);
+angleEstSymMinList = strings(dataFileNum+1,channelNum+1);
+angleEstSymAvgList = strings(dataFileNum+1,channelNum+1);
+
+ampEstSymMaxList(1,:)   = ["Amp Max Value", "ch1", "ch2", "ch3", "ch4"];
+ampEstSymMinList(1,:)   = ["Amp Min Value", "ch1", "ch2", "ch3", "ch4"];
+ampEstSymAvgList(1,:)   = ["Amp Avg Value", "ch1", "ch2", "ch3", "ch4"];
+angleEstSymMaxList(1,:) = ["Angle Max Value", "ch1", "ch2", "ch3", "ch4"];
+angleEstSymMinList(1,:) = ["Angle Min Value", "ch1", "ch2", "ch3", "ch4"];
+angleEstSymAvgList(1,:) = ["Angle Avg Value", "ch1", "ch2", "ch3", "ch4"];
+
+ampEstSymMaxList(2:end,1)   = dataFile;
+ampEstSymMinList(2:end,1)   = dataFile;
+ampEstSymAvgList(2:end,1)   = dataFile;
+angleEstSymMaxList(2:end,1) = dataFile;
+angleEstSymMinList(2:end,1) = dataFile;
+angleEstSymAvgList(2:end,1) = dataFile;
+
+for dataFileIndex = 1:dataFileNum
+  disp(dataFile(dataFileIndex)); 
+
+  %% data analysis
+  
+  % read data, and swap ch1 and ch2, because loop data locate at ch2 and ch4
+  rxdata = readmatrix(dataFile(dataFileIndex));
+  seqRx(:,1) = (rxdata(:, 6) + 1i*rxdata(:, 7)).';
+  seqRx(:,2) = (rxdata(:, 4) + 1i*rxdata(:, 5)).';
+  seqRx(:,3) = (rxdata(:, 8) + 1i*rxdata(:, 9)).';
+  seqRx(:,4) = (rxdata(:,10) + 1i*rxdata(:,11)).';
+  
+  % compensate frequecny deviation and downsample at optimum sample position based
+  % on the varience of constellation
+  [seqRxDown,fd,samplePos] = suqareShapeFreqEst(seqRx,interp,fs,-25000,-21000,5);
+  
+  % split [seqRxDown] into multiple groups, each group contains several symbols to
+  % be correlated with PRBS7 and accumulated
+  seqRxDownSplit = reshape(seqRxDown(1:dataLen/interp,:),chipLen*symNumPerAccum, ...
+    accNum,channelNum);
+  
+  seqRxAcc = zeros(chipLen,accNum,channelNum);
+  desiredPnt = zeros(accNum,channelNum);
+  ampEstSym = zeros(accNum,channelNum);
+  angleEstSym = zeros(accNum,channelNum);
+  
+  for i = 1:accNum
+    for j = 1:channelNum
+      % correlation & multi-symbol accumulation
+      groupCorrAcc = sum(...
+        reshape(...
+          conv(...
+            flip(seqRxDownSplit(:,i,j)),...
+            PRBS7_polar,'same'),...
+          chipLen,symNumPerAccum),...
+        2)';
+      seqRxAcc(:,i,j) = groupCorrAcc;
+      % peak position
+      desiredPnt(i,j) = groupCorrAcc(abs(groupCorrAcc)==max(abs(groupCorrAcc)));
+    end
+  end
+  
+  for i = 1:channelNum
+    ampEstSym(:,i) = abs(desiredPnt(:,i))./abs(desiredPnt(:,1));
+    angleEstSym(:,i) = mod((angle(desiredPnt(:,i))-angle(desiredPnt(:,1)))/pi*180,360);
+  end
+
+  ampEstSymMax(dataFileIndex,:) =  max(ampEstSym);
+  ampEstSymMin(dataFileIndex,:) =  min(ampEstSym);
+  ampEstSymAvg(dataFileIndex,:) = mean(ampEstSym);
+  angleEstSymMax(dataFileIndex,:) =  max(angleEstSym);
+  angleEstSymMin(dataFileIndex,:) =  min(angleEstSym);
+  angleEstSymAvg(dataFileIndex,:) = mean(angleEstSym);
+
+  ampEstSymMaxList(dataFileIndex+1,2:end)   = string(ampEstSymMax(dataFileIndex,:));
+  ampEstSymMinList(dataFileIndex+1,2:end)   = string(ampEstSymMin(dataFileIndex,:));
+  ampEstSymAvgList(dataFileIndex+1,2:end)   = string(ampEstSymAvg(dataFileIndex,:));
+  angleEstSymMaxList(dataFileIndex+1,2:end) = string(angleEstSymMax(dataFileIndex,:));
+  angleEstSymMinList(dataFileIndex+1,2:end) = string(angleEstSymMin(dataFileIndex,:));
+  angleEstSymAvgList(dataFileIndex+1,2:end) = string(angleEstSymAvg(dataFileIndex,:));
+
+end
+
+
+
+%% figures
+% figure(1);
+% 
+% subplot(121);
+% plot(ampEstSym);
+% legend({"ch1","ch2","ch3","ch4"});
+% title("Amplitude Estimation");
+% ylim([min(ampEstSym,[],'all')-0.2,max(ampEstSym,[],'all')+0.2]);
+% grid on; grid minor;
+% 
+% subplot(122);
+% plot(angleEstSym);
+% legend({"ch1","ch2","ch3","ch4"});
+% title("Angle Estimation");
+% ylim([-10,370]);
+% grid on; grid minor;
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/data/20230423-天线幅相测试-不同频点/multiBitCorrInterSampleDiff.m b/projects/dl814_k7/dl814_k7_cal_coarse/data/20230423-天线幅相测试-不同频点/multiBitCorrInterSampleDiff.m
new file mode 100644
index 00000000..76316c8b
--- /dev/null
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/data/20230423-天线幅相测试-不同频点/multiBitCorrInterSampleDiff.m
@@ -0,0 +1,199 @@
+%% File Header/文件说明
+%
+% Beamforming with phased array derives signal characteristics from phase
+% differences between sensors. Therefore the amplitude-phase consistence is
+% vital to phased systems.
+%
+% The script analyzes the amp-phase relations of ILA captured data, the format
+% of which is square-shaped pseudorandorm bit sequence. Each channel is
+% processed seperately with different frequency shifts and different optimum
+% sampling points. The estimation of amplitude and phase are based on
+% acculumated correlation peaks.
+%
+clc; clear;
+%% initial parameters/初始参数
+interp = 8; % interpolation factor
+channelNum = 4;
+dataLen = 8192;
+fs = 48e6;
+dataFile = [...
+"iladata_25.0G_1-1.csv",...
+"iladata_25.0G_1-2.csv",...
+"iladata_25.0G_1-3.csv",...
+"iladata_25.1G_1-1.csv",...
+"iladata_25.1G_1-2.csv",...
+"iladata_25.1G_1-3.csv",...
+"iladata_25.2G_1-1.csv",...
+"iladata_25.2G_1-2.csv",...
+"iladata_25.2G_1-3.csv",...
+"iladata_25.3G_1-1.csv",...
+"iladata_25.3G_1-2.csv",...
+"iladata_25.3G_1-3.csv",...
+"iladata_25.4G_1-1.csv",...
+"iladata_25.4G_1-2.csv",...
+"iladata_25.4G_1-3.csv",...
+"iladata_25.5G_1-1.csv",...
+"iladata_25.5G_1-2.csv",...
+"iladata_25.5G_1-3.csv",...
+"iladata_25.6G_1-1.csv",...
+"iladata_25.6G_1-2.csv",...
+"iladata_25.6G_1-3.csv",...
+"iladata_25.7G_1-1.csv",...
+"iladata_25.7G_1-2.csv",...
+"iladata_25.7G_1-3.csv",...
+"iladata_25.8G_1-1.csv",...
+"iladata_25.8G_1-2.csv",...
+"iladata_25.8G_1-3.csv",...
+"iladata_25.9G_1-1.csv",...
+"iladata_25.9G_1-2.csv",...
+"iladata_25.9G_1-3.csv",...
+"iladata_26.0G_1-1.csv",...
+"iladata_26.0G_1-2.csv",...
+"iladata_26.0G_1-3.csv",...
+"iladata_26.1G_1-1.csv",...
+"iladata_26.1G_1-2.csv",...
+"iladata_26.1G_1-3.csv",...
+"iladata_26.2G_1-1.csv",...
+"iladata_26.2G_1-2.csv",...
+"iladata_26.2G_1-3.csv",...
+"iladata_26.3G_1-1.csv",...
+"iladata_26.3G_1-2.csv",...
+"iladata_26.3G_1-3.csv",...
+"iladata_26.4G_1-1.csv",...
+"iladata_26.4G_1-2.csv",...
+"iladata_26.4G_1-3.csv",...
+"iladata_26.5G_1-1.csv",...
+"iladata_26.5G_1-2.csv",...
+"iladata_26.5G_1-3.csv",...
+"iladata_26.6G_1-1.csv",...
+"iladata_26.6G_1-2.csv",...
+"iladata_26.6G_1-3.csv",...
+"iladata_26.7G_1-1.csv",...
+"iladata_26.7G_1-2.csv",...
+"iladata_26.8G_1-1.csv",...
+"iladata_26.8G_1-2.csv",...
+"iladata_26.8G_1-3.csv",...
+"iladata_26.9G_1-1.csv",...
+"iladata_26.9G_1-2.csv",...
+"iladata_26.9G_1-3.csv",...
+"iladata_27.0G_1-1.csv",...
+"iladata_27.0G_1-2.csv",...
+"iladata_27.0G_1-3.csv",...  
+];
+dataFileNum = length(dataFile);
+
+% standard pn sequence
+pnSequence = comm.PNSequence('Polynomial','x^7+x^6+1', ...
+  'InitialConditions',[zeros(1,6),1],'SamplesPerFrame',2^7-1);
+PRBS7 = pnSequence();
+PRBS7_polar = 1-2*[PRBS7;0];
+
+chipLen = length(PRBS7_polar);    % pn chip length
+symNum = dataLen/chipLen/interp;  % total symbol number
+symNumPerAccum = 1;               % symbol nbumber of each accumulation
+accNum = symNum/symNumPerAccum;   % total accumulation numbers, i.e. peak numbers
+
+ampEstSymMax   = zeros(dataFileNum,channelNum);
+ampEstSymMin   = zeros(dataFileNum,channelNum);
+ampEstSymAvg   = zeros(dataFileNum,channelNum);
+angleEstSymMax = zeros(dataFileNum,channelNum);
+angleEstSymMin = zeros(dataFileNum,channelNum);
+angleEstSymAvg = zeros(dataFileNum,channelNum);
+
+ampEstSymMaxList   = strings(dataFileNum+1,channelNum+1);
+ampEstSymMinList   = strings(dataFileNum+1,channelNum+1);
+ampEstSymAvgList   = strings(dataFileNum+1,channelNum+1);
+angleEstSymMaxList = strings(dataFileNum+1,channelNum+1);
+angleEstSymMinList = strings(dataFileNum+1,channelNum+1);
+angleEstSymAvgList = strings(dataFileNum+1,channelNum+1);
+
+ampEstSymMaxList(1,:)   = ["Amp Max Value", "ch1", "ch2", "ch3", "ch4"];
+ampEstSymMinList(1,:)   = ["Amp Min Value", "ch1", "ch2", "ch3", "ch4"];
+ampEstSymAvgList(1,:)   = ["Amp Avg Value", "ch1", "ch2", "ch3", "ch4"];
+angleEstSymMaxList(1,:) = ["Angle Max Value", "ch1", "ch2", "ch3", "ch4"];
+angleEstSymMinList(1,:) = ["Angle Min Value", "ch1", "ch2", "ch3", "ch4"];
+angleEstSymAvgList(1,:) = ["Angle Avg Value", "ch1", "ch2", "ch3", "ch4"];
+
+ampEstSymMaxList(2:end,1)   = dataFile;
+ampEstSymMinList(2:end,1)   = dataFile;
+ampEstSymAvgList(2:end,1)   = dataFile;
+angleEstSymMaxList(2:end,1) = dataFile;
+angleEstSymMinList(2:end,1) = dataFile;
+angleEstSymAvgList(2:end,1) = dataFile;
+
+for dataFileIndex = 1:dataFileNum
+  disp(dataFile(dataFileIndex)); 
+
+  %% data analysis
+  
+  % read data, and swap ch1 and ch2, because loop data locate at ch2 and ch4
+  rxdata = readmatrix(dataFile(dataFileIndex));
+  seqRx(:,1) = (rxdata(:, 6) + 1i*rxdata(:, 7)).';
+  seqRx(:,2) = (rxdata(:, 4) + 1i*rxdata(:, 5)).';
+  seqRx(:,3) = (rxdata(:, 8) + 1i*rxdata(:, 9)).';
+  seqRx(:,4) = (rxdata(:,10) + 1i*rxdata(:,11)).';
+  
+  % compensate frequecny deviation and downsample at optimum sample position based
+  % on the varience of constellation
+  [seqRxDown,fd,samplePos] = suqareShapeFreqEst(seqRx,interp,fs,-25000,-21000,5);
+  
+  % split [seqRxDown] into multiple groups, each group contains several symbols to
+  % be correlated with PRBS7 and accumulated
+  seqRxDownSplit = reshape(seqRxDown(1:dataLen/interp,:),chipLen*symNumPerAccum, ...
+    accNum,channelNum);
+  
+  seqRxAcc = zeros(chipLen,accNum,channelNum);
+  desiredPnt = zeros(accNum,channelNum);
+  ampEstSym = zeros(accNum,channelNum);
+  angleEstSym = zeros(accNum,channelNum);
+  
+  for i = 1:accNum
+    for j = 1:channelNum
+      % correlation & multi-symbol accumulation
+      groupCorrAcc = sum(reshape(conv(flip(seqRxDownSplit(:,i,j)), ...
+        PRBS7_polar,'same'),chipLen,symNumPerAccum),2)';
+      seqRxAcc(:,i,j) = groupCorrAcc;
+      % peak position
+      desiredPnt(i,j) = groupCorrAcc(abs(groupCorrAcc)==max(abs(groupCorrAcc)));
+    end
+  end
+  
+  for i = 1:channelNum
+    ampEstSym(:,i) = abs(desiredPnt(:,i))./abs(desiredPnt(:,1));
+    angleEstSym(:,i) = mod((angle(desiredPnt(:,i))-angle(desiredPnt(:,1)))/pi*180,360);
+  end
+
+  ampEstSymMax(dataFileIndex,:) =  max(ampEstSym);
+  ampEstSymMin(dataFileIndex,:) =  min(ampEstSym);
+  ampEstSymAvg(dataFileIndex,:) = mean(ampEstSym);
+  angleEstSymMax(dataFileIndex,:) =  max(angleEstSym);
+  angleEstSymMin(dataFileIndex,:) =  min(angleEstSym);
+  angleEstSymAvg(dataFileIndex,:) = mean(angleEstSym);
+
+  ampEstSymMaxList(dataFileIndex+1,2:end)   = string(ampEstSymMax(dataFileIndex,:));
+  ampEstSymMinList(dataFileIndex+1,2:end)   = string(ampEstSymMin(dataFileIndex,:));
+  ampEstSymAvgList(dataFileIndex+1,2:end)   = string(ampEstSymAvg(dataFileIndex,:));
+  angleEstSymMaxList(dataFileIndex+1,2:end) = string(angleEstSymMax(dataFileIndex,:));
+  angleEstSymMinList(dataFileIndex+1,2:end) = string(angleEstSymMin(dataFileIndex,:));
+  angleEstSymAvgList(dataFileIndex+1,2:end) = string(angleEstSymAvg(dataFileIndex,:));
+
+end
+
+
+
+%% figures
+% figure(1);
+% 
+% subplot(121);
+% plot(ampEstSym);
+% legend({"ch1","ch2","ch3","ch4"});
+% title("Amplitude Estimation");
+% ylim([min(ampEstSym,[],'all')-0.2,max(ampEstSym,[],'all')+0.2]);
+% grid on; grid minor;
+% 
+% subplot(122);
+% plot(angleEstSym);
+% legend({"ch1","ch2","ch3","ch4"});
+% title("Angle Estimation");
+% ylim([-10,370]);
+% grid on; grid minor;
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/data/20230423-天线幅相测试-不同频点/suqareShapeFreqEst.m b/projects/dl814_k7/dl814_k7_cal_coarse/data/20230423-天线幅相测试-不同频点/suqareShapeFreqEst.m
new file mode 100644
index 00000000..bb33a13f
--- /dev/null
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/data/20230423-天线幅相测试-不同频点/suqareShapeFreqEst.m
@@ -0,0 +1,50 @@
+function [dataOut, fdTarget, samplePosTarget] = suqareShapeFreqEst(dataIn, interp, fs, fmin, fmax, fd)
+%suqareShapeFreqEst - 利用星座图的集中程度在一定频率范围内使用频率步进估计方波成形信号的频偏
+%
+% data - input complex data, row vector
+% dataLen - data length
+% interp - interpolation rate
+% fs - sampling rate, in Herts
+% fmin - minimum estimation frequency, in Herts
+% fmax - maximum estimation frequency, in Herts
+% fd - estimation frequency step, in Herts
+  
+% dimension
+[dataLen,channelNum] = size(dataIn);
+
+freqList = fmin:fd:fmax; 
+freqNum = length(freqList);
+varRecord = zeros(freqNum,interp);
+
+dataOut = zeros(dataLen/interp,channelNum);
+fdTarget = zeros(channelNum,1);
+samplePosTarget = zeros(channelNum,1);
+
+for channel = 1:channelNum
+
+  for freq = 1:freqNum
+
+    % carrier
+    cxr = exp(-1i*2*pi*freqList(freq)/fs*(0:dataLen-1)');
+
+    % apply frequency shift onto input data
+    seqRx = dataIn(:,channel).*cxr;
+  
+    for samplePos = 0:interp-1
+      seqRxDown = downsample(seqRx,interp,samplePos); % 下采样
+      seqRxDownQuaterOne = abs(real(seqRxDown)) + 1i*abs(imag(seqRxDown)); % 集中到第一象限
+      varRecord(freq,samplePos+1) = var(seqRxDownQuaterOne);
+    end
+  
+  end
+
+  [fdIndex, samplePosIndex] = find(varRecord==min(min(varRecord)));
+  fdTarget(channel) = freqList(fdIndex);
+  samplePosTarget(channel) = samplePosIndex-1;
+
+  cxrTarget = exp(-1i*2*pi*fdTarget(channel)/fs*(0:dataLen-1)');
+  seqRxTarget = dataIn(:,channel).*cxrTarget;
+  dataOut(:,channel) = downsample(seqRxTarget,interp,samplePosTarget(channel));
+end
+
+end
\ No newline at end of file
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/data/20230423-天线幅相测试-不同频点/数据说明.md b/projects/dl814_k7/dl814_k7_cal_coarse/data/20230423-天线幅相测试-不同频点/数据说明.md
new file mode 100644
index 00000000..ce577bdc
--- /dev/null
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/data/20230423-天线幅相测试-不同频点/数据说明.md
@@ -0,0 +1,11 @@
+# 数据说明
+
+1. iladata_ad9361_pure_noise.csv: 调零板 AD9361 单板噪声。
+
+2. iladata_ad9361_ant_noise.csv: 调零板射频接收噪声。
+
+3. iladata_ad9361_pure_noise_A-B.csv: 调零板 AD9361 单板噪声，第 A 次上电过程中第 B 次采集结果。
+
+> 1~3 AD9361 配置均为 48Msps，BW 40MHz，外部本振，使用 AD9516-3 的 VCO 分频时钟。
+
+4. iladata_814_1t2r_48msps_bwxxm_xxx_lo_A-B.csv：调零板 AD9361 单板噪声，48Msps，BW xxMHz，ext_lo 表示外部本振，int_lo 表示内部本振，第 A 次上电过程中第 B 次采集结果。
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_manual_ctrl/sim/vio_manual_ctrl.v b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_manual_ctrl/sim/vio_manual_ctrl.v
index 493f196e..05906ce5 100644
--- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_manual_ctrl/sim/vio_manual_ctrl.v
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_manual_ctrl/sim/vio_manual_ctrl.v
@@ -53,7 +53,8 @@ probe_out0,
 probe_out1,
 probe_out2,
 probe_out3,
-probe_out4
+probe_out4,
+probe_out5
 );
 
 input clk;
@@ -63,6 +64,7 @@ output reg [0 : 0] probe_out1 = 'h0 ;
 output reg [31 : 0] probe_out2 = 'h00000000 ;
 output reg [1 : 0] probe_out3 = 'h3 ;
 output reg [3 : 0] probe_out4 = 'h0 ;
+output reg [0 : 0] probe_out5 = 'h0 ;
 
 
 endmodule
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl.veo b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl.veo
index 39fbf855..550ac454 100644
--- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl.veo
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl.veo
@@ -60,7 +60,8 @@ vio_manual_ctrl your_instance_name (
   .probe_out1(probe_out1),  // output wire [0 : 0] probe_out1
   .probe_out2(probe_out2),  // output wire [31 : 0] probe_out2
   .probe_out3(probe_out3),  // output wire [1 : 0] probe_out3
-  .probe_out4(probe_out4)  // output wire [3 : 0] probe_out4
+  .probe_out4(probe_out4),  // output wire [3 : 0] probe_out4
+  .probe_out5(probe_out5)  // output wire [0 : 0] probe_out5
 );
 // INST_TAG_END ------ End INSTANTIATION Template ---------
 
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl.vho b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl.vho
index 877bb0cb..1c2c6619 100644
--- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl.vho
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl.vho
@@ -59,7 +59,8 @@ COMPONENT vio_manual_ctrl
     probe_out1 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
     probe_out2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
     probe_out3 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
-    probe_out4 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
+    probe_out4 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+    probe_out5 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
   );
 END COMPONENT;
 -- COMP_TAG_END ------ End COMPONENT Declaration ------------
@@ -75,7 +76,8 @@ your_instance_name : vio_manual_ctrl
     probe_out1 => probe_out1,
     probe_out2 => probe_out2,
     probe_out3 => probe_out3,
-    probe_out4 => probe_out4
+    probe_out4 => probe_out4,
+    probe_out5 => probe_out5
   );
 -- INST_TAG_END ------ End INSTANTIATION Template ---------
 
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_sim_netlist.v b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_sim_netlist.v
index 44d0af55..fd04dbe0 100644
--- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_sim_netlist.v
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_sim_netlist.v
@@ -1,3 +1,3 @@
 version https://git-lfs.github.com/spec/v1
-oid sha256:1ef789b139dd21314f2f64ed27ffe456fe9f3780bffc1b839629a84a6d76d369
-size 352468
+oid sha256:a01fafc69a1a3ba5410b7a42027cc78e47f5b15cfdae5003802be620f113aeb6
+size 355493
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_sim_netlist.vhdl b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_sim_netlist.vhdl
index 88e89736..b34a8cc6 100644
--- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_sim_netlist.vhdl
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_sim_netlist.vhdl
@@ -1,3 +1,3 @@
 version https://git-lfs.github.com/spec/v1
-oid sha256:60f900616e80d391d0f1ca17c739ffeb62b08557d1f784a2224cbc94a84eb147
-size 633949
+oid sha256:824bcac0396eea134efa41f3102c915ef47b199e1c4072d91d827c19f22fc999
+size 637257
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_stub.v b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_stub.v
index 34b2261b..a1f4f379 100644
--- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_stub.v
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_stub.v
@@ -1,7 +1,7 @@
 // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
 // --------------------------------------------------------------------------------
 // Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
-// Date        : Wed Apr 19 12:03:53 2023
+// Date        : Sun Apr 23 16:19:11 2023
 // Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
 // Command     : write_verilog -force -mode synth_stub
 //               /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.v
@@ -15,12 +15,13 @@
 // Please paste the declaration into a Verilog source file or add the file as an additional source.
 (* X_CORE_INFO = "vio,Vivado 2019.1.3" *)
 module vio_manual_ctrl(clk, probe_out0, probe_out1, probe_out2, 
-  probe_out3, probe_out4)
-/* synthesis syn_black_box black_box_pad_pin="clk,probe_out0[1:0],probe_out1[0:0],probe_out2[31:0],probe_out3[1:0],probe_out4[3:0]" */;
+  probe_out3, probe_out4, probe_out5)
+/* synthesis syn_black_box black_box_pad_pin="clk,probe_out0[1:0],probe_out1[0:0],probe_out2[31:0],probe_out3[1:0],probe_out4[3:0],probe_out5[0:0]" */;
   input clk;
   output [1:0]probe_out0;
   output [0:0]probe_out1;
   output [31:0]probe_out2;
   output [1:0]probe_out3;
   output [3:0]probe_out4;
+  output [0:0]probe_out5;
 endmodule
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_stub.vhdl b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_stub.vhdl
index 087749f8..20780871 100644
--- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_stub.vhdl
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_stub.vhdl
@@ -1,7 +1,7 @@
 -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
 -- --------------------------------------------------------------------------------
 -- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
--- Date        : Wed Apr 19 12:03:53 2023
+-- Date        : Sun Apr 23 16:19:11 2023
 -- Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
 -- Command     : write_vhdl -force -mode synth_stub
 --               /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.vhdl
@@ -19,7 +19,8 @@ entity vio_manual_ctrl is
     probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 );
     probe_out2 : out STD_LOGIC_VECTOR ( 31 downto 0 );
     probe_out3 : out STD_LOGIC_VECTOR ( 1 downto 0 );
-    probe_out4 : out STD_LOGIC_VECTOR ( 3 downto 0 )
+    probe_out4 : out STD_LOGIC_VECTOR ( 3 downto 0 );
+    probe_out5 : out STD_LOGIC_VECTOR ( 0 to 0 )
   );
 
 end vio_manual_ctrl;
@@ -28,7 +29,7 @@ architecture stub of vio_manual_ctrl is
 attribute syn_black_box : boolean;
 attribute black_box_pad_pin : string;
 attribute syn_black_box of stub : architecture is true;
-attribute black_box_pad_pin of stub : architecture is "clk,probe_out0[1:0],probe_out1[0:0],probe_out2[31:0],probe_out3[1:0],probe_out4[3:0]";
+attribute black_box_pad_pin of stub : architecture is "clk,probe_out0[1:0],probe_out1[0:0],probe_out2[31:0],probe_out3[1:0],probe_out4[3:0],probe_out5[0:0]";
 attribute X_CORE_INFO : string;
 attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3";
 begin
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/README.txt b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/README.txt
index 2cc3d67e..f1e61954 100644
--- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/README.txt
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/README.txt
@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Wed Apr 19 12:03:35 CST 2023
+# Generated by export_simulation on Sun Apr 23 16:18:53 CST 2023
 #
 ################################################################################
 
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/compile.do b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/compile.do
index 1f6495c2..daf63fe1 100644
--- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/compile.do
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/compile.do
@@ -8,7 +8,6 @@ vmap xil_defaultlib activehdl/xil_defaultlib
 vmap xpm activehdl/xpm
 
 vlog -work xil_defaultlib  -sv2k12 "+incdir+../../../ip/vio_manual_ctrl/hdl/verilog" "+incdir+../../../ip/vio_manual_ctrl/hdl" \
-"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
 "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
 
 vcom -work xpm -93 \
@@ -17,6 +16,7 @@ vcom -work xpm -93 \
 vlog -work xil_defaultlib  -v2k5 "+incdir+../../../ip/vio_manual_ctrl/hdl/verilog" "+incdir+../../../ip/vio_manual_ctrl/hdl" \
 "../../../ip/vio_manual_ctrl/sim/vio_manual_ctrl.v" \
 
+
 vlog -work xil_defaultlib \
 "glbl.v"
 
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/file_info.txt b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/file_info.txt
index f5242d57..0d9ab1d7 100644
--- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/file_info.txt
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/file_info.txt
@@ -1,4 +1,3 @@
-xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl"
 xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl"
 xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl"
 vio_manual_ctrl.v,verilog,xil_defaultlib,../../../ip/vio_manual_ctrl/sim/vio_manual_ctrl.v,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl"
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/vio_manual_ctrl.sh b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/vio_manual_ctrl.sh
index 71fa89d3..e2932229 100755
--- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/vio_manual_ctrl.sh
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/vio_manual_ctrl.sh
@@ -9,7 +9,7 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Wed Apr 19 12:03:35 CST 2023
+# Generated by Vivado on Sun Apr 23 16:18:53 CST 2023
 # SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/ies/README.txt b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/ies/README.txt
index a8967b35..ced5c5e1 100644
--- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/ies/README.txt
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/ies/README.txt
@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Wed Apr 19 12:03:35 CST 2023
+# Generated by export_simulation on Sun Apr 23 16:18:53 CST 2023
 #
 ################################################################################
 
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/ies/file_info.txt b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/ies/file_info.txt
index f5242d57..0d9ab1d7 100644
--- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/ies/file_info.txt
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/ies/file_info.txt
@@ -1,4 +1,3 @@
-xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl"
 xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl"
 xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl"
 vio_manual_ctrl.v,verilog,xil_defaultlib,../../../ip/vio_manual_ctrl/sim/vio_manual_ctrl.v,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl"
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/ies/run.f b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/ies/run.f
index 36f5e07d..f6cdd3c7 100644
--- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/ies/run.f
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/ies/run.f
@@ -1,5 +1,4 @@
 -makelib ies_lib/xil_defaultlib -sv \
-  "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
   "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
 -endlib
 -makelib ies_lib/xpm \
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/ies/vio_manual_ctrl.sh b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/ies/vio_manual_ctrl.sh
index de4a5529..7bf82c40 100755
--- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/ies/vio_manual_ctrl.sh
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/ies/vio_manual_ctrl.sh
@@ -9,7 +9,7 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Wed Apr 19 12:03:35 CST 2023
+# Generated by Vivado on Sun Apr 23 16:18:53 CST 2023
 # SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/README.txt b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/README.txt
index 2cc3d67e..f1e61954 100644
--- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/README.txt
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/README.txt
@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Wed Apr 19 12:03:35 CST 2023
+# Generated by export_simulation on Sun Apr 23 16:18:53 CST 2023
 #
 ################################################################################
 
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/vio_manual_ctrl.sh b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/vio_manual_ctrl.sh
index 84ea4824..790747c7 100755
--- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/vio_manual_ctrl.sh
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/vio_manual_ctrl.sh
@@ -9,7 +9,7 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Wed Apr 19 12:03:35 CST 2023
+# Generated by Vivado on Sun Apr 23 16:18:53 CST 2023
 # SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/README.txt b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/README.txt
index 2cc3d67e..f1e61954 100644
--- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/README.txt
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/README.txt
@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Wed Apr 19 12:03:35 CST 2023
+# Generated by export_simulation on Sun Apr 23 16:18:53 CST 2023
 #
 ################################################################################
 
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/compile.do b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/compile.do
index a2f2d23e..733b0014 100644
--- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/compile.do
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/compile.do
@@ -8,7 +8,6 @@ vmap xil_defaultlib questa_lib/msim/xil_defaultlib
 vmap xpm questa_lib/msim/xpm
 
 vlog -work xil_defaultlib -64 -sv "+incdir+../../../ip/vio_manual_ctrl/hdl/verilog" "+incdir+../../../ip/vio_manual_ctrl/hdl" \
-"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
 "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
 
 vcom -work xpm -64 -93 \
@@ -17,6 +16,7 @@ vcom -work xpm -64 -93 \
 vlog -work xil_defaultlib -64 "+incdir+../../../ip/vio_manual_ctrl/hdl/verilog" "+incdir+../../../ip/vio_manual_ctrl/hdl" \
 "../../../ip/vio_manual_ctrl/sim/vio_manual_ctrl.v" \
 
+
 vlog -work xil_defaultlib \
 "glbl.v"
 
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/file_info.txt b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/file_info.txt
index f5242d57..0d9ab1d7 100644
--- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/file_info.txt
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/file_info.txt
@@ -1,4 +1,3 @@
-xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl"
 xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl"
 xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl"
 vio_manual_ctrl.v,verilog,xil_defaultlib,../../../ip/vio_manual_ctrl/sim/vio_manual_ctrl.v,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl"
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/vio_manual_ctrl.sh b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/vio_manual_ctrl.sh
index 760b7daa..678c7c11 100755
--- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/vio_manual_ctrl.sh
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/vio_manual_ctrl.sh
@@ -9,7 +9,7 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Wed Apr 19 12:03:35 CST 2023
+# Generated by Vivado on Sun Apr 23 16:18:53 CST 2023
 # SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/README.txt b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/README.txt
index 2cc3d67e..f1e61954 100644
--- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/README.txt
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/README.txt
@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Wed Apr 19 12:03:35 CST 2023
+# Generated by export_simulation on Sun Apr 23 16:18:53 CST 2023
 #
 ################################################################################
 
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/compile.do b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/compile.do
index 8710eef1..c4528b78 100644
--- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/compile.do
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/compile.do
@@ -8,7 +8,6 @@ vmap xil_defaultlib riviera/xil_defaultlib
 vmap xpm riviera/xpm
 
 vlog -work xil_defaultlib  -sv2k12 "+incdir+../../../ip/vio_manual_ctrl/hdl/verilog" "+incdir+../../../ip/vio_manual_ctrl/hdl" \
-"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
 "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
 
 vcom -work xpm -93 \
@@ -17,6 +16,7 @@ vcom -work xpm -93 \
 vlog -work xil_defaultlib  -v2k5 "+incdir+../../../ip/vio_manual_ctrl/hdl/verilog" "+incdir+../../../ip/vio_manual_ctrl/hdl" \
 "../../../ip/vio_manual_ctrl/sim/vio_manual_ctrl.v" \
 
+
 vlog -work xil_defaultlib \
 "glbl.v"
 
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/file_info.txt b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/file_info.txt
index f5242d57..0d9ab1d7 100644
--- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/file_info.txt
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/file_info.txt
@@ -1,4 +1,3 @@
-xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl"
 xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl"
 xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl"
 vio_manual_ctrl.v,verilog,xil_defaultlib,../../../ip/vio_manual_ctrl/sim/vio_manual_ctrl.v,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl"
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/vio_manual_ctrl.sh b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/vio_manual_ctrl.sh
index a762810a..7057353c 100755
--- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/vio_manual_ctrl.sh
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/vio_manual_ctrl.sh
@@ -9,7 +9,7 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Wed Apr 19 12:03:35 CST 2023
+# Generated by Vivado on Sun Apr 23 16:18:53 CST 2023
 # SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/vcs/README.txt b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/vcs/README.txt
index 2cc3d67e..f1e61954 100644
--- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/vcs/README.txt
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/vcs/README.txt
@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Wed Apr 19 12:03:35 CST 2023
+# Generated by export_simulation on Sun Apr 23 16:18:53 CST 2023
 #
 ################################################################################
 
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/vcs/vio_manual_ctrl.sh b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/vcs/vio_manual_ctrl.sh
index 0f86940b..403c4271 100755
--- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/vcs/vio_manual_ctrl.sh
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/vcs/vio_manual_ctrl.sh
@@ -9,7 +9,7 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Wed Apr 19 12:03:35 CST 2023
+# Generated by Vivado on Sun Apr 23 16:18:53 CST 2023
 # SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xcelium/README.txt b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xcelium/README.txt
index a8967b35..ced5c5e1 100644
--- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xcelium/README.txt
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xcelium/README.txt
@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Wed Apr 19 12:03:35 CST 2023
+# Generated by export_simulation on Sun Apr 23 16:18:53 CST 2023
 #
 ################################################################################
 
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xcelium/file_info.txt b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xcelium/file_info.txt
index f5242d57..0d9ab1d7 100644
--- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xcelium/file_info.txt
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xcelium/file_info.txt
@@ -1,4 +1,3 @@
-xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl"
 xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl"
 xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl"
 vio_manual_ctrl.v,verilog,xil_defaultlib,../../../ip/vio_manual_ctrl/sim/vio_manual_ctrl.v,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl"
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xcelium/run.f b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xcelium/run.f
index f65ce74a..e7d20cbc 100644
--- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xcelium/run.f
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xcelium/run.f
@@ -1,5 +1,4 @@
 -makelib xcelium_lib/xil_defaultlib -sv \
-  "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
   "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
 -endlib
 -makelib xcelium_lib/xpm \
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xcelium/vio_manual_ctrl.sh b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xcelium/vio_manual_ctrl.sh
index d9258930..15534909 100755
--- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xcelium/vio_manual_ctrl.sh
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xcelium/vio_manual_ctrl.sh
@@ -9,7 +9,7 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Wed Apr 19 12:03:35 CST 2023
+# Generated by Vivado on Sun Apr 23 16:18:53 CST 2023
 # SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xsim/README.txt b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xsim/README.txt
index 2cc3d67e..f1e61954 100644
--- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xsim/README.txt
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xsim/README.txt
@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Wed Apr 19 12:03:35 CST 2023
+# Generated by export_simulation on Sun Apr 23 16:18:53 CST 2023
 #
 ################################################################################
 
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xsim/vio_manual_ctrl.sh b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xsim/vio_manual_ctrl.sh
index 94d6a51c..450ff7df 100755
--- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xsim/vio_manual_ctrl.sh
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xsim/vio_manual_ctrl.sh
@@ -9,7 +9,7 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Wed Apr 19 12:03:35 CST 2023
+# Generated by Vivado on Sun Apr 23 16:18:53 CST 2023
 # SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/1f2022300f50ed09/1f2022300f50ed09.xci b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/1f2022300f50ed09/1f2022300f50ed09.xci
new file mode 100644
index 00000000..32b6da74
--- /dev/null
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/1f2022300f50ed09/1f2022300f50ed09.xci
@@ -0,0 +1,810 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>ipcache</spirit:library>
+  <spirit:name>1f2022300f50ed09</spirit:name>
+  <spirit:version>0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>vio_manual_ctrl</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="vio" spirit:version="3.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SIGNAL_CLOCK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_EN_PROBE_IN_ACTIVITY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_EN_SYNCHRONIZATION">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_PROBE_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_PROBE_OUT">6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN0_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN100_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN101_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN102_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN103_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN104_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN105_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN106_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN107_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN108_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN109_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN10_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN110_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN111_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN112_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN113_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN114_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN115_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN116_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN117_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN118_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN119_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN11_WIDTH">1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN121_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN122_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN123_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN124_WIDTH">1</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT9_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">vio_manual_ctrl</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k410t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
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+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
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+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHRUNTIME">14</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Unknown</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">20</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/1f2022300f50ed09/vio_manual_ctrl.dcp b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/1f2022300f50ed09/vio_manual_ctrl.dcp
new file mode 100644
index 00000000..be7681a2
--- /dev/null
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/1f2022300f50ed09/vio_manual_ctrl.dcp
@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:85b96f3fd48d5a53bc6c64876c2fb42b53c830f62affbc15338b20705ac160ba
+size 145700
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@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:2002d4c2e7161f8ea1d24180209085e1e4ac8c5bd001afdf89beae2eef71892d
+size 355776
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new file mode 100755
index 00000000..62c9ef2b
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+version https://git-lfs.github.com/spec/v1
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diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/1f2022300f50ed09/vio_manual_ctrl_stub.v b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/1f2022300f50ed09/vio_manual_ctrl_stub.v
new file mode 100755
index 00000000..5c5bbb6e
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+++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/1f2022300f50ed09/vio_manual_ctrl_stub.v
@@ -0,0 +1,27 @@
+// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
+// Date        : Sun Apr 23 16:19:11 2023
+// Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
+// Command     : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+//               decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_manual_ctrl_stub.v
+// Design      : vio_manual_ctrl
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7k410tffg900-2
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* X_CORE_INFO = "vio,Vivado 2019.1.3" *)
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe_out0, probe_out1, probe_out2, 
+  probe_out3, probe_out4, probe_out5)
+/* synthesis syn_black_box black_box_pad_pin="clk,probe_out0[1:0],probe_out1[0:0],probe_out2[31:0],probe_out3[1:0],probe_out4[3:0],probe_out5[0:0]" */;
+  input clk;
+  output [1:0]probe_out0;
+  output [0:0]probe_out1;
+  output [31:0]probe_out2;
+  output [1:0]probe_out3;
+  output [3:0]probe_out4;
+  output [0:0]probe_out5;
+endmodule
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/1f2022300f50ed09/vio_manual_ctrl_stub.vhdl b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/1f2022300f50ed09/vio_manual_ctrl_stub.vhdl
new file mode 100755
index 00000000..22df82f3
--- /dev/null
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/1f2022300f50ed09/vio_manual_ctrl_stub.vhdl
@@ -0,0 +1,36 @@
+-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
+-- Date        : Sun Apr 23 16:19:11 2023
+-- Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
+-- Command     : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+--               decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_manual_ctrl_stub.vhdl
+-- Design      : vio_manual_ctrl
+-- Purpose     : Stub declaration of top-level module interface
+-- Device      : xc7k410tffg900-2
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
+  Port ( 
+    clk : in STD_LOGIC;
+    probe_out0 : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 );
+    probe_out2 : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    probe_out3 : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    probe_out4 : out STD_LOGIC_VECTOR ( 3 downto 0 );
+    probe_out5 : out STD_LOGIC_VECTOR ( 0 to 0 )
+  );
+
+end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
+
+architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "clk,probe_out0[1:0],probe_out1[0:0],probe_out2[31:0],probe_out3[1:0],probe_out4[3:0],probe_out5[0:0]";
+attribute X_CORE_INFO : string;
+attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3";
+begin
+end;
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/gui_handlers.wdf b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/gui_handlers.wdf
index f2506efc..c7815ad5 100644
--- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/gui_handlers.wdf
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/gui_handlers.wdf
@@ -1,10 +1,10 @@
 version:1
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diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/java_command_handlers.wdf b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/java_command_handlers.wdf
index 1b873048..33bcc252 100644
--- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/java_command_handlers.wdf
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/java_command_handlers.wdf
@@ -7,6 +7,6 @@ version:1
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index ccef59f4..4e6ebcf8 100644
--- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/project.wpc
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/project.wpc
@@ -1,3 +1,3 @@
 version:1
-6d6f64655f636f756e7465727c4755494d6f6465:9
+6d6f64655f636f756e7465727c4755494d6f6465:10
 eof:
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/synthesis.wdf b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/synthesis.wdf
index 7a2206ae..c199495b 100644
--- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/synthesis.wdf
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/synthesis.wdf
@@ -1,7 +1,7 @@
 version:1
 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:7863376b343130746666673930302d32:00:00
 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:696c615f72785f7072655f737973:00:00
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:76696f5f6d616e75616c5f6374726c:00:00
 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e636c7564655f64697273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67656e65726963:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d766572696c6f675f646566696e65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
@@ -33,7 +33,7 @@ version:1
 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d617373657274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
-73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a353873:00:00
-73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:323331372e3630394d42:00:00
-73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3839392e3231354d42:00:00
-eof:2246763269
+73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a313073:00:00
+73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:323037392e3638344d42:00:00
+73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3637362e3830314d42:00:00
+eof:3750586285
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/webtalk_pa.xml b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/webtalk_pa.xml
index e6f981bc..5c1a9ff6 100644
--- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/webtalk_pa.xml
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/webtalk_pa.xml
@@ -3,7 +3,7 @@
 <!--The data in this file is primarily intended for consumption by Xilinx tools.
 The structure and the elements are likely to change over the next few releases.
 This means code written to parse this file will need to be revisited each subsequent release.-->
-<application name="pa" timeStamp="Wed Apr 19 19:54:43 2023">
+<application name="pa" timeStamp="Sun Apr 23 17:37:09 2023">
 <section name="Project Information" visible="false">
 <property name="ProjectID" value="ce818763e31a4de8ac7850431f15fb5a" type="ProjectID"/>
 <property name="ProjectIteration" value="1" type="ProjectIteration"/>
@@ -25,16 +25,16 @@ This means code written to parse this file will need to be revisited each subseq
 <property name="ManageCompositeTargets" value="2" type="JavaHandler"/>
 <property name="NewIPLocationHandler" value="1" type="JavaHandler"/>
 <property name="OpenIPLocationHandler" value="1" type="JavaHandler"/>
-<property name="OpenPreviousIPHandler" value="8" type="JavaHandler"/>
-<property name="RecustomizeCore" value="17" type="JavaHandler"/>
+<property name="OpenPreviousIPHandler" value="9" type="JavaHandler"/>
+<property name="RecustomizeCore" value="18" type="JavaHandler"/>
 </item>
 <item name="Gui Handlers">
 <property name="BaseDialog_CANCEL" value="7" type="GuiHandlerData"/>
-<property name="BaseDialog_OK" value="26" type="GuiHandlerData"/>
+<property name="BaseDialog_OK" value="27" type="GuiHandlerData"/>
 <property name="CopyIPHandler_DESTINATION_IP_NAME" value="3" type="GuiHandlerData"/>
 <property name="CoreTreeTablePanel_CORE_TREE_TABLE" value="4" type="GuiHandlerData"/>
 <property name="ExpRunTreePanel_EXP_RUN_TREE_TABLE" value="9" type="GuiHandlerData"/>
-<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="96" type="GuiHandlerData"/>
+<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="98" type="GuiHandlerData"/>
 <property name="GettingStartedView_MANAGE_IP" value="2" type="GuiHandlerData"/>
 <property name="GettingStartedView_START_USING_VIVADO_WITH_IP_CATALOG" value="1" type="GuiHandlerData"/>
 <property name="HACGCCoeFileWidget_BROWSE" value="1" type="GuiHandlerData"/>
@@ -51,15 +51,15 @@ This means code written to parse this file will need to be revisited each subseq
 <property name="PACommandNames_GENERATE_COMPOSITE_FILE" value="2" type="GuiHandlerData"/>
 <property name="PACommandNames_OPEN_IP_LOCATION" value="1" type="GuiHandlerData"/>
 <property name="RemoveSourcesDialog_ALSO_DELETE" value="6" type="GuiHandlerData"/>
-<property name="SimpleOutputProductDialog_GENERATE_OUTPUT_PRODUCTS_IMMEDIATELY" value="13" type="GuiHandlerData"/>
+<property name="SimpleOutputProductDialog_GENERATE_OUTPUT_PRODUCTS_IMMEDIATELY" value="14" type="GuiHandlerData"/>
 <property name="SrcChooserPanel_ADD_CONFIGURABLE_IP_FILES" value="4" type="GuiHandlerData"/>
 <property name="SrcMenu_IP_DOCUMENTATION" value="4" type="GuiHandlerData"/>
-<property name="SyntheticaGettingStartedView_RECENT_IP_LOCATIONS" value="8" type="GuiHandlerData"/>
+<property name="SyntheticaGettingStartedView_RECENT_IP_LOCATIONS" value="9" type="GuiHandlerData"/>
 </item>
 <item name="Other">
-<property name="GuiMode" value="98" type="GuiMode"/>
+<property name="GuiMode" value="109" type="GuiMode"/>
 <property name="BatchMode" value="0" type="BatchMode"/>
-<property name="TclMode" value="66" type="TclMode"/>
+<property name="TclMode" value="76" type="TclMode"/>
 </item>
 </section>
 </application>
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_12.xml b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_12.xml
new file mode 100644
index 00000000..78e31a19
--- /dev/null
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_12.xml
@@ -0,0 +1,8 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="vio_manual_ctrl_synth_1" LaunchDir="/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+	<Parameters>
+		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+	</Parameters>
+</Runs>
+
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/rom_hop_data_synth_1/gen_run.xml b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/rom_hop_data_synth_1/gen_run.xml
index c5bda25b..cb43132a 100644
--- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/rom_hop_data_synth_1/gen_run.xml
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/rom_hop_data_synth_1/gen_run.xml
@@ -1,7 +1,7 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <GenRun Id="rom_hop_data_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1681709915">
-  <File Type="RDS-UTIL-PB" Name="rom_hop_data_utilization_synth.pb"/>
   <File Type="RDS-UTIL" Name="rom_hop_data_utilization_synth.rpt"/>
+  <File Type="RDS-UTIL-PB" Name="rom_hop_data_utilization_synth.pb"/>
   <File Type="RDS-RDS" Name="rom_hop_data.vds"/>
   <File Type="RDS-DCP" Name="rom_hop_data.dcp"/>
   <File Type="PA-TCL" Name="rom_hop_data.tcl"/>
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/gen_run.xml b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/gen_run.xml
index 1822c528..1151cb63 100644
--- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/gen_run.xml
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/gen_run.xml
@@ -1,7 +1,7 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <GenRun Id="vio_hop_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1681877041">
-  <File Type="RDS-UTIL" Name="vio_hop_utilization_synth.rpt"/>
   <File Type="RDS-UTIL-PB" Name="vio_hop_utilization_synth.pb"/>
+  <File Type="RDS-UTIL" Name="vio_hop_utilization_synth.rpt"/>
   <File Type="RDS-RDS" Name="vio_hop.vds"/>
   <File Type="RDS-DCP" Name="vio_hop.dcp"/>
   <File Type="PA-TCL" Name="vio_hop.tcl"/>
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/.vivado.begin.rst b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/.vivado.begin.rst
index e79ea38a..98aca3b5 100644
--- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/.vivado.begin.rst
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/.vivado.begin.rst
@@ -1,5 +1,5 @@
 <?xml version="1.0"?>
 <ProcessHandle Version="1" Minor="0">
-    <Process Command="vivado" Owner="josh" Host="JOSH-ASUS-Z690" Pid="1955893" HostCore="20" HostMemory="65589000">
+    <Process Command="vivado" Owner="josh" Host="JOSH-ASUS-Z690" Pid="2442084" HostCore="20" HostMemory="65589000">
     </Process>
 </ProcessHandle>
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/gen_run.xml b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/gen_run.xml
index 04497055..fec7bef0 100644
--- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/gen_run.xml
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/gen_run.xml
@@ -1,20 +1,23 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<GenRun Id="vio_manual_ctrl_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1681877015">
-  <File Type="REPORTS-TCL" Name="vio_manual_ctrl_reports.tcl"/>
-  <File Type="PA-TCL" Name="vio_manual_ctrl.tcl"/>
+<GenRun Id="vio_manual_ctrl_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1682237933">
+  <File Type="VDS-TIMING-PB" Name="vio_manual_ctrl_timing_summary_synth.pb"/>
+  <File Type="VDS-TIMINGSUMMARY" Name="vio_manual_ctrl_timing_summary_synth.rpt"/>
   <File Type="RDS-DCP" Name="vio_manual_ctrl.dcp"/>
-  <File Type="RDS-RDS" Name="vio_manual_ctrl.vds"/>
   <File Type="RDS-UTIL-PB" Name="vio_manual_ctrl_utilization_synth.pb"/>
   <File Type="RDS-UTIL" Name="vio_manual_ctrl_utilization_synth.rpt"/>
+  <File Type="RDS-PROPCONSTRS" Name="vio_manual_ctrl_drc_synth.rpt"/>
+  <File Type="RDS-RDS" Name="vio_manual_ctrl.vds"/>
+  <File Type="REPORTS-TCL" Name="vio_manual_ctrl_reports.tcl"/>
+  <File Type="PA-TCL" Name="vio_manual_ctrl.tcl"/>
   <FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/vio_manual_ctrl">
-    <File Path="$PPRDIR/../vio_manual_ctrl/vio_manual_ctrl.xci">
+    <File Path="$PPRDIR/../vio_manual_ctrl.xcix">
       <FileInfo>
         <Attr Name="UsedIn" Val="synthesis"/>
         <Attr Name="UsedIn" Val="implementation"/>
         <Attr Name="UsedIn" Val="simulation"/>
       </FileInfo>
     </File>
-    <File Path="$PPRDIR/../vio_manual_ctrl.xcix">
+    <File Path="$PPRDIR/../vio_manual_ctrl/vio_manual_ctrl.xci">
       <FileInfo>
         <Attr Name="UsedIn" Val="synthesis"/>
         <Attr Name="UsedIn" Val="implementation"/>
@@ -27,14 +30,14 @@
     </Config>
   </FileSet>
   <FileSet Name="constrs_in" Type="BlockSrcs" RelSrcDir="$PSRCDIR/vio_manual_ctrl">
-    <File Path="$PPRDIR/../vio_manual_ctrl/vio_manual_ctrl.xci">
+    <File Path="$PPRDIR/../vio_manual_ctrl.xcix">
       <FileInfo>
         <Attr Name="UsedIn" Val="synthesis"/>
         <Attr Name="UsedIn" Val="implementation"/>
         <Attr Name="UsedIn" Val="simulation"/>
       </FileInfo>
     </File>
-    <File Path="$PPRDIR/../vio_manual_ctrl.xcix">
+    <File Path="$PPRDIR/../vio_manual_ctrl/vio_manual_ctrl.xci">
       <FileInfo>
         <Attr Name="UsedIn" Val="synthesis"/>
         <Attr Name="UsedIn" Val="implementation"/>
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/project.wdf b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/project.wdf
index 96dd836c..041072b4 100644
--- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/project.wdf
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/project.wdf
@@ -1,5 +1,5 @@
 version:1
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:37:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:33:00:00
 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00
 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00
 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00
@@ -13,11 +13,9 @@ version:1
 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00
 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00
 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00
-70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f63616c:636f72655f636f6e7461696e6572:74727565:00:00
-70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f72785f707265:636f72655f636f6e7461696e6572:74727565:00:00
 70726f6a656374:69705f636f72655f636f6e7461696e65725c626c6b5f6d656d5f67656e5f76385f345f335c726f6d5f686f705f64617461:636f72655f636f6e7461696e6572:74727565:00:00
 70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f63616c:636f72655f636f6e7461696e6572:74727565:00:00
-70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f636c6b5f6c645f7264:636f72655f636f6e7461696e6572:74727565:00:00
+70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f686f70:636f72655f636f6e7461696e6572:74727565:00:00
 70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f6d616e75616c5f6374726c:636f72655f636f6e7461696e6572:74727565:00:00
 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:30:00:00
 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
@@ -26,12 +24,12 @@ version:1
 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00
 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00
 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:3130:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:3130:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:3130:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:3130:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:3130:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3130:00:00
-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3130:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:3138:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:3138:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:3138:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:3138:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:3138:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3138:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3138:00:00
 5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3966393835363732626435303431393139633038356339623061353561633562:506172656e742050412070726f6a656374204944:00
-eof:4104132677
+eof:42320968
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.dcp b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.dcp
index de371a0d..1c6f8881 100644
--- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.dcp
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.dcp
@@ -1,3 +1,3 @@
 version https://git-lfs.github.com/spec/v1
-oid sha256:bb492a9cc911e5684d7d097ca4507bab54f6c07c61420e038d896b45fbc5c8f0
-size 144603
+oid sha256:7b2ce454d454de2ef11bb32b57ee3941db582464be46a75cdabb91dd223093e8
+size 145880
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.tcl b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.tcl
index 6970ee5f..96324412 100644
--- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.tcl
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.tcl
@@ -29,7 +29,7 @@ set_param synth.vivado.isSynthRun true
 set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info
 set_property webtalk.parent_dir /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt [current_project]
 set_property parent.project_path /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.xpr [current_project]
-set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project]
+set_property XPM_LIBRARIES XPM_MEMORY [current_project]
 set_property default_lib xil_defaultlib [current_project]
 set_property target_language Verilog [current_project]
 set_property ip_output_repo /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip [current_project]
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.vds b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.vds
index dba5b833..33ae8f5d 100644
--- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.vds
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.vds
@@ -2,8 +2,8 @@
 # Vivado v2019.1.3 (64-bit)
 # SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 # IP Build 2633630 on Wed Sep  4 12:30:14 MDT 2019
-# Start of session at: Wed Apr 19 12:03:36 2023
-# Process ID: 1955932
+# Start of session at: Sun Apr 23 16:18:54 2023
+# Process ID: 2442123
 # Current directory: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1
 # Command line: vivado -log vio_manual_ctrl.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_manual_ctrl.tcl
 # Log file: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.vds
@@ -16,13 +16,31 @@ Attempting to get a license for feature 'Synthesis' and/or device 'xc7k410t'
 INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k410t'
 INFO: [Device 21-403] Loading part xc7k410tffg900-2
 INFO: Launching helper process for spawning children vivado processes
-INFO: Helper process launched with PID 1956171 
+INFO: Helper process launched with PID 2442459 
 ---------------------------------------------------------------------------------
-Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 1829.438 ; gain = 152.719 ; free physical = 2454 ; free virtual = 42839
+Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 1829.402 ; gain = 152.688 ; free physical = 11602 ; free virtual = 32278
 ---------------------------------------------------------------------------------
 INFO: [Synth 8-6157] synthesizing module 'vio_manual_ctrl' [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/vio_manual_ctrl/synth/vio_manual_ctrl.v:59]
-WARNING: [Synth 8-3848] Net sl_iport0 in module/entity vio_manual_ctrl does not have driver. [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/vio_manual_ctrl/synth/vio_manual_ctrl.v:79]
+WARNING: [Synth 8-3848] Net sl_iport0 in module/entity vio_manual_ctrl does not have driver. [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/vio_manual_ctrl/synth/vio_manual_ctrl.v:81]
 INFO: [Synth 8-6155] done synthesizing module 'vio_manual_ctrl' (7#1) [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/vio_manual_ctrl/synth/vio_manual_ctrl.v:59]
+WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_rst
+WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Read
+WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[15]
+WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[14]
+WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[13]
+WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[12]
+WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[11]
+WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[10]
+WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[9]
+WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[8]
+WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[7]
+WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[6]
+WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[5]
+WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[4]
+WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[3]
+WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[2]
+WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[1]
+WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Internal_cnt_rst
 WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_rst
 WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Read
 WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[15]
@@ -56,24 +74,6 @@ WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unc
 WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[2]
 WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Internal_cnt_rst
 WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_rst
-WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_rst
-WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Read
-WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[15]
-WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[14]
-WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[13]
-WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[12]
-WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[11]
-WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[10]
-WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[9]
-WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[8]
-WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[7]
-WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[6]
-WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[5]
-WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[4]
-WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[3]
-WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[2]
-WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[1]
-WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Internal_cnt_rst
 WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_rst
 WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Read
 WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[15]
@@ -125,7 +125,7 @@ WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in30[0
 WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in31[0]
 INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
 ---------------------------------------------------------------------------------
-Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1892.125 ; gain = 215.406 ; free physical = 2480 ; free virtual = 42873
+Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1892.121 ; gain = 215.406 ; free physical = 11540 ; free virtual = 32237
 ---------------------------------------------------------------------------------
 
 Report Check Netlist: 
@@ -138,10 +138,10 @@ Report Check Netlist:
 Start Handling Custom Attributes
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
-Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1895.094 ; gain = 218.375 ; free physical = 2481 ; free virtual = 42874
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1895.090 ; gain = 218.375 ; free physical = 11539 ; free virtual = 32236
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
-Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1895.094 ; gain = 218.375 ; free physical = 2481 ; free virtual = 42874
+Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1895.090 ; gain = 218.375 ; free physical = 11539 ; free virtual = 32236
 ---------------------------------------------------------------------------------
 INFO: [Project 1-570] Preparing netlist for logic optimization
 
@@ -153,29 +153,29 @@ Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal
 Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/vio_manual_ctrl/vio_manual_ctrl.xdc]
 Completed Processing XDC Constraints
 
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2068.750 ; gain = 0.000 ; free physical = 2365 ; free virtual = 42776
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2072.746 ; gain = 0.000 ; free physical = 11494 ; free virtual = 32200
 INFO: [Project 1-111] Unisim Transformation Summary:
 No Unisim elements were transformed.
 
-Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2074.688 ; gain = 5.938 ; free physical = 2366 ; free virtual = 42776
+Constraint Validation Runtime : Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2079.684 ; gain = 6.938 ; free physical = 11494 ; free virtual = 32200
 ---------------------------------------------------------------------------------
-Finished Constraint Validation : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2074.688 ; gain = 397.969 ; free physical = 2420 ; free virtual = 42846
+Finished Constraint Validation : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2079.684 ; gain = 402.969 ; free physical = 11546 ; free virtual = 32249
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Loading Part and Timing Information
 ---------------------------------------------------------------------------------
 Loading part: xc7k410tffg900-2
 ---------------------------------------------------------------------------------
-Finished Loading Part and Timing Information : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2074.688 ; gain = 397.969 ; free physical = 2420 ; free virtual = 42846
+Finished Loading Part and Timing Information : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2079.684 ; gain = 402.969 ; free physical = 11546 ; free virtual = 32249
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Applying 'set_property' XDC Constraints
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
-Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2074.688 ; gain = 397.969 ; free physical = 2418 ; free virtual = 42847
+Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2079.684 ; gain = 402.969 ; free physical = 11546 ; free virtual = 32249
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
-Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2074.688 ; gain = 397.969 ; free physical = 2391 ; free virtual = 42827
+Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2079.684 ; gain = 402.969 ; free physical = 11540 ; free virtual = 32244
 ---------------------------------------------------------------------------------
 
 Report RTL Partitions: 
@@ -192,18 +192,18 @@ Detailed RTL Component Info :
 +---Registers : 
 	              128 Bit    Registers := 1     
 	               32 Bit    Registers := 1     
-	               16 Bit    Registers := 13    
+	               16 Bit    Registers := 14    
 	                9 Bit    Registers := 1     
 	                7 Bit    Registers := 1     
 	                5 Bit    Registers := 1     
 	                4 Bit    Registers := 1     
 	                3 Bit    Registers := 3     
 	                2 Bit    Registers := 4     
-	                1 Bit    Registers := 18    
+	                1 Bit    Registers := 20    
 +---Muxes : 
 	   2 Input     16 Bit        Muxes := 3     
 	   3 Input      9 Bit        Muxes := 1     
-	   2 Input      1 Bit        Muxes := 10    
+	   2 Input      1 Bit        Muxes := 11    
 ---------------------------------------------------------------------------------
 Finished RTL Component Statistics 
 ---------------------------------------------------------------------------------
@@ -254,7 +254,7 @@ Detailed RTL Component Info :
 +---Registers : 
 	               16 Bit    Registers := 1     
 	                3 Bit    Registers := 1     
-	                1 Bit    Registers := 7     
+	                1 Bit    Registers := 8     
 +---Muxes : 
 	   2 Input      1 Bit        Muxes := 2     
 Module vio_v3_0_20_probe_width 
@@ -306,57 +306,72 @@ Finished Part Resource Summary
 Start Cross Boundary and Area Optimization
 ---------------------------------------------------------------------------------
 Warning: Parallel synthesis criteria is not met 
+INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[2]'
 INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[2]'
+INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[3]'
 INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[3]'
 INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[3]'
 INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[3]'
+INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[4]'
 INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[4]'
 INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[4]'
 INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[4]'
+INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[5]'
 INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[5]'
 INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[5]'
 INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[5]'
 INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[5]'
+INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[6]'
 INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[6]'
 INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[6]'
 INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[6]'
 INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[6]'
+INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[7]'
 INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[7]'
 INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[7]'
 INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[7]'
 INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[7]'
+INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[8]'
 INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[8]'
 INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[8]'
 INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[8]'
 INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[8]'
+INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[9]'
 INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[9]'
 INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[9]'
 INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[9]'
 INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[9]'
+INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[10]'
 INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[10]'
 INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[10]'
 INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[10]'
 INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[10]'
+INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[11]'
 INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[11]'
 INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[11]'
 INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[11]'
 INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[11]'
+INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[12]'
 INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[12]'
 INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[12]'
 INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[12]'
 INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[12]'
+INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[13]'
 INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[13]'
 INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[13]'
 INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[13]'
 INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[13]'
+INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[14]'
 INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[14]'
 INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[14]'
 INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[14]'
 INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[14]'
+INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[15]'
 INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[15]'
 INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[15]'
 INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[15]'
 INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[15]'
+INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[15] )
 INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[15] )
 INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[15] )
 INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[15] )
@@ -368,7 +383,7 @@ INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int
 INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[6]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[7]'
 INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_WIDTH_INST/probe_width_int_reg[7] )
 ---------------------------------------------------------------------------------
-Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2074.688 ; gain = 397.969 ; free physical = 2375 ; free virtual = 42822
+Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2079.684 ; gain = 402.969 ; free physical = 11527 ; free virtual = 32234
 ---------------------------------------------------------------------------------
 
 Report RTL Partitions: 
@@ -380,13 +395,13 @@ Report RTL Partitions:
 Start Applying XDC Timing Constraints
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
-Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2074.688 ; gain = 397.969 ; free physical = 2202 ; free virtual = 42669
+Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2079.684 ; gain = 402.969 ; free physical = 10722 ; free virtual = 31560
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Timing Optimization
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
-Finished Timing Optimization : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2074.688 ; gain = 397.969 ; free physical = 2202 ; free virtual = 42669
+Finished Timing Optimization : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2079.684 ; gain = 402.969 ; free physical = 10720 ; free virtual = 31558
 ---------------------------------------------------------------------------------
 
 Report RTL Partitions: 
@@ -398,7 +413,7 @@ Report RTL Partitions:
 Start Technology Mapping
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
-Finished Technology Mapping : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2074.688 ; gain = 397.969 ; free physical = 2199 ; free virtual = 42665
+Finished Technology Mapping : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2079.684 ; gain = 402.969 ; free physical = 10706 ; free virtual = 31545
 ---------------------------------------------------------------------------------
 
 Report RTL Partitions: 
@@ -459,7 +474,7 @@ WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[2] to constant 0
 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[1] to constant 0
 WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[0] to constant 0
 ---------------------------------------------------------------------------------
-Finished IO Insertion : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2074.688 ; gain = 397.969 ; free physical = 2206 ; free virtual = 42674
+Finished IO Insertion : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2079.684 ; gain = 402.969 ; free physical = 10614 ; free virtual = 31452
 ---------------------------------------------------------------------------------
 
 Report Check Netlist: 
@@ -472,7 +487,7 @@ Report Check Netlist:
 Start Renaming Generated Instances
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
-Finished Renaming Generated Instances : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2074.688 ; gain = 397.969 ; free physical = 2206 ; free virtual = 42674
+Finished Renaming Generated Instances : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2079.684 ; gain = 402.969 ; free physical = 10613 ; free virtual = 31452
 ---------------------------------------------------------------------------------
 
 Report RTL Partitions: 
@@ -484,25 +499,25 @@ Report RTL Partitions:
 Start Rebuilding User Hierarchy
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
-Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2074.688 ; gain = 397.969 ; free physical = 2206 ; free virtual = 42674
+Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2079.684 ; gain = 402.969 ; free physical = 10612 ; free virtual = 31451
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Renaming Generated Ports
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
-Finished Renaming Generated Ports : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2074.688 ; gain = 397.969 ; free physical = 2206 ; free virtual = 42674
+Finished Renaming Generated Ports : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2079.684 ; gain = 402.969 ; free physical = 10612 ; free virtual = 31450
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Handling Custom Attributes
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
-Finished Handling Custom Attributes : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2074.688 ; gain = 397.969 ; free physical = 2206 ; free virtual = 42674
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2079.684 ; gain = 402.969 ; free physical = 10611 ; free virtual = 31449
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Renaming Generated Nets
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
-Finished Renaming Generated Nets : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2074.688 ; gain = 397.969 ; free physical = 2206 ; free virtual = 42674
+Finished Renaming Generated Nets : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2079.684 ; gain = 402.969 ; free physical = 10610 ; free virtual = 31449
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Writing Synthesis Report
@@ -519,57 +534,58 @@ Report Cell Usage:
 |      |Cell |Count |
 +------+-----+------+
 |1     |LUT2 |     7|
-|2     |LUT3 |    58|
-|3     |LUT4 |    10|
-|4     |LUT5 |    26|
-|5     |LUT6 |    81|
-|6     |FDRE |   348|
+|2     |LUT3 |    57|
+|3     |LUT4 |    11|
+|4     |LUT5 |    27|
+|5     |LUT6 |    82|
+|6     |FDRE |   351|
 |7     |FDSE |     6|
 +------+-----+------+
 
 Report Instance Areas: 
-+------+---------------------------------------+------------------------------------------+------+
-|      |Instance                               |Module                                    |Cells |
-+------+---------------------------------------+------------------------------------------+------+
-|1     |top                                    |                                          |   536|
-|2     |  inst                                 |vio_v3_0_20_vio                           |   536|
-|3     |    U_XSDB_SLAVE                       |xsdbs_v1_0_2_xsdbs                        |   248|
-|4     |    DECODER_INST                       |vio_v3_0_20_decoder                       |    82|
-|5     |    PROBE_OUT_ALL_INST                 |vio_v3_0_20_probe_out_all                 |   180|
-|6     |      \G_PROBE_OUT[0].PROBE_OUT0_INST  |vio_v3_0_20_probe_out_one                 |     6|
-|7     |      \G_PROBE_OUT[1].PROBE_OUT0_INST  |vio_v3_0_20_probe_out_one__parameterized0 |     3|
-|8     |      \G_PROBE_OUT[2].PROBE_OUT0_INST  |vio_v3_0_20_probe_out_one__parameterized1 |   104|
-|9     |      \G_PROBE_OUT[3].PROBE_OUT0_INST  |vio_v3_0_20_probe_out_one__parameterized2 |     6|
-|10    |      \G_PROBE_OUT[4].PROBE_OUT0_INST  |vio_v3_0_20_probe_out_one__parameterized3 |     8|
-|11    |    PROBE_OUT_WIDTH_INST               |vio_v3_0_20_probe_width                   |    10|
-+------+---------------------------------------+------------------------------------------+------+
++------+---------------------------------------+--------------------------------------------+------+
+|      |Instance                               |Module                                      |Cells |
++------+---------------------------------------+--------------------------------------------+------+
+|1     |top                                    |                                            |   541|
+|2     |  inst                                 |vio_v3_0_20_vio                             |   541|
+|3     |    U_XSDB_SLAVE                       |xsdbs_v1_0_2_xsdbs                          |   248|
+|4     |    DECODER_INST                       |vio_v3_0_20_decoder                         |    82|
+|5     |    PROBE_OUT_ALL_INST                 |vio_v3_0_20_probe_out_all                   |   185|
+|6     |      \G_PROBE_OUT[0].PROBE_OUT0_INST  |vio_v3_0_20_probe_out_one                   |     6|
+|7     |      \G_PROBE_OUT[1].PROBE_OUT0_INST  |vio_v3_0_20_probe_out_one__parameterized0   |     3|
+|8     |      \G_PROBE_OUT[2].PROBE_OUT0_INST  |vio_v3_0_20_probe_out_one__parameterized1   |   104|
+|9     |      \G_PROBE_OUT[3].PROBE_OUT0_INST  |vio_v3_0_20_probe_out_one__parameterized2   |     6|
+|10    |      \G_PROBE_OUT[4].PROBE_OUT0_INST  |vio_v3_0_20_probe_out_one__parameterized3   |     8|
+|11    |      \G_PROBE_OUT[5].PROBE_OUT0_INST  |vio_v3_0_20_probe_out_one__parameterized0_0 |     3|
+|12    |    PROBE_OUT_WIDTH_INST               |vio_v3_0_20_probe_width                     |    10|
++------+---------------------------------------+--------------------------------------------+------+
 ---------------------------------------------------------------------------------
-Finished Writing Synthesis Report : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2074.688 ; gain = 397.969 ; free physical = 2206 ; free virtual = 42674
+Finished Writing Synthesis Report : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2079.684 ; gain = 402.969 ; free physical = 10610 ; free virtual = 31449
 ---------------------------------------------------------------------------------
 Synthesis finished with 0 errors, 0 critical warnings and 293 warnings.
-Synthesis Optimization Runtime : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 2074.688 ; gain = 218.375 ; free physical = 2254 ; free virtual = 42730
-Synthesis Optimization Complete : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2074.688 ; gain = 397.969 ; free physical = 2256 ; free virtual = 42731
+Synthesis Optimization Runtime : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 2079.684 ; gain = 218.375 ; free physical = 10655 ; free virtual = 31494
+Synthesis Optimization Complete : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2079.684 ; gain = 402.969 ; free physical = 10655 ; free virtual = 31494
 INFO: [Project 1-571] Translating synthesized netlist
 INFO: [Project 1-570] Preparing netlist for logic optimization
 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2074.688 ; gain = 0.000 ; free physical = 2203 ; free virtual = 42682
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2079.684 ; gain = 0.000 ; free physical = 10505 ; free virtual = 31348
 INFO: [Project 1-111] Unisim Transformation Summary:
 No Unisim elements were transformed.
 
 INFO: [Common 17-83] Releasing license: Synthesis
-73 Infos, 138 Warnings, 0 Critical Warnings and 0 Errors encountered.
+88 Infos, 138 Warnings, 0 Critical Warnings and 0 Errors encountered.
 synth_design completed successfully
-synth_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 2074.688 ; gain = 675.770 ; free physical = 2296 ; free virtual = 42774
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2074.688 ; gain = 0.000 ; free physical = 2296 ; free virtual = 42774
+synth_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 2079.684 ; gain = 680.770 ; free physical = 10592 ; free virtual = 31436
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2079.684 ; gain = 0.000 ; free physical = 10592 ; free virtual = 31435
 WARNING: [Constraints 18-5210] No constraints selected for write.
 Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
 INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.dcp' has been generated.
 WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used.
-INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP vio_manual_ctrl, cache-ID = f95fe35d68f7828e
-INFO: [Coretcl 2-1174] Renamed 10 cell refs.
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2098.699 ; gain = 0.000 ; free physical = 2299 ; free virtual = 42780
+INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP vio_manual_ctrl, cache-ID = 1f2022300f50ed09
+INFO: [Coretcl 2-1174] Renamed 11 cell refs.
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2103.695 ; gain = 0.000 ; free physical = 10459 ; free virtual = 31304
 WARNING: [Constraints 18-5210] No constraints selected for write.
 Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
 INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.dcp' has been generated.
 INFO: [runtcl-4] Executing : report_utilization -file vio_manual_ctrl_utilization_synth.rpt -pb vio_manual_ctrl_utilization_synth.pb
-INFO: [Common 17-206] Exiting Vivado at Wed Apr 19 12:03:53 2023...
+INFO: [Common 17-206] Exiting Vivado at Sun Apr 23 16:19:12 2023...
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.v b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.v
index 44d0af55..fd04dbe0 100644
--- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.v
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.v
@@ -1,3 +1,3 @@
 version https://git-lfs.github.com/spec/v1
-oid sha256:1ef789b139dd21314f2f64ed27ffe456fe9f3780bffc1b839629a84a6d76d369
-size 352468
+oid sha256:a01fafc69a1a3ba5410b7a42027cc78e47f5b15cfdae5003802be620f113aeb6
+size 355493
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.vhdl b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.vhdl
index 88e89736..b34a8cc6 100644
--- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.vhdl
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.vhdl
@@ -1,3 +1,3 @@
 version https://git-lfs.github.com/spec/v1
-oid sha256:60f900616e80d391d0f1ca17c739ffeb62b08557d1f784a2224cbc94a84eb147
-size 633949
+oid sha256:824bcac0396eea134efa41f3102c915ef47b199e1c4072d91d827c19f22fc999
+size 637257
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.v b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.v
index 34b2261b..a1f4f379 100644
--- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.v
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.v
@@ -1,7 +1,7 @@
 // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
 // --------------------------------------------------------------------------------
 // Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
-// Date        : Wed Apr 19 12:03:53 2023
+// Date        : Sun Apr 23 16:19:11 2023
 // Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
 // Command     : write_verilog -force -mode synth_stub
 //               /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.v
@@ -15,12 +15,13 @@
 // Please paste the declaration into a Verilog source file or add the file as an additional source.
 (* X_CORE_INFO = "vio,Vivado 2019.1.3" *)
 module vio_manual_ctrl(clk, probe_out0, probe_out1, probe_out2, 
-  probe_out3, probe_out4)
-/* synthesis syn_black_box black_box_pad_pin="clk,probe_out0[1:0],probe_out1[0:0],probe_out2[31:0],probe_out3[1:0],probe_out4[3:0]" */;
+  probe_out3, probe_out4, probe_out5)
+/* synthesis syn_black_box black_box_pad_pin="clk,probe_out0[1:0],probe_out1[0:0],probe_out2[31:0],probe_out3[1:0],probe_out4[3:0],probe_out5[0:0]" */;
   input clk;
   output [1:0]probe_out0;
   output [0:0]probe_out1;
   output [31:0]probe_out2;
   output [1:0]probe_out3;
   output [3:0]probe_out4;
+  output [0:0]probe_out5;
 endmodule
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.vhdl b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.vhdl
index 087749f8..20780871 100644
--- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.vhdl
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.vhdl
@@ -1,7 +1,7 @@
 -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
 -- --------------------------------------------------------------------------------
 -- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
--- Date        : Wed Apr 19 12:03:53 2023
+-- Date        : Sun Apr 23 16:19:11 2023
 -- Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
 -- Command     : write_vhdl -force -mode synth_stub
 --               /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.vhdl
@@ -19,7 +19,8 @@ entity vio_manual_ctrl is
     probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 );
     probe_out2 : out STD_LOGIC_VECTOR ( 31 downto 0 );
     probe_out3 : out STD_LOGIC_VECTOR ( 1 downto 0 );
-    probe_out4 : out STD_LOGIC_VECTOR ( 3 downto 0 )
+    probe_out4 : out STD_LOGIC_VECTOR ( 3 downto 0 );
+    probe_out5 : out STD_LOGIC_VECTOR ( 0 to 0 )
   );
 
 end vio_manual_ctrl;
@@ -28,7 +29,7 @@ architecture stub of vio_manual_ctrl is
 attribute syn_black_box : boolean;
 attribute black_box_pad_pin : string;
 attribute syn_black_box of stub : architecture is true;
-attribute black_box_pad_pin of stub : architecture is "clk,probe_out0[1:0],probe_out1[0:0],probe_out2[31:0],probe_out3[1:0],probe_out4[3:0]";
+attribute black_box_pad_pin of stub : architecture is "clk,probe_out0[1:0],probe_out1[0:0],probe_out2[31:0],probe_out3[1:0],probe_out4[3:0],probe_out5[0:0]";
 attribute X_CORE_INFO : string;
 attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3";
 begin
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_utilization_synth.pb b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_utilization_synth.pb
index 37765f1c..0f4c8633 100644
Binary files a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_utilization_synth.pb and b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_utilization_synth.pb differ
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_utilization_synth.rpt b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_utilization_synth.rpt
index b4109c80..a92c3eae 100644
--- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_utilization_synth.rpt
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_utilization_synth.rpt
@@ -1,7 +1,7 @@
 Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
 -------------------------------------------------------------------------------------------------------------------------
 | Tool Version : Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
-| Date         : Wed Apr 19 12:03:53 2023
+| Date         : Sun Apr 23 16:19:11 2023
 | Host         : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
 | Command      : report_utilization -file vio_manual_ctrl_utilization_synth.rpt -pb vio_manual_ctrl_utilization_synth.pb
 | Design       : vio_manual_ctrl
@@ -30,11 +30,11 @@ Table of Contents
 +-------------------------+------+-------+-----------+-------+
 |        Site Type        | Used | Fixed | Available | Util% |
 +-------------------------+------+-------+-----------+-------+
-| Slice LUTs*             |  150 |     0 |    254200 |  0.06 |
-|   LUT as Logic          |  150 |     0 |    254200 |  0.06 |
+| Slice LUTs*             |  153 |     0 |    254200 |  0.06 |
+|   LUT as Logic          |  153 |     0 |    254200 |  0.06 |
 |   LUT as Memory         |    0 |     0 |     90600 |  0.00 |
-| Slice Registers         |  354 |     0 |    508400 |  0.07 |
-|   Register as Flip Flop |  354 |     0 |    508400 |  0.07 |
+| Slice Registers         |  357 |     0 |    508400 |  0.07 |
+|   Register as Flip Flop |  357 |     0 |    508400 |  0.07 |
 |   Register as Latch     |    0 |     0 |    508400 |  0.00 |
 | F7 Muxes                |    0 |     0 |    127100 |  0.00 |
 | F8 Muxes                |    0 |     0 |     63550 |  0.00 |
@@ -57,7 +57,7 @@ Table of Contents
 | 0     |          Yes |           - |          Set |
 | 0     |          Yes |           - |        Reset |
 | 6     |          Yes |         Set |            - |
-| 348   |          Yes |       Reset |            - |
+| 351   |          Yes |       Reset |            - |
 +-------+--------------+-------------+--------------+
 
 
@@ -151,11 +151,11 @@ Table of Contents
 +----------+------+---------------------+
 | Ref Name | Used | Functional Category |
 +----------+------+---------------------+
-| FDRE     |  348 |        Flop & Latch |
-| LUT6     |   81 |                 LUT |
-| LUT3     |   58 |                 LUT |
-| LUT5     |   26 |                 LUT |
-| LUT4     |   10 |                 LUT |
+| FDRE     |  351 |        Flop & Latch |
+| LUT6     |   82 |                 LUT |
+| LUT3     |   57 |                 LUT |
+| LUT5     |   27 |                 LUT |
+| LUT4     |   11 |                 LUT |
 | LUT2     |    7 |                 LUT |
 | FDSE     |    6 |        Flop & Latch |
 +----------+------+---------------------+
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vivado.pb b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vivado.pb
index 599cdcf3..eec173a7 100644
Binary files a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vivado.pb and b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vivado.pb differ
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.xpr b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.xpr
index d04b7bb5..e28838c2 100644
--- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.xpr
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.xpr
@@ -39,13 +39,13 @@
     <Option Name="WTVcsLaunchSim" Val="0"/>
     <Option Name="WTRivieraLaunchSim" Val="0"/>
     <Option Name="WTActivehdlLaunchSim" Val="0"/>
-    <Option Name="WTXSimExportSim" Val="18"/>
-    <Option Name="WTModelSimExportSim" Val="18"/>
-    <Option Name="WTQuestaExportSim" Val="18"/>
-    <Option Name="WTIesExportSim" Val="18"/>
-    <Option Name="WTVcsExportSim" Val="18"/>
-    <Option Name="WTRivieraExportSim" Val="18"/>
-    <Option Name="WTActivehdlExportSim" Val="18"/>
+    <Option Name="WTXSimExportSim" Val="19"/>
+    <Option Name="WTModelSimExportSim" Val="19"/>
+    <Option Name="WTQuestaExportSim" Val="19"/>
+    <Option Name="WTIesExportSim" Val="19"/>
+    <Option Name="WTVcsExportSim" Val="19"/>
+    <Option Name="WTRivieraExportSim" Val="19"/>
+    <Option Name="WTActivehdlExportSim" Val="19"/>
     <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
     <Option Name="XSimRadix" Val="hex"/>
     <Option Name="XSimTimeUnit" Val="ns"/>
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/ip/vio_manual_ctrl.xcix b/projects/dl814_k7/dl814_k7_cal_coarse/ip/vio_manual_ctrl.xcix
index 9588dada..4714d726 100644
--- a/projects/dl814_k7/dl814_k7_cal_coarse/ip/vio_manual_ctrl.xcix
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/ip/vio_manual_ctrl.xcix
@@ -1,3 +1,3 @@
 version https://git-lfs.github.com/spec/v1
-oid sha256:9dc7eb2f48d8d32a5c97f47f18a5dbfa0caba47a559483c5c6c0f9ff40f5f1e6
-size 720700
+oid sha256:1c0d0c93f4dcdda250ab0938f0f71e958a56e6e947551856a562bb8f549a65ec
+size 723033
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/project.tcl b/projects/dl814_k7/dl814_k7_cal_coarse/project.tcl
index af4b0f2c..e0cf9005 100644
--- a/projects/dl814_k7/dl814_k7_cal_coarse/project.tcl
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/project.tcl
@@ -3,7 +3,7 @@
 #
 # project.tcl: Tcl script for re-creating project 'project'
 #
-# Generated by Vivado on Wed Apr 19 21:06:57 CST 2023
+# Generated by Vivado on Mon Apr 24 11:12:47 CST 2023
 # IP Build 2633630 on Wed Sep  4 12:30:14 MDT 2019
 #
 # This file contains the Vivado Tcl commands for re-creating the project to the state*
@@ -32,8 +32,8 @@
 #    "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/rx_pre_process/ila_rx_pre_ant/ila_rx_pre_ant.xci"
 #    "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/rx_pre_process/ila_rx_pre_sys/ila_rx_pre_sys.xci"
 #    "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/rx_pre_process/ila_cal/ila_cal.xci"
-#    "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/basic_driver/ila_8x12_2x30_8192/ila_8x12_2x30_8192.xci"
-#    "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/basic_driver/ila_2x12x1024/ila_2x12x1024.xci"
+#    "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/basic_driver/ila_8x12_2x30_131072/ila_8x12_2x30_131072.xci"
+#    "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/basic_driver/ila_2x12x131072/ila_2x12x131072.xci"
 #    "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/ant_rf_interface/vio_rf_rd/vio_rf_rd.xci"
 #    "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/ant_rf_interface/ila_AntCtrl/ila_AntCtrl.xci"
 #    "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/ant_rf_interface/ila_rfcontrl/ila_rfcontrl.xci"
@@ -217,16 +217,15 @@ set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_use
 set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
 set_property -name "simulator_language" -value "Mixed" -objects $obj
 set_property -name "target_simulator" -value "VCS" -objects $obj
-set_property -name "webtalk.activehdl_export_sim" -value "87" -objects $obj
-set_property -name "webtalk.ies_export_sim" -value "87" -objects $obj
-set_property -name "webtalk.modelsim_export_sim" -value "87" -objects $obj
+set_property -name "webtalk.activehdl_export_sim" -value "89" -objects $obj
+set_property -name "webtalk.ies_export_sim" -value "89" -objects $obj
+set_property -name "webtalk.modelsim_export_sim" -value "89" -objects $obj
 set_property -name "webtalk.modelsim_launch_sim" -value "2" -objects $obj
-set_property -name "webtalk.questa_export_sim" -value "87" -objects $obj
-set_property -name "webtalk.riviera_export_sim" -value "87" -objects $obj
-set_property -name "webtalk.vcs_export_sim" -value "87" -objects $obj
+set_property -name "webtalk.questa_export_sim" -value "89" -objects $obj
+set_property -name "webtalk.riviera_export_sim" -value "89" -objects $obj
+set_property -name "webtalk.vcs_export_sim" -value "89" -objects $obj
 set_property -name "webtalk.vcs_launch_sim" -value "69" -objects $obj
-set_property -name "webtalk.xcelium_export_sim" -value "10" -objects $obj
-set_property -name "webtalk.xsim_export_sim" -value "87" -objects $obj
+set_property -name "webtalk.xsim_export_sim" -value "89" -objects $obj
 set_property -name "xpm_libraries" -value "XPM_CDC XPM_MEMORY" -objects $obj
 
 # Create 'sources_1' fileset (if not found)
@@ -249,8 +248,8 @@ set files [list \
  [file normalize "${origin_dir}/../common_ip/rx_pre_process/ila_rx_pre_ant/ila_rx_pre_ant.xci"] \
  [file normalize "${origin_dir}/../common_ip/rx_pre_process/ila_rx_pre_sys/ila_rx_pre_sys.xci"] \
  [file normalize "${origin_dir}/../common_ip/rx_pre_process/ila_cal/ila_cal.xci"] \
- [file normalize "${origin_dir}/../common_ip/basic_driver/ila_8x12_2x30_8192/ila_8x12_2x30_8192.xci"] \
- [file normalize "${origin_dir}/../common_ip/basic_driver/ila_2x12x1024/ila_2x12x1024.xci"] \
+ [file normalize "${origin_dir}/../common_ip/basic_driver/ila_8x12_2x30_131072/ila_8x12_2x30_131072.xci"] \
+ [file normalize "${origin_dir}/../common_ip/basic_driver/ila_2x12x131072/ila_2x12x131072.xci"] \
  [file normalize "${origin_dir}/../common_ip/ant_rf_interface/vio_rf_rd/vio_rf_rd.xci"] \
  [file normalize "${origin_dir}/../common_ip/ant_rf_interface/ila_AntCtrl/ila_AntCtrl.xci"] \
  [file normalize "${origin_dir}/../common_ip/ant_rf_interface/ila_rfcontrl/ila_rfcontrl.xci"] \
@@ -370,7 +369,7 @@ if { ![get_property "is_locked" $file_obj] } {
   set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
 }
 
-set file "$origin_dir/../common_ip/basic_driver/ila_8x12_2x30_8192/ila_8x12_2x30_8192.xci"
+set file "$origin_dir/../common_ip/basic_driver/ila_8x12_2x30_131072/ila_8x12_2x30_131072.xci"
 set file [file normalize $file]
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
@@ -379,7 +378,7 @@ if { ![get_property "is_locked" $file_obj] } {
   set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
 }
 
-set file "$origin_dir/../common_ip/basic_driver/ila_2x12x1024/ila_2x12x1024.xci"
+set file "$origin_dir/../common_ip/basic_driver/ila_2x12x131072/ila_2x12x131072.xci"
 set file [file normalize $file]
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
 set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/project/project.runs/impl_1/debug_nets.ltx b/projects/dl814_k7/dl814_k7_cal_coarse/project/project.runs/impl_1/debug_nets.ltx
index c594f69c..0f56a60d 100644
--- a/projects/dl814_k7/dl814_k7_cal_coarse/project/project.runs/impl_1/debug_nets.ltx
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/project/project.runs/impl_1/debug_nets.ltx
@@ -859,11 +859,11 @@
                                         "subnets": [
                                             {
                                                 "name": "curr_state[1]",
-                                                "parentNetId": 15
+                                                "parentNetId": 174
                                             },
                                             {
                                                 "name": "curr_state[0]",
-                                                "parentNetId": 16
+                                                "parentNetId": 175
                                             }
                                         ]
                                     }
@@ -4541,6 +4541,22 @@
                                         ]
                                     }
                                 ]
+                            },
+                            {
+                                "name": "probe_out5",
+                                "id": 122,
+                                "type": "DATA",
+                                "direction": "OUT",
+                                "isVector": false,
+                                "leftIndex": 0,
+                                "rightIndex": 0,
+                                "portIndex": 5,
+                                "nets": [
+                                    {
+                                        "name": "rx_test_en",
+                                        "isBus": false
+                                    }
+                                ]
                             }
                         ]
                     },
@@ -4558,7 +4574,7 @@
                         "pins": [
                             {
                                 "name": "probe_in0",
-                                "id": 122,
+                                "id": 123,
                                 "type": "DATA",
                                 "direction": "IN",
                                 "isVector": true,
@@ -4600,7 +4616,7 @@
                             },
                             {
                                 "name": "probe_in1",
-                                "id": 123,
+                                "id": 124,
                                 "type": "DATA",
                                 "direction": "IN",
                                 "isVector": true,
@@ -4642,7 +4658,7 @@
                             },
                             {
                                 "name": "probe_in2",
-                                "id": 124,
+                                "id": 125,
                                 "type": "DATA",
                                 "direction": "IN",
                                 "isVector": true,
@@ -4684,7 +4700,7 @@
                             },
                             {
                                 "name": "probe_in3",
-                                "id": 125,
+                                "id": 126,
                                 "type": "DATA",
                                 "direction": "IN",
                                 "isVector": true,
@@ -4726,7 +4742,7 @@
                             },
                             {
                                 "name": "probe_in4",
-                                "id": 126,
+                                "id": 127,
                                 "type": "DATA",
                                 "direction": "IN",
                                 "isVector": true,
@@ -4756,7 +4772,7 @@
                             },
                             {
                                 "name": "probe_in5",
-                                "id": 127,
+                                "id": 128,
                                 "type": "DATA",
                                 "direction": "IN",
                                 "isVector": true,
@@ -4786,7 +4802,7 @@
                             },
                             {
                                 "name": "probe_in6",
-                                "id": 128,
+                                "id": 129,
                                 "type": "DATA",
                                 "direction": "IN",
                                 "isVector": true,
@@ -4816,7 +4832,7 @@
                             },
                             {
                                 "name": "probe_in7",
-                                "id": 129,
+                                "id": 130,
                                 "type": "DATA",
                                 "direction": "IN",
                                 "isVector": true,
@@ -4846,7 +4862,7 @@
                             },
                             {
                                 "name": "probe_in8",
-                                "id": 130,
+                                "id": 131,
                                 "type": "DATA",
                                 "direction": "IN",
                                 "isVector": true,
@@ -4960,7 +4976,7 @@
                             },
                             {
                                 "name": "probe_in9",
-                                "id": 131,
+                                "id": 132,
                                 "type": "DATA",
                                 "direction": "IN",
                                 "isVector": true,
@@ -5280,7 +5296,7 @@
                         "pins": [
                             {
                                 "name": "probe_out0",
-                                "id": 132,
+                                "id": 133,
                                 "type": "DATA",
                                 "direction": "OUT",
                                 "isVector": false,
@@ -5296,7 +5312,7 @@
                             },
                             {
                                 "name": "probe_out1",
-                                "id": 133,
+                                "id": 134,
                                 "type": "DATA",
                                 "direction": "OUT",
                                 "isVector": false,
@@ -5312,7 +5328,7 @@
                             },
                             {
                                 "name": "probe_out2",
-                                "id": 134,
+                                "id": 135,
                                 "type": "DATA",
                                 "direction": "OUT",
                                 "isVector": true,
@@ -5378,7 +5394,7 @@
                             },
                             {
                                 "name": "probe_out3",
-                                "id": 135,
+                                "id": 136,
                                 "type": "DATA",
                                 "direction": "OUT",
                                 "isVector": true,
@@ -5420,7 +5436,7 @@
                             },
                             {
                                 "name": "probe_out4",
-                                "id": 136,
+                                "id": 137,
                                 "type": "DATA",
                                 "direction": "OUT",
                                 "isVector": true,
@@ -5450,7 +5466,7 @@
                             },
                             {
                                 "name": "probe_out5",
-                                "id": 137,
+                                "id": 138,
                                 "type": "DATA",
                                 "direction": "OUT",
                                 "isVector": true,
@@ -5480,7 +5496,7 @@
                             },
                             {
                                 "name": "probe_out6",
-                                "id": 138,
+                                "id": 139,
                                 "type": "DATA",
                                 "direction": "OUT",
                                 "isVector": true,
@@ -5510,7 +5526,7 @@
                             },
                             {
                                 "name": "probe_out7",
-                                "id": 139,
+                                "id": 140,
                                 "type": "DATA",
                                 "direction": "OUT",
                                 "isVector": true,
@@ -5540,7 +5556,7 @@
                             },
                             {
                                 "name": "probe_out8",
-                                "id": 140,
+                                "id": 141,
                                 "type": "DATA",
                                 "direction": "OUT",
                                 "isVector": true,
@@ -5582,7 +5598,7 @@
                             },
                             {
                                 "name": "probe_out9",
-                                "id": 141,
+                                "id": 142,
                                 "type": "DATA",
                                 "direction": "OUT",
                                 "isVector": true,
@@ -5624,7 +5640,7 @@
                             },
                             {
                                 "name": "probe_out10",
-                                "id": 142,
+                                "id": 143,
                                 "type": "DATA",
                                 "direction": "OUT",
                                 "isVector": true,
@@ -5690,7 +5706,7 @@
                             },
                             {
                                 "name": "probe_out11",
-                                "id": 143,
+                                "id": 144,
                                 "type": "DATA",
                                 "direction": "OUT",
                                 "isVector": true,
@@ -5756,7 +5772,7 @@
                             },
                             {
                                 "name": "probe_out12",
-                                "id": 144,
+                                "id": 145,
                                 "type": "DATA",
                                 "direction": "OUT",
                                 "isVector": true,
@@ -5825,7 +5841,7 @@
                 ],
                 "parent_nets": [
                     {
-                        "id": 15,
+                        "id": 174,
                         "name": "u_rx_pre_process/u_ad9361_phase_cal/out[1]",
                         "state_reg": [
                             {
@@ -5852,7 +5868,7 @@
                         ]
                     },
                     {
-                        "id": 16,
+                        "id": 175,
                         "name": "u_rx_pre_process/u_ad9361_phase_cal/out[0]",
                         "state_reg": [
                             {
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/project/project.runs/impl_1/system_top.bit b/projects/dl814_k7/dl814_k7_cal_coarse/project/project.runs/impl_1/system_top.bit
index b1db947c..2f219f69 100644
Binary files a/projects/dl814_k7/dl814_k7_cal_coarse/project/project.runs/impl_1/system_top.bit and b/projects/dl814_k7/dl814_k7_cal_coarse/project/project.runs/impl_1/system_top.bit differ
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/project/project.runs/impl_1/system_top.ltx b/projects/dl814_k7/dl814_k7_cal_coarse/project/project.runs/impl_1/system_top.ltx
index c594f69c..0f56a60d 100644
--- a/projects/dl814_k7/dl814_k7_cal_coarse/project/project.runs/impl_1/system_top.ltx
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/project/project.runs/impl_1/system_top.ltx
@@ -859,11 +859,11 @@
                                         "subnets": [
                                             {
                                                 "name": "curr_state[1]",
-                                                "parentNetId": 15
+                                                "parentNetId": 174
                                             },
                                             {
                                                 "name": "curr_state[0]",
-                                                "parentNetId": 16
+                                                "parentNetId": 175
                                             }
                                         ]
                                     }
@@ -4541,6 +4541,22 @@
                                         ]
                                     }
                                 ]
+                            },
+                            {
+                                "name": "probe_out5",
+                                "id": 122,
+                                "type": "DATA",
+                                "direction": "OUT",
+                                "isVector": false,
+                                "leftIndex": 0,
+                                "rightIndex": 0,
+                                "portIndex": 5,
+                                "nets": [
+                                    {
+                                        "name": "rx_test_en",
+                                        "isBus": false
+                                    }
+                                ]
                             }
                         ]
                     },
@@ -4558,7 +4574,7 @@
                         "pins": [
                             {
                                 "name": "probe_in0",
-                                "id": 122,
+                                "id": 123,
                                 "type": "DATA",
                                 "direction": "IN",
                                 "isVector": true,
@@ -4600,7 +4616,7 @@
                             },
                             {
                                 "name": "probe_in1",
-                                "id": 123,
+                                "id": 124,
                                 "type": "DATA",
                                 "direction": "IN",
                                 "isVector": true,
@@ -4642,7 +4658,7 @@
                             },
                             {
                                 "name": "probe_in2",
-                                "id": 124,
+                                "id": 125,
                                 "type": "DATA",
                                 "direction": "IN",
                                 "isVector": true,
@@ -4684,7 +4700,7 @@
                             },
                             {
                                 "name": "probe_in3",
-                                "id": 125,
+                                "id": 126,
                                 "type": "DATA",
                                 "direction": "IN",
                                 "isVector": true,
@@ -4726,7 +4742,7 @@
                             },
                             {
                                 "name": "probe_in4",
-                                "id": 126,
+                                "id": 127,
                                 "type": "DATA",
                                 "direction": "IN",
                                 "isVector": true,
@@ -4756,7 +4772,7 @@
                             },
                             {
                                 "name": "probe_in5",
-                                "id": 127,
+                                "id": 128,
                                 "type": "DATA",
                                 "direction": "IN",
                                 "isVector": true,
@@ -4786,7 +4802,7 @@
                             },
                             {
                                 "name": "probe_in6",
-                                "id": 128,
+                                "id": 129,
                                 "type": "DATA",
                                 "direction": "IN",
                                 "isVector": true,
@@ -4816,7 +4832,7 @@
                             },
                             {
                                 "name": "probe_in7",
-                                "id": 129,
+                                "id": 130,
                                 "type": "DATA",
                                 "direction": "IN",
                                 "isVector": true,
@@ -4846,7 +4862,7 @@
                             },
                             {
                                 "name": "probe_in8",
-                                "id": 130,
+                                "id": 131,
                                 "type": "DATA",
                                 "direction": "IN",
                                 "isVector": true,
@@ -4960,7 +4976,7 @@
                             },
                             {
                                 "name": "probe_in9",
-                                "id": 131,
+                                "id": 132,
                                 "type": "DATA",
                                 "direction": "IN",
                                 "isVector": true,
@@ -5280,7 +5296,7 @@
                         "pins": [
                             {
                                 "name": "probe_out0",
-                                "id": 132,
+                                "id": 133,
                                 "type": "DATA",
                                 "direction": "OUT",
                                 "isVector": false,
@@ -5296,7 +5312,7 @@
                             },
                             {
                                 "name": "probe_out1",
-                                "id": 133,
+                                "id": 134,
                                 "type": "DATA",
                                 "direction": "OUT",
                                 "isVector": false,
@@ -5312,7 +5328,7 @@
                             },
                             {
                                 "name": "probe_out2",
-                                "id": 134,
+                                "id": 135,
                                 "type": "DATA",
                                 "direction": "OUT",
                                 "isVector": true,
@@ -5378,7 +5394,7 @@
                             },
                             {
                                 "name": "probe_out3",
-                                "id": 135,
+                                "id": 136,
                                 "type": "DATA",
                                 "direction": "OUT",
                                 "isVector": true,
@@ -5420,7 +5436,7 @@
                             },
                             {
                                 "name": "probe_out4",
-                                "id": 136,
+                                "id": 137,
                                 "type": "DATA",
                                 "direction": "OUT",
                                 "isVector": true,
@@ -5450,7 +5466,7 @@
                             },
                             {
                                 "name": "probe_out5",
-                                "id": 137,
+                                "id": 138,
                                 "type": "DATA",
                                 "direction": "OUT",
                                 "isVector": true,
@@ -5480,7 +5496,7 @@
                             },
                             {
                                 "name": "probe_out6",
-                                "id": 138,
+                                "id": 139,
                                 "type": "DATA",
                                 "direction": "OUT",
                                 "isVector": true,
@@ -5510,7 +5526,7 @@
                             },
                             {
                                 "name": "probe_out7",
-                                "id": 139,
+                                "id": 140,
                                 "type": "DATA",
                                 "direction": "OUT",
                                 "isVector": true,
@@ -5540,7 +5556,7 @@
                             },
                             {
                                 "name": "probe_out8",
-                                "id": 140,
+                                "id": 141,
                                 "type": "DATA",
                                 "direction": "OUT",
                                 "isVector": true,
@@ -5582,7 +5598,7 @@
                             },
                             {
                                 "name": "probe_out9",
-                                "id": 141,
+                                "id": 142,
                                 "type": "DATA",
                                 "direction": "OUT",
                                 "isVector": true,
@@ -5624,7 +5640,7 @@
                             },
                             {
                                 "name": "probe_out10",
-                                "id": 142,
+                                "id": 143,
                                 "type": "DATA",
                                 "direction": "OUT",
                                 "isVector": true,
@@ -5690,7 +5706,7 @@
                             },
                             {
                                 "name": "probe_out11",
-                                "id": 143,
+                                "id": 144,
                                 "type": "DATA",
                                 "direction": "OUT",
                                 "isVector": true,
@@ -5756,7 +5772,7 @@
                             },
                             {
                                 "name": "probe_out12",
-                                "id": 144,
+                                "id": 145,
                                 "type": "DATA",
                                 "direction": "OUT",
                                 "isVector": true,
@@ -5825,7 +5841,7 @@
                 ],
                 "parent_nets": [
                     {
-                        "id": 15,
+                        "id": 174,
                         "name": "u_rx_pre_process/u_ad9361_phase_cal/out[1]",
                         "state_reg": [
                             {
@@ -5852,7 +5868,7 @@
                         ]
                     },
                     {
-                        "id": 16,
+                        "id": 175,
                         "name": "u_rx_pre_process/u_ad9361_phase_cal/out[0]",
                         "state_reg": [
                             {
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/project/project.sdk/system_top.hdf b/projects/dl814_k7/dl814_k7_cal_coarse/project/project.sdk/system_top.hdf
index a3245a0a..c18f8704 100644
Binary files a/projects/dl814_k7/dl814_k7_cal_coarse/project/project.sdk/system_top.hdf and b/projects/dl814_k7/dl814_k7_cal_coarse/project/project.sdk/system_top.hdf differ
diff --git a/projects/dl814_k7/dl814_k7_cal_coarse/rtl/system_top.v b/projects/dl814_k7/dl814_k7_cal_coarse/rtl/system_top.v
index 1bf2fb55..ffa0052f 100644
--- a/projects/dl814_k7/dl814_k7_cal_coarse/rtl/system_top.v
+++ b/projects/dl814_k7/dl814_k7_cal_coarse/rtl/system_top.v
@@ -457,7 +457,7 @@ ant_rf_ctrl u_ant_rf_ctrl
     .ant_data    (rf_data     ), // output          ant_data
     .ant_tr      (rf_tr       ), // output          ant_tr
     .ant_dary    (rf_dary     ), // output          ant_dary
-    .ant_dout    (rf_dout     ), // input           ant_dout
+    .ant_dout    (ant_dout1_d2), // input           ant_dout
 
     .rf_standby  (rf_standby  ), // output          rf_standby
     .rf_sw_pll   (rf_sw_pll   ), // output          rf_sw_pll
@@ -602,6 +602,8 @@ wire            rx_data_valid;
 wire    [29:0]  rx_data_i, rx_data_q;
 
 wire            hop_trigger;
+wire            hop_trigger_en;
+wire            rx_test_en;
 
 wire            hop_start_flag      ;
 // wire            accor_stream_valid  ;
@@ -619,7 +621,7 @@ always @(posedge sys_clk) begin
         rx_ch3_q <= 'b0;
         rx_ch4_q <= 'b0;
     end
-    else if (ad9361_cal_valid) begin
+    else if (rx_test_en && ad9361_cal_valid) begin
         rx_ch1_i <= rx_ch1_i_test;
         rx_ch2_i <= rx_ch2_i_test;
         rx_ch3_i <= rx_ch3_i_test;
@@ -877,14 +879,14 @@ vio_rf_rd u_vio_rf_rd (
 //     .probe_in5  (u_ant_rf_ctrl.Ant_RecvWord_last    )  // input wire [127 : 0] probe_in5
 // );
 
-ila_2x12x1024 u_ila_tx
+ila_2x12x131072 u_ila_tx
 (
     .clk    (sys_clk        ), // input wire clk
     .probe0 (tx_ch1_i       ), // input wire [11:0]  probe0
     .probe1 (tx_ch1_q       )  // input wire [11:0]  probe1
 );
 
-ila_8x12_2x30_8192 u_ila_rx
+ila_8x12_2x30_131072 u_ila_rx
 (
     .clk    (sys_clk                        ), // input wire clk
     .probe0 (u_rx_pre_process.rx_cal_ch1_i  ), // input wire [11:0]  probe0
@@ -957,7 +959,8 @@ vio_manual_ctrl u_vio_manual_ctrl
     .probe_out1 (sweep_on           ), // output wire [0 : 0] probe_out1
     .probe_out2 (freq_set[31:0]     ), // output wire [31 : 0] probe_out2
     .probe_out3 (iq_sel[1:0]        ), // output wire [1 : 0] probe_out3
-    .probe_out4 (bb_rshift[3:0]     )  // output wire [3 : 0] probe_out4
+    .probe_out4 (bb_rshift[3:0]     ), // output wire [3 : 0] probe_out4
+    .probe_out5 (rx_test_en         )  // output wire [0 : 0] probe_out5
 );
 
 vio_hop u_vio_hop